drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/aer.h>
  16 #include <linux/async.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/blk-mq.h>
  19 #include <linux/blk-mq-pci.h>
  20 #include <linux/dmi.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24 #include <linux/mm.h>
  25 #include <linux/module.h>
  26 #include <linux/mutex.h>
  27 #include <linux/once.h>
  28 #include <linux/pci.h>
  29 #include <linux/t10-pi.h>
  30 #include <linux/types.h>
  31 #include <linux/io-64-nonatomic-lo-hi.h>
  32 #include <linux/sed-opal.h>
  33
  34 #include "nvme.h"
  35
  36 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  37 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  38
  39 #define SGES_PER_PAGE   (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
  40
  41 /*
  42  * These can be higher, but we need to ensure that any command doesn't
  43  * require an sg allocation that needs more than a page of data.
  44  */
  45 #define NVME_MAX_KB_SZ  4096
  46 #define NVME_MAX_SEGS   127
  47
  48 static int use_threaded_interrupts;
  49 module_param(use_threaded_interrupts, int, 0);
  50
  51 static bool use_cmb_sqes = true;
  52 module_param(use_cmb_sqes, bool, 0444);
  53 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  54
  55 static unsigned int max_host_mem_size_mb = 128;
  56 module_param(max_host_mem_size_mb, uint, 0444);
  57 MODULE_PARM_DESC(max_host_mem_size_mb,
  58         "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
  59
  60 static unsigned int sgl_threshold = SZ_32K;
  61 module_param(sgl_threshold, uint, 0644);
  62 MODULE_PARM_DESC(sgl_threshold,
  63                 "Use SGLs when average request segment size is larger or equal to "
  64                 "this size. Use 0 to disable SGLs.");
  65
  66 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
  67 static const struct kernel_param_ops io_queue_depth_ops = {
  68         .set = io_queue_depth_set,
  69         .get = param_get_int,
  70 };
  71
  72 static int io_queue_depth = 1024;
  73 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
  74 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
  75
  76 struct nvme_dev;
  77 struct nvme_queue;
  78
  79 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  80
  81 /*
  82  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  83  */
  84 struct nvme_dev {
  85         struct nvme_queue *queues;
  86         struct blk_mq_tag_set tagset;
  87         struct blk_mq_tag_set admin_tagset;
  88         u32 __iomem *dbs;
  89         struct device *dev;
  90         struct dma_pool *prp_page_pool;
  91         struct dma_pool *prp_small_pool;
  92         unsigned online_queues;
  93         unsigned max_qid;
  94         unsigned int num_vecs;
  95         int q_depth;
  96         u32 db_stride;
  97         void __iomem *bar;
  98         unsigned long bar_mapped_size;
  99         struct work_struct remove_work;
 100         struct mutex shutdown_lock;
 101         bool subsystem;
 102         void __iomem *cmb;
 103         pci_bus_addr_t cmb_bus_addr;
 104         u64 cmb_size;
 105         u32 cmbsz;
 106         u32 cmbloc;
 107         struct nvme_ctrl ctrl;
 108         struct completion ioq_wait;
 109
 110         mempool_t *iod_mempool;
 111
 112         /* shadow doorbell buffer support: */
 113         u32 *dbbuf_dbs;
 114         dma_addr_t dbbuf_dbs_dma_addr;
 115         u32 *dbbuf_eis;
 116         dma_addr_t dbbuf_eis_dma_addr;
 117
 118         /* host memory buffer support: */
 119         u64 host_mem_size;
 120         u32 nr_host_mem_descs;
 121         dma_addr_t host_mem_descs_dma;
 122         struct nvme_host_mem_buf_desc *host_mem_descs;
 123         void **host_mem_desc_bufs;
 124 };
 125
 126 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
 127 {
 128         int n = 0, ret;
 129
 130         ret = kstrtoint(val, 10, &n);
 131         if (ret != 0 || n < 2)
 132                 return -EINVAL;
 133
 134         return param_set_int(val, kp);
 135 }
 136
 137 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
 138 {
 139         return qid * 2 * stride;
 140 }
 141
 142 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
 143 {
 144         return (qid * 2 + 1) * stride;
 145 }
 146
 147 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 148 {
 149         return container_of(ctrl, struct nvme_dev, ctrl);
 150 }
 151
 152 /*
 153  * An NVM Express queue.  Each device has at least two (one for admin
 154  * commands and one for I/O commands).
 155  */
 156 struct nvme_queue {
 157         struct device *q_dmadev;
 158         struct nvme_dev *dev;
 159         spinlock_t sq_lock;
 160         struct nvme_command *sq_cmds;
 161         struct nvme_command __iomem *sq_cmds_io;
 162         spinlock_t cq_lock ____cacheline_aligned_in_smp;
 163         volatile struct nvme_completion *cqes;
 164         struct blk_mq_tags **tags;
 165         dma_addr_t sq_dma_addr;
 166         dma_addr_t cq_dma_addr;
 167         u32 __iomem *q_db;
 168         u16 q_depth;
 169         s16 cq_vector;
 170         u16 sq_tail;
 171         u16 cq_head;
 172         u16 last_cq_head;
 173         u16 qid;
 174         u8 cq_phase;
 175         u32 *dbbuf_sq_db;
 176         u32 *dbbuf_cq_db;
 177         u32 *dbbuf_sq_ei;
 178         u32 *dbbuf_cq_ei;
 179 };
 180
 181 /*
 182  * The nvme_iod describes the data in an I/O, including the list of PRP
 183  * entries.  You can't see it in this data structure because C doesn't let
 184  * me express that.  Use nvme_init_iod to ensure there's enough space
 185  * allocated to store the PRP list.
 186  */
 187 struct nvme_iod {
 188         struct nvme_request req;
 189         struct nvme_queue *nvmeq;
 190         bool use_sgl;
 191         int aborted;
 192         int npages;             /* In the PRP list. 0 means small pool in use */
 193         int nents;              /* Used in scatterlist */
 194         int length;             /* Of data, in bytes */
 195         dma_addr_t first_dma;
 196         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 197         struct scatterlist *sg;
 198         struct scatterlist inline_sg[0];
 199 };
 200
 201 /*
 202  * Check we didin't inadvertently grow the command struct
 203  */
 204 static inline void _nvme_check_size(void)
 205 {
 206         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 207         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 208         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 209         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 210         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 211         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 212         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 213         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 214         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
 215         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
 216         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 217         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 218         BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
 219 }
 220
 221 static inline unsigned int nvme_dbbuf_size(u32 stride)
 222 {
 223         return ((num_possible_cpus() + 1) * 8 * stride);
 224 }
 225
 226 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
 227 {
 228         unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
 229
 230         if (dev->dbbuf_dbs)
 231                 return 0;
 232
 233         dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
 234                                             &dev->dbbuf_dbs_dma_addr,
 235                                             GFP_KERNEL);
 236         if (!dev->dbbuf_dbs)
 237                 return -ENOMEM;
 238         dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
 239                                             &dev->dbbuf_eis_dma_addr,
 240                                             GFP_KERNEL);
 241         if (!dev->dbbuf_eis) {
 242                 dma_free_coherent(dev->dev, mem_size,
 243                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 244                 dev->dbbuf_dbs = NULL;
 245                 return -ENOMEM;
 246         }
 247
 248         return 0;
 249 }
 250
 251 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
 252 {
 253         unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
 254
 255         if (dev->dbbuf_dbs) {
 256                 dma_free_coherent(dev->dev, mem_size,
 257                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 258                 dev->dbbuf_dbs = NULL;
 259         }
 260         if (dev->dbbuf_eis) {
 261                 dma_free_coherent(dev->dev, mem_size,
 262                                   dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
 263                 dev->dbbuf_eis = NULL;
 264         }
 265 }
 266
 267 static void nvme_dbbuf_init(struct nvme_dev *dev,
 268                             struct nvme_queue *nvmeq, int qid)
 269 {
 270         if (!dev->dbbuf_dbs || !qid)
 271                 return;
 272
 273         nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
 274         nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
 275         nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
 276         nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
 277 }
 278
 279 static void nvme_dbbuf_set(struct nvme_dev *dev)
 280 {
 281         struct nvme_command c;
 282
 283         if (!dev->dbbuf_dbs)
 284                 return;
 285
 286         memset(&c, 0, sizeof(c));
 287         c.dbbuf.opcode = nvme_admin_dbbuf;
 288         c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
 289         c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
 290
 291         if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
 292                 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
 293                 /* Free memory and continue on */
 294                 nvme_dbbuf_dma_free(dev);
 295         }
 296 }
 297
 298 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
 299 {
 300         return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
 301 }
 302
 303 /* Update dbbuf and return true if an MMIO is required */
 304 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
 305                                               volatile u32 *dbbuf_ei)
 306 {
 307         if (dbbuf_db) {
 308                 u16 old_value;
 309
 310                 /*
 311                  * Ensure that the queue is written before updating
 312                  * the doorbell in memory
 313                  */
 314                 wmb();
 315
 316                 old_value = *dbbuf_db;
 317                 *dbbuf_db = value;
 318
 319                 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
 320                         return false;
 321         }
 322
 323         return true;
 324 }
 325
 326 /*
 327  * Max size of iod being embedded in the request payload
 328  */
 329 #define NVME_INT_PAGES          2
 330 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 331
 332 /*
 333  * Will slightly overestimate the number of pages needed.  This is OK
 334  * as it only leads to a small amount of wasted memory for the lifetime of
 335  * the I/O.
 336  */
 337 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 338 {
 339         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 340                                       dev->ctrl.page_size);
 341         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 342 }
 343
 344 /*
 345  * Calculates the number of pages needed for the SGL segments. For example a 4k
 346  * page can accommodate 256 SGL descriptors.
 347  */
 348 static int nvme_pci_npages_sgl(unsigned int num_seg)
 349 {
 350         return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
 351 }
 352
 353 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
 354                 unsigned int size, unsigned int nseg, bool use_sgl)
 355 {
 356         size_t alloc_size;
 357
 358         if (use_sgl)
 359                 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
 360         else
 361                 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
 362
 363         return alloc_size + sizeof(struct scatterlist) * nseg;
 364 }
 365
 366 static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
 367 {
 368         unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
 369                                     NVME_INT_BYTES(dev), NVME_INT_PAGES,
 370                                     use_sgl);
 371
 372         return sizeof(struct nvme_iod) + alloc_size;
 373 }
 374
 375 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 376                                 unsigned int hctx_idx)
 377 {
 378         struct nvme_dev *dev = data;
 379         struct nvme_queue *nvmeq = &dev->queues[0];
 380
 381         WARN_ON(hctx_idx != 0);
 382         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 383         WARN_ON(nvmeq->tags);
 384
 385         hctx->driver_data = nvmeq;
 386         nvmeq->tags = &dev->admin_tagset.tags[0];
 387         return 0;
 388 }
 389
 390 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 391 {
 392         struct nvme_queue *nvmeq = hctx->driver_data;
 393
 394         nvmeq->tags = NULL;
 395 }
 396
 397 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 398                           unsigned int hctx_idx)
 399 {
 400         struct nvme_dev *dev = data;
 401         struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
 402
 403         if (!nvmeq->tags)
 404                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 405
 406         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 407         hctx->driver_data = nvmeq;
 408         return 0;
 409 }
 410
 411 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
 412                 unsigned int hctx_idx, unsigned int numa_node)
 413 {
 414         struct nvme_dev *dev = set->driver_data;
 415         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 416         int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
 417         struct nvme_queue *nvmeq = &dev->queues[queue_idx];
 418
 419         BUG_ON(!nvmeq);
 420         iod->nvmeq = nvmeq;
 421         return 0;
 422 }
 423
 424 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 425 {
 426         struct nvme_dev *dev = set->driver_data;
 427
 428         return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev),
 429                         dev->num_vecs > 1 ? 1 /* admin queue */ : 0);
 430 }
 431
 432 /**
 433  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 434  * @nvmeq: The queue to use
 435  * @cmd: The command to send
 436  */
 437 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 438 {
 439         spin_lock(&nvmeq->sq_lock);
 440         if (nvmeq->sq_cmds_io)
 441                 memcpy_toio(&nvmeq->sq_cmds_io[nvmeq->sq_tail], cmd,
 442                                 sizeof(*cmd));
 443         else
 444                 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
 445
 446         if (++nvmeq->sq_tail == nvmeq->q_depth)
 447                 nvmeq->sq_tail = 0;
 448         if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
 449                         nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
 450                 writel(nvmeq->sq_tail, nvmeq->q_db);
 451         spin_unlock(&nvmeq->sq_lock);
 452 }
 453
 454 static void **nvme_pci_iod_list(struct request *req)
 455 {
 456         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 457         return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
 458 }
 459
 460 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
 461 {
 462         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 463         int nseg = blk_rq_nr_phys_segments(req);
 464         unsigned int avg_seg_size;
 465
 466         if (nseg == 0)
 467                 return false;
 468
 469         avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
 470
 471         if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
 472                 return false;
 473         if (!iod->nvmeq->qid)
 474                 return false;
 475         if (!sgl_threshold || avg_seg_size < sgl_threshold)
 476                 return false;
 477         return true;
 478 }
 479
 480 static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
 481 {
 482         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
 483         int nseg = blk_rq_nr_phys_segments(rq);
 484         unsigned int size = blk_rq_payload_bytes(rq);
 485
 486         iod->use_sgl = nvme_pci_use_sgls(dev, rq);
 487
 488         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
 489                 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
 490                 if (!iod->sg)
 491                         return BLK_STS_RESOURCE;
 492         } else {
 493                 iod->sg = iod->inline_sg;
 494         }
 495
 496         iod->aborted = 0;
 497         iod->npages = -1;
 498         iod->nents = 0;
 499         iod->length = size;
 500
 501         return BLK_STS_OK;
 502 }
 503
 504 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
 505 {
 506         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 507         const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
 508         dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
 509
 510         int i;
 511
 512         if (iod->npages == 0)
 513                 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
 514                         dma_addr);
 515
 516         for (i = 0; i < iod->npages; i++) {
 517                 void *addr = nvme_pci_iod_list(req)[i];
 518
 519                 if (iod->use_sgl) {
 520                         struct nvme_sgl_desc *sg_list = addr;
 521
 522                         next_dma_addr =
 523                             le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
 524                 } else {
 525                         __le64 *prp_list = addr;
 526
 527                         next_dma_addr = le64_to_cpu(prp_list[last_prp]);
 528                 }
 529
 530                 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
 531                 dma_addr = next_dma_addr;
 532         }
 533
 534         if (iod->sg != iod->inline_sg)
 535                 mempool_free(iod->sg, dev->iod_mempool);
 536 }
 537
 538 #ifdef CONFIG_BLK_DEV_INTEGRITY
 539 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 540 {
 541         if (be32_to_cpu(pi->ref_tag) == v)
 542                 pi->ref_tag = cpu_to_be32(p);
 543 }
 544
 545 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 546 {
 547         if (be32_to_cpu(pi->ref_tag) == p)
 548                 pi->ref_tag = cpu_to_be32(v);
 549 }
 550
 551 /**
 552  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 553  *
 554  * The virtual start sector is the one that was originally submitted by the
 555  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 556  * start sector may be different. Remap protection information to match the
 557  * physical LBA on writes, and back to the original seed on reads.
 558  *
 559  * Type 0 and 3 do not have a ref tag, so no remapping required.
 560  */
 561 static void nvme_dif_remap(struct request *req,
 562                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 563 {
 564         struct nvme_ns *ns = req->rq_disk->private_data;
 565         struct bio_integrity_payload *bip;
 566         struct t10_pi_tuple *pi;
 567         void *p, *pmap;
 568         u32 i, nlb, ts, phys, virt;
 569
 570         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 571                 return;
 572
 573         bip = bio_integrity(req->bio);
 574         if (!bip)
 575                 return;
 576
 577         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 578
 579         p = pmap;
 580         virt = bip_get_seed(bip);
 581         phys = nvme_block_nr(ns, blk_rq_pos(req));
 582         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 583         ts = ns->disk->queue->integrity.tuple_size;
 584
 585         for (i = 0; i < nlb; i++, virt++, phys++) {
 586                 pi = (struct t10_pi_tuple *)p;
 587                 dif_swap(phys, virt, pi);
 588                 p += ts;
 589         }
 590         kunmap_atomic(pmap);
 591 }
 592 #else /* CONFIG_BLK_DEV_INTEGRITY */
 593 static void nvme_dif_remap(struct request *req,
 594                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 595 {
 596 }
 597 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 598 {
 599 }
 600 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 601 {
 602 }
 603 #endif
 604
 605 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
 606 {
 607         int i;
 608         struct scatterlist *sg;
 609
 610         for_each_sg(sgl, sg, nents, i) {
 611                 dma_addr_t phys = sg_phys(sg);
 612                 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
 613                         "dma_address:%pad dma_length:%d\n",
 614                         i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
 615                         sg_dma_len(sg));
 616         }
 617 }
 618
 619 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
 620                 struct request *req, struct nvme_rw_command *cmnd)
 621 {
 622         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 623         struct dma_pool *pool;
 624         int length = blk_rq_payload_bytes(req);
 625         struct scatterlist *sg = iod->sg;
 626         int dma_len = sg_dma_len(sg);
 627         u64 dma_addr = sg_dma_address(sg);
 628         u32 page_size = dev->ctrl.page_size;
 629         int offset = dma_addr & (page_size - 1);
 630         __le64 *prp_list;
 631         void **list = nvme_pci_iod_list(req);
 632         dma_addr_t prp_dma;
 633         int nprps, i;
 634
 635         length -= (page_size - offset);
 636         if (length <= 0) {
 637                 iod->first_dma = 0;
 638                 goto done;
 639         }
 640
 641         dma_len -= (page_size - offset);
 642         if (dma_len) {
 643                 dma_addr += (page_size - offset);
 644         } else {
 645                 sg = sg_next(sg);
 646                 dma_addr = sg_dma_address(sg);
 647                 dma_len = sg_dma_len(sg);
 648         }
 649
 650         if (length <= page_size) {
 651                 iod->first_dma = dma_addr;
 652                 goto done;
 653         }
 654
 655         nprps = DIV_ROUND_UP(length, page_size);
 656         if (nprps <= (256 / 8)) {
 657                 pool = dev->prp_small_pool;
 658                 iod->npages = 0;
 659         } else {
 660                 pool = dev->prp_page_pool;
 661                 iod->npages = 1;
 662         }
 663
 664         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 665         if (!prp_list) {
 666                 iod->first_dma = dma_addr;
 667                 iod->npages = -1;
 668                 return BLK_STS_RESOURCE;
 669         }
 670         list[0] = prp_list;
 671         iod->first_dma = prp_dma;
 672         i = 0;
 673         for (;;) {
 674                 if (i == page_size >> 3) {
 675                         __le64 *old_prp_list = prp_list;
 676                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 677                         if (!prp_list)
 678                                 return BLK_STS_RESOURCE;
 679                         list[iod->npages++] = prp_list;
 680                         prp_list[0] = old_prp_list[i - 1];
 681                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 682                         i = 1;
 683                 }
 684                 prp_list[i++] = cpu_to_le64(dma_addr);
 685                 dma_len -= page_size;
 686                 dma_addr += page_size;
 687                 length -= page_size;
 688                 if (length <= 0)
 689                         break;
 690                 if (dma_len > 0)
 691                         continue;
 692                 if (unlikely(dma_len < 0))
 693                         goto bad_sgl;
 694                 sg = sg_next(sg);
 695                 dma_addr = sg_dma_address(sg);
 696                 dma_len = sg_dma_len(sg);
 697         }
 698
 699 done:
 700         cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 701         cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
 702
 703         return BLK_STS_OK;
 704
 705  bad_sgl:
 706         WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
 707                         "Invalid SGL for payload:%d nents:%d\n",
 708                         blk_rq_payload_bytes(req), iod->nents);
 709         return BLK_STS_IOERR;
 710 }
 711
 712 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
 713                 struct scatterlist *sg)
 714 {
 715         sge->addr = cpu_to_le64(sg_dma_address(sg));
 716         sge->length = cpu_to_le32(sg_dma_len(sg));
 717         sge->type = NVME_SGL_FMT_DATA_DESC << 4;
 718 }
 719
 720 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
 721                 dma_addr_t dma_addr, int entries)
 722 {
 723         sge->addr = cpu_to_le64(dma_addr);
 724         if (entries < SGES_PER_PAGE) {
 725                 sge->length = cpu_to_le32(entries * sizeof(*sge));
 726                 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
 727         } else {
 728                 sge->length = cpu_to_le32(PAGE_SIZE);
 729                 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
 730         }
 731 }
 732
 733 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
 734                 struct request *req, struct nvme_rw_command *cmd, int entries)
 735 {
 736         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 737         struct dma_pool *pool;
 738         struct nvme_sgl_desc *sg_list;
 739         struct scatterlist *sg = iod->sg;
 740         dma_addr_t sgl_dma;
 741         int i = 0;
 742
 743         /* setting the transfer type as SGL */
 744         cmd->flags = NVME_CMD_SGL_METABUF;
 745
 746         if (entries == 1) {
 747                 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
 748                 return BLK_STS_OK;
 749         }
 750
 751         if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
 752                 pool = dev->prp_small_pool;
 753                 iod->npages = 0;
 754         } else {
 755                 pool = dev->prp_page_pool;
 756                 iod->npages = 1;
 757         }
 758
 759         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 760         if (!sg_list) {
 761                 iod->npages = -1;
 762                 return BLK_STS_RESOURCE;
 763         }
 764
 765         nvme_pci_iod_list(req)[0] = sg_list;
 766         iod->first_dma = sgl_dma;
 767
 768         nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
 769
 770         do {
 771                 if (i == SGES_PER_PAGE) {
 772                         struct nvme_sgl_desc *old_sg_desc = sg_list;
 773                         struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
 774
 775                         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 776                         if (!sg_list)
 777                                 return BLK_STS_RESOURCE;
 778
 779                         i = 0;
 780                         nvme_pci_iod_list(req)[iod->npages++] = sg_list;
 781                         sg_list[i++] = *link;
 782                         nvme_pci_sgl_set_seg(link, sgl_dma, entries);
 783                 }
 784
 785                 nvme_pci_sgl_set_data(&sg_list[i++], sg);
 786                 sg = sg_next(sg);
 787         } while (--entries > 0);
 788
 789         return BLK_STS_OK;
 790 }
 791
 792 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
 793                 struct nvme_command *cmnd)
 794 {
 795         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 796         struct request_queue *q = req->q;
 797         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 798                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 799         blk_status_t ret = BLK_STS_IOERR;
 800         int nr_mapped;
 801
 802         sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
 803         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 804         if (!iod->nents)
 805                 goto out;
 806
 807         ret = BLK_STS_RESOURCE;
 808         nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
 809                         DMA_ATTR_NO_WARN);
 810         if (!nr_mapped)
 811                 goto out;
 812
 813         if (iod->use_sgl)
 814                 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
 815         else
 816                 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
 817
 818         if (ret != BLK_STS_OK)
 819                 goto out_unmap;
 820
 821         ret = BLK_STS_IOERR;
 822         if (blk_integrity_rq(req)) {
 823                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 824                         goto out_unmap;
 825
 826                 sg_init_table(&iod->meta_sg, 1);
 827                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 828                         goto out_unmap;
 829
 830                 if (req_op(req) == REQ_OP_WRITE)
 831                         nvme_dif_remap(req, nvme_dif_prep);
 832
 833                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 834                         goto out_unmap;
 835         }
 836
 837         if (blk_integrity_rq(req))
 838                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 839         return BLK_STS_OK;
 840
 841 out_unmap:
 842         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 843 out:
 844         return ret;
 845 }
 846
 847 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 848 {
 849         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 850         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 851                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 852
 853         if (iod->nents) {
 854                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 855                 if (blk_integrity_rq(req)) {
 856                         if (req_op(req) == REQ_OP_READ)
 857                                 nvme_dif_remap(req, nvme_dif_complete);
 858                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 859                 }
 860         }
 861
 862         nvme_cleanup_cmd(req);
 863         nvme_free_iod(dev, req);
 864 }
 865
 866 /*
 867  * NOTE: ns is NULL when called on the admin queue.
 868  */
 869 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 870                          const struct blk_mq_queue_data *bd)
 871 {
 872         struct nvme_ns *ns = hctx->queue->queuedata;
 873         struct nvme_queue *nvmeq = hctx->driver_data;
 874         struct nvme_dev *dev = nvmeq->dev;
 875         struct request *req = bd->rq;
 876         struct nvme_command cmnd;
 877         blk_status_t ret;
 878
 879         /*
 880          * We should not need to do this, but we're still using this to
 881          * ensure we can drain requests on a dying queue.
 882          */
 883         if (unlikely(nvmeq->cq_vector < 0))
 884                 return BLK_STS_IOERR;
 885
 886         ret = nvme_setup_cmd(ns, req, &cmnd);
 887         if (ret)
 888                 return ret;
 889
 890         ret = nvme_init_iod(req, dev);
 891         if (ret)
 892                 goto out_free_cmd;
 893
 894         if (blk_rq_nr_phys_segments(req)) {
 895                 ret = nvme_map_data(dev, req, &cmnd);
 896                 if (ret)
 897                         goto out_cleanup_iod;
 898         }
 899
 900         blk_mq_start_request(req);
 901         nvme_submit_cmd(nvmeq, &cmnd);
 902         return BLK_STS_OK;
 903 out_cleanup_iod:
 904         nvme_free_iod(dev, req);
 905 out_free_cmd:
 906         nvme_cleanup_cmd(req);
 907         return ret;
 908 }
 909
 910 static void nvme_pci_complete_rq(struct request *req)
 911 {
 912         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 913
 914         nvme_unmap_data(iod->nvmeq->dev, req);
 915         nvme_complete_rq(req);
 916 }
 917
 918 /* We read the CQE phase first to check if the rest of the entry is valid */
 919 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
 920 {
 921         return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
 922                         nvmeq->cq_phase;
 923 }
 924
 925 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
 926 {
 927         u16 head = nvmeq->cq_head;
 928
 929         if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
 930                                               nvmeq->dbbuf_cq_ei))
 931                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 932 }
 933
 934 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
 935 {
 936         volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
 937         struct request *req;
 938
 939         if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
 940                 dev_warn(nvmeq->dev->ctrl.device,
 941                         "invalid id %d completed on queue %d\n",
 942                         cqe->command_id, le16_to_cpu(cqe->sq_id));
 943                 return;
 944         }
 945
 946         /*
 947          * AEN requests are special as they don't time out and can
 948          * survive any kind of queue freeze and often don't respond to
 949          * aborts.  We don't even bother to allocate a struct request
 950          * for them but rather special case them here.
 951          */
 952         if (unlikely(nvmeq->qid == 0 &&
 953                         cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
 954                 nvme_complete_async_event(&nvmeq->dev->ctrl,
 955                                 cqe->status, &cqe->result);
 956                 return;
 957         }
 958
 959         req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
 960         nvme_end_request(req, cqe->status, cqe->result);
 961 }
 962
 963 static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
 964 {
 965         while (start != end) {
 966                 nvme_handle_cqe(nvmeq, start);
 967                 if (++start == nvmeq->q_depth)
 968                         start = 0;
 969         }
 970 }
 971
 972 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
 973 {
 974         if (++nvmeq->cq_head == nvmeq->q_depth) {
 975                 nvmeq->cq_head = 0;
 976                 nvmeq->cq_phase = !nvmeq->cq_phase;
 977         }
 978 }
 979
 980 static inline bool nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
 981                 u16 *end, int tag)
 982 {
 983         bool found = false;
 984
 985         *start = nvmeq->cq_head;
 986         while (!found && nvme_cqe_pending(nvmeq)) {
 987                 if (nvmeq->cqes[nvmeq->cq_head].command_id == tag)
 988                         found = true;
 989                 nvme_update_cq_head(nvmeq);
 990         }
 991         *end = nvmeq->cq_head;
 992
 993         if (*start != *end)
 994                 nvme_ring_cq_doorbell(nvmeq);
 995         return found;
 996 }
 997
 998 static irqreturn_t nvme_irq(int irq, void *data)
 999 {
1000         struct nvme_queue *nvmeq = data;
1001         irqreturn_t ret = IRQ_NONE;
1002         u16 start, end;
1003
1004         spin_lock(&nvmeq->cq_lock);
1005         if (nvmeq->cq_head != nvmeq->last_cq_head)
1006                 ret = IRQ_HANDLED;
1007         nvme_process_cq(nvmeq, &start, &end, -1);
1008         nvmeq->last_cq_head = nvmeq->cq_head;
1009         spin_unlock(&nvmeq->cq_lock);
1010
1011         if (start != end) {
1012                 nvme_complete_cqes(nvmeq, start, end);
1013                 return IRQ_HANDLED;
1014         }
1015
1016         return ret;
1017 }
1018
1019 static irqreturn_t nvme_irq_check(int irq, void *data)
1020 {
1021         struct nvme_queue *nvmeq = data;
1022         if (nvme_cqe_pending(nvmeq))
1023                 return IRQ_WAKE_THREAD;
1024         return IRQ_NONE;
1025 }
1026
1027 static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
1028 {
1029         u16 start, end;
1030         bool found;
1031
1032         if (!nvme_cqe_pending(nvmeq))
1033                 return 0;
1034
1035         spin_lock_irq(&nvmeq->cq_lock);
1036         found = nvme_process_cq(nvmeq, &start, &end, tag);
1037         spin_unlock_irq(&nvmeq->cq_lock);
1038
1039         nvme_complete_cqes(nvmeq, start, end);
1040         return found;
1041 }
1042
1043 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
1044 {
1045         struct nvme_queue *nvmeq = hctx->driver_data;
1046
1047         return __nvme_poll(nvmeq, tag);
1048 }
1049
1050 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1051 {
1052         struct nvme_dev *dev = to_nvme_dev(ctrl);
1053         struct nvme_queue *nvmeq = &dev->queues[0];
1054         struct nvme_command c;
1055
1056         memset(&c, 0, sizeof(c));
1057         c.common.opcode = nvme_admin_async_event;
1058         c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1059         nvme_submit_cmd(nvmeq, &c);
1060 }
1061
1062 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1063 {
1064         struct nvme_command c;
1065
1066         memset(&c, 0, sizeof(c));
1067         c.delete_queue.opcode = opcode;
1068         c.delete_queue.qid = cpu_to_le16(id);
1069
1070         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1071 }
1072
1073 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1074                 struct nvme_queue *nvmeq, s16 vector)
1075 {
1076         struct nvme_command c;
1077         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1078
1079         /*
1080          * Note: we (ab)use the fact that the prp fields survive if no data
1081          * is attached to the request.
1082          */
1083         memset(&c, 0, sizeof(c));
1084         c.create_cq.opcode = nvme_admin_create_cq;
1085         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1086         c.create_cq.cqid = cpu_to_le16(qid);
1087         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1088         c.create_cq.cq_flags = cpu_to_le16(flags);
1089         c.create_cq.irq_vector = cpu_to_le16(vector);
1090
1091         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1092 }
1093
1094 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1095                                                 struct nvme_queue *nvmeq)
1096 {
1097         struct nvme_ctrl *ctrl = &dev->ctrl;
1098         struct nvme_command c;
1099         int flags = NVME_QUEUE_PHYS_CONTIG;
1100
1101         /*
1102          * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1103          * set. Since URGENT priority is zeroes, it makes all queues
1104          * URGENT.
1105          */
1106         if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1107                 flags |= NVME_SQ_PRIO_MEDIUM;
1108
1109         /*
1110          * Note: we (ab)use the fact that the prp fields survive if no data
1111          * is attached to the request.
1112          */
1113         memset(&c, 0, sizeof(c));
1114         c.create_sq.opcode = nvme_admin_create_sq;
1115         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1116         c.create_sq.sqid = cpu_to_le16(qid);
1117         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1118         c.create_sq.sq_flags = cpu_to_le16(flags);
1119         c.create_sq.cqid = cpu_to_le16(qid);
1120
1121         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1122 }
1123
1124 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1125 {
1126         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1127 }
1128
1129 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1130 {
1131         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1132 }
1133
1134 static void abort_endio(struct request *req, blk_status_t error)
1135 {
1136         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1137         struct nvme_queue *nvmeq = iod->nvmeq;
1138
1139         dev_warn(nvmeq->dev->ctrl.device,
1140                  "Abort status: 0x%x", nvme_req(req)->status);
1141         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1142         blk_mq_free_request(req);
1143 }
1144
1145 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1146 {
1147
1148         /* If true, indicates loss of adapter communication, possibly by a
1149          * NVMe Subsystem reset.
1150          */
1151         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1152
1153         /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1154         switch (dev->ctrl.state) {
1155         case NVME_CTRL_RESETTING:
1156         case NVME_CTRL_CONNECTING:
1157                 return false;
1158         default:
1159                 break;
1160         }
1161
1162         /* We shouldn't reset unless the controller is on fatal error state
1163          * _or_ if we lost the communication with it.
1164          */
1165         if (!(csts & NVME_CSTS_CFS) && !nssro)
1166                 return false;
1167
1168         return true;
1169 }
1170
1171 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1172 {
1173         /* Read a config register to help see what died. */
1174         u16 pci_status;
1175         int result;
1176
1177         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1178                                       &pci_status);
1179         if (result == PCIBIOS_SUCCESSFUL)
1180                 dev_warn(dev->ctrl.device,
1181                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1182                          csts, pci_status);
1183         else
1184                 dev_warn(dev->ctrl.device,
1185                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1186                          csts, result);
1187 }
1188
1189 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1190 {
1191         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1192         struct nvme_queue *nvmeq = iod->nvmeq;
1193         struct nvme_dev *dev = nvmeq->dev;
1194         struct request *abort_req;
1195         struct nvme_command cmd;
1196         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1197
1198         /* If PCI error recovery process is happening, we cannot reset or
1199          * the recovery mechanism will surely fail.
1200          */
1201         mb();
1202         if (pci_channel_offline(to_pci_dev(dev->dev)))
1203                 return BLK_EH_RESET_TIMER;
1204
1205         /*
1206          * Reset immediately if the controller is failed
1207          */
1208         if (nvme_should_reset(dev, csts)) {
1209                 nvme_warn_reset(dev, csts);
1210                 nvme_dev_disable(dev, false);
1211                 nvme_reset_ctrl(&dev->ctrl);
1212                 return BLK_EH_DONE;
1213         }
1214
1215         /*
1216          * Did we miss an interrupt?
1217          */
1218         if (__nvme_poll(nvmeq, req->tag)) {
1219                 dev_warn(dev->ctrl.device,
1220                          "I/O %d QID %d timeout, completion polled\n",
1221                          req->tag, nvmeq->qid);
1222                 return BLK_EH_DONE;
1223         }
1224
1225         /*
1226          * Shutdown immediately if controller times out while starting. The
1227          * reset work will see the pci device disabled when it gets the forced
1228          * cancellation error. All outstanding requests are completed on
1229          * shutdown, so we return BLK_EH_DONE.
1230          */
1231         switch (dev->ctrl.state) {
1232         case NVME_CTRL_CONNECTING:
1233         case NVME_CTRL_RESETTING:
1234                 dev_warn_ratelimited(dev->ctrl.device,
1235                          "I/O %d QID %d timeout, disable controller\n",
1236                          req->tag, nvmeq->qid);
1237                 nvme_dev_disable(dev, false);
1238                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1239                 return BLK_EH_DONE;
1240         default:
1241                 break;
1242         }
1243
1244         /*
1245          * Shutdown the controller immediately and schedule a reset if the
1246          * command was already aborted once before and still hasn't been
1247          * returned to the driver, or if this is the admin queue.
1248          */
1249         if (!nvmeq->qid || iod->aborted) {
1250                 dev_warn(dev->ctrl.device,
1251                          "I/O %d QID %d timeout, reset controller\n",
1252                          req->tag, nvmeq->qid);
1253                 nvme_dev_disable(dev, false);
1254                 nvme_reset_ctrl(&dev->ctrl);
1255
1256                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1257                 return BLK_EH_DONE;
1258         }
1259
1260         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1261                 atomic_inc(&dev->ctrl.abort_limit);
1262                 return BLK_EH_RESET_TIMER;
1263         }
1264         iod->aborted = 1;
1265
1266         memset(&cmd, 0, sizeof(cmd));
1267         cmd.abort.opcode = nvme_admin_abort_cmd;
1268         cmd.abort.cid = req->tag;
1269         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1270
1271         dev_warn(nvmeq->dev->ctrl.device,
1272                 "I/O %d QID %d timeout, aborting\n",
1273                  req->tag, nvmeq->qid);
1274
1275         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1276                         BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1277         if (IS_ERR(abort_req)) {
1278                 atomic_inc(&dev->ctrl.abort_limit);
1279                 return BLK_EH_RESET_TIMER;
1280         }
1281
1282         abort_req->timeout = ADMIN_TIMEOUT;
1283         abort_req->end_io_data = NULL;
1284         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1285
1286         /*
1287          * The aborted req will be completed on receiving the abort req.
1288          * We enable the timer again. If hit twice, it'll cause a device reset,
1289          * as the device then is in a faulty state.
1290          */
1291         return BLK_EH_RESET_TIMER;
1292 }
1293
1294 static void nvme_free_queue(struct nvme_queue *nvmeq)
1295 {
1296         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1297                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1298         if (nvmeq->sq_cmds)
1299                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1300                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1301 }
1302
1303 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1304 {
1305         int i;
1306
1307         for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1308                 dev->ctrl.queue_count--;
1309                 nvme_free_queue(&dev->queues[i]);
1310         }
1311 }
1312
1313 /**
1314  * nvme_suspend_queue - put queue into suspended state
1315  * @nvmeq - queue to suspend
1316  */
1317 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1318 {
1319         int vector;
1320
1321         spin_lock_irq(&nvmeq->cq_lock);
1322         if (nvmeq->cq_vector == -1) {
1323                 spin_unlock_irq(&nvmeq->cq_lock);
1324                 return 1;
1325         }
1326         vector = nvmeq->cq_vector;
1327         nvmeq->dev->online_queues--;
1328         nvmeq->cq_vector = -1;
1329         spin_unlock_irq(&nvmeq->cq_lock);
1330
1331         /*
1332          * Ensure that nvme_queue_rq() sees it ->cq_vector == -1 without
1333          * having to grab the lock.
1334          */
1335         mb();
1336
1337         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1338                 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1339
1340         pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
1341
1342         return 0;
1343 }
1344
1345 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1346 {
1347         struct nvme_queue *nvmeq = &dev->queues[0];
1348         u16 start, end;
1349
1350         if (shutdown)
1351                 nvme_shutdown_ctrl(&dev->ctrl);
1352         else
1353                 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1354
1355         spin_lock_irq(&nvmeq->cq_lock);
1356         nvme_process_cq(nvmeq, &start, &end, -1);
1357         spin_unlock_irq(&nvmeq->cq_lock);
1358
1359         nvme_complete_cqes(nvmeq, start, end);
1360 }
1361
1362 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1363                                 int entry_size)
1364 {
1365         int q_depth = dev->q_depth;
1366         unsigned q_size_aligned = roundup(q_depth * entry_size,
1367                                           dev->ctrl.page_size);
1368
1369         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1370                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1371                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1372                 q_depth = div_u64(mem_per_q, entry_size);
1373
1374                 /*
1375                  * Ensure the reduced q_depth is above some threshold where it
1376                  * would be better to map queues in system memory with the
1377                  * original depth
1378                  */
1379                 if (q_depth < 64)
1380                         return -ENOMEM;
1381         }
1382
1383         return q_depth;
1384 }
1385
1386 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1387                                 int qid, int depth)
1388 {
1389         /* CMB SQEs will be mapped before creation */
1390         if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS))
1391                 return 0;
1392
1393         nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1394                                             &nvmeq->sq_dma_addr, GFP_KERNEL);
1395         if (!nvmeq->sq_cmds)
1396                 return -ENOMEM;
1397         return 0;
1398 }
1399
1400 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1401 {
1402         struct nvme_queue *nvmeq = &dev->queues[qid];
1403
1404         if (dev->ctrl.queue_count > qid)
1405                 return 0;
1406
1407         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1408                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1409         if (!nvmeq->cqes)
1410                 goto free_nvmeq;
1411
1412         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1413                 goto free_cqdma;
1414
1415         nvmeq->q_dmadev = dev->dev;
1416         nvmeq->dev = dev;
1417         spin_lock_init(&nvmeq->sq_lock);
1418         spin_lock_init(&nvmeq->cq_lock);
1419         nvmeq->cq_head = 0;
1420         nvmeq->cq_phase = 1;
1421         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1422         nvmeq->q_depth = depth;
1423         nvmeq->qid = qid;
1424         nvmeq->cq_vector = -1;
1425         dev->ctrl.queue_count++;
1426
1427         return 0;
1428
1429  free_cqdma:
1430         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1431                                                         nvmeq->cq_dma_addr);
1432  free_nvmeq:
1433         return -ENOMEM;
1434 }
1435
1436 static int queue_request_irq(struct nvme_queue *nvmeq)
1437 {
1438         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1439         int nr = nvmeq->dev->ctrl.instance;
1440
1441         if (use_threaded_interrupts) {
1442                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1443                                 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1444         } else {
1445                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1446                                 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1447         }
1448 }
1449
1450 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1451 {
1452         struct nvme_dev *dev = nvmeq->dev;
1453
1454         spin_lock_irq(&nvmeq->cq_lock);
1455         nvmeq->sq_tail = 0;
1456         nvmeq->cq_head = 0;
1457         nvmeq->cq_phase = 1;
1458         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1459         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1460         nvme_dbbuf_init(dev, nvmeq, qid);
1461         dev->online_queues++;
1462         spin_unlock_irq(&nvmeq->cq_lock);
1463 }
1464
1465 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1466 {
1467         struct nvme_dev *dev = nvmeq->dev;
1468         int result;
1469         s16 vector;
1470
1471         if (dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1472                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth),
1473                                                       dev->ctrl.page_size);
1474                 nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
1475                 nvmeq->sq_cmds_io = dev->cmb + offset;
1476         }
1477
1478         /*
1479          * A queue's vector matches the queue identifier unless the controller
1480          * has only one vector available.
1481          */
1482         vector = dev->num_vecs == 1 ? 0 : qid;
1483         result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1484         if (result)
1485                 return result;
1486
1487         result = adapter_alloc_sq(dev, qid, nvmeq);
1488         if (result < 0)
1489                 return result;
1490         else if (result)
1491                 goto release_cq;
1492
1493         /*
1494          * Set cq_vector after alloc cq/sq, otherwise nvme_suspend_queue will
1495          * invoke free_irq for it and cause a 'Trying to free already-free IRQ
1496          * xxx' warning if the create CQ/SQ command times out.
1497          */
1498         nvmeq->cq_vector = vector;
1499         nvme_init_queue(nvmeq, qid);
1500         result = queue_request_irq(nvmeq);
1501         if (result < 0)
1502                 goto release_sq;
1503
1504         return result;
1505
1506 release_sq:
1507         nvmeq->cq_vector = -1;
1508         dev->online_queues--;
1509         adapter_delete_sq(dev, qid);
1510 release_cq:
1511         adapter_delete_cq(dev, qid);
1512         return result;
1513 }
1514
1515 static const struct blk_mq_ops nvme_mq_admin_ops = {
1516         .queue_rq       = nvme_queue_rq,
1517         .complete       = nvme_pci_complete_rq,
1518         .init_hctx      = nvme_admin_init_hctx,
1519         .exit_hctx      = nvme_admin_exit_hctx,
1520         .init_request   = nvme_init_request,
1521         .timeout        = nvme_timeout,
1522 };
1523
1524 static const struct blk_mq_ops nvme_mq_ops = {
1525         .queue_rq       = nvme_queue_rq,
1526         .complete       = nvme_pci_complete_rq,
1527         .init_hctx      = nvme_init_hctx,
1528         .init_request   = nvme_init_request,
1529         .map_queues     = nvme_pci_map_queues,
1530         .timeout        = nvme_timeout,
1531         .poll           = nvme_poll,
1532 };
1533
1534 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1535 {
1536         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1537                 /*
1538                  * If the controller was reset during removal, it's possible
1539                  * user requests may be waiting on a stopped queue. Start the
1540                  * queue to flush these to completion.
1541                  */
1542                 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1543                 blk_cleanup_queue(dev->ctrl.admin_q);
1544                 blk_mq_free_tag_set(&dev->admin_tagset);
1545         }
1546 }
1547
1548 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1549 {
1550         if (!dev->ctrl.admin_q) {
1551                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1552                 dev->admin_tagset.nr_hw_queues = 1;
1553
1554                 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1555                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1556                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1557                 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
1558                 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1559                 dev->admin_tagset.driver_data = dev;
1560
1561                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1562                         return -ENOMEM;
1563                 dev->ctrl.admin_tagset = &dev->admin_tagset;
1564
1565                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1566                 if (IS_ERR(dev->ctrl.admin_q)) {
1567                         blk_mq_free_tag_set(&dev->admin_tagset);
1568                         return -ENOMEM;
1569                 }
1570                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1571                         nvme_dev_remove_admin(dev);
1572                         dev->ctrl.admin_q = NULL;
1573                         return -ENODEV;
1574                 }
1575         } else
1576                 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1577
1578         return 0;
1579 }
1580
1581 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1582 {
1583         return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1584 }
1585
1586 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1587 {
1588         struct pci_dev *pdev = to_pci_dev(dev->dev);
1589
1590         if (size <= dev->bar_mapped_size)
1591                 return 0;
1592         if (size > pci_resource_len(pdev, 0))
1593                 return -ENOMEM;
1594         if (dev->bar)
1595                 iounmap(dev->bar);
1596         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1597         if (!dev->bar) {
1598                 dev->bar_mapped_size = 0;
1599                 return -ENOMEM;
1600         }
1601         dev->bar_mapped_size = size;
1602         dev->dbs = dev->bar + NVME_REG_DBS;
1603
1604         return 0;
1605 }
1606
1607 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1608 {
1609         int result;
1610         u32 aqa;
1611         struct nvme_queue *nvmeq;
1612
1613         result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1614         if (result < 0)
1615                 return result;
1616
1617         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1618                                 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1619
1620         if (dev->subsystem &&
1621             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1622                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1623
1624         result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1625         if (result < 0)
1626                 return result;
1627
1628         result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1629         if (result)
1630                 return result;
1631
1632         nvmeq = &dev->queues[0];
1633         aqa = nvmeq->q_depth - 1;
1634         aqa |= aqa << 16;
1635
1636         writel(aqa, dev->bar + NVME_REG_AQA);
1637         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1638         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1639
1640         result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
1641         if (result)
1642                 return result;
1643
1644         nvmeq->cq_vector = 0;
1645         nvme_init_queue(nvmeq, 0);
1646         result = queue_request_irq(nvmeq);
1647         if (result) {
1648                 nvmeq->cq_vector = -1;
1649                 return result;
1650         }
1651
1652         return result;
1653 }
1654
1655 static int nvme_create_io_queues(struct nvme_dev *dev)
1656 {
1657         unsigned i, max;
1658         int ret = 0;
1659
1660         for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1661                 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1662                         ret = -ENOMEM;
1663                         break;
1664                 }
1665         }
1666
1667         max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1668         for (i = dev->online_queues; i <= max; i++) {
1669                 ret = nvme_create_queue(&dev->queues[i], i);
1670                 if (ret)
1671                         break;
1672         }
1673
1674         /*
1675          * Ignore failing Create SQ/CQ commands, we can continue with less
1676          * than the desired amount of queues, and even a controller without
1677          * I/O queues can still be used to issue admin commands.  This might
1678          * be useful to upgrade a buggy firmware for example.
1679          */
1680         return ret >= 0 ? 0 : ret;
1681 }
1682
1683 static ssize_t nvme_cmb_show(struct device *dev,
1684                              struct device_attribute *attr,
1685                              char *buf)
1686 {
1687         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1688
1689         return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1690                        ndev->cmbloc, ndev->cmbsz);
1691 }
1692 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1693
1694 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1695 {
1696         u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1697
1698         return 1ULL << (12 + 4 * szu);
1699 }
1700
1701 static u32 nvme_cmb_size(struct nvme_dev *dev)
1702 {
1703         return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1704 }
1705
1706 static void nvme_map_cmb(struct nvme_dev *dev)
1707 {
1708         u64 size, offset;
1709         resource_size_t bar_size;
1710         struct pci_dev *pdev = to_pci_dev(dev->dev);
1711         int bar;
1712
1713         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1714         if (!dev->cmbsz)
1715                 return;
1716         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1717
1718         if (!use_cmb_sqes)
1719                 return;
1720
1721         size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1722         offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1723         bar = NVME_CMB_BIR(dev->cmbloc);
1724         bar_size = pci_resource_len(pdev, bar);
1725
1726         if (offset > bar_size)
1727                 return;
1728
1729         /*
1730          * Controllers may support a CMB size larger than their BAR,
1731          * for example, due to being behind a bridge. Reduce the CMB to
1732          * the reported size of the BAR
1733          */
1734         if (size > bar_size - offset)
1735                 size = bar_size - offset;
1736
1737         dev->cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size);
1738         if (!dev->cmb)
1739                 return;
1740         dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset;
1741         dev->cmb_size = size;
1742
1743         if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1744                                     &dev_attr_cmb.attr, NULL))
1745                 dev_warn(dev->ctrl.device,
1746                          "failed to add sysfs attribute for CMB\n");
1747 }
1748
1749 static inline void nvme_release_cmb(struct nvme_dev *dev)
1750 {
1751         if (dev->cmb) {
1752                 iounmap(dev->cmb);
1753                 dev->cmb = NULL;
1754                 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1755                                              &dev_attr_cmb.attr, NULL);
1756                 dev->cmbsz = 0;
1757         }
1758 }
1759
1760 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1761 {
1762         u64 dma_addr = dev->host_mem_descs_dma;
1763         struct nvme_command c;
1764         int ret;
1765
1766         memset(&c, 0, sizeof(c));
1767         c.features.opcode       = nvme_admin_set_features;
1768         c.features.fid          = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1769         c.features.dword11      = cpu_to_le32(bits);
1770         c.features.dword12      = cpu_to_le32(dev->host_mem_size >>
1771                                               ilog2(dev->ctrl.page_size));
1772         c.features.dword13      = cpu_to_le32(lower_32_bits(dma_addr));
1773         c.features.dword14      = cpu_to_le32(upper_32_bits(dma_addr));
1774         c.features.dword15      = cpu_to_le32(dev->nr_host_mem_descs);
1775
1776         ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1777         if (ret) {
1778                 dev_warn(dev->ctrl.device,
1779                          "failed to set host mem (err %d, flags %#x).\n",
1780                          ret, bits);
1781         }
1782         return ret;
1783 }
1784
1785 static void nvme_free_host_mem(struct nvme_dev *dev)
1786 {
1787         int i;
1788
1789         for (i = 0; i < dev->nr_host_mem_descs; i++) {
1790                 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1791                 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1792
1793                 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1794                                 le64_to_cpu(desc->addr));
1795         }
1796
1797         kfree(dev->host_mem_desc_bufs);
1798         dev->host_mem_desc_bufs = NULL;
1799         dma_free_coherent(dev->dev,
1800                         dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1801                         dev->host_mem_descs, dev->host_mem_descs_dma);
1802         dev->host_mem_descs = NULL;
1803         dev->nr_host_mem_descs = 0;
1804 }
1805
1806 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1807                 u32 chunk_size)
1808 {
1809         struct nvme_host_mem_buf_desc *descs;
1810         u32 max_entries, len;
1811         dma_addr_t descs_dma;
1812         int i = 0;
1813         void **bufs;
1814         u64 size, tmp;
1815
1816         tmp = (preferred + chunk_size - 1);
1817         do_div(tmp, chunk_size);
1818         max_entries = tmp;
1819
1820         if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1821                 max_entries = dev->ctrl.hmmaxd;
1822
1823         descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1824                         &descs_dma, GFP_KERNEL);
1825         if (!descs)
1826                 goto out;
1827
1828         bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1829         if (!bufs)
1830                 goto out_free_descs;
1831
1832         for (size = 0; size < preferred && i < max_entries; size += len) {
1833                 dma_addr_t dma_addr;
1834
1835                 len = min_t(u64, chunk_size, preferred - size);
1836                 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1837                                 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1838                 if (!bufs[i])
1839                         break;
1840
1841                 descs[i].addr = cpu_to_le64(dma_addr);
1842                 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1843                 i++;
1844         }
1845
1846         if (!size)
1847                 goto out_free_bufs;
1848
1849         dev->nr_host_mem_descs = i;
1850         dev->host_mem_size = size;
1851         dev->host_mem_descs = descs;
1852         dev->host_mem_descs_dma = descs_dma;
1853         dev->host_mem_desc_bufs = bufs;
1854         return 0;
1855
1856 out_free_bufs:
1857         while (--i >= 0) {
1858                 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1859
1860                 dma_free_coherent(dev->dev, size, bufs[i],
1861                                 le64_to_cpu(descs[i].addr));
1862         }
1863
1864         kfree(bufs);
1865 out_free_descs:
1866         dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1867                         descs_dma);
1868 out:
1869         dev->host_mem_descs = NULL;
1870         return -ENOMEM;
1871 }
1872
1873 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1874 {
1875         u32 chunk_size;
1876
1877         /* start big and work our way down */
1878         for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1879              chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1880              chunk_size /= 2) {
1881                 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1882                         if (!min || dev->host_mem_size >= min)
1883                                 return 0;
1884                         nvme_free_host_mem(dev);
1885                 }
1886         }
1887
1888         return -ENOMEM;
1889 }
1890
1891 static int nvme_setup_host_mem(struct nvme_dev *dev)
1892 {
1893         u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1894         u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1895         u64 min = (u64)dev->ctrl.hmmin * 4096;
1896         u32 enable_bits = NVME_HOST_MEM_ENABLE;
1897         int ret;
1898
1899         preferred = min(preferred, max);
1900         if (min > max) {
1901                 dev_warn(dev->ctrl.device,
1902                         "min host memory (%lld MiB) above limit (%d MiB).\n",
1903                         min >> ilog2(SZ_1M), max_host_mem_size_mb);
1904                 nvme_free_host_mem(dev);
1905                 return 0;
1906         }
1907
1908         /*
1909          * If we already have a buffer allocated check if we can reuse it.
1910          */
1911         if (dev->host_mem_descs) {
1912                 if (dev->host_mem_size >= min)
1913                         enable_bits |= NVME_HOST_MEM_RETURN;
1914                 else
1915                         nvme_free_host_mem(dev);
1916         }
1917
1918         if (!dev->host_mem_descs) {
1919                 if (nvme_alloc_host_mem(dev, min, preferred)) {
1920                         dev_warn(dev->ctrl.device,
1921                                 "failed to allocate host memory buffer.\n");
1922                         return 0; /* controller must work without HMB */
1923                 }
1924
1925                 dev_info(dev->ctrl.device,
1926                         "allocated %lld MiB host memory buffer.\n",
1927                         dev->host_mem_size >> ilog2(SZ_1M));
1928         }
1929
1930         ret = nvme_set_host_mem(dev, enable_bits);
1931         if (ret)
1932                 nvme_free_host_mem(dev);
1933         return ret;
1934 }
1935
1936 static int nvme_setup_io_queues(struct nvme_dev *dev)
1937 {
1938         struct nvme_queue *adminq = &dev->queues[0];
1939         struct pci_dev *pdev = to_pci_dev(dev->dev);
1940         int result, nr_io_queues;
1941         unsigned long size;
1942
1943         struct irq_affinity affd = {
1944                 .pre_vectors = 1
1945         };
1946
1947         nr_io_queues = num_possible_cpus();
1948         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1949         if (result < 0)
1950                 return result;
1951
1952         if (nr_io_queues == 0)
1953                 return 0;
1954
1955         if (dev->cmb && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1956                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1957                                 sizeof(struct nvme_command));
1958                 if (result > 0)
1959                         dev->q_depth = result;
1960                 else
1961                         nvme_release_cmb(dev);
1962         }
1963
1964         do {
1965                 size = db_bar_size(dev, nr_io_queues);
1966                 result = nvme_remap_bar(dev, size);
1967                 if (!result)
1968                         break;
1969                 if (!--nr_io_queues)
1970                         return -ENOMEM;
1971         } while (1);
1972         adminq->q_db = dev->dbs;
1973
1974         /* Deregister the admin queue's interrupt */
1975         pci_free_irq(pdev, 0, adminq);
1976
1977         /*
1978          * If we enable msix early due to not intx, disable it again before
1979          * setting up the full range we need.
1980          */
1981         pci_free_irq_vectors(pdev);
1982         result = pci_alloc_irq_vectors_affinity(pdev, 1, nr_io_queues + 1,
1983                         PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
1984         if (result <= 0)
1985                 return -EIO;
1986         dev->num_vecs = result;
1987         dev->max_qid = max(result - 1, 1);
1988
1989         /*
1990          * Should investigate if there's a performance win from allocating
1991          * more queues than interrupt vectors; it might allow the submission
1992          * path to scale better, even if the receive path is limited by the
1993          * number of interrupts.
1994          */
1995
1996         result = queue_request_irq(adminq);
1997         if (result) {
1998                 adminq->cq_vector = -1;
1999                 return result;
2000         }
2001         return nvme_create_io_queues(dev);
2002 }
2003
2004 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2005 {
2006         struct nvme_queue *nvmeq = req->end_io_data;
2007
2008         blk_mq_free_request(req);
2009         complete(&nvmeq->dev->ioq_wait);
2010 }
2011
2012 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2013 {
2014         struct nvme_queue *nvmeq = req->end_io_data;
2015         u16 start, end;
2016
2017         if (!error) {
2018                 unsigned long flags;
2019
2020                 spin_lock_irqsave(&nvmeq->cq_lock, flags);
2021                 nvme_process_cq(nvmeq, &start, &end, -1);
2022                 spin_unlock_irqrestore(&nvmeq->cq_lock, flags);
2023
2024                 nvme_complete_cqes(nvmeq, start, end);
2025         }
2026
2027         nvme_del_queue_end(req, error);
2028 }
2029
2030 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2031 {
2032         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2033         struct request *req;
2034         struct nvme_command cmd;
2035
2036         memset(&cmd, 0, sizeof(cmd));
2037         cmd.delete_queue.opcode = opcode;
2038         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2039
2040         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
2041         if (IS_ERR(req))
2042                 return PTR_ERR(req);
2043
2044         req->timeout = ADMIN_TIMEOUT;
2045         req->end_io_data = nvmeq;
2046
2047         blk_execute_rq_nowait(q, NULL, req, false,
2048                         opcode == nvme_admin_delete_cq ?
2049                                 nvme_del_cq_end : nvme_del_queue_end);
2050         return 0;
2051 }
2052
2053 static void nvme_disable_io_queues(struct nvme_dev *dev)
2054 {
2055         int pass, queues = dev->online_queues - 1;
2056         unsigned long timeout;
2057         u8 opcode = nvme_admin_delete_sq;
2058
2059         for (pass = 0; pass < 2; pass++) {
2060                 int sent = 0, i = queues;
2061
2062                 reinit_completion(&dev->ioq_wait);
2063  retry:
2064                 timeout = ADMIN_TIMEOUT;
2065                 for (; i > 0; i--, sent++)
2066                         if (nvme_delete_queue(&dev->queues[i], opcode))
2067                                 break;
2068
2069                 while (sent--) {
2070                         timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
2071                         if (timeout == 0)
2072                                 return;
2073                         if (i)
2074                                 goto retry;
2075                 }
2076                 opcode = nvme_admin_delete_cq;
2077         }
2078 }
2079
2080 /*
2081  * return error value only when tagset allocation failed
2082  */
2083 static int nvme_dev_add(struct nvme_dev *dev)
2084 {
2085         int ret;
2086
2087         if (!dev->ctrl.tagset) {
2088                 dev->tagset.ops = &nvme_mq_ops;
2089                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2090                 dev->tagset.timeout = NVME_IO_TIMEOUT;
2091                 dev->tagset.numa_node = dev_to_node(dev->dev);
2092                 dev->tagset.queue_depth =
2093                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2094                 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2095                 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2096                         dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2097                                         nvme_pci_cmd_size(dev, true));
2098                 }
2099                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2100                 dev->tagset.driver_data = dev;
2101
2102                 ret = blk_mq_alloc_tag_set(&dev->tagset);
2103                 if (ret) {
2104                         dev_warn(dev->ctrl.device,
2105                                 "IO queues tagset allocation failed %d\n", ret);
2106                         return ret;
2107                 }
2108                 dev->ctrl.tagset = &dev->tagset;
2109
2110                 nvme_dbbuf_set(dev);
2111         } else {
2112                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2113
2114                 /* Free previously allocated queues that are no longer usable */
2115                 nvme_free_queues(dev, dev->online_queues);
2116         }
2117
2118         return 0;
2119 }
2120
2121 static int nvme_pci_enable(struct nvme_dev *dev)
2122 {
2123         int result = -ENOMEM;
2124         struct pci_dev *pdev = to_pci_dev(dev->dev);
2125
2126         if (pci_enable_device_mem(pdev))
2127                 return result;
2128
2129         pci_set_master(pdev);
2130
2131         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2132             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
2133                 goto disable;
2134
2135         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2136                 result = -ENODEV;
2137                 goto disable;
2138         }
2139
2140         /*
2141          * Some devices and/or platforms don't advertise or work with INTx
2142          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2143          * adjust this later.
2144          */
2145         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2146         if (result < 0)
2147                 return result;
2148
2149         dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2150
2151         dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2152                                 io_queue_depth);
2153         dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2154         dev->dbs = dev->bar + 4096;
2155
2156         /*
2157          * Temporary fix for the Apple controller found in the MacBook8,1 and
2158          * some MacBook7,1 to avoid controller resets and data loss.
2159          */
2160         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2161                 dev->q_depth = 2;
2162                 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2163                         "set queue depth=%u to work around controller resets\n",
2164                         dev->q_depth);
2165         } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2166                    (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2167                    NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2168                 dev->q_depth = 64;
2169                 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2170                         "set queue depth=%u\n", dev->q_depth);
2171         }
2172
2173         nvme_map_cmb(dev);
2174
2175         pci_enable_pcie_error_reporting(pdev);
2176         pci_save_state(pdev);
2177         return 0;
2178
2179  disable:
2180         pci_disable_device(pdev);
2181         return result;
2182 }
2183
2184 static void nvme_dev_unmap(struct nvme_dev *dev)
2185 {
2186         if (dev->bar)
2187                 iounmap(dev->bar);
2188         pci_release_mem_regions(to_pci_dev(dev->dev));
2189 }
2190
2191 static void nvme_pci_disable(struct nvme_dev *dev)
2192 {
2193         struct pci_dev *pdev = to_pci_dev(dev->dev);
2194
2195         nvme_release_cmb(dev);
2196         pci_free_irq_vectors(pdev);
2197
2198         if (pci_is_enabled(pdev)) {
2199                 pci_disable_pcie_error_reporting(pdev);
2200                 pci_disable_device(pdev);
2201         }
2202 }
2203
2204 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2205 {
2206         int i;
2207         bool dead = true;
2208         struct pci_dev *pdev = to_pci_dev(dev->dev);
2209
2210         mutex_lock(&dev->shutdown_lock);
2211         if (pci_is_enabled(pdev)) {
2212                 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2213
2214                 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2215                     dev->ctrl.state == NVME_CTRL_RESETTING)
2216                         nvme_start_freeze(&dev->ctrl);
2217                 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2218                         pdev->error_state  != pci_channel_io_normal);
2219         }
2220
2221         /*
2222          * Give the controller a chance to complete all entered requests if
2223          * doing a safe shutdown.
2224          */
2225         if (!dead) {
2226                 if (shutdown)
2227                         nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2228         }
2229
2230         nvme_stop_queues(&dev->ctrl);
2231
2232         if (!dead && dev->ctrl.queue_count > 0) {
2233                 nvme_disable_io_queues(dev);
2234                 nvme_disable_admin_queue(dev, shutdown);
2235         }
2236         for (i = dev->ctrl.queue_count - 1; i >= 0; i--)
2237                 nvme_suspend_queue(&dev->queues[i]);
2238
2239         nvme_pci_disable(dev);
2240
2241         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2242         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2243
2244         /*
2245          * The driver will not be starting up queues again if shutting down so
2246          * must flush all entered requests to their failed completion to avoid
2247          * deadlocking blk-mq hot-cpu notifier.
2248          */
2249         if (shutdown)
2250                 nvme_start_queues(&dev->ctrl);
2251         mutex_unlock(&dev->shutdown_lock);
2252 }
2253
2254 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2255 {
2256         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2257                                                 PAGE_SIZE, PAGE_SIZE, 0);
2258         if (!dev->prp_page_pool)
2259                 return -ENOMEM;
2260
2261         /* Optimisation for I/Os between 4k and 128k */
2262         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2263                                                 256, 256, 0);
2264         if (!dev->prp_small_pool) {
2265                 dma_pool_destroy(dev->prp_page_pool);
2266                 return -ENOMEM;
2267         }
2268         return 0;
2269 }
2270
2271 static void nvme_release_prp_pools(struct nvme_dev *dev)
2272 {
2273         dma_pool_destroy(dev->prp_page_pool);
2274         dma_pool_destroy(dev->prp_small_pool);
2275 }
2276
2277 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2278 {
2279         struct nvme_dev *dev = to_nvme_dev(ctrl);
2280
2281         nvme_dbbuf_dma_free(dev);
2282         put_device(dev->dev);
2283         if (dev->tagset.tags)
2284                 blk_mq_free_tag_set(&dev->tagset);
2285         if (dev->ctrl.admin_q)
2286                 blk_put_queue(dev->ctrl.admin_q);
2287         kfree(dev->queues);
2288         free_opal_dev(dev->ctrl.opal_dev);
2289         mempool_destroy(dev->iod_mempool);
2290         kfree(dev);
2291 }
2292
2293 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2294 {
2295         dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
2296
2297         nvme_get_ctrl(&dev->ctrl);
2298         nvme_dev_disable(dev, false);
2299         nvme_kill_queues(&dev->ctrl);
2300         if (!queue_work(nvme_wq, &dev->remove_work))
2301                 nvme_put_ctrl(&dev->ctrl);
2302 }
2303
2304 static void nvme_reset_work(struct work_struct *work)
2305 {
2306         struct nvme_dev *dev =
2307                 container_of(work, struct nvme_dev, ctrl.reset_work);
2308         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2309         int result = -ENODEV;
2310         enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
2311
2312         if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
2313                 goto out;
2314
2315         /*
2316          * If we're called to reset a live controller first shut it down before
2317          * moving on.
2318          */
2319         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2320                 nvme_dev_disable(dev, false);
2321
2322         /*
2323          * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2324          * initializing procedure here.
2325          */
2326         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2327                 dev_warn(dev->ctrl.device,
2328                         "failed to mark controller CONNECTING\n");
2329                 goto out;
2330         }
2331
2332         result = nvme_pci_enable(dev);
2333         if (result)
2334                 goto out;
2335
2336         result = nvme_pci_configure_admin_queue(dev);
2337         if (result)
2338                 goto out;
2339
2340         result = nvme_alloc_admin_tags(dev);
2341         if (result)
2342                 goto out;
2343
2344         /*
2345          * Limit the max command size to prevent iod->sg allocations going
2346          * over a single page.
2347          */
2348         dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1;
2349         dev->ctrl.max_segments = NVME_MAX_SEGS;
2350
2351         result = nvme_init_identify(&dev->ctrl);
2352         if (result)
2353                 goto out;
2354
2355         if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2356                 if (!dev->ctrl.opal_dev)
2357                         dev->ctrl.opal_dev =
2358                                 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2359                 else if (was_suspend)
2360                         opal_unlock_from_suspend(dev->ctrl.opal_dev);
2361         } else {
2362                 free_opal_dev(dev->ctrl.opal_dev);
2363                 dev->ctrl.opal_dev = NULL;
2364         }
2365
2366         if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2367                 result = nvme_dbbuf_dma_alloc(dev);
2368                 if (result)
2369                         dev_warn(dev->dev,
2370                                  "unable to allocate dma for dbbuf\n");
2371         }
2372
2373         if (dev->ctrl.hmpre) {
2374                 result = nvme_setup_host_mem(dev);
2375                 if (result < 0)
2376                         goto out;
2377         }
2378
2379         result = nvme_setup_io_queues(dev);
2380         if (result)
2381                 goto out;
2382
2383         /*
2384          * Keep the controller around but remove all namespaces if we don't have
2385          * any working I/O queue.
2386          */
2387         if (dev->online_queues < 2) {
2388                 dev_warn(dev->ctrl.device, "IO queues not created\n");
2389                 nvme_kill_queues(&dev->ctrl);
2390                 nvme_remove_namespaces(&dev->ctrl);
2391                 new_state = NVME_CTRL_ADMIN_ONLY;
2392         } else {
2393                 nvme_start_queues(&dev->ctrl);
2394                 nvme_wait_freeze(&dev->ctrl);
2395                 /* hit this only when allocate tagset fails */
2396                 if (nvme_dev_add(dev))
2397                         new_state = NVME_CTRL_ADMIN_ONLY;
2398                 nvme_unfreeze(&dev->ctrl);
2399         }
2400
2401         /*
2402          * If only admin queue live, keep it to do further investigation or
2403          * recovery.
2404          */
2405         if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2406                 dev_warn(dev->ctrl.device,
2407                         "failed to mark controller state %d\n", new_state);
2408                 goto out;
2409         }
2410
2411         nvme_start_ctrl(&dev->ctrl);
2412         return;
2413
2414  out:
2415         nvme_remove_dead_ctrl(dev, result);
2416 }
2417
2418 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2419 {
2420         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2421         struct pci_dev *pdev = to_pci_dev(dev->dev);
2422
2423         if (pci_get_drvdata(pdev))
2424                 device_release_driver(&pdev->dev);
2425         nvme_put_ctrl(&dev->ctrl);
2426 }
2427
2428 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2429 {
2430         *val = readl(to_nvme_dev(ctrl)->bar + off);
2431         return 0;
2432 }
2433
2434 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2435 {
2436         writel(val, to_nvme_dev(ctrl)->bar + off);
2437         return 0;
2438 }
2439
2440 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2441 {
2442         *val = readq(to_nvme_dev(ctrl)->bar + off);
2443         return 0;
2444 }
2445
2446 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2447 {
2448         struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2449
2450         return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2451 }
2452
2453 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2454         .name                   = "pcie",
2455         .module                 = THIS_MODULE,
2456         .flags                  = NVME_F_METADATA_SUPPORTED,
2457         .reg_read32             = nvme_pci_reg_read32,
2458         .reg_write32            = nvme_pci_reg_write32,
2459         .reg_read64             = nvme_pci_reg_read64,
2460         .free_ctrl              = nvme_pci_free_ctrl,
2461         .submit_async_event     = nvme_pci_submit_async_event,
2462         .get_address            = nvme_pci_get_address,
2463 };
2464
2465 static int nvme_dev_map(struct nvme_dev *dev)
2466 {
2467         struct pci_dev *pdev = to_pci_dev(dev->dev);
2468
2469         if (pci_request_mem_regions(pdev, "nvme"))
2470                 return -ENODEV;
2471
2472         if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2473                 goto release;
2474
2475         return 0;
2476   release:
2477         pci_release_mem_regions(pdev);
2478         return -ENODEV;
2479 }
2480
2481 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2482 {
2483         if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2484                 /*
2485                  * Several Samsung devices seem to drop off the PCIe bus
2486                  * randomly when APST is on and uses the deepest sleep state.
2487                  * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2488                  * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2489                  * 950 PRO 256GB", but it seems to be restricted to two Dell
2490                  * laptops.
2491                  */
2492                 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2493                     (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2494                      dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2495                         return NVME_QUIRK_NO_DEEPEST_PS;
2496         } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2497                 /*
2498                  * Samsung SSD 960 EVO drops off the PCIe bus after system
2499                  * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2500                  * within few minutes after bootup on a Coffee Lake board -
2501                  * ASUS PRIME Z370-A
2502                  */
2503                 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2504                     (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2505                      dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2506                         return NVME_QUIRK_NO_APST;
2507         }
2508
2509         return 0;
2510 }
2511
2512 static void nvme_async_probe(void *data, async_cookie_t cookie)
2513 {
2514         struct nvme_dev *dev = data;
2515
2516         nvme_reset_ctrl_sync(&dev->ctrl);
2517         flush_work(&dev->ctrl.scan_work);
2518         nvme_put_ctrl(&dev->ctrl);
2519 }
2520
2521 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2522 {
2523         int node, result = -ENOMEM;
2524         struct nvme_dev *dev;
2525         unsigned long quirks = id->driver_data;
2526         size_t alloc_size;
2527
2528         node = dev_to_node(&pdev->dev);
2529         if (node == NUMA_NO_NODE)
2530                 set_dev_node(&pdev->dev, first_memory_node);
2531
2532         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2533         if (!dev)
2534                 return -ENOMEM;
2535
2536         dev->queues = kcalloc_node(num_possible_cpus() + 1,
2537                         sizeof(struct nvme_queue), GFP_KERNEL, node);
2538         if (!dev->queues)
2539                 goto free;
2540
2541         dev->dev = get_device(&pdev->dev);
2542         pci_set_drvdata(pdev, dev);
2543
2544         result = nvme_dev_map(dev);
2545         if (result)
2546                 goto put_pci;
2547
2548         INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2549         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2550         mutex_init(&dev->shutdown_lock);
2551         init_completion(&dev->ioq_wait);
2552
2553         result = nvme_setup_prp_pools(dev);
2554         if (result)
2555                 goto unmap;
2556
2557         quirks |= check_vendor_combination_bug(pdev);
2558
2559         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2560                         quirks);
2561         if (result)
2562                 goto release_pools;
2563
2564         /*
2565          * Double check that our mempool alloc size will cover the biggest
2566          * command we support.
2567          */
2568         alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2569                                                 NVME_MAX_SEGS, true);
2570         WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2571
2572         dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2573                                                 mempool_kfree,
2574                                                 (void *) alloc_size,
2575                                                 GFP_KERNEL, node);
2576         if (!dev->iod_mempool) {
2577                 result = -ENOMEM;
2578                 goto release_pools;
2579         }
2580
2581         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2582
2583         nvme_get_ctrl(&dev->ctrl);
2584         async_schedule(nvme_async_probe, dev);
2585
2586         return 0;
2587
2588  release_pools:
2589         nvme_release_prp_pools(dev);
2590  unmap:
2591         nvme_dev_unmap(dev);
2592  put_pci:
2593         put_device(dev->dev);
2594  free:
2595         kfree(dev->queues);
2596         kfree(dev);
2597         return result;
2598 }
2599
2600 static void nvme_reset_prepare(struct pci_dev *pdev)
2601 {
2602         struct nvme_dev *dev = pci_get_drvdata(pdev);
2603         nvme_dev_disable(dev, false);
2604 }
2605
2606 static void nvme_reset_done(struct pci_dev *pdev)
2607 {
2608         struct nvme_dev *dev = pci_get_drvdata(pdev);
2609         nvme_reset_ctrl_sync(&dev->ctrl);
2610 }
2611
2612 static void nvme_shutdown(struct pci_dev *pdev)
2613 {
2614         struct nvme_dev *dev = pci_get_drvdata(pdev);
2615         nvme_dev_disable(dev, true);
2616 }
2617
2618 /*
2619  * The driver's remove may be called on a device in a partially initialized
2620  * state. This function must not have any dependencies on the device state in
2621  * order to proceed.
2622  */
2623 static void nvme_remove(struct pci_dev *pdev)
2624 {
2625         struct nvme_dev *dev = pci_get_drvdata(pdev);
2626
2627         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2628
2629         cancel_work_sync(&dev->ctrl.reset_work);
2630         pci_set_drvdata(pdev, NULL);
2631
2632         if (!pci_device_is_present(pdev)) {
2633                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2634                 nvme_dev_disable(dev, true);
2635         }
2636
2637         flush_work(&dev->ctrl.reset_work);
2638         nvme_stop_ctrl(&dev->ctrl);
2639         nvme_remove_namespaces(&dev->ctrl);
2640         nvme_dev_disable(dev, true);
2641         nvme_free_host_mem(dev);
2642         nvme_dev_remove_admin(dev);
2643         nvme_free_queues(dev, 0);
2644         nvme_uninit_ctrl(&dev->ctrl);
2645         nvme_release_prp_pools(dev);
2646         nvme_dev_unmap(dev);
2647         nvme_put_ctrl(&dev->ctrl);
2648 }
2649
2650 #ifdef CONFIG_PM_SLEEP
2651 static int nvme_suspend(struct device *dev)
2652 {
2653         struct pci_dev *pdev = to_pci_dev(dev);
2654         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2655
2656         nvme_dev_disable(ndev, true);
2657         return 0;
2658 }
2659
2660 static int nvme_resume(struct device *dev)
2661 {
2662         struct pci_dev *pdev = to_pci_dev(dev);
2663         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2664
2665         nvme_reset_ctrl(&ndev->ctrl);
2666         return 0;
2667 }
2668 #endif
2669
2670 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2671
2672 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2673                                                 pci_channel_state_t state)
2674 {
2675         struct nvme_dev *dev = pci_get_drvdata(pdev);
2676
2677         /*
2678          * A frozen channel requires a reset. When detected, this method will
2679          * shutdown the controller to quiesce. The controller will be restarted
2680          * after the slot reset through driver's slot_reset callback.
2681          */
2682         switch (state) {
2683         case pci_channel_io_normal:
2684                 return PCI_ERS_RESULT_CAN_RECOVER;
2685         case pci_channel_io_frozen:
2686                 dev_warn(dev->ctrl.device,
2687                         "frozen state error detected, reset controller\n");
2688                 nvme_dev_disable(dev, false);
2689                 return PCI_ERS_RESULT_NEED_RESET;
2690         case pci_channel_io_perm_failure:
2691                 dev_warn(dev->ctrl.device,
2692                         "failure state error detected, request disconnect\n");
2693                 return PCI_ERS_RESULT_DISCONNECT;
2694         }
2695         return PCI_ERS_RESULT_NEED_RESET;
2696 }
2697
2698 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2699 {
2700         struct nvme_dev *dev = pci_get_drvdata(pdev);
2701
2702         dev_info(dev->ctrl.device, "restart after slot reset\n");
2703         pci_restore_state(pdev);
2704         nvme_reset_ctrl(&dev->ctrl);
2705         return PCI_ERS_RESULT_RECOVERED;
2706 }
2707
2708 static void nvme_error_resume(struct pci_dev *pdev)
2709 {
2710         struct nvme_dev *dev = pci_get_drvdata(pdev);
2711
2712         flush_work(&dev->ctrl.reset_work);
2713         pci_cleanup_aer_uncorrect_error_status(pdev);
2714 }
2715
2716 static const struct pci_error_handlers nvme_err_handler = {
2717         .error_detected = nvme_error_detected,
2718         .slot_reset     = nvme_slot_reset,
2719         .resume         = nvme_error_resume,
2720         .reset_prepare  = nvme_reset_prepare,
2721         .reset_done     = nvme_reset_done,
2722 };
2723
2724 static const struct pci_device_id nvme_id_table[] = {
2725         { PCI_VDEVICE(INTEL, 0x0953),
2726                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2727                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2728         { PCI_VDEVICE(INTEL, 0x0a53),
2729                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2730                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2731         { PCI_VDEVICE(INTEL, 0x0a54),
2732                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2733                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2734         { PCI_VDEVICE(INTEL, 0x0a55),
2735                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2736                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2737         { PCI_VDEVICE(INTEL, 0xf1a5),   /* Intel 600P/P3100 */
2738                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2739                                 NVME_QUIRK_MEDIUM_PRIO_SQ },
2740         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2741                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2742         { PCI_DEVICE(0x1bb1, 0x0100),   /* Seagate Nytro Flash Storage */
2743                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2744         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
2745                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2746         { PCI_DEVICE(0x1c58, 0x0023),   /* WDC SN200 adapter */
2747                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2748         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
2749                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2750         { PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */
2751                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2752         { PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */
2753                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2754         { PCI_DEVICE(0x1d1d, 0x1f1f),   /* LighNVM qemu device */
2755                 .driver_data = NVME_QUIRK_LIGHTNVM, },
2756         { PCI_DEVICE(0x1d1d, 0x2807),   /* CNEX WL */
2757                 .driver_data = NVME_QUIRK_LIGHTNVM, },
2758         { PCI_DEVICE(0x1d1d, 0x2601),   /* CNEX Granby */
2759                 .driver_data = NVME_QUIRK_LIGHTNVM, },
2760         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2761         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2762         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2763         { 0, }
2764 };
2765 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2766
2767 static struct pci_driver nvme_driver = {
2768         .name           = "nvme",
2769         .id_table       = nvme_id_table,
2770         .probe          = nvme_probe,
2771         .remove         = nvme_remove,
2772         .shutdown       = nvme_shutdown,
2773         .driver         = {
2774                 .pm     = &nvme_dev_pm_ops,
2775         },
2776         .sriov_configure = pci_sriov_configure_simple,
2777         .err_handler    = &nvme_err_handler,
2778 };
2779
2780 static int __init nvme_init(void)
2781 {
2782         return pci_register_driver(&nvme_driver);
2783 }
2784
2785 static void __exit nvme_exit(void)
2786 {
2787         pci_unregister_driver(&nvme_driver);
2788         flush_workqueue(nvme_wq);
2789         _nvme_check_size();
2790 }
2791
2792 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2793 MODULE_LICENSE("GPL");
2794 MODULE_VERSION("1.0");
2795 module_init(nvme_init);
2796 module_exit(nvme_exit);