drivers/nvme/host/pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * NVM Express device driver
   4  * Copyright (c) 2011-2014, Intel Corporation.
   5  */
   6
   7 #include <linux/acpi.h>
   8 #include <linux/aer.h>
   9 #include <linux/async.h>
  10 #include <linux/blkdev.h>
  11 #include <linux/blk-mq.h>
  12 #include <linux/blk-mq-pci.h>
  13 #include <linux/dmi.h>
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/mm.h>
  18 #include <linux/module.h>
  19 #include <linux/mutex.h>
  20 #include <linux/once.h>
  21 #include <linux/pci.h>
  22 #include <linux/suspend.h>
  23 #include <linux/t10-pi.h>
  24 #include <linux/types.h>
  25 #include <linux/io-64-nonatomic-lo-hi.h>
  26 #include <linux/io-64-nonatomic-hi-lo.h>
  27 #include <linux/sed-opal.h>
  28 #include <linux/pci-p2pdma.h>
  29
  30 #include "trace.h"
  31 #include "nvme.h"
  32
  33 #define SQ_SIZE(q)      ((q)->q_depth << (q)->sqes)
  34 #define CQ_SIZE(q)      ((q)->q_depth * sizeof(struct nvme_completion))
  35
  36 #define SGES_PER_PAGE   (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
  37
  38 /*
  39  * These can be higher, but we need to ensure that any command doesn't
  40  * require an sg allocation that needs more than a page of data.
  41  */
  42 #define NVME_MAX_KB_SZ  4096
  43 #define NVME_MAX_SEGS   127
  44
  45 static int use_threaded_interrupts;
  46 module_param(use_threaded_interrupts, int, 0);
  47
  48 static bool use_cmb_sqes = true;
  49 module_param(use_cmb_sqes, bool, 0444);
  50 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  51
  52 static unsigned int max_host_mem_size_mb = 128;
  53 module_param(max_host_mem_size_mb, uint, 0444);
  54 MODULE_PARM_DESC(max_host_mem_size_mb,
  55         "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
  56
  57 static unsigned int sgl_threshold = SZ_32K;
  58 module_param(sgl_threshold, uint, 0644);
  59 MODULE_PARM_DESC(sgl_threshold,
  60                 "Use SGLs when average request segment size is larger or equal to "
  61                 "this size. Use 0 to disable SGLs.");
  62
  63 #define NVME_PCI_MIN_QUEUE_SIZE 2
  64 #define NVME_PCI_MAX_QUEUE_SIZE 4095
  65 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
  66 static const struct kernel_param_ops io_queue_depth_ops = {
  67         .set = io_queue_depth_set,
  68         .get = param_get_uint,
  69 };
  70
  71 static unsigned int io_queue_depth = 1024;
  72 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
  73 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
  74
  75 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
  76 {
  77         unsigned int n;
  78         int ret;
  79
  80         ret = kstrtouint(val, 10, &n);
  81         if (ret != 0 || n > num_possible_cpus())
  82                 return -EINVAL;
  83         return param_set_uint(val, kp);
  84 }
  85
  86 static const struct kernel_param_ops io_queue_count_ops = {
  87         .set = io_queue_count_set,
  88         .get = param_get_uint,
  89 };
  90
  91 static unsigned int write_queues;
  92 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
  93 MODULE_PARM_DESC(write_queues,
  94         "Number of queues to use for writes. If not set, reads and writes "
  95         "will share a queue set.");
  96
  97 static unsigned int poll_queues;
  98 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
  99 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
 100
 101 static bool noacpi;
 102 module_param(noacpi, bool, 0444);
 103 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
 104
 105 struct nvme_dev;
 106 struct nvme_queue;
 107
 108 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
 109 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
 110
 111 /*
 112  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
 113  */
 114 struct nvme_dev {
 115         struct nvme_queue *queues;
 116         struct blk_mq_tag_set tagset;
 117         struct blk_mq_tag_set admin_tagset;
 118         u32 __iomem *dbs;
 119         struct device *dev;
 120         struct dma_pool *prp_page_pool;
 121         struct dma_pool *prp_small_pool;
 122         unsigned online_queues;
 123         unsigned max_qid;
 124         unsigned io_queues[HCTX_MAX_TYPES];
 125         unsigned int num_vecs;
 126         u32 q_depth;
 127         int io_sqes;
 128         u32 db_stride;
 129         void __iomem *bar;
 130         unsigned long bar_mapped_size;
 131         struct work_struct remove_work;
 132         struct mutex shutdown_lock;
 133         bool subsystem;
 134         u64 cmb_size;
 135         bool cmb_use_sqes;
 136         u32 cmbsz;
 137         u32 cmbloc;
 138         struct nvme_ctrl ctrl;
 139         u32 last_ps;
 140
 141         mempool_t *iod_mempool;
 142
 143         /* shadow doorbell buffer support: */
 144         u32 *dbbuf_dbs;
 145         dma_addr_t dbbuf_dbs_dma_addr;
 146         u32 *dbbuf_eis;
 147         dma_addr_t dbbuf_eis_dma_addr;
 148
 149         /* host memory buffer support: */
 150         u64 host_mem_size;
 151         u32 nr_host_mem_descs;
 152         dma_addr_t host_mem_descs_dma;
 153         struct nvme_host_mem_buf_desc *host_mem_descs;
 154         void **host_mem_desc_bufs;
 155         unsigned int nr_allocated_queues;
 156         unsigned int nr_write_queues;
 157         unsigned int nr_poll_queues;
 158
 159         bool attrs_added;
 160 };
 161
 162 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
 163 {
 164         return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
 165                         NVME_PCI_MAX_QUEUE_SIZE);
 166 }
 167
 168 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
 169 {
 170         return qid * 2 * stride;
 171 }
 172
 173 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
 174 {
 175         return (qid * 2 + 1) * stride;
 176 }
 177
 178 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 179 {
 180         return container_of(ctrl, struct nvme_dev, ctrl);
 181 }
 182
 183 /*
 184  * An NVM Express queue.  Each device has at least two (one for admin
 185  * commands and one for I/O commands).
 186  */
 187 struct nvme_queue {
 188         struct nvme_dev *dev;
 189         spinlock_t sq_lock;
 190         void *sq_cmds;
 191          /* only used for poll queues: */
 192         spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
 193         struct nvme_completion *cqes;
 194         dma_addr_t sq_dma_addr;
 195         dma_addr_t cq_dma_addr;
 196         u32 __iomem *q_db;
 197         u32 q_depth;
 198         u16 cq_vector;
 199         u16 sq_tail;
 200         u16 last_sq_tail;
 201         u16 cq_head;
 202         u16 qid;
 203         u8 cq_phase;
 204         u8 sqes;
 205         unsigned long flags;
 206 #define NVMEQ_ENABLED           0
 207 #define NVMEQ_SQ_CMB            1
 208 #define NVMEQ_DELETE_ERROR      2
 209 #define NVMEQ_POLLED            3
 210         u32 *dbbuf_sq_db;
 211         u32 *dbbuf_cq_db;
 212         u32 *dbbuf_sq_ei;
 213         u32 *dbbuf_cq_ei;
 214         struct completion delete_done;
 215 };
 216
 217 /*
 218  * The nvme_iod describes the data in an I/O.
 219  *
 220  * The sg pointer contains the list of PRP/SGL chunk allocations in addition
 221  * to the actual struct scatterlist.
 222  */
 223 struct nvme_iod {
 224         struct nvme_request req;
 225         struct nvme_command cmd;
 226         struct nvme_queue *nvmeq;
 227         bool use_sgl;
 228         int aborted;
 229         int npages;             /* In the PRP list. 0 means small pool in use */
 230         int nents;              /* Used in scatterlist */
 231         dma_addr_t first_dma;
 232         unsigned int dma_len;   /* length of single DMA segment mapping */
 233         dma_addr_t meta_dma;
 234         struct scatterlist *sg;
 235 };
 236
 237 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
 238 {
 239         return dev->nr_allocated_queues * 8 * dev->db_stride;
 240 }
 241
 242 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
 243 {
 244         unsigned int mem_size = nvme_dbbuf_size(dev);
 245
 246         if (dev->dbbuf_dbs)
 247                 return 0;
 248
 249         dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
 250                                             &dev->dbbuf_dbs_dma_addr,
 251                                             GFP_KERNEL);
 252         if (!dev->dbbuf_dbs)
 253                 return -ENOMEM;
 254         dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
 255                                             &dev->dbbuf_eis_dma_addr,
 256                                             GFP_KERNEL);
 257         if (!dev->dbbuf_eis) {
 258                 dma_free_coherent(dev->dev, mem_size,
 259                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 260                 dev->dbbuf_dbs = NULL;
 261                 return -ENOMEM;
 262         }
 263
 264         return 0;
 265 }
 266
 267 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
 268 {
 269         unsigned int mem_size = nvme_dbbuf_size(dev);
 270
 271         if (dev->dbbuf_dbs) {
 272                 dma_free_coherent(dev->dev, mem_size,
 273                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 274                 dev->dbbuf_dbs = NULL;
 275         }
 276         if (dev->dbbuf_eis) {
 277                 dma_free_coherent(dev->dev, mem_size,
 278                                   dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
 279                 dev->dbbuf_eis = NULL;
 280         }
 281 }
 282
 283 static void nvme_dbbuf_init(struct nvme_dev *dev,
 284                             struct nvme_queue *nvmeq, int qid)
 285 {
 286         if (!dev->dbbuf_dbs || !qid)
 287                 return;
 288
 289         nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
 290         nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
 291         nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
 292         nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
 293 }
 294
 295 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
 296 {
 297         if (!nvmeq->qid)
 298                 return;
 299
 300         nvmeq->dbbuf_sq_db = NULL;
 301         nvmeq->dbbuf_cq_db = NULL;
 302         nvmeq->dbbuf_sq_ei = NULL;
 303         nvmeq->dbbuf_cq_ei = NULL;
 304 }
 305
 306 static void nvme_dbbuf_set(struct nvme_dev *dev)
 307 {
 308         struct nvme_command c = { };
 309         unsigned int i;
 310
 311         if (!dev->dbbuf_dbs)
 312                 return;
 313
 314         c.dbbuf.opcode = nvme_admin_dbbuf;
 315         c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
 316         c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
 317
 318         if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
 319                 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
 320                 /* Free memory and continue on */
 321                 nvme_dbbuf_dma_free(dev);
 322
 323                 for (i = 1; i <= dev->online_queues; i++)
 324                         nvme_dbbuf_free(&dev->queues[i]);
 325         }
 326 }
 327
 328 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
 329 {
 330         return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
 331 }
 332
 333 /* Update dbbuf and return true if an MMIO is required */
 334 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
 335                                               volatile u32 *dbbuf_ei)
 336 {
 337         if (dbbuf_db) {
 338                 u16 old_value;
 339
 340                 /*
 341                  * Ensure that the queue is written before updating
 342                  * the doorbell in memory
 343                  */
 344                 wmb();
 345
 346                 old_value = *dbbuf_db;
 347                 *dbbuf_db = value;
 348
 349                 /*
 350                  * Ensure that the doorbell is updated before reading the event
 351                  * index from memory.  The controller needs to provide similar
 352                  * ordering to ensure the envent index is updated before reading
 353                  * the doorbell.
 354                  */
 355                 mb();
 356
 357                 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
 358                         return false;
 359         }
 360
 361         return true;
 362 }
 363
 364 /*
 365  * Will slightly overestimate the number of pages needed.  This is OK
 366  * as it only leads to a small amount of wasted memory for the lifetime of
 367  * the I/O.
 368  */
 369 static int nvme_pci_npages_prp(void)
 370 {
 371         unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
 372                                       NVME_CTRL_PAGE_SIZE);
 373         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 374 }
 375
 376 /*
 377  * Calculates the number of pages needed for the SGL segments. For example a 4k
 378  * page can accommodate 256 SGL descriptors.
 379  */
 380 static int nvme_pci_npages_sgl(void)
 381 {
 382         return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
 383                         PAGE_SIZE);
 384 }
 385
 386 static size_t nvme_pci_iod_alloc_size(void)
 387 {
 388         size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
 389
 390         return sizeof(__le64 *) * npages +
 391                 sizeof(struct scatterlist) * NVME_MAX_SEGS;
 392 }
 393
 394 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 395                                 unsigned int hctx_idx)
 396 {
 397         struct nvme_dev *dev = data;
 398         struct nvme_queue *nvmeq = &dev->queues[0];
 399
 400         WARN_ON(hctx_idx != 0);
 401         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 402
 403         hctx->driver_data = nvmeq;
 404         return 0;
 405 }
 406
 407 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 408                           unsigned int hctx_idx)
 409 {
 410         struct nvme_dev *dev = data;
 411         struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
 412
 413         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 414         hctx->driver_data = nvmeq;
 415         return 0;
 416 }
 417
 418 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
 419                 unsigned int hctx_idx, unsigned int numa_node)
 420 {
 421         struct nvme_dev *dev = set->driver_data;
 422         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 423         int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
 424         struct nvme_queue *nvmeq = &dev->queues[queue_idx];
 425
 426         BUG_ON(!nvmeq);
 427         iod->nvmeq = nvmeq;
 428
 429         nvme_req(req)->ctrl = &dev->ctrl;
 430         nvme_req(req)->cmd = &iod->cmd;
 431         return 0;
 432 }
 433
 434 static int queue_irq_offset(struct nvme_dev *dev)
 435 {
 436         /* if we have more than 1 vec, admin queue offsets us by 1 */
 437         if (dev->num_vecs > 1)
 438                 return 1;
 439
 440         return 0;
 441 }
 442
 443 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 444 {
 445         struct nvme_dev *dev = set->driver_data;
 446         int i, qoff, offset;
 447
 448         offset = queue_irq_offset(dev);
 449         for (i = 0, qoff = 0; i < set->nr_maps; i++) {
 450                 struct blk_mq_queue_map *map = &set->map[i];
 451
 452                 map->nr_queues = dev->io_queues[i];
 453                 if (!map->nr_queues) {
 454                         BUG_ON(i == HCTX_TYPE_DEFAULT);
 455                         continue;
 456                 }
 457
 458                 /*
 459                  * The poll queue(s) doesn't have an IRQ (and hence IRQ
 460                  * affinity), so use the regular blk-mq cpu mapping
 461                  */
 462                 map->queue_offset = qoff;
 463                 if (i != HCTX_TYPE_POLL && offset)
 464                         blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
 465                 else
 466                         blk_mq_map_queues(map);
 467                 qoff += map->nr_queues;
 468                 offset += map->nr_queues;
 469         }
 470
 471         return 0;
 472 }
 473
 474 /*
 475  * Write sq tail if we are asked to, or if the next command would wrap.
 476  */
 477 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
 478 {
 479         if (!write_sq) {
 480                 u16 next_tail = nvmeq->sq_tail + 1;
 481
 482                 if (next_tail == nvmeq->q_depth)
 483                         next_tail = 0;
 484                 if (next_tail != nvmeq->last_sq_tail)
 485                         return;
 486         }
 487
 488         if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
 489                         nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
 490                 writel(nvmeq->sq_tail, nvmeq->q_db);
 491         nvmeq->last_sq_tail = nvmeq->sq_tail;
 492 }
 493
 494 /**
 495  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 496  * @nvmeq: The queue to use
 497  * @cmd: The command to send
 498  * @write_sq: whether to write to the SQ doorbell
 499  */
 500 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
 501                             bool write_sq)
 502 {
 503         spin_lock(&nvmeq->sq_lock);
 504         memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
 505                cmd, sizeof(*cmd));
 506         if (++nvmeq->sq_tail == nvmeq->q_depth)
 507                 nvmeq->sq_tail = 0;
 508         nvme_write_sq_db(nvmeq, write_sq);
 509         spin_unlock(&nvmeq->sq_lock);
 510 }
 511
 512 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
 513 {
 514         struct nvme_queue *nvmeq = hctx->driver_data;
 515
 516         spin_lock(&nvmeq->sq_lock);
 517         if (nvmeq->sq_tail != nvmeq->last_sq_tail)
 518                 nvme_write_sq_db(nvmeq, true);
 519         spin_unlock(&nvmeq->sq_lock);
 520 }
 521
 522 static void **nvme_pci_iod_list(struct request *req)
 523 {
 524         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 525         return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
 526 }
 527
 528 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
 529 {
 530         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 531         int nseg = blk_rq_nr_phys_segments(req);
 532         unsigned int avg_seg_size;
 533
 534         avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
 535
 536         if (!nvme_ctrl_sgl_supported(&dev->ctrl))
 537                 return false;
 538         if (!iod->nvmeq->qid)
 539                 return false;
 540         if (!sgl_threshold || avg_seg_size < sgl_threshold)
 541                 return false;
 542         return true;
 543 }
 544
 545 static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
 546 {
 547         const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
 548         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 549         dma_addr_t dma_addr = iod->first_dma;
 550         int i;
 551
 552         for (i = 0; i < iod->npages; i++) {
 553                 __le64 *prp_list = nvme_pci_iod_list(req)[i];
 554                 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
 555
 556                 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
 557                 dma_addr = next_dma_addr;
 558         }
 559 }
 560
 561 static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
 562 {
 563         const int last_sg = SGES_PER_PAGE - 1;
 564         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 565         dma_addr_t dma_addr = iod->first_dma;
 566         int i;
 567
 568         for (i = 0; i < iod->npages; i++) {
 569                 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
 570                 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
 571
 572                 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
 573                 dma_addr = next_dma_addr;
 574         }
 575 }
 576
 577 static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
 578 {
 579         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 580
 581         if (is_pci_p2pdma_page(sg_page(iod->sg)))
 582                 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
 583                                     rq_dma_dir(req));
 584         else
 585                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
 586 }
 587
 588 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 589 {
 590         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 591
 592         if (iod->dma_len) {
 593                 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
 594                                rq_dma_dir(req));
 595                 return;
 596         }
 597
 598         WARN_ON_ONCE(!iod->nents);
 599
 600         nvme_unmap_sg(dev, req);
 601         if (iod->npages == 0)
 602                 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
 603                               iod->first_dma);
 604         else if (iod->use_sgl)
 605                 nvme_free_sgls(dev, req);
 606         else
 607                 nvme_free_prps(dev, req);
 608         mempool_free(iod->sg, dev->iod_mempool);
 609 }
 610
 611 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
 612 {
 613         int i;
 614         struct scatterlist *sg;
 615
 616         for_each_sg(sgl, sg, nents, i) {
 617                 dma_addr_t phys = sg_phys(sg);
 618                 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
 619                         "dma_address:%pad dma_length:%d\n",
 620                         i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
 621                         sg_dma_len(sg));
 622         }
 623 }
 624
 625 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
 626                 struct request *req, struct nvme_rw_command *cmnd)
 627 {
 628         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 629         struct dma_pool *pool;
 630         int length = blk_rq_payload_bytes(req);
 631         struct scatterlist *sg = iod->sg;
 632         int dma_len = sg_dma_len(sg);
 633         u64 dma_addr = sg_dma_address(sg);
 634         int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
 635         __le64 *prp_list;
 636         void **list = nvme_pci_iod_list(req);
 637         dma_addr_t prp_dma;
 638         int nprps, i;
 639
 640         length -= (NVME_CTRL_PAGE_SIZE - offset);
 641         if (length <= 0) {
 642                 iod->first_dma = 0;
 643                 goto done;
 644         }
 645
 646         dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
 647         if (dma_len) {
 648                 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
 649         } else {
 650                 sg = sg_next(sg);
 651                 dma_addr = sg_dma_address(sg);
 652                 dma_len = sg_dma_len(sg);
 653         }
 654
 655         if (length <= NVME_CTRL_PAGE_SIZE) {
 656                 iod->first_dma = dma_addr;
 657                 goto done;
 658         }
 659
 660         nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
 661         if (nprps <= (256 / 8)) {
 662                 pool = dev->prp_small_pool;
 663                 iod->npages = 0;
 664         } else {
 665                 pool = dev->prp_page_pool;
 666                 iod->npages = 1;
 667         }
 668
 669         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 670         if (!prp_list) {
 671                 iod->first_dma = dma_addr;
 672                 iod->npages = -1;
 673                 return BLK_STS_RESOURCE;
 674         }
 675         list[0] = prp_list;
 676         iod->first_dma = prp_dma;
 677         i = 0;
 678         for (;;) {
 679                 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
 680                         __le64 *old_prp_list = prp_list;
 681                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 682                         if (!prp_list)
 683                                 goto free_prps;
 684                         list[iod->npages++] = prp_list;
 685                         prp_list[0] = old_prp_list[i - 1];
 686                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 687                         i = 1;
 688                 }
 689                 prp_list[i++] = cpu_to_le64(dma_addr);
 690                 dma_len -= NVME_CTRL_PAGE_SIZE;
 691                 dma_addr += NVME_CTRL_PAGE_SIZE;
 692                 length -= NVME_CTRL_PAGE_SIZE;
 693                 if (length <= 0)
 694                         break;
 695                 if (dma_len > 0)
 696                         continue;
 697                 if (unlikely(dma_len < 0))
 698                         goto bad_sgl;
 699                 sg = sg_next(sg);
 700                 dma_addr = sg_dma_address(sg);
 701                 dma_len = sg_dma_len(sg);
 702         }
 703 done:
 704         cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 705         cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
 706         return BLK_STS_OK;
 707 free_prps:
 708         nvme_free_prps(dev, req);
 709         return BLK_STS_RESOURCE;
 710 bad_sgl:
 711         WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
 712                         "Invalid SGL for payload:%d nents:%d\n",
 713                         blk_rq_payload_bytes(req), iod->nents);
 714         return BLK_STS_IOERR;
 715 }
 716
 717 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
 718                 struct scatterlist *sg)
 719 {
 720         sge->addr = cpu_to_le64(sg_dma_address(sg));
 721         sge->length = cpu_to_le32(sg_dma_len(sg));
 722         sge->type = NVME_SGL_FMT_DATA_DESC << 4;
 723 }
 724
 725 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
 726                 dma_addr_t dma_addr, int entries)
 727 {
 728         sge->addr = cpu_to_le64(dma_addr);
 729         if (entries < SGES_PER_PAGE) {
 730                 sge->length = cpu_to_le32(entries * sizeof(*sge));
 731                 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
 732         } else {
 733                 sge->length = cpu_to_le32(PAGE_SIZE);
 734                 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
 735         }
 736 }
 737
 738 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
 739                 struct request *req, struct nvme_rw_command *cmd, int entries)
 740 {
 741         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 742         struct dma_pool *pool;
 743         struct nvme_sgl_desc *sg_list;
 744         struct scatterlist *sg = iod->sg;
 745         dma_addr_t sgl_dma;
 746         int i = 0;
 747
 748         /* setting the transfer type as SGL */
 749         cmd->flags = NVME_CMD_SGL_METABUF;
 750
 751         if (entries == 1) {
 752                 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
 753                 return BLK_STS_OK;
 754         }
 755
 756         if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
 757                 pool = dev->prp_small_pool;
 758                 iod->npages = 0;
 759         } else {
 760                 pool = dev->prp_page_pool;
 761                 iod->npages = 1;
 762         }
 763
 764         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 765         if (!sg_list) {
 766                 iod->npages = -1;
 767                 return BLK_STS_RESOURCE;
 768         }
 769
 770         nvme_pci_iod_list(req)[0] = sg_list;
 771         iod->first_dma = sgl_dma;
 772
 773         nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
 774
 775         do {
 776                 if (i == SGES_PER_PAGE) {
 777                         struct nvme_sgl_desc *old_sg_desc = sg_list;
 778                         struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
 779
 780                         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 781                         if (!sg_list)
 782                                 goto free_sgls;
 783
 784                         i = 0;
 785                         nvme_pci_iod_list(req)[iod->npages++] = sg_list;
 786                         sg_list[i++] = *link;
 787                         nvme_pci_sgl_set_seg(link, sgl_dma, entries);
 788                 }
 789
 790                 nvme_pci_sgl_set_data(&sg_list[i++], sg);
 791                 sg = sg_next(sg);
 792         } while (--entries > 0);
 793
 794         return BLK_STS_OK;
 795 free_sgls:
 796         nvme_free_sgls(dev, req);
 797         return BLK_STS_RESOURCE;
 798 }
 799
 800 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
 801                 struct request *req, struct nvme_rw_command *cmnd,
 802                 struct bio_vec *bv)
 803 {
 804         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 805         unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
 806         unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
 807
 808         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 809         if (dma_mapping_error(dev->dev, iod->first_dma))
 810                 return BLK_STS_RESOURCE;
 811         iod->dma_len = bv->bv_len;
 812
 813         cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
 814         if (bv->bv_len > first_prp_len)
 815                 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
 816         return BLK_STS_OK;
 817 }
 818
 819 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
 820                 struct request *req, struct nvme_rw_command *cmnd,
 821                 struct bio_vec *bv)
 822 {
 823         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 824
 825         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 826         if (dma_mapping_error(dev->dev, iod->first_dma))
 827                 return BLK_STS_RESOURCE;
 828         iod->dma_len = bv->bv_len;
 829
 830         cmnd->flags = NVME_CMD_SGL_METABUF;
 831         cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
 832         cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
 833         cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
 834         return BLK_STS_OK;
 835 }
 836
 837 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
 838                 struct nvme_command *cmnd)
 839 {
 840         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 841         blk_status_t ret = BLK_STS_RESOURCE;
 842         int nr_mapped;
 843
 844         if (blk_rq_nr_phys_segments(req) == 1) {
 845                 struct bio_vec bv = req_bvec(req);
 846
 847                 if (!is_pci_p2pdma_page(bv.bv_page)) {
 848                         if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
 849                                 return nvme_setup_prp_simple(dev, req,
 850                                                              &cmnd->rw, &bv);
 851
 852                         if (iod->nvmeq->qid && sgl_threshold &&
 853                             nvme_ctrl_sgl_supported(&dev->ctrl))
 854                                 return nvme_setup_sgl_simple(dev, req,
 855                                                              &cmnd->rw, &bv);
 856                 }
 857         }
 858
 859         iod->dma_len = 0;
 860         iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
 861         if (!iod->sg)
 862                 return BLK_STS_RESOURCE;
 863         sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
 864         iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
 865         if (!iod->nents)
 866                 goto out_free_sg;
 867
 868         if (is_pci_p2pdma_page(sg_page(iod->sg)))
 869                 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
 870                                 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
 871         else
 872                 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
 873                                              rq_dma_dir(req), DMA_ATTR_NO_WARN);
 874         if (!nr_mapped)
 875                 goto out_free_sg;
 876
 877         iod->use_sgl = nvme_pci_use_sgls(dev, req);
 878         if (iod->use_sgl)
 879                 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
 880         else
 881                 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
 882         if (ret != BLK_STS_OK)
 883                 goto out_unmap_sg;
 884         return BLK_STS_OK;
 885
 886 out_unmap_sg:
 887         nvme_unmap_sg(dev, req);
 888 out_free_sg:
 889         mempool_free(iod->sg, dev->iod_mempool);
 890         return ret;
 891 }
 892
 893 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
 894                 struct nvme_command *cmnd)
 895 {
 896         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 897
 898         iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
 899                         rq_dma_dir(req), 0);
 900         if (dma_mapping_error(dev->dev, iod->meta_dma))
 901                 return BLK_STS_IOERR;
 902         cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
 903         return BLK_STS_OK;
 904 }
 905
 906 /*
 907  * NOTE: ns is NULL when called on the admin queue.
 908  */
 909 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 910                          const struct blk_mq_queue_data *bd)
 911 {
 912         struct nvme_ns *ns = hctx->queue->queuedata;
 913         struct nvme_queue *nvmeq = hctx->driver_data;
 914         struct nvme_dev *dev = nvmeq->dev;
 915         struct request *req = bd->rq;
 916         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 917         struct nvme_command *cmnd = &iod->cmd;
 918         blk_status_t ret;
 919
 920         iod->aborted = 0;
 921         iod->npages = -1;
 922         iod->nents = 0;
 923
 924         /*
 925          * We should not need to do this, but we're still using this to
 926          * ensure we can drain requests on a dying queue.
 927          */
 928         if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
 929                 return BLK_STS_IOERR;
 930
 931         if (!nvme_check_ready(&dev->ctrl, req, true))
 932                 return nvme_fail_nonready_command(&dev->ctrl, req);
 933
 934         ret = nvme_setup_cmd(ns, req);
 935         if (ret)
 936                 return ret;
 937
 938         if (blk_rq_nr_phys_segments(req)) {
 939                 ret = nvme_map_data(dev, req, cmnd);
 940                 if (ret)
 941                         goto out_free_cmd;
 942         }
 943
 944         if (blk_integrity_rq(req)) {
 945                 ret = nvme_map_metadata(dev, req, cmnd);
 946                 if (ret)
 947                         goto out_unmap_data;
 948         }
 949
 950         blk_mq_start_request(req);
 951         nvme_submit_cmd(nvmeq, cmnd, bd->last);
 952         return BLK_STS_OK;
 953 out_unmap_data:
 954         nvme_unmap_data(dev, req);
 955 out_free_cmd:
 956         nvme_cleanup_cmd(req);
 957         return ret;
 958 }
 959
 960 static void nvme_pci_complete_rq(struct request *req)
 961 {
 962         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 963         struct nvme_dev *dev = iod->nvmeq->dev;
 964
 965         if (blk_integrity_rq(req))
 966                 dma_unmap_page(dev->dev, iod->meta_dma,
 967                                rq_integrity_vec(req)->bv_len, rq_data_dir(req));
 968         if (blk_rq_nr_phys_segments(req))
 969                 nvme_unmap_data(dev, req);
 970         nvme_complete_rq(req);
 971 }
 972
 973 /* We read the CQE phase first to check if the rest of the entry is valid */
 974 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
 975 {
 976         struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
 977
 978         return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
 979 }
 980
 981 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
 982 {
 983         u16 head = nvmeq->cq_head;
 984
 985         if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
 986                                               nvmeq->dbbuf_cq_ei))
 987                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 988 }
 989
 990 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
 991 {
 992         if (!nvmeq->qid)
 993                 return nvmeq->dev->admin_tagset.tags[0];
 994         return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
 995 }
 996
 997 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
 998 {
 999         struct nvme_completion *cqe = &nvmeq->cqes[idx];
1000         __u16 command_id = READ_ONCE(cqe->command_id);
1001         struct request *req;
1002
1003         /*
1004          * AEN requests are special as they don't time out and can
1005          * survive any kind of queue freeze and often don't respond to
1006          * aborts.  We don't even bother to allocate a struct request
1007          * for them but rather special case them here.
1008          */
1009         if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1010                 nvme_complete_async_event(&nvmeq->dev->ctrl,
1011                                 cqe->status, &cqe->result);
1012                 return;
1013         }
1014
1015         req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
1016         if (unlikely(!req)) {
1017                 dev_warn(nvmeq->dev->ctrl.device,
1018                         "invalid id %d completed on queue %d\n",
1019                         command_id, le16_to_cpu(cqe->sq_id));
1020                 return;
1021         }
1022
1023         trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1024         if (!nvme_try_complete_req(req, cqe->status, cqe->result))
1025                 nvme_pci_complete_rq(req);
1026 }
1027
1028 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1029 {
1030         u32 tmp = nvmeq->cq_head + 1;
1031
1032         if (tmp == nvmeq->q_depth) {
1033                 nvmeq->cq_head = 0;
1034                 nvmeq->cq_phase ^= 1;
1035         } else {
1036                 nvmeq->cq_head = tmp;
1037         }
1038 }
1039
1040 static inline int nvme_process_cq(struct nvme_queue *nvmeq)
1041 {
1042         int found = 0;
1043
1044         while (nvme_cqe_pending(nvmeq)) {
1045                 found++;
1046                 /*
1047                  * load-load control dependency between phase and the rest of
1048                  * the cqe requires a full read memory barrier
1049                  */
1050                 dma_rmb();
1051                 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
1052                 nvme_update_cq_head(nvmeq);
1053         }
1054
1055         if (found)
1056                 nvme_ring_cq_doorbell(nvmeq);
1057         return found;
1058 }
1059
1060 static irqreturn_t nvme_irq(int irq, void *data)
1061 {
1062         struct nvme_queue *nvmeq = data;
1063
1064         if (nvme_process_cq(nvmeq))
1065                 return IRQ_HANDLED;
1066         return IRQ_NONE;
1067 }
1068
1069 static irqreturn_t nvme_irq_check(int irq, void *data)
1070 {
1071         struct nvme_queue *nvmeq = data;
1072
1073         if (nvme_cqe_pending(nvmeq))
1074                 return IRQ_WAKE_THREAD;
1075         return IRQ_NONE;
1076 }
1077
1078 /*
1079  * Poll for completions for any interrupt driven queue
1080  * Can be called from any context.
1081  */
1082 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1083 {
1084         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1085
1086         WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1087
1088         disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1089         nvme_process_cq(nvmeq);
1090         enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1091 }
1092
1093 static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1094 {
1095         struct nvme_queue *nvmeq = hctx->driver_data;
1096         bool found;
1097
1098         if (!nvme_cqe_pending(nvmeq))
1099                 return 0;
1100
1101         spin_lock(&nvmeq->cq_poll_lock);
1102         found = nvme_process_cq(nvmeq);
1103         spin_unlock(&nvmeq->cq_poll_lock);
1104
1105         return found;
1106 }
1107
1108 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1109 {
1110         struct nvme_dev *dev = to_nvme_dev(ctrl);
1111         struct nvme_queue *nvmeq = &dev->queues[0];
1112         struct nvme_command c = { };
1113
1114         c.common.opcode = nvme_admin_async_event;
1115         c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1116         nvme_submit_cmd(nvmeq, &c, true);
1117 }
1118
1119 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1120 {
1121         struct nvme_command c = { };
1122
1123         c.delete_queue.opcode = opcode;
1124         c.delete_queue.qid = cpu_to_le16(id);
1125
1126         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1127 }
1128
1129 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1130                 struct nvme_queue *nvmeq, s16 vector)
1131 {
1132         struct nvme_command c = { };
1133         int flags = NVME_QUEUE_PHYS_CONTIG;
1134
1135         if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1136                 flags |= NVME_CQ_IRQ_ENABLED;
1137
1138         /*
1139          * Note: we (ab)use the fact that the prp fields survive if no data
1140          * is attached to the request.
1141          */
1142         c.create_cq.opcode = nvme_admin_create_cq;
1143         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1144         c.create_cq.cqid = cpu_to_le16(qid);
1145         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1146         c.create_cq.cq_flags = cpu_to_le16(flags);
1147         c.create_cq.irq_vector = cpu_to_le16(vector);
1148
1149         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1150 }
1151
1152 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1153                                                 struct nvme_queue *nvmeq)
1154 {
1155         struct nvme_ctrl *ctrl = &dev->ctrl;
1156         struct nvme_command c = { };
1157         int flags = NVME_QUEUE_PHYS_CONTIG;
1158
1159         /*
1160          * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1161          * set. Since URGENT priority is zeroes, it makes all queues
1162          * URGENT.
1163          */
1164         if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1165                 flags |= NVME_SQ_PRIO_MEDIUM;
1166
1167         /*
1168          * Note: we (ab)use the fact that the prp fields survive if no data
1169          * is attached to the request.
1170          */
1171         c.create_sq.opcode = nvme_admin_create_sq;
1172         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1173         c.create_sq.sqid = cpu_to_le16(qid);
1174         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1175         c.create_sq.sq_flags = cpu_to_le16(flags);
1176         c.create_sq.cqid = cpu_to_le16(qid);
1177
1178         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1179 }
1180
1181 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1182 {
1183         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1184 }
1185
1186 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1187 {
1188         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1189 }
1190
1191 static void abort_endio(struct request *req, blk_status_t error)
1192 {
1193         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1194         struct nvme_queue *nvmeq = iod->nvmeq;
1195
1196         dev_warn(nvmeq->dev->ctrl.device,
1197                  "Abort status: 0x%x", nvme_req(req)->status);
1198         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1199         blk_mq_free_request(req);
1200 }
1201
1202 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1203 {
1204         /* If true, indicates loss of adapter communication, possibly by a
1205          * NVMe Subsystem reset.
1206          */
1207         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1208
1209         /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1210         switch (dev->ctrl.state) {
1211         case NVME_CTRL_RESETTING:
1212         case NVME_CTRL_CONNECTING:
1213                 return false;
1214         default:
1215                 break;
1216         }
1217
1218         /* We shouldn't reset unless the controller is on fatal error state
1219          * _or_ if we lost the communication with it.
1220          */
1221         if (!(csts & NVME_CSTS_CFS) && !nssro)
1222                 return false;
1223
1224         return true;
1225 }
1226
1227 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1228 {
1229         /* Read a config register to help see what died. */
1230         u16 pci_status;
1231         int result;
1232
1233         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1234                                       &pci_status);
1235         if (result == PCIBIOS_SUCCESSFUL)
1236                 dev_warn(dev->ctrl.device,
1237                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1238                          csts, pci_status);
1239         else
1240                 dev_warn(dev->ctrl.device,
1241                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1242                          csts, result);
1243 }
1244
1245 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1246 {
1247         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1248         struct nvme_queue *nvmeq = iod->nvmeq;
1249         struct nvme_dev *dev = nvmeq->dev;
1250         struct request *abort_req;
1251         struct nvme_command cmd = { };
1252         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1253
1254         /* If PCI error recovery process is happening, we cannot reset or
1255          * the recovery mechanism will surely fail.
1256          */
1257         mb();
1258         if (pci_channel_offline(to_pci_dev(dev->dev)))
1259                 return BLK_EH_RESET_TIMER;
1260
1261         /*
1262          * Reset immediately if the controller is failed
1263          */
1264         if (nvme_should_reset(dev, csts)) {
1265                 nvme_warn_reset(dev, csts);
1266                 nvme_dev_disable(dev, false);
1267                 nvme_reset_ctrl(&dev->ctrl);
1268                 return BLK_EH_DONE;
1269         }
1270
1271         /*
1272          * Did we miss an interrupt?
1273          */
1274         if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1275                 nvme_poll(req->mq_hctx);
1276         else
1277                 nvme_poll_irqdisable(nvmeq);
1278
1279         if (blk_mq_request_completed(req)) {
1280                 dev_warn(dev->ctrl.device,
1281                          "I/O %d QID %d timeout, completion polled\n",
1282                          req->tag, nvmeq->qid);
1283                 return BLK_EH_DONE;
1284         }
1285
1286         /*
1287          * Shutdown immediately if controller times out while starting. The
1288          * reset work will see the pci device disabled when it gets the forced
1289          * cancellation error. All outstanding requests are completed on
1290          * shutdown, so we return BLK_EH_DONE.
1291          */
1292         switch (dev->ctrl.state) {
1293         case NVME_CTRL_CONNECTING:
1294                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1295                 fallthrough;
1296         case NVME_CTRL_DELETING:
1297                 dev_warn_ratelimited(dev->ctrl.device,
1298                          "I/O %d QID %d timeout, disable controller\n",
1299                          req->tag, nvmeq->qid);
1300                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1301                 nvme_dev_disable(dev, true);
1302                 return BLK_EH_DONE;
1303         case NVME_CTRL_RESETTING:
1304                 return BLK_EH_RESET_TIMER;
1305         default:
1306                 break;
1307         }
1308
1309         /*
1310          * Shutdown the controller immediately and schedule a reset if the
1311          * command was already aborted once before and still hasn't been
1312          * returned to the driver, or if this is the admin queue.
1313          */
1314         if (!nvmeq->qid || iod->aborted) {
1315                 dev_warn(dev->ctrl.device,
1316                          "I/O %d QID %d timeout, reset controller\n",
1317                          req->tag, nvmeq->qid);
1318                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1319                 nvme_dev_disable(dev, false);
1320                 nvme_reset_ctrl(&dev->ctrl);
1321
1322                 return BLK_EH_DONE;
1323         }
1324
1325         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1326                 atomic_inc(&dev->ctrl.abort_limit);
1327                 return BLK_EH_RESET_TIMER;
1328         }
1329         iod->aborted = 1;
1330
1331         cmd.abort.opcode = nvme_admin_abort_cmd;
1332         cmd.abort.cid = req->tag;
1333         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1334
1335         dev_warn(nvmeq->dev->ctrl.device,
1336                 "I/O %d QID %d timeout, aborting\n",
1337                  req->tag, nvmeq->qid);
1338
1339         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1340                         BLK_MQ_REQ_NOWAIT);
1341         if (IS_ERR(abort_req)) {
1342                 atomic_inc(&dev->ctrl.abort_limit);
1343                 return BLK_EH_RESET_TIMER;
1344         }
1345
1346         abort_req->end_io_data = NULL;
1347         blk_execute_rq_nowait(NULL, abort_req, 0, abort_endio);
1348
1349         /*
1350          * The aborted req will be completed on receiving the abort req.
1351          * We enable the timer again. If hit twice, it'll cause a device reset,
1352          * as the device then is in a faulty state.
1353          */
1354         return BLK_EH_RESET_TIMER;
1355 }
1356
1357 static void nvme_free_queue(struct nvme_queue *nvmeq)
1358 {
1359         dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1360                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1361         if (!nvmeq->sq_cmds)
1362                 return;
1363
1364         if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1365                 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1366                                 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1367         } else {
1368                 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1369                                 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1370         }
1371 }
1372
1373 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1374 {
1375         int i;
1376
1377         for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1378                 dev->ctrl.queue_count--;
1379                 nvme_free_queue(&dev->queues[i]);
1380         }
1381 }
1382
1383 /**
1384  * nvme_suspend_queue - put queue into suspended state
1385  * @nvmeq: queue to suspend
1386  */
1387 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1388 {
1389         if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1390                 return 1;
1391
1392         /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1393         mb();
1394
1395         nvmeq->dev->online_queues--;
1396         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1397                 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1398         if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1399                 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1400         return 0;
1401 }
1402
1403 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1404 {
1405         int i;
1406
1407         for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1408                 nvme_suspend_queue(&dev->queues[i]);
1409 }
1410
1411 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1412 {
1413         struct nvme_queue *nvmeq = &dev->queues[0];
1414
1415         if (shutdown)
1416                 nvme_shutdown_ctrl(&dev->ctrl);
1417         else
1418                 nvme_disable_ctrl(&dev->ctrl);
1419
1420         nvme_poll_irqdisable(nvmeq);
1421 }
1422
1423 /*
1424  * Called only on a device that has been disabled and after all other threads
1425  * that can check this device's completion queues have synced, except
1426  * nvme_poll(). This is the last chance for the driver to see a natural
1427  * completion before nvme_cancel_request() terminates all incomplete requests.
1428  */
1429 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1430 {
1431         int i;
1432
1433         for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1434                 spin_lock(&dev->queues[i].cq_poll_lock);
1435                 nvme_process_cq(&dev->queues[i]);
1436                 spin_unlock(&dev->queues[i].cq_poll_lock);
1437         }
1438 }
1439
1440 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1441                                 int entry_size)
1442 {
1443         int q_depth = dev->q_depth;
1444         unsigned q_size_aligned = roundup(q_depth * entry_size,
1445                                           NVME_CTRL_PAGE_SIZE);
1446
1447         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1448                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1449
1450                 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1451                 q_depth = div_u64(mem_per_q, entry_size);
1452
1453                 /*
1454                  * Ensure the reduced q_depth is above some threshold where it
1455                  * would be better to map queues in system memory with the
1456                  * original depth
1457                  */
1458                 if (q_depth < 64)
1459                         return -ENOMEM;
1460         }
1461
1462         return q_depth;
1463 }
1464
1465 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1466                                 int qid)
1467 {
1468         struct pci_dev *pdev = to_pci_dev(dev->dev);
1469
1470         if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1471                 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1472                 if (nvmeq->sq_cmds) {
1473                         nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1474                                                         nvmeq->sq_cmds);
1475                         if (nvmeq->sq_dma_addr) {
1476                                 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1477                                 return 0;
1478                         }
1479
1480                         pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1481                 }
1482         }
1483
1484         nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1485                                 &nvmeq->sq_dma_addr, GFP_KERNEL);
1486         if (!nvmeq->sq_cmds)
1487                 return -ENOMEM;
1488         return 0;
1489 }
1490
1491 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1492 {
1493         struct nvme_queue *nvmeq = &dev->queues[qid];
1494
1495         if (dev->ctrl.queue_count > qid)
1496                 return 0;
1497
1498         nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1499         nvmeq->q_depth = depth;
1500         nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1501                                          &nvmeq->cq_dma_addr, GFP_KERNEL);
1502         if (!nvmeq->cqes)
1503                 goto free_nvmeq;
1504
1505         if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1506                 goto free_cqdma;
1507
1508         nvmeq->dev = dev;
1509         spin_lock_init(&nvmeq->sq_lock);
1510         spin_lock_init(&nvmeq->cq_poll_lock);
1511         nvmeq->cq_head = 0;
1512         nvmeq->cq_phase = 1;
1513         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1514         nvmeq->qid = qid;
1515         dev->ctrl.queue_count++;
1516
1517         return 0;
1518
1519  free_cqdma:
1520         dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1521                           nvmeq->cq_dma_addr);
1522  free_nvmeq:
1523         return -ENOMEM;
1524 }
1525
1526 static int queue_request_irq(struct nvme_queue *nvmeq)
1527 {
1528         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1529         int nr = nvmeq->dev->ctrl.instance;
1530
1531         if (use_threaded_interrupts) {
1532                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1533                                 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1534         } else {
1535                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1536                                 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1537         }
1538 }
1539
1540 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1541 {
1542         struct nvme_dev *dev = nvmeq->dev;
1543
1544         nvmeq->sq_tail = 0;
1545         nvmeq->last_sq_tail = 0;
1546         nvmeq->cq_head = 0;
1547         nvmeq->cq_phase = 1;
1548         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1549         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1550         nvme_dbbuf_init(dev, nvmeq, qid);
1551         dev->online_queues++;
1552         wmb(); /* ensure the first interrupt sees the initialization */
1553 }
1554
1555 /*
1556  * Try getting shutdown_lock while setting up IO queues.
1557  */
1558 static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1559 {
1560         /*
1561          * Give up if the lock is being held by nvme_dev_disable.
1562          */
1563         if (!mutex_trylock(&dev->shutdown_lock))
1564                 return -ENODEV;
1565
1566         /*
1567          * Controller is in wrong state, fail early.
1568          */
1569         if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1570                 mutex_unlock(&dev->shutdown_lock);
1571                 return -ENODEV;
1572         }
1573
1574         return 0;
1575 }
1576
1577 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1578 {
1579         struct nvme_dev *dev = nvmeq->dev;
1580         int result;
1581         u16 vector = 0;
1582
1583         clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1584
1585         /*
1586          * A queue's vector matches the queue identifier unless the controller
1587          * has only one vector available.
1588          */
1589         if (!polled)
1590                 vector = dev->num_vecs == 1 ? 0 : qid;
1591         else
1592                 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1593
1594         result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1595         if (result)
1596                 return result;
1597
1598         result = adapter_alloc_sq(dev, qid, nvmeq);
1599         if (result < 0)
1600                 return result;
1601         if (result)
1602                 goto release_cq;
1603
1604         nvmeq->cq_vector = vector;
1605
1606         result = nvme_setup_io_queues_trylock(dev);
1607         if (result)
1608                 return result;
1609         nvme_init_queue(nvmeq, qid);
1610         if (!polled) {
1611                 result = queue_request_irq(nvmeq);
1612                 if (result < 0)
1613                         goto release_sq;
1614         }
1615
1616         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1617         mutex_unlock(&dev->shutdown_lock);
1618         return result;
1619
1620 release_sq:
1621         dev->online_queues--;
1622         mutex_unlock(&dev->shutdown_lock);
1623         adapter_delete_sq(dev, qid);
1624 release_cq:
1625         adapter_delete_cq(dev, qid);
1626         return result;
1627 }
1628
1629 static const struct blk_mq_ops nvme_mq_admin_ops = {
1630         .queue_rq       = nvme_queue_rq,
1631         .complete       = nvme_pci_complete_rq,
1632         .init_hctx      = nvme_admin_init_hctx,
1633         .init_request   = nvme_init_request,
1634         .timeout        = nvme_timeout,
1635 };
1636
1637 static const struct blk_mq_ops nvme_mq_ops = {
1638         .queue_rq       = nvme_queue_rq,
1639         .complete       = nvme_pci_complete_rq,
1640         .commit_rqs     = nvme_commit_rqs,
1641         .init_hctx      = nvme_init_hctx,
1642         .init_request   = nvme_init_request,
1643         .map_queues     = nvme_pci_map_queues,
1644         .timeout        = nvme_timeout,
1645         .poll           = nvme_poll,
1646 };
1647
1648 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1649 {
1650         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1651                 /*
1652                  * If the controller was reset during removal, it's possible
1653                  * user requests may be waiting on a stopped queue. Start the
1654                  * queue to flush these to completion.
1655                  */
1656                 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1657                 blk_cleanup_queue(dev->ctrl.admin_q);
1658                 blk_mq_free_tag_set(&dev->admin_tagset);
1659         }
1660 }
1661
1662 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1663 {
1664         if (!dev->ctrl.admin_q) {
1665                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1666                 dev->admin_tagset.nr_hw_queues = 1;
1667
1668                 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1669                 dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT;
1670                 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
1671                 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1672                 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1673                 dev->admin_tagset.driver_data = dev;
1674
1675                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1676                         return -ENOMEM;
1677                 dev->ctrl.admin_tagset = &dev->admin_tagset;
1678
1679                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1680                 if (IS_ERR(dev->ctrl.admin_q)) {
1681                         blk_mq_free_tag_set(&dev->admin_tagset);
1682                         return -ENOMEM;
1683                 }
1684                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1685                         nvme_dev_remove_admin(dev);
1686                         dev->ctrl.admin_q = NULL;
1687                         return -ENODEV;
1688                 }
1689         } else
1690                 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1691
1692         return 0;
1693 }
1694
1695 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1696 {
1697         return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1698 }
1699
1700 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1701 {
1702         struct pci_dev *pdev = to_pci_dev(dev->dev);
1703
1704         if (size <= dev->bar_mapped_size)
1705                 return 0;
1706         if (size > pci_resource_len(pdev, 0))
1707                 return -ENOMEM;
1708         if (dev->bar)
1709                 iounmap(dev->bar);
1710         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1711         if (!dev->bar) {
1712                 dev->bar_mapped_size = 0;
1713                 return -ENOMEM;
1714         }
1715         dev->bar_mapped_size = size;
1716         dev->dbs = dev->bar + NVME_REG_DBS;
1717
1718         return 0;
1719 }
1720
1721 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1722 {
1723         int result;
1724         u32 aqa;
1725         struct nvme_queue *nvmeq;
1726
1727         result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1728         if (result < 0)
1729                 return result;
1730
1731         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1732                                 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1733
1734         if (dev->subsystem &&
1735             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1736                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1737
1738         result = nvme_disable_ctrl(&dev->ctrl);
1739         if (result < 0)
1740                 return result;
1741
1742         result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1743         if (result)
1744                 return result;
1745
1746         dev->ctrl.numa_node = dev_to_node(dev->dev);
1747
1748         nvmeq = &dev->queues[0];
1749         aqa = nvmeq->q_depth - 1;
1750         aqa |= aqa << 16;
1751
1752         writel(aqa, dev->bar + NVME_REG_AQA);
1753         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1754         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1755
1756         result = nvme_enable_ctrl(&dev->ctrl);
1757         if (result)
1758                 return result;
1759
1760         nvmeq->cq_vector = 0;
1761         nvme_init_queue(nvmeq, 0);
1762         result = queue_request_irq(nvmeq);
1763         if (result) {
1764                 dev->online_queues--;
1765                 return result;
1766         }
1767
1768         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1769         return result;
1770 }
1771
1772 static int nvme_create_io_queues(struct nvme_dev *dev)
1773 {
1774         unsigned i, max, rw_queues;
1775         int ret = 0;
1776
1777         for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1778                 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1779                         ret = -ENOMEM;
1780                         break;
1781                 }
1782         }
1783
1784         max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1785         if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1786                 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1787                                 dev->io_queues[HCTX_TYPE_READ];
1788         } else {
1789                 rw_queues = max;
1790         }
1791
1792         for (i = dev->online_queues; i <= max; i++) {
1793                 bool polled = i > rw_queues;
1794
1795                 ret = nvme_create_queue(&dev->queues[i], i, polled);
1796                 if (ret)
1797                         break;
1798         }
1799
1800         /*
1801          * Ignore failing Create SQ/CQ commands, we can continue with less
1802          * than the desired amount of queues, and even a controller without
1803          * I/O queues can still be used to issue admin commands.  This might
1804          * be useful to upgrade a buggy firmware for example.
1805          */
1806         return ret >= 0 ? 0 : ret;
1807 }
1808
1809 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1810 {
1811         u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1812
1813         return 1ULL << (12 + 4 * szu);
1814 }
1815
1816 static u32 nvme_cmb_size(struct nvme_dev *dev)
1817 {
1818         return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1819 }
1820
1821 static void nvme_map_cmb(struct nvme_dev *dev)
1822 {
1823         u64 size, offset;
1824         resource_size_t bar_size;
1825         struct pci_dev *pdev = to_pci_dev(dev->dev);
1826         int bar;
1827
1828         if (dev->cmb_size)
1829                 return;
1830
1831         if (NVME_CAP_CMBS(dev->ctrl.cap))
1832                 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1833
1834         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1835         if (!dev->cmbsz)
1836                 return;
1837         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1838
1839         size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1840         offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1841         bar = NVME_CMB_BIR(dev->cmbloc);
1842         bar_size = pci_resource_len(pdev, bar);
1843
1844         if (offset > bar_size)
1845                 return;
1846
1847         /*
1848          * Tell the controller about the host side address mapping the CMB,
1849          * and enable CMB decoding for the NVMe 1.4+ scheme:
1850          */
1851         if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1852                 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1853                              (pci_bus_address(pdev, bar) + offset),
1854                              dev->bar + NVME_REG_CMBMSC);
1855         }
1856
1857         /*
1858          * Controllers may support a CMB size larger than their BAR,
1859          * for example, due to being behind a bridge. Reduce the CMB to
1860          * the reported size of the BAR
1861          */
1862         if (size > bar_size - offset)
1863                 size = bar_size - offset;
1864
1865         if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1866                 dev_warn(dev->ctrl.device,
1867                          "failed to register the CMB\n");
1868                 return;
1869         }
1870
1871         dev->cmb_size = size;
1872         dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1873
1874         if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1875                         (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1876                 pci_p2pmem_publish(pdev, true);
1877 }
1878
1879 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1880 {
1881         u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1882         u64 dma_addr = dev->host_mem_descs_dma;
1883         struct nvme_command c = { };
1884         int ret;
1885
1886         c.features.opcode       = nvme_admin_set_features;
1887         c.features.fid          = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1888         c.features.dword11      = cpu_to_le32(bits);
1889         c.features.dword12      = cpu_to_le32(host_mem_size);
1890         c.features.dword13      = cpu_to_le32(lower_32_bits(dma_addr));
1891         c.features.dword14      = cpu_to_le32(upper_32_bits(dma_addr));
1892         c.features.dword15      = cpu_to_le32(dev->nr_host_mem_descs);
1893
1894         ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1895         if (ret) {
1896                 dev_warn(dev->ctrl.device,
1897                          "failed to set host mem (err %d, flags %#x).\n",
1898                          ret, bits);
1899         }
1900         return ret;
1901 }
1902
1903 static void nvme_free_host_mem(struct nvme_dev *dev)
1904 {
1905         int i;
1906
1907         for (i = 0; i < dev->nr_host_mem_descs; i++) {
1908                 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1909                 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
1910
1911                 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1912                                le64_to_cpu(desc->addr),
1913                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1914         }
1915
1916         kfree(dev->host_mem_desc_bufs);
1917         dev->host_mem_desc_bufs = NULL;
1918         dma_free_coherent(dev->dev,
1919                         dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1920                         dev->host_mem_descs, dev->host_mem_descs_dma);
1921         dev->host_mem_descs = NULL;
1922         dev->nr_host_mem_descs = 0;
1923 }
1924
1925 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1926                 u32 chunk_size)
1927 {
1928         struct nvme_host_mem_buf_desc *descs;
1929         u32 max_entries, len;
1930         dma_addr_t descs_dma;
1931         int i = 0;
1932         void **bufs;
1933         u64 size, tmp;
1934
1935         tmp = (preferred + chunk_size - 1);
1936         do_div(tmp, chunk_size);
1937         max_entries = tmp;
1938
1939         if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1940                 max_entries = dev->ctrl.hmmaxd;
1941
1942         descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1943                                    &descs_dma, GFP_KERNEL);
1944         if (!descs)
1945                 goto out;
1946
1947         bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1948         if (!bufs)
1949                 goto out_free_descs;
1950
1951         for (size = 0; size < preferred && i < max_entries; size += len) {
1952                 dma_addr_t dma_addr;
1953
1954                 len = min_t(u64, chunk_size, preferred - size);
1955                 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1956                                 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1957                 if (!bufs[i])
1958                         break;
1959
1960                 descs[i].addr = cpu_to_le64(dma_addr);
1961                 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
1962                 i++;
1963         }
1964
1965         if (!size)
1966                 goto out_free_bufs;
1967
1968         dev->nr_host_mem_descs = i;
1969         dev->host_mem_size = size;
1970         dev->host_mem_descs = descs;
1971         dev->host_mem_descs_dma = descs_dma;
1972         dev->host_mem_desc_bufs = bufs;
1973         return 0;
1974
1975 out_free_bufs:
1976         while (--i >= 0) {
1977                 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
1978
1979                 dma_free_attrs(dev->dev, size, bufs[i],
1980                                le64_to_cpu(descs[i].addr),
1981                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1982         }
1983
1984         kfree(bufs);
1985 out_free_descs:
1986         dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1987                         descs_dma);
1988 out:
1989         dev->host_mem_descs = NULL;
1990         return -ENOMEM;
1991 }
1992
1993 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1994 {
1995         u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1996         u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1997         u64 chunk_size;
1998
1999         /* start big and work our way down */
2000         for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2001                 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2002                         if (!min || dev->host_mem_size >= min)
2003                                 return 0;
2004                         nvme_free_host_mem(dev);
2005                 }
2006         }
2007
2008         return -ENOMEM;
2009 }
2010
2011 static int nvme_setup_host_mem(struct nvme_dev *dev)
2012 {
2013         u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2014         u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2015         u64 min = (u64)dev->ctrl.hmmin * 4096;
2016         u32 enable_bits = NVME_HOST_MEM_ENABLE;
2017         int ret;
2018
2019         preferred = min(preferred, max);
2020         if (min > max) {
2021                 dev_warn(dev->ctrl.device,
2022                         "min host memory (%lld MiB) above limit (%d MiB).\n",
2023                         min >> ilog2(SZ_1M), max_host_mem_size_mb);
2024                 nvme_free_host_mem(dev);
2025                 return 0;
2026         }
2027
2028         /*
2029          * If we already have a buffer allocated check if we can reuse it.
2030          */
2031         if (dev->host_mem_descs) {
2032                 if (dev->host_mem_size >= min)
2033                         enable_bits |= NVME_HOST_MEM_RETURN;
2034                 else
2035                         nvme_free_host_mem(dev);
2036         }
2037
2038         if (!dev->host_mem_descs) {
2039                 if (nvme_alloc_host_mem(dev, min, preferred)) {
2040                         dev_warn(dev->ctrl.device,
2041                                 "failed to allocate host memory buffer.\n");
2042                         return 0; /* controller must work without HMB */
2043                 }
2044
2045                 dev_info(dev->ctrl.device,
2046                         "allocated %lld MiB host memory buffer.\n",
2047                         dev->host_mem_size >> ilog2(SZ_1M));
2048         }
2049
2050         ret = nvme_set_host_mem(dev, enable_bits);
2051         if (ret)
2052                 nvme_free_host_mem(dev);
2053         return ret;
2054 }
2055
2056 static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2057                 char *buf)
2058 {
2059         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2060
2061         return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz  : x%08x\n",
2062                        ndev->cmbloc, ndev->cmbsz);
2063 }
2064 static DEVICE_ATTR_RO(cmb);
2065
2066 static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2067                 struct attribute *a, int n)
2068 {
2069         struct nvme_ctrl *ctrl =
2070                 dev_get_drvdata(container_of(kobj, struct device, kobj));
2071         struct nvme_dev *dev = to_nvme_dev(ctrl);
2072
2073         if (a == &dev_attr_cmb.attr && !dev->cmbsz)
2074                 return 0;
2075         return a->mode;
2076 }
2077
2078 static struct attribute *nvme_pci_attrs[] = {
2079         &dev_attr_cmb.attr,
2080         NULL,
2081 };
2082
2083 static const struct attribute_group nvme_pci_attr_group = {
2084         .attrs          = nvme_pci_attrs,
2085         .is_visible     = nvme_pci_attrs_are_visible,
2086 };
2087
2088 /*
2089  * nirqs is the number of interrupts available for write and read
2090  * queues. The core already reserved an interrupt for the admin queue.
2091  */
2092 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2093 {
2094         struct nvme_dev *dev = affd->priv;
2095         unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2096
2097         /*
2098          * If there is no interrupt available for queues, ensure that
2099          * the default queue is set to 1. The affinity set size is
2100          * also set to one, but the irq core ignores it for this case.
2101          *
2102          * If only one interrupt is available or 'write_queue' == 0, combine
2103          * write and read queues.
2104          *
2105          * If 'write_queues' > 0, ensure it leaves room for at least one read
2106          * queue.
2107          */
2108         if (!nrirqs) {
2109                 nrirqs = 1;
2110                 nr_read_queues = 0;
2111         } else if (nrirqs == 1 || !nr_write_queues) {
2112                 nr_read_queues = 0;
2113         } else if (nr_write_queues >= nrirqs) {
2114                 nr_read_queues = 1;
2115         } else {
2116                 nr_read_queues = nrirqs - nr_write_queues;
2117         }
2118
2119         dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2120         affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2121         dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2122         affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2123         affd->nr_sets = nr_read_queues ? 2 : 1;
2124 }
2125
2126 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2127 {
2128         struct pci_dev *pdev = to_pci_dev(dev->dev);
2129         struct irq_affinity affd = {
2130                 .pre_vectors    = 1,
2131                 .calc_sets      = nvme_calc_irq_sets,
2132                 .priv           = dev,
2133         };
2134         unsigned int irq_queues, poll_queues;
2135
2136         /*
2137          * Poll queues don't need interrupts, but we need at least one I/O queue
2138          * left over for non-polled I/O.
2139          */
2140         poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2141         dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2142
2143         /*
2144          * Initialize for the single interrupt case, will be updated in
2145          * nvme_calc_irq_sets().
2146          */
2147         dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2148         dev->io_queues[HCTX_TYPE_READ] = 0;
2149
2150         /*
2151          * We need interrupts for the admin queue and each non-polled I/O queue,
2152          * but some Apple controllers require all queues to use the first
2153          * vector.
2154          */
2155         irq_queues = 1;
2156         if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2157                 irq_queues += (nr_io_queues - poll_queues);
2158         return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2159                               PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2160 }
2161
2162 static void nvme_disable_io_queues(struct nvme_dev *dev)
2163 {
2164         if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2165                 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2166 }
2167
2168 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2169 {
2170         /*
2171          * If tags are shared with admin queue (Apple bug), then
2172          * make sure we only use one IO queue.
2173          */
2174         if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2175                 return 1;
2176         return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2177 }
2178
2179 static int nvme_setup_io_queues(struct nvme_dev *dev)
2180 {
2181         struct nvme_queue *adminq = &dev->queues[0];
2182         struct pci_dev *pdev = to_pci_dev(dev->dev);
2183         unsigned int nr_io_queues;
2184         unsigned long size;
2185         int result;
2186
2187         /*
2188          * Sample the module parameters once at reset time so that we have
2189          * stable values to work with.
2190          */
2191         dev->nr_write_queues = write_queues;
2192         dev->nr_poll_queues = poll_queues;
2193
2194         nr_io_queues = dev->nr_allocated_queues - 1;
2195         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2196         if (result < 0)
2197                 return result;
2198
2199         if (nr_io_queues == 0)
2200                 return 0;
2201
2202         /*
2203          * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2204          * from set to unset. If there is a window to it is truely freed,
2205          * pci_free_irq_vectors() jumping into this window will crash.
2206          * And take lock to avoid racing with pci_free_irq_vectors() in
2207          * nvme_dev_disable() path.
2208          */
2209         result = nvme_setup_io_queues_trylock(dev);
2210         if (result)
2211                 return result;
2212         if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2213                 pci_free_irq(pdev, 0, adminq);
2214
2215         if (dev->cmb_use_sqes) {
2216                 result = nvme_cmb_qdepth(dev, nr_io_queues,
2217                                 sizeof(struct nvme_command));
2218                 if (result > 0)
2219                         dev->q_depth = result;
2220                 else
2221                         dev->cmb_use_sqes = false;
2222         }
2223
2224         do {
2225                 size = db_bar_size(dev, nr_io_queues);
2226                 result = nvme_remap_bar(dev, size);
2227                 if (!result)
2228                         break;
2229                 if (!--nr_io_queues) {
2230                         result = -ENOMEM;
2231                         goto out_unlock;
2232                 }
2233         } while (1);
2234         adminq->q_db = dev->dbs;
2235
2236  retry:
2237         /* Deregister the admin queue's interrupt */
2238         if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2239                 pci_free_irq(pdev, 0, adminq);
2240
2241         /*
2242          * If we enable msix early due to not intx, disable it again before
2243          * setting up the full range we need.
2244          */
2245         pci_free_irq_vectors(pdev);
2246
2247         result = nvme_setup_irqs(dev, nr_io_queues);
2248         if (result <= 0) {
2249                 result = -EIO;
2250                 goto out_unlock;
2251         }
2252
2253         dev->num_vecs = result;
2254         result = max(result - 1, 1);
2255         dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2256
2257         /*
2258          * Should investigate if there's a performance win from allocating
2259          * more queues than interrupt vectors; it might allow the submission
2260          * path to scale better, even if the receive path is limited by the
2261          * number of interrupts.
2262          */
2263         result = queue_request_irq(adminq);
2264         if (result)
2265                 goto out_unlock;
2266         set_bit(NVMEQ_ENABLED, &adminq->flags);
2267         mutex_unlock(&dev->shutdown_lock);
2268
2269         result = nvme_create_io_queues(dev);
2270         if (result || dev->online_queues < 2)
2271                 return result;
2272
2273         if (dev->online_queues - 1 < dev->max_qid) {
2274                 nr_io_queues = dev->online_queues - 1;
2275                 nvme_disable_io_queues(dev);
2276                 result = nvme_setup_io_queues_trylock(dev);
2277                 if (result)
2278                         return result;
2279                 nvme_suspend_io_queues(dev);
2280                 goto retry;
2281         }
2282         dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2283                                         dev->io_queues[HCTX_TYPE_DEFAULT],
2284                                         dev->io_queues[HCTX_TYPE_READ],
2285                                         dev->io_queues[HCTX_TYPE_POLL]);
2286         return 0;
2287 out_unlock:
2288         mutex_unlock(&dev->shutdown_lock);
2289         return result;
2290 }
2291
2292 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2293 {
2294         struct nvme_queue *nvmeq = req->end_io_data;
2295
2296         blk_mq_free_request(req);
2297         complete(&nvmeq->delete_done);
2298 }
2299
2300 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2301 {
2302         struct nvme_queue *nvmeq = req->end_io_data;
2303
2304         if (error)
2305                 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2306
2307         nvme_del_queue_end(req, error);
2308 }
2309
2310 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2311 {
2312         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2313         struct request *req;
2314         struct nvme_command cmd = { };
2315
2316         cmd.delete_queue.opcode = opcode;
2317         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2318
2319         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
2320         if (IS_ERR(req))
2321                 return PTR_ERR(req);
2322
2323         req->end_io_data = nvmeq;
2324
2325         init_completion(&nvmeq->delete_done);
2326         blk_execute_rq_nowait(NULL, req, false,
2327                         opcode == nvme_admin_delete_cq ?
2328                                 nvme_del_cq_end : nvme_del_queue_end);
2329         return 0;
2330 }
2331
2332 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2333 {
2334         int nr_queues = dev->online_queues - 1, sent = 0;
2335         unsigned long timeout;
2336
2337  retry:
2338         timeout = NVME_ADMIN_TIMEOUT;
2339         while (nr_queues > 0) {
2340                 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2341                         break;
2342                 nr_queues--;
2343                 sent++;
2344         }
2345         while (sent) {
2346                 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2347
2348                 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2349                                 timeout);
2350                 if (timeout == 0)
2351                         return false;
2352
2353                 sent--;
2354                 if (nr_queues)
2355                         goto retry;
2356         }
2357         return true;
2358 }
2359
2360 static void nvme_dev_add(struct nvme_dev *dev)
2361 {
2362         int ret;
2363
2364         if (!dev->ctrl.tagset) {
2365                 dev->tagset.ops = &nvme_mq_ops;
2366                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2367                 dev->tagset.nr_maps = 2; /* default + read */
2368                 if (dev->io_queues[HCTX_TYPE_POLL])
2369                         dev->tagset.nr_maps++;
2370                 dev->tagset.timeout = NVME_IO_TIMEOUT;
2371                 dev->tagset.numa_node = dev->ctrl.numa_node;
2372                 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2373                                                 BLK_MQ_MAX_DEPTH) - 1;
2374                 dev->tagset.cmd_size = sizeof(struct nvme_iod);
2375                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2376                 dev->tagset.driver_data = dev;
2377
2378                 /*
2379                  * Some Apple controllers requires tags to be unique
2380                  * across admin and IO queue, so reserve the first 32
2381                  * tags of the IO queue.
2382                  */
2383                 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2384                         dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2385
2386                 ret = blk_mq_alloc_tag_set(&dev->tagset);
2387                 if (ret) {
2388                         dev_warn(dev->ctrl.device,
2389                                 "IO queues tagset allocation failed %d\n", ret);
2390                         return;
2391                 }
2392                 dev->ctrl.tagset = &dev->tagset;
2393         } else {
2394                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2395
2396                 /* Free previously allocated queues that are no longer usable */
2397                 nvme_free_queues(dev, dev->online_queues);
2398         }
2399
2400         nvme_dbbuf_set(dev);
2401 }
2402
2403 static int nvme_pci_enable(struct nvme_dev *dev)
2404 {
2405         int result = -ENOMEM;
2406         struct pci_dev *pdev = to_pci_dev(dev->dev);
2407         int dma_address_bits = 64;
2408
2409         if (pci_enable_device_mem(pdev))
2410                 return result;
2411
2412         pci_set_master(pdev);
2413
2414         if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2415                 dma_address_bits = 48;
2416         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
2417                 goto disable;
2418
2419         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2420                 result = -ENODEV;
2421                 goto disable;
2422         }
2423
2424         /*
2425          * Some devices and/or platforms don't advertise or work with INTx
2426          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2427          * adjust this later.
2428          */
2429         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2430         if (result < 0)
2431                 return result;
2432
2433         dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2434
2435         dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2436                                 io_queue_depth);
2437         dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2438         dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2439         dev->dbs = dev->bar + 4096;
2440
2441         /*
2442          * Some Apple controllers require a non-standard SQE size.
2443          * Interestingly they also seem to ignore the CC:IOSQES register
2444          * so we don't bother updating it here.
2445          */
2446         if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2447                 dev->io_sqes = 7;
2448         else
2449                 dev->io_sqes = NVME_NVM_IOSQES;
2450
2451         /*
2452          * Temporary fix for the Apple controller found in the MacBook8,1 and
2453          * some MacBook7,1 to avoid controller resets and data loss.
2454          */
2455         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2456                 dev->q_depth = 2;
2457                 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2458                         "set queue depth=%u to work around controller resets\n",
2459                         dev->q_depth);
2460         } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2461                    (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2462                    NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2463                 dev->q_depth = 64;
2464                 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2465                         "set queue depth=%u\n", dev->q_depth);
2466         }
2467
2468         /*
2469          * Controllers with the shared tags quirk need the IO queue to be
2470          * big enough so that we get 32 tags for the admin queue
2471          */
2472         if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2473             (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2474                 dev->q_depth = NVME_AQ_DEPTH + 2;
2475                 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2476                          dev->q_depth);
2477         }
2478
2479
2480         nvme_map_cmb(dev);
2481
2482         pci_enable_pcie_error_reporting(pdev);
2483         pci_save_state(pdev);
2484         return 0;
2485
2486  disable:
2487         pci_disable_device(pdev);
2488         return result;
2489 }
2490
2491 static void nvme_dev_unmap(struct nvme_dev *dev)
2492 {
2493         if (dev->bar)
2494                 iounmap(dev->bar);
2495         pci_release_mem_regions(to_pci_dev(dev->dev));
2496 }
2497
2498 static void nvme_pci_disable(struct nvme_dev *dev)
2499 {
2500         struct pci_dev *pdev = to_pci_dev(dev->dev);
2501
2502         pci_free_irq_vectors(pdev);
2503
2504         if (pci_is_enabled(pdev)) {
2505                 pci_disable_pcie_error_reporting(pdev);
2506                 pci_disable_device(pdev);
2507         }
2508 }
2509
2510 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2511 {
2512         bool dead = true, freeze = false;
2513         struct pci_dev *pdev = to_pci_dev(dev->dev);
2514
2515         mutex_lock(&dev->shutdown_lock);
2516         if (pci_is_enabled(pdev)) {
2517                 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2518
2519                 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2520                     dev->ctrl.state == NVME_CTRL_RESETTING) {
2521                         freeze = true;
2522                         nvme_start_freeze(&dev->ctrl);
2523                 }
2524                 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2525                         pdev->error_state  != pci_channel_io_normal);
2526         }
2527
2528         /*
2529          * Give the controller a chance to complete all entered requests if
2530          * doing a safe shutdown.
2531          */
2532         if (!dead && shutdown && freeze)
2533                 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2534
2535         nvme_stop_queues(&dev->ctrl);
2536
2537         if (!dead && dev->ctrl.queue_count > 0) {
2538                 nvme_disable_io_queues(dev);
2539                 nvme_disable_admin_queue(dev, shutdown);
2540         }
2541         nvme_suspend_io_queues(dev);
2542         nvme_suspend_queue(&dev->queues[0]);
2543         nvme_pci_disable(dev);
2544         nvme_reap_pending_cqes(dev);
2545
2546         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2547         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2548         blk_mq_tagset_wait_completed_request(&dev->tagset);
2549         blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
2550
2551         /*
2552          * The driver will not be starting up queues again if shutting down so
2553          * must flush all entered requests to their failed completion to avoid
2554          * deadlocking blk-mq hot-cpu notifier.
2555          */
2556         if (shutdown) {
2557                 nvme_start_queues(&dev->ctrl);
2558                 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2559                         blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2560         }
2561         mutex_unlock(&dev->shutdown_lock);
2562 }
2563
2564 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2565 {
2566         if (!nvme_wait_reset(&dev->ctrl))
2567                 return -EBUSY;
2568         nvme_dev_disable(dev, shutdown);
2569         return 0;
2570 }
2571
2572 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2573 {
2574         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2575                                                 NVME_CTRL_PAGE_SIZE,
2576                                                 NVME_CTRL_PAGE_SIZE, 0);
2577         if (!dev->prp_page_pool)
2578                 return -ENOMEM;
2579
2580         /* Optimisation for I/Os between 4k and 128k */
2581         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2582                                                 256, 256, 0);
2583         if (!dev->prp_small_pool) {
2584                 dma_pool_destroy(dev->prp_page_pool);
2585                 return -ENOMEM;
2586         }
2587         return 0;
2588 }
2589
2590 static void nvme_release_prp_pools(struct nvme_dev *dev)
2591 {
2592         dma_pool_destroy(dev->prp_page_pool);
2593         dma_pool_destroy(dev->prp_small_pool);
2594 }
2595
2596 static void nvme_free_tagset(struct nvme_dev *dev)
2597 {
2598         if (dev->tagset.tags)
2599                 blk_mq_free_tag_set(&dev->tagset);
2600         dev->ctrl.tagset = NULL;
2601 }
2602
2603 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2604 {
2605         struct nvme_dev *dev = to_nvme_dev(ctrl);
2606
2607         nvme_dbbuf_dma_free(dev);
2608         nvme_free_tagset(dev);
2609         if (dev->ctrl.admin_q)
2610                 blk_put_queue(dev->ctrl.admin_q);
2611         free_opal_dev(dev->ctrl.opal_dev);
2612         mempool_destroy(dev->iod_mempool);
2613         put_device(dev->dev);
2614         kfree(dev->queues);
2615         kfree(dev);
2616 }
2617
2618 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2619 {
2620         /*
2621          * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2622          * may be holding this pci_dev's device lock.
2623          */
2624         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2625         nvme_get_ctrl(&dev->ctrl);
2626         nvme_dev_disable(dev, false);
2627         nvme_kill_queues(&dev->ctrl);
2628         if (!queue_work(nvme_wq, &dev->remove_work))
2629                 nvme_put_ctrl(&dev->ctrl);
2630 }
2631
2632 static void nvme_reset_work(struct work_struct *work)
2633 {
2634         struct nvme_dev *dev =
2635                 container_of(work, struct nvme_dev, ctrl.reset_work);
2636         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2637         int result;
2638
2639         if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2640                 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2641                          dev->ctrl.state);
2642                 result = -ENODEV;
2643                 goto out;
2644         }
2645
2646         /*
2647          * If we're called to reset a live controller first shut it down before
2648          * moving on.
2649          */
2650         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2651                 nvme_dev_disable(dev, false);
2652         nvme_sync_queues(&dev->ctrl);
2653
2654         mutex_lock(&dev->shutdown_lock);
2655         result = nvme_pci_enable(dev);
2656         if (result)
2657                 goto out_unlock;
2658
2659         result = nvme_pci_configure_admin_queue(dev);
2660         if (result)
2661                 goto out_unlock;
2662
2663         result = nvme_alloc_admin_tags(dev);
2664         if (result)
2665                 goto out_unlock;
2666
2667         /*
2668          * Limit the max command size to prevent iod->sg allocations going
2669          * over a single page.
2670          */
2671         dev->ctrl.max_hw_sectors = min_t(u32,
2672                 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2673         dev->ctrl.max_segments = NVME_MAX_SEGS;
2674
2675         /*
2676          * Don't limit the IOMMU merged segment size.
2677          */
2678         dma_set_max_seg_size(dev->dev, 0xffffffff);
2679         dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
2680
2681         mutex_unlock(&dev->shutdown_lock);
2682
2683         /*
2684          * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2685          * initializing procedure here.
2686          */
2687         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2688                 dev_warn(dev->ctrl.device,
2689                         "failed to mark controller CONNECTING\n");
2690                 result = -EBUSY;
2691                 goto out;
2692         }
2693
2694         /*
2695          * We do not support an SGL for metadata (yet), so we are limited to a
2696          * single integrity segment for the separate metadata pointer.
2697          */
2698         dev->ctrl.max_integrity_segments = 1;
2699
2700         result = nvme_init_ctrl_finish(&dev->ctrl);
2701         if (result)
2702                 goto out;
2703
2704         if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2705                 if (!dev->ctrl.opal_dev)
2706                         dev->ctrl.opal_dev =
2707                                 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2708                 else if (was_suspend)
2709                         opal_unlock_from_suspend(dev->ctrl.opal_dev);
2710         } else {
2711                 free_opal_dev(dev->ctrl.opal_dev);
2712                 dev->ctrl.opal_dev = NULL;
2713         }
2714
2715         if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2716                 result = nvme_dbbuf_dma_alloc(dev);
2717                 if (result)
2718                         dev_warn(dev->dev,
2719                                  "unable to allocate dma for dbbuf\n");
2720         }
2721
2722         if (dev->ctrl.hmpre) {
2723                 result = nvme_setup_host_mem(dev);
2724                 if (result < 0)
2725                         goto out;
2726         }
2727
2728         result = nvme_setup_io_queues(dev);
2729         if (result)
2730                 goto out;
2731
2732         /*
2733          * Keep the controller around but remove all namespaces if we don't have
2734          * any working I/O queue.
2735          */
2736         if (dev->online_queues < 2) {
2737                 dev_warn(dev->ctrl.device, "IO queues not created\n");
2738                 nvme_kill_queues(&dev->ctrl);
2739                 nvme_remove_namespaces(&dev->ctrl);
2740                 nvme_free_tagset(dev);
2741         } else {
2742                 nvme_start_queues(&dev->ctrl);
2743                 nvme_wait_freeze(&dev->ctrl);
2744                 nvme_dev_add(dev);
2745                 nvme_unfreeze(&dev->ctrl);
2746         }
2747
2748         /*
2749          * If only admin queue live, keep it to do further investigation or
2750          * recovery.
2751          */
2752         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2753                 dev_warn(dev->ctrl.device,
2754                         "failed to mark controller live state\n");
2755                 result = -ENODEV;
2756                 goto out;
2757         }
2758
2759         if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj,
2760                         &nvme_pci_attr_group))
2761                 dev->attrs_added = true;
2762
2763         nvme_start_ctrl(&dev->ctrl);
2764         return;
2765
2766  out_unlock:
2767         mutex_unlock(&dev->shutdown_lock);
2768  out:
2769         if (result)
2770                 dev_warn(dev->ctrl.device,
2771                          "Removing after probe failure status: %d\n", result);
2772         nvme_remove_dead_ctrl(dev);
2773 }
2774
2775 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2776 {
2777         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2778         struct pci_dev *pdev = to_pci_dev(dev->dev);
2779
2780         if (pci_get_drvdata(pdev))
2781                 device_release_driver(&pdev->dev);
2782         nvme_put_ctrl(&dev->ctrl);
2783 }
2784
2785 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2786 {
2787         *val = readl(to_nvme_dev(ctrl)->bar + off);
2788         return 0;
2789 }
2790
2791 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2792 {
2793         writel(val, to_nvme_dev(ctrl)->bar + off);
2794         return 0;
2795 }
2796
2797 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2798 {
2799         *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2800         return 0;
2801 }
2802
2803 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2804 {
2805         struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2806
2807         return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2808 }
2809
2810 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2811         .name                   = "pcie",
2812         .module                 = THIS_MODULE,
2813         .flags                  = NVME_F_METADATA_SUPPORTED |
2814                                   NVME_F_PCI_P2PDMA,
2815         .reg_read32             = nvme_pci_reg_read32,
2816         .reg_write32            = nvme_pci_reg_write32,
2817         .reg_read64             = nvme_pci_reg_read64,
2818         .free_ctrl              = nvme_pci_free_ctrl,
2819         .submit_async_event     = nvme_pci_submit_async_event,
2820         .get_address            = nvme_pci_get_address,
2821 };
2822
2823 static int nvme_dev_map(struct nvme_dev *dev)
2824 {
2825         struct pci_dev *pdev = to_pci_dev(dev->dev);
2826
2827         if (pci_request_mem_regions(pdev, "nvme"))
2828                 return -ENODEV;
2829
2830         if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2831                 goto release;
2832
2833         return 0;
2834   release:
2835         pci_release_mem_regions(pdev);
2836         return -ENODEV;
2837 }
2838
2839 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2840 {
2841         if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2842                 /*
2843                  * Several Samsung devices seem to drop off the PCIe bus
2844                  * randomly when APST is on and uses the deepest sleep state.
2845                  * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2846                  * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2847                  * 950 PRO 256GB", but it seems to be restricted to two Dell
2848                  * laptops.
2849                  */
2850                 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2851                     (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2852                      dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2853                         return NVME_QUIRK_NO_DEEPEST_PS;
2854         } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2855                 /*
2856                  * Samsung SSD 960 EVO drops off the PCIe bus after system
2857                  * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2858                  * within few minutes after bootup on a Coffee Lake board -
2859                  * ASUS PRIME Z370-A
2860                  */
2861                 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2862                     (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2863                      dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2864                         return NVME_QUIRK_NO_APST;
2865         } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2866                     pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2867                    (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2868                 /*
2869                  * Forcing to use host managed nvme power settings for
2870                  * lowest idle power with quick resume latency on
2871                  * Samsung and Toshiba SSDs based on suspend behavior
2872                  * on Coffee Lake board for LENOVO C640
2873                  */
2874                 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2875                      dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2876                         return NVME_QUIRK_SIMPLE_SUSPEND;
2877         }
2878
2879         return 0;
2880 }
2881
2882 static void nvme_async_probe(void *data, async_cookie_t cookie)
2883 {
2884         struct nvme_dev *dev = data;
2885
2886         flush_work(&dev->ctrl.reset_work);
2887         flush_work(&dev->ctrl.scan_work);
2888         nvme_put_ctrl(&dev->ctrl);
2889 }
2890
2891 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2892 {
2893         int node, result = -ENOMEM;
2894         struct nvme_dev *dev;
2895         unsigned long quirks = id->driver_data;
2896         size_t alloc_size;
2897
2898         node = dev_to_node(&pdev->dev);
2899         if (node == NUMA_NO_NODE)
2900                 set_dev_node(&pdev->dev, first_memory_node);
2901
2902         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2903         if (!dev)
2904                 return -ENOMEM;
2905
2906         dev->nr_write_queues = write_queues;
2907         dev->nr_poll_queues = poll_queues;
2908         dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2909         dev->queues = kcalloc_node(dev->nr_allocated_queues,
2910                         sizeof(struct nvme_queue), GFP_KERNEL, node);
2911         if (!dev->queues)
2912                 goto free;
2913
2914         dev->dev = get_device(&pdev->dev);
2915         pci_set_drvdata(pdev, dev);
2916
2917         result = nvme_dev_map(dev);
2918         if (result)
2919                 goto put_pci;
2920
2921         INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2922         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2923         mutex_init(&dev->shutdown_lock);
2924
2925         result = nvme_setup_prp_pools(dev);
2926         if (result)
2927                 goto unmap;
2928
2929         quirks |= check_vendor_combination_bug(pdev);
2930
2931         if (!noacpi && acpi_storage_d3(&pdev->dev)) {
2932                 /*
2933                  * Some systems use a bios work around to ask for D3 on
2934                  * platforms that support kernel managed suspend.
2935                  */
2936                 dev_info(&pdev->dev,
2937                          "platform quirk: setting simple suspend\n");
2938                 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2939         }
2940
2941         /*
2942          * Double check that our mempool alloc size will cover the biggest
2943          * command we support.
2944          */
2945         alloc_size = nvme_pci_iod_alloc_size();
2946         WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2947
2948         dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2949                                                 mempool_kfree,
2950                                                 (void *) alloc_size,
2951                                                 GFP_KERNEL, node);
2952         if (!dev->iod_mempool) {
2953                 result = -ENOMEM;
2954                 goto release_pools;
2955         }
2956
2957         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2958                         quirks);
2959         if (result)
2960                 goto release_mempool;
2961
2962         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2963
2964         nvme_reset_ctrl(&dev->ctrl);
2965         async_schedule(nvme_async_probe, dev);
2966
2967         return 0;
2968
2969  release_mempool:
2970         mempool_destroy(dev->iod_mempool);
2971  release_pools:
2972         nvme_release_prp_pools(dev);
2973  unmap:
2974         nvme_dev_unmap(dev);
2975  put_pci:
2976         put_device(dev->dev);
2977  free:
2978         kfree(dev->queues);
2979         kfree(dev);
2980         return result;
2981 }
2982
2983 static void nvme_reset_prepare(struct pci_dev *pdev)
2984 {
2985         struct nvme_dev *dev = pci_get_drvdata(pdev);
2986
2987         /*
2988          * We don't need to check the return value from waiting for the reset
2989          * state as pci_dev device lock is held, making it impossible to race
2990          * with ->remove().
2991          */
2992         nvme_disable_prepare_reset(dev, false);
2993         nvme_sync_queues(&dev->ctrl);
2994 }
2995
2996 static void nvme_reset_done(struct pci_dev *pdev)
2997 {
2998         struct nvme_dev *dev = pci_get_drvdata(pdev);
2999
3000         if (!nvme_try_sched_reset(&dev->ctrl))
3001                 flush_work(&dev->ctrl.reset_work);
3002 }
3003
3004 static void nvme_shutdown(struct pci_dev *pdev)
3005 {
3006         struct nvme_dev *dev = pci_get_drvdata(pdev);
3007
3008         nvme_disable_prepare_reset(dev, true);
3009 }
3010
3011 static void nvme_remove_attrs(struct nvme_dev *dev)
3012 {
3013         if (dev->attrs_added)
3014                 sysfs_remove_group(&dev->ctrl.device->kobj,
3015                                    &nvme_pci_attr_group);
3016 }
3017
3018 /*
3019  * The driver's remove may be called on a device in a partially initialized
3020  * state. This function must not have any dependencies on the device state in
3021  * order to proceed.
3022  */
3023 static void nvme_remove(struct pci_dev *pdev)
3024 {
3025         struct nvme_dev *dev = pci_get_drvdata(pdev);
3026
3027         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3028         pci_set_drvdata(pdev, NULL);
3029
3030         if (!pci_device_is_present(pdev)) {
3031                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3032                 nvme_dev_disable(dev, true);
3033         }
3034
3035         flush_work(&dev->ctrl.reset_work);
3036         nvme_stop_ctrl(&dev->ctrl);
3037         nvme_remove_namespaces(&dev->ctrl);
3038         nvme_dev_disable(dev, true);
3039         nvme_remove_attrs(dev);
3040         nvme_free_host_mem(dev);
3041         nvme_dev_remove_admin(dev);
3042         nvme_free_queues(dev, 0);
3043         nvme_release_prp_pools(dev);
3044         nvme_dev_unmap(dev);
3045         nvme_uninit_ctrl(&dev->ctrl);
3046 }
3047
3048 #ifdef CONFIG_PM_SLEEP
3049 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3050 {
3051         return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3052 }
3053
3054 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3055 {
3056         return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3057 }
3058
3059 static int nvme_resume(struct device *dev)
3060 {
3061         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3062         struct nvme_ctrl *ctrl = &ndev->ctrl;
3063
3064         if (ndev->last_ps == U32_MAX ||
3065             nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3066                 return nvme_try_sched_reset(&ndev->ctrl);
3067         return 0;
3068 }
3069
3070 static int nvme_suspend(struct device *dev)
3071 {
3072         struct pci_dev *pdev = to_pci_dev(dev);
3073         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3074         struct nvme_ctrl *ctrl = &ndev->ctrl;
3075         int ret = -EBUSY;
3076
3077         ndev->last_ps = U32_MAX;
3078
3079         /*
3080          * The platform does not remove power for a kernel managed suspend so
3081          * use host managed nvme power settings for lowest idle power if
3082          * possible. This should have quicker resume latency than a full device
3083          * shutdown.  But if the firmware is involved after the suspend or the
3084          * device does not support any non-default power states, shut down the
3085          * device fully.
3086          *
3087          * If ASPM is not enabled for the device, shut down the device and allow
3088          * the PCI bus layer to put it into D3 in order to take the PCIe link
3089          * down, so as to allow the platform to achieve its minimum low-power
3090          * state (which may not be possible if the link is up).
3091          *
3092          * If a host memory buffer is enabled, shut down the device as the NVMe
3093          * specification allows the device to access the host memory buffer in
3094          * host DRAM from all power states, but hosts will fail access to DRAM
3095          * during S3.
3096          */
3097         if (pm_suspend_via_firmware() || !ctrl->npss ||
3098             !pcie_aspm_enabled(pdev) ||
3099             ndev->nr_host_mem_descs ||
3100             (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3101                 return nvme_disable_prepare_reset(ndev, true);
3102
3103         nvme_start_freeze(ctrl);
3104         nvme_wait_freeze(ctrl);
3105         nvme_sync_queues(ctrl);
3106
3107         if (ctrl->state != NVME_CTRL_LIVE)
3108                 goto unfreeze;
3109
3110         ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3111         if (ret < 0)
3112                 goto unfreeze;
3113
3114         /*
3115          * A saved state prevents pci pm from generically controlling the
3116          * device's power. If we're using protocol specific settings, we don't
3117          * want pci interfering.
3118          */
3119         pci_save_state(pdev);
3120
3121         ret = nvme_set_power_state(ctrl, ctrl->npss);
3122         if (ret < 0)
3123                 goto unfreeze;
3124
3125         if (ret) {
3126                 /* discard the saved state */
3127                 pci_load_saved_state(pdev, NULL);
3128
3129                 /*
3130                  * Clearing npss forces a controller reset on resume. The
3131                  * correct value will be rediscovered then.
3132                  */
3133                 ret = nvme_disable_prepare_reset(ndev, true);
3134                 ctrl->npss = 0;
3135         }
3136 unfreeze:
3137         nvme_unfreeze(ctrl);
3138         return ret;
3139 }
3140
3141 static int nvme_simple_suspend(struct device *dev)
3142 {
3143         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3144
3145         return nvme_disable_prepare_reset(ndev, true);
3146 }
3147
3148 static int nvme_simple_resume(struct device *dev)
3149 {
3150         struct pci_dev *pdev = to_pci_dev(dev);
3151         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3152
3153         return nvme_try_sched_reset(&ndev->ctrl);
3154 }
3155
3156 static const struct dev_pm_ops nvme_dev_pm_ops = {
3157         .suspend        = nvme_suspend,
3158         .resume         = nvme_resume,
3159         .freeze         = nvme_simple_suspend,
3160         .thaw           = nvme_simple_resume,
3161         .poweroff       = nvme_simple_suspend,
3162         .restore        = nvme_simple_resume,
3163 };
3164 #endif /* CONFIG_PM_SLEEP */
3165
3166 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3167                                                 pci_channel_state_t state)
3168 {
3169         struct nvme_dev *dev = pci_get_drvdata(pdev);
3170
3171         /*
3172          * A frozen channel requires a reset. When detected, this method will
3173          * shutdown the controller to quiesce. The controller will be restarted
3174          * after the slot reset through driver's slot_reset callback.
3175          */
3176         switch (state) {
3177         case pci_channel_io_normal:
3178                 return PCI_ERS_RESULT_CAN_RECOVER;
3179         case pci_channel_io_frozen:
3180                 dev_warn(dev->ctrl.device,
3181                         "frozen state error detected, reset controller\n");
3182                 nvme_dev_disable(dev, false);
3183                 return PCI_ERS_RESULT_NEED_RESET;
3184         case pci_channel_io_perm_failure:
3185                 dev_warn(dev->ctrl.device,
3186                         "failure state error detected, request disconnect\n");
3187                 return PCI_ERS_RESULT_DISCONNECT;
3188         }
3189         return PCI_ERS_RESULT_NEED_RESET;
3190 }
3191
3192 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3193 {
3194         struct nvme_dev *dev = pci_get_drvdata(pdev);
3195
3196         dev_info(dev->ctrl.device, "restart after slot reset\n");
3197         pci_restore_state(pdev);
3198         nvme_reset_ctrl(&dev->ctrl);
3199         return PCI_ERS_RESULT_RECOVERED;
3200 }
3201
3202 static void nvme_error_resume(struct pci_dev *pdev)
3203 {
3204         struct nvme_dev *dev = pci_get_drvdata(pdev);
3205
3206         flush_work(&dev->ctrl.reset_work);
3207 }
3208
3209 static const struct pci_error_handlers nvme_err_handler = {
3210         .error_detected = nvme_error_detected,
3211         .slot_reset     = nvme_slot_reset,
3212         .resume         = nvme_error_resume,
3213         .reset_prepare  = nvme_reset_prepare,
3214         .reset_done     = nvme_reset_done,
3215 };
3216
3217 static const struct pci_device_id nvme_id_table[] = {
3218         { PCI_VDEVICE(INTEL, 0x0953),   /* Intel 750/P3500/P3600/P3700 */
3219                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3220                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3221         { PCI_VDEVICE(INTEL, 0x0a53),   /* Intel P3520 */
3222                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3223                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3224         { PCI_VDEVICE(INTEL, 0x0a54),   /* Intel P4500/P4600 */
3225                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3226                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3227         { PCI_VDEVICE(INTEL, 0x0a55),   /* Dell Express Flash P4600 */
3228                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3229                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3230         { PCI_VDEVICE(INTEL, 0xf1a5),   /* Intel 600P/P3100 */
3231                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3232                                 NVME_QUIRK_MEDIUM_PRIO_SQ |
3233                                 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3234                                 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3235         { PCI_VDEVICE(INTEL, 0xf1a6),   /* Intel 760p/Pro 7600p */
3236                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3237         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
3238                 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3239                                 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3240         { PCI_DEVICE(0x126f, 0x2263),   /* Silicon Motion unidentified */
3241                 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
3242         { PCI_DEVICE(0x1bb1, 0x0100),   /* Seagate Nytro Flash Storage */
3243                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3244                                 NVME_QUIRK_NO_NS_DESC_LIST, },
3245         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
3246                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3247         { PCI_DEVICE(0x1c58, 0x0023),   /* WDC SN200 adapter */
3248                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3249         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
3250                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3251         { PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */
3252                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3253         { PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */
3254                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3255                                 NVME_QUIRK_DISABLE_WRITE_ZEROES|
3256                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3257         { PCI_DEVICE(0x1987, 0x5016),   /* Phison E16 */
3258                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3259         { PCI_DEVICE(0x1b4b, 0x1092),   /* Lexar 256 GB SSD */
3260                 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3261                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3262         { PCI_DEVICE(0x10ec, 0x5762),   /* ADATA SX6000LNP */
3263                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3264         { PCI_DEVICE(0x1cc1, 0x8201),   /* ADATA SX8200PNP 512GB */
3265                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3266                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3267         { PCI_DEVICE(0x1c5c, 0x1504),   /* SK Hynix PC400 */
3268                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3269         { PCI_DEVICE(0x15b7, 0x2001),   /*  Sandisk Skyhawk */
3270                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3271         { PCI_DEVICE(0x1d97, 0x2263),   /* SPCC */
3272                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3273         { PCI_DEVICE(0x2646, 0x2262),   /* KINGSTON SKC2000 NVMe SSD */
3274                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3275         { PCI_DEVICE(0x2646, 0x2263),   /* KINGSTON A2000 NVMe SSD  */
3276                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3277         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3278                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3279         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3280                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3281         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3282                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3283         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3284                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3285         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3286                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3287         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3288                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3289         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3290                 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3291         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3292         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3293                 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3294                                 NVME_QUIRK_128_BYTES_SQES |
3295                                 NVME_QUIRK_SHARED_TAGS },
3296
3297         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3298         { 0, }
3299 };
3300 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3301
3302 static struct pci_driver nvme_driver = {
3303         .name           = "nvme",
3304         .id_table       = nvme_id_table,
3305         .probe          = nvme_probe,
3306         .remove         = nvme_remove,
3307         .shutdown       = nvme_shutdown,
3308 #ifdef CONFIG_PM_SLEEP
3309         .driver         = {
3310                 .pm     = &nvme_dev_pm_ops,
3311         },
3312 #endif
3313         .sriov_configure = pci_sriov_configure_simple,
3314         .err_handler    = &nvme_err_handler,
3315 };
3316
3317 static int __init nvme_init(void)
3318 {
3319         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3320         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3321         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3322         BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3323
3324         return pci_register_driver(&nvme_driver);
3325 }
3326
3327 static void __exit nvme_exit(void)
3328 {
3329         pci_unregister_driver(&nvme_driver);
3330         flush_workqueue(nvme_wq);
3331 }
3332
3333 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3334 MODULE_LICENSE("GPL");
3335 MODULE_VERSION("1.0");
3336 module_init(nvme_init);
3337 module_exit(nvme_exit);