drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2009-2010  Realtek Corporation.*/
   3
   4 #include "../wifi.h"
   5 #include "../pci.h"
   6 #include "../ps.h"
   7 #include "reg.h"
   8 #include "def.h"
   9 #include "phy.h"
  10 #include "rf.h"
  11 #include "dm.h"
  12 #include "table.h"
  13 #include "trx.h"
  14 #include "../btcoexist/halbt_precomp.h"
  15 #include "hw.h"
  16 #include "../efuse.h"
  17
  18 #define READ_NEXT_PAIR(array_table, v1, v2, i) \
  19         do { \
  20                 i += 2; \
  21                 v1 = array_table[i]; \
  22                 v2 = array_table[i+1]; \
  23         } while (0)
  24
  25 static u32 _rtl8821ae_phy_rf_serial_read(struct ieee80211_hw *hw,
  26                                          enum radio_path rfpath, u32 offset);
  27 static void _rtl8821ae_phy_rf_serial_write(struct ieee80211_hw *hw,
  28                                            enum radio_path rfpath, u32 offset,
  29                                            u32 data);
  30 static u32 _rtl8821ae_phy_calculate_bit_shift(u32 bitmask);
  31 static bool _rtl8821ae_phy_bb8821a_config_parafile(struct ieee80211_hw *hw);
  32 /*static bool _rtl8812ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);*/
  33 static bool _rtl8821ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
  34 static bool _rtl8821ae_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
  35                                                      u8 configtype);
  36 static bool _rtl8821ae_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
  37                                                        u8 configtype);
  38 static void phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
  39
  40 static long _rtl8821ae_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
  41                                             enum wireless_mode wirelessmode,
  42                                             u8 txpwridx);
  43 static void rtl8821ae_phy_set_rf_on(struct ieee80211_hw *hw);
  44 static void rtl8821ae_phy_set_io(struct ieee80211_hw *hw);
  45
  46 static void rtl8812ae_fixspur(struct ieee80211_hw *hw,
  47                               enum ht_channel_width band_width, u8 channel)
  48 {
  49         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  50
  51         /*C cut Item12 ADC FIFO CLOCK*/
  52         if (IS_VENDOR_8812A_C_CUT(rtlhal->version)) {
  53                 if (band_width == HT_CHANNEL_WIDTH_20_40 && channel == 11)
  54                         rtl_set_bbreg(hw, RRFMOD, 0xC00, 0x3);
  55                         /* 0x8AC[11:10] = 2'b11*/
  56                 else
  57                         rtl_set_bbreg(hw, RRFMOD, 0xC00, 0x2);
  58                         /* 0x8AC[11:10] = 2'b10*/
  59
  60                 /* <20120914, Kordan> A workarould to resolve
  61                  * 2480Mhz spur by setting ADC clock as 160M. (Asked by Binson)
  62                  */
  63                 if (band_width == HT_CHANNEL_WIDTH_20 &&
  64                     (channel == 13 || channel == 14)) {
  65                         rtl_set_bbreg(hw, RRFMOD, 0x300, 0x3);
  66                         /*0x8AC[9:8] = 2'b11*/
  67                         rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1);
  68                         /* 0x8C4[30] = 1*/
  69                 } else if (band_width == HT_CHANNEL_WIDTH_20_40 &&
  70                            channel == 11) {
  71                         rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1);
  72                         /*0x8C4[30] = 1*/
  73                 } else if (band_width != HT_CHANNEL_WIDTH_80) {
  74                         rtl_set_bbreg(hw, RRFMOD, 0x300, 0x2);
  75                         /*0x8AC[9:8] = 2'b10*/
  76                         rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0);
  77                         /*0x8C4[30] = 0*/
  78                 }
  79         } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
  80                 /* <20120914, Kordan> A workarould to resolve
  81                  * 2480Mhz spur by setting ADC clock as 160M.
  82                  */
  83                 if (band_width == HT_CHANNEL_WIDTH_20 &&
  84                     (channel == 13 || channel == 14))
  85                         rtl_set_bbreg(hw, RRFMOD, 0x300, 0x3);
  86                         /*0x8AC[9:8] = 11*/
  87                 else if (channel  <= 14) /*2.4G only*/
  88                         rtl_set_bbreg(hw, RRFMOD, 0x300, 0x2);
  89                         /*0x8AC[9:8] = 10*/
  90         }
  91 }
  92
  93 u32 rtl8821ae_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr,
  94                                u32 bitmask)
  95 {
  96         struct rtl_priv *rtlpriv = rtl_priv(hw);
  97         u32 returnvalue, originalvalue, bitshift;
  98
  99         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
 100                 "regaddr(%#x), bitmask(%#x)\n",
 101                 regaddr, bitmask);
 102         originalvalue = rtl_read_dword(rtlpriv, regaddr);
 103         bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask);
 104         returnvalue = (originalvalue & bitmask) >> bitshift;
 105
 106         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
 107                 "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
 108                 bitmask, regaddr, originalvalue);
 109         return returnvalue;
 110 }
 111
 112 void rtl8821ae_phy_set_bb_reg(struct ieee80211_hw *hw,
 113                               u32 regaddr, u32 bitmask, u32 data)
 114 {
 115         struct rtl_priv *rtlpriv = rtl_priv(hw);
 116         u32 originalvalue, bitshift;
 117
 118         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
 119                 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
 120                 regaddr, bitmask, data);
 121
 122         if (bitmask != MASKDWORD) {
 123                 originalvalue = rtl_read_dword(rtlpriv, regaddr);
 124                 bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask);
 125                 data = ((originalvalue & (~bitmask)) |
 126                         ((data << bitshift) & bitmask));
 127         }
 128
 129         rtl_write_dword(rtlpriv, regaddr, data);
 130
 131         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
 132                 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
 133                 regaddr, bitmask, data);
 134 }
 135
 136 u32 rtl8821ae_phy_query_rf_reg(struct ieee80211_hw *hw,
 137                                enum radio_path rfpath, u32 regaddr,
 138                                u32 bitmask)
 139 {
 140         struct rtl_priv *rtlpriv = rtl_priv(hw);
 141         u32 original_value, readback_value, bitshift;
 142
 143         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
 144                 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
 145                 regaddr, rfpath, bitmask);
 146
 147         spin_lock(&rtlpriv->locks.rf_lock);
 148
 149         original_value = _rtl8821ae_phy_rf_serial_read(hw, rfpath, regaddr);
 150         bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask);
 151         readback_value = (original_value & bitmask) >> bitshift;
 152
 153         spin_unlock(&rtlpriv->locks.rf_lock);
 154
 155         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
 156                 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
 157                 regaddr, rfpath, bitmask, original_value);
 158
 159         return readback_value;
 160 }
 161
 162 void rtl8821ae_phy_set_rf_reg(struct ieee80211_hw *hw,
 163                            enum radio_path rfpath,
 164                            u32 regaddr, u32 bitmask, u32 data)
 165 {
 166         struct rtl_priv *rtlpriv = rtl_priv(hw);
 167         u32 original_value, bitshift;
 168
 169         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
 170                 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 171                 regaddr, bitmask, data, rfpath);
 172
 173         spin_lock(&rtlpriv->locks.rf_lock);
 174
 175         if (bitmask != RFREG_OFFSET_MASK) {
 176                 original_value =
 177                    _rtl8821ae_phy_rf_serial_read(hw, rfpath, regaddr);
 178                 bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask);
 179                 data = ((original_value & (~bitmask)) | (data << bitshift));
 180         }
 181
 182         _rtl8821ae_phy_rf_serial_write(hw, rfpath, regaddr, data);
 183
 184         spin_unlock(&rtlpriv->locks.rf_lock);
 185
 186         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
 187                 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 188                  regaddr, bitmask, data, rfpath);
 189 }
 190
 191 static u32 _rtl8821ae_phy_rf_serial_read(struct ieee80211_hw *hw,
 192                                          enum radio_path rfpath, u32 offset)
 193 {
 194         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 195         bool is_pi_mode = false;
 196         u32 retvalue = 0;
 197
 198         /* 2009/06/17 MH We can not execute IO for power
 199         save or other accident mode.*/
 200         if (RT_CANNOT_IO(hw)) {
 201                 pr_err("return all one\n");
 202                 return 0xFFFFFFFF;
 203         }
 204         /* <20120809, Kordan> CCA OFF(when entering),
 205                 asked by James to avoid reading the wrong value.
 206             <20120828, Kordan> Toggling CCA would affect RF 0x0, skip it!*/
 207         if (offset != 0x0 &&
 208             !((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) ||
 209             (IS_VENDOR_8812A_C_CUT(rtlhal->version))))
 210                 rtl_set_bbreg(hw, RCCAONSEC, 0x8, 1);
 211         offset &= 0xff;
 212
 213         if (rfpath == RF90_PATH_A)
 214                 is_pi_mode = (bool)rtl_get_bbreg(hw, 0xC00, 0x4);
 215         else if (rfpath == RF90_PATH_B)
 216                 is_pi_mode = (bool)rtl_get_bbreg(hw, 0xE00, 0x4);
 217
 218         rtl_set_bbreg(hw, RHSSIREAD_8821AE, 0xff, offset);
 219
 220         if ((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) ||
 221             (IS_VENDOR_8812A_C_CUT(rtlhal->version)))
 222                 udelay(20);
 223
 224         if (is_pi_mode) {
 225                 if (rfpath == RF90_PATH_A)
 226                         retvalue =
 227                           rtl_get_bbreg(hw, RA_PIREAD_8821A, BLSSIREADBACKDATA);
 228                 else if (rfpath == RF90_PATH_B)
 229                         retvalue =
 230                           rtl_get_bbreg(hw, RB_PIREAD_8821A, BLSSIREADBACKDATA);
 231         } else {
 232                 if (rfpath == RF90_PATH_A)
 233                         retvalue =
 234                           rtl_get_bbreg(hw, RA_SIREAD_8821A, BLSSIREADBACKDATA);
 235                 else if (rfpath == RF90_PATH_B)
 236                         retvalue =
 237                           rtl_get_bbreg(hw, RB_SIREAD_8821A, BLSSIREADBACKDATA);
 238         }
 239
 240         /*<20120809, Kordan> CCA ON(when exiting),
 241          * asked by James to avoid reading the wrong value.
 242          *   <20120828, Kordan> Toggling CCA would affect RF 0x0, skip it!
 243          */
 244         if (offset != 0x0 &&
 245             !((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) ||
 246             (IS_VENDOR_8812A_C_CUT(rtlhal->version))))
 247                 rtl_set_bbreg(hw, RCCAONSEC, 0x8, 0);
 248         return retvalue;
 249 }
 250
 251 static void _rtl8821ae_phy_rf_serial_write(struct ieee80211_hw *hw,
 252                                            enum radio_path rfpath, u32 offset,
 253                                            u32 data)
 254 {
 255         struct rtl_priv *rtlpriv = rtl_priv(hw);
 256         struct rtl_phy *rtlphy = &rtlpriv->phy;
 257         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
 258         u32 data_and_addr;
 259         u32 newoffset;
 260
 261         if (RT_CANNOT_IO(hw)) {
 262                 pr_err("stop\n");
 263                 return;
 264         }
 265         offset &= 0xff;
 266         newoffset = offset;
 267         data_and_addr = ((newoffset << 20) |
 268                          (data & 0x000fffff)) & 0x0fffffff;
 269         rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
 270         rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
 271                 "RFW-%d Addr[0x%x]=0x%x\n",
 272                 rfpath, pphyreg->rf3wire_offset, data_and_addr);
 273 }
 274
 275 static u32 _rtl8821ae_phy_calculate_bit_shift(u32 bitmask)
 276 {
 277         u32 i;
 278
 279         for (i = 0; i <= 31; i++) {
 280                 if (((bitmask >> i) & 0x1) == 1)
 281                         break;
 282         }
 283         return i;
 284 }
 285
 286 bool rtl8821ae_phy_mac_config(struct ieee80211_hw *hw)
 287 {
 288         bool rtstatus = 0;
 289
 290         rtstatus = _rtl8821ae_phy_config_mac_with_headerfile(hw);
 291
 292         return rtstatus;
 293 }
 294
 295 bool rtl8821ae_phy_bb_config(struct ieee80211_hw *hw)
 296 {
 297         bool rtstatus = true;
 298         struct rtl_priv *rtlpriv = rtl_priv(hw);
 299         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 300         struct rtl_phy *rtlphy = &rtlpriv->phy;
 301         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 302         u8 regval;
 303         u8 crystal_cap;
 304
 305         phy_init_bb_rf_register_definition(hw);
 306
 307         regval = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
 308         regval |= FEN_PCIEA;
 309         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, regval);
 310         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
 311                        regval | FEN_BB_GLB_RSTN | FEN_BBRSTB);
 312
 313         rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x7);
 314         rtl_write_byte(rtlpriv, REG_OPT_CTRL + 2, 0x7);
 315
 316         rtstatus = _rtl8821ae_phy_bb8821a_config_parafile(hw);
 317
 318         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
 319                 crystal_cap = rtlefuse->crystalcap & 0x3F;
 320                 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0x7FF80000,
 321                               (crystal_cap | (crystal_cap << 6)));
 322         } else {
 323                 crystal_cap = rtlefuse->crystalcap & 0x3F;
 324                 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000,
 325                               (crystal_cap | (crystal_cap << 6)));
 326         }
 327         rtlphy->reg_837 = rtl_read_byte(rtlpriv, 0x837);
 328
 329         return rtstatus;
 330 }
 331
 332 bool rtl8821ae_phy_rf_config(struct ieee80211_hw *hw)
 333 {
 334         return rtl8821ae_phy_rf6052_config(hw);
 335 }
 336
 337 static void _rtl8812ae_phy_set_rfe_reg_24g(struct ieee80211_hw *hw)
 338 {
 339         struct rtl_priv *rtlpriv = rtl_priv(hw);
 340         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 341         u8 tmp;
 342
 343         switch (rtlhal->rfe_type) {
 344         case 3:
 345                 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x54337770);
 346                 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x54337770);
 347                 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x010);
 348                 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010);
 349                 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x1);
 350                 break;
 351         case 4:
 352                 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77777777);
 353                 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77777777);
 354                 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x001);
 355                 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x001);
 356                 break;
 357         case 5:
 358                 rtl_write_byte(rtlpriv, RA_RFE_PINMUX + 2, 0x77);
 359                 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77777777);
 360                 tmp = rtl_read_byte(rtlpriv, RA_RFE_INV + 3);
 361                 rtl_write_byte(rtlpriv, RA_RFE_INV + 3, tmp & ~0x1);
 362                 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000);
 363                 break;
 364         case 1:
 365                 if (rtlpriv->btcoexist.bt_coexistence) {
 366                         rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xffffff, 0x777777);
 367                         rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD,
 368                                       0x77777777);
 369                         rtl_set_bbreg(hw, RA_RFE_INV, 0x33f00000, 0x000);
 370                         rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000);
 371                         break;
 372                 }
 373                 fallthrough;
 374         case 0:
 375         case 2:
 376         default:
 377                 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77777777);
 378                 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77777777);
 379                 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x000);
 380                 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000);
 381                 break;
 382         }
 383 }
 384
 385 static void _rtl8812ae_phy_set_rfe_reg_5g(struct ieee80211_hw *hw)
 386 {
 387         struct rtl_priv *rtlpriv = rtl_priv(hw);
 388         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 389         u8 tmp;
 390
 391         switch (rtlhal->rfe_type) {
 392         case 0:
 393                 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77337717);
 394                 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77337717);
 395                 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x010);
 396                 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010);
 397                 break;
 398         case 1:
 399                 if (rtlpriv->btcoexist.bt_coexistence) {
 400                         rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xffffff, 0x337717);
 401                         rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD,
 402                                       0x77337717);
 403                         rtl_set_bbreg(hw, RA_RFE_INV, 0x33f00000, 0x000);
 404                         rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000);
 405                 } else {
 406                         rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD,
 407                                       0x77337717);
 408                         rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD,
 409                                       0x77337717);
 410                         rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x000);
 411                         rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000);
 412                 }
 413                 break;
 414         case 3:
 415                 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x54337717);
 416                 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x54337717);
 417                 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x010);
 418                 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010);
 419                 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x1);
 420                 break;
 421         case 5:
 422                 rtl_write_byte(rtlpriv, RA_RFE_PINMUX + 2, 0x33);
 423                 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77337777);
 424                 tmp = rtl_read_byte(rtlpriv, RA_RFE_INV + 3);
 425                 rtl_write_byte(rtlpriv, RA_RFE_INV + 3, tmp | 0x1);
 426                 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010);
 427                 break;
 428         case 2:
 429         case 4:
 430         default:
 431                 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77337777);
 432                 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77337777);
 433                 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x010);
 434                 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010);
 435                 break;
 436         }
 437 }
 438
 439 u32 phy_get_tx_swing_8812A(struct ieee80211_hw *hw, u8  band,
 440                            u8 rf_path)
 441 {
 442         struct rtl_priv *rtlpriv = rtl_priv(hw);
 443         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 444         struct rtl_dm *rtldm = rtl_dm(rtlpriv);
 445         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 446         s8 reg_swing_2g = -1;/* 0xff; */
 447         s8 reg_swing_5g = -1;/* 0xff; */
 448         s8 swing_2g = -1 * reg_swing_2g;
 449         s8 swing_5g = -1 * reg_swing_5g;
 450         u32  out = 0x200;
 451         const s8 auto_temp = -1;
 452
 453         rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
 454                 "===> PHY_GetTXBBSwing_8812A, bbSwing_2G: %d, bbSwing_5G: %d,autoload_failflag=%d.\n",
 455                 (int)swing_2g, (int)swing_5g,
 456                 (int)rtlefuse->autoload_failflag);
 457
 458         if (rtlefuse->autoload_failflag) {
 459                 if (band == BAND_ON_2_4G) {
 460                         rtldm->swing_diff_2g = swing_2g;
 461                         if (swing_2g == 0) {
 462                                 out = 0x200; /* 0 dB */
 463                         } else if (swing_2g == -3) {
 464                                 out = 0x16A; /* -3 dB */
 465                         } else if (swing_2g == -6) {
 466                                 out = 0x101; /* -6 dB */
 467                         } else if (swing_2g == -9) {
 468                                 out = 0x0B6; /* -9 dB */
 469                         } else {
 470                                 rtldm->swing_diff_2g = 0;
 471                                 out = 0x200;
 472                         }
 473                 } else if (band == BAND_ON_5G) {
 474                         rtldm->swing_diff_5g = swing_5g;
 475                         if (swing_5g == 0) {
 476                                 out = 0x200; /* 0 dB */
 477                         } else if (swing_5g == -3) {
 478                                 out = 0x16A; /* -3 dB */
 479                         } else if (swing_5g == -6) {
 480                                 out = 0x101; /* -6 dB */
 481                         } else if (swing_5g == -9) {
 482                                 out = 0x0B6; /* -9 dB */
 483                         } else {
 484                                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
 485                                         rtldm->swing_diff_5g = -3;
 486                                         out = 0x16A;
 487                                 } else {
 488                                         rtldm->swing_diff_5g = 0;
 489                                         out = 0x200;
 490                                 }
 491                         }
 492                 } else {
 493                         rtldm->swing_diff_2g = -3;
 494                         rtldm->swing_diff_5g = -3;
 495                         out = 0x16A; /* -3 dB */
 496                 }
 497         } else {
 498                 u32 swing = 0, swing_a = 0, swing_b = 0;
 499
 500                 if (band == BAND_ON_2_4G) {
 501                         if (reg_swing_2g == auto_temp) {
 502                                 efuse_shadow_read(hw, 1, 0xC6, (u32 *)&swing);
 503                                 swing = (swing == 0xFF) ? 0x00 : swing;
 504                         } else if (swing_2g ==  0) {
 505                                 swing = 0x00; /* 0 dB */
 506                         } else if (swing_2g == -3) {
 507                                 swing = 0x05; /* -3 dB */
 508                         } else if (swing_2g == -6) {
 509                                 swing = 0x0A; /* -6 dB */
 510                         } else if (swing_2g == -9) {
 511                                 swing = 0xFF; /* -9 dB */
 512                         } else {
 513                                 swing = 0x00;
 514                         }
 515                 } else {
 516                         if (reg_swing_5g == auto_temp) {
 517                                 efuse_shadow_read(hw, 1, 0xC7, (u32 *)&swing);
 518                                 swing = (swing == 0xFF) ? 0x00 : swing;
 519                         } else if (swing_5g ==  0) {
 520                                 swing = 0x00; /* 0 dB */
 521                         } else if (swing_5g == -3) {
 522                                 swing = 0x05; /* -3 dB */
 523                         } else if (swing_5g == -6) {
 524                                 swing = 0x0A; /* -6 dB */
 525                         } else if (swing_5g == -9) {
 526                                 swing = 0xFF; /* -9 dB */
 527                         } else {
 528                                 swing = 0x00;
 529                         }
 530                 }
 531
 532                 swing_a = (swing & 0x3) >> 0; /* 0xC6/C7[1:0] */
 533                 swing_b = (swing & 0xC) >> 2; /* 0xC6/C7[3:2] */
 534                 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
 535                         "===> PHY_GetTXBBSwing_8812A, swingA: 0x%X, swingB: 0x%X\n",
 536                         swing_a, swing_b);
 537
 538                 /* 3 Path-A */
 539                 if (swing_a == 0x0) {
 540                         if (band == BAND_ON_2_4G)
 541                                 rtldm->swing_diff_2g = 0;
 542                         else
 543                                 rtldm->swing_diff_5g = 0;
 544                         out = 0x200; /* 0 dB */
 545                 } else if (swing_a == 0x1) {
 546                         if (band == BAND_ON_2_4G)
 547                                 rtldm->swing_diff_2g = -3;
 548                         else
 549                                 rtldm->swing_diff_5g = -3;
 550                         out = 0x16A; /* -3 dB */
 551                 } else if (swing_a == 0x2) {
 552                         if (band == BAND_ON_2_4G)
 553                                 rtldm->swing_diff_2g = -6;
 554                         else
 555                                 rtldm->swing_diff_5g = -6;
 556                         out = 0x101; /* -6 dB */
 557                 } else if (swing_a == 0x3) {
 558                         if (band == BAND_ON_2_4G)
 559                                 rtldm->swing_diff_2g = -9;
 560                         else
 561                                 rtldm->swing_diff_5g = -9;
 562                         out = 0x0B6; /* -9 dB */
 563                 }
 564                 /* 3 Path-B */
 565                 if (swing_b == 0x0) {
 566                         if (band == BAND_ON_2_4G)
 567                                 rtldm->swing_diff_2g = 0;
 568                         else
 569                                 rtldm->swing_diff_5g = 0;
 570                         out = 0x200; /* 0 dB */
 571                 } else if (swing_b == 0x1) {
 572                         if (band == BAND_ON_2_4G)
 573                                 rtldm->swing_diff_2g = -3;
 574                         else
 575                                 rtldm->swing_diff_5g = -3;
 576                         out = 0x16A; /* -3 dB */
 577                 } else if (swing_b == 0x2) {
 578                         if (band == BAND_ON_2_4G)
 579                                 rtldm->swing_diff_2g = -6;
 580                         else
 581                                 rtldm->swing_diff_5g = -6;
 582                         out = 0x101; /* -6 dB */
 583                 } else if (swing_b == 0x3) {
 584                         if (band == BAND_ON_2_4G)
 585                                 rtldm->swing_diff_2g = -9;
 586                         else
 587                                 rtldm->swing_diff_5g = -9;
 588                         out = 0x0B6; /* -9 dB */
 589                 }
 590         }
 591
 592         rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
 593                 "<=== PHY_GetTXBBSwing_8812A, out = 0x%X\n", out);
 594         return out;
 595 }
 596
 597 void rtl8821ae_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band)
 598 {
 599         struct rtl_priv *rtlpriv = rtl_priv(hw);
 600         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 601         struct rtl_dm *rtldm = rtl_dm(rtlpriv);
 602         u8 current_band = rtlhal->current_bandtype;
 603         u32 txpath, rxpath;
 604         s8 bb_diff_between_band;
 605
 606         txpath = rtl8821ae_phy_query_bb_reg(hw, RTXPATH, 0xf0);
 607         rxpath = rtl8821ae_phy_query_bb_reg(hw, RCCK_RX, 0x0f000000);
 608         rtlhal->current_bandtype = (enum band_type) band;
 609         /* reconfig BB/RF according to wireless mode */
 610         if (rtlhal->current_bandtype == BAND_ON_2_4G) {
 611                 /* BB & RF Config */
 612                 rtl_set_bbreg(hw, ROFDMCCKEN, BOFDMEN|BCCKEN, 0x03);
 613
 614                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
 615                         /* 0xCB0[15:12] = 0x7 (LNA_On)*/
 616                         rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF000, 0x7);
 617                         /* 0xCB0[7:4] = 0x7 (PAPE_A)*/
 618                         rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF0, 0x7);
 619                 }
 620
 621                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
 622                         /*0x834[1:0] = 0x1*/
 623                         rtl_set_bbreg(hw, 0x834, 0x3, 0x1);
 624                 }
 625
 626                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
 627                         /* 0xC1C[11:8] = 0 */
 628                         rtl_set_bbreg(hw, RA_TXSCALE, 0xF00, 0);
 629                 } else {
 630                         /* 0x82C[1:0] = 2b'00 */
 631                         rtl_set_bbreg(hw, 0x82c, 0x3, 0);
 632                 }
 633
 634                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 635                         _rtl8812ae_phy_set_rfe_reg_24g(hw);
 636
 637                 rtl_set_bbreg(hw, RTXPATH, 0xf0, 0x1);
 638                 rtl_set_bbreg(hw, RCCK_RX, 0x0f000000, 0x1);
 639
 640                 rtl_write_byte(rtlpriv, REG_CCK_CHECK, 0x0);
 641         } else {/* 5G band */
 642                 u16 count, reg_41a;
 643
 644                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
 645                         /*0xCB0[15:12] = 0x5 (LNA_On)*/
 646                         rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF000, 0x5);
 647                         /*0xCB0[7:4] = 0x4 (PAPE_A)*/
 648                         rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF0, 0x4);
 649                 }
 650                 /*CCK_CHECK_en*/
 651                 rtl_write_byte(rtlpriv, REG_CCK_CHECK, 0x80);
 652
 653                 count = 0;
 654                 reg_41a = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
 655                 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
 656                         "Reg41A value %d\n", reg_41a);
 657                 reg_41a &= 0x30;
 658                 while ((reg_41a != 0x30) && (count < 50)) {
 659                         udelay(50);
 660                         rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, "Delay 50us\n");
 661
 662                         reg_41a = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
 663                         reg_41a &= 0x30;
 664                         count++;
 665                         rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
 666                                 "Reg41A value %d\n", reg_41a);
 667                 }
 668                 if (count != 0)
 669                         rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
 670                                 "PHY_SwitchWirelessBand8812(): Switch to 5G Band. Count = %d reg41A=0x%x\n",
 671                                 count, reg_41a);
 672
 673                 /* 2012/02/01, Sinda add registry to switch workaround
 674                 without long-run verification for scan issue. */
 675                 rtl_set_bbreg(hw, ROFDMCCKEN, BOFDMEN|BCCKEN, 0x03);
 676
 677                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
 678                         /*0x834[1:0] = 0x2*/
 679                         rtl_set_bbreg(hw, 0x834, 0x3, 0x2);
 680                 }
 681
 682                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
 683                         /* AGC table select */
 684                         /* 0xC1C[11:8] = 1*/
 685                         rtl_set_bbreg(hw, RA_TXSCALE, 0xF00, 1);
 686                 } else
 687                         /* 0x82C[1:0] = 2'b00 */
 688                         rtl_set_bbreg(hw, 0x82c, 0x3, 1);
 689
 690                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
 691                         _rtl8812ae_phy_set_rfe_reg_5g(hw);
 692
 693                 rtl_set_bbreg(hw, RTXPATH, 0xf0, 0);
 694                 rtl_set_bbreg(hw, RCCK_RX, 0x0f000000, 0xf);
 695
 696                 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
 697                         "==>PHY_SwitchWirelessBand8812() BAND_ON_5G settings OFDM index 0x%x\n",
 698                         rtlpriv->dm.ofdm_index[RF90_PATH_A]);
 699         }
 700
 701         if ((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) ||
 702             (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)) {
 703                 /* 0xC1C[31:21] */
 704                 rtl_set_bbreg(hw, RA_TXSCALE, 0xFFE00000,
 705                               phy_get_tx_swing_8812A(hw, band, RF90_PATH_A));
 706                 /* 0xE1C[31:21] */
 707                 rtl_set_bbreg(hw, RB_TXSCALE, 0xFFE00000,
 708                               phy_get_tx_swing_8812A(hw, band, RF90_PATH_B));
 709
 710                 /* <20121005, Kordan> When TxPowerTrack is ON,
 711                  *      we should take care of the change of BB swing.
 712                  *   That is, reset all info to trigger Tx power tracking.
 713                  */
 714                 if (band != current_band) {
 715                         bb_diff_between_band =
 716                                 (rtldm->swing_diff_2g - rtldm->swing_diff_5g);
 717                         bb_diff_between_band = (band == BAND_ON_2_4G) ?
 718                                                 bb_diff_between_band :
 719                                                 (-1 * bb_diff_between_band);
 720                         rtldm->default_ofdm_index += bb_diff_between_band * 2;
 721                 }
 722                 rtl8821ae_dm_clear_txpower_tracking_state(hw);
 723         }
 724
 725         rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
 726                 "<==%s():Switch Band OK.\n", __func__);
 727         return;
 728 }
 729
 730 static bool _rtl8821ae_check_positive(struct ieee80211_hw *hw,
 731                                       const u32 condition1,
 732                                       const u32 condition2)
 733 {
 734         struct rtl_priv *rtlpriv = rtl_priv(hw);
 735         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
 736         u32 cut_ver = ((rtlhal->version & CHIP_VER_RTL_MASK)
 737                                         >> CHIP_VER_RTL_SHIFT);
 738         u32 intf = (rtlhal->interface == INTF_USB ? BIT(1) : BIT(0));
 739
 740         u8  board_type = ((rtlhal->board_type & BIT(4)) >> 4) << 0 | /* _GLNA */
 741                          ((rtlhal->board_type & BIT(3)) >> 3) << 1 | /* _GPA  */
 742                          ((rtlhal->board_type & BIT(7)) >> 7) << 2 | /* _ALNA */
 743                          ((rtlhal->board_type & BIT(6)) >> 6) << 3 | /* _APA  */
 744                          ((rtlhal->board_type & BIT(2)) >> 2) << 4;  /* _BT   */
 745
 746         u32 cond1 = condition1, cond2 = condition2;
 747         u32 driver1 = cut_ver << 24 |   /* CUT ver */
 748                       0 << 20 |                 /* interface 2/2 */
 749                       0x04 << 16 |              /* platform */
 750                       rtlhal->package_type << 12 |
 751                       intf << 8 |                       /* interface 1/2 */
 752                       board_type;
 753
 754         u32 driver2 = rtlhal->type_glna <<  0 |
 755                       rtlhal->type_gpa  <<  8 |
 756                       rtlhal->type_alna << 16 |
 757                       rtlhal->type_apa  << 24;
 758
 759         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 760                 "===> [8812A] CheckPositive (cond1, cond2) = (0x%X 0x%X)\n",
 761                 cond1, cond2);
 762         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 763                 "===> [8812A] CheckPositive (driver1, driver2) = (0x%X 0x%X)\n",
 764                 driver1, driver2);
 765
 766         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 767                 "       (Platform, Interface) = (0x%X, 0x%X)\n", 0x04, intf);
 768         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
 769                 "       (Board, Package) = (0x%X, 0x%X)\n",
 770                 rtlhal->board_type, rtlhal->package_type);
 771
 772         /*============== Value Defined Check ===============*/
 773         /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/
 774
 775         if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) !=
 776                 (driver1 & 0x0000F000)))
 777                 return false;
 778         if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) !=
 779                 (driver1 & 0x0F000000)))
 780                 return false;
 781
 782         /*=============== Bit Defined Check ================*/
 783         /* We don't care [31:28] */
 784
 785         cond1   &= 0x00FF0FFF;
 786         driver1 &= 0x00FF0FFF;
 787
 788         if ((cond1 & driver1) == cond1) {
 789                 u32 mask = 0;
 790
 791                 if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/
 792                         return true;
 793
 794                 if ((cond1 & BIT(0)) != 0) /*GLNA*/
 795                         mask |= 0x000000FF;
 796                 if ((cond1 & BIT(1)) != 0) /*GPA*/
 797                         mask |= 0x0000FF00;
 798                 if ((cond1 & BIT(2)) != 0) /*ALNA*/
 799                         mask |= 0x00FF0000;
 800                 if ((cond1 & BIT(3)) != 0) /*APA*/
 801                         mask |= 0xFF000000;
 802
 803                 /* BoardType of each RF path is matched*/
 804                 if ((cond2 & mask) == (driver2 & mask))
 805                         return true;
 806                 else
 807                         return false;
 808         } else
 809                 return false;
 810 }
 811
 812 static bool _rtl8821ae_check_condition(struct ieee80211_hw *hw,
 813                                        const u32 condition)
 814 {
 815         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 816         u32 _board = rtlefuse->board_type; /*need efuse define*/
 817         u32 _interface = 0x01; /* ODM_ITRF_PCIE */
 818         u32 _platform = 0x08;/* ODM_WIN */
 819         u32 cond = condition;
 820
 821         if (condition == 0xCDCDCDCD)
 822                 return true;
 823
 824         cond = condition & 0xFF;
 825         if ((_board != cond) && cond != 0xFF)
 826                 return false;
 827
 828         cond = condition & 0xFF00;
 829         cond = cond >> 8;
 830         if ((_interface & cond) == 0 && cond != 0x07)
 831                 return false;
 832
 833         cond = condition & 0xFF0000;
 834         cond = cond >> 16;
 835         if ((_platform & cond) == 0 && cond != 0x0F)
 836                 return false;
 837         return true;
 838 }
 839
 840 static void _rtl8821ae_config_rf_reg(struct ieee80211_hw *hw,
 841                                      u32 addr, u32 data,
 842                                      enum radio_path rfpath, u32 regaddr)
 843 {
 844         if (addr == 0xfe || addr == 0xffe) {
 845                 /* In order not to disturb BT music when
 846                  * wifi init.(1ant NIC only)
 847                  */
 848                 mdelay(50);
 849         } else {
 850                 rtl_set_rfreg(hw, rfpath, regaddr, RFREG_OFFSET_MASK, data);
 851                 udelay(1);
 852         }
 853 }
 854
 855 static void _rtl8821ae_config_rf_radio_a(struct ieee80211_hw *hw,
 856                                          u32 addr, u32 data)
 857 {
 858         u32 content = 0x1000; /*RF Content: radio_a_txt*/
 859         u32 maskforphyset = (u32)(content & 0xE000);
 860
 861         _rtl8821ae_config_rf_reg(hw, addr, data,
 862                                  RF90_PATH_A, addr | maskforphyset);
 863 }
 864
 865 static void _rtl8821ae_config_rf_radio_b(struct ieee80211_hw *hw,
 866                                          u32 addr, u32 data)
 867 {
 868         u32 content = 0x1001; /*RF Content: radio_b_txt*/
 869         u32 maskforphyset = (u32)(content & 0xE000);
 870
 871         _rtl8821ae_config_rf_reg(hw, addr, data,
 872                                  RF90_PATH_B, addr | maskforphyset);
 873 }
 874
 875 static void _rtl8821ae_config_bb_reg(struct ieee80211_hw *hw,
 876                                      u32 addr, u32 data)
 877 {
 878         if (addr == 0xfe)
 879                 mdelay(50);
 880         else if (addr == 0xfd)
 881                 mdelay(5);
 882         else if (addr == 0xfc)
 883                 mdelay(1);
 884         else if (addr == 0xfb)
 885                 udelay(50);
 886         else if (addr == 0xfa)
 887                 udelay(5);
 888         else if (addr == 0xf9)
 889                 udelay(1);
 890         else
 891                 rtl_set_bbreg(hw, addr, MASKDWORD, data);
 892
 893         udelay(1);
 894 }
 895
 896 static void _rtl8821ae_phy_init_tx_power_by_rate(struct ieee80211_hw *hw)
 897 {
 898         struct rtl_priv *rtlpriv = rtl_priv(hw);
 899         struct rtl_phy *rtlphy = &rtlpriv->phy;
 900         u8 band, rfpath, txnum, rate_section;
 901
 902         for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band)
 903                 for (rfpath = 0; rfpath < TX_PWR_BY_RATE_NUM_RF; ++rfpath)
 904                         for (txnum = 0; txnum < TX_PWR_BY_RATE_NUM_RF; ++txnum)
 905                                 for (rate_section = 0;
 906                                      rate_section < TX_PWR_BY_RATE_NUM_SECTION;
 907                                      ++rate_section)
 908                                         rtlphy->tx_power_by_rate_offset[band]
 909                                             [rfpath][txnum][rate_section] = 0;
 910 }
 911
 912 static void _rtl8821ae_phy_set_txpower_by_rate_base(struct ieee80211_hw *hw,
 913                                           u8 band, u8 path,
 914                                           u8 rate_section,
 915                                           u8 txnum, u8 value)
 916 {
 917         struct rtl_priv *rtlpriv = rtl_priv(hw);
 918         struct rtl_phy *rtlphy = &rtlpriv->phy;
 919
 920         if (path > RF90_PATH_D) {
 921                 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
 922                         "Invalid Rf Path %d in phy_SetTxPowerByRatBase()\n", path);
 923                 return;
 924         }
 925
 926         if (band == BAND_ON_2_4G) {
 927                 switch (rate_section) {
 928                 case CCK:
 929                         rtlphy->txpwr_by_rate_base_24g[path][txnum][0] = value;
 930                         break;
 931                 case OFDM:
 932                         rtlphy->txpwr_by_rate_base_24g[path][txnum][1] = value;
 933                         break;
 934                 case HT_MCS0_MCS7:
 935                         rtlphy->txpwr_by_rate_base_24g[path][txnum][2] = value;
 936                         break;
 937                 case HT_MCS8_MCS15:
 938                         rtlphy->txpwr_by_rate_base_24g[path][txnum][3] = value;
 939                         break;
 940                 case VHT_1SSMCS0_1SSMCS9:
 941                         rtlphy->txpwr_by_rate_base_24g[path][txnum][4] = value;
 942                         break;
 943                 case VHT_2SSMCS0_2SSMCS9:
 944                         rtlphy->txpwr_by_rate_base_24g[path][txnum][5] = value;
 945                         break;
 946                 default:
 947                         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
 948                                 "Invalid RateSection %d in Band 2.4G,Rf Path %d, %dTx in PHY_SetTxPowerByRateBase()\n",
 949                                 rate_section, path, txnum);
 950                         break;
 951                 }
 952         } else if (band == BAND_ON_5G) {
 953                 switch (rate_section) {
 954                 case OFDM:
 955                         rtlphy->txpwr_by_rate_base_5g[path][txnum][0] = value;
 956                         break;
 957                 case HT_MCS0_MCS7:
 958                         rtlphy->txpwr_by_rate_base_5g[path][txnum][1] = value;
 959                         break;
 960                 case HT_MCS8_MCS15:
 961                         rtlphy->txpwr_by_rate_base_5g[path][txnum][2] = value;
 962                         break;
 963                 case VHT_1SSMCS0_1SSMCS9:
 964                         rtlphy->txpwr_by_rate_base_5g[path][txnum][3] = value;
 965                         break;
 966                 case VHT_2SSMCS0_2SSMCS9:
 967                         rtlphy->txpwr_by_rate_base_5g[path][txnum][4] = value;
 968                         break;
 969                 default:
 970                         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
 971                                 "Invalid RateSection %d in Band 5G, Rf Path %d, %dTx in PHY_SetTxPowerByRateBase()\n",
 972                                 rate_section, path, txnum);
 973                         break;
 974                 }
 975         } else {
 976                 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
 977                         "Invalid Band %d in PHY_SetTxPowerByRateBase()\n", band);
 978         }
 979 }
 980
 981 static u8 _rtl8821ae_phy_get_txpower_by_rate_base(struct ieee80211_hw *hw,
 982                                                   u8 band, u8 path,
 983                                                   u8 txnum, u8 rate_section)
 984 {
 985         struct rtl_priv *rtlpriv = rtl_priv(hw);
 986         struct rtl_phy *rtlphy = &rtlpriv->phy;
 987         u8 value = 0;
 988
 989         if (path > RF90_PATH_D) {
 990                 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
 991                         "Invalid Rf Path %d in PHY_GetTxPowerByRateBase()\n",
 992                         path);
 993                 return 0;
 994         }
 995
 996         if (band == BAND_ON_2_4G) {
 997                 switch (rate_section) {
 998                 case CCK:
 999                         value = rtlphy->txpwr_by_rate_base_24g[path][txnum][0];
1000                         break;
1001                 case OFDM:
1002                         value = rtlphy->txpwr_by_rate_base_24g[path][txnum][1];
1003                         break;
1004                 case HT_MCS0_MCS7:
1005                         value = rtlphy->txpwr_by_rate_base_24g[path][txnum][2];
1006                         break;
1007                 case HT_MCS8_MCS15:
1008                         value = rtlphy->txpwr_by_rate_base_24g[path][txnum][3];
1009                         break;
1010                 case VHT_1SSMCS0_1SSMCS9:
1011                         value = rtlphy->txpwr_by_rate_base_24g[path][txnum][4];
1012                         break;
1013                 case VHT_2SSMCS0_2SSMCS9:
1014                         value = rtlphy->txpwr_by_rate_base_24g[path][txnum][5];
1015                         break;
1016                 default:
1017                         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1018                                 "Invalid RateSection %d in Band 2.4G, Rf Path %d, %dTx in PHY_GetTxPowerByRateBase()\n",
1019                                 rate_section, path, txnum);
1020                         break;
1021                 }
1022         } else if (band == BAND_ON_5G) {
1023                 switch (rate_section) {
1024                 case OFDM:
1025                         value = rtlphy->txpwr_by_rate_base_5g[path][txnum][0];
1026                         break;
1027                 case HT_MCS0_MCS7:
1028                         value = rtlphy->txpwr_by_rate_base_5g[path][txnum][1];
1029                         break;
1030                 case HT_MCS8_MCS15:
1031                         value = rtlphy->txpwr_by_rate_base_5g[path][txnum][2];
1032                         break;
1033                 case VHT_1SSMCS0_1SSMCS9:
1034                         value = rtlphy->txpwr_by_rate_base_5g[path][txnum][3];
1035                         break;
1036                 case VHT_2SSMCS0_2SSMCS9:
1037                         value = rtlphy->txpwr_by_rate_base_5g[path][txnum][4];
1038                         break;
1039                 default:
1040                         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1041                                 "Invalid RateSection %d in Band 5G, Rf Path %d, %dTx in PHY_GetTxPowerByRateBase()\n",
1042                                 rate_section, path, txnum);
1043                         break;
1044                 }
1045         } else {
1046                 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1047                         "Invalid Band %d in PHY_GetTxPowerByRateBase()\n", band);
1048         }
1049
1050         return value;
1051 }
1052
1053 static void _rtl8821ae_phy_store_txpower_by_rate_base(struct ieee80211_hw *hw)
1054 {
1055         struct rtl_priv *rtlpriv = rtl_priv(hw);
1056         struct rtl_phy *rtlphy = &rtlpriv->phy;
1057         u16 rawvalue = 0;
1058         u8 base = 0, path = 0;
1059
1060         for (path = RF90_PATH_A; path <= RF90_PATH_B; ++path) {
1061                 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][0] >> 24) & 0xFF;
1062                 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1063                 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, CCK, RF_1TX, base);
1064
1065                 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][2] >> 24) & 0xFF;
1066                 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1067                 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, OFDM, RF_1TX, base);
1068
1069                 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][4] >> 24) & 0xFF;
1070                 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1071                 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, HT_MCS0_MCS7, RF_1TX, base);
1072
1073                 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_2TX][6] >> 24) & 0xFF;
1074                 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1075                 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, HT_MCS8_MCS15, RF_2TX, base);
1076
1077                 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][8] >> 24) & 0xFF;
1078                 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1079                 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, VHT_1SSMCS0_1SSMCS9, RF_1TX, base);
1080
1081                 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_2TX][11] >> 8) & 0xFF;
1082                 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1083                 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, VHT_2SSMCS0_2SSMCS9, RF_2TX, base);
1084
1085                 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_1TX][2] >> 24) & 0xFF;
1086                 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1087                 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, OFDM, RF_1TX, base);
1088
1089                 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_1TX][4] >> 24) & 0xFF;
1090                 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1091                 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, HT_MCS0_MCS7, RF_1TX, base);
1092
1093                 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_2TX][6] >> 24) & 0xFF;
1094                 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1095                 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, HT_MCS8_MCS15, RF_2TX, base);
1096
1097                 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_1TX][8] >> 24) & 0xFF;
1098                 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1099                 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, VHT_1SSMCS0_1SSMCS9, RF_1TX, base);
1100
1101                 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_2TX][11] >> 8) & 0xFF;
1102                 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1103                 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, VHT_2SSMCS0_2SSMCS9, RF_2TX, base);
1104         }
1105 }
1106
1107 static void _phy_convert_txpower_dbm_to_relative_value(u32 *data, u8 start,
1108                                                 u8 end, u8 base_val)
1109 {
1110         int i;
1111         u8 temp_value = 0;
1112         u32 temp_data = 0;
1113
1114         for (i = 3; i >= 0; --i) {
1115                 if (i >= start && i <= end) {
1116                         /* Get the exact value */
1117                         temp_value = (u8)(*data >> (i * 8)) & 0xF;
1118                         temp_value += ((u8)((*data >> (i * 8 + 4)) & 0xF)) * 10;
1119
1120                         /* Change the value to a relative value */
1121                         temp_value = (temp_value > base_val) ? temp_value -
1122                                         base_val : base_val - temp_value;
1123                 } else {
1124                         temp_value = (u8)(*data >> (i * 8)) & 0xFF;
1125                 }
1126                 temp_data <<= 8;
1127                 temp_data |= temp_value;
1128         }
1129         *data = temp_data;
1130 }
1131
1132 static void _rtl8812ae_phy_cross_reference_ht_and_vht_txpower_limit(struct ieee80211_hw *hw)
1133 {
1134         struct rtl_priv *rtlpriv = rtl_priv(hw);
1135         struct rtl_phy *rtlphy = &rtlpriv->phy;
1136         u8 regulation, bw, channel, rate_section;
1137         s8 temp_pwrlmt = 0;
1138
1139         for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {
1140                 for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) {
1141                         for (channel = 0; channel < CHANNEL_MAX_NUMBER_5G; ++channel) {
1142                                 for (rate_section = 0; rate_section < MAX_RATE_SECTION_NUM; ++rate_section) {
1143                                         temp_pwrlmt = rtlphy->txpwr_limit_5g[regulation]
1144                                                 [bw][rate_section][channel][RF90_PATH_A];
1145                                         if (temp_pwrlmt == MAX_POWER_INDEX) {
1146                                                 if (bw == 0 || bw == 1) { /*5G 20M 40M VHT and HT can cross reference*/
1147                                                         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1148                                                                 "No power limit table of the specified band %d, bandwidth %d, ratesection %d, channel %d, rf path %d\n",
1149                                                                 1, bw, rate_section, channel, RF90_PATH_A);
1150                                                         if (rate_section == 2) {
1151                                                                 rtlphy->txpwr_limit_5g[regulation][bw][2][channel][RF90_PATH_A] =
1152                                                                         rtlphy->txpwr_limit_5g[regulation][bw][4][channel][RF90_PATH_A];
1153                                                         } else if (rate_section == 4) {
1154                                                                 rtlphy->txpwr_limit_5g[regulation][bw][4][channel][RF90_PATH_A] =
1155                                                                         rtlphy->txpwr_limit_5g[regulation][bw][2][channel][RF90_PATH_A];
1156                                                         } else if (rate_section == 3) {
1157                                                                 rtlphy->txpwr_limit_5g[regulation][bw][3][channel][RF90_PATH_A] =
1158                                                                         rtlphy->txpwr_limit_5g[regulation][bw][5][channel][RF90_PATH_A];
1159                                                         } else if (rate_section == 5) {
1160                                                                 rtlphy->txpwr_limit_5g[regulation][bw][5][channel][RF90_PATH_A] =
1161                                                                         rtlphy->txpwr_limit_5g[regulation][bw][3][channel][RF90_PATH_A];
1162                                                         }
1163
1164                                                         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1165                                                                 "use other value %d\n",
1166                                                                 temp_pwrlmt);
1167                                                 }
1168                                         }
1169                                 }
1170                         }
1171                 }
1172         }
1173 }
1174
1175 static u8 _rtl8812ae_phy_get_txpower_by_rate_base_index(struct ieee80211_hw *hw,
1176                                                    enum band_type band, u8 rate)
1177 {
1178         struct rtl_priv *rtlpriv = rtl_priv(hw);
1179         u8 index = 0;
1180         if (band == BAND_ON_2_4G) {
1181                 switch (rate) {
1182                 case MGN_1M:
1183                 case MGN_2M:
1184                 case MGN_5_5M:
1185                 case MGN_11M:
1186                         index = 0;
1187                         break;
1188
1189                 case MGN_6M:
1190                 case MGN_9M:
1191                 case MGN_12M:
1192                 case MGN_18M:
1193                 case MGN_24M:
1194                 case MGN_36M:
1195                 case MGN_48M:
1196                 case MGN_54M:
1197                         index = 1;
1198                         break;
1199
1200                 case MGN_MCS0:
1201                 case MGN_MCS1:
1202                 case MGN_MCS2:
1203                 case MGN_MCS3:
1204                 case MGN_MCS4:
1205                 case MGN_MCS5:
1206                 case MGN_MCS6:
1207                 case MGN_MCS7:
1208                         index = 2;
1209                         break;
1210
1211                 case MGN_MCS8:
1212                 case MGN_MCS9:
1213                 case MGN_MCS10:
1214                 case MGN_MCS11:
1215                 case MGN_MCS12:
1216                 case MGN_MCS13:
1217                 case MGN_MCS14:
1218                 case MGN_MCS15:
1219                         index = 3;
1220                         break;
1221
1222                 default:
1223                         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1224                                 "Wrong rate 0x%x to obtain index in 2.4G in PHY_GetTxPowerByRateBaseIndex()\n",
1225                                 rate);
1226                         break;
1227                 }
1228         } else if (band == BAND_ON_5G) {
1229                 switch (rate) {
1230                 case MGN_6M:
1231                 case MGN_9M:
1232                 case MGN_12M:
1233                 case MGN_18M:
1234                 case MGN_24M:
1235                 case MGN_36M:
1236                 case MGN_48M:
1237                 case MGN_54M:
1238                         index = 0;
1239                         break;
1240
1241                 case MGN_MCS0:
1242                 case MGN_MCS1:
1243                 case MGN_MCS2:
1244                 case MGN_MCS3:
1245                 case MGN_MCS4:
1246                 case MGN_MCS5:
1247                 case MGN_MCS6:
1248                 case MGN_MCS7:
1249                         index = 1;
1250                         break;
1251
1252                 case MGN_MCS8:
1253                 case MGN_MCS9:
1254                 case MGN_MCS10:
1255                 case MGN_MCS11:
1256                 case MGN_MCS12:
1257                 case MGN_MCS13:
1258                 case MGN_MCS14:
1259                 case MGN_MCS15:
1260                         index = 2;
1261                         break;
1262
1263                 case MGN_VHT1SS_MCS0:
1264                 case MGN_VHT1SS_MCS1:
1265                 case MGN_VHT1SS_MCS2:
1266                 case MGN_VHT1SS_MCS3:
1267                 case MGN_VHT1SS_MCS4:
1268                 case MGN_VHT1SS_MCS5:
1269                 case MGN_VHT1SS_MCS6:
1270                 case MGN_VHT1SS_MCS7:
1271                 case MGN_VHT1SS_MCS8:
1272                 case MGN_VHT1SS_MCS9:
1273                         index = 3;
1274                         break;
1275
1276                 case MGN_VHT2SS_MCS0:
1277                 case MGN_VHT2SS_MCS1:
1278                 case MGN_VHT2SS_MCS2:
1279                 case MGN_VHT2SS_MCS3:
1280                 case MGN_VHT2SS_MCS4:
1281                 case MGN_VHT2SS_MCS5:
1282                 case MGN_VHT2SS_MCS6:
1283                 case MGN_VHT2SS_MCS7:
1284                 case MGN_VHT2SS_MCS8:
1285                 case MGN_VHT2SS_MCS9:
1286                         index = 4;
1287                         break;
1288
1289                 default:
1290                         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1291                                 "Wrong rate 0x%x to obtain index in 5G in PHY_GetTxPowerByRateBaseIndex()\n",
1292                                 rate);
1293                         break;
1294                 }
1295         }
1296
1297         return index;
1298 }
1299
1300 static void _rtl8812ae_phy_convert_txpower_limit_to_power_index(struct ieee80211_hw *hw)
1301 {
1302         struct rtl_priv *rtlpriv = rtl_priv(hw);
1303         struct rtl_phy *rtlphy = &rtlpriv->phy;
1304         u8 bw40_pwr_base_dbm2_4G, bw40_pwr_base_dbm5G;
1305         u8 regulation, bw, channel, rate_section;
1306         u8 base_index2_4G = 0;
1307         u8 base_index5G = 0;
1308         s8 temp_value = 0, temp_pwrlmt = 0;
1309         u8 rf_path = 0;
1310
1311         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1312                 "=====> _rtl8812ae_phy_convert_txpower_limit_to_power_index()\n");
1313
1314         _rtl8812ae_phy_cross_reference_ht_and_vht_txpower_limit(hw);
1315
1316         for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {
1317                 for (bw = 0; bw < MAX_2_4G_BANDWIDTH_NUM; ++bw) {
1318                         for (channel = 0; channel < CHANNEL_MAX_NUMBER_2G; ++channel) {
1319                                 for (rate_section = 0; rate_section < MAX_RATE_SECTION_NUM; ++rate_section) {
1320                                         /* obtain the base dBm values in 2.4G band
1321                                          CCK => 11M, OFDM => 54M, HT 1T => MCS7, HT 2T => MCS15*/
1322                                         if (rate_section == 0) { /*CCK*/
1323                                                 base_index2_4G =
1324                                                         _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1325                                                         BAND_ON_2_4G, MGN_11M);
1326                                         } else if (rate_section == 1) { /*OFDM*/
1327                                                 base_index2_4G =
1328                                                         _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1329                                                         BAND_ON_2_4G, MGN_54M);
1330                                         } else if (rate_section == 2) { /*HT IT*/
1331                                                 base_index2_4G =
1332                                                         _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1333                                                         BAND_ON_2_4G, MGN_MCS7);
1334                                         } else if (rate_section == 3) { /*HT 2T*/
1335                                                 base_index2_4G =
1336                                                         _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1337                                                         BAND_ON_2_4G, MGN_MCS15);
1338                                         }
1339
1340                                         temp_pwrlmt = rtlphy->txpwr_limit_2_4g[regulation]
1341                                                 [bw][rate_section][channel][RF90_PATH_A];
1342
1343                                         for (rf_path = RF90_PATH_A;
1344                                                 rf_path < MAX_RF_PATH_NUM;
1345                                                 ++rf_path) {
1346                                                 if (rate_section == 3)
1347                                                         bw40_pwr_base_dbm2_4G =
1348                                                         rtlphy->txpwr_by_rate_base_24g[rf_path][RF_2TX][base_index2_4G];
1349                                                 else
1350                                                         bw40_pwr_base_dbm2_4G =
1351                                                         rtlphy->txpwr_by_rate_base_24g[rf_path][RF_1TX][base_index2_4G];
1352
1353                                                 if (temp_pwrlmt != MAX_POWER_INDEX) {
1354                                                         temp_value = temp_pwrlmt - bw40_pwr_base_dbm2_4G;
1355                                                         rtlphy->txpwr_limit_2_4g[regulation]
1356                                                                 [bw][rate_section][channel][rf_path] =
1357                                                                 temp_value;
1358                                                 }
1359
1360                                                 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1361                                                         "TxPwrLimit_2_4G[regulation %d][bw %d][rateSection %d][channel %d] = %d\n(TxPwrLimit in dBm %d - BW40PwrLmt2_4G[channel %d][rfpath %d] %d)\n",
1362                                                         regulation, bw, rate_section, channel,
1363                                                         rtlphy->txpwr_limit_2_4g[regulation][bw]
1364                                                         [rate_section][channel][rf_path], (temp_pwrlmt == 63)
1365                                                         ? 0 : temp_pwrlmt/2, channel, rf_path,
1366                                                         bw40_pwr_base_dbm2_4G);
1367                                         }
1368                                 }
1369                         }
1370                 }
1371         }
1372         for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {
1373                 for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) {
1374                         for (channel = 0; channel < CHANNEL_MAX_NUMBER_5G; ++channel) {
1375                                 for (rate_section = 0; rate_section < MAX_RATE_SECTION_NUM; ++rate_section) {
1376                                         /* obtain the base dBm values in 5G band
1377                                          OFDM => 54M, HT 1T => MCS7, HT 2T => MCS15,
1378                                         VHT => 1SSMCS7, VHT 2T => 2SSMCS7*/
1379                                         if (rate_section == 1) { /*OFDM*/
1380                                                 base_index5G =
1381                                                         _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1382                                                         BAND_ON_5G, MGN_54M);
1383                                         } else if (rate_section == 2) { /*HT 1T*/
1384                                                 base_index5G =
1385                                                         _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1386                                                         BAND_ON_5G, MGN_MCS7);
1387                                         } else if (rate_section == 3) { /*HT 2T*/
1388                                                 base_index5G =
1389                                                         _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1390                                                         BAND_ON_5G, MGN_MCS15);
1391                                         } else if (rate_section == 4) { /*VHT 1T*/
1392                                                 base_index5G =
1393                                                         _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1394                                                         BAND_ON_5G, MGN_VHT1SS_MCS7);
1395                                         } else if (rate_section == 5) { /*VHT 2T*/
1396                                                 base_index5G =
1397                                                         _rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1398                                                         BAND_ON_5G, MGN_VHT2SS_MCS7);
1399                                         }
1400
1401                                         temp_pwrlmt = rtlphy->txpwr_limit_5g[regulation]
1402                                                 [bw][rate_section][channel]
1403                                                 [RF90_PATH_A];
1404
1405                                         for (rf_path = RF90_PATH_A;
1406                                              rf_path < MAX_RF_PATH_NUM;
1407                                              ++rf_path) {
1408                                                 if (rate_section == 3 || rate_section == 5)
1409                                                         bw40_pwr_base_dbm5G =
1410                                                         rtlphy->txpwr_by_rate_base_5g[rf_path]
1411                                                         [RF_2TX][base_index5G];
1412                                                 else
1413                                                         bw40_pwr_base_dbm5G =
1414                                                         rtlphy->txpwr_by_rate_base_5g[rf_path]
1415                                                         [RF_1TX][base_index5G];
1416
1417                                                 if (temp_pwrlmt != MAX_POWER_INDEX) {
1418                                                         temp_value =
1419                                                                 temp_pwrlmt - bw40_pwr_base_dbm5G;
1420                                                         rtlphy->txpwr_limit_5g[regulation]
1421                                                                 [bw][rate_section][channel]
1422                                                                 [rf_path] = temp_value;
1423                                                 }
1424
1425                                                 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1426                                                         "TxPwrLimit_5G[regulation %d][bw %d][rateSection %d][channel %d] =%d\n(TxPwrLimit in dBm %d - BW40PwrLmt5G[chnl group %d][rfpath %d] %d)\n",
1427                                                         regulation, bw, rate_section,
1428                                                         channel, rtlphy->txpwr_limit_5g[regulation]
1429                                                         [bw][rate_section][channel][rf_path],
1430                                                         temp_pwrlmt, channel, rf_path, bw40_pwr_base_dbm5G);
1431                                         }
1432                                 }
1433                         }
1434                 }
1435         }
1436         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1437                 "<===== %s()\n", __func__);
1438 }
1439
1440 static void _rtl8821ae_phy_init_txpower_limit(struct ieee80211_hw *hw)
1441 {
1442         struct rtl_priv *rtlpriv = rtl_priv(hw);
1443         struct rtl_phy *rtlphy = &rtlpriv->phy;
1444         u8 i, j, k, l, m;
1445
1446         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1447                 "=====>`%s()!\n", __func__);
1448
1449         for (i = 0; i < MAX_REGULATION_NUM; ++i) {
1450                 for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j)
1451                         for (k = 0; k < MAX_RATE_SECTION_NUM; ++k)
1452                                 for (m = 0; m < CHANNEL_MAX_NUMBER_2G; ++m)
1453                                         for (l = 0; l < MAX_RF_PATH_NUM; ++l)
1454                                                 rtlphy->txpwr_limit_2_4g
1455                                                                 [i][j][k][m][l]
1456                                                         = MAX_POWER_INDEX;
1457         }
1458         for (i = 0; i < MAX_REGULATION_NUM; ++i) {
1459                 for (j = 0; j < MAX_5G_BANDWIDTH_NUM; ++j)
1460                         for (k = 0; k < MAX_RATE_SECTION_NUM; ++k)
1461                                 for (m = 0; m < CHANNEL_MAX_NUMBER_5G; ++m)
1462                                         for (l = 0; l < MAX_RF_PATH_NUM; ++l)
1463                                                 rtlphy->txpwr_limit_5g
1464                                                                 [i][j][k][m][l]
1465                                                         = MAX_POWER_INDEX;
1466         }
1467
1468         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1469                 "<===== %s()!\n", __func__);
1470 }
1471
1472 static void _rtl8821ae_phy_convert_txpower_dbm_to_relative_value(struct ieee80211_hw *hw)
1473 {
1474         struct rtl_priv *rtlpriv = rtl_priv(hw);
1475         struct rtl_phy *rtlphy = &rtlpriv->phy;
1476         u8 base = 0, rfpath = 0;
1477
1478         for (rfpath = RF90_PATH_A; rfpath <= RF90_PATH_B; ++rfpath) {
1479                 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_1TX, CCK);
1480                 _phy_convert_txpower_dbm_to_relative_value(
1481                         &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][0],
1482                         0, 3, base);
1483
1484                 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_1TX, OFDM);
1485                 _phy_convert_txpower_dbm_to_relative_value(
1486                         &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][1],
1487                         0, 3, base);
1488                 _phy_convert_txpower_dbm_to_relative_value(
1489                         &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][2],
1490                         0, 3, base);
1491
1492                 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_1TX, HT_MCS0_MCS7);
1493                 _phy_convert_txpower_dbm_to_relative_value(
1494                         &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][3],
1495                         0, 3, base);
1496                 _phy_convert_txpower_dbm_to_relative_value(
1497                         &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][4],
1498                         0, 3, base);
1499
1500                 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_2TX, HT_MCS8_MCS15);
1501
1502                 _phy_convert_txpower_dbm_to_relative_value(
1503                         &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_2TX][5],
1504                         0, 3, base);
1505
1506                 _phy_convert_txpower_dbm_to_relative_value(
1507                         &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_2TX][6],
1508                         0, 3, base);
1509
1510                 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_1TX, VHT_1SSMCS0_1SSMCS9);
1511                 _phy_convert_txpower_dbm_to_relative_value(
1512                         &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][7],
1513                         0, 3, base);
1514                 _phy_convert_txpower_dbm_to_relative_value(
1515                         &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][8],
1516                         0, 3, base);
1517                 _phy_convert_txpower_dbm_to_relative_value(
1518                         &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][9],
1519                         0, 1, base);
1520
1521                 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_2TX, VHT_2SSMCS0_2SSMCS9);
1522                 _phy_convert_txpower_dbm_to_relative_value(
1523                         &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][9],
1524                         2, 3, base);
1525                 _phy_convert_txpower_dbm_to_relative_value(
1526                         &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_2TX][10],
1527                         0, 3, base);
1528                 _phy_convert_txpower_dbm_to_relative_value(
1529                         &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_2TX][11],
1530                         0, 3, base);
1531
1532                 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_1TX, OFDM);
1533                 _phy_convert_txpower_dbm_to_relative_value(
1534                         &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][1],
1535                         0, 3, base);
1536                 _phy_convert_txpower_dbm_to_relative_value(
1537                         &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][2],
1538                         0, 3, base);
1539
1540                 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_1TX, HT_MCS0_MCS7);
1541                 _phy_convert_txpower_dbm_to_relative_value(
1542                         &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][3],
1543                         0, 3, base);
1544                 _phy_convert_txpower_dbm_to_relative_value(
1545                         &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][4],
1546                         0, 3, base);
1547
1548                 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_2TX, HT_MCS8_MCS15);
1549                 _phy_convert_txpower_dbm_to_relative_value(
1550                         &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_2TX][5],
1551                         0, 3, base);
1552                 _phy_convert_txpower_dbm_to_relative_value(
1553                         &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_2TX][6],
1554                         0, 3, base);
1555
1556                 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_1TX, VHT_1SSMCS0_1SSMCS9);
1557                 _phy_convert_txpower_dbm_to_relative_value(
1558                         &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][7],
1559                         0, 3, base);
1560                 _phy_convert_txpower_dbm_to_relative_value(
1561                         &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][8],
1562                         0, 3, base);
1563                 _phy_convert_txpower_dbm_to_relative_value(
1564                         &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][9],
1565                         0, 1, base);
1566
1567                 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_2TX, VHT_2SSMCS0_2SSMCS9);
1568                 _phy_convert_txpower_dbm_to_relative_value(
1569                         &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][9],
1570                         2, 3, base);
1571                 _phy_convert_txpower_dbm_to_relative_value(
1572                         &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_2TX][10],
1573                         0, 3, base);
1574                 _phy_convert_txpower_dbm_to_relative_value(
1575                         &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_2TX][11],
1576                         0, 3, base);
1577         }
1578
1579         rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
1580                 "<===_rtl8821ae_phy_convert_txpower_dbm_to_relative_value()\n");
1581 }
1582
1583 static void _rtl8821ae_phy_txpower_by_rate_configuration(struct ieee80211_hw *hw)
1584 {
1585         _rtl8821ae_phy_store_txpower_by_rate_base(hw);
1586         _rtl8821ae_phy_convert_txpower_dbm_to_relative_value(hw);
1587 }
1588
1589 /* string is in decimal */
1590 static bool _rtl8812ae_get_integer_from_string(char *str, u8 *pint)
1591 {
1592         u16 i = 0;
1593         *pint = 0;
1594
1595         while (str[i] != '\0') {
1596                 if (str[i] >= '0' && str[i] <= '9') {
1597                         *pint *= 10;
1598                         *pint += (str[i] - '0');
1599                 } else {
1600                         return false;
1601                 }
1602                 ++i;
1603         }
1604
1605         return true;
1606 }
1607
1608 static bool _rtl8812ae_eq_n_byte(u8 *str1, u8 *str2, u32 num)
1609 {
1610         if (num == 0)
1611                 return false;
1612         while (num > 0) {
1613                 num--;
1614                 if (str1[num] != str2[num])
1615                         return false;
1616         }
1617         return true;
1618 }
1619
1620 static s8 _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(struct ieee80211_hw *hw,
1621                                               u8 band, u8 channel)
1622 {
1623         struct rtl_priv *rtlpriv = rtl_priv(hw);
1624         s8 channel_index = -1;
1625         u8  i = 0;
1626
1627         if (band == BAND_ON_2_4G)
1628                 channel_index = channel - 1;
1629         else if (band == BAND_ON_5G) {
1630                 for (i = 0; i < sizeof(channel5g)/sizeof(u8); ++i) {
1631                         if (channel5g[i] == channel)
1632                                 channel_index = i;
1633                 }
1634         } else
1635                 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "Invalid Band %d in %s\n",
1636                         band,  __func__);
1637
1638         if (channel_index == -1)
1639                 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
1640                         "Invalid Channel %d of Band %d in %s\n", channel,
1641                         band, __func__);
1642
1643         return channel_index;
1644 }
1645
1646 static void _rtl8812ae_phy_set_txpower_limit(struct ieee80211_hw *hw, u8 *pregulation,
1647                                       u8 *pband, u8 *pbandwidth,
1648                                       u8 *prate_section, u8 *prf_path,
1649                                       u8 *pchannel, u8 *ppower_limit)
1650 {
1651         struct rtl_priv *rtlpriv = rtl_priv(hw);
1652         struct rtl_phy *rtlphy = &rtlpriv->phy;
1653         u8 regulation = 0, bandwidth = 0, rate_section = 0, channel;
1654         u8 channel_index;
1655         s8 power_limit = 0, prev_power_limit, ret;
1656
1657         if (!_rtl8812ae_get_integer_from_string((char *)pchannel, &channel) ||
1658             !_rtl8812ae_get_integer_from_string((char *)ppower_limit,
1659                                                 &power_limit)) {
1660                 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1661                         "Illegal index of pwr_lmt table [chnl %d][val %d]\n",
1662                         channel, power_limit);
1663         }
1664
1665         power_limit = power_limit > MAX_POWER_INDEX ?
1666                       MAX_POWER_INDEX : power_limit;
1667
1668         if (_rtl8812ae_eq_n_byte(pregulation, (u8 *)("FCC"), 3))
1669                 regulation = 0;
1670         else if (_rtl8812ae_eq_n_byte(pregulation, (u8 *)("MKK"), 3))
1671                 regulation = 1;
1672         else if (_rtl8812ae_eq_n_byte(pregulation, (u8 *)("ETSI"), 4))
1673                 regulation = 2;
1674         else if (_rtl8812ae_eq_n_byte(pregulation, (u8 *)("WW13"), 4))
1675                 regulation = 3;
1676
1677         if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("CCK"), 3))
1678                 rate_section = 0;
1679         else if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("OFDM"), 4))
1680                 rate_section = 1;
1681         else if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("HT"), 2) &&
1682                  _rtl8812ae_eq_n_byte(prf_path, (u8 *)("1T"), 2))
1683                 rate_section = 2;
1684         else if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("HT"), 2) &&
1685                  _rtl8812ae_eq_n_byte(prf_path, (u8 *)("2T"), 2))
1686                 rate_section = 3;
1687         else if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("VHT"), 3) &&
1688                  _rtl8812ae_eq_n_byte(prf_path, (u8 *)("1T"), 2))
1689                 rate_section = 4;
1690         else if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("VHT"), 3) &&
1691                  _rtl8812ae_eq_n_byte(prf_path, (u8 *)("2T"), 2))
1692                 rate_section = 5;
1693
1694         if (_rtl8812ae_eq_n_byte(pbandwidth, (u8 *)("20M"), 3))
1695                 bandwidth = 0;
1696         else if (_rtl8812ae_eq_n_byte(pbandwidth, (u8 *)("40M"), 3))
1697                 bandwidth = 1;
1698         else if (_rtl8812ae_eq_n_byte(pbandwidth, (u8 *)("80M"), 3))
1699                 bandwidth = 2;
1700         else if (_rtl8812ae_eq_n_byte(pbandwidth, (u8 *)("160M"), 4))
1701                 bandwidth = 3;
1702
1703         if (_rtl8812ae_eq_n_byte(pband, (u8 *)("2.4G"), 4)) {
1704                 ret = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw,
1705                                                                BAND_ON_2_4G,
1706                                                                channel);
1707
1708                 if (ret == -1)
1709                         return;
1710
1711                 channel_index = ret;
1712
1713                 prev_power_limit = rtlphy->txpwr_limit_2_4g[regulation]
1714                                                 [bandwidth][rate_section]
1715                                                 [channel_index][RF90_PATH_A];
1716
1717                 if (power_limit < prev_power_limit)
1718                         rtlphy->txpwr_limit_2_4g[regulation][bandwidth]
1719                                 [rate_section][channel_index][RF90_PATH_A] =
1720                                                                    power_limit;
1721
1722                 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1723                         "2.4G [regula %d][bw %d][sec %d][chnl %d][val %d]\n",
1724                         regulation, bandwidth, rate_section, channel_index,
1725                         rtlphy->txpwr_limit_2_4g[regulation][bandwidth]
1726                                 [rate_section][channel_index][RF90_PATH_A]);
1727         } else if (_rtl8812ae_eq_n_byte(pband, (u8 *)("5G"), 2)) {
1728                 ret = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw,
1729                                                                BAND_ON_5G,
1730                                                                channel);
1731
1732                 if (ret == -1)
1733                         return;
1734
1735                 channel_index = ret;
1736
1737                 prev_power_limit = rtlphy->txpwr_limit_5g[regulation][bandwidth]
1738                                                 [rate_section][channel_index]
1739                                                 [RF90_PATH_A];
1740
1741                 if (power_limit < prev_power_limit)
1742                         rtlphy->txpwr_limit_5g[regulation][bandwidth]
1743                         [rate_section][channel_index][RF90_PATH_A] = power_limit;
1744
1745                 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1746                         "5G: [regul %d][bw %d][sec %d][chnl %d][val %d]\n",
1747                         regulation, bandwidth, rate_section, channel,
1748                         rtlphy->txpwr_limit_5g[regulation][bandwidth]
1749                                 [rate_section][channel_index][RF90_PATH_A]);
1750         } else {
1751                 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1752                         "Cannot recognize the band info in %s\n", pband);
1753                 return;
1754         }
1755 }
1756
1757 static void _rtl8812ae_phy_config_bb_txpwr_lmt(struct ieee80211_hw *hw,
1758                                           u8 *regulation, u8 *band,
1759                                           u8 *bandwidth, u8 *rate_section,
1760                                           u8 *rf_path, u8 *channel,
1761                                           u8 *power_limit)
1762 {
1763         _rtl8812ae_phy_set_txpower_limit(hw, regulation, band, bandwidth,
1764                                          rate_section, rf_path, channel,
1765                                          power_limit);
1766 }
1767
1768 static void _rtl8821ae_phy_read_and_config_txpwr_lmt(struct ieee80211_hw *hw)
1769 {
1770         struct rtl_priv *rtlpriv = rtl_priv(hw);
1771         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1772         u32 i = 0;
1773         u32 array_len;
1774         u8 **array;
1775
1776         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1777                 array_len = RTL8812AE_TXPWR_LMT_ARRAY_LEN;
1778                 array = RTL8812AE_TXPWR_LMT;
1779         } else {
1780                 array_len = RTL8821AE_TXPWR_LMT_ARRAY_LEN;
1781                 array = RTL8821AE_TXPWR_LMT;
1782         }
1783
1784         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "\n");
1785
1786         for (i = 0; i < array_len; i += 7) {
1787                 u8 *regulation = array[i];
1788                 u8 *band = array[i+1];
1789                 u8 *bandwidth = array[i+2];
1790                 u8 *rate = array[i+3];
1791                 u8 *rf_path = array[i+4];
1792                 u8 *chnl = array[i+5];
1793                 u8 *val = array[i+6];
1794
1795                 _rtl8812ae_phy_config_bb_txpwr_lmt(hw, regulation, band,
1796                                                    bandwidth, rate, rf_path,
1797                                                    chnl, val);
1798         }
1799 }
1800
1801 static bool _rtl8821ae_phy_bb8821a_config_parafile(struct ieee80211_hw *hw)
1802 {
1803         struct rtl_priv *rtlpriv = rtl_priv(hw);
1804         struct rtl_phy *rtlphy = &rtlpriv->phy;
1805         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1806         bool rtstatus;
1807
1808         _rtl8821ae_phy_init_txpower_limit(hw);
1809
1810         /* RegEnableTxPowerLimit == 1 for 8812a & 8821a */
1811         if (rtlefuse->eeprom_regulatory != 2)
1812                 _rtl8821ae_phy_read_and_config_txpwr_lmt(hw);
1813
1814         rtstatus = _rtl8821ae_phy_config_bb_with_headerfile(hw,
1815                                                        BASEBAND_CONFIG_PHY_REG);
1816         if (!rtstatus) {
1817                 pr_err("Write BB Reg Fail!!\n");
1818                 return false;
1819         }
1820         _rtl8821ae_phy_init_tx_power_by_rate(hw);
1821         if (rtlefuse->autoload_failflag == false) {
1822                 rtstatus = _rtl8821ae_phy_config_bb_with_pgheaderfile(hw,
1823                                                     BASEBAND_CONFIG_PHY_REG);
1824         }
1825         if (!rtstatus) {
1826                 pr_err("BB_PG Reg Fail!!\n");
1827                 return false;
1828         }
1829
1830         _rtl8821ae_phy_txpower_by_rate_configuration(hw);
1831
1832         /* RegEnableTxPowerLimit == 1 for 8812a & 8821a */
1833         if (rtlefuse->eeprom_regulatory != 2)
1834                 _rtl8812ae_phy_convert_txpower_limit_to_power_index(hw);
1835
1836         rtstatus = _rtl8821ae_phy_config_bb_with_headerfile(hw,
1837                                                 BASEBAND_CONFIG_AGC_TAB);
1838
1839         if (!rtstatus) {
1840                 pr_err("AGC Table Fail\n");
1841                 return false;
1842         }
1843         rtlphy->cck_high_power = (bool)(rtl_get_bbreg(hw,
1844                         RFPGA0_XA_HSSIPARAMETER2, 0x200));
1845         return true;
1846 }
1847
1848 static bool
1849 __rtl8821ae_phy_config_with_headerfile(struct ieee80211_hw *hw,
1850                                        u32 *array_table, u16 arraylen,
1851                                        void (*set_reg)(struct ieee80211_hw *hw,
1852                                                        u32 regaddr, u32 data))
1853 {
1854         #define COND_ELSE  2
1855         #define COND_ENDIF 3
1856
1857         int i = 0;
1858         u8 cond;
1859         bool matched = true, skipped = false;
1860
1861         while ((i + 1) < arraylen) {
1862                 u32 v1 = array_table[i];
1863                 u32 v2 = array_table[i + 1];
1864
1865                 if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/
1866                         if (v1 & BIT(31)) {/* positive condition*/
1867                                 cond  = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
1868                                 if (cond == COND_ENDIF) {/*end*/
1869                                         matched = true;
1870                                         skipped = false;
1871                                 } else if (cond == COND_ELSE) /*else*/
1872                                         matched = skipped ? false : true;
1873                                 else {/*if , else if*/
1874                                         if (skipped) {
1875                                                 matched = false;
1876                                         } else {
1877                                                 if (_rtl8821ae_check_positive(
1878                                                                 hw, v1, v2)) {
1879                                                         matched = true;
1880                                                         skipped = true;
1881                                                 } else {
1882                                                         matched = false;
1883                                                         skipped = false;
1884                                                 }
1885                                         }
1886                                 }
1887                         } else if (v1 & BIT(30)) { /*negative condition*/
1888                         /*do nothing*/
1889                         }
1890                 } else {
1891                         if (matched)
1892                                 set_reg(hw, v1, v2);
1893                 }
1894                 i = i + 2;
1895         }
1896
1897         return true;
1898 }
1899
1900 static bool _rtl8821ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
1901 {
1902         struct rtl_priv *rtlpriv = rtl_priv(hw);
1903         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1904         u32 arraylength;
1905         u32 *ptrarray;
1906
1907         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Read MAC_REG_Array\n");
1908         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1909                 arraylength = RTL8821AE_MAC_1T_ARRAYLEN;
1910                 ptrarray = RTL8821AE_MAC_REG_ARRAY;
1911         } else {
1912                 arraylength = RTL8812AE_MAC_1T_ARRAYLEN;
1913                 ptrarray = RTL8812AE_MAC_REG_ARRAY;
1914         }
1915         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1916                 "Img: MAC_REG_ARRAY LEN %d\n", arraylength);
1917
1918         return __rtl8821ae_phy_config_with_headerfile(hw,
1919                         ptrarray, arraylength, rtl_write_byte_with_val32);
1920 }
1921
1922 static bool _rtl8821ae_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
1923                                                      u8 configtype)
1924 {
1925         struct rtl_priv *rtlpriv = rtl_priv(hw);
1926         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1927         u32 *array_table;
1928         u16 arraylen;
1929
1930         if (configtype == BASEBAND_CONFIG_PHY_REG) {
1931                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1932                         arraylen = RTL8812AE_PHY_REG_1TARRAYLEN;
1933                         array_table = RTL8812AE_PHY_REG_ARRAY;
1934                 } else {
1935                         arraylen = RTL8821AE_PHY_REG_1TARRAYLEN;
1936                         array_table = RTL8821AE_PHY_REG_ARRAY;
1937                 }
1938
1939                 return __rtl8821ae_phy_config_with_headerfile(hw,
1940                                 array_table, arraylen,
1941                                 _rtl8821ae_config_bb_reg);
1942         } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
1943                 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1944                         arraylen = RTL8812AE_AGC_TAB_1TARRAYLEN;
1945                         array_table = RTL8812AE_AGC_TAB_ARRAY;
1946                 } else {
1947                         arraylen = RTL8821AE_AGC_TAB_1TARRAYLEN;
1948                         array_table = RTL8821AE_AGC_TAB_ARRAY;
1949                 }
1950
1951                 return __rtl8821ae_phy_config_with_headerfile(hw,
1952                                 array_table, arraylen,
1953                                 rtl_set_bbreg_with_dwmask);
1954         }
1955         return true;
1956 }
1957
1958 static u8 _rtl8821ae_get_rate_section_index(u32 regaddr)
1959 {
1960         u8 index = 0;
1961         regaddr &= 0xFFF;
1962         if (regaddr >= 0xC20 && regaddr <= 0xC4C)
1963                 index = (u8)((regaddr - 0xC20) / 4);
1964         else if (regaddr >= 0xE20 && regaddr <= 0xE4C)
1965                 index = (u8)((regaddr - 0xE20) / 4);
1966         else
1967                 WARN_ONCE(true,
1968                           "rtl8821ae: Invalid RegAddr 0x%x\n", regaddr);
1969         return index;
1970 }
1971
1972 static void _rtl8821ae_store_tx_power_by_rate(struct ieee80211_hw *hw,
1973                                               u32 band, u32 rfpath,
1974                                               u32 txnum, u32 regaddr,
1975                                               u32 bitmask, u32 data)
1976 {
1977         struct rtl_priv *rtlpriv = rtl_priv(hw);
1978         struct rtl_phy *rtlphy = &rtlpriv->phy;
1979         u8 rate_section = _rtl8821ae_get_rate_section_index(regaddr);
1980
1981         if (band != BAND_ON_2_4G && band != BAND_ON_5G) {
1982                 rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING, "Invalid Band %d\n", band);
1983                 band = BAND_ON_2_4G;
1984         }
1985         if (rfpath >= MAX_RF_PATH) {
1986                 rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING, "Invalid RfPath %d\n", rfpath);
1987                 rfpath = MAX_RF_PATH - 1;
1988         }
1989         if (txnum >= MAX_RF_PATH) {
1990                 rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING, "Invalid TxNum %d\n", txnum);
1991                 txnum = MAX_RF_PATH - 1;
1992         }
1993         rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][rate_section] = data;
1994         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1995                 "TxPwrByRateOffset[Band %d][RfPath %d][TxNum %d][RateSection %d] = 0x%x\n",
1996                 band, rfpath, txnum, rate_section,
1997                 rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][rate_section]);
1998 }
1999
2000 static bool _rtl8821ae_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
2001                                                         u8 configtype)
2002 {
2003         struct rtl_priv *rtlpriv = rtl_priv(hw);
2004         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2005         int i;
2006         u32 *array;
2007         u16 arraylen;
2008         u32 v1, v2, v3, v4, v5, v6;
2009
2010         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2011                 arraylen = RTL8812AE_PHY_REG_ARRAY_PGLEN;
2012                 array = RTL8812AE_PHY_REG_ARRAY_PG;
2013         } else {
2014                 arraylen = RTL8821AE_PHY_REG_ARRAY_PGLEN;
2015                 array = RTL8821AE_PHY_REG_ARRAY_PG;
2016         }
2017
2018         if (configtype != BASEBAND_CONFIG_PHY_REG) {
2019                 rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE,
2020                         "configtype != BaseBand_Config_PHY_REG\n");
2021                 return true;
2022         }
2023         for (i = 0; i < arraylen; i += 6) {
2024                 v1 = array[i];
2025                 v2 = array[i+1];
2026                 v3 = array[i+2];
2027                 v4 = array[i+3];
2028                 v5 = array[i+4];
2029                 v6 = array[i+5];
2030
2031                 if (v1 < 0xCDCDCDCD) {
2032                         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE &&
2033                                 (v4 == 0xfe || v4 == 0xffe)) {
2034                                 msleep(50);
2035                                 continue;
2036                         }
2037
2038                         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2039                                 if (v4 == 0xfe)
2040                                         msleep(50);
2041                                 else if (v4 == 0xfd)
2042                                         mdelay(5);
2043                                 else if (v4 == 0xfc)
2044                                         mdelay(1);
2045                                 else if (v4 == 0xfb)
2046                                         udelay(50);
2047                                 else if (v4 == 0xfa)
2048                                         udelay(5);
2049                                 else if (v4 == 0xf9)
2050                                         udelay(1);
2051                         }
2052                         _rtl8821ae_store_tx_power_by_rate(hw, v1, v2, v3,
2053                                                           v4, v5, v6);
2054                         continue;
2055                 } else {
2056                          /*don't need the hw_body*/
2057                         if (!_rtl8821ae_check_condition(hw, v1)) {
2058                                 i += 2; /* skip the pair of expression*/
2059                                 v1 = array[i];
2060                                 v2 = array[i+1];
2061                                 v3 = array[i+2];
2062                                 while (v2 != 0xDEAD) {
2063                                         i += 3;
2064                                         v1 = array[i];
2065                                         v2 = array[i+1];
2066                                         v3 = array[i+2];
2067                                 }
2068                         }
2069                 }
2070         }
2071
2072         return true;
2073 }
2074
2075 bool rtl8812ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
2076                                              enum radio_path rfpath)
2077 {
2078         u32 *radioa_array_table_a, *radioa_array_table_b;
2079         u16 radioa_arraylen_a, radioa_arraylen_b;
2080         struct rtl_priv *rtlpriv = rtl_priv(hw);
2081
2082         radioa_arraylen_a = RTL8812AE_RADIOA_1TARRAYLEN;
2083         radioa_array_table_a = RTL8812AE_RADIOA_ARRAY;
2084         radioa_arraylen_b = RTL8812AE_RADIOB_1TARRAYLEN;
2085         radioa_array_table_b = RTL8812AE_RADIOB_ARRAY;
2086         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2087                 "Radio_A:RTL8821AE_RADIOA_ARRAY %d\n", radioa_arraylen_a);
2088         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
2089         switch (rfpath) {
2090         case RF90_PATH_A:
2091                 return __rtl8821ae_phy_config_with_headerfile(hw,
2092                                 radioa_array_table_a, radioa_arraylen_a,
2093                                 _rtl8821ae_config_rf_radio_a);
2094                 break;
2095         case RF90_PATH_B:
2096                 return __rtl8821ae_phy_config_with_headerfile(hw,
2097                                 radioa_array_table_b, radioa_arraylen_b,
2098                                 _rtl8821ae_config_rf_radio_b);
2099                 break;
2100         case RF90_PATH_C:
2101         case RF90_PATH_D:
2102                 pr_err("switch case %#x not processed\n", rfpath);
2103                 break;
2104         }
2105         return true;
2106 }
2107
2108 bool rtl8821ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
2109                                                 enum radio_path rfpath)
2110 {
2111         u32 *radioa_array_table;
2112         u16 radioa_arraylen;
2113         struct rtl_priv *rtlpriv = rtl_priv(hw);
2114
2115         radioa_arraylen = RTL8821AE_RADIOA_1TARRAYLEN;
2116         radioa_array_table = RTL8821AE_RADIOA_ARRAY;
2117         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2118                 "Radio_A:RTL8821AE_RADIOA_ARRAY %d\n", radioa_arraylen);
2119         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
2120         switch (rfpath) {
2121         case RF90_PATH_A:
2122                 return __rtl8821ae_phy_config_with_headerfile(hw,
2123                         radioa_array_table, radioa_arraylen,
2124                         _rtl8821ae_config_rf_radio_a);
2125                 break;
2126
2127         case RF90_PATH_B:
2128         case RF90_PATH_C:
2129         case RF90_PATH_D:
2130                 pr_err("switch case %#x not processed\n", rfpath);
2131                 break;
2132         }
2133         return true;
2134 }
2135
2136 void rtl8821ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
2137 {
2138         struct rtl_priv *rtlpriv = rtl_priv(hw);
2139         struct rtl_phy *rtlphy = &rtlpriv->phy;
2140
2141         rtlphy->default_initialgain[0] =
2142             (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
2143         rtlphy->default_initialgain[1] =
2144             (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
2145         rtlphy->default_initialgain[2] =
2146             (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
2147         rtlphy->default_initialgain[3] =
2148             (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
2149
2150         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2151                 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
2152                 rtlphy->default_initialgain[0],
2153                 rtlphy->default_initialgain[1],
2154                 rtlphy->default_initialgain[2],
2155                 rtlphy->default_initialgain[3]);
2156
2157         rtlphy->framesync = (u8)rtl_get_bbreg(hw,
2158                                                ROFDM0_RXDETECTOR3, MASKBYTE0);
2159         rtlphy->framesync_c34 = rtl_get_bbreg(hw,
2160                                               ROFDM0_RXDETECTOR2, MASKDWORD);
2161
2162         rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2163                 "Default framesync (0x%x) = 0x%x\n",
2164                 ROFDM0_RXDETECTOR3, rtlphy->framesync);
2165 }
2166
2167 static void phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
2168 {
2169         struct rtl_priv *rtlpriv = rtl_priv(hw);
2170         struct rtl_phy *rtlphy = &rtlpriv->phy;
2171
2172         rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
2173         rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
2174
2175         rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
2176         rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
2177
2178         rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
2179         rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
2180
2181         rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = RA_LSSIWRITE_8821A;
2182         rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = RB_LSSIWRITE_8821A;
2183
2184         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RHSSIREAD_8821AE;
2185         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RHSSIREAD_8821AE;
2186
2187         rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RA_SIREAD_8821A;
2188         rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RB_SIREAD_8821A;
2189
2190         rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = RA_PIREAD_8821A;
2191         rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = RB_PIREAD_8821A;
2192 }
2193
2194 void rtl8821ae_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
2195 {
2196         struct rtl_priv *rtlpriv = rtl_priv(hw);
2197         struct rtl_phy *rtlphy = &rtlpriv->phy;
2198         u8 txpwr_level;
2199         long txpwr_dbm;
2200
2201         txpwr_level = rtlphy->cur_cck_txpwridx;
2202         txpwr_dbm = _rtl8821ae_phy_txpwr_idx_to_dbm(hw,
2203                                                  WIRELESS_MODE_B, txpwr_level);
2204         txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
2205         if (_rtl8821ae_phy_txpwr_idx_to_dbm(hw,
2206                                          WIRELESS_MODE_G,
2207                                          txpwr_level) > txpwr_dbm)
2208                 txpwr_dbm =
2209                     _rtl8821ae_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
2210                                                  txpwr_level);
2211         txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
2212         if (_rtl8821ae_phy_txpwr_idx_to_dbm(hw,
2213                                          WIRELESS_MODE_N_24G,
2214                                          txpwr_level) > txpwr_dbm)
2215                 txpwr_dbm =
2216                     _rtl8821ae_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
2217                                                  txpwr_level);
2218         *powerlevel = txpwr_dbm;
2219 }
2220
2221 static bool _rtl8821ae_phy_get_chnl_index(u8 channel, u8 *chnl_index)
2222 {
2223         u8 i = 0;
2224         bool in_24g = true;
2225
2226         if (channel <= 14) {
2227                 in_24g = true;
2228                 *chnl_index = channel - 1;
2229         } else {
2230                 in_24g = false;
2231
2232                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; ++i) {
2233                         if (channel5g[i] == channel) {
2234                                 *chnl_index = i;
2235                                 return in_24g;
2236                         }
2237                 }
2238         }
2239         return in_24g;
2240 }
2241
2242 static s8 _rtl8821ae_phy_get_ratesection_intxpower_byrate(u8 path, u8 rate)
2243 {
2244         s8 rate_section = 0;
2245         switch (rate) {
2246         case DESC_RATE1M:
2247         case DESC_RATE2M:
2248         case DESC_RATE5_5M:
2249         case DESC_RATE11M:
2250                 rate_section = 0;
2251                 break;
2252         case DESC_RATE6M:
2253         case DESC_RATE9M:
2254         case DESC_RATE12M:
2255         case DESC_RATE18M:
2256                 rate_section = 1;
2257                 break;
2258         case DESC_RATE24M:
2259         case DESC_RATE36M:
2260         case DESC_RATE48M:
2261         case DESC_RATE54M:
2262                 rate_section = 2;
2263                 break;
2264         case DESC_RATEMCS0:
2265         case DESC_RATEMCS1:
2266         case DESC_RATEMCS2:
2267         case DESC_RATEMCS3:
2268                 rate_section = 3;
2269                 break;
2270         case DESC_RATEMCS4:
2271         case DESC_RATEMCS5:
2272         case DESC_RATEMCS6:
2273         case DESC_RATEMCS7:
2274                 rate_section = 4;
2275                 break;
2276         case DESC_RATEMCS8:
2277         case DESC_RATEMCS9:
2278         case DESC_RATEMCS10:
2279         case DESC_RATEMCS11:
2280                 rate_section = 5;
2281                 break;
2282         case DESC_RATEMCS12:
2283         case DESC_RATEMCS13:
2284         case DESC_RATEMCS14:
2285         case DESC_RATEMCS15:
2286                 rate_section = 6;
2287                 break;
2288         case DESC_RATEVHT1SS_MCS0:
2289         case DESC_RATEVHT1SS_MCS1:
2290         case DESC_RATEVHT1SS_MCS2:
2291         case DESC_RATEVHT1SS_MCS3:
2292                 rate_section = 7;
2293                 break;
2294         case DESC_RATEVHT1SS_MCS4:
2295         case DESC_RATEVHT1SS_MCS5:
2296         case DESC_RATEVHT1SS_MCS6:
2297         case DESC_RATEVHT1SS_MCS7:
2298                 rate_section = 8;
2299                 break;
2300         case DESC_RATEVHT1SS_MCS8:
2301         case DESC_RATEVHT1SS_MCS9:
2302         case DESC_RATEVHT2SS_MCS0:
2303         case DESC_RATEVHT2SS_MCS1:
2304                 rate_section = 9;
2305                 break;
2306         case DESC_RATEVHT2SS_MCS2:
2307         case DESC_RATEVHT2SS_MCS3:
2308         case DESC_RATEVHT2SS_MCS4:
2309         case DESC_RATEVHT2SS_MCS5:
2310                 rate_section = 10;
2311                 break;
2312         case DESC_RATEVHT2SS_MCS6:
2313         case DESC_RATEVHT2SS_MCS7:
2314         case DESC_RATEVHT2SS_MCS8:
2315         case DESC_RATEVHT2SS_MCS9:
2316                 rate_section = 11;
2317                 break;
2318         default:
2319                 WARN_ONCE(true, "rtl8821ae: Rate_Section is Illegal\n");
2320                 break;
2321         }
2322
2323         return rate_section;
2324 }
2325
2326 static s8 _rtl8812ae_phy_get_world_wide_limit(s8  *limit_table)
2327 {
2328         s8 min = limit_table[0];
2329         u8 i = 0;
2330
2331         for (i = 0; i < MAX_REGULATION_NUM; ++i) {
2332                 if (limit_table[i] < min)
2333                         min = limit_table[i];
2334         }
2335         return min;
2336 }
2337
2338 static s8 _rtl8812ae_phy_get_txpower_limit(struct ieee80211_hw *hw,
2339                                              u8 band,
2340                                              enum ht_channel_width bandwidth,
2341                                              enum radio_path rf_path,
2342                                              u8 rate, u8 channel)
2343 {
2344         struct rtl_priv *rtlpriv = rtl_priv(hw);
2345         struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
2346         struct rtl_phy *rtlphy = &rtlpriv->phy;
2347         short band_temp = -1, regulation = -1, bandwidth_temp = -1,
2348                  rate_section = -1, channel_temp = -1;
2349         u16 regu, bdwidth, sec, chnl;
2350         s8 power_limit = MAX_POWER_INDEX;
2351
2352         if (rtlefuse->eeprom_regulatory == 2)
2353                 return MAX_POWER_INDEX;
2354
2355         regulation = TXPWR_LMT_WW;
2356
2357         if (band == BAND_ON_2_4G)
2358                 band_temp = 0;
2359         else if (band == BAND_ON_5G)
2360                 band_temp = 1;
2361
2362         if (bandwidth == HT_CHANNEL_WIDTH_20)
2363                 bandwidth_temp = 0;
2364         else if (bandwidth == HT_CHANNEL_WIDTH_20_40)
2365                 bandwidth_temp = 1;
2366         else if (bandwidth == HT_CHANNEL_WIDTH_80)
2367                 bandwidth_temp = 2;
2368
2369         switch (rate) {
2370         case DESC_RATE1M:
2371         case DESC_RATE2M:
2372         case DESC_RATE5_5M:
2373         case DESC_RATE11M:
2374                 rate_section = 0;
2375                 break;
2376         case DESC_RATE6M:
2377         case DESC_RATE9M:
2378         case DESC_RATE12M:
2379         case DESC_RATE18M:
2380         case DESC_RATE24M:
2381         case DESC_RATE36M:
2382         case DESC_RATE48M:
2383         case DESC_RATE54M:
2384                 rate_section = 1;
2385                 break;
2386         case DESC_RATEMCS0:
2387         case DESC_RATEMCS1:
2388         case DESC_RATEMCS2:
2389         case DESC_RATEMCS3:
2390         case DESC_RATEMCS4:
2391         case DESC_RATEMCS5:
2392         case DESC_RATEMCS6:
2393         case DESC_RATEMCS7:
2394                 rate_section = 2;
2395                 break;
2396         case DESC_RATEMCS8:
2397         case DESC_RATEMCS9:
2398         case DESC_RATEMCS10:
2399         case DESC_RATEMCS11:
2400         case DESC_RATEMCS12:
2401         case DESC_RATEMCS13:
2402         case DESC_RATEMCS14:
2403         case DESC_RATEMCS15:
2404                 rate_section = 3;
2405                 break;
2406         case DESC_RATEVHT1SS_MCS0:
2407         case DESC_RATEVHT1SS_MCS1:
2408         case DESC_RATEVHT1SS_MCS2:
2409         case DESC_RATEVHT1SS_MCS3:
2410         case DESC_RATEVHT1SS_MCS4:
2411         case DESC_RATEVHT1SS_MCS5:
2412         case DESC_RATEVHT1SS_MCS6:
2413         case DESC_RATEVHT1SS_MCS7:
2414         case DESC_RATEVHT1SS_MCS8:
2415         case DESC_RATEVHT1SS_MCS9:
2416                 rate_section = 4;
2417                 break;
2418         case DESC_RATEVHT2SS_MCS0:
2419         case DESC_RATEVHT2SS_MCS1:
2420         case DESC_RATEVHT2SS_MCS2:
2421         case DESC_RATEVHT2SS_MCS3:
2422         case DESC_RATEVHT2SS_MCS4:
2423         case DESC_RATEVHT2SS_MCS5:
2424         case DESC_RATEVHT2SS_MCS6:
2425         case DESC_RATEVHT2SS_MCS7:
2426         case DESC_RATEVHT2SS_MCS8:
2427         case DESC_RATEVHT2SS_MCS9:
2428                 rate_section = 5;
2429                 break;
2430         default:
2431                 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
2432                         "Wrong rate 0x%x\n", rate);
2433                 break;
2434         }
2435
2436         if (band_temp == BAND_ON_5G  && rate_section == 0)
2437                 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
2438                         "Wrong rate 0x%x: No CCK in 5G Band\n", rate);
2439
2440         /*workaround for wrong index combination to obtain tx power limit,
2441           OFDM only exists in BW 20M*/
2442         if (rate_section == 1)
2443                 bandwidth_temp = 0;
2444
2445         /*workaround for wrong index combination to obtain tx power limit,
2446          *HT on 80M will reference to HT on 40M
2447          */
2448         if ((rate_section == 2 || rate_section == 3) && band == BAND_ON_5G &&
2449             bandwidth_temp == 2)
2450                 bandwidth_temp = 1;
2451
2452         if (band == BAND_ON_2_4G)
2453                 channel_temp = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw,
2454                 BAND_ON_2_4G, channel);
2455         else if (band == BAND_ON_5G)
2456                 channel_temp = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw,
2457                 BAND_ON_5G, channel);
2458         else if (band == BAND_ON_BOTH)
2459                 ;/* BAND_ON_BOTH don't care temporarily */
2460
2461         if (band_temp == -1 || regulation == -1 || bandwidth_temp == -1 ||
2462                 rate_section == -1 || channel_temp == -1) {
2463                 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
2464                         "Wrong index value to access power limit table [band %d][regulation %d][bandwidth %d][rf_path %d][rate_section %d][chnl %d]\n",
2465                         band_temp, regulation, bandwidth_temp, rf_path,
2466                         rate_section, channel_temp);
2467                 return MAX_POWER_INDEX;
2468         }
2469
2470         regu = regulation;
2471         bdwidth = bandwidth_temp;
2472         sec = rate_section;
2473         chnl = channel_temp;
2474
2475         if (band == BAND_ON_2_4G) {
2476                 s8 limits[10] = {0};
2477                 u8 i;
2478
2479                 for (i = 0; i < 4; ++i)
2480                         limits[i] = rtlphy->txpwr_limit_2_4g[i][bdwidth]
2481                         [sec][chnl][rf_path];
2482
2483                 power_limit = (regulation == TXPWR_LMT_WW) ?
2484                         _rtl8812ae_phy_get_world_wide_limit(limits) :
2485                         rtlphy->txpwr_limit_2_4g[regu][bdwidth]
2486                                         [sec][chnl][rf_path];
2487         } else if (band == BAND_ON_5G) {
2488                 s8 limits[10] = {0};
2489                 u8 i;
2490
2491                 for (i = 0; i < MAX_REGULATION_NUM; ++i)
2492                         limits[i] = rtlphy->txpwr_limit_5g[i][bdwidth]
2493                         [sec][chnl][rf_path];
2494
2495                 power_limit = (regulation == TXPWR_LMT_WW) ?
2496                         _rtl8812ae_phy_get_world_wide_limit(limits) :
2497                         rtlphy->txpwr_limit_5g[regu][chnl]
2498                         [sec][chnl][rf_path];
2499         } else {
2500                 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2501                         "No power limit table of the specified band\n");
2502         }
2503         return power_limit;
2504 }
2505
2506 static s8 _rtl8821ae_phy_get_txpower_by_rate(struct ieee80211_hw *hw,
2507                                         u8 band, u8 path, u8 rate)
2508 {
2509         struct rtl_priv *rtlpriv = rtl_priv(hw);
2510         struct rtl_phy *rtlphy = &rtlpriv->phy;
2511         u8 shift = 0, rate_section, tx_num;
2512         s8 tx_pwr_diff = 0;
2513         s8 limit = 0;
2514
2515         rate_section = _rtl8821ae_phy_get_ratesection_intxpower_byrate(path, rate);
2516         tx_num = RF_TX_NUM_NONIMPLEMENT;
2517
2518         if (tx_num == RF_TX_NUM_NONIMPLEMENT) {
2519                 if ((rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) ||
2520                         (rate >= DESC_RATEVHT2SS_MCS2 && rate <= DESC_RATEVHT2SS_MCS9))
2521                         tx_num = RF_2TX;
2522                 else
2523                         tx_num = RF_1TX;
2524         }
2525
2526         switch (rate) {
2527         case DESC_RATE1M:
2528         case DESC_RATE6M:
2529         case DESC_RATE24M:
2530         case DESC_RATEMCS0:
2531         case DESC_RATEMCS4:
2532         case DESC_RATEMCS8:
2533         case DESC_RATEMCS12:
2534         case DESC_RATEVHT1SS_MCS0:
2535         case DESC_RATEVHT1SS_MCS4:
2536         case DESC_RATEVHT1SS_MCS8:
2537         case DESC_RATEVHT2SS_MCS2:
2538         case DESC_RATEVHT2SS_MCS6:
2539                 shift = 0;
2540                 break;
2541         case DESC_RATE2M:
2542         case DESC_RATE9M:
2543         case DESC_RATE36M:
2544         case DESC_RATEMCS1:
2545         case DESC_RATEMCS5:
2546         case DESC_RATEMCS9:
2547         case DESC_RATEMCS13:
2548         case DESC_RATEVHT1SS_MCS1:
2549         case DESC_RATEVHT1SS_MCS5:
2550         case DESC_RATEVHT1SS_MCS9:
2551         case DESC_RATEVHT2SS_MCS3:
2552         case DESC_RATEVHT2SS_MCS7:
2553                 shift = 8;
2554                 break;
2555         case DESC_RATE5_5M:
2556         case DESC_RATE12M:
2557         case DESC_RATE48M:
2558         case DESC_RATEMCS2:
2559         case DESC_RATEMCS6:
2560         case DESC_RATEMCS10:
2561         case DESC_RATEMCS14:
2562         case DESC_RATEVHT1SS_MCS2:
2563         case DESC_RATEVHT1SS_MCS6:
2564         case DESC_RATEVHT2SS_MCS0:
2565         case DESC_RATEVHT2SS_MCS4:
2566         case DESC_RATEVHT2SS_MCS8:
2567                 shift = 16;
2568                 break;
2569         case DESC_RATE11M:
2570         case DESC_RATE18M:
2571         case DESC_RATE54M:
2572         case DESC_RATEMCS3:
2573         case DESC_RATEMCS7:
2574         case DESC_RATEMCS11:
2575         case DESC_RATEMCS15:
2576         case DESC_RATEVHT1SS_MCS3:
2577         case DESC_RATEVHT1SS_MCS7:
2578         case DESC_RATEVHT2SS_MCS1:
2579         case DESC_RATEVHT2SS_MCS5:
2580         case DESC_RATEVHT2SS_MCS9:
2581                 shift = 24;
2582                 break;
2583         default:
2584                 WARN_ONCE(true, "rtl8821ae: Rate_Section is Illegal\n");
2585                 break;
2586         }
2587
2588         tx_pwr_diff = (u8)(rtlphy->tx_power_by_rate_offset[band][path]
2589                 [tx_num][rate_section] >> shift) & 0xff;
2590
2591         /* RegEnableTxPowerLimit == 1 for 8812a & 8821a */
2592         if (rtlpriv->efuse.eeprom_regulatory != 2) {
2593                 limit = _rtl8812ae_phy_get_txpower_limit(hw, band,
2594                         rtlphy->current_chan_bw, path, rate,
2595                         rtlphy->current_channel);
2596
2597                 if (rate == DESC_RATEVHT1SS_MCS8 || rate == DESC_RATEVHT1SS_MCS9  ||
2598                          rate == DESC_RATEVHT2SS_MCS8 || rate == DESC_RATEVHT2SS_MCS9) {
2599                         if (limit < 0) {
2600                                 if (tx_pwr_diff < (-limit))
2601                                         tx_pwr_diff = -limit;
2602                         }
2603                 } else {
2604                         if (limit < 0)
2605                                 tx_pwr_diff = limit;
2606                         else
2607                                 tx_pwr_diff = tx_pwr_diff > limit ? limit : tx_pwr_diff;
2608                 }
2609                 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2610                         "Maximum power by rate %d, final power by rate %d\n",
2611                         limit, tx_pwr_diff);
2612         }
2613
2614         return  tx_pwr_diff;
2615 }
2616
2617 static u8 _rtl8821ae_get_txpower_index(struct ieee80211_hw *hw, u8 path,
2618                                         u8 rate, u8 bandwidth, u8 channel)
2619 {
2620         struct rtl_priv *rtlpriv = rtl_priv(hw);
2621         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2622         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2623         u8 index = (channel - 1);
2624         u8 txpower = 0;
2625         bool in_24g = false;
2626         s8 powerdiff_byrate = 0;
2627
2628         if (((rtlhal->current_bandtype == BAND_ON_2_4G) &&
2629             (channel > 14 || channel < 1)) ||
2630             ((rtlhal->current_bandtype == BAND_ON_5G) && (channel <= 14))) {
2631                 index = 0;
2632                 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2633                         "Illegal channel!!\n");
2634         }
2635
2636         in_24g = _rtl8821ae_phy_get_chnl_index(channel, &index);
2637         if (in_24g) {
2638                 if (RTL8821AE_RX_HAL_IS_CCK_RATE(rate))
2639                         txpower = rtlefuse->txpwrlevel_cck[path][index];
2640                 else if (DESC_RATE6M <= rate)
2641                         txpower = rtlefuse->txpwrlevel_ht40_1s[path][index];
2642                 else
2643                         rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "invalid rate\n");
2644
2645                 if (DESC_RATE6M <= rate && rate <= DESC_RATE54M &&
2646                     !RTL8821AE_RX_HAL_IS_CCK_RATE(rate))
2647                         txpower += rtlefuse->txpwr_legacyhtdiff[path][TX_1S];
2648
2649                 if (bandwidth == HT_CHANNEL_WIDTH_20) {
2650                         if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2651                                 (DESC_RATEVHT1SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2652                                 txpower += rtlefuse->txpwr_ht20diff[path][TX_1S];
2653                         if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2654                                 (DESC_RATEVHT2SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2655                                 txpower += rtlefuse->txpwr_ht20diff[path][TX_2S];
2656                 } else if (bandwidth == HT_CHANNEL_WIDTH_20_40) {
2657                         if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2658                                 (DESC_RATEVHT1SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2659                                 txpower += rtlefuse->txpwr_ht40diff[path][TX_1S];
2660                         if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2661                                 (DESC_RATEVHT2SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2662                                 txpower += rtlefuse->txpwr_ht40diff[path][TX_2S];
2663                 } else if (bandwidth == HT_CHANNEL_WIDTH_80) {
2664                         if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2665                             (DESC_RATEVHT1SS_MCS0 <= rate &&
2666                              rate <= DESC_RATEVHT2SS_MCS9))
2667                                 txpower += rtlefuse->txpwr_ht40diff[path][TX_1S];
2668                         if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2669                             (DESC_RATEVHT2SS_MCS0 <= rate &&
2670                              rate <= DESC_RATEVHT2SS_MCS9))
2671                                 txpower += rtlefuse->txpwr_ht40diff[path][TX_2S];
2672                 }
2673         } else {
2674                 if (DESC_RATE6M <= rate)
2675                         txpower = rtlefuse->txpwr_5g_bw40base[path][index];
2676                 else
2677                         rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_WARNING,
2678                                 "INVALID Rate.\n");
2679
2680                 if (DESC_RATE6M <= rate && rate <= DESC_RATE54M &&
2681                     !RTL8821AE_RX_HAL_IS_CCK_RATE(rate))
2682                         txpower += rtlefuse->txpwr_5g_ofdmdiff[path][TX_1S];
2683
2684                 if (bandwidth == HT_CHANNEL_WIDTH_20) {
2685                         if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2686                             (DESC_RATEVHT1SS_MCS0 <= rate &&
2687                              rate <= DESC_RATEVHT2SS_MCS9))
2688                                 txpower += rtlefuse->txpwr_5g_bw20diff[path][TX_1S];
2689                         if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2690                             (DESC_RATEVHT2SS_MCS0 <= rate &&
2691                              rate <= DESC_RATEVHT2SS_MCS9))
2692                                 txpower += rtlefuse->txpwr_5g_bw20diff[path][TX_2S];
2693                 } else if (bandwidth == HT_CHANNEL_WIDTH_20_40) {
2694                         if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2695                             (DESC_RATEVHT1SS_MCS0 <= rate &&
2696                              rate <= DESC_RATEVHT2SS_MCS9))
2697                                 txpower += rtlefuse->txpwr_5g_bw40diff[path][TX_1S];
2698                         if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2699                             (DESC_RATEVHT2SS_MCS0 <= rate &&
2700                              rate <= DESC_RATEVHT2SS_MCS9))
2701                                 txpower += rtlefuse->txpwr_5g_bw40diff[path][TX_2S];
2702                 } else if (bandwidth == HT_CHANNEL_WIDTH_80) {
2703                         u8 i;
2704
2705                         for (i = 0; i < sizeof(channel5g_80m) / sizeof(u8); ++i)
2706                                 if (channel5g_80m[i] == channel)
2707                                         index = i;
2708
2709                         if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2710                             (DESC_RATEVHT1SS_MCS0 <= rate &&
2711                              rate <= DESC_RATEVHT2SS_MCS9))
2712                                 txpower = rtlefuse->txpwr_5g_bw80base[path][index]
2713                                         + rtlefuse->txpwr_5g_bw80diff[path][TX_1S];
2714                         if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2715                             (DESC_RATEVHT2SS_MCS0 <= rate &&
2716                              rate <= DESC_RATEVHT2SS_MCS9))
2717                                 txpower = rtlefuse->txpwr_5g_bw80base[path][index]
2718                                         + rtlefuse->txpwr_5g_bw80diff[path][TX_1S]
2719                                         + rtlefuse->txpwr_5g_bw80diff[path][TX_2S];
2720                     }
2721         }
2722         if (rtlefuse->eeprom_regulatory != 2)
2723                 powerdiff_byrate =
2724                   _rtl8821ae_phy_get_txpower_by_rate(hw, (u8)(!in_24g),
2725                                                      path, rate);
2726
2727         if (rate == DESC_RATEVHT1SS_MCS8 || rate == DESC_RATEVHT1SS_MCS9 ||
2728             rate == DESC_RATEVHT2SS_MCS8 || rate == DESC_RATEVHT2SS_MCS9)
2729                 txpower -= powerdiff_byrate;
2730         else
2731                 txpower += powerdiff_byrate;
2732
2733         if (rate > DESC_RATE11M)
2734                 txpower += rtlpriv->dm.remnant_ofdm_swing_idx[path];
2735         else
2736                 txpower += rtlpriv->dm.remnant_cck_idx;
2737
2738         if (txpower > MAX_POWER_INDEX)
2739                 txpower = MAX_POWER_INDEX;
2740
2741         return txpower;
2742 }
2743
2744 static void _rtl8821ae_phy_set_txpower_index(struct ieee80211_hw *hw,
2745                                              u8 power_index, u8 path, u8 rate)
2746 {
2747         struct rtl_priv *rtlpriv = rtl_priv(hw);
2748
2749         if (path == RF90_PATH_A) {
2750                 switch (rate) {
2751                 case DESC_RATE1M:
2752                         rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1,
2753                                       MASKBYTE0, power_index);
2754                         break;
2755                 case DESC_RATE2M:
2756                         rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1,
2757                                       MASKBYTE1, power_index);
2758                         break;
2759                 case DESC_RATE5_5M:
2760                         rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1,
2761                                       MASKBYTE2, power_index);
2762                         break;
2763                 case DESC_RATE11M:
2764                         rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1,
2765                                       MASKBYTE3, power_index);
2766                         break;
2767                 case DESC_RATE6M:
2768                         rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6,
2769                                       MASKBYTE0, power_index);
2770                         break;
2771                 case DESC_RATE9M:
2772                         rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6,
2773                                       MASKBYTE1, power_index);
2774                         break;
2775                 case DESC_RATE12M:
2776                         rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6,
2777                                       MASKBYTE2, power_index);
2778                         break;
2779                 case DESC_RATE18M:
2780                         rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6,
2781                                       MASKBYTE3, power_index);
2782                         break;
2783                 case DESC_RATE24M:
2784                         rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24,
2785                                       MASKBYTE0, power_index);
2786                         break;
2787                 case DESC_RATE36M:
2788                         rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24,
2789                                       MASKBYTE1, power_index);
2790                         break;
2791                 case DESC_RATE48M:
2792                         rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24,
2793                                       MASKBYTE2, power_index);
2794                         break;
2795                 case DESC_RATE54M:
2796                         rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24,
2797                                       MASKBYTE3, power_index);
2798                         break;
2799                 case DESC_RATEMCS0:
2800                         rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
2801                                       MASKBYTE0, power_index);
2802                         break;
2803                 case DESC_RATEMCS1:
2804                         rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
2805                                       MASKBYTE1, power_index);
2806                         break;
2807                 case DESC_RATEMCS2:
2808                         rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
2809                                       MASKBYTE2, power_index);
2810                         break;
2811                 case DESC_RATEMCS3:
2812                         rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
2813                                       MASKBYTE3, power_index);
2814                         break;
2815                 case DESC_RATEMCS4:
2816                         rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
2817                                       MASKBYTE0, power_index);
2818                         break;
2819                 case DESC_RATEMCS5:
2820                         rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
2821                                       MASKBYTE1, power_index);
2822                         break;
2823                 case DESC_RATEMCS6:
2824                         rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
2825                                       MASKBYTE2, power_index);
2826                         break;
2827                 case DESC_RATEMCS7:
2828                         rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
2829                                       MASKBYTE3, power_index);
2830                         break;
2831                 case DESC_RATEMCS8:
2832                         rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
2833                                       MASKBYTE0, power_index);
2834                         break;
2835                 case DESC_RATEMCS9:
2836                         rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
2837                                       MASKBYTE1, power_index);
2838                         break;
2839                 case DESC_RATEMCS10:
2840                         rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
2841                                       MASKBYTE2, power_index);
2842                         break;
2843                 case DESC_RATEMCS11:
2844                         rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
2845                                       MASKBYTE3, power_index);
2846                         break;
2847                 case DESC_RATEMCS12:
2848                         rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
2849                                       MASKBYTE0, power_index);
2850                         break;
2851                 case DESC_RATEMCS13:
2852                         rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
2853                                       MASKBYTE1, power_index);
2854                         break;
2855                 case DESC_RATEMCS14:
2856                         rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
2857                                       MASKBYTE2, power_index);
2858                         break;
2859                 case DESC_RATEMCS15:
2860                         rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
2861                                       MASKBYTE3, power_index);
2862                         break;
2863                 case DESC_RATEVHT1SS_MCS0:
2864                         rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0,
2865                                       MASKBYTE0, power_index);
2866                         break;
2867                 case DESC_RATEVHT1SS_MCS1:
2868                         rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0,
2869                                       MASKBYTE1, power_index);
2870                         break;
2871                 case DESC_RATEVHT1SS_MCS2:
2872                         rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0,
2873                                       MASKBYTE2, power_index);
2874                         break;
2875                 case DESC_RATEVHT1SS_MCS3:
2876                         rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0,
2877                                       MASKBYTE3, power_index);
2878                         break;
2879                 case DESC_RATEVHT1SS_MCS4:
2880                         rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4,
2881                                       MASKBYTE0, power_index);
2882                         break;
2883                 case DESC_RATEVHT1SS_MCS5:
2884                         rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4,
2885                                       MASKBYTE1, power_index);
2886                         break;
2887                 case DESC_RATEVHT1SS_MCS6:
2888                         rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4,
2889                                       MASKBYTE2, power_index);
2890                         break;
2891                 case DESC_RATEVHT1SS_MCS7:
2892                         rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4,
2893                                       MASKBYTE3, power_index);
2894                         break;
2895                 case DESC_RATEVHT1SS_MCS8:
2896                         rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8,
2897                                       MASKBYTE0, power_index);
2898                         break;
2899                 case DESC_RATEVHT1SS_MCS9:
2900                         rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8,
2901                                       MASKBYTE1, power_index);
2902                         break;
2903                 case DESC_RATEVHT2SS_MCS0:
2904                         rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8,
2905                                       MASKBYTE2, power_index);
2906                         break;
2907                 case DESC_RATEVHT2SS_MCS1:
2908                         rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8,
2909                                       MASKBYTE3, power_index);
2910                         break;
2911                 case DESC_RATEVHT2SS_MCS2:
2912                         rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2,
2913                                       MASKBYTE0, power_index);
2914                         break;
2915                 case DESC_RATEVHT2SS_MCS3:
2916                         rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2,
2917                                       MASKBYTE1, power_index);
2918                         break;
2919                 case DESC_RATEVHT2SS_MCS4:
2920                         rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2,
2921                                       MASKBYTE2, power_index);
2922                         break;
2923                 case DESC_RATEVHT2SS_MCS5:
2924                         rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2,
2925                                       MASKBYTE3, power_index);
2926                         break;
2927                 case DESC_RATEVHT2SS_MCS6:
2928                         rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6,
2929                                       MASKBYTE0, power_index);
2930                         break;
2931                 case DESC_RATEVHT2SS_MCS7:
2932                         rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6,
2933                                       MASKBYTE1, power_index);
2934                         break;
2935                 case DESC_RATEVHT2SS_MCS8:
2936                         rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6,
2937                                       MASKBYTE2, power_index);
2938                         break;
2939                 case DESC_RATEVHT2SS_MCS9:
2940                         rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6,
2941                                       MASKBYTE3, power_index);
2942                         break;
2943                 default:
2944                         rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
2945                                 "Invalid Rate!!\n");
2946                         break;
2947                 }
2948         } else if (path == RF90_PATH_B) {
2949                 switch (rate) {
2950                 case DESC_RATE1M:
2951                         rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1,
2952                                       MASKBYTE0, power_index);
2953                         break;
2954                 case DESC_RATE2M:
2955                         rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1,
2956                                       MASKBYTE1, power_index);
2957                         break;
2958                 case DESC_RATE5_5M:
2959                         rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1,
2960                                       MASKBYTE2, power_index);
2961                         break;
2962                 case DESC_RATE11M:
2963                         rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1,
2964                                       MASKBYTE3, power_index);
2965                         break;
2966                 case DESC_RATE6M:
2967                         rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6,
2968                                       MASKBYTE0, power_index);
2969                         break;
2970                 case DESC_RATE9M:
2971                         rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6,
2972                                       MASKBYTE1, power_index);
2973                         break;
2974                 case DESC_RATE12M:
2975                         rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6,
2976                                       MASKBYTE2, power_index);
2977                         break;
2978                 case DESC_RATE18M:
2979                         rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6,
2980                                       MASKBYTE3, power_index);
2981                         break;
2982                 case DESC_RATE24M:
2983                         rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24,
2984                                       MASKBYTE0, power_index);
2985                         break;
2986                 case DESC_RATE36M:
2987                         rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24,
2988                                       MASKBYTE1, power_index);
2989                         break;
2990                 case DESC_RATE48M:
2991                         rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24,
2992                                       MASKBYTE2, power_index);
2993                         break;
2994                 case DESC_RATE54M:
2995                         rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24,
2996                                       MASKBYTE3, power_index);
2997                         break;
2998                 case DESC_RATEMCS0:
2999                         rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
3000                                       MASKBYTE0, power_index);
3001                         break;
3002                 case DESC_RATEMCS1:
3003                         rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
3004                                       MASKBYTE1, power_index);
3005                         break;
3006                 case DESC_RATEMCS2:
3007                         rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
3008                                       MASKBYTE2, power_index);
3009                         break;
3010                 case DESC_RATEMCS3:
3011                         rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
3012                                       MASKBYTE3, power_index);
3013                         break;
3014                 case DESC_RATEMCS4:
3015                         rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
3016                                       MASKBYTE0, power_index);
3017                         break;
3018                 case DESC_RATEMCS5:
3019                         rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
3020                                       MASKBYTE1, power_index);
3021                         break;
3022                 case DESC_RATEMCS6:
3023                         rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
3024                                       MASKBYTE2, power_index);
3025                         break;
3026                 case DESC_RATEMCS7:
3027                         rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
3028                                       MASKBYTE3, power_index);
3029                         break;
3030                 case DESC_RATEMCS8:
3031                         rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
3032                                       MASKBYTE0, power_index);
3033                         break;
3034                 case DESC_RATEMCS9:
3035                         rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
3036                                       MASKBYTE1, power_index);
3037                         break;
3038                 case DESC_RATEMCS10:
3039                         rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
3040                                       MASKBYTE2, power_index);
3041                         break;
3042                 case DESC_RATEMCS11:
3043                         rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
3044                                       MASKBYTE3, power_index);
3045                         break;
3046                 case DESC_RATEMCS12:
3047                         rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
3048                                       MASKBYTE0, power_index);
3049                         break;
3050                 case DESC_RATEMCS13:
3051                         rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
3052                                       MASKBYTE1, power_index);
3053                         break;
3054                 case DESC_RATEMCS14:
3055                         rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
3056                                       MASKBYTE2, power_index);
3057                         break;
3058                 case DESC_RATEMCS15:
3059                         rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
3060                                       MASKBYTE3, power_index);
3061                         break;
3062                 case DESC_RATEVHT1SS_MCS0:
3063                         rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0,
3064                                       MASKBYTE0, power_index);
3065                         break;
3066                 case DESC_RATEVHT1SS_MCS1:
3067                         rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0,
3068                                       MASKBYTE1, power_index);
3069                         break;
3070                 case DESC_RATEVHT1SS_MCS2:
3071                         rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0,
3072                                       MASKBYTE2, power_index);
3073                         break;
3074                 case DESC_RATEVHT1SS_MCS3:
3075                         rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0,
3076                                       MASKBYTE3, power_index);
3077                         break;
3078                 case DESC_RATEVHT1SS_MCS4:
3079                         rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4,
3080                                       MASKBYTE0, power_index);
3081                         break;
3082                 case DESC_RATEVHT1SS_MCS5:
3083                         rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4,
3084                                       MASKBYTE1, power_index);
3085                         break;
3086                 case DESC_RATEVHT1SS_MCS6:
3087                         rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4,
3088                                       MASKBYTE2, power_index);
3089                         break;
3090                 case DESC_RATEVHT1SS_MCS7:
3091                         rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4,
3092                                       MASKBYTE3, power_index);
3093                         break;
3094                 case DESC_RATEVHT1SS_MCS8:
3095                         rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8,
3096                                       MASKBYTE0, power_index);
3097                         break;
3098                 case DESC_RATEVHT1SS_MCS9:
3099                         rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8,
3100                                       MASKBYTE1, power_index);
3101                         break;
3102                 case DESC_RATEVHT2SS_MCS0:
3103                         rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8,
3104                                       MASKBYTE2, power_index);
3105                         break;
3106                 case DESC_RATEVHT2SS_MCS1:
3107                         rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8,
3108                                       MASKBYTE3, power_index);
3109                         break;
3110                 case DESC_RATEVHT2SS_MCS2:
3111                         rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2,
3112                                       MASKBYTE0, power_index);
3113                         break;
3114                 case DESC_RATEVHT2SS_MCS3:
3115                         rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2,
3116                                       MASKBYTE1, power_index);
3117                         break;
3118                 case DESC_RATEVHT2SS_MCS4:
3119                         rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2,
3120                                       MASKBYTE2, power_index);
3121                         break;
3122                 case DESC_RATEVHT2SS_MCS5:
3123                         rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2,
3124                                       MASKBYTE3, power_index);
3125                         break;
3126                 case DESC_RATEVHT2SS_MCS6:
3127                         rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6,
3128                                       MASKBYTE0, power_index);
3129                         break;
3130                 case DESC_RATEVHT2SS_MCS7:
3131                         rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6,
3132                                       MASKBYTE1, power_index);
3133                         break;
3134                 case DESC_RATEVHT2SS_MCS8:
3135                         rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6,
3136                                       MASKBYTE2, power_index);
3137                         break;
3138                 case DESC_RATEVHT2SS_MCS9:
3139                         rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6,
3140                                       MASKBYTE3, power_index);
3141                         break;
3142                 default:
3143                         rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
3144                                 "Invalid Rate!!\n");
3145                         break;
3146                 }
3147         } else {
3148                 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
3149                         "Invalid RFPath!!\n");
3150         }
3151 }
3152
3153 static void _rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw *hw,
3154                                                      u8 *array, u8 path,
3155                                                      u8 channel, u8 size)
3156 {
3157         struct rtl_priv *rtlpriv = rtl_priv(hw);
3158         struct rtl_phy *rtlphy = &rtlpriv->phy;
3159         u8 i;
3160         u8 power_index;
3161
3162         for (i = 0; i < size; i++) {
3163                 power_index =
3164                   _rtl8821ae_get_txpower_index(hw, path, array[i],
3165                                                rtlphy->current_chan_bw,
3166                                                channel);
3167                 _rtl8821ae_phy_set_txpower_index(hw, power_index, path,
3168                                                  array[i]);
3169         }
3170 }
3171
3172 static void _rtl8821ae_phy_txpower_training_by_path(struct ieee80211_hw *hw,
3173                                                     u8 bw, u8 channel, u8 path)
3174 {
3175         struct rtl_priv *rtlpriv = rtl_priv(hw);
3176         struct rtl_phy *rtlphy = &rtlpriv->phy;
3177
3178         u8 i;
3179         u32 power_level, data, offset;
3180
3181         if (path >= rtlphy->num_total_rfpath)
3182                 return;
3183
3184         data = 0;
3185         if (path == RF90_PATH_A) {
3186                 power_level =
3187                         _rtl8821ae_get_txpower_index(hw, RF90_PATH_A,
3188                         DESC_RATEMCS7, bw, channel);
3189                 offset =  RA_TXPWRTRAING;
3190         } else {
3191                 power_level =
3192                         _rtl8821ae_get_txpower_index(hw, RF90_PATH_B,
3193                         DESC_RATEMCS7, bw, channel);
3194                 offset =  RB_TXPWRTRAING;
3195         }
3196
3197         for (i = 0; i < 3; i++) {
3198                 if (i == 0)
3199                         power_level = power_level - 10;
3200                 else if (i == 1)
3201                         power_level = power_level - 8;
3202                 else
3203                         power_level = power_level - 6;
3204
3205                 data |= (((power_level > 2) ? (power_level) : 2) << (i * 8));
3206         }
3207         rtl_set_bbreg(hw, offset, 0xffffff, data);
3208 }
3209
3210 void rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw *hw,
3211                                              u8 channel, u8 path)
3212 {
3213         /* struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); */
3214         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3215         struct rtl_priv *rtlpriv = rtl_priv(hw);
3216         struct rtl_phy *rtlphy = &rtlpriv->phy;
3217         u8 cck_rates[]  = {DESC_RATE1M, DESC_RATE2M, DESC_RATE5_5M,
3218                               DESC_RATE11M};
3219         u8 sizes_of_cck_retes = 4;
3220         u8 ofdm_rates[]  = {DESC_RATE6M, DESC_RATE9M, DESC_RATE12M,
3221                                 DESC_RATE18M, DESC_RATE24M, DESC_RATE36M,
3222                                 DESC_RATE48M, DESC_RATE54M};
3223         u8 sizes_of_ofdm_retes = 8;
3224         u8 ht_rates_1t[]  = {DESC_RATEMCS0, DESC_RATEMCS1, DESC_RATEMCS2,
3225                                 DESC_RATEMCS3, DESC_RATEMCS4, DESC_RATEMCS5,
3226                                 DESC_RATEMCS6, DESC_RATEMCS7};
3227         u8 sizes_of_ht_retes_1t = 8;
3228         u8 ht_rates_2t[]  = {DESC_RATEMCS8, DESC_RATEMCS9,
3229                                 DESC_RATEMCS10, DESC_RATEMCS11,
3230                                 DESC_RATEMCS12, DESC_RATEMCS13,
3231                                 DESC_RATEMCS14, DESC_RATEMCS15};
3232         u8 sizes_of_ht_retes_2t = 8;
3233         u8 vht_rates_1t[]  = {DESC_RATEVHT1SS_MCS0, DESC_RATEVHT1SS_MCS1,
3234                                 DESC_RATEVHT1SS_MCS2, DESC_RATEVHT1SS_MCS3,
3235                                 DESC_RATEVHT1SS_MCS4, DESC_RATEVHT1SS_MCS5,
3236                                 DESC_RATEVHT1SS_MCS6, DESC_RATEVHT1SS_MCS7,
3237                              DESC_RATEVHT1SS_MCS8, DESC_RATEVHT1SS_MCS9};
3238         u8 vht_rates_2t[]  = {DESC_RATEVHT2SS_MCS0, DESC_RATEVHT2SS_MCS1,
3239                                 DESC_RATEVHT2SS_MCS2, DESC_RATEVHT2SS_MCS3,
3240                                 DESC_RATEVHT2SS_MCS4, DESC_RATEVHT2SS_MCS5,
3241                                 DESC_RATEVHT2SS_MCS6, DESC_RATEVHT2SS_MCS7,
3242                                 DESC_RATEVHT2SS_MCS8, DESC_RATEVHT2SS_MCS9};
3243         u8 sizes_of_vht_retes = 10;
3244
3245         if (rtlhal->current_bandtype == BAND_ON_2_4G)
3246                 _rtl8821ae_phy_set_txpower_level_by_path(hw, cck_rates, path, channel,
3247                                                          sizes_of_cck_retes);
3248
3249         _rtl8821ae_phy_set_txpower_level_by_path(hw, ofdm_rates, path, channel,
3250                                                  sizes_of_ofdm_retes);
3251         _rtl8821ae_phy_set_txpower_level_by_path(hw, ht_rates_1t, path, channel,
3252                                                  sizes_of_ht_retes_1t);
3253         _rtl8821ae_phy_set_txpower_level_by_path(hw, vht_rates_1t, path, channel,
3254                                                  sizes_of_vht_retes);
3255
3256         if (rtlphy->num_total_rfpath >= 2) {
3257                 _rtl8821ae_phy_set_txpower_level_by_path(hw, ht_rates_2t, path,
3258                                                          channel,
3259                                                          sizes_of_ht_retes_2t);
3260                 _rtl8821ae_phy_set_txpower_level_by_path(hw, vht_rates_2t, path,
3261                                                          channel,
3262                                                          sizes_of_vht_retes);
3263         }
3264
3265         _rtl8821ae_phy_txpower_training_by_path(hw, rtlphy->current_chan_bw,
3266                                                 channel, path);
3267 }
3268
3269 /*just in case, write txpower in DW, to reduce time*/
3270 void rtl8821ae_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
3271 {
3272         struct rtl_priv *rtlpriv = rtl_priv(hw);
3273         struct rtl_phy *rtlphy = &rtlpriv->phy;
3274         u8 path = 0;
3275
3276         for (path = RF90_PATH_A; path < rtlphy->num_total_rfpath; ++path)
3277                 rtl8821ae_phy_set_txpower_level_by_path(hw, channel, path);
3278 }
3279
3280 static long _rtl8821ae_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
3281                                             enum wireless_mode wirelessmode,
3282                                             u8 txpwridx)
3283 {
3284         long offset;
3285         long pwrout_dbm;
3286
3287         switch (wirelessmode) {
3288         case WIRELESS_MODE_B:
3289                 offset = -7;
3290                 break;
3291         case WIRELESS_MODE_G:
3292         case WIRELESS_MODE_N_24G:
3293                 offset = -8;
3294                 break;
3295         default:
3296                 offset = -8;
3297                 break;
3298         }
3299         pwrout_dbm = txpwridx / 2 + offset;
3300         return pwrout_dbm;
3301 }
3302
3303 void rtl8821ae_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
3304 {
3305         struct rtl_priv *rtlpriv = rtl_priv(hw);
3306         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3307         enum io_type iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
3308
3309         if (!is_hal_stop(rtlhal)) {
3310                 switch (operation) {
3311                 case SCAN_OPT_BACKUP_BAND0:
3312                         iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
3313                         rtlpriv->cfg->ops->set_hw_reg(hw,
3314                                                       HW_VAR_IO_CMD,
3315                                                       (u8 *)&iotype);
3316
3317                         break;
3318                 case SCAN_OPT_BACKUP_BAND1:
3319                         iotype = IO_CMD_PAUSE_BAND1_DM_BY_SCAN;
3320                         rtlpriv->cfg->ops->set_hw_reg(hw,
3321                                                       HW_VAR_IO_CMD,
3322                                                       (u8 *)&iotype);
3323
3324                         break;
3325                 case SCAN_OPT_RESTORE:
3326                         iotype = IO_CMD_RESUME_DM_BY_SCAN;
3327                         rtlpriv->cfg->ops->set_hw_reg(hw,
3328                                                       HW_VAR_IO_CMD,
3329                                                       (u8 *)&iotype);
3330                         break;
3331                 default:
3332                         pr_err("Unknown Scan Backup operation.\n");
3333                         break;
3334                 }
3335         }
3336 }
3337
3338 static void _rtl8821ae_phy_set_reg_bw(struct rtl_priv *rtlpriv, u8 bw)
3339 {
3340         u16 reg_rf_mode_bw, tmp = 0;
3341
3342         reg_rf_mode_bw = rtl_read_word(rtlpriv, REG_TRXPTCL_CTL);
3343         switch (bw) {
3344         case HT_CHANNEL_WIDTH_20:
3345                 rtl_write_word(rtlpriv, REG_TRXPTCL_CTL, reg_rf_mode_bw & 0xFE7F);
3346                 break;
3347         case HT_CHANNEL_WIDTH_20_40:
3348                 tmp = reg_rf_mode_bw | BIT(7);
3349                 rtl_write_word(rtlpriv, REG_TRXPTCL_CTL, tmp & 0xFEFF);
3350                 break;
3351         case HT_CHANNEL_WIDTH_80:
3352                 tmp = reg_rf_mode_bw | BIT(8);
3353                 rtl_write_word(rtlpriv, REG_TRXPTCL_CTL, tmp & 0xFF7F);
3354                 break;
3355         default:
3356                 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "unknown Bandwidth: 0x%x\n", bw);
3357                 break;
3358         }
3359 }
3360
3361 static u8 _rtl8821ae_phy_get_secondary_chnl(struct rtl_priv *rtlpriv)
3362 {
3363         struct rtl_phy *rtlphy = &rtlpriv->phy;
3364         struct rtl_mac *mac = rtl_mac(rtlpriv);
3365         u8 sc_set_40 = 0, sc_set_20 = 0;
3366
3367         if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) {
3368                 if (mac->cur_80_prime_sc == PRIME_CHNL_OFFSET_LOWER)
3369                         sc_set_40 = VHT_DATA_SC_40_LOWER_OF_80MHZ;
3370                 else if (mac->cur_80_prime_sc == PRIME_CHNL_OFFSET_UPPER)
3371                         sc_set_40 = VHT_DATA_SC_40_UPPER_OF_80MHZ;
3372                 else
3373                         pr_err("SCMapping: Not Correct Primary40MHz Setting\n");
3374
3375                 if ((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_LOWER) &&
3376                         (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_LOWER))
3377                         sc_set_20 = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
3378                 else if ((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_UPPER) &&
3379                         (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_LOWER))
3380                         sc_set_20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
3381                 else if ((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_LOWER) &&
3382                         (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_UPPER))
3383                         sc_set_20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
3384                 else if ((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_UPPER) &&
3385                         (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_UPPER))
3386                         sc_set_20 = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
3387                 else
3388                         pr_err("SCMapping: Not Correct Primary40MHz Setting\n");
3389         } else if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
3390                 if (mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_UPPER)
3391                         sc_set_20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
3392                 else if (mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_LOWER)
3393                         sc_set_20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
3394                 else
3395                         pr_err("SCMapping: Not Correct Primary40MHz Setting\n");
3396         }
3397         return (sc_set_40 << 4) | sc_set_20;
3398 }
3399
3400 void rtl8821ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
3401 {
3402         struct rtl_priv *rtlpriv = rtl_priv(hw);
3403         struct rtl_phy *rtlphy = &rtlpriv->phy;
3404         u8 sub_chnl = 0;
3405         u8 l1pk_val = 0;
3406
3407         rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
3408                 "Switch to %s bandwidth\n",
3409                 (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
3410                  "20MHz" :
3411                  (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40 ?
3412                   "40MHz" : "80MHz")));
3413
3414         _rtl8821ae_phy_set_reg_bw(rtlpriv, rtlphy->current_chan_bw);
3415         sub_chnl = _rtl8821ae_phy_get_secondary_chnl(rtlpriv);
3416         rtl_write_byte(rtlpriv, 0x0483, sub_chnl);
3417
3418         switch (rtlphy->current_chan_bw) {
3419         case HT_CHANNEL_WIDTH_20:
3420                 rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300200);
3421                 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0);
3422
3423                 if (rtlphy->rf_type == RF_2T2R)
3424                         rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, 7);
3425                 else
3426                         rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, 8);
3427                 break;
3428         case HT_CHANNEL_WIDTH_20_40:
3429                 rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300201);
3430                 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0);
3431                 rtl_set_bbreg(hw, RRFMOD, 0x3C, sub_chnl);
3432                 rtl_set_bbreg(hw, RCCAONSEC, 0xf0000000, sub_chnl);
3433
3434                 if (rtlphy->reg_837 & BIT(2))
3435                         l1pk_val = 6;
3436                 else {
3437                         if (rtlphy->rf_type == RF_2T2R)
3438                                 l1pk_val = 7;
3439                         else
3440                                 l1pk_val = 8;
3441                 }
3442                 /* 0x848[25:22] = 0x6 */
3443                 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, l1pk_val);
3444
3445                 if (sub_chnl == VHT_DATA_SC_20_UPPER_OF_80MHZ)
3446                         rtl_set_bbreg(hw, RCCK_SYSTEM, BCCK_SYSTEM, 1);
3447                 else
3448                         rtl_set_bbreg(hw, RCCK_SYSTEM, BCCK_SYSTEM, 0);
3449                 break;
3450
3451         case HT_CHANNEL_WIDTH_80:
3452                  /* 0x8ac[21,20,9:6,1,0]=8'b11100010 */
3453                 rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300202);
3454                 /* 0x8c4[30] = 1 */
3455                 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1);
3456                 rtl_set_bbreg(hw, RRFMOD, 0x3C, sub_chnl);
3457                 rtl_set_bbreg(hw, RCCAONSEC, 0xf0000000, sub_chnl);
3458
3459                 if (rtlphy->reg_837 & BIT(2))
3460                         l1pk_val = 5;
3461                 else {
3462                         if (rtlphy->rf_type == RF_2T2R)
3463                                 l1pk_val = 6;
3464                         else
3465                                 l1pk_val = 7;
3466                 }
3467                 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, l1pk_val);
3468
3469                 break;
3470         default:
3471                 pr_err("unknown bandwidth: %#X\n",
3472                        rtlphy->current_chan_bw);
3473                 break;
3474         }
3475
3476         rtl8812ae_fixspur(hw, rtlphy->current_chan_bw, rtlphy->current_channel);
3477
3478         rtl8821ae_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
3479         rtlphy->set_bwmode_inprogress = false;
3480
3481         rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, "\n");
3482 }
3483
3484 void rtl8821ae_phy_set_bw_mode(struct ieee80211_hw *hw,
3485                             enum nl80211_channel_type ch_type)
3486 {
3487         struct rtl_priv *rtlpriv = rtl_priv(hw);
3488         struct rtl_phy *rtlphy = &rtlpriv->phy;
3489         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3490         u8 tmp_bw = rtlphy->current_chan_bw;
3491
3492         if (rtlphy->set_bwmode_inprogress)
3493                 return;
3494         rtlphy->set_bwmode_inprogress = true;
3495         if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw)))
3496                 rtl8821ae_phy_set_bw_mode_callback(hw);
3497         else {
3498                 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
3499                         "FALSE driver sleep or unload\n");
3500                 rtlphy->set_bwmode_inprogress = false;
3501                 rtlphy->current_chan_bw = tmp_bw;
3502         }
3503 }
3504
3505 void rtl8821ae_phy_sw_chnl_callback(struct ieee80211_hw *hw)
3506 {
3507         struct rtl_priv *rtlpriv = rtl_priv(hw);
3508         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3509         struct rtl_phy *rtlphy = &rtlpriv->phy;
3510         u8 channel = rtlphy->current_channel;
3511         u8 path;
3512         u32 data;
3513
3514         rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
3515                 "switch to channel%d\n", rtlphy->current_channel);
3516         if (is_hal_stop(rtlhal))
3517                 return;
3518
3519         if (36 <= channel && channel <= 48)
3520                 data = 0x494;
3521         else if (50 <= channel && channel <= 64)
3522                 data = 0x453;
3523         else if (100 <= channel && channel <= 116)
3524                 data = 0x452;
3525         else if (118 <= channel)
3526                 data = 0x412;
3527         else
3528                 data = 0x96a;
3529         rtl_set_bbreg(hw, RFC_AREA, 0x1ffe0000, data);
3530
3531         for (path = RF90_PATH_A; path < rtlphy->num_total_rfpath; path++) {
3532                 if (36 <= channel && channel <= 64)
3533                         data = 0x101;
3534                 else if (100 <= channel && channel <= 140)
3535                         data = 0x301;
3536                 else if (140 < channel)
3537                         data = 0x501;
3538                 else
3539                         data = 0x000;
3540                 rtl8821ae_phy_set_rf_reg(hw, path, RF_CHNLBW,
3541                         BIT(18)|BIT(17)|BIT(16)|BIT(9)|BIT(8), data);
3542
3543                 rtl8821ae_phy_set_rf_reg(hw, path, RF_CHNLBW,
3544                         BMASKBYTE0, channel);
3545
3546                 if (channel > 14) {
3547                         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
3548                                 if (36 <= channel && channel <= 64)
3549                                         data = 0x114E9;
3550                                 else
3551                                         data = 0x110E9;
3552                                 rtl8821ae_phy_set_rf_reg(hw, path, RF_APK,
3553                                         BRFREGOFFSETMASK, data);
3554                         }
3555                 }
3556         }
3557         rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
3558 }
3559
3560 u8 rtl8821ae_phy_sw_chnl(struct ieee80211_hw *hw)
3561 {
3562         struct rtl_priv *rtlpriv = rtl_priv(hw);
3563         struct rtl_phy *rtlphy = &rtlpriv->phy;
3564         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3565         u32 timeout = 1000, timecount = 0;
3566         u8 channel = rtlphy->current_channel;
3567
3568         if (rtlphy->sw_chnl_inprogress)
3569                 return 0;
3570         if (rtlphy->set_bwmode_inprogress)
3571                 return 0;
3572
3573         if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
3574                 rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD,
3575                         "sw_chnl_inprogress false driver sleep or unload\n");
3576                 return 0;
3577         }
3578         while (rtlphy->lck_inprogress && timecount < timeout) {
3579                 mdelay(50);
3580                 timecount += 50;
3581         }
3582
3583         if (rtlphy->current_channel > 14 && rtlhal->current_bandtype != BAND_ON_5G)
3584                 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_5G);
3585         else if (rtlphy->current_channel <= 14 && rtlhal->current_bandtype != BAND_ON_2_4G)
3586                 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G);
3587
3588         rtlphy->sw_chnl_inprogress = true;
3589         if (channel == 0)
3590                 channel = 1;
3591
3592         rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
3593                 "switch to channel%d, band type is %d\n",
3594                 rtlphy->current_channel, rtlhal->current_bandtype);
3595
3596         rtl8821ae_phy_sw_chnl_callback(hw);
3597
3598         rtl8821ae_dm_clear_txpower_tracking_state(hw);
3599         rtl8821ae_phy_set_txpower_level(hw, rtlphy->current_channel);
3600
3601         rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
3602         rtlphy->sw_chnl_inprogress = false;
3603         return 1;
3604 }
3605
3606 u8 _rtl8812ae_get_right_chnl_place_for_iqk(u8 chnl)
3607 {
3608         static const u8 channel_all[TARGET_CHNL_NUM_2G_5G_8812] = {
3609                 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
3610                 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54,
3611                 56, 58, 60, 62, 64, 100, 102, 104, 106, 108,
3612                 110, 112, 114, 116, 118, 120, 122, 124, 126,
3613                 128, 130, 132, 134, 136, 138, 140, 149, 151,
3614                 153, 155, 157, 159, 161, 163, 165};
3615         u8 place;
3616
3617         if (chnl > 14) {
3618                 for (place = 14; place < sizeof(channel_all); place++)
3619                         if (channel_all[place] == chnl)
3620                                 return place-13;
3621         }
3622
3623         return 0;
3624 }
3625
3626 #define MACBB_REG_NUM 10
3627 #define AFE_REG_NUM 14
3628 #define RF_REG_NUM 3
3629
3630 static void _rtl8821ae_iqk_backup_macbb(struct ieee80211_hw *hw,
3631                                         u32 *macbb_backup,
3632                                         u32 *backup_macbb_reg, u32 mac_bb_num)
3633 {
3634         struct rtl_priv *rtlpriv = rtl_priv(hw);
3635         u32 i;
3636
3637         rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3638         /*save MACBB default value*/
3639         for (i = 0; i < mac_bb_num; i++)
3640                 macbb_backup[i] = rtl_read_dword(rtlpriv, backup_macbb_reg[i]);
3641
3642         rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "BackupMacBB Success!!!!\n");
3643 }
3644
3645 static void _rtl8821ae_iqk_backup_afe(struct ieee80211_hw *hw, u32 *afe_backup,
3646                                       u32 *backup_afe_REG, u32 afe_num)
3647 {
3648         struct rtl_priv *rtlpriv = rtl_priv(hw);
3649         u32 i;
3650
3651         rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3652         /*Save AFE Parameters */
3653         for (i = 0; i < afe_num; i++)
3654                 afe_backup[i] = rtl_read_dword(rtlpriv, backup_afe_REG[i]);
3655         rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "BackupAFE Success!!!!\n");
3656 }
3657
3658 static void _rtl8821ae_iqk_backup_rf(struct ieee80211_hw *hw, u32 *rfa_backup,
3659                                      u32 *rfb_backup, u32 *backup_rf_reg,
3660                                      u32 rf_num)
3661 {
3662         struct rtl_priv *rtlpriv = rtl_priv(hw);
3663         u32 i;
3664
3665         rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3666         /*Save RF Parameters*/
3667         for (i = 0; i < rf_num; i++) {
3668                 rfa_backup[i] = rtl_get_rfreg(hw, RF90_PATH_A, backup_rf_reg[i],
3669                                               BMASKDWORD);
3670                 rfb_backup[i] = rtl_get_rfreg(hw, RF90_PATH_B, backup_rf_reg[i],
3671                                               BMASKDWORD);
3672         }
3673         rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "BackupRF Success!!!!\n");
3674 }
3675
3676 static void _rtl8821ae_iqk_configure_mac(
3677                 struct ieee80211_hw *hw
3678                 )
3679 {
3680         struct rtl_priv *rtlpriv = rtl_priv(hw);
3681         /* ========MAC register setting========*/
3682         rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3683         rtl_write_byte(rtlpriv, 0x522, 0x3f);
3684         rtl_set_bbreg(hw, 0x550, BIT(11) | BIT(3), 0x0);
3685         rtl_write_byte(rtlpriv, 0x808, 0x00);           /*RX ante off*/
3686         rtl_set_bbreg(hw, 0x838, 0xf, 0xc);             /*CCA off*/
3687 }
3688
3689 static void _rtl8821ae_iqk_tx_fill_iqc(struct ieee80211_hw *hw,
3690                                        enum radio_path path, u32 tx_x, u32 tx_y)
3691 {
3692         struct rtl_priv *rtlpriv = rtl_priv(hw);
3693         switch (path) {
3694         case RF90_PATH_A:
3695                 /* [31] = 1 --> Page C1 */
3696                 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1);
3697                 rtl_write_dword(rtlpriv, 0xc90, 0x00000080);
3698                 rtl_write_dword(rtlpriv, 0xcc4, 0x20040000);
3699                 rtl_write_dword(rtlpriv, 0xcc8, 0x20000000);
3700                 rtl_set_bbreg(hw, 0xccc, 0x000007ff, tx_y);
3701                 rtl_set_bbreg(hw, 0xcd4, 0x000007ff, tx_x);
3702                 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
3703                         "TX_X = %x;;TX_Y = %x =====> fill to IQC\n",
3704                         tx_x, tx_y);
3705                 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
3706                         "0xcd4 = %x;;0xccc = %x ====>fill to IQC\n",
3707                         rtl_get_bbreg(hw, 0xcd4, 0x000007ff),
3708                         rtl_get_bbreg(hw, 0xccc, 0x000007ff));
3709                 break;
3710         default:
3711                 break;
3712         }
3713 }
3714
3715 static void _rtl8821ae_iqk_rx_fill_iqc(struct ieee80211_hw *hw,
3716                                        enum radio_path path, u32 rx_x, u32 rx_y)
3717 {
3718         struct rtl_priv *rtlpriv = rtl_priv(hw);
3719         switch (path) {
3720         case RF90_PATH_A:
3721                 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
3722                 rtl_set_bbreg(hw, 0xc10, 0x000003ff, rx_x>>1);
3723                 rtl_set_bbreg(hw, 0xc10, 0x03ff0000, rx_y>>1);
3724                 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
3725                         "rx_x = %x;;rx_y = %x ====>fill to IQC\n",
3726                         rx_x >> 1, rx_y >> 1);
3727                 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
3728                         "0xc10 = %x ====>fill to IQC\n",
3729                         rtl_read_dword(rtlpriv, 0xc10));
3730                 break;
3731         default:
3732                 break;
3733         }
3734 }
3735
3736 #define cal_num 10
3737
3738 static void _rtl8821ae_iqk_tx(struct ieee80211_hw *hw, enum radio_path path)
3739 {
3740         struct rtl_priv *rtlpriv = rtl_priv(hw);
3741         struct rtl_phy *rtlphy = &rtlpriv->phy;
3742         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3743
3744         u32     tx_fail, rx_fail, delay_count, iqk_ready, cal_retry, cal = 0, temp_reg65;
3745         int     tx_x = 0, tx_y = 0, rx_x = 0, rx_y = 0, tx_average = 0, rx_average = 0;
3746         int     tx_x0[cal_num], tx_y0[cal_num], tx_x0_rxk[cal_num],
3747                 tx_y0_rxk[cal_num], rx_x0[cal_num], rx_y0[cal_num],
3748                 tx_dt[cal_num], rx_dt[cal_num];
3749         bool    tx0iqkok = false, rx0iqkok = false;
3750         bool    vdf_enable = false;
3751         int     i, k, vdf_y[3], vdf_x[3],
3752                 ii, dx = 0, dy = 0, tx_finish = 0, rx_finish = 0;
3753
3754         rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
3755                 "BandWidth = %d.\n",
3756                 rtlphy->current_chan_bw);
3757         if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3758                 vdf_enable = true;
3759
3760         while (cal < cal_num) {
3761                 switch (path) {
3762                 case RF90_PATH_A:
3763                         temp_reg65 = rtl_get_rfreg(hw, path, 0x65, 0xffffffff);
3764                         /* Path-A LOK */
3765                         rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3766                         /*========Path-A AFE all on========*/
3767                         /*Port 0 DAC/ADC on*/
3768                         rtl_write_dword(rtlpriv, 0xc60, 0x77777777);
3769                         rtl_write_dword(rtlpriv, 0xc64, 0x77777777);
3770                         rtl_write_dword(rtlpriv, 0xc68, 0x19791979);
3771                         rtl_write_dword(rtlpriv, 0xc6c, 0x19791979);
3772                         rtl_write_dword(rtlpriv, 0xc70, 0x19791979);
3773                         rtl_write_dword(rtlpriv, 0xc74, 0x19791979);
3774                         rtl_write_dword(rtlpriv, 0xc78, 0x19791979);
3775                         rtl_write_dword(rtlpriv, 0xc7c, 0x19791979);
3776                         rtl_write_dword(rtlpriv, 0xc80, 0x19791979);
3777                         rtl_write_dword(rtlpriv, 0xc84, 0x19791979);
3778
3779                         rtl_set_bbreg(hw, 0xc00, 0xf, 0x4); /*hardware 3-wire off*/
3780
3781                         /* LOK Setting */
3782                         /* ====== LOK ====== */
3783                         /*DAC/ADC sampling rate (160 MHz)*/
3784                         rtl_set_bbreg(hw, 0xc5c, BIT(26) | BIT(25) | BIT(24), 0x7);
3785
3786                         /* 2. LoK RF Setting (at BW = 20M) */
3787                         rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80002);
3788                         rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x3);     /* BW 20M */
3789                         rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x20000);
3790                         rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0003f);
3791                         rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xf3fc3);
3792                         rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d5);
3793                         rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001);
3794                         rtl_set_bbreg(hw, 0xcb8, 0xf, 0xd);
3795                         rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
3796                         rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
3797                         rtl_set_bbreg(hw, 0xc94, BIT(0), 0x1);
3798                         rtl_write_dword(rtlpriv, 0x978, 0x29002000);/* TX (X,Y) */
3799                         rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);/* RX (X,Y) */
3800                         rtl_write_dword(rtlpriv, 0x984, 0x00462910);/* [0]:AGC_en, [15]:idac_K_Mask */
3801
3802                         rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
3803                         rtl_write_dword(rtlpriv, 0xc88, 0x821403f4);
3804
3805                         if (rtlhal->current_bandtype)
3806                                 rtl_write_dword(rtlpriv, 0xc8c, 0x68163e96);
3807                         else
3808                                 rtl_write_dword(rtlpriv, 0xc8c, 0x28163e96);
3809
3810                         rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
3811                         rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */
3812                         rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
3813                         rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
3814                         rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
3815
3816                         mdelay(10); /* Delay 10ms */
3817                         rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
3818
3819                         rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
3820                         rtl_set_rfreg(hw, path, 0x58, 0x7fe00, rtl_get_rfreg(hw, path, 0x8, 0xffc00)); /* Load LOK */
3821
3822                         switch (rtlphy->current_chan_bw) {
3823                         case 1:
3824                                 rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x1);
3825                                 break;
3826                         case 2:
3827                                 rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x0);
3828                                 break;
3829                         default:
3830                                 break;
3831                         }
3832
3833                         rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
3834
3835                         /* 3. TX RF Setting */
3836                         rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
3837                         rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
3838                         rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x20000);
3839                         rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0003f);
3840                         rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xf3fc3);
3841                         rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d5);
3842                         rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001);
3843                         rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
3844                         /* ODM_SetBBReg(pDM_Odm, 0xcb8, 0xf, 0xd); */
3845                         rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
3846                         rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
3847                         rtl_set_bbreg(hw, 0xc94, BIT(0), 0x1);
3848                         rtl_write_dword(rtlpriv, 0x978, 0x29002000);/* TX (X,Y) */
3849                         rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);/* RX (X,Y) */
3850                         rtl_write_dword(rtlpriv, 0x984, 0x0046a910);/* [0]:AGC_en, [15]:idac_K_Mask */
3851
3852                         rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
3853                         rtl_write_dword(rtlpriv, 0xc88, 0x821403f1);
3854                         if (rtlhal->current_bandtype)
3855                                 rtl_write_dword(rtlpriv, 0xc8c, 0x40163e96);
3856                         else
3857                                 rtl_write_dword(rtlpriv, 0xc8c, 0x00163e96);
3858
3859                         if (vdf_enable == 1) {
3860                                 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "VDF_enable\n");
3861                                 for (k = 0; k <= 2; k++) {
3862                                         switch (k) {
3863                                         case 0:
3864                                                 rtl_write_dword(rtlpriv, 0xc80, 0x18008c38);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
3865                                                 rtl_write_dword(rtlpriv, 0xc84, 0x38008c38);/* RX_TONE_idx[9:0], RxK_Mask[29] */
3866                                                 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0);
3867                                                 break;
3868                                         case 1:
3869                                                 rtl_set_bbreg(hw, 0xc80, BIT(28), 0x0);
3870                                                 rtl_set_bbreg(hw, 0xc84, BIT(28), 0x0);
3871                                                 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0);
3872                                                 break;
3873                                         case 2:
3874                                                 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
3875                                                         "vdf_y[1] = %x;;;vdf_y[0] = %x\n", vdf_y[1]>>21 & 0x00007ff, vdf_y[0]>>21 & 0x00007ff);
3876                                                 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
3877                                                         "vdf_x[1] = %x;;;vdf_x[0] = %x\n", vdf_x[1]>>21 & 0x00007ff, vdf_x[0]>>21 & 0x00007ff);
3878                                                 tx_dt[cal] = (vdf_y[1]>>20)-(vdf_y[0]>>20);
3879                                                 tx_dt[cal] = ((16*tx_dt[cal])*10000/15708);
3880                                                 tx_dt[cal] = (tx_dt[cal] >> 1)+(tx_dt[cal] & BIT(0));
3881                                                 rtl_write_dword(rtlpriv, 0xc80, 0x18008c20);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
3882                                                 rtl_write_dword(rtlpriv, 0xc84, 0x38008c20);/* RX_TONE_idx[9:0], RxK_Mask[29] */
3883                                                 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x1);
3884                                                 rtl_set_bbreg(hw, 0xce8, 0x3fff0000, tx_dt[cal] & 0x00003fff);
3885                                                 break;
3886                                         default:
3887                                                 break;
3888                                         }
3889                                         rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
3890                                         cal_retry = 0;
3891                                         while (1) {
3892                                                 /* one shot */
3893                                                 rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
3894                                                 rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
3895
3896                                                 mdelay(10); /* Delay 10ms */
3897                                                 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
3898                                                 delay_count = 0;
3899                                                 while (1) {
3900                                                         iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
3901                                                         if ((~iqk_ready) || (delay_count > 20))
3902                                                                 break;
3903                                                         else{
3904                                                                 mdelay(1);
3905                                                                 delay_count++;
3906                                                         }
3907                                                 }
3908
3909                                                 if (delay_count < 20) {                                                 /* If 20ms No Result, then cal_retry++ */
3910                                                         /* ============TXIQK Check============== */
3911                                                         tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12));
3912
3913                                                         if (~tx_fail) {
3914                                                                 rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
3915                                                                 vdf_x[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
3916                                                                 rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
3917                                                                 vdf_y[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
3918                                                                 tx0iqkok = true;
3919                                                                 break;
3920                                                         } else {
3921                                                                 rtl_set_bbreg(hw, 0xccc, 0x000007ff, 0x0);
3922                                                                 rtl_set_bbreg(hw, 0xcd4, 0x000007ff, 0x200);
3923                                                                 tx0iqkok = false;
3924                                                                 cal_retry++;
3925                                                                 if (cal_retry == 10)
3926                                                                         break;
3927                                                         }
3928                                                 } else {
3929                                                         tx0iqkok = false;
3930                                                         cal_retry++;
3931                                                         if (cal_retry == 10)
3932                                                                 break;
3933                                                 }
3934                                         }
3935                                 }
3936                                 if (k == 3) {
3937                                         tx_x0[cal] = vdf_x[k-1];
3938                                         tx_y0[cal] = vdf_y[k-1];
3939                                 }
3940                         } else {
3941                                 rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
3942                                 rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */
3943                                 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
3944                                 cal_retry = 0;
3945                                 while (1) {
3946                                         /* one shot */
3947                                         rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
3948                                         rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
3949
3950                                         mdelay(10); /* Delay 10ms */
3951                                         rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
3952                                         delay_count = 0;
3953                                         while (1) {
3954                                                 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
3955                                                 if ((~iqk_ready) || (delay_count > 20))
3956                                                         break;
3957                                                 else{
3958                                                         mdelay(1);
3959                                                         delay_count++;
3960                                                 }
3961                                         }
3962
3963                                         if (delay_count < 20) {                                                 /* If 20ms No Result, then cal_retry++ */
3964                                                 /* ============TXIQK Check============== */
3965                                                 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12));
3966
3967                                                 if (~tx_fail) {
3968                                                         rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
3969                                                         tx_x0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
3970                                                         rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
3971                                                         tx_y0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
3972                                                         tx0iqkok = true;
3973                                                         break;
3974                                                 } else {
3975                                                         rtl_set_bbreg(hw, 0xccc, 0x000007ff, 0x0);
3976                                                         rtl_set_bbreg(hw, 0xcd4, 0x000007ff, 0x200);
3977                                                         tx0iqkok = false;
3978                                                         cal_retry++;
3979                                                         if (cal_retry == 10)
3980                                                                 break;
3981                                                 }
3982                                         } else {
3983                                                 tx0iqkok = false;
3984                                                 cal_retry++;
3985                                                 if (cal_retry == 10)
3986                                                         break;
3987                                         }
3988                                 }
3989                         }
3990
3991                         if (tx0iqkok == false)
3992                                 break;                          /* TXK fail, Don't do RXK */
3993
3994                         if (vdf_enable == 1) {
3995                                 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0);    /* TX VDF Disable */
3996                                 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "RXVDF Start\n");
3997                                 for (k = 0; k <= 2; k++) {
3998                                         /* ====== RX mode TXK (RXK Step 1) ====== */
3999                                         rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4000                                         /* 1. TX RF Setting */
4001                                         rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
4002                                         rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000);
4003                                         rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x00029);
4004                                         rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xd7ffb);
4005                                         rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65);
4006                                         rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001);
4007                                         rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
4008
4009                                         rtl_set_bbreg(hw, 0xcb8, 0xf, 0xd);
4010                                         rtl_write_dword(rtlpriv, 0x978, 0x29002000);/* TX (X,Y) */
4011                                         rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);/* RX (X,Y) */
4012                                         rtl_write_dword(rtlpriv, 0x984, 0x0046a910);/* [0]:AGC_en, [15]:idac_K_Mask */
4013                                         rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4014                                         rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
4015                                         rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4016                                         switch (k) {
4017                                         case 0:
4018                                                 {
4019                                                         rtl_write_dword(rtlpriv, 0xc80, 0x18008c38);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
4020                                                         rtl_write_dword(rtlpriv, 0xc84, 0x38008c38);/* RX_TONE_idx[9:0], RxK_Mask[29] */
4021                                                         rtl_set_bbreg(hw, 0xce8, BIT(30), 0x0);
4022                                                 }
4023                                                 break;
4024                                         case 1:
4025                                                 {
4026                                                         rtl_write_dword(rtlpriv, 0xc80, 0x08008c38);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
4027                                                         rtl_write_dword(rtlpriv, 0xc84, 0x28008c38);/* RX_TONE_idx[9:0], RxK_Mask[29] */
4028                                                         rtl_set_bbreg(hw, 0xce8, BIT(30), 0x0);
4029                                                 }
4030                                                 break;
4031                                         case 2:
4032                                                 {
4033                                                         rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
4034                                                                 "VDF_Y[1] = %x;;;VDF_Y[0] = %x\n",
4035                                                                 vdf_y[1] >> 21 & 0x00007ff,
4036                                                                 vdf_y[0] >> 21 & 0x00007ff);
4037                                                         rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
4038                                                                 "VDF_X[1] = %x;;;VDF_X[0] = %x\n",
4039                                                                 vdf_x[1] >> 21 & 0x00007ff,
4040                                                                 vdf_x[0] >> 21 & 0x00007ff);
4041                                                         rx_dt[cal] = (vdf_y[1]>>20)-(vdf_y[0]>>20);
4042                                                         rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "Rx_dt = %d\n",
4043                                                                 rx_dt[cal]);
4044                                                         rx_dt[cal] = ((16*rx_dt[cal])*10000/13823);
4045                                                         rx_dt[cal] = (rx_dt[cal] >> 1)+(rx_dt[cal] & BIT(0));
4046                                                         rtl_write_dword(rtlpriv, 0xc80, 0x18008c20);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
4047                                                         rtl_write_dword(rtlpriv, 0xc84, 0x38008c20);/* RX_TONE_idx[9:0], RxK_Mask[29] */
4048                                                         rtl_set_bbreg(hw, 0xce8, 0x00003fff, rx_dt[cal] & 0x00003fff);
4049                                                 }
4050                                                 break;
4051                                         default:
4052                                                 break;
4053                                         }
4054                                         rtl_write_dword(rtlpriv, 0xc88, 0x821603e0);
4055                                         rtl_write_dword(rtlpriv, 0xc8c, 0x68163e96);
4056                                         rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
4057                                         cal_retry = 0;
4058                                         while (1) {
4059                                                 /* one shot */
4060                                                 rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4061                                                 rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4062
4063                                                 mdelay(10); /* Delay 10ms */
4064                                                 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4065                                                 delay_count = 0;
4066                                                 while (1) {
4067                                                         iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4068                                                         if ((~iqk_ready) || (delay_count > 20))
4069                                                                 break;
4070                                                         else{
4071                                                                 mdelay(1);
4072                                                                 delay_count++;
4073                                                         }
4074                                                 }
4075
4076                                                 if (delay_count < 20) {                                                 /* If 20ms No Result, then cal_retry++ */
4077                                                         /* ============TXIQK Check============== */
4078                                                         tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12));
4079
4080                                                         if (~tx_fail) {
4081                                                                 rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
4082                                                                 tx_x0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4083                                                                 rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
4084                                                                 tx_y0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4085                                                                 tx0iqkok = true;
4086                                                                 break;
4087                                                         } else{
4088                                                                 tx0iqkok = false;
4089                                                                 cal_retry++;
4090                                                                 if (cal_retry == 10)
4091                                                                         break;
4092                                                         }
4093                                                 } else {
4094                                                         tx0iqkok = false;
4095                                                         cal_retry++;
4096                                                         if (cal_retry == 10)
4097                                                                 break;
4098                                                 }
4099                                         }
4100
4101                                         if (tx0iqkok == false) {   /* If RX mode TXK fail, then take TXK Result */
4102                                                 tx_x0_rxk[cal] = tx_x0[cal];
4103                                                 tx_y0_rxk[cal] = tx_y0[cal];
4104                                                 tx0iqkok = true;
4105                                                 rtl_dbg(rtlpriv,
4106                                                         COMP_IQK,
4107                                                         DBG_LOUD,
4108                                                         "RXK Step 1 fail\n");
4109                                         }
4110
4111                                         /* ====== RX IQK ====== */
4112                                         rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4113                                         /* 1. RX RF Setting */
4114                                         rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
4115                                         rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000);
4116                                         rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0002f);
4117                                         rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xfffbb);
4118                                         rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x88001);
4119                                         rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d8);
4120                                         rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
4121
4122                                         rtl_set_bbreg(hw, 0x978, 0x03FF8000, (tx_x0_rxk[cal])>>21&0x000007ff);
4123                                         rtl_set_bbreg(hw, 0x978, 0x000007FF, (tx_y0_rxk[cal])>>21&0x000007ff);
4124                                         rtl_set_bbreg(hw, 0x978, BIT(31), 0x1);
4125                                         rtl_set_bbreg(hw, 0x97c, BIT(31), 0x0);
4126                                         rtl_set_bbreg(hw, 0xcb8, 0xF, 0xe);
4127                                         rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4128                                         rtl_write_dword(rtlpriv, 0x984, 0x0046a911);
4129
4130                                         rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4131                                         rtl_set_bbreg(hw, 0xc80, BIT(29), 0x1);
4132                                         rtl_set_bbreg(hw, 0xc84, BIT(29), 0x0);
4133                                         rtl_write_dword(rtlpriv, 0xc88, 0x02140119);
4134
4135                                         rtl_write_dword(rtlpriv, 0xc8c, 0x28160d00); /* pDM_Odm->SupportInterface == 1 */
4136
4137                                         if (k == 2)
4138                                                 rtl_set_bbreg(hw, 0xce8, BIT(30), 0x1);  /* RX VDF Enable */
4139                                         rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
4140
4141                                         cal_retry = 0;
4142                                         while (1) {
4143                                                 /* one shot */
4144                                                 rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4145                                                 rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4146
4147                                                 mdelay(10); /* Delay 10ms */
4148                                                 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4149                                                 delay_count = 0;
4150                                                 while (1) {
4151                                                         iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4152                                                         if ((~iqk_ready) || (delay_count > 20))
4153                                                                 break;
4154                                                         else{
4155                                                                 mdelay(1);
4156                                                                 delay_count++;
4157                                                         }
4158                                                 }
4159
4160                                                 if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
4161                                                         /* ============RXIQK Check============== */
4162                                                         rx_fail = rtl_get_bbreg(hw, 0xd00, BIT(11));
4163                                                         if (rx_fail == 0) {
4164                                                                 rtl_write_dword(rtlpriv, 0xcb8, 0x06000000);
4165                                                                 vdf_x[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4166                                                                 rtl_write_dword(rtlpriv, 0xcb8, 0x08000000);
4167                                                                 vdf_y[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4168                                                                 rx0iqkok = true;
4169                                                                 break;
4170                                                         } else {
4171                                                                 rtl_set_bbreg(hw, 0xc10, 0x000003ff, 0x200>>1);
4172                                                                 rtl_set_bbreg(hw, 0xc10, 0x03ff0000, 0x0>>1);
4173                                                                 rx0iqkok = false;
4174                                                                 cal_retry++;
4175                                                                 if (cal_retry == 10)
4176                                                                         break;
4177
4178                                                         }
4179                                                 } else{
4180                                                         rx0iqkok = false;
4181                                                         cal_retry++;
4182                                                         if (cal_retry == 10)
4183                                                                 break;
4184                                                 }
4185                                         }
4186
4187                                 }
4188                                 if (k == 3) {
4189                                         rx_x0[cal] = vdf_x[k-1];
4190                                         rx_y0[cal] = vdf_y[k-1];
4191                                 }
4192                                 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x1);    /* TX VDF Enable */
4193                         }
4194
4195                         else{
4196                                 /* ====== RX mode TXK (RXK Step 1) ====== */
4197                                 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4198                                 /* 1. TX RF Setting */
4199                                 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
4200                                 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000);
4201                                 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x00029);
4202                                 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xd7ffb);
4203                                 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65);
4204                                 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001);
4205                                 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
4206                                 rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4207                                 rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
4208                                 rtl_write_dword(rtlpriv, 0x984, 0x0046a910);/* [0]:AGC_en, [15]:idac_K_Mask */
4209
4210                                 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4211                                 rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
4212                                 rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */
4213                                 rtl_write_dword(rtlpriv, 0xc88, 0x821603e0);
4214                                 /* ODM_Write4Byte(pDM_Odm, 0xc8c, 0x68163e96); */
4215                                 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
4216                                 cal_retry = 0;
4217                                 while (1) {
4218                                         /* one shot */
4219                                         rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4220                                         rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4221
4222                                         mdelay(10); /* Delay 10ms */
4223                                         rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4224                                         delay_count = 0;
4225                                         while (1) {
4226                                                 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4227                                                 if ((~iqk_ready) || (delay_count > 20))
4228                                                         break;
4229                                                 else{
4230                                                         mdelay(1);
4231                                                         delay_count++;
4232                                                 }
4233                                         }
4234
4235                                         if (delay_count < 20) {                                                 /* If 20ms No Result, then cal_retry++ */
4236                                                 /* ============TXIQK Check============== */
4237                                                 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12));
4238
4239                                                 if (~tx_fail) {
4240                                                         rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
4241                                                         tx_x0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4242                                                         rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
4243                                                         tx_y0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4244                                                         tx0iqkok = true;
4245                                                         break;
4246                                                 } else {
4247                                                         tx0iqkok = false;
4248                                                         cal_retry++;
4249                                                         if (cal_retry == 10)
4250                                                                 break;
4251                                                 }
4252                                         } else{
4253                                                 tx0iqkok = false;
4254                                                 cal_retry++;
4255                                                 if (cal_retry == 10)
4256                                                         break;
4257                                         }
4258                                 }
4259
4260                                 if (tx0iqkok == false) {   /* If RX mode TXK fail, then take TXK Result */
4261                                         tx_x0_rxk[cal] = tx_x0[cal];
4262                                         tx_y0_rxk[cal] = tx_y0[cal];
4263                                         tx0iqkok = true;
4264                                         rtl_dbg(rtlpriv, COMP_IQK,
4265                                                 DBG_LOUD, "1");
4266                                 }
4267
4268                                 /* ====== RX IQK ====== */
4269                                 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4270                                 /* 1. RX RF Setting */
4271                                 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
4272                                 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000);
4273                                 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0002f);
4274                                 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xfffbb);
4275                                 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x88001);
4276                                 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d8);
4277                                 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
4278
4279                                 rtl_set_bbreg(hw, 0x978, 0x03FF8000, (tx_x0_rxk[cal])>>21&0x000007ff);
4280                                 rtl_set_bbreg(hw, 0x978, 0x000007FF, (tx_y0_rxk[cal])>>21&0x000007ff);
4281                                 rtl_set_bbreg(hw, 0x978, BIT(31), 0x1);
4282                                 rtl_set_bbreg(hw, 0x97c, BIT(31), 0x0);
4283                                 /* ODM_SetBBReg(pDM_Odm, 0xcb8, 0xF, 0xe); */
4284                                 rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4285                                 rtl_write_dword(rtlpriv, 0x984, 0x0046a911);
4286
4287                                 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4288                                 rtl_write_dword(rtlpriv, 0xc80, 0x38008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
4289                                 rtl_write_dword(rtlpriv, 0xc84, 0x18008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */
4290                                 rtl_write_dword(rtlpriv, 0xc88, 0x02140119);
4291
4292                                 rtl_write_dword(rtlpriv, 0xc8c, 0x28160d00); /*pDM_Odm->SupportInterface == 1*/
4293
4294                                 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
4295
4296                                 cal_retry = 0;
4297                                 while (1) {
4298                                         /* one shot */
4299                                         rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4300                                         rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4301
4302                                         mdelay(10); /* Delay 10ms */
4303                                         rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4304                                         delay_count = 0;
4305                                         while (1) {
4306                                                 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4307                                                 if ((~iqk_ready) || (delay_count > 20))
4308                                                         break;
4309                                                 else{
4310                                                         mdelay(1);
4311                                                         delay_count++;
4312                                                 }
4313                                         }
4314
4315                                         if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
4316                                                 /* ============RXIQK Check============== */
4317                                                 rx_fail = rtl_get_bbreg(hw, 0xd00, BIT(11));
4318                                                 if (rx_fail == 0) {
4319                                                         rtl_write_dword(rtlpriv, 0xcb8, 0x06000000);
4320                                                         rx_x0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4321                                                         rtl_write_dword(rtlpriv, 0xcb8, 0x08000000);
4322                                                         rx_y0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4323                                                         rx0iqkok = true;
4324                                                         break;
4325                                                 } else{
4326                                                         rtl_set_bbreg(hw, 0xc10, 0x000003ff, 0x200>>1);
4327                                                         rtl_set_bbreg(hw, 0xc10, 0x03ff0000, 0x0>>1);
4328                                                         rx0iqkok = false;
4329                                                         cal_retry++;
4330                                                         if (cal_retry == 10)
4331                                                                 break;
4332
4333                                                 }
4334                                         } else{
4335                                                 rx0iqkok = false;
4336                                                 cal_retry++;
4337                                                 if (cal_retry == 10)
4338                                                         break;
4339                                         }
4340                                 }
4341                         }
4342
4343                         if (tx0iqkok)
4344                                 tx_average++;
4345                         if (rx0iqkok)
4346                                 rx_average++;
4347                         rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4348                         rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65);
4349                         break;
4350                 default:
4351                         break;
4352                 }
4353                 cal++;
4354         }
4355
4356         /* FillIQK Result */
4357         switch (path) {
4358         case RF90_PATH_A:
4359                 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
4360                         "========Path_A =======\n");
4361                 if (tx_average == 0)
4362                         break;
4363
4364                 for (i = 0; i < tx_average; i++) {
4365                         rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
4366                                 "TX_X0_RXK[%d] = %x ;; TX_Y0_RXK[%d] = %x\n", i,
4367                                 (tx_x0_rxk[i]) >> 21 & 0x000007ff, i,
4368                                 (tx_y0_rxk[i]) >> 21 & 0x000007ff);
4369                         rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
4370                                 "TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", i,
4371                                 (tx_x0[i]) >> 21 & 0x000007ff, i,
4372                                 (tx_y0[i]) >> 21 & 0x000007ff);
4373                 }
4374                 for (i = 0; i < tx_average; i++) {
4375                         for (ii = i+1; ii < tx_average; ii++) {
4376                                 dx = (tx_x0[i]>>21) - (tx_x0[ii]>>21);
4377                                 if (dx < 3 && dx > -3) {
4378                                         dy = (tx_y0[i]>>21) - (tx_y0[ii]>>21);
4379                                         if (dy < 3 && dy > -3) {
4380                                                 tx_x = ((tx_x0[i]>>21) + (tx_x0[ii]>>21))/2;
4381                                                 tx_y = ((tx_y0[i]>>21) + (tx_y0[ii]>>21))/2;
4382                                                 tx_finish = 1;
4383                                                 break;
4384                                         }
4385                                 }
4386                         }
4387                         if (tx_finish == 1)
4388                                 break;
4389                 }
4390
4391                 if (tx_finish == 1)
4392                         _rtl8821ae_iqk_tx_fill_iqc(hw, path, tx_x, tx_y); /* ? */
4393                 else
4394                         _rtl8821ae_iqk_tx_fill_iqc(hw, path, 0x200, 0x0);
4395
4396                 if (rx_average == 0)
4397                         break;
4398
4399                 for (i = 0; i < rx_average; i++)
4400                         rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
4401                                 "RX_X0[%d] = %x ;; RX_Y0[%d] = %x\n", i,
4402                                 (rx_x0[i])>>21&0x000007ff, i,
4403                                 (rx_y0[i])>>21&0x000007ff);
4404                 for (i = 0; i < rx_average; i++) {
4405                         for (ii = i+1; ii < rx_average; ii++) {
4406                                 dx = (rx_x0[i]>>21) - (rx_x0[ii]>>21);
4407                                 if (dx < 4 && dx > -4) {
4408                                         dy = (rx_y0[i]>>21) - (rx_y0[ii]>>21);
4409                                         if (dy < 4 && dy > -4) {
4410                                                 rx_x = ((rx_x0[i]>>21) + (rx_x0[ii]>>21))/2;
4411                                                 rx_y = ((rx_y0[i]>>21) + (rx_y0[ii]>>21))/2;
4412                                                 rx_finish = 1;
4413                                                 break;
4414                                         }
4415                                 }
4416                         }
4417                         if (rx_finish == 1)
4418                                 break;
4419                 }
4420
4421                 if (rx_finish == 1)
4422                         _rtl8821ae_iqk_rx_fill_iqc(hw, path, rx_x, rx_y);
4423                 else
4424                         _rtl8821ae_iqk_rx_fill_iqc(hw, path, 0x200, 0x0);
4425                 break;
4426         default:
4427                 break;
4428         }
4429 }
4430
4431 static void _rtl8821ae_iqk_restore_rf(struct ieee80211_hw *hw,
4432                                       enum radio_path path,
4433                                       u32 *backup_rf_reg,
4434                                       u32 *rf_backup, u32 rf_reg_num)
4435 {
4436         struct rtl_priv *rtlpriv = rtl_priv(hw);
4437         u32 i;
4438
4439         rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4440         for (i = 0; i < RF_REG_NUM; i++)
4441                 rtl_set_rfreg(hw, path, backup_rf_reg[i], RFREG_OFFSET_MASK,
4442                               rf_backup[i]);
4443
4444         switch (path) {
4445         case RF90_PATH_A:
4446                 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
4447                         "RestoreRF Path A Success!!!!\n");
4448                 break;
4449         default:
4450                         break;
4451         }
4452 }
4453
4454 static void _rtl8821ae_iqk_restore_afe(struct ieee80211_hw *hw,
4455                                        u32 *afe_backup, u32 *backup_afe_reg,
4456                                        u32 afe_num)
4457 {
4458         u32 i;
4459         struct rtl_priv *rtlpriv = rtl_priv(hw);
4460
4461         rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4462         /* Reload AFE Parameters */
4463         for (i = 0; i < afe_num; i++)
4464                 rtl_write_dword(rtlpriv, backup_afe_reg[i], afe_backup[i]);
4465         rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4466         rtl_write_dword(rtlpriv, 0xc80, 0x0);
4467         rtl_write_dword(rtlpriv, 0xc84, 0x0);
4468         rtl_write_dword(rtlpriv, 0xc88, 0x0);
4469         rtl_write_dword(rtlpriv, 0xc8c, 0x3c000000);
4470         rtl_write_dword(rtlpriv, 0xc90, 0x00000080);
4471         rtl_write_dword(rtlpriv, 0xc94, 0x00000000);
4472         rtl_write_dword(rtlpriv, 0xcc4, 0x20040000);
4473         rtl_write_dword(rtlpriv, 0xcc8, 0x20000000);
4474         rtl_write_dword(rtlpriv, 0xcb8, 0x0);
4475         rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "RestoreAFE Success!!!!\n");
4476 }
4477
4478 static void _rtl8821ae_iqk_restore_macbb(struct ieee80211_hw *hw,
4479                                          u32 *macbb_backup,
4480                                          u32 *backup_macbb_reg,
4481                                          u32 macbb_num)
4482 {
4483         u32 i;
4484         struct rtl_priv *rtlpriv = rtl_priv(hw);
4485
4486         rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4487         /* Reload MacBB Parameters */
4488         for (i = 0; i < macbb_num; i++)
4489                 rtl_write_dword(rtlpriv, backup_macbb_reg[i], macbb_backup[i]);
4490         rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "RestoreMacBB Success!!!!\n");
4491 }
4492
4493 #undef MACBB_REG_NUM
4494 #undef AFE_REG_NUM
4495 #undef RF_REG_NUM
4496
4497 #define MACBB_REG_NUM 11
4498 #define AFE_REG_NUM 12
4499 #define RF_REG_NUM 3
4500
4501 static void _rtl8821ae_phy_iq_calibrate(struct ieee80211_hw *hw)
4502 {
4503         u32     macbb_backup[MACBB_REG_NUM];
4504         u32 afe_backup[AFE_REG_NUM];
4505         u32 rfa_backup[RF_REG_NUM];
4506         u32 rfb_backup[RF_REG_NUM];
4507         u32 backup_macbb_reg[MACBB_REG_NUM] = {
4508                 0xb00, 0x520, 0x550, 0x808, 0x90c, 0xc00, 0xc50,
4509                 0xe00, 0xe50, 0x838, 0x82c
4510         };
4511         u32 backup_afe_reg[AFE_REG_NUM] = {
4512                 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74,
4513                 0xc78, 0xc7c, 0xc80, 0xc84, 0xcb8
4514         };
4515         u32     backup_rf_reg[RF_REG_NUM] = {0x65, 0x8f, 0x0};
4516
4517         _rtl8821ae_iqk_backup_macbb(hw, macbb_backup, backup_macbb_reg,
4518                                     MACBB_REG_NUM);
4519         _rtl8821ae_iqk_backup_afe(hw, afe_backup, backup_afe_reg, AFE_REG_NUM);
4520         _rtl8821ae_iqk_backup_rf(hw, rfa_backup, rfb_backup, backup_rf_reg,
4521                                  RF_REG_NUM);
4522
4523         _rtl8821ae_iqk_configure_mac(hw);
4524         _rtl8821ae_iqk_tx(hw, RF90_PATH_A);
4525         _rtl8821ae_iqk_restore_rf(hw, RF90_PATH_A, backup_rf_reg, rfa_backup,
4526                                   RF_REG_NUM);
4527
4528         _rtl8821ae_iqk_restore_afe(hw, afe_backup, backup_afe_reg, AFE_REG_NUM);
4529         _rtl8821ae_iqk_restore_macbb(hw, macbb_backup, backup_macbb_reg,
4530                                      MACBB_REG_NUM);
4531 }
4532
4533 static void _rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool main)
4534 {
4535         struct rtl_priv *rtlpriv = rtl_priv(hw);
4536         /* struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); */
4537         /* struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); */
4538         rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
4539
4540         if (main)
4541                 rtl_set_bbreg(hw, RA_RFE_PINMUX + 4, BIT(29) | BIT(28), 0x1);
4542         else
4543                 rtl_set_bbreg(hw, RA_RFE_PINMUX + 4, BIT(29) | BIT(28), 0x2);
4544 }
4545
4546 #undef IQK_ADDA_REG_NUM
4547 #undef IQK_DELAY_TIME
4548
4549 void rtl8812ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
4550 {
4551 }
4552
4553 void rtl8812ae_do_iqk(struct ieee80211_hw *hw, u8 delta_thermal_index,
4554                       u8 thermal_value, u8 threshold)
4555 {
4556         struct rtl_dm   *rtldm = rtl_dm(rtl_priv(hw));
4557
4558         rtldm->thermalvalue_iqk = thermal_value;
4559         rtl8812ae_phy_iq_calibrate(hw, false);
4560 }
4561
4562 void rtl8821ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
4563 {
4564         struct rtl_priv *rtlpriv = rtl_priv(hw);
4565         struct rtl_phy *rtlphy = &rtlpriv->phy;
4566
4567         if (!rtlphy->lck_inprogress) {
4568                 spin_lock(&rtlpriv->locks.iqk_lock);
4569                 rtlphy->lck_inprogress = true;
4570                 spin_unlock(&rtlpriv->locks.iqk_lock);
4571
4572                 _rtl8821ae_phy_iq_calibrate(hw);
4573
4574                 spin_lock(&rtlpriv->locks.iqk_lock);
4575                 rtlphy->lck_inprogress = false;
4576                 spin_unlock(&rtlpriv->locks.iqk_lock);
4577         }
4578 }
4579
4580 void rtl8821ae_reset_iqk_result(struct ieee80211_hw *hw)
4581 {
4582         struct rtl_priv *rtlpriv = rtl_priv(hw);
4583         struct rtl_phy *rtlphy = &rtlpriv->phy;
4584         u8 i;
4585
4586         rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
4587                 "rtl8812ae_dm_reset_iqk_result:: settings regs %d default regs %d\n",
4588                 (int)(sizeof(rtlphy->iqk_matrix) /
4589                 sizeof(struct iqk_matrix_regs)),
4590                 IQK_MATRIX_SETTINGS_NUM);
4591
4592         for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) {
4593                 rtlphy->iqk_matrix[i].value[0][0] = 0x100;
4594                 rtlphy->iqk_matrix[i].value[0][2] = 0x100;
4595                 rtlphy->iqk_matrix[i].value[0][4] = 0x100;
4596                 rtlphy->iqk_matrix[i].value[0][6] = 0x100;
4597
4598                 rtlphy->iqk_matrix[i].value[0][1] = 0x0;
4599                 rtlphy->iqk_matrix[i].value[0][3] = 0x0;
4600                 rtlphy->iqk_matrix[i].value[0][5] = 0x0;
4601                 rtlphy->iqk_matrix[i].value[0][7] = 0x0;
4602
4603                 rtlphy->iqk_matrix[i].iqk_done = false;
4604         }
4605 }
4606
4607 void rtl8821ae_do_iqk(struct ieee80211_hw *hw, u8 delta_thermal_index,
4608                       u8 thermal_value, u8 threshold)
4609 {
4610         struct rtl_dm   *rtldm = rtl_dm(rtl_priv(hw));
4611
4612         rtl8821ae_reset_iqk_result(hw);
4613
4614         rtldm->thermalvalue_iqk = thermal_value;
4615         rtl8821ae_phy_iq_calibrate(hw, false);
4616 }
4617
4618 void rtl8821ae_phy_lc_calibrate(struct ieee80211_hw *hw)
4619 {
4620 }
4621
4622 void rtl8821ae_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta)
4623 {
4624 }
4625
4626 void rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
4627 {
4628         _rtl8821ae_phy_set_rfpath_switch(hw, bmain);
4629 }
4630
4631 bool rtl8821ae_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
4632 {
4633         struct rtl_priv *rtlpriv = rtl_priv(hw);
4634         struct rtl_phy *rtlphy = &rtlpriv->phy;
4635         bool postprocessing = false;
4636
4637         rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
4638                 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
4639                 iotype, rtlphy->set_io_inprogress);
4640         do {
4641                 switch (iotype) {
4642                 case IO_CMD_RESUME_DM_BY_SCAN:
4643                         rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
4644                                 "[IO CMD] Resume DM after scan.\n");
4645                         postprocessing = true;
4646                         break;
4647                 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
4648                 case IO_CMD_PAUSE_BAND1_DM_BY_SCAN:
4649                         rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
4650                                 "[IO CMD] Pause DM before scan.\n");
4651                         postprocessing = true;
4652                         break;
4653                 default:
4654                         pr_err("switch case %#x not processed\n",
4655                                iotype);
4656                         break;
4657                 }
4658         } while (false);
4659         if (postprocessing && !rtlphy->set_io_inprogress) {
4660                 rtlphy->set_io_inprogress = true;
4661                 rtlphy->current_io_type = iotype;
4662         } else {
4663                 return false;
4664         }
4665         rtl8821ae_phy_set_io(hw);
4666         rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
4667         return true;
4668 }
4669
4670 static void rtl8821ae_phy_set_io(struct ieee80211_hw *hw)
4671 {
4672         struct rtl_priv *rtlpriv = rtl_priv(hw);
4673         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
4674         struct rtl_phy *rtlphy = &rtlpriv->phy;
4675
4676         rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
4677                 "--->Cmd(%#x), set_io_inprogress(%d)\n",
4678                 rtlphy->current_io_type, rtlphy->set_io_inprogress);
4679         switch (rtlphy->current_io_type) {
4680         case IO_CMD_RESUME_DM_BY_SCAN:
4681                 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC)
4682                         _rtl8821ae_resume_tx_beacon(hw);
4683                 rtl8821ae_dm_write_dig(hw, rtlphy->initgain_backup.xaagccore1);
4684                 rtl8821ae_dm_write_cck_cca_thres(hw,
4685                                                  rtlphy->initgain_backup.cca);
4686                 break;
4687         case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
4688                 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC)
4689                         _rtl8821ae_stop_tx_beacon(hw);
4690                 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
4691                 rtl8821ae_dm_write_dig(hw, 0x17);
4692                 rtlphy->initgain_backup.cca = dm_digtable->cur_cck_cca_thres;
4693                 rtl8821ae_dm_write_cck_cca_thres(hw, 0x40);
4694                 break;
4695         case IO_CMD_PAUSE_BAND1_DM_BY_SCAN:
4696                 break;
4697         default:
4698                 pr_err("switch case %#x not processed\n",
4699                        rtlphy->current_io_type);
4700                 break;
4701         }
4702         rtlphy->set_io_inprogress = false;
4703         rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
4704                 "(%#x)\n", rtlphy->current_io_type);
4705 }
4706
4707 static void rtl8821ae_phy_set_rf_on(struct ieee80211_hw *hw)
4708 {
4709         struct rtl_priv *rtlpriv = rtl_priv(hw);
4710
4711         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
4712         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
4713         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
4714         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
4715         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
4716 }
4717
4718 static bool _rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
4719                                               enum rf_pwrstate rfpwr_state)
4720 {
4721         struct rtl_priv *rtlpriv = rtl_priv(hw);
4722         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
4723         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
4724         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
4725         bool bresult = true;
4726         u8 i, queue_id;
4727         struct rtl8192_tx_ring *ring = NULL;
4728
4729         switch (rfpwr_state) {
4730         case ERFON:
4731                 if ((ppsc->rfpwr_state == ERFOFF) &&
4732                     RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
4733                         bool rtstatus = false;
4734                         u32 initializecount = 0;
4735
4736                         do {
4737                                 initializecount++;
4738                                 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
4739                                         "IPS Set eRf nic enable\n");
4740                                 rtstatus = rtl_ps_enable_nic(hw);
4741                         } while (!rtstatus && (initializecount < 10));
4742                         RT_CLEAR_PS_LEVEL(ppsc,
4743                                           RT_RF_OFF_LEVL_HALT_NIC);
4744                 } else {
4745                         rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
4746                                 "Set ERFON slept:%d ms\n",
4747                                 jiffies_to_msecs(jiffies -
4748                                                  ppsc->last_sleep_jiffies));
4749                         ppsc->last_awake_jiffies = jiffies;
4750                         rtl8821ae_phy_set_rf_on(hw);
4751                 }
4752                 if (mac->link_state == MAC80211_LINKED) {
4753                         rtlpriv->cfg->ops->led_control(hw,
4754                                                        LED_CTL_LINK);
4755                 } else {
4756                         rtlpriv->cfg->ops->led_control(hw,
4757                                                        LED_CTL_NO_LINK);
4758                 }
4759                 break;
4760         case ERFOFF:
4761                 for (queue_id = 0, i = 0;
4762                      queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
4763                         ring = &pcipriv->dev.tx_ring[queue_id];
4764                         if (queue_id == BEACON_QUEUE ||
4765                             skb_queue_len(&ring->queue) == 0) {
4766                                 queue_id++;
4767                                 continue;
4768                         } else {
4769                                 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
4770                                         "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
4771                                         (i + 1), queue_id,
4772                                         skb_queue_len(&ring->queue));
4773
4774                                 udelay(10);
4775                                 i++;
4776                         }
4777                         if (i >= MAX_DOZE_WAITING_TIMES_9x) {
4778                                 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
4779                                         "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
4780                                         MAX_DOZE_WAITING_TIMES_9x,
4781                                         queue_id,
4782                                         skb_queue_len(&ring->queue));
4783                                 break;
4784                         }
4785                 }
4786
4787                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
4788                         rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
4789                                 "IPS Set eRf nic disable\n");
4790                         rtl_ps_disable_nic(hw);
4791                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
4792                 } else {
4793                         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
4794                                 rtlpriv->cfg->ops->led_control(hw,
4795                                                                LED_CTL_NO_LINK);
4796                         } else {
4797                                 rtlpriv->cfg->ops->led_control(hw,
4798                                                                LED_CTL_POWER_OFF);
4799                         }
4800                 }
4801                 break;
4802         default:
4803                 pr_err("switch case %#x not processed\n",
4804                        rfpwr_state);
4805                 bresult = false;
4806                 break;
4807         }
4808         if (bresult)
4809                 ppsc->rfpwr_state = rfpwr_state;
4810         return bresult;
4811 }
4812
4813 bool rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
4814                                       enum rf_pwrstate rfpwr_state)
4815 {
4816         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
4817
4818         bool bresult = false;
4819
4820         if (rfpwr_state == ppsc->rfpwr_state)
4821                 return bresult;
4822         bresult = _rtl8821ae_phy_set_rf_power_state(hw, rfpwr_state);
4823         return bresult;
4824 }