drivers/net/wireless/realtek/rtlwifi/rtl8192ee/dm.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2009-2014  Realtek Corporation.*/
   3
   4 #include "../wifi.h"
   5 #include "../base.h"
   6 #include "../pci.h"
   7 #include "../core.h"
   8 #include "reg.h"
   9 #include "def.h"
  10 #include "phy.h"
  11 #include "dm.h"
  12 #include "fw.h"
  13 #include "trx.h"
  14
  15 static void rtl92ee_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
  16 {
  17         u32 ret_value;
  18         struct rtl_priv *rtlpriv = rtl_priv(hw);
  19         struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt;
  20
  21         rtl_set_bbreg(hw, DM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1);
  22         rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(31), 1);
  23
  24         ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE1_11N, MASKDWORD);
  25         falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff);
  26         falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16);
  27
  28         ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE2_11N, MASKDWORD);
  29         falsealm_cnt->cnt_ofdm_cca = (ret_value & 0xffff);
  30         falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
  31
  32         ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE3_11N, MASKDWORD);
  33         falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
  34         falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
  35
  36         ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE4_11N, MASKDWORD);
  37         falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
  38
  39         falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
  40                                       falsealm_cnt->cnt_rate_illegal +
  41                                       falsealm_cnt->cnt_crc8_fail +
  42                                       falsealm_cnt->cnt_mcs_fail +
  43                                       falsealm_cnt->cnt_fast_fsync_fail +
  44                                       falsealm_cnt->cnt_sb_search_fail;
  45
  46         ret_value = rtl_get_bbreg(hw, DM_REG_SC_CNT_11N, MASKDWORD);
  47         falsealm_cnt->cnt_bw_lsc = (ret_value & 0xffff);
  48         falsealm_cnt->cnt_bw_usc = ((ret_value & 0xffff0000) >> 16);
  49
  50         rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(12), 1);
  51         rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(14), 1);
  52
  53         ret_value = rtl_get_bbreg(hw, DM_REG_CCK_FA_LSB_11N, MASKBYTE0);
  54         falsealm_cnt->cnt_cck_fail = ret_value;
  55
  56         ret_value = rtl_get_bbreg(hw, DM_REG_CCK_FA_MSB_11N, MASKBYTE3);
  57         falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
  58
  59         ret_value = rtl_get_bbreg(hw, DM_REG_CCK_CCA_CNT_11N, MASKDWORD);
  60         falsealm_cnt->cnt_cck_cca = ((ret_value & 0xff) << 8) |
  61                                     ((ret_value & 0xFF00) >> 8);
  62
  63         falsealm_cnt->cnt_all = falsealm_cnt->cnt_fast_fsync_fail +
  64                                 falsealm_cnt->cnt_sb_search_fail +
  65                                 falsealm_cnt->cnt_parity_fail +
  66                                 falsealm_cnt->cnt_rate_illegal +
  67                                 falsealm_cnt->cnt_crc8_fail +
  68                                 falsealm_cnt->cnt_mcs_fail +
  69                                 falsealm_cnt->cnt_cck_fail;
  70
  71         falsealm_cnt->cnt_cca_all = falsealm_cnt->cnt_ofdm_cca +
  72                                     falsealm_cnt->cnt_cck_cca;
  73
  74         /*reset false alarm counter registers*/
  75         rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTC_11N, BIT(31), 1);
  76         rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTC_11N, BIT(31), 0);
  77         rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(27), 1);
  78         rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(27), 0);
  79         /*update ofdm counter*/
  80         rtl_set_bbreg(hw, DM_REG_OFDM_FA_HOLDC_11N, BIT(31), 0);
  81         rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(31), 0);
  82         /*reset CCK CCA counter*/
  83         rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(13) | BIT(12), 0);
  84         rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(13) | BIT(12), 2);
  85         /*reset CCK FA counter*/
  86         rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 0);
  87         rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 2);
  88
  89         rtl_dbg(rtlpriv, COMP_DIG, DBG_TRACE,
  90                 "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
  91                 falsealm_cnt->cnt_parity_fail,
  92                 falsealm_cnt->cnt_rate_illegal,
  93                 falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail);
  94
  95         rtl_dbg(rtlpriv, COMP_DIG, DBG_TRACE,
  96                 "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
  97                 falsealm_cnt->cnt_ofdm_fail,
  98                 falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all);
  99 }
 100
 101 static void rtl92ee_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
 102 {
 103         struct rtl_priv *rtlpriv = rtl_priv(hw);
 104         struct dig_t *dm_dig = &rtlpriv->dm_digtable;
 105         u8 cur_cck_cca_thresh;
 106
 107         if (rtlpriv->mac80211.link_state >= MAC80211_LINKED) {
 108                 if (dm_dig->rssi_val_min > 25) {
 109                         cur_cck_cca_thresh = 0xcd;
 110                 } else if ((dm_dig->rssi_val_min <= 25) &&
 111                            (dm_dig->rssi_val_min > 10)) {
 112                         cur_cck_cca_thresh = 0x83;
 113                 } else {
 114                         if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000)
 115                                 cur_cck_cca_thresh = 0x83;
 116                         else
 117                                 cur_cck_cca_thresh = 0x40;
 118                 }
 119         } else {
 120                 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000)
 121                         cur_cck_cca_thresh = 0x83;
 122                 else
 123                         cur_cck_cca_thresh = 0x40;
 124         }
 125         rtl92ee_dm_write_cck_cca_thres(hw, cur_cck_cca_thresh);
 126 }
 127
 128 static void rtl92ee_dm_dig(struct ieee80211_hw *hw)
 129 {
 130         struct rtl_priv *rtlpriv = rtl_priv(hw);
 131         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 132         struct dig_t *dm_dig = &rtlpriv->dm_digtable;
 133         u8 dig_min_0, dig_maxofmin;
 134         bool bfirstconnect , bfirstdisconnect;
 135         u8 dm_dig_max, dm_dig_min;
 136         u8 current_igi = dm_dig->cur_igvalue;
 137         u8 offset;
 138
 139         /* AP,BT */
 140         if (mac->act_scanning)
 141                 return;
 142
 143         dig_min_0 = dm_dig->dig_min_0;
 144         bfirstconnect = (mac->link_state >= MAC80211_LINKED) &&
 145                         !dm_dig->media_connect_0;
 146         bfirstdisconnect = (mac->link_state < MAC80211_LINKED) &&
 147                            dm_dig->media_connect_0;
 148
 149         dm_dig_max = 0x5a;
 150         dm_dig_min = DM_DIG_MIN;
 151         dig_maxofmin = DM_DIG_MAX_AP;
 152
 153         if (mac->link_state >= MAC80211_LINKED) {
 154                 if ((dm_dig->rssi_val_min + 10) > dm_dig_max)
 155                         dm_dig->rx_gain_max = dm_dig_max;
 156                 else if ((dm_dig->rssi_val_min + 10) < dm_dig_min)
 157                         dm_dig->rx_gain_max = dm_dig_min;
 158                 else
 159                         dm_dig->rx_gain_max = dm_dig->rssi_val_min + 10;
 160
 161                 if (rtlpriv->dm.one_entry_only) {
 162                         offset = 0;
 163                         if (dm_dig->rssi_val_min - offset < dm_dig_min)
 164                                 dig_min_0 = dm_dig_min;
 165                         else if (dm_dig->rssi_val_min - offset >
 166                                  dig_maxofmin)
 167                                 dig_min_0 = dig_maxofmin;
 168                         else
 169                                 dig_min_0 = dm_dig->rssi_val_min - offset;
 170                 } else {
 171                         dig_min_0 = dm_dig_min;
 172                 }
 173
 174         } else {
 175                 dm_dig->rx_gain_max = dm_dig_max;
 176                 dig_min_0 = dm_dig_min;
 177                 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "no link\n");
 178         }
 179
 180         if (rtlpriv->falsealm_cnt.cnt_all > 10000) {
 181                 if (dm_dig->large_fa_hit != 3)
 182                         dm_dig->large_fa_hit++;
 183                 if (dm_dig->forbidden_igi < current_igi) {
 184                         dm_dig->forbidden_igi = current_igi;
 185                         dm_dig->large_fa_hit = 1;
 186                 }
 187
 188                 if (dm_dig->large_fa_hit >= 3) {
 189                         if (dm_dig->forbidden_igi + 1 > dm_dig->rx_gain_max)
 190                                 dm_dig->rx_gain_min =
 191                                                 dm_dig->rx_gain_max;
 192                         else
 193                                 dm_dig->rx_gain_min =
 194                                                 dm_dig->forbidden_igi + 1;
 195                         dm_dig->recover_cnt = 3600;
 196                 }
 197         } else {
 198                 if (dm_dig->recover_cnt != 0) {
 199                         dm_dig->recover_cnt--;
 200                 } else {
 201                         if (dm_dig->large_fa_hit < 3) {
 202                                 if ((dm_dig->forbidden_igi - 1) <
 203                                     dig_min_0) {
 204                                         dm_dig->forbidden_igi = dig_min_0;
 205                                         dm_dig->rx_gain_min =
 206                                                                 dig_min_0;
 207                                 } else {
 208                                         dm_dig->forbidden_igi--;
 209                                         dm_dig->rx_gain_min =
 210                                                 dm_dig->forbidden_igi + 1;
 211                                 }
 212                         } else {
 213                                 dm_dig->large_fa_hit = 0;
 214                         }
 215                 }
 216         }
 217
 218         if (rtlpriv->dm.dbginfo.num_qry_beacon_pkt < 5)
 219                 dm_dig->rx_gain_min = dm_dig_min;
 220
 221         if (dm_dig->rx_gain_min > dm_dig->rx_gain_max)
 222                 dm_dig->rx_gain_min = dm_dig->rx_gain_max;
 223
 224         if (mac->link_state >= MAC80211_LINKED) {
 225                 if (bfirstconnect) {
 226                         if (dm_dig->rssi_val_min <= dig_maxofmin)
 227                                 current_igi = dm_dig->rssi_val_min;
 228                         else
 229                                 current_igi = dig_maxofmin;
 230
 231                         dm_dig->large_fa_hit = 0;
 232                 } else {
 233                         if (rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH2)
 234                                 current_igi += 4;
 235                         else if (rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH1)
 236                                 current_igi += 2;
 237                         else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
 238                                 current_igi -= 2;
 239
 240                         if (rtlpriv->dm.dbginfo.num_qry_beacon_pkt < 5 &&
 241                             rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
 242                                 current_igi = dm_dig->rx_gain_min;
 243                 }
 244         } else {
 245                 if (bfirstdisconnect) {
 246                         current_igi = dm_dig->rx_gain_min;
 247                 } else {
 248                         if (rtlpriv->falsealm_cnt.cnt_all > 10000)
 249                                 current_igi += 4;
 250                         else if (rtlpriv->falsealm_cnt.cnt_all > 8000)
 251                                 current_igi += 2;
 252                         else if (rtlpriv->falsealm_cnt.cnt_all < 500)
 253                                 current_igi -= 2;
 254                 }
 255         }
 256
 257         if (current_igi > dm_dig->rx_gain_max)
 258                 current_igi = dm_dig->rx_gain_max;
 259         if (current_igi < dm_dig->rx_gain_min)
 260                 current_igi = dm_dig->rx_gain_min;
 261
 262         rtl92ee_dm_write_dig(hw , current_igi);
 263         dm_dig->media_connect_0 = ((mac->link_state >= MAC80211_LINKED) ?
 264                                    true : false);
 265         dm_dig->dig_min_0 = dig_min_0;
 266 }
 267
 268 void rtl92ee_dm_write_cck_cca_thres(struct ieee80211_hw *hw, u8 cur_thres)
 269 {
 270         struct rtl_priv *rtlpriv = rtl_priv(hw);
 271         struct dig_t *dm_dig = &rtlpriv->dm_digtable;
 272
 273         if (dm_dig->cur_cck_cca_thres != cur_thres)
 274                 rtl_write_byte(rtlpriv, DM_REG_CCK_CCA_11N, cur_thres);
 275
 276         dm_dig->pre_cck_cca_thres = dm_dig->cur_cck_cca_thres;
 277         dm_dig->cur_cck_cca_thres = cur_thres;
 278 }
 279
 280 void rtl92ee_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi)
 281 {
 282         struct rtl_priv *rtlpriv = rtl_priv(hw);
 283         struct dig_t *dm_dig = &rtlpriv->dm_digtable;
 284
 285         if (dm_dig->stop_dig)
 286                 return;
 287
 288         if (dm_dig->cur_igvalue != current_igi) {
 289                 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f, current_igi);
 290                 if (rtlpriv->phy.rf_type != RF_1T1R)
 291                         rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f, current_igi);
 292         }
 293         dm_dig->pre_igvalue = dm_dig->cur_igvalue;
 294         dm_dig->cur_igvalue = current_igi;
 295 }
 296
 297 static void rtl92ee_rssi_dump_to_register(struct ieee80211_hw *hw)
 298 {
 299         struct rtl_priv *rtlpriv = rtl_priv(hw);
 300
 301         rtl_write_byte(rtlpriv, RA_RSSIDUMP,
 302                        rtlpriv->stats.rx_rssi_percentage[0]);
 303         rtl_write_byte(rtlpriv, RB_RSSIDUMP,
 304                        rtlpriv->stats.rx_rssi_percentage[1]);
 305         /*It seems the following values are not initialized.
 306           *According to Windows code,
 307           *these value will only be valid with JAGUAR chips
 308           */
 309         /* Rx EVM */
 310         rtl_write_byte(rtlpriv, RS1_RXEVMDUMP, rtlpriv->stats.rx_evm_dbm[0]);
 311         rtl_write_byte(rtlpriv, RS2_RXEVMDUMP, rtlpriv->stats.rx_evm_dbm[1]);
 312         /* Rx SNR */
 313         rtl_write_byte(rtlpriv, RA_RXSNRDUMP,
 314                        (u8)(rtlpriv->stats.rx_snr_db[0]));
 315         rtl_write_byte(rtlpriv, RB_RXSNRDUMP,
 316                        (u8)(rtlpriv->stats.rx_snr_db[1]));
 317         /* Rx Cfo_Short */
 318         rtl_write_word(rtlpriv, RA_CFOSHORTDUMP,
 319                        rtlpriv->stats.rx_cfo_short[0]);
 320         rtl_write_word(rtlpriv, RB_CFOSHORTDUMP,
 321                        rtlpriv->stats.rx_cfo_short[1]);
 322         /* Rx Cfo_Tail */
 323         rtl_write_word(rtlpriv, RA_CFOLONGDUMP, rtlpriv->stats.rx_cfo_tail[0]);
 324         rtl_write_word(rtlpriv, RB_CFOLONGDUMP, rtlpriv->stats.rx_cfo_tail[1]);
 325 }
 326
 327 static void rtl92ee_dm_find_minimum_rssi(struct ieee80211_hw *hw)
 328 {
 329         struct rtl_priv *rtlpriv = rtl_priv(hw);
 330         struct dig_t *rtl_dm_dig = &rtlpriv->dm_digtable;
 331         struct rtl_mac *mac = rtl_mac(rtlpriv);
 332
 333         /* Determine the minimum RSSI  */
 334         if ((mac->link_state < MAC80211_LINKED) &&
 335             (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
 336                 rtl_dm_dig->min_undec_pwdb_for_dm = 0;
 337                 rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
 338                         "Not connected to any\n");
 339         }
 340         if (mac->link_state >= MAC80211_LINKED) {
 341                 if (mac->opmode == NL80211_IFTYPE_AP ||
 342                     mac->opmode == NL80211_IFTYPE_ADHOC) {
 343                         rtl_dm_dig->min_undec_pwdb_for_dm =
 344                                 rtlpriv->dm.entry_min_undec_sm_pwdb;
 345                         rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
 346                                 "AP Client PWDB = 0x%lx\n",
 347                                 rtlpriv->dm.entry_min_undec_sm_pwdb);
 348                 } else {
 349                         rtl_dm_dig->min_undec_pwdb_for_dm =
 350                             rtlpriv->dm.undec_sm_pwdb;
 351                         rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
 352                                 "STA Default Port PWDB = 0x%x\n",
 353                                 rtl_dm_dig->min_undec_pwdb_for_dm);
 354                 }
 355         } else {
 356                 rtl_dm_dig->min_undec_pwdb_for_dm =
 357                         rtlpriv->dm.entry_min_undec_sm_pwdb;
 358                 rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
 359                         "AP Ext Port or disconnect PWDB = 0x%x\n",
 360                         rtl_dm_dig->min_undec_pwdb_for_dm);
 361         }
 362         rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
 363                 "MinUndecoratedPWDBForDM =%d\n",
 364                 rtl_dm_dig->min_undec_pwdb_for_dm);
 365 }
 366
 367 static void rtl92ee_dm_check_rssi_monitor(struct ieee80211_hw *hw)
 368 {
 369         struct rtl_priv *rtlpriv = rtl_priv(hw);
 370         struct dig_t *dm_dig = &rtlpriv->dm_digtable;
 371         struct rtl_mac *mac = rtl_mac(rtlpriv);
 372         struct rtl_dm *dm = rtl_dm(rtlpriv);
 373         struct rtl_sta_info *drv_priv;
 374         u8 h2c[4] = { 0 };
 375         long max = 0, min = 0xff;
 376         u8 i = 0;
 377
 378         if (mac->opmode == NL80211_IFTYPE_AP ||
 379             mac->opmode == NL80211_IFTYPE_ADHOC ||
 380             mac->opmode == NL80211_IFTYPE_MESH_POINT) {
 381                 /* AP & ADHOC & MESH */
 382                 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
 383                 list_for_each_entry(drv_priv, &rtlpriv->entry_list, list) {
 384                         struct rssi_sta *stat = &drv_priv->rssi_stat;
 385
 386                         if (stat->undec_sm_pwdb < min)
 387                                 min = stat->undec_sm_pwdb;
 388                         if (stat->undec_sm_pwdb > max)
 389                                 max = stat->undec_sm_pwdb;
 390
 391                         h2c[3] = 0;
 392                         h2c[2] = (u8)(dm->undec_sm_pwdb & 0xFF);
 393                         h2c[1] = 0x20;
 394                         h2c[0] = ++i;
 395                         rtl92ee_fill_h2c_cmd(hw, H2C_92E_RSSI_REPORT, 4, h2c);
 396                 }
 397                 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
 398
 399                 /* If associated entry is found */
 400                 if (max != 0) {
 401                         dm->entry_max_undec_sm_pwdb = max;
 402                         RTPRINT(rtlpriv, FDM, DM_PWDB,
 403                                 "EntryMaxPWDB = 0x%lx(%ld)\n", max, max);
 404                 } else {
 405                         dm->entry_max_undec_sm_pwdb = 0;
 406                 }
 407                 /* If associated entry is found */
 408                 if (min != 0xff) {
 409                         dm->entry_min_undec_sm_pwdb = min;
 410                         RTPRINT(rtlpriv, FDM, DM_PWDB,
 411                                 "EntryMinPWDB = 0x%lx(%ld)\n", min, min);
 412                 } else {
 413                         dm->entry_min_undec_sm_pwdb = 0;
 414                 }
 415         }
 416
 417         /* Indicate Rx signal strength to FW. */
 418         if (dm->useramask) {
 419                 h2c[3] = 0;
 420                 h2c[2] = (u8)(dm->undec_sm_pwdb & 0xFF);
 421                 h2c[1] = 0x20;
 422                 h2c[0] = 0;
 423                 rtl92ee_fill_h2c_cmd(hw, H2C_92E_RSSI_REPORT, 4, h2c);
 424         } else {
 425                 rtl_write_byte(rtlpriv, 0x4fe, dm->undec_sm_pwdb);
 426         }
 427         rtl92ee_rssi_dump_to_register(hw);
 428         rtl92ee_dm_find_minimum_rssi(hw);
 429         dm_dig->rssi_val_min = rtlpriv->dm_digtable.min_undec_pwdb_for_dm;
 430 }
 431
 432 static void rtl92ee_dm_init_primary_cca_check(struct ieee80211_hw *hw)
 433 {
 434         struct rtl_priv *rtlpriv = rtl_priv(hw);
 435         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
 436         struct dynamic_primary_cca *primarycca = &rtlpriv->primarycca;
 437
 438         rtlhal->rts_en = 0;
 439         primarycca->dup_rts_flag = 0;
 440         primarycca->intf_flag = 0;
 441         primarycca->intf_type = 0;
 442         primarycca->monitor_flag = 0;
 443         primarycca->ch_offset = 0;
 444         primarycca->mf_state = 0;
 445 }
 446
 447 static bool rtl92ee_dm_is_edca_turbo_disable(struct ieee80211_hw *hw)
 448 {
 449         struct rtl_priv *rtlpriv = rtl_priv(hw);
 450
 451         if (rtlpriv->mac80211.mode == WIRELESS_MODE_B)
 452                 return true;
 453
 454         return false;
 455 }
 456
 457 void rtl92ee_dm_init_edca_turbo(struct ieee80211_hw *hw)
 458 {
 459         struct rtl_priv *rtlpriv = rtl_priv(hw);
 460
 461         rtlpriv->dm.current_turbo_edca = false;
 462         rtlpriv->dm.is_cur_rdlstate = false;
 463         rtlpriv->dm.is_any_nonbepkts = false;
 464 }
 465
 466 static void rtl92ee_dm_check_edca_turbo(struct ieee80211_hw *hw)
 467 {
 468         struct rtl_priv *rtlpriv = rtl_priv(hw);
 469
 470         static u64 last_txok_cnt;
 471         static u64 last_rxok_cnt;
 472         u64 cur_txok_cnt = 0;
 473         u64 cur_rxok_cnt = 0;
 474         u32 edca_be_ul = 0x5ea42b;
 475         u32 edca_be_dl = 0x5ea42b; /*not sure*/
 476         u32 edca_be = 0x5ea42b;
 477         bool is_cur_rdlstate;
 478         bool b_edca_turbo_on = false;
 479
 480         if (rtlpriv->dm.dbginfo.num_non_be_pkt > 0x100)
 481                 rtlpriv->dm.is_any_nonbepkts = true;
 482         rtlpriv->dm.dbginfo.num_non_be_pkt = 0;
 483
 484         cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
 485         cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
 486
 487         /*b_bias_on_rx = false;*/
 488         b_edca_turbo_on = ((!rtlpriv->dm.is_any_nonbepkts) &&
 489                            (!rtlpriv->dm.disable_framebursting)) ?
 490                           true : false;
 491
 492         if (rtl92ee_dm_is_edca_turbo_disable(hw))
 493                 goto check_exit;
 494
 495         if (b_edca_turbo_on) {
 496                 is_cur_rdlstate = (cur_rxok_cnt > cur_txok_cnt * 4) ?
 497                                     true : false;
 498
 499                 edca_be = is_cur_rdlstate ? edca_be_dl : edca_be_ul;
 500                 rtl_write_dword(rtlpriv , REG_EDCA_BE_PARAM , edca_be);
 501                 rtlpriv->dm.is_cur_rdlstate = is_cur_rdlstate;
 502                 rtlpriv->dm.current_turbo_edca = true;
 503         } else {
 504                 if (rtlpriv->dm.current_turbo_edca) {
 505                         u8 tmp = AC0_BE;
 506
 507                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
 508                                                       (u8 *)(&tmp));
 509                 }
 510                 rtlpriv->dm.current_turbo_edca = false;
 511         }
 512
 513 check_exit:
 514         rtlpriv->dm.is_any_nonbepkts = false;
 515         last_txok_cnt = rtlpriv->stats.txbytesunicast;
 516         last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
 517 }
 518
 519 static void rtl92ee_dm_dynamic_edcca(struct ieee80211_hw *hw)
 520 {
 521         struct rtl_priv *rtlpriv = rtl_priv(hw);
 522         u8 reg_c50 , reg_c58;
 523         bool fw_current_in_ps_mode = false;
 524
 525         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 526                                       (u8 *)(&fw_current_in_ps_mode));
 527         if (fw_current_in_ps_mode)
 528                 return;
 529
 530         reg_c50 = rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
 531         reg_c58 = rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
 532
 533         if (reg_c50 > 0x28 && reg_c58 > 0x28) {
 534                 if (!rtlpriv->rtlhal.pre_edcca_enable) {
 535                         rtl_write_byte(rtlpriv, ROFDM0_ECCATHRESHOLD, 0x03);
 536                         rtl_write_byte(rtlpriv, ROFDM0_ECCATHRESHOLD + 2, 0x00);
 537                         rtlpriv->rtlhal.pre_edcca_enable = true;
 538                 }
 539         } else if (reg_c50 < 0x25 && reg_c58 < 0x25) {
 540                 if (rtlpriv->rtlhal.pre_edcca_enable) {
 541                         rtl_write_byte(rtlpriv, ROFDM0_ECCATHRESHOLD, 0x7f);
 542                         rtl_write_byte(rtlpriv, ROFDM0_ECCATHRESHOLD + 2, 0x7f);
 543                         rtlpriv->rtlhal.pre_edcca_enable = false;
 544                 }
 545         }
 546 }
 547
 548 static void rtl92ee_dm_adaptivity(struct ieee80211_hw *hw)
 549 {
 550         rtl92ee_dm_dynamic_edcca(hw);
 551 }
 552
 553 static void rtl92ee_dm_write_dynamic_cca(struct ieee80211_hw *hw,
 554                                          u8 cur_mf_state)
 555 {
 556         struct dynamic_primary_cca *primarycca = &rtl_priv(hw)->primarycca;
 557
 558         if (primarycca->mf_state != cur_mf_state)
 559                 rtl_set_bbreg(hw, DM_REG_L1SBD_PD_CH_11N, BIT(8) | BIT(7),
 560                               cur_mf_state);
 561
 562         primarycca->mf_state = cur_mf_state;
 563 }
 564
 565 static void rtl92ee_dm_dynamic_primary_cca_ckeck(struct ieee80211_hw *hw)
 566 {
 567         struct rtl_priv *rtlpriv = rtl_priv(hw);
 568         struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt;
 569         struct dynamic_primary_cca *primarycca = &rtlpriv->primarycca;
 570         bool is40mhz = false;
 571         u64 ofdm_cca, ofdm_fa, bw_usc_cnt, bw_lsc_cnt;
 572         u8 sec_ch_offset;
 573         u8 cur_mf_state;
 574         static u8 count_down = MONITOR_TIME;
 575
 576         ofdm_cca = falsealm_cnt->cnt_ofdm_cca;
 577         ofdm_fa = falsealm_cnt->cnt_ofdm_fail;
 578         bw_usc_cnt = falsealm_cnt->cnt_bw_usc;
 579         bw_lsc_cnt = falsealm_cnt->cnt_bw_lsc;
 580         is40mhz = rtlpriv->mac80211.bw_40;
 581         sec_ch_offset = rtlpriv->mac80211.cur_40_prime_sc;
 582         /* NIC: 2: sec is below,  1: sec is above */
 583
 584         if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) {
 585                 cur_mf_state = MF_USC_LSC;
 586                 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
 587                 return;
 588         }
 589
 590         if (rtlpriv->mac80211.link_state < MAC80211_LINKED)
 591                 return;
 592
 593         if (is40mhz)
 594                 return;
 595
 596         if (primarycca->pricca_flag == 0) {
 597                 /* Primary channel is above
 598                  * NOTE: duplicate CTS can remove this condition
 599                  */
 600                 if (sec_ch_offset == 2) {
 601                         if ((ofdm_cca > OFDMCCA_TH) &&
 602                             (bw_lsc_cnt > (bw_usc_cnt + BW_IND_BIAS)) &&
 603                             (ofdm_fa > (ofdm_cca >> 1))) {
 604                                 primarycca->intf_type = 1;
 605                                 primarycca->intf_flag = 1;
 606                                 cur_mf_state = MF_USC;
 607                                 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
 608                                 primarycca->pricca_flag = 1;
 609                         } else if ((ofdm_cca > OFDMCCA_TH) &&
 610                                    (bw_lsc_cnt > (bw_usc_cnt + BW_IND_BIAS)) &&
 611                                    (ofdm_fa < (ofdm_cca >> 1))) {
 612                                 primarycca->intf_type = 2;
 613                                 primarycca->intf_flag = 1;
 614                                 cur_mf_state = MF_USC;
 615                                 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
 616                                 primarycca->pricca_flag = 1;
 617                                 primarycca->dup_rts_flag = 1;
 618                                 rtlpriv->rtlhal.rts_en = 1;
 619                         } else {
 620                                 primarycca->intf_type = 0;
 621                                 primarycca->intf_flag = 0;
 622                                 cur_mf_state = MF_USC_LSC;
 623                                 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
 624                                 rtlpriv->rtlhal.rts_en = 0;
 625                                 primarycca->dup_rts_flag = 0;
 626                         }
 627                 } else if (sec_ch_offset == 1) {
 628                         if ((ofdm_cca > OFDMCCA_TH) &&
 629                             (bw_usc_cnt > (bw_lsc_cnt + BW_IND_BIAS)) &&
 630                             (ofdm_fa > (ofdm_cca >> 1))) {
 631                                 primarycca->intf_type = 1;
 632                                 primarycca->intf_flag = 1;
 633                                 cur_mf_state = MF_LSC;
 634                                 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
 635                                 primarycca->pricca_flag = 1;
 636                         } else if ((ofdm_cca > OFDMCCA_TH) &&
 637                                    (bw_usc_cnt > (bw_lsc_cnt + BW_IND_BIAS)) &&
 638                                    (ofdm_fa < (ofdm_cca >> 1))) {
 639                                 primarycca->intf_type = 2;
 640                                 primarycca->intf_flag = 1;
 641                                 cur_mf_state = MF_LSC;
 642                                 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
 643                                 primarycca->pricca_flag = 1;
 644                                 primarycca->dup_rts_flag = 1;
 645                                 rtlpriv->rtlhal.rts_en = 1;
 646                         } else {
 647                                 primarycca->intf_type = 0;
 648                                 primarycca->intf_flag = 0;
 649                                 cur_mf_state = MF_USC_LSC;
 650                                 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
 651                                 rtlpriv->rtlhal.rts_en = 0;
 652                                 primarycca->dup_rts_flag = 0;
 653                         }
 654                 }
 655         } else {/* PrimaryCCA->PriCCA_flag==1 */
 656                 count_down--;
 657                 if (count_down == 0) {
 658                         count_down = MONITOR_TIME;
 659                         primarycca->pricca_flag = 0;
 660                         cur_mf_state = MF_USC_LSC;
 661                         /* default */
 662                         rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
 663                         rtlpriv->rtlhal.rts_en = 0;
 664                         primarycca->dup_rts_flag = 0;
 665                         primarycca->intf_type = 0;
 666                         primarycca->intf_flag = 0;
 667                 }
 668         }
 669 }
 670
 671 static void rtl92ee_dm_dynamic_atc_switch(struct ieee80211_hw *hw)
 672 {
 673         struct rtl_priv *rtlpriv = rtl_priv(hw);
 674         struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
 675         u8 crystal_cap;
 676         u32 packet_count;
 677         int cfo_khz_a , cfo_khz_b , cfo_ave = 0, adjust_xtal = 0;
 678         int cfo_ave_diff;
 679
 680         if (rtlpriv->mac80211.link_state < MAC80211_LINKED) {
 681                 if (rtldm->atc_status == ATC_STATUS_OFF) {
 682                         rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11),
 683                                       ATC_STATUS_ON);
 684                         rtldm->atc_status = ATC_STATUS_ON;
 685                 }
 686                 /* Disable CFO tracking for BT */
 687                 if (rtlpriv->cfg->ops->get_btc_status()) {
 688                         if (!rtlpriv->btcoexist.btc_ops->
 689                             btc_is_bt_disabled(rtlpriv)) {
 690                                 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
 691                                         "odm_DynamicATCSwitch(): Disable CFO tracking for BT!!\n");
 692                                 return;
 693                         }
 694                 }
 695                 /* Reset Crystal Cap */
 696                 if (rtldm->crystal_cap != rtlpriv->efuse.crystalcap) {
 697                         rtldm->crystal_cap = rtlpriv->efuse.crystalcap;
 698                         crystal_cap = rtldm->crystal_cap & 0x3f;
 699                         rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000,
 700                                       (crystal_cap | (crystal_cap << 6)));
 701                 }
 702         } else {
 703                 cfo_khz_a = (int)(rtldm->cfo_tail[0] * 3125) / 1280;
 704                 cfo_khz_b = (int)(rtldm->cfo_tail[1] * 3125) / 1280;
 705                 packet_count = rtldm->packet_count;
 706
 707                 if (packet_count == rtldm->packet_count_pre)
 708                         return;
 709
 710                 rtldm->packet_count_pre = packet_count;
 711
 712                 if (rtlpriv->phy.rf_type == RF_1T1R)
 713                         cfo_ave = cfo_khz_a;
 714                 else
 715                         cfo_ave = (int)(cfo_khz_a + cfo_khz_b) >> 1;
 716
 717                 cfo_ave_diff = (rtldm->cfo_ave_pre >= cfo_ave) ?
 718                                (rtldm->cfo_ave_pre - cfo_ave) :
 719                                (cfo_ave - rtldm->cfo_ave_pre);
 720
 721                 if (cfo_ave_diff > 20 && !rtldm->large_cfo_hit) {
 722                         rtldm->large_cfo_hit = true;
 723                         return;
 724                 }
 725                 rtldm->large_cfo_hit = false;
 726
 727                 rtldm->cfo_ave_pre = cfo_ave;
 728
 729                 if (cfo_ave >= -rtldm->cfo_threshold &&
 730                     cfo_ave <= rtldm->cfo_threshold && rtldm->is_freeze == 0) {
 731                         if (rtldm->cfo_threshold == CFO_THRESHOLD_XTAL) {
 732                                 rtldm->cfo_threshold = CFO_THRESHOLD_XTAL + 10;
 733                                 rtldm->is_freeze = 1;
 734                         } else {
 735                                 rtldm->cfo_threshold = CFO_THRESHOLD_XTAL;
 736                         }
 737                 }
 738
 739                 if (cfo_ave > rtldm->cfo_threshold && rtldm->crystal_cap < 0x3f)
 740                         adjust_xtal = ((cfo_ave - CFO_THRESHOLD_XTAL) >> 2) + 1;
 741                 else if ((cfo_ave < -rtlpriv->dm.cfo_threshold) &&
 742                          rtlpriv->dm.crystal_cap > 0)
 743                         adjust_xtal = ((cfo_ave + CFO_THRESHOLD_XTAL) >> 2) - 1;
 744
 745                 if (adjust_xtal != 0) {
 746                         rtldm->is_freeze = 0;
 747                         rtldm->crystal_cap += adjust_xtal;
 748
 749                         if (rtldm->crystal_cap > 0x3f)
 750                                 rtldm->crystal_cap = 0x3f;
 751                         else if (rtldm->crystal_cap < 0)
 752                                 rtldm->crystal_cap = 0;
 753
 754                         crystal_cap = rtldm->crystal_cap & 0x3f;
 755                         rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000,
 756                                       (crystal_cap | (crystal_cap << 6)));
 757                 }
 758
 759                 if (cfo_ave < CFO_THRESHOLD_ATC &&
 760                     cfo_ave > -CFO_THRESHOLD_ATC) {
 761                         if (rtldm->atc_status == ATC_STATUS_ON) {
 762                                 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11),
 763                                               ATC_STATUS_OFF);
 764                                 rtldm->atc_status = ATC_STATUS_OFF;
 765                         }
 766                 } else {
 767                         if (rtldm->atc_status == ATC_STATUS_OFF) {
 768                                 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11),
 769                                               ATC_STATUS_ON);
 770                                 rtldm->atc_status = ATC_STATUS_ON;
 771                         }
 772                 }
 773         }
 774 }
 775
 776 static void rtl92ee_dm_init_txpower_tracking(struct ieee80211_hw *hw)
 777 {
 778         struct rtl_priv *rtlpriv = rtl_priv(hw);
 779         struct rtl_dm *dm = rtl_dm(rtlpriv);
 780         u8 path;
 781
 782         dm->txpower_tracking = true;
 783         dm->default_ofdm_index = 30;
 784         dm->default_cck_index = 20;
 785
 786         dm->swing_idx_cck_base = dm->default_cck_index;
 787         dm->cck_index = dm->default_cck_index;
 788
 789         for (path = RF90_PATH_A; path < MAX_RF_PATH; path++) {
 790                 dm->swing_idx_ofdm_base[path] = dm->default_ofdm_index;
 791                 dm->ofdm_index[path] = dm->default_ofdm_index;
 792                 dm->delta_power_index[path] = 0;
 793                 dm->delta_power_index_last[path] = 0;
 794                 dm->power_index_offset[path] = 0;
 795         }
 796 }
 797
 798 void rtl92ee_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
 799 {
 800         struct rtl_priv *rtlpriv = rtl_priv(hw);
 801         struct rate_adaptive *p_ra = &rtlpriv->ra;
 802
 803         p_ra->ratr_state = DM_RATR_STA_INIT;
 804         p_ra->pre_ratr_state = DM_RATR_STA_INIT;
 805
 806         if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
 807                 rtlpriv->dm.useramask = true;
 808         else
 809                 rtlpriv->dm.useramask = false;
 810
 811         p_ra->ldpc_thres = 35;
 812         p_ra->use_ldpc = false;
 813         p_ra->high_rssi_thresh_for_ra = 50;
 814         p_ra->low_rssi_thresh_for_ra40m = 20;
 815 }
 816
 817 static bool _rtl92ee_dm_ra_state_check(struct ieee80211_hw *hw,
 818                                        s32 rssi, u8 *ratr_state)
 819 {
 820         struct rtl_priv *rtlpriv = rtl_priv(hw);
 821         struct rate_adaptive *p_ra = &rtlpriv->ra;
 822         const u8 go_up_gap = 5;
 823         u32 high_rssithresh_for_ra = p_ra->high_rssi_thresh_for_ra;
 824         u32 low_rssithresh_for_ra = p_ra->low_rssi_thresh_for_ra40m;
 825         u8 state;
 826
 827         /* Threshold Adjustment:
 828          * when RSSI state trends to go up one or two levels,
 829          * make sure RSSI is high enough.
 830          * Here GoUpGap is added to solve
 831          * the boundary's level alternation issue.
 832          */
 833         switch (*ratr_state) {
 834         case DM_RATR_STA_INIT:
 835         case DM_RATR_STA_HIGH:
 836                 break;
 837         case DM_RATR_STA_MIDDLE:
 838                 high_rssithresh_for_ra += go_up_gap;
 839                 break;
 840         case DM_RATR_STA_LOW:
 841                 high_rssithresh_for_ra += go_up_gap;
 842                 low_rssithresh_for_ra += go_up_gap;
 843                 break;
 844         default:
 845                 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
 846                         "wrong rssi level setting %d !\n", *ratr_state);
 847                 break;
 848         }
 849
 850         /* Decide RATRState by RSSI. */
 851         if (rssi > high_rssithresh_for_ra)
 852                 state = DM_RATR_STA_HIGH;
 853         else if (rssi > low_rssithresh_for_ra)
 854                 state = DM_RATR_STA_MIDDLE;
 855         else
 856                 state = DM_RATR_STA_LOW;
 857
 858         if (*ratr_state != state) {
 859                 *ratr_state = state;
 860                 return true;
 861         }
 862
 863         return false;
 864 }
 865
 866 static void rtl92ee_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
 867 {
 868         struct rtl_priv *rtlpriv = rtl_priv(hw);
 869         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 870         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 871         struct rate_adaptive *p_ra = &rtlpriv->ra;
 872         struct ieee80211_sta *sta = NULL;
 873
 874         if (is_hal_stop(rtlhal)) {
 875                 rtl_dbg(rtlpriv, COMP_RATE, DBG_LOUD,
 876                         "driver is going to unload\n");
 877                 return;
 878         }
 879
 880         if (!rtlpriv->dm.useramask) {
 881                 rtl_dbg(rtlpriv, COMP_RATE, DBG_LOUD,
 882                         "driver does not control rate adaptive mask\n");
 883                 return;
 884         }
 885
 886         if (mac->link_state == MAC80211_LINKED &&
 887             mac->opmode == NL80211_IFTYPE_STATION) {
 888                 if (rtlpriv->dm.undec_sm_pwdb < p_ra->ldpc_thres) {
 889                         p_ra->use_ldpc = true;
 890                         p_ra->lower_rts_rate = true;
 891                 } else if (rtlpriv->dm.undec_sm_pwdb >
 892                            (p_ra->ldpc_thres - 5)) {
 893                         p_ra->use_ldpc = false;
 894                         p_ra->lower_rts_rate = false;
 895                 }
 896                 if (_rtl92ee_dm_ra_state_check(hw, rtlpriv->dm.undec_sm_pwdb,
 897                                                &p_ra->ratr_state)) {
 898                         rcu_read_lock();
 899                         sta = rtl_find_sta(hw, mac->bssid);
 900                         if (sta)
 901                                 rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
 902                                                               p_ra->ratr_state,
 903                                                               true);
 904                         rcu_read_unlock();
 905
 906                         p_ra->pre_ratr_state = p_ra->ratr_state;
 907                 }
 908         }
 909 }
 910
 911 static void rtl92ee_dm_init_dynamic_atc_switch(struct ieee80211_hw *hw)
 912 {
 913         struct rtl_priv *rtlpriv = rtl_priv(hw);
 914
 915         rtlpriv->dm.crystal_cap = rtlpriv->efuse.crystalcap;
 916
 917         rtlpriv->dm.atc_status = rtl_get_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11));
 918         rtlpriv->dm.cfo_threshold = CFO_THRESHOLD_XTAL;
 919 }
 920
 921 void rtl92ee_dm_init(struct ieee80211_hw *hw)
 922 {
 923         struct rtl_priv *rtlpriv = rtl_priv(hw);
 924         u32 cur_igvalue = rtl_get_bbreg(hw, DM_REG_IGI_A_11N, DM_BIT_IGI_11N);
 925
 926         rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
 927
 928         rtl_dm_diginit(hw, cur_igvalue);
 929         rtl92ee_dm_init_rate_adaptive_mask(hw);
 930         rtl92ee_dm_init_primary_cca_check(hw);
 931         rtl92ee_dm_init_edca_turbo(hw);
 932         rtl92ee_dm_init_txpower_tracking(hw);
 933         rtl92ee_dm_init_dynamic_atc_switch(hw);
 934 }
 935
 936 static void rtl92ee_dm_common_info_self_update(struct ieee80211_hw *hw)
 937 {
 938         struct rtl_priv *rtlpriv = rtl_priv(hw);
 939         struct rtl_sta_info *drv_priv;
 940         u8 cnt = 0;
 941
 942         rtlpriv->dm.one_entry_only = false;
 943
 944         if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_STATION &&
 945             rtlpriv->mac80211.link_state >= MAC80211_LINKED) {
 946                 rtlpriv->dm.one_entry_only = true;
 947                 return;
 948         }
 949
 950         if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP ||
 951             rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC ||
 952             rtlpriv->mac80211.opmode == NL80211_IFTYPE_MESH_POINT) {
 953                 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
 954                 list_for_each_entry(drv_priv, &rtlpriv->entry_list, list) {
 955                         cnt++;
 956                 }
 957                 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
 958
 959                 if (cnt == 1)
 960                         rtlpriv->dm.one_entry_only = true;
 961         }
 962 }
 963
 964 void rtl92ee_dm_dynamic_arfb_select(struct ieee80211_hw *hw,
 965                                     u8 rate, bool collision_state)
 966 {
 967         struct rtl_priv *rtlpriv = rtl_priv(hw);
 968
 969         if (rate >= DESC92C_RATEMCS8  && rate <= DESC92C_RATEMCS12) {
 970                 if (collision_state == 1) {
 971                         if (rate == DESC92C_RATEMCS12) {
 972                                 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
 973                                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
 974                                                 0x07060501);
 975                         } else if (rate == DESC92C_RATEMCS11) {
 976                                 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
 977                                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
 978                                                 0x07070605);
 979                         } else if (rate == DESC92C_RATEMCS10) {
 980                                 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
 981                                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
 982                                                 0x08080706);
 983                         } else if (rate == DESC92C_RATEMCS9) {
 984                                 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
 985                                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
 986                                                 0x08080707);
 987                         } else {
 988                                 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
 989                                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
 990                                                 0x09090808);
 991                         }
 992                 } else {   /* collision_state == 0 */
 993                         if (rate == DESC92C_RATEMCS12) {
 994                                 rtl_write_dword(rtlpriv, REG_DARFRC,
 995                                                 0x05010000);
 996                                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
 997                                                 0x09080706);
 998                         } else if (rate == DESC92C_RATEMCS11) {
 999                                 rtl_write_dword(rtlpriv, REG_DARFRC,
1000                                                 0x06050000);
1001                                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1002                                                 0x09080807);
1003                         } else if (rate == DESC92C_RATEMCS10) {
1004                                 rtl_write_dword(rtlpriv, REG_DARFRC,
1005                                                 0x07060000);
1006                                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1007                                                 0x0a090908);
1008                         } else if (rate == DESC92C_RATEMCS9) {
1009                                 rtl_write_dword(rtlpriv, REG_DARFRC,
1010                                                 0x07070000);
1011                                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1012                                                 0x0a090808);
1013                         } else {
1014                                 rtl_write_dword(rtlpriv, REG_DARFRC,
1015                                                 0x08080000);
1016                                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1017                                                 0x0b0a0909);
1018                         }
1019                 }
1020         } else {  /* MCS13~MCS15,  1SS, G-mode */
1021                 if (collision_state == 1) {
1022                         if (rate == DESC92C_RATEMCS15) {
1023                                 rtl_write_dword(rtlpriv, REG_DARFRC,
1024                                                 0x00000000);
1025                                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1026                                                 0x05040302);
1027                         } else if (rate == DESC92C_RATEMCS14) {
1028                                 rtl_write_dword(rtlpriv, REG_DARFRC,
1029                                                 0x00000000);
1030                                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1031                                                 0x06050302);
1032                         } else if (rate == DESC92C_RATEMCS13) {
1033                                 rtl_write_dword(rtlpriv, REG_DARFRC,
1034                                                 0x00000000);
1035                                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1036                                                 0x07060502);
1037                         } else {
1038                                 rtl_write_dword(rtlpriv, REG_DARFRC,
1039                                                 0x00000000);
1040                                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1041                                                 0x06050402);
1042                         }
1043                 } else{   /* collision_state == 0 */
1044                         if (rate == DESC92C_RATEMCS15) {
1045                                 rtl_write_dword(rtlpriv, REG_DARFRC,
1046                                                 0x03020000);
1047                                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1048                                                 0x07060504);
1049                         } else if (rate == DESC92C_RATEMCS14) {
1050                                 rtl_write_dword(rtlpriv, REG_DARFRC,
1051                                                 0x03020000);
1052                                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1053                                                 0x08070605);
1054                         } else if (rate == DESC92C_RATEMCS13) {
1055                                 rtl_write_dword(rtlpriv, REG_DARFRC,
1056                                                 0x05020000);
1057                                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1058                                                 0x09080706);
1059                         } else {
1060                                 rtl_write_dword(rtlpriv, REG_DARFRC,
1061                                                 0x04020000);
1062                                 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1063                                                 0x08070605);
1064                         }
1065                 }
1066         }
1067 }
1068
1069 void rtl92ee_dm_watchdog(struct ieee80211_hw *hw)
1070 {
1071         struct rtl_priv *rtlpriv = rtl_priv(hw);
1072         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1073         bool fw_current_inpsmode = false;
1074         bool fw_ps_awake = true;
1075
1076         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
1077                                       (u8 *)(&fw_current_inpsmode));
1078         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
1079                                       (u8 *)(&fw_ps_awake));
1080         if (ppsc->p2p_ps_info.p2p_ps_mode)
1081                 fw_ps_awake = false;
1082
1083         spin_lock(&rtlpriv->locks.rf_ps_lock);
1084         if ((ppsc->rfpwr_state == ERFON) &&
1085             ((!fw_current_inpsmode) && fw_ps_awake) &&
1086             (!ppsc->rfchange_inprogress)) {
1087                 rtl92ee_dm_common_info_self_update(hw);
1088                 rtl92ee_dm_false_alarm_counter_statistics(hw);
1089                 rtl92ee_dm_check_rssi_monitor(hw);
1090                 rtl92ee_dm_dig(hw);
1091                 rtl92ee_dm_adaptivity(hw);
1092                 rtl92ee_dm_cck_packet_detection_thresh(hw);
1093                 rtl92ee_dm_refresh_rate_adaptive_mask(hw);
1094                 rtl92ee_dm_check_edca_turbo(hw);
1095                 rtl92ee_dm_dynamic_atc_switch(hw);
1096                 rtl92ee_dm_dynamic_primary_cca_ckeck(hw);
1097         }
1098         spin_unlock(&rtlpriv->locks.rf_ps_lock);
1099 }