1 /* SPDX-License-Identifier: ISC */
2 /* Copyright (C) 2020 MediaTek Inc. */
7 struct mt7915_mcu_txd {
15 u8 set_query; /* FW don't care */
24 } __packed __aligned(4);
28 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01,
29 MCU_EVENT_FW_START = 0x01,
30 MCU_EVENT_GENERIC = 0x01,
31 MCU_EVENT_ACCESS_REG = 0x02,
32 MCU_EVENT_MT_PATCH_SEM = 0x04,
33 MCU_EVENT_CH_PRIVILEGE = 0x18,
35 MCU_EVENT_RESTART_DL = 0xef,
40 MCU_EXT_EVENT_PS_SYNC = 0x5,
41 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13,
42 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22,
43 MCU_EXT_EVENT_ASSERT_DUMP = 0x23,
44 MCU_EXT_EVENT_RDD_REPORT = 0x3a,
45 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f,
46 MCU_EXT_EVENT_RATE_REPORT = 0x87,
50 MCU_ATE_SET_TRX = 0x1,
51 MCU_ATE_SET_FREQ_OFFSET = 0xa,
52 MCU_ATE_SET_SLOT_TIME = 0x13,
53 MCU_ATE_CLEAN_TXQUEUE = 0x1c,
56 struct mt7915_mcu_rxd {
71 struct mt7915_mcu_thermal_ctrl {
76 u8 protect_type; /* 1: duty admit, 2: radio off */
77 u8 trigger_type; /* 0: low, 1: high */
80 u8 duty_level; /* level 0~3 */
86 struct mt7915_mcu_thermal_notify {
87 struct mt7915_mcu_rxd rxd;
89 struct mt7915_mcu_thermal_ctrl ctrl;
94 struct mt7915_mcu_csa_notify {
95 struct mt7915_mcu_rxd rxd;
103 struct mt7915_mcu_rdd_report {
104 struct mt7915_mcu_rxd rxd;
108 u8 constant_prf_detected;
109 u8 staggered_prf_detected;
111 u8 periodic_pulse_num;
125 __le32 out_pri_const;
126 __le32 out_pri_stg[3];
142 } periodic_pulse[32];
155 struct mt7915_mcu_eeprom {
161 struct mt7915_mcu_eeprom_info {
167 struct mt7915_mcu_ra_info {
168 struct mt7915_mcu_rxd rxd;
177 __le32 min_rate; /* for dynamic sounding */
178 __le32 max_rate; /* for dynamic sounding */
179 __le32 init_rate_down_rate;
182 __le16 init_rate_down_total;
183 __le16 init_rate_down_succ;
198 u8 prob_down_pending;
202 struct mt7915_mcu_phy_rx_info {
213 #define MT_RA_RATE_NSS GENMASK(8, 6)
214 #define MT_RA_RATE_MCS GENMASK(3, 0)
215 #define MT_RA_RATE_TX_MODE GENMASK(12, 9)
216 #define MT_RA_RATE_DCM_EN BIT(4)
217 #define MT_RA_RATE_BW GENMASK(14, 13)
219 struct mt7915_mcu_mib {
225 enum mt7915_chan_mib_offs {
229 MIB_OBSS_AIRTIME = 86
241 struct mt7915_mcu_tx {
247 struct edca edca[IEEE80211_NUM_ACS];
250 #define WMM_AIFS_SET BIT(0)
251 #define WMM_CW_MIN_SET BIT(1)
252 #define WMM_CW_MAX_SET BIT(2)
253 #define WMM_TXOP_SET BIT(3)
254 #define WMM_PARAM_SET GENMASK(3, 0)
256 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10))
257 #define MCU_PKT_ID 0xa0
274 #define __MCU_CMD_FIELD_ID GENMASK(7, 0)
275 #define __MCU_CMD_FIELD_EXT_ID GENMASK(15, 8)
276 #define __MCU_CMD_FIELD_QUERY BIT(16)
277 #define __MCU_CMD_FIELD_WA BIT(17)
280 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01,
281 MCU_CMD_FW_START_REQ = 0x02,
282 MCU_CMD_INIT_ACCESS_REG = 0x3,
283 MCU_CMD_NIC_POWER_CTRL = 0x4,
284 MCU_CMD_PATCH_START_REQ = 0x05,
285 MCU_CMD_PATCH_FINISH_REQ = 0x07,
286 MCU_CMD_PATCH_SEM_CONTROL = 0x10,
287 MCU_CMD_WA_PARAM = 0xC4,
288 MCU_CMD_EXT_CID = 0xED,
289 MCU_CMD_FW_SCATTER = 0xEE,
290 MCU_CMD_RESTART_DL_REQ = 0xEF,
294 MCU_EXT_CMD_EFUSE_ACCESS = 0x01,
295 MCU_EXT_CMD_RF_TEST = 0x04,
296 MCU_EXT_CMD_PM_STATE_CTRL = 0x07,
297 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08,
298 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
299 MCU_EXT_CMD_TXBF_ACTION = 0x1e,
300 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
301 MCU_EXT_CMD_THERMAL_PROT = 0x23,
302 MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
303 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26,
304 MCU_EXT_CMD_EDCA_UPDATE = 0x27,
305 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A,
306 MCU_EXT_CMD_THERMAL_CTRL = 0x2c,
307 MCU_EXT_CMD_WTBL_UPDATE = 0x32,
308 MCU_EXT_CMD_SET_DRR_CTRL = 0x36,
309 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a,
310 MCU_EXT_CMD_ATE_CTRL = 0x3d,
311 MCU_EXT_CMD_PROTECT_CTRL = 0x3e,
312 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46,
313 MCU_EXT_CMD_RX_HDR_TRANS = 0x47,
314 MCU_EXT_CMD_MUAR_UPDATE = 0x48,
315 MCU_EXT_CMD_SET_RX_PATH = 0x4e,
316 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
317 MCU_EXT_CMD_GET_MIB_INFO = 0x5a,
318 MCU_EXT_CMD_MWDS_SUPPORT = 0x80,
319 MCU_EXT_CMD_SET_SER_TRIGGER = 0x81,
320 MCU_EXT_CMD_SCS_CTRL = 0x82,
321 MCU_EXT_CMD_RATE_CTRL = 0x87,
322 MCU_EXT_CMD_FW_DBG_CTRL = 0x95,
323 MCU_EXT_CMD_SET_RDD_TH = 0x9d,
324 MCU_EXT_CMD_SET_SPR = 0xa8,
325 MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab,
326 MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac,
327 MCU_EXT_CMD_PHY_STAT_INFO = 0xad,
331 MCU_WA_PARAM_CMD_QUERY,
332 MCU_WA_PARAM_CMD_SET,
333 MCU_WA_PARAM_CMD_CAPABILITY,
334 MCU_WA_PARAM_CMD_DEBUG,
338 MCU_WA_PARAM_RED = 0x0e,
341 #define MCU_CMD(_t) FIELD_PREP(__MCU_CMD_FIELD_ID, MCU_CMD_##_t)
342 #define MCU_EXT_CMD(_t) (MCU_CMD(EXT_CID) | \
343 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \
345 #define MCU_EXT_QUERY(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY)
347 #define MCU_WA_CMD(_t) (MCU_CMD(_t) | __MCU_CMD_FIELD_WA)
348 #define MCU_WA_EXT_CMD(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_WA)
349 #define MCU_WA_PARAM_CMD(_t) (MCU_WA_CMD(WA_PARAM) | \
350 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \
351 MCU_WA_PARAM_CMD_##_t))
359 PATCH_NOT_DL_SEM_FAIL,
361 PATCH_NOT_DL_SEM_SUCCESS,
362 PATCH_REL_SEM_SUCCESS
367 FW_STATE_FW_DOWNLOAD,
368 FW_STATE_NORMAL_OPERATION,
370 FW_STATE_WACPU_RDY = 7
385 MCU_PHY_STATE_TX_RATE,
386 MCU_PHY_STATE_RX_RATE,
388 MCU_PHY_STATE_CONTENTION_RX_RATE,
389 MCU_PHY_STATE_OFDMLQ_CNINFO,
392 #define STA_TYPE_STA BIT(0)
393 #define STA_TYPE_AP BIT(1)
394 #define STA_TYPE_ADHOC BIT(2)
395 #define STA_TYPE_WDS BIT(4)
396 #define STA_TYPE_BC BIT(5)
398 #define NETWORK_INFRA BIT(16)
399 #define NETWORK_P2P BIT(17)
400 #define NETWORK_IBSS BIT(18)
401 #define NETWORK_WDS BIT(21)
403 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA)
404 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA)
405 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P)
406 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P)
407 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS)
408 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS)
409 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA)
411 #define CONN_STATE_DISCONNECT 0
412 #define CONN_STATE_CONNECT 1
413 #define CONN_STATE_PORT_SECURE 2
422 SCS_SET_MANUAL_PD_TH,
427 SCS_GET_GLO_ADDR_EVENT,
431 CMD_CBW_20MHZ = IEEE80211_STA_RX_BW_20,
432 CMD_CBW_40MHZ = IEEE80211_STA_RX_BW_40,
433 CMD_CBW_80MHZ = IEEE80211_STA_RX_BW_80,
434 CMD_CBW_160MHZ = IEEE80211_STA_RX_BW_160,
450 struct bss_info_omac {
461 struct bss_info_basic {
474 u8 max_bssid; /* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */
475 u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */
476 u8 bmc_wcid_hi; /* high Byte and version */
480 struct bss_info_rf_ch {
487 u8 he_ru26_block; /* 1: don't send HETB in RU26, 0: allow */
488 u8 he_all_disable; /* 1: disallow all HETB, 0: allow */
492 struct bss_info_ext_bss {
495 __le32 mbss_tsf_offset; /* in unit of us */
499 struct bss_info_bmc_rate {
520 u8 has_20_sta; /* Check if any sta support GF. */
521 u8 bss_width_trigger_events;
523 u8 vht_bw_signal; /* not use */
524 u8 vht_force_sgi; /* not use */
529 unsigned short train_up_high_thres;
530 short train_up_rule_rssi;
531 unsigned short low_traffic_thres;
535 __le32 fast_interval;
538 struct bss_info_hw_amsdu {
552 u8 vht_op_info_present;
554 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
558 struct bss_info_bcn {
564 } __packed __aligned(4);
566 struct bss_info_bcn_csa {
571 } __packed __aligned(4);
573 struct bss_info_bcn_bcc {
578 } __packed __aligned(4);
580 struct bss_info_bcn_mbss {
581 #define MAX_BEACON_NUM 32
585 __le16 offset[MAX_BEACON_NUM];
587 } __packed __aligned(4);
589 struct bss_info_bcn_cont {
596 } __packed __aligned(4);
602 BSS_INFO_BCN_CONTENT,
609 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */
610 BSS_INFO_PM, /* sta only */
611 BSS_INFO_UAPSD, /* sta only */
612 BSS_INFO_ROAM_DETECT, /* obsoleted */
613 BSS_INFO_LQ_RM, /* obsoleted */
615 BSS_INFO_BMC_RATE, /* for bmc rate control in CR4 */
616 BSS_INFO_SYNC_MODE, /* obsoleted */
621 BSS_INFO_PROTECT_INFO,
628 WTBL_RESET_AND_SET = 1,
634 struct wtbl_req_hdr {
642 struct wtbl_generic {
645 u8 peer_addr[ETH_ALEN];
687 struct wtbl_hdr_trans {
698 MT_BA_TYPE_ORIGINATOR,
703 RST_BA_MAC_TID_MATCH,
715 /* originator only */
721 u8 peer_addr[ETH_ALEN];
741 WTBL_PEER_PS, /* not used */
746 WTBL_RDG, /* obsoleted */
747 WTBL_PROTECT, /* not used */
748 WTBL_CLEAR, /* not used */
751 WTBL_RAW_DATA, /* debug only */
757 struct sta_ntlv_hdr {
772 struct sta_rec_basic {
779 u8 peer_addr[ETH_ALEN];
794 __le16 vht_rx_mcs_map;
795 __le16 vht_tx_mcs_map;
800 struct sta_rec_uapsd {
807 __le16 listen_interval;
811 struct sta_rec_muru {
825 bool he_20m_in_40m_2g;
829 bool rx_su_comp_sigb;
830 bool rx_su_non_comp_sigb;
845 bool partial_bw_dl_mimo;
851 bool partial_ul_mimo;
875 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
891 struct sta_rec_amsdu {
915 struct sec_key key[2];
953 __le16 supp_vht_mcs[4];
956 u8 op_vht_chan_width;
958 u8 op_vht_rx_nss_type;
965 struct sta_rec_ra_fixed {
971 u8 op_vht_chan_width;
973 u8 op_vht_rx_nss_type;
983 #define RATE_PARAM_FIXED 3
984 #define RATE_PARAM_AUTO 20
985 #define RATE_CFG_MCS GENMASK(3, 0)
986 #define RATE_CFG_NSS GENMASK(7, 4)
987 #define RATE_CFG_GI GENMASK(11, 8)
988 #define RATE_CFG_BW GENMASK(15, 12)
989 #define RATE_CFG_STBC GENMASK(19, 16)
990 #define RATE_CFG_LDPC GENMASK(23, 20)
991 #define RATE_CFG_PHY_TYPE GENMASK(27, 24)
997 __le16 pfmu; /* 0xffff: no access right for PFMU */
998 bool su_mu; /* 0: SU, 1: MU */
999 u8 bf_cap; /* 0: iBF, 1: eBF */
1000 u8 sounding_phy; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT */
1004 u8 tx_mode; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */
1007 u8 bw; /* 0: 20M, 1: 40M, 2: 80M, 3: 160M */
1013 u8 col: 6, row_msb: 2;
1018 u8 auto_sounding; /* b7: low traffic indicator
1019 * b6: Stop sounding for this entry
1020 * b5 ~ b0: postpone sounding
1042 struct sta_rec_bfee {
1045 bool fb_identity_matrix; /* 1: feedback identity matrix */
1046 bool ignore_feedback; /* 1: ignore */
1053 STA_REC_RA_CMM_INFO,
1058 STA_REC_RED, /* not used */
1059 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */
1075 enum mcu_cipher_type {
1076 MCU_CIPHER_NONE = 0,
1081 MCU_CIPHER_AES_CCMP,
1082 MCU_CIPHER_CCMP_256,
1084 MCU_CIPHER_GCMP_256,
1086 MCU_CIPHER_BIP_CMAC_128,
1090 CH_SWITCH_NORMAL = 0,
1094 CH_SWITCH_BACKGROUND_SCAN_START = 6,
1095 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7,
1096 CH_SWITCH_BACKGROUND_SCAN_STOP = 8,
1097 CH_SWITCH_SCAN_BYPASS_DPD = 9
1101 THERMAL_SENSOR_TEMP_QUERY,
1102 THERMAL_SENSOR_MANUAL_CTRL,
1103 THERMAL_SENSOR_INFO_QUERY,
1104 THERMAL_SENSOR_TASK_CTRL,
1108 THERMAL_PROTECT_PARAMETER_CTRL,
1109 THERMAL_PROTECT_BASIC_INFO,
1110 THERMAL_PROTECT_ENABLE,
1111 THERMAL_PROTECT_DISABLE,
1112 THERMAL_PROTECT_DUTY_CONFIG,
1113 THERMAL_PROTECT_MECH_INFO,
1114 THERMAL_PROTECT_DUTY_INFO,
1115 THERMAL_PROTECT_STATE_ACT,
1119 MT_EBF = BIT(0), /* explicit beamforming */
1120 MT_IBF = BIT(1) /* implicit beamforming */
1124 MT_BF_SOUNDING_ON = 1,
1125 MT_BF_TYPE_UPDATE = 20,
1126 MT_BF_MODULE_UPDATE = 25
1129 #define MT7915_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \
1130 sizeof(struct wtbl_generic) + \
1131 sizeof(struct wtbl_rx) + \
1132 sizeof(struct wtbl_ht) + \
1133 sizeof(struct wtbl_vht) + \
1134 sizeof(struct wtbl_hdr_trans) +\
1135 sizeof(struct wtbl_ba) + \
1136 sizeof(struct wtbl_smps))
1138 #define MT7915_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \
1139 sizeof(struct sta_rec_basic) + \
1140 sizeof(struct sta_rec_ht) + \
1141 sizeof(struct sta_rec_he) + \
1142 sizeof(struct sta_rec_ba) + \
1143 sizeof(struct sta_rec_vht) + \
1144 sizeof(struct sta_rec_uapsd) + \
1145 sizeof(struct sta_rec_amsdu) + \
1146 sizeof(struct tlv) + \
1147 MT7915_WTBL_UPDATE_MAX_SIZE)
1149 #define MT7915_BSS_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \
1150 sizeof(struct bss_info_omac) + \
1151 sizeof(struct bss_info_basic) +\
1152 sizeof(struct bss_info_rf_ch) +\
1153 sizeof(struct bss_info_ra) + \
1154 sizeof(struct bss_info_hw_amsdu) +\
1155 sizeof(struct bss_info_he) + \
1156 sizeof(struct bss_info_bmc_rate) +\
1157 sizeof(struct bss_info_ext_bss))
1159 #define MT7915_BEACON_UPDATE_SIZE (sizeof(struct sta_req_hdr) + \
1160 sizeof(struct bss_info_bcn_csa) + \
1161 sizeof(struct bss_info_bcn_bcc) + \
1162 sizeof(struct bss_info_bcn_mbss) + \
1163 sizeof(struct bss_info_bcn_cont))
1165 #define PHY_MODE_A BIT(0)
1166 #define PHY_MODE_B BIT(1)
1167 #define PHY_MODE_G BIT(2)
1168 #define PHY_MODE_GN BIT(3)
1169 #define PHY_MODE_AN BIT(4)
1170 #define PHY_MODE_AC BIT(5)
1171 #define PHY_MODE_AX_24G BIT(6)
1172 #define PHY_MODE_AX_5G BIT(7)
1173 #define PHY_MODE_AX_6G BIT(8)
1175 #define MODE_CCK BIT(0)
1176 #define MODE_OFDM BIT(1)
1177 #define MODE_HT BIT(2)
1178 #define MODE_VHT BIT(3)
1179 #define MODE_HE BIT(4)
1181 #define STA_CAP_WMM BIT(0)
1182 #define STA_CAP_SGI_20 BIT(4)
1183 #define STA_CAP_SGI_40 BIT(5)
1184 #define STA_CAP_TX_STBC BIT(6)
1185 #define STA_CAP_RX_STBC BIT(7)
1186 #define STA_CAP_VHT_SGI_80 BIT(16)
1187 #define STA_CAP_VHT_SGI_160 BIT(17)
1188 #define STA_CAP_VHT_TX_STBC BIT(18)
1189 #define STA_CAP_VHT_RX_STBC BIT(19)
1190 #define STA_CAP_VHT_LDPC BIT(23)
1191 #define STA_CAP_LDPC BIT(24)
1192 #define STA_CAP_HT BIT(26)
1193 #define STA_CAP_VHT BIT(27)
1194 #define STA_CAP_HE BIT(28)
1197 #define STA_REC_HE_CAP_HTC BIT(0)
1198 #define STA_REC_HE_CAP_BQR BIT(1)
1199 #define STA_REC_HE_CAP_BSR BIT(2)
1200 #define STA_REC_HE_CAP_OM BIT(3)
1201 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4)
1203 #define STA_REC_HE_CAP_DUAL_BAND BIT(5)
1204 #define STA_REC_HE_CAP_LDPC BIT(6)
1205 #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7)
1206 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8)
1208 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9)
1209 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10)
1210 #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11)
1211 #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12)
1213 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13)
1214 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14)
1215 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15)
1216 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16)
1217 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17)
1219 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18)
1220 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19)
1221 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20)