1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2019 MediaTek Inc.
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 * Roy Luo <royluo@google.com>
6 * Felix Fietkau <nbd@nbd.name>
7 * Lorenzo Bianconi <lorenzo@kernel.org>
10 #include <linux/etherdevice.h>
11 #include <linux/timekeeping.h>
15 #include "mt7615_trace.h"
18 #define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2)
20 static const struct mt7615_dfs_radar_spec etsi_radar_specs = {
21 .pulse_th = { 40, -10, -80, 800, 3360, 128, 5200 },
23 [5] = { 1, 0, 6, 32, 28, 0, 17, 990, 5010, 1, 1 },
24 [6] = { 1, 0, 9, 32, 28, 0, 27, 615, 5010, 1, 1 },
25 [7] = { 1, 0, 15, 32, 28, 0, 27, 240, 445, 1, 1 },
26 [8] = { 1, 0, 12, 32, 28, 0, 42, 240, 510, 1, 1 },
27 [9] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 12, 32, 28 },
28 [10] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 15, 32, 24 },
29 [11] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 18, 32, 28 },
30 [12] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 27, 32, 24 },
34 static const struct mt7615_dfs_radar_spec fcc_radar_specs = {
35 .pulse_th = { 40, -10, -80, 800, 3360, 128, 5200 },
37 [0] = { 1, 0, 9, 32, 28, 0, 13, 508, 3076, 1, 1 },
38 [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 },
39 [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 },
40 [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 },
41 [4] = { 1, 0, 9, 255, 28, 0, 13, 323, 343, 1, 32 },
45 static const struct mt7615_dfs_radar_spec jp_radar_specs = {
46 .pulse_th = { 40, -10, -80, 800, 3360, 128, 5200 },
48 [0] = { 1, 0, 8, 32, 28, 0, 13, 508, 3076, 1, 1 },
49 [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 },
50 [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 },
51 [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 },
52 [4] = { 1, 0, 9, 32, 28, 0, 13, 323, 343, 1, 32 },
53 [13] = { 1, 0, 8, 32, 28, 0, 14, 3836, 3856, 1, 1 },
54 [14] = { 1, 0, 8, 32, 28, 0, 14, 3990, 4010, 1, 1 },
58 static struct mt76_wcid *mt7615_rx_get_wcid(struct mt7615_dev *dev,
61 struct mt7615_sta *sta;
62 struct mt76_wcid *wcid;
64 if (idx >= MT7615_WTBL_SIZE)
67 wcid = rcu_dereference(dev->mt76.wcid[idx]);
74 sta = container_of(wcid, struct mt7615_sta, wcid);
78 return &sta->vif->sta.wcid;
81 void mt7615_mac_reset_counters(struct mt7615_dev *dev)
85 for (i = 0; i < 4; i++) {
86 mt76_rr(dev, MT_TX_AGG_CNT(0, i));
87 mt76_rr(dev, MT_TX_AGG_CNT(1, i));
90 memset(dev->mt76.aggr_stats, 0, sizeof(dev->mt76.aggr_stats));
91 dev->mt76.phy.survey_time = ktime_get_boottime();
93 dev->mt76.phy2->survey_time = ktime_get_boottime();
95 /* reset airtime counters */
96 mt76_rr(dev, MT_MIB_SDR9(0));
97 mt76_rr(dev, MT_MIB_SDR9(1));
99 mt76_rr(dev, MT_MIB_SDR36(0));
100 mt76_rr(dev, MT_MIB_SDR36(1));
102 mt76_rr(dev, MT_MIB_SDR37(0));
103 mt76_rr(dev, MT_MIB_SDR37(1));
105 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR);
106 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0, MT_WF_RMAC_MIB_RXTIME_CLR);
109 void mt7615_mac_set_timing(struct mt7615_phy *phy)
111 s16 coverage_class = phy->coverage_class;
112 struct mt7615_dev *dev = phy->dev;
113 bool ext_phy = phy != &dev->phy;
115 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) |
116 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
117 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
118 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28);
120 bool is_5ghz = phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ;
122 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
131 coverage_class = max_t(s16, dev->phy.coverage_class,
133 mt76_set(dev, MT_ARB_SCR,
134 MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE);
136 struct mt7615_phy *phy_ext = mt7615_ext_phy(dev);
139 coverage_class = max_t(s16, phy_ext->coverage_class,
141 mt76_set(dev, MT_ARB_SCR,
142 MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE);
146 offset = 3 * coverage_class;
147 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
148 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset);
149 mt76_wr(dev, MT_TMAC_CDTR, cck + reg_offset);
150 mt76_wr(dev, MT_TMAC_ODTR, ofdm + reg_offset);
152 mt76_wr(dev, MT_TMAC_ICR(ext_phy),
153 FIELD_PREP(MT_IFS_EIFS, 360) |
154 FIELD_PREP(MT_IFS_RIFS, 2) |
155 FIELD_PREP(MT_IFS_SIFS, sifs) |
156 FIELD_PREP(MT_IFS_SLOT, phy->slottime));
158 if (phy->slottime < 20 || is_5ghz)
159 val = MT7615_CFEND_RATE_DEFAULT;
161 val = MT7615_CFEND_RATE_11B;
163 mt76_rmw_field(dev, MT_AGG_ACR(ext_phy), MT_AGG_ACR_CFEND_RATE, val);
165 mt76_clear(dev, MT_ARB_SCR,
166 MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE);
168 mt76_clear(dev, MT_ARB_SCR,
169 MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE);
174 mt7615_get_status_freq_info(struct mt7615_dev *dev, struct mt76_phy *mphy,
175 struct mt76_rx_status *status, u8 chfreq)
177 if (!test_bit(MT76_HW_SCANNING, &mphy->state) &&
178 !test_bit(MT76_HW_SCHED_SCANNING, &mphy->state) &&
179 !test_bit(MT76_STATE_ROC, &mphy->state)) {
180 status->freq = mphy->chandef.chan->center_freq;
181 status->band = mphy->chandef.chan->band;
185 status->band = chfreq <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
186 status->freq = ieee80211_channel_to_frequency(chfreq, status->band);
189 static int mt7615_mac_fill_rx(struct mt7615_dev *dev, struct sk_buff *skb)
191 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
192 struct mt76_phy *mphy = &dev->mt76.phy;
193 struct mt7615_phy *phy = &dev->phy;
194 struct mt7615_phy *phy2 = dev->mt76.phy2 ? dev->mt76.phy2->priv : NULL;
195 struct ieee80211_supported_band *sband;
196 struct ieee80211_hdr *hdr;
197 __le32 *rxd = (__le32 *)skb->data;
198 u32 rxd0 = le32_to_cpu(rxd[0]);
199 u32 rxd1 = le32_to_cpu(rxd[1]);
200 u32 rxd2 = le32_to_cpu(rxd[2]);
201 __le32 rxd12 = rxd[12];
202 bool unicast, remove_pad, insert_ccmp_hdr = false;
207 memset(status, 0, sizeof(*status));
209 chfreq = FIELD_GET(MT_RXD1_NORMAL_CH_FREQ, rxd1);
212 else if (phy2->chfreq == phy->chfreq)
214 else if (phy->chfreq == chfreq)
216 else if (phy2->chfreq == chfreq)
221 unicast = (rxd1 & MT_RXD1_NORMAL_ADDR_TYPE) == MT_RXD1_NORMAL_U2M;
222 idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2);
223 status->wcid = mt7615_rx_get_wcid(dev, idx, unicast);
226 struct mt7615_sta *msta;
228 msta = container_of(status->wcid, struct mt7615_sta, wcid);
229 spin_lock_bh(&dev->sta_poll_lock);
230 if (list_empty(&msta->poll_list))
231 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
232 spin_unlock_bh(&dev->sta_poll_lock);
235 if (rxd2 & MT_RXD2_NORMAL_FCS_ERR)
236 status->flag |= RX_FLAG_FAILED_FCS_CRC;
238 if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR)
239 status->flag |= RX_FLAG_MMIC_ERROR;
241 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 &&
242 !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) {
243 status->flag |= RX_FLAG_DECRYPTED;
244 status->flag |= RX_FLAG_IV_STRIPPED;
245 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
248 remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET;
250 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
254 if (rxd0 & MT_RXD0_NORMAL_GROUP_4) {
256 if ((u8 *)rxd - skb->data >= skb->len)
260 if (rxd0 & MT_RXD0_NORMAL_GROUP_1) {
261 u8 *data = (u8 *)rxd;
263 if (status->flag & RX_FLAG_DECRYPTED) {
264 status->iv[0] = data[5];
265 status->iv[1] = data[4];
266 status->iv[2] = data[3];
267 status->iv[3] = data[2];
268 status->iv[4] = data[1];
269 status->iv[5] = data[0];
271 insert_ccmp_hdr = FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
274 if ((u8 *)rxd - skb->data >= skb->len)
278 if (rxd0 & MT_RXD0_NORMAL_GROUP_2) {
280 if ((u8 *)rxd - skb->data >= skb->len)
284 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
285 u32 rxdg5 = le32_to_cpu(rxd[5]);
288 * If both PHYs are on the same channel and we don't have a WCID,
289 * we need to figure out which PHY this packet was received on.
290 * On the primary PHY, the noise value for the chains belonging to the
291 * second PHY will be set to the noise value of the last packet from
295 int first_chain = ffs(phy2->chainmask) - 1;
297 phy_idx = ((rxdg5 >> (first_chain * 8)) & 0xff) == 0;
301 if (phy_idx == 1 && phy2) {
302 mphy = dev->mt76.phy2;
304 status->ext_phy = true;
307 if (!mt7615_firmware_offload(dev) && chfreq != phy->chfreq)
310 mt7615_get_status_freq_info(dev, mphy, status, chfreq);
311 if (status->band == NL80211_BAND_5GHZ)
312 sband = &mphy->sband_5g.sband;
314 sband = &mphy->sband_2g.sband;
316 if (!test_bit(MT76_STATE_RUNNING, &mphy->state))
319 if (!sband->channels)
322 if (!(rxd2 & (MT_RXD2_NORMAL_NON_AMPDU_SUB |
323 MT_RXD2_NORMAL_NON_AMPDU))) {
324 status->flag |= RX_FLAG_AMPDU_DETAILS;
326 /* all subframes of an A-MPDU have the same timestamp */
327 if (phy->rx_ampdu_ts != rxd12) {
328 if (!++phy->ampdu_ref)
331 phy->rx_ampdu_ts = rxd12;
333 status->ampdu_ref = phy->ampdu_ref;
336 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
337 u32 rxdg0 = le32_to_cpu(rxd[0]);
338 u32 rxdg1 = le32_to_cpu(rxd[1]);
339 u32 rxdg3 = le32_to_cpu(rxd[3]);
340 u8 stbc = FIELD_GET(MT_RXV1_HT_STBC, rxdg0);
343 i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0);
344 switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) {
345 case MT_PHY_TYPE_CCK:
348 case MT_PHY_TYPE_OFDM:
349 i = mt76_get_rate(&dev->mt76, sband, i, cck);
351 case MT_PHY_TYPE_HT_GF:
353 status->encoding = RX_ENC_HT;
357 case MT_PHY_TYPE_VHT:
358 status->nss = FIELD_GET(MT_RXV2_NSTS, rxdg1) + 1;
359 status->encoding = RX_ENC_VHT;
364 status->rate_idx = i;
366 switch (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0)) {
370 status->bw = RATE_INFO_BW_40;
373 status->bw = RATE_INFO_BW_80;
376 status->bw = RATE_INFO_BW_160;
382 if (rxdg0 & MT_RXV1_HT_SHORT_GI)
383 status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
384 if (rxdg0 & MT_RXV1_HT_AD_CODE)
385 status->enc_flags |= RX_ENC_FLAG_LDPC;
387 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
389 status->chains = mphy->antenna_mask;
390 status->chain_signal[0] = to_rssi(MT_RXV4_RCPI0, rxdg3);
391 status->chain_signal[1] = to_rssi(MT_RXV4_RCPI1, rxdg3);
392 status->chain_signal[2] = to_rssi(MT_RXV4_RCPI2, rxdg3);
393 status->chain_signal[3] = to_rssi(MT_RXV4_RCPI3, rxdg3);
394 status->signal = status->chain_signal[0];
396 for (i = 1; i < hweight8(mphy->antenna_mask); i++) {
397 if (!(status->chains & BIT(i)))
400 status->signal = max(status->signal,
401 status->chain_signal[i]);
405 if ((u8 *)rxd - skb->data >= skb->len)
409 skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad);
411 if (insert_ccmp_hdr) {
412 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
414 mt76_insert_ccmp_hdr(skb, key_id);
417 hdr = (struct ieee80211_hdr *)skb->data;
418 if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control))
421 status->aggr = unicast &&
422 !ieee80211_is_qos_nullfunc(hdr->frame_control);
423 status->tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK;
424 status->seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
429 void mt7615_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps)
432 EXPORT_SYMBOL_GPL(mt7615_sta_ps);
435 mt7615_mac_tx_rate_val(struct mt7615_dev *dev,
436 struct mt76_phy *mphy,
437 const struct ieee80211_tx_rate *rate,
440 u8 phy, nss, rate_idx;
445 if (rate->flags & IEEE80211_TX_RC_VHT_MCS) {
446 rate_idx = ieee80211_rate_get_vht_mcs(rate);
447 nss = ieee80211_rate_get_vht_nss(rate);
448 phy = MT_PHY_TYPE_VHT;
449 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
451 else if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH)
453 else if (rate->flags & IEEE80211_TX_RC_160_MHZ_WIDTH)
455 } else if (rate->flags & IEEE80211_TX_RC_MCS) {
456 rate_idx = rate->idx;
457 nss = 1 + (rate->idx >> 3);
458 phy = MT_PHY_TYPE_HT;
459 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD)
460 phy = MT_PHY_TYPE_HT_GF;
461 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
464 const struct ieee80211_rate *r;
465 int band = mphy->chandef.chan->band;
469 r = &mphy->hw->wiphy->bands[band]->bitrates[rate->idx];
470 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
471 val = r->hw_value_short;
476 rate_idx = val & 0xff;
479 if (stbc && nss == 1) {
481 rateval |= MT_TX_RATE_STBC;
484 rateval |= (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) |
485 FIELD_PREP(MT_TX_RATE_MODE, phy) |
486 FIELD_PREP(MT_TX_RATE_NSS, nss - 1));
491 int mt7615_mac_write_txwi(struct mt7615_dev *dev, __le32 *txwi,
492 struct sk_buff *skb, struct mt76_wcid *wcid,
493 struct ieee80211_sta *sta, int pid,
494 struct ieee80211_key_conf *key, bool beacon)
496 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
497 struct ieee80211_tx_rate *rate = &info->control.rates[0];
498 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
499 bool multicast = is_multicast_ether_addr(hdr->addr1);
500 struct ieee80211_vif *vif = info->control.vif;
501 struct mt76_phy *mphy = &dev->mphy;
502 bool ext_phy = info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY;
503 bool is_usb = mt76_is_usb(&dev->mt76);
505 u8 fc_type, fc_stype, p_fmt, q_idx, omac_idx = 0, wmm_idx = 0;
506 __le16 fc = hdr->frame_control;
507 u32 val, sz_txd = is_usb ? MT_USB_TXD_SIZE : MT_TXD_SIZE;
511 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
513 omac_idx = mvif->omac_idx;
514 wmm_idx = mvif->wmm_idx;
518 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv;
520 tx_count = msta->rate_count;
523 if (ext_phy && dev->mt76.phy2)
524 mphy = dev->mt76.phy2;
526 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2;
527 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4;
529 if (ieee80211_is_data(fc) || ieee80211_is_bufferable_mmpdu(fc)) {
530 q_idx = wmm_idx * MT7615_MAX_WMM_SETS +
531 skb_get_queue_mapping(skb);
532 p_fmt = is_usb ? MT_TX_TYPE_SF : MT_TX_TYPE_CT;
535 q_idx = MT_LMAC_BCN1;
537 q_idx = MT_LMAC_BCN0;
538 p_fmt = MT_TX_TYPE_FW;
541 q_idx = MT_LMAC_ALTX1;
543 q_idx = MT_LMAC_ALTX0;
544 p_fmt = is_usb ? MT_TX_TYPE_SF : MT_TX_TYPE_CT;
547 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + sz_txd) |
548 FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_LMAC) |
549 FIELD_PREP(MT_TXD0_Q_IDX, q_idx);
550 txwi[0] = cpu_to_le32(val);
552 val = MT_TXD1_LONG_FORMAT |
553 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) |
554 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
555 FIELD_PREP(MT_TXD1_HDR_INFO,
556 ieee80211_get_hdrlen_from_skb(skb) / 2) |
557 FIELD_PREP(MT_TXD1_TID,
558 skb->priority & IEEE80211_QOS_CTL_TID_MASK) |
559 FIELD_PREP(MT_TXD1_PKT_FMT, p_fmt) |
560 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx);
561 txwi[1] = cpu_to_le32(val);
563 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) |
564 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) |
565 FIELD_PREP(MT_TXD2_MULTICAST, multicast);
567 if (multicast && ieee80211_is_robust_mgmt_frame(skb) &&
568 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) {
572 txwi[3] = cpu_to_le32(MT_TXD3_PROTECT_FRAME);
577 txwi[2] = cpu_to_le32(val);
579 if (!(info->flags & IEEE80211_TX_CTL_AMPDU))
580 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
585 if (rate->idx >= 0 && rate->count &&
586 !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) {
587 bool stbc = info->flags & IEEE80211_TX_CTL_STBC;
589 u16 rateval = mt7615_mac_tx_rate_val(dev, mphy, rate, stbc,
592 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE);
594 val = MT_TXD6_FIXED_BW |
595 FIELD_PREP(MT_TXD6_BW, bw) |
596 FIELD_PREP(MT_TXD6_TX_RATE, rateval);
597 txwi[6] |= cpu_to_le32(val);
599 if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
600 txwi[6] |= cpu_to_le32(MT_TXD6_SGI);
602 if (info->flags & IEEE80211_TX_CTL_LDPC)
603 txwi[6] |= cpu_to_le32(MT_TXD6_LDPC);
605 if (!(rate->flags & (IEEE80211_TX_RC_MCS |
606 IEEE80211_TX_RC_VHT_MCS)))
607 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
609 tx_count = rate->count;
612 if (!ieee80211_is_beacon(fc)) {
613 struct ieee80211_hw *hw = mt76_hw(dev);
615 val = MT_TXD5_TX_STATUS_HOST | FIELD_PREP(MT_TXD5_PID, pid);
616 if (!ieee80211_hw_check(hw, SUPPORTS_PS))
617 val |= MT_TXD5_SW_POWER_MGMT;
618 txwi[5] = cpu_to_le32(val);
621 /* use maximum tx count for beacons */
625 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count);
626 if (ieee80211_is_data_qos(hdr->frame_control)) {
627 seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
628 val |= MT_TXD3_SN_VALID;
629 } else if (ieee80211_is_back_req(hdr->frame_control)) {
630 struct ieee80211_bar *bar = (struct ieee80211_bar *)skb->data;
632 seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(bar->start_seq_num));
633 val |= MT_TXD3_SN_VALID;
635 val |= FIELD_PREP(MT_TXD3_SEQ, seqno);
637 txwi[3] |= cpu_to_le32(val);
639 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
640 txwi[3] |= cpu_to_le32(MT_TXD3_NO_ACK);
642 txwi[7] = FIELD_PREP(MT_TXD7_TYPE, fc_type) |
643 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype) |
644 FIELD_PREP(MT_TXD7_SPE_IDX, 0x18);
646 txwi[8] = FIELD_PREP(MT_TXD8_L_TYPE, fc_type) |
647 FIELD_PREP(MT_TXD8_L_SUB_TYPE, fc_stype);
651 EXPORT_SYMBOL_GPL(mt7615_mac_write_txwi);
654 mt7615_txp_skb_unmap_fw(struct mt76_dev *dev, struct mt7615_fw_txp *txp)
658 for (i = 1; i < txp->nbuf; i++)
659 dma_unmap_single(dev->dev, le32_to_cpu(txp->buf[i]),
660 le16_to_cpu(txp->len[i]), DMA_TO_DEVICE);
664 mt7615_txp_skb_unmap_hw(struct mt76_dev *dev, struct mt7615_hw_txp *txp)
669 last_mask = is_mt7663(dev) ? MT_TXD_LEN_LAST : MT_TXD_LEN_MSDU_LAST;
671 for (i = 0; i < ARRAY_SIZE(txp->ptr); i++) {
672 struct mt7615_txp_ptr *ptr = &txp->ptr[i];
676 len = le16_to_cpu(ptr->len0);
677 last = len & last_mask;
678 len &= MT_TXD_LEN_MASK;
679 dma_unmap_single(dev->dev, le32_to_cpu(ptr->buf0), len,
684 len = le16_to_cpu(ptr->len1);
685 last = len & last_mask;
686 len &= MT_TXD_LEN_MASK;
687 dma_unmap_single(dev->dev, le32_to_cpu(ptr->buf1), len,
694 void mt7615_txp_skb_unmap(struct mt76_dev *dev,
695 struct mt76_txwi_cache *t)
697 struct mt7615_txp_common *txp;
699 txp = mt7615_txwi_to_txp(dev, t);
701 mt7615_txp_skb_unmap_fw(dev, &txp->fw);
703 mt7615_txp_skb_unmap_hw(dev, &txp->hw);
705 EXPORT_SYMBOL_GPL(mt7615_txp_skb_unmap);
707 bool mt7615_mac_wtbl_update(struct mt7615_dev *dev, int idx, u32 mask)
709 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
710 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
712 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY,
716 void mt7615_mac_sta_poll(struct mt7615_dev *dev)
718 static const u8 ac_to_tid[4] = {
719 [IEEE80211_AC_BE] = 0,
720 [IEEE80211_AC_BK] = 1,
721 [IEEE80211_AC_VI] = 4,
722 [IEEE80211_AC_VO] = 6
724 static const u8 hw_queue_map[] = {
725 [IEEE80211_AC_BK] = 0,
726 [IEEE80211_AC_BE] = 1,
727 [IEEE80211_AC_VI] = 2,
728 [IEEE80211_AC_VO] = 3,
730 struct ieee80211_sta *sta;
731 struct mt7615_sta *msta;
732 u32 addr, tx_time[4], rx_time[4];
733 struct list_head sta_poll_list;
736 INIT_LIST_HEAD(&sta_poll_list);
737 spin_lock_bh(&dev->sta_poll_lock);
738 list_splice_init(&dev->sta_poll_list, &sta_poll_list);
739 spin_unlock_bh(&dev->sta_poll_lock);
741 while (!list_empty(&sta_poll_list)) {
744 msta = list_first_entry(&sta_poll_list, struct mt7615_sta,
746 list_del_init(&msta->poll_list);
748 addr = mt7615_mac_wtbl_addr(dev, msta->wcid.idx) + 19 * 4;
750 for (i = 0; i < 4; i++, addr += 8) {
751 u32 tx_last = msta->airtime_ac[i];
752 u32 rx_last = msta->airtime_ac[i + 4];
754 msta->airtime_ac[i] = mt76_rr(dev, addr);
755 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4);
756 tx_time[i] = msta->airtime_ac[i] - tx_last;
757 rx_time[i] = msta->airtime_ac[i + 4] - rx_last;
759 if ((tx_last | rx_last) & BIT(30))
764 mt7615_mac_wtbl_update(dev, msta->wcid.idx,
765 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
766 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac));
772 sta = container_of((void *)msta, struct ieee80211_sta,
774 for (i = 0; i < 4; i++) {
775 u32 tx_cur = tx_time[i];
776 u32 rx_cur = rx_time[hw_queue_map[i]];
777 u8 tid = ac_to_tid[i];
779 if (!tx_cur && !rx_cur)
782 ieee80211_sta_register_airtime(sta, tid, tx_cur,
787 EXPORT_SYMBOL_GPL(mt7615_mac_sta_poll);
790 mt7615_mac_update_rate_desc(struct mt7615_phy *phy, struct mt7615_sta *sta,
791 struct ieee80211_tx_rate *probe_rate,
792 struct ieee80211_tx_rate *rates,
793 struct mt7615_rate_desc *rd)
795 struct mt7615_dev *dev = phy->dev;
796 struct mt76_phy *mphy = phy->mt76;
797 struct ieee80211_tx_rate *ref;
798 bool rateset, stbc = false;
799 int n_rates = sta->n_rates;
803 for (i = n_rates; i < 4; i++)
804 rates[i] = rates[n_rates - 1];
806 rateset = !(sta->rate_set_tsf & BIT(0));
807 memcpy(sta->rateset[rateset].rates, rates,
808 sizeof(sta->rateset[rateset].rates));
810 sta->rateset[rateset].probe_rate = *probe_rate;
811 ref = &sta->rateset[rateset].probe_rate;
813 sta->rateset[rateset].probe_rate.idx = -1;
814 ref = &sta->rateset[rateset].rates[0];
817 rates = sta->rateset[rateset].rates;
818 for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) {
820 * We don't support switching between short and long GI
821 * within the rate set. For accurate tx status reporting, we
822 * need to make sure that flags match.
823 * For improved performance, avoid duplicate entries by
824 * decrementing the MCS index if necessary
826 if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI)
827 rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI;
829 for (j = 0; j < i; j++) {
830 if (rates[i].idx != rates[j].idx)
832 if ((rates[i].flags ^ rates[j].flags) &
833 (IEEE80211_TX_RC_40_MHZ_WIDTH |
834 IEEE80211_TX_RC_80_MHZ_WIDTH |
835 IEEE80211_TX_RC_160_MHZ_WIDTH))
845 rd->val[0] = mt7615_mac_tx_rate_val(dev, mphy, &rates[0], stbc, &bw);
849 rd->probe_val = mt7615_mac_tx_rate_val(dev, mphy, probe_rate,
856 rd->probe_val = rd->val[0];
859 rd->val[1] = mt7615_mac_tx_rate_val(dev, mphy, &rates[1], stbc, &bw);
865 rd->val[2] = mt7615_mac_tx_rate_val(dev, mphy, &rates[2], stbc, &bw);
871 rd->val[3] = mt7615_mac_tx_rate_val(dev, mphy, &rates[3], stbc, &bw);
875 rd->rateset = rateset;
880 mt7615_mac_queue_rate_update(struct mt7615_phy *phy, struct mt7615_sta *sta,
881 struct ieee80211_tx_rate *probe_rate,
882 struct ieee80211_tx_rate *rates)
884 struct mt7615_dev *dev = phy->dev;
885 struct mt7615_wtbl_desc *wd;
887 wd = kzalloc(sizeof(*wd), GFP_ATOMIC);
891 wd->type = MT7615_WTBL_RATE_DESC;
894 mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates,
896 list_add_tail(&wd->node, &dev->wd_head);
897 queue_work(dev->mt76.usb.wq, &dev->wtbl_work);
902 void mt7615_mac_set_rates(struct mt7615_phy *phy, struct mt7615_sta *sta,
903 struct ieee80211_tx_rate *probe_rate,
904 struct ieee80211_tx_rate *rates)
906 int wcid = sta->wcid.idx, n_rates = sta->n_rates;
907 struct mt7615_dev *dev = phy->dev;
908 struct mt7615_rate_desc rd;
911 if (mt76_is_usb(&dev->mt76)) {
912 mt7615_mac_queue_rate_update(phy, sta, probe_rate, rates);
916 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
919 memset(&rd, 0, sizeof(struct mt7615_rate_desc));
920 mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates, &rd);
922 addr = mt7615_mac_wtbl_addr(dev, wcid);
923 w27 = mt76_rr(dev, addr + 27 * 4);
924 w27 &= ~MT_WTBL_W27_CC_BW_SEL;
925 w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, rd.bw);
927 w5 = mt76_rr(dev, addr + 5 * 4);
928 w5 &= ~(MT_WTBL_W5_BW_CAP | MT_WTBL_W5_CHANGE_BW_RATE |
929 MT_WTBL_W5_MPDU_OK_COUNT |
930 MT_WTBL_W5_MPDU_FAIL_COUNT |
931 MT_WTBL_W5_RATE_IDX);
932 w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, rd.bw) |
933 FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE,
934 rd.bw_idx ? rd.bw_idx - 1 : 7);
936 mt76_wr(dev, MT_WTBL_RIUCR0, w5);
938 mt76_wr(dev, MT_WTBL_RIUCR1,
939 FIELD_PREP(MT_WTBL_RIUCR1_RATE0, rd.probe_val) |
940 FIELD_PREP(MT_WTBL_RIUCR1_RATE1, rd.val[0]) |
941 FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, rd.val[1]));
943 mt76_wr(dev, MT_WTBL_RIUCR2,
944 FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, rd.val[1] >> 8) |
945 FIELD_PREP(MT_WTBL_RIUCR2_RATE3, rd.val[1]) |
946 FIELD_PREP(MT_WTBL_RIUCR2_RATE4, rd.val[2]) |
947 FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, rd.val[2]));
949 mt76_wr(dev, MT_WTBL_RIUCR3,
950 FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, rd.val[2] >> 4) |
951 FIELD_PREP(MT_WTBL_RIUCR3_RATE6, rd.val[3]) |
952 FIELD_PREP(MT_WTBL_RIUCR3_RATE7, rd.val[3]));
954 mt76_wr(dev, MT_WTBL_UPDATE,
955 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) |
956 MT_WTBL_UPDATE_RATE_UPDATE |
957 MT_WTBL_UPDATE_TX_COUNT_CLEAR);
959 mt76_wr(dev, addr + 27 * 4, w27);
961 mt76_set(dev, MT_LPON_T0CR, MT_LPON_T0CR_MODE); /* TSF read */
962 sta->rate_set_tsf = mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0);
963 sta->rate_set_tsf |= rd.rateset;
965 if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET))
966 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
968 sta->rate_count = 2 * MT7615_RATE_RETRY * n_rates;
969 sta->wcid.tx_info |= MT_WCID_TX_INFO_SET;
971 EXPORT_SYMBOL_GPL(mt7615_mac_set_rates);
973 int mt7615_mac_wtbl_update_key(struct mt7615_dev *dev,
974 struct mt76_wcid *wcid,
976 enum mt7615_cipher_type cipher,
977 enum set_key_cmd cmd)
979 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx) + 30 * 4;
982 if (keylen > sizeof(data))
985 mt76_rr_copy(dev, addr, data, sizeof(data));
986 if (cmd == SET_KEY) {
987 if (cipher == MT_CIPHER_TKIP) {
988 /* Rx/Tx MIC keys are swapped */
989 memcpy(data + 16, key + 24, 8);
990 memcpy(data + 24, key + 16, 8);
992 if (cipher != MT_CIPHER_BIP_CMAC_128 && wcid->cipher)
993 memmove(data + 16, data, 16);
994 if (cipher != MT_CIPHER_BIP_CMAC_128 || !wcid->cipher)
995 memcpy(data, key, keylen);
996 else if (cipher == MT_CIPHER_BIP_CMAC_128)
997 memcpy(data + 16, key, 16);
999 if (wcid->cipher & ~BIT(cipher)) {
1000 if (cipher != MT_CIPHER_BIP_CMAC_128)
1001 memmove(data, data + 16, 16);
1002 memset(data + 16, 0, 16);
1004 memset(data, 0, sizeof(data));
1007 mt76_wr_copy(dev, addr, data, sizeof(data));
1011 EXPORT_SYMBOL_GPL(mt7615_mac_wtbl_update_key);
1013 int mt7615_mac_wtbl_update_pk(struct mt7615_dev *dev,
1014 struct mt76_wcid *wcid,
1015 enum mt7615_cipher_type cipher,
1016 int keyidx, enum set_key_cmd cmd)
1018 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx), w0, w1;
1020 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
1023 w0 = mt76_rr(dev, addr);
1024 w1 = mt76_rr(dev, addr + 4);
1025 if (cmd == SET_KEY) {
1026 w0 |= MT_WTBL_W0_RX_KEY_VALID |
1027 FIELD_PREP(MT_WTBL_W0_RX_IK_VALID,
1028 cipher == MT_CIPHER_BIP_CMAC_128);
1029 if (cipher != MT_CIPHER_BIP_CMAC_128 ||
1031 w0 |= FIELD_PREP(MT_WTBL_W0_KEY_IDX, keyidx);
1033 if (!(wcid->cipher & ~BIT(cipher)))
1034 w0 &= ~(MT_WTBL_W0_RX_KEY_VALID |
1035 MT_WTBL_W0_KEY_IDX);
1036 if (cipher == MT_CIPHER_BIP_CMAC_128)
1037 w0 &= ~MT_WTBL_W0_RX_IK_VALID;
1039 mt76_wr(dev, MT_WTBL_RICR0, w0);
1040 mt76_wr(dev, MT_WTBL_RICR1, w1);
1042 if (!mt7615_mac_wtbl_update(dev, wcid->idx,
1043 MT_WTBL_UPDATE_RXINFO_UPDATE))
1048 EXPORT_SYMBOL_GPL(mt7615_mac_wtbl_update_pk);
1050 void mt7615_mac_wtbl_update_cipher(struct mt7615_dev *dev,
1051 struct mt76_wcid *wcid,
1052 enum mt7615_cipher_type cipher,
1053 enum set_key_cmd cmd)
1055 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx);
1057 if (cmd == SET_KEY) {
1058 if (cipher != MT_CIPHER_BIP_CMAC_128 || !wcid->cipher)
1059 mt76_rmw(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE,
1060 FIELD_PREP(MT_WTBL_W2_KEY_TYPE, cipher));
1062 if (cipher != MT_CIPHER_BIP_CMAC_128 &&
1063 wcid->cipher & BIT(MT_CIPHER_BIP_CMAC_128))
1064 mt76_rmw(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE,
1065 FIELD_PREP(MT_WTBL_W2_KEY_TYPE,
1066 MT_CIPHER_BIP_CMAC_128));
1067 else if (!(wcid->cipher & ~BIT(cipher)))
1068 mt76_clear(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE);
1071 EXPORT_SYMBOL_GPL(mt7615_mac_wtbl_update_cipher);
1073 int mt7615_mac_wtbl_set_key(struct mt7615_dev *dev,
1074 struct mt76_wcid *wcid,
1075 struct ieee80211_key_conf *key,
1076 enum set_key_cmd cmd)
1078 enum mt7615_cipher_type cipher;
1081 cipher = mt7615_mac_get_cipher(key->cipher);
1082 if (cipher == MT_CIPHER_NONE)
1085 spin_lock_bh(&dev->mt76.lock);
1087 mt7615_mac_wtbl_update_cipher(dev, wcid, cipher, cmd);
1088 err = mt7615_mac_wtbl_update_key(dev, wcid, key->key, key->keylen,
1093 err = mt7615_mac_wtbl_update_pk(dev, wcid, cipher, key->keyidx,
1099 wcid->cipher |= BIT(cipher);
1101 wcid->cipher &= ~BIT(cipher);
1104 spin_unlock_bh(&dev->mt76.lock);
1109 static bool mt7615_fill_txs(struct mt7615_dev *dev, struct mt7615_sta *sta,
1110 struct ieee80211_tx_info *info, __le32 *txs_data)
1112 struct ieee80211_supported_band *sband;
1113 struct mt7615_rate_set *rs;
1114 struct mt76_phy *mphy;
1115 int first_idx = 0, last_idx;
1117 bool fixed_rate, ack_timeout;
1118 bool probe, ampdu, cck = false;
1121 u32 final_rate, final_rate_flags, final_nss, txs;
1123 fixed_rate = info->status.rates[0].count;
1124 probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1126 txs = le32_to_cpu(txs_data[1]);
1127 ampdu = !fixed_rate && (txs & MT_TXS1_AMPDU);
1129 txs = le32_to_cpu(txs_data[3]);
1130 count = FIELD_GET(MT_TXS3_TX_COUNT, txs);
1131 last_idx = FIELD_GET(MT_TXS3_LAST_TX_RATE, txs);
1133 txs = le32_to_cpu(txs_data[0]);
1134 final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs);
1135 ack_timeout = txs & MT_TXS0_ACK_TIMEOUT;
1137 if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT))
1140 if (txs & MT_TXS0_QUEUE_TIMEOUT)
1144 info->flags |= IEEE80211_TX_STAT_ACK;
1146 info->status.ampdu_len = 1;
1147 info->status.ampdu_ack_len = !!(info->flags &
1148 IEEE80211_TX_STAT_ACK);
1150 if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU))
1151 info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU;
1153 first_idx = max_t(int, 0, last_idx - (count - 1) / MT7615_RATE_RETRY);
1155 if (fixed_rate && !probe) {
1156 info->status.rates[0].count = count;
1161 rate_set_tsf = READ_ONCE(sta->rate_set_tsf);
1162 rs_idx = !((u32)(FIELD_GET(MT_TXS4_F0_TIMESTAMP, le32_to_cpu(txs_data[4])) -
1163 rate_set_tsf) < 1000000);
1164 rs_idx ^= rate_set_tsf & BIT(0);
1165 rs = &sta->rateset[rs_idx];
1167 if (!first_idx && rs->probe_rate.idx >= 0) {
1168 info->status.rates[0] = rs->probe_rate;
1170 spin_lock_bh(&dev->mt76.lock);
1171 if (sta->rate_probe) {
1172 struct mt7615_phy *phy = &dev->phy;
1174 if (sta->wcid.ext_phy && dev->mt76.phy2)
1175 phy = dev->mt76.phy2->priv;
1177 mt7615_mac_set_rates(phy, sta, NULL, sta->rates);
1178 sta->rate_probe = false;
1180 spin_unlock_bh(&dev->mt76.lock);
1182 info->status.rates[0] = rs->rates[first_idx / 2];
1184 info->status.rates[0].count = 0;
1186 for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) {
1187 struct ieee80211_tx_rate *cur_rate;
1190 cur_rate = &rs->rates[idx / 2];
1191 cur_count = min_t(int, MT7615_RATE_RETRY, count);
1194 if (idx && (cur_rate->idx != info->status.rates[i].idx ||
1195 cur_rate->flags != info->status.rates[i].flags)) {
1197 if (i == ARRAY_SIZE(info->status.rates)) {
1202 info->status.rates[i] = *cur_rate;
1203 info->status.rates[i].count = 0;
1206 info->status.rates[i].count += cur_count;
1210 final_rate_flags = info->status.rates[i].flags;
1212 switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) {
1213 case MT_PHY_TYPE_CCK:
1216 case MT_PHY_TYPE_OFDM:
1218 if (sta->wcid.ext_phy && dev->mt76.phy2)
1219 mphy = dev->mt76.phy2;
1221 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ)
1222 sband = &mphy->sband_5g.sband;
1224 sband = &mphy->sband_2g.sband;
1225 final_rate &= MT_TX_RATE_IDX;
1226 final_rate = mt76_get_rate(&dev->mt76, sband, final_rate,
1228 final_rate_flags = 0;
1230 case MT_PHY_TYPE_HT_GF:
1231 case MT_PHY_TYPE_HT:
1232 final_rate_flags |= IEEE80211_TX_RC_MCS;
1233 final_rate &= MT_TX_RATE_IDX;
1234 if (final_rate > 31)
1237 case MT_PHY_TYPE_VHT:
1238 final_nss = FIELD_GET(MT_TX_RATE_NSS, final_rate);
1240 if ((final_rate & MT_TX_RATE_STBC) && final_nss)
1243 final_rate_flags |= IEEE80211_TX_RC_VHT_MCS;
1244 final_rate = (final_rate & MT_TX_RATE_IDX) | (final_nss << 4);
1250 info->status.rates[i].idx = final_rate;
1251 info->status.rates[i].flags = final_rate_flags;
1256 static bool mt7615_mac_add_txs_skb(struct mt7615_dev *dev,
1257 struct mt7615_sta *sta, int pid,
1260 struct mt76_dev *mdev = &dev->mt76;
1261 struct sk_buff_head list;
1262 struct sk_buff *skb;
1264 if (pid < MT_PACKET_ID_FIRST)
1267 trace_mac_txdone(mdev, sta->wcid.idx, pid);
1269 mt76_tx_status_lock(mdev, &list);
1270 skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list);
1272 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1274 if (!mt7615_fill_txs(dev, sta, info, txs_data)) {
1275 ieee80211_tx_info_clear_status(info);
1276 info->status.rates[0].idx = -1;
1279 mt76_tx_status_skb_done(mdev, skb, &list);
1281 mt76_tx_status_unlock(mdev, &list);
1286 static void mt7615_mac_add_txs(struct mt7615_dev *dev, void *data)
1288 struct ieee80211_tx_info info = {};
1289 struct ieee80211_sta *sta = NULL;
1290 struct mt7615_sta *msta = NULL;
1291 struct mt76_wcid *wcid;
1292 struct mt76_phy *mphy = &dev->mt76.phy;
1293 __le32 *txs_data = data;
1298 txs = le32_to_cpu(txs_data[0]);
1299 pid = FIELD_GET(MT_TXS0_PID, txs);
1300 txs = le32_to_cpu(txs_data[2]);
1301 wcidx = FIELD_GET(MT_TXS2_WCID, txs);
1303 if (pid == MT_PACKET_ID_NO_ACK)
1306 if (wcidx >= MT7615_WTBL_SIZE)
1311 wcid = rcu_dereference(dev->mt76.wcid[wcidx]);
1315 msta = container_of(wcid, struct mt7615_sta, wcid);
1316 sta = wcid_to_sta(wcid);
1318 spin_lock_bh(&dev->sta_poll_lock);
1319 if (list_empty(&msta->poll_list))
1320 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
1321 spin_unlock_bh(&dev->sta_poll_lock);
1323 if (mt7615_mac_add_txs_skb(dev, msta, pid, txs_data))
1326 if (wcidx >= MT7615_WTBL_STA || !sta)
1329 if (wcid->ext_phy && dev->mt76.phy2)
1330 mphy = dev->mt76.phy2;
1332 if (mt7615_fill_txs(dev, msta, &info, txs_data))
1333 ieee80211_tx_status_noskb(mphy->hw, sta, &info);
1340 mt7615_mac_tx_free_token(struct mt7615_dev *dev, u16 token)
1342 struct mt76_dev *mdev = &dev->mt76;
1343 struct mt76_txwi_cache *txwi;
1345 trace_mac_tx_free(dev, token);
1347 spin_lock_bh(&dev->token_lock);
1348 txwi = idr_remove(&dev->token, token);
1349 spin_unlock_bh(&dev->token_lock);
1354 mt7615_txp_skb_unmap(mdev, txwi);
1356 mt76_tx_complete_skb(mdev, txwi->skb);
1360 mt76_put_txwi(mdev, txwi);
1363 static void mt7615_mac_tx_free(struct mt7615_dev *dev, struct sk_buff *skb)
1365 struct mt7615_tx_free *free = (struct mt7615_tx_free *)skb->data;
1368 count = FIELD_GET(MT_TX_FREE_MSDU_ID_CNT, le16_to_cpu(free->ctrl));
1369 if (is_mt7615(&dev->mt76)) {
1370 __le16 *token = &free->token[0];
1372 for (i = 0; i < count; i++)
1373 mt7615_mac_tx_free_token(dev, le16_to_cpu(token[i]));
1375 __le32 *token = (__le32 *)&free->token[0];
1377 for (i = 0; i < count; i++)
1378 mt7615_mac_tx_free_token(dev, le32_to_cpu(token[i]));
1384 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1385 struct sk_buff *skb)
1387 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
1388 __le32 *rxd = (__le32 *)skb->data;
1389 __le32 *end = (__le32 *)&skb->data[skb->len];
1390 enum rx_pkt_type type;
1393 type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0]));
1394 flag = FIELD_GET(MT_RXD0_PKT_FLAG, le32_to_cpu(rxd[0]));
1395 if (type == PKT_TYPE_RX_EVENT && flag == 0x1)
1396 type = PKT_TYPE_NORMAL_MCU;
1400 for (rxd++; rxd + 7 <= end; rxd += 7)
1401 mt7615_mac_add_txs(dev, rxd);
1404 case PKT_TYPE_TXRX_NOTIFY:
1405 mt7615_mac_tx_free(dev, skb);
1407 case PKT_TYPE_RX_EVENT:
1408 mt7615_mcu_rx_event(dev, skb);
1410 case PKT_TYPE_NORMAL_MCU:
1411 case PKT_TYPE_NORMAL:
1412 if (!mt7615_mac_fill_rx(dev, skb)) {
1413 mt76_rx(&dev->mt76, q, skb);
1422 EXPORT_SYMBOL_GPL(mt7615_queue_rx_skb);
1425 mt7615_mac_set_sensitivity(struct mt7615_phy *phy, int val, bool ofdm)
1427 struct mt7615_dev *dev = phy->dev;
1428 bool ext_phy = phy != &dev->phy;
1430 if (is_mt7663(&dev->mt76)) {
1432 mt76_rmw(dev, MT7663_WF_PHY_MIN_PRI_PWR(ext_phy),
1433 MT_WF_PHY_PD_OFDM_MASK(0),
1434 MT_WF_PHY_PD_OFDM(0, val));
1436 mt76_rmw(dev, MT7663_WF_PHY_RXTD_CCK_PD(ext_phy),
1437 MT_WF_PHY_PD_CCK_MASK(ext_phy),
1438 MT_WF_PHY_PD_CCK(ext_phy, val));
1443 mt76_rmw(dev, MT_WF_PHY_MIN_PRI_PWR(ext_phy),
1444 MT_WF_PHY_PD_OFDM_MASK(ext_phy),
1445 MT_WF_PHY_PD_OFDM(ext_phy, val));
1447 mt76_rmw(dev, MT_WF_PHY_RXTD_CCK_PD(ext_phy),
1448 MT_WF_PHY_PD_CCK_MASK(ext_phy),
1449 MT_WF_PHY_PD_CCK(ext_phy, val));
1453 mt7615_mac_set_default_sensitivity(struct mt7615_phy *phy)
1456 mt7615_mac_set_sensitivity(phy, 0x13c, true);
1458 mt7615_mac_set_sensitivity(phy, 0x92, false);
1460 phy->ofdm_sensitivity = -98;
1461 phy->cck_sensitivity = -110;
1462 phy->last_cca_adj = jiffies;
1465 void mt7615_mac_set_scs(struct mt7615_phy *phy, bool enable)
1467 struct mt7615_dev *dev = phy->dev;
1468 bool ext_phy = phy != &dev->phy;
1471 mutex_lock(&dev->mt76.mutex);
1473 if (phy->scs_en == enable)
1476 if (is_mt7663(&dev->mt76)) {
1477 reg = MT7663_WF_PHY_MIN_PRI_PWR(ext_phy);
1478 mask = MT_WF_PHY_PD_BLK(0);
1480 reg = MT_WF_PHY_MIN_PRI_PWR(ext_phy);
1481 mask = MT_WF_PHY_PD_BLK(ext_phy);
1485 mt76_set(dev, reg, mask);
1486 if (is_mt7622(&dev->mt76)) {
1487 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7 << 8);
1488 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7);
1491 mt76_clear(dev, reg, mask);
1494 mt7615_mac_set_default_sensitivity(phy);
1495 phy->scs_en = enable;
1498 mutex_unlock(&dev->mt76.mutex);
1501 void mt7615_mac_enable_nf(struct mt7615_dev *dev, bool ext_phy)
1505 if (is_mt7663(&dev->mt76))
1506 reg = MT7663_WF_PHY_R0_PHYMUX_5;
1508 reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy);
1511 rxtd = MT_WF_PHY_RXTD2(10);
1513 rxtd = MT_WF_PHY_RXTD(12);
1515 mt76_set(dev, rxtd, BIT(18) | BIT(29));
1516 mt76_set(dev, reg, 0x5 << 12);
1519 void mt7615_mac_cca_stats_reset(struct mt7615_phy *phy)
1521 struct mt7615_dev *dev = phy->dev;
1522 bool ext_phy = phy != &dev->phy;
1525 if (is_mt7663(&dev->mt76))
1526 reg = MT7663_WF_PHY_R0_PHYMUX_5;
1528 reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy);
1530 /* reset PD and MDRDY counters */
1531 mt76_clear(dev, reg, GENMASK(22, 20));
1532 mt76_set(dev, reg, BIT(22) | BIT(20));
1536 mt7615_mac_adjust_sensitivity(struct mt7615_phy *phy,
1537 u32 rts_err_rate, bool ofdm)
1539 struct mt7615_dev *dev = phy->dev;
1540 int false_cca = ofdm ? phy->false_cca_ofdm : phy->false_cca_cck;
1541 bool ext_phy = phy != &dev->phy;
1542 u16 def_th = ofdm ? -98 : -110;
1543 bool update = false;
1547 sensitivity = ofdm ? &phy->ofdm_sensitivity : &phy->cck_sensitivity;
1548 signal = mt76_get_min_avg_rssi(&dev->mt76, ext_phy);
1550 mt7615_mac_set_default_sensitivity(phy);
1554 signal = min(signal, -72);
1555 if (false_cca > 500) {
1556 if (rts_err_rate > MT_FRAC(40, 100))
1559 /* decrease coverage */
1560 if (*sensitivity == def_th && signal > -90) {
1563 } else if (*sensitivity + 2 < signal) {
1567 } else if ((false_cca > 0 && false_cca < 50) ||
1568 rts_err_rate > MT_FRAC(60, 100)) {
1569 /* increase coverage */
1570 if (*sensitivity - 2 >= def_th) {
1576 if (*sensitivity > signal) {
1577 *sensitivity = signal;
1582 u16 val = ofdm ? *sensitivity * 2 + 512 : *sensitivity + 256;
1584 mt7615_mac_set_sensitivity(phy, val, ofdm);
1585 phy->last_cca_adj = jiffies;
1590 mt7615_mac_scs_check(struct mt7615_phy *phy)
1592 struct mt7615_dev *dev = phy->dev;
1593 struct mib_stats *mib = &phy->mib;
1594 u32 val, rts_err_rate = 0;
1595 u32 mdrdy_cck, mdrdy_ofdm, pd_cck, pd_ofdm;
1596 bool ext_phy = phy != &dev->phy;
1601 if (is_mt7663(&dev->mt76))
1602 val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS0(ext_phy));
1604 val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS0(ext_phy));
1605 pd_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_CCK, val);
1606 pd_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_OFDM, val);
1608 if (is_mt7663(&dev->mt76))
1609 val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS5(ext_phy));
1611 val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS5(ext_phy));
1612 mdrdy_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_CCK, val);
1613 mdrdy_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_OFDM, val);
1615 phy->false_cca_ofdm = pd_ofdm - mdrdy_ofdm;
1616 phy->false_cca_cck = pd_cck - mdrdy_cck;
1617 mt7615_mac_cca_stats_reset(phy);
1619 if (mib->rts_cnt + mib->rts_retries_cnt)
1620 rts_err_rate = MT_FRAC(mib->rts_retries_cnt,
1621 mib->rts_cnt + mib->rts_retries_cnt);
1624 mt7615_mac_adjust_sensitivity(phy, rts_err_rate, false);
1626 mt7615_mac_adjust_sensitivity(phy, rts_err_rate, true);
1628 if (time_after(jiffies, phy->last_cca_adj + 10 * HZ))
1629 mt7615_mac_set_default_sensitivity(phy);
1633 mt7615_phy_get_nf(struct mt7615_dev *dev, int idx)
1635 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 };
1636 u32 reg, val, sum = 0, n = 0;
1639 if (is_mt7663(&dev->mt76))
1640 reg = MT7663_WF_PHY_RXTD(20);
1642 reg = idx ? MT_WF_PHY_RXTD2(17) : MT_WF_PHY_RXTD(20);
1644 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) {
1645 val = mt76_rr(dev, reg);
1646 sum += val * nf_power[i];
1657 mt7615_phy_update_channel(struct mt76_phy *mphy, int idx)
1659 struct mt7615_dev *dev = container_of(mphy->dev, struct mt7615_dev, mt76);
1660 struct mt7615_phy *phy = mphy->priv;
1661 struct mt76_channel_state *state;
1662 u64 busy_time, tx_time, rx_time, obss_time;
1663 u32 obss_reg = idx ? MT_WF_RMAC_MIB_TIME6 : MT_WF_RMAC_MIB_TIME5;
1666 busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx),
1667 MT_MIB_SDR9_BUSY_MASK);
1668 tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx),
1669 MT_MIB_SDR36_TXTIME_MASK);
1670 rx_time = mt76_get_field(dev, MT_MIB_SDR37(idx),
1671 MT_MIB_SDR37_RXTIME_MASK);
1672 obss_time = mt76_get_field(dev, obss_reg, MT_MIB_OBSSTIME_MASK);
1674 nf = mt7615_phy_get_nf(dev, idx);
1676 phy->noise = nf << 4;
1678 phy->noise += nf - (phy->noise >> 4);
1680 state = mphy->chan_state;
1681 state->cc_busy += busy_time;
1682 state->cc_tx += tx_time;
1683 state->cc_rx += rx_time + obss_time;
1684 state->cc_bss_rx += rx_time;
1685 state->noise = -(phy->noise >> 4);
1688 void mt7615_update_channel(struct mt76_dev *mdev)
1690 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
1692 mt7615_phy_update_channel(&mdev->phy, 0);
1694 mt7615_phy_update_channel(mdev->phy2, 1);
1696 /* reset obss airtime */
1697 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR);
1699 EXPORT_SYMBOL_GPL(mt7615_update_channel);
1702 mt7615_mac_update_mib_stats(struct mt7615_phy *phy)
1704 struct mt7615_dev *dev = phy->dev;
1705 struct mib_stats *mib = &phy->mib;
1706 bool ext_phy = phy != &dev->phy;
1710 memset(mib, 0, sizeof(*mib));
1712 mib->fcs_err_cnt = mt76_get_field(dev, MT_MIB_SDR3(ext_phy),
1713 MT_MIB_SDR3_FCS_ERR_MASK);
1715 val = mt76_get_field(dev, MT_MIB_SDR14(ext_phy),
1716 MT_MIB_AMPDU_MPDU_COUNT);
1718 val2 = mt76_get_field(dev, MT_MIB_SDR15(ext_phy),
1719 MT_MIB_AMPDU_ACK_COUNT);
1720 mib->aggr_per = 1000 * (val - val2) / val;
1723 aggr = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0;
1724 for (i = 0; i < 4; i++) {
1725 val = mt76_rr(dev, MT_MIB_MB_SDR1(ext_phy, i));
1727 val2 = FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, val);
1728 if (val2 > mib->ack_fail_cnt)
1729 mib->ack_fail_cnt = val2;
1731 val2 = FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val);
1732 if (val2 > mib->ba_miss_cnt)
1733 mib->ba_miss_cnt = val2;
1735 val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i));
1736 val2 = FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val);
1737 if (val2 > mib->rts_retries_cnt) {
1738 mib->rts_cnt = FIELD_GET(MT_MIB_RTS_COUNT_MASK, val);
1739 mib->rts_retries_cnt = val2;
1742 val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i));
1744 dev->mt76.aggr_stats[aggr++] += val & 0xffff;
1745 dev->mt76.aggr_stats[aggr++] += val >> 16;
1749 void mt7615_mac_work(struct work_struct *work)
1751 struct mt7615_phy *phy;
1752 struct mt76_dev *mdev;
1754 phy = (struct mt7615_phy *)container_of(work, struct mt7615_phy,
1756 mdev = &phy->dev->mt76;
1758 mutex_lock(&mdev->mutex);
1760 mt76_update_survey(mdev);
1761 if (++phy->mac_work_count == 5) {
1762 phy->mac_work_count = 0;
1764 mt7615_mac_update_mib_stats(phy);
1765 mt7615_mac_scs_check(phy);
1768 mutex_unlock(&mdev->mutex);
1770 mt76_tx_status_check(mdev, NULL, false);
1771 ieee80211_queue_delayed_work(phy->mt76->hw, &phy->mac_work,
1772 MT7615_WATCHDOG_TIME);
1776 mt7615_wait_reset_state(struct mt7615_dev *dev, u32 state)
1780 ret = wait_event_timeout(dev->reset_wait,
1781 (READ_ONCE(dev->reset_state) & state),
1782 MT7615_RESET_TIMEOUT);
1783 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state);
1788 mt7615_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif)
1790 struct ieee80211_hw *hw = priv;
1791 struct mt7615_dev *dev = mt7615_hw_dev(hw);
1793 mt7615_mcu_add_beacon(dev, hw, vif, vif->bss_conf.enable_beacon);
1797 mt7615_update_beacons(struct mt7615_dev *dev)
1799 ieee80211_iterate_active_interfaces(dev->mt76.hw,
1800 IEEE80211_IFACE_ITER_RESUME_ALL,
1801 mt7615_update_vif_beacon, dev->mt76.hw);
1803 if (!dev->mt76.phy2)
1806 ieee80211_iterate_active_interfaces(dev->mt76.phy2->hw,
1807 IEEE80211_IFACE_ITER_RESUME_ALL,
1808 mt7615_update_vif_beacon, dev->mt76.phy2->hw);
1811 void mt7615_dma_reset(struct mt7615_dev *dev)
1815 mt76_clear(dev, MT_WPDMA_GLO_CFG,
1816 MT_WPDMA_GLO_CFG_RX_DMA_EN | MT_WPDMA_GLO_CFG_TX_DMA_EN |
1817 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
1818 usleep_range(1000, 2000);
1820 for (i = 0; i < __MT_TXQ_MAX; i++)
1821 mt76_queue_tx_cleanup(dev, i, true);
1823 mt76_for_each_q_rx(&dev->mt76, i) {
1824 mt76_queue_rx_reset(dev, i);
1827 mt76_set(dev, MT_WPDMA_GLO_CFG,
1828 MT_WPDMA_GLO_CFG_RX_DMA_EN | MT_WPDMA_GLO_CFG_TX_DMA_EN |
1829 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
1831 EXPORT_SYMBOL_GPL(mt7615_dma_reset);
1833 void mt7615_mac_reset_work(struct work_struct *work)
1835 struct mt7615_phy *phy2;
1836 struct mt76_phy *ext_phy;
1837 struct mt7615_dev *dev;
1839 dev = container_of(work, struct mt7615_dev, reset_work);
1840 ext_phy = dev->mt76.phy2;
1841 phy2 = ext_phy ? ext_phy->priv : NULL;
1843 if (!(READ_ONCE(dev->reset_state) & MT_MCU_CMD_STOP_PDMA))
1846 ieee80211_stop_queues(mt76_hw(dev));
1848 ieee80211_stop_queues(ext_phy->hw);
1850 set_bit(MT76_RESET, &dev->mphy.state);
1851 set_bit(MT76_MCU_RESET, &dev->mphy.state);
1852 wake_up(&dev->mt76.mcu.wait);
1853 cancel_delayed_work_sync(&dev->phy.mac_work);
1854 del_timer_sync(&dev->phy.roc_timer);
1855 cancel_work_sync(&dev->phy.roc_work);
1857 cancel_delayed_work_sync(&phy2->mac_work);
1858 del_timer_sync(&phy2->roc_timer);
1859 cancel_work_sync(&phy2->roc_work);
1862 /* lock/unlock all queues to ensure that no tx is pending */
1863 mt76_txq_schedule_all(&dev->mphy);
1865 mt76_txq_schedule_all(ext_phy);
1867 tasklet_disable(&dev->mt76.tx_tasklet);
1868 napi_disable(&dev->mt76.napi[0]);
1869 napi_disable(&dev->mt76.napi[1]);
1870 napi_disable(&dev->mt76.tx_napi);
1872 mutex_lock(&dev->mt76.mutex);
1874 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_PDMA_STOPPED);
1876 if (mt7615_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) {
1877 mt7615_dma_reset(dev);
1879 mt76_wr(dev, MT_WPDMA_MEM_RNG_ERR, 0);
1881 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_PDMA_INIT);
1882 mt7615_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE);
1885 clear_bit(MT76_MCU_RESET, &dev->mphy.state);
1886 clear_bit(MT76_RESET, &dev->mphy.state);
1888 tasklet_enable(&dev->mt76.tx_tasklet);
1889 napi_enable(&dev->mt76.tx_napi);
1890 napi_schedule(&dev->mt76.tx_napi);
1892 napi_enable(&dev->mt76.napi[0]);
1893 napi_schedule(&dev->mt76.napi[0]);
1895 napi_enable(&dev->mt76.napi[1]);
1896 napi_schedule(&dev->mt76.napi[1]);
1898 ieee80211_wake_queues(mt76_hw(dev));
1900 ieee80211_wake_queues(ext_phy->hw);
1902 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE);
1903 mt7615_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE);
1905 mutex_unlock(&dev->mt76.mutex);
1907 mt7615_update_beacons(dev);
1909 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->phy.mac_work,
1910 MT7615_WATCHDOG_TIME);
1912 ieee80211_queue_delayed_work(ext_phy->hw, &phy2->mac_work,
1913 MT7615_WATCHDOG_TIME);
1917 static void mt7615_dfs_stop_radar_detector(struct mt7615_phy *phy)
1919 struct mt7615_dev *dev = phy->dev;
1921 if (phy->rdd_state & BIT(0))
1922 mt7615_mcu_rdd_cmd(dev, RDD_STOP, 0, MT_RX_SEL0, 0);
1923 if (phy->rdd_state & BIT(1))
1924 mt7615_mcu_rdd_cmd(dev, RDD_STOP, 1, MT_RX_SEL0, 0);
1927 static int mt7615_dfs_start_rdd(struct mt7615_dev *dev, int chain)
1931 err = mt7615_mcu_rdd_cmd(dev, RDD_START, chain, MT_RX_SEL0, 0);
1935 return mt7615_mcu_rdd_cmd(dev, RDD_DET_MODE, chain,
1939 static int mt7615_dfs_start_radar_detector(struct mt7615_phy *phy)
1941 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
1942 struct mt7615_dev *dev = phy->dev;
1943 bool ext_phy = phy != &dev->phy;
1947 err = mt7615_mcu_rdd_cmd(dev, RDD_CAC_START, ext_phy, MT_RX_SEL0, 0);
1951 err = mt7615_dfs_start_rdd(dev, ext_phy);
1955 phy->rdd_state |= BIT(ext_phy);
1957 if (chandef->width == NL80211_CHAN_WIDTH_160 ||
1958 chandef->width == NL80211_CHAN_WIDTH_80P80) {
1959 err = mt7615_dfs_start_rdd(dev, 1);
1963 phy->rdd_state |= BIT(1);
1970 mt7615_dfs_init_radar_specs(struct mt7615_phy *phy)
1972 const struct mt7615_dfs_radar_spec *radar_specs;
1973 struct mt7615_dev *dev = phy->dev;
1976 switch (dev->mt76.region) {
1977 case NL80211_DFS_FCC:
1978 radar_specs = &fcc_radar_specs;
1979 err = mt7615_mcu_set_fcc5_lpn(dev, 8);
1983 case NL80211_DFS_ETSI:
1984 radar_specs = &etsi_radar_specs;
1986 case NL80211_DFS_JP:
1987 radar_specs = &jp_radar_specs;
1993 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) {
1994 err = mt7615_mcu_set_radar_th(dev, i,
1995 &radar_specs->radar_pattern[i]);
2000 return mt7615_mcu_set_pulse_th(dev, &radar_specs->pulse_th);
2003 int mt7615_dfs_init_radar_detector(struct mt7615_phy *phy)
2005 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
2006 struct mt7615_dev *dev = phy->dev;
2007 bool ext_phy = phy != &dev->phy;
2010 if (is_mt7663(&dev->mt76))
2013 if (dev->mt76.region == NL80211_DFS_UNSET) {
2014 phy->dfs_state = -1;
2021 if (test_bit(MT76_SCANNING, &phy->mt76->state))
2024 if (phy->dfs_state == chandef->chan->dfs_state)
2027 err = mt7615_dfs_init_radar_specs(phy);
2029 phy->dfs_state = -1;
2033 phy->dfs_state = chandef->chan->dfs_state;
2035 if (chandef->chan->flags & IEEE80211_CHAN_RADAR) {
2036 if (chandef->chan->dfs_state != NL80211_DFS_AVAILABLE)
2037 return mt7615_dfs_start_radar_detector(phy);
2039 return mt7615_mcu_rdd_cmd(dev, RDD_CAC_END, ext_phy,
2044 err = mt7615_mcu_rdd_cmd(dev, RDD_NORMAL_START, ext_phy, MT_RX_SEL0, 0);
2048 mt7615_dfs_stop_radar_detector(phy);