1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2019 MediaTek Inc.
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 * Roy Luo <royluo@google.com>
6 * Felix Fietkau <nbd@nbd.name>
7 * Lorenzo Bianconi <lorenzo@kernel.org>
10 #include <linux/devcoredump.h>
11 #include <linux/etherdevice.h>
12 #include <linux/timekeeping.h>
16 #include "mt7615_trace.h"
20 #define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2)
22 static const struct mt7615_dfs_radar_spec etsi_radar_specs = {
23 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
25 [5] = { 1, 0, 6, 32, 28, 0, 17, 990, 5010, 1, 1 },
26 [6] = { 1, 0, 9, 32, 28, 0, 27, 615, 5010, 1, 1 },
27 [7] = { 1, 0, 15, 32, 28, 0, 27, 240, 445, 1, 1 },
28 [8] = { 1, 0, 12, 32, 28, 0, 42, 240, 510, 1, 1 },
29 [9] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 12, 32, 28 },
30 [10] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 15, 32, 24 },
31 [11] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 18, 32, 28 },
32 [12] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 27, 32, 24 },
36 static const struct mt7615_dfs_radar_spec fcc_radar_specs = {
37 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
39 [0] = { 1, 0, 9, 32, 28, 0, 13, 508, 3076, 1, 1 },
40 [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 },
41 [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 },
42 [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 },
43 [4] = { 1, 0, 9, 255, 28, 0, 13, 323, 343, 1, 32 },
47 static const struct mt7615_dfs_radar_spec jp_radar_specs = {
48 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
50 [0] = { 1, 0, 8, 32, 28, 0, 13, 508, 3076, 1, 1 },
51 [1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 },
52 [2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 },
53 [3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 },
54 [4] = { 1, 0, 9, 32, 28, 0, 13, 323, 343, 1, 32 },
55 [13] = { 1, 0, 8, 32, 28, 0, 14, 3836, 3856, 1, 1 },
56 [14] = { 1, 0, 8, 32, 28, 0, 14, 3990, 4010, 1, 1 },
60 static enum mt76_cipher_type
61 mt7615_mac_get_cipher(int cipher)
64 case WLAN_CIPHER_SUITE_WEP40:
65 return MT_CIPHER_WEP40;
66 case WLAN_CIPHER_SUITE_WEP104:
67 return MT_CIPHER_WEP104;
68 case WLAN_CIPHER_SUITE_TKIP:
69 return MT_CIPHER_TKIP;
70 case WLAN_CIPHER_SUITE_AES_CMAC:
71 return MT_CIPHER_BIP_CMAC_128;
72 case WLAN_CIPHER_SUITE_CCMP:
73 return MT_CIPHER_AES_CCMP;
74 case WLAN_CIPHER_SUITE_CCMP_256:
75 return MT_CIPHER_CCMP_256;
76 case WLAN_CIPHER_SUITE_GCMP:
77 return MT_CIPHER_GCMP;
78 case WLAN_CIPHER_SUITE_GCMP_256:
79 return MT_CIPHER_GCMP_256;
80 case WLAN_CIPHER_SUITE_SMS4:
81 return MT_CIPHER_WAPI;
83 return MT_CIPHER_NONE;
87 static struct mt76_wcid *mt7615_rx_get_wcid(struct mt7615_dev *dev,
90 struct mt7615_sta *sta;
91 struct mt76_wcid *wcid;
93 if (idx >= MT7615_WTBL_SIZE)
96 wcid = rcu_dereference(dev->mt76.wcid[idx]);
103 sta = container_of(wcid, struct mt7615_sta, wcid);
107 return &sta->vif->sta.wcid;
110 void mt7615_mac_reset_counters(struct mt7615_dev *dev)
114 for (i = 0; i < 4; i++) {
115 mt76_rr(dev, MT_TX_AGG_CNT(0, i));
116 mt76_rr(dev, MT_TX_AGG_CNT(1, i));
119 memset(dev->mt76.aggr_stats, 0, sizeof(dev->mt76.aggr_stats));
120 dev->mt76.phy.survey_time = ktime_get_boottime();
122 dev->mt76.phy2->survey_time = ktime_get_boottime();
124 /* reset airtime counters */
125 mt76_rr(dev, MT_MIB_SDR9(0));
126 mt76_rr(dev, MT_MIB_SDR9(1));
128 mt76_rr(dev, MT_MIB_SDR36(0));
129 mt76_rr(dev, MT_MIB_SDR36(1));
131 mt76_rr(dev, MT_MIB_SDR37(0));
132 mt76_rr(dev, MT_MIB_SDR37(1));
134 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR);
135 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0, MT_WF_RMAC_MIB_RXTIME_CLR);
138 void mt7615_mac_set_timing(struct mt7615_phy *phy)
140 s16 coverage_class = phy->coverage_class;
141 struct mt7615_dev *dev = phy->dev;
142 bool ext_phy = phy != &dev->phy;
144 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) |
145 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
146 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
147 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28);
149 bool is_5ghz = phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ;
151 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
160 coverage_class = max_t(s16, dev->phy.coverage_class,
162 mt76_set(dev, MT_ARB_SCR,
163 MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE);
165 struct mt7615_phy *phy_ext = mt7615_ext_phy(dev);
168 coverage_class = max_t(s16, phy_ext->coverage_class,
170 mt76_set(dev, MT_ARB_SCR,
171 MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE);
175 offset = 3 * coverage_class;
176 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
177 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset);
178 mt76_wr(dev, MT_TMAC_CDTR, cck + reg_offset);
179 mt76_wr(dev, MT_TMAC_ODTR, ofdm + reg_offset);
181 mt76_wr(dev, MT_TMAC_ICR(ext_phy),
182 FIELD_PREP(MT_IFS_EIFS, 360) |
183 FIELD_PREP(MT_IFS_RIFS, 2) |
184 FIELD_PREP(MT_IFS_SIFS, sifs) |
185 FIELD_PREP(MT_IFS_SLOT, phy->slottime));
187 if (phy->slottime < 20 || is_5ghz)
188 val = MT7615_CFEND_RATE_DEFAULT;
190 val = MT7615_CFEND_RATE_11B;
192 mt76_rmw_field(dev, MT_AGG_ACR(ext_phy), MT_AGG_ACR_CFEND_RATE, val);
194 mt76_clear(dev, MT_ARB_SCR,
195 MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE);
197 mt76_clear(dev, MT_ARB_SCR,
198 MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE);
203 mt7615_get_status_freq_info(struct mt7615_dev *dev, struct mt76_phy *mphy,
204 struct mt76_rx_status *status, u8 chfreq)
206 if (!test_bit(MT76_HW_SCANNING, &mphy->state) &&
207 !test_bit(MT76_HW_SCHED_SCANNING, &mphy->state) &&
208 !test_bit(MT76_STATE_ROC, &mphy->state)) {
209 status->freq = mphy->chandef.chan->center_freq;
210 status->band = mphy->chandef.chan->band;
214 status->band = chfreq <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
215 status->freq = ieee80211_channel_to_frequency(chfreq, status->band);
218 static void mt7615_mac_fill_tm_rx(struct mt7615_phy *phy, __le32 *rxv)
220 #ifdef CONFIG_NL80211_TESTMODE
221 u32 rxv1 = le32_to_cpu(rxv[0]);
222 u32 rxv3 = le32_to_cpu(rxv[2]);
223 u32 rxv4 = le32_to_cpu(rxv[3]);
224 u32 rxv5 = le32_to_cpu(rxv[4]);
225 u8 cbw = FIELD_GET(MT_RXV1_FRAME_MODE, rxv1);
226 u8 mode = FIELD_GET(MT_RXV1_TX_MODE, rxv1);
227 s16 foe = FIELD_GET(MT_RXV5_FOE, rxv5);
228 u32 foe_const = (BIT(cbw + 1) & 0xf) * 10000;
239 foe = (foe * foe_const) >> 15;
242 phy->test.last_freq_offset = foe;
243 phy->test.last_rcpi[0] = FIELD_GET(MT_RXV4_RCPI0, rxv4);
244 phy->test.last_rcpi[1] = FIELD_GET(MT_RXV4_RCPI1, rxv4);
245 phy->test.last_rcpi[2] = FIELD_GET(MT_RXV4_RCPI2, rxv4);
246 phy->test.last_rcpi[3] = FIELD_GET(MT_RXV4_RCPI3, rxv4);
247 phy->test.last_ib_rssi[0] = FIELD_GET(MT_RXV3_IB_RSSI, rxv3);
248 phy->test.last_wb_rssi[0] = FIELD_GET(MT_RXV3_WB_RSSI, rxv3);
252 /* The HW does not translate the mac header to 802.3 for mesh point */
253 static int mt7615_reverse_frag0_hdr_trans(struct sk_buff *skb, u16 hdr_gap)
255 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
256 struct ethhdr *eth_hdr = (struct ethhdr *)(skb->data + hdr_gap);
257 struct mt7615_sta *msta = (struct mt7615_sta *)status->wcid;
258 __le32 *rxd = (__le32 *)skb->data;
259 struct ieee80211_sta *sta;
260 struct ieee80211_vif *vif;
261 struct ieee80211_hdr hdr;
264 if (le32_get_bits(rxd[1], MT_RXD1_NORMAL_ADDR_TYPE) !=
268 if (!(le32_to_cpu(rxd[0]) & MT_RXD0_NORMAL_GROUP_4))
271 if (!msta || !msta->vif)
274 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv);
275 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv);
277 /* store the info from RXD and ethhdr to avoid being overridden */
278 frame_control = le32_get_bits(rxd[4], MT_RXD4_FRAME_CONTROL);
279 hdr.frame_control = cpu_to_le16(frame_control);
280 hdr.seq_ctrl = cpu_to_le16(le32_get_bits(rxd[6], MT_RXD6_SEQ_CTRL));
283 ether_addr_copy(hdr.addr1, vif->addr);
284 ether_addr_copy(hdr.addr2, sta->addr);
285 switch (frame_control & (IEEE80211_FCTL_TODS |
286 IEEE80211_FCTL_FROMDS)) {
288 ether_addr_copy(hdr.addr3, vif->bss_conf.bssid);
290 case IEEE80211_FCTL_FROMDS:
291 ether_addr_copy(hdr.addr3, eth_hdr->h_source);
293 case IEEE80211_FCTL_TODS:
294 ether_addr_copy(hdr.addr3, eth_hdr->h_dest);
296 case IEEE80211_FCTL_TODS | IEEE80211_FCTL_FROMDS:
297 ether_addr_copy(hdr.addr3, eth_hdr->h_dest);
298 ether_addr_copy(hdr.addr4, eth_hdr->h_source);
304 skb_pull(skb, hdr_gap + sizeof(struct ethhdr) - 2);
305 if (eth_hdr->h_proto == cpu_to_be16(ETH_P_AARP) ||
306 eth_hdr->h_proto == cpu_to_be16(ETH_P_IPX))
307 ether_addr_copy(skb_push(skb, ETH_ALEN), bridge_tunnel_header);
308 else if (be16_to_cpu(eth_hdr->h_proto) >= ETH_P_802_3_MIN)
309 ether_addr_copy(skb_push(skb, ETH_ALEN), rfc1042_header);
313 if (ieee80211_has_order(hdr.frame_control))
314 memcpy(skb_push(skb, IEEE80211_HT_CTL_LEN), &rxd[7],
315 IEEE80211_HT_CTL_LEN);
317 if (ieee80211_is_data_qos(hdr.frame_control)) {
320 qos_ctrl = cpu_to_le16(le32_get_bits(rxd[6], MT_RXD6_QOS_CTL));
321 memcpy(skb_push(skb, IEEE80211_QOS_CTL_LEN), &qos_ctrl,
322 IEEE80211_QOS_CTL_LEN);
325 if (ieee80211_has_a4(hdr.frame_control))
326 memcpy(skb_push(skb, sizeof(hdr)), &hdr, sizeof(hdr));
328 memcpy(skb_push(skb, sizeof(hdr) - 6), &hdr, sizeof(hdr) - 6);
330 status->flag &= ~(RX_FLAG_RADIOTAP_HE | RX_FLAG_RADIOTAP_HE_MU);
334 static int mt7615_mac_fill_rx(struct mt7615_dev *dev, struct sk_buff *skb)
336 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
337 struct mt76_phy *mphy = &dev->mt76.phy;
338 struct mt7615_phy *phy = &dev->phy;
339 struct mt7615_phy *phy2 = dev->mt76.phy2 ? dev->mt76.phy2->priv : NULL;
340 struct ieee80211_supported_band *sband;
341 struct ieee80211_hdr *hdr;
342 __le32 *rxd = (__le32 *)skb->data;
343 u32 rxd0 = le32_to_cpu(rxd[0]);
344 u32 rxd1 = le32_to_cpu(rxd[1]);
345 u32 rxd2 = le32_to_cpu(rxd[2]);
346 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM;
347 bool unicast, hdr_trans, remove_pad, insert_ccmp_hdr = false;
351 u8 chfreq, amsdu_info, qos_ctl = 0;
355 memset(status, 0, sizeof(*status));
357 chfreq = FIELD_GET(MT_RXD1_NORMAL_CH_FREQ, rxd1);
360 else if (phy2->chfreq == phy->chfreq)
362 else if (phy->chfreq == chfreq)
364 else if (phy2->chfreq == chfreq)
369 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR)
372 hdr_trans = rxd1 & MT_RXD1_NORMAL_HDR_TRANS;
373 if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_CM))
376 /* ICV error or CCMP/BIP/WPI MIC error */
377 if (rxd2 & MT_RXD2_NORMAL_ICV_ERR)
378 status->flag |= RX_FLAG_ONLY_MONITOR;
380 unicast = (rxd1 & MT_RXD1_NORMAL_ADDR_TYPE) == MT_RXD1_NORMAL_U2M;
381 idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2);
382 status->wcid = mt7615_rx_get_wcid(dev, idx, unicast);
385 struct mt7615_sta *msta;
387 msta = container_of(status->wcid, struct mt7615_sta, wcid);
388 spin_lock_bh(&dev->sta_poll_lock);
389 if (list_empty(&msta->poll_list))
390 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
391 spin_unlock_bh(&dev->sta_poll_lock);
394 if ((rxd0 & csum_mask) == csum_mask)
395 skb->ip_summed = CHECKSUM_UNNECESSARY;
397 if (rxd2 & MT_RXD2_NORMAL_FCS_ERR)
398 status->flag |= RX_FLAG_FAILED_FCS_CRC;
400 if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR)
401 status->flag |= RX_FLAG_MMIC_ERROR;
403 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 &&
404 !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) {
405 status->flag |= RX_FLAG_DECRYPTED;
406 status->flag |= RX_FLAG_IV_STRIPPED;
407 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
410 remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET;
412 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
416 if (rxd0 & MT_RXD0_NORMAL_GROUP_4) {
417 u32 v0 = le32_to_cpu(rxd[0]);
418 u32 v2 = le32_to_cpu(rxd[2]);
420 fc = cpu_to_le16(FIELD_GET(MT_RXD4_FRAME_CONTROL, v0));
421 qos_ctl = FIELD_GET(MT_RXD6_QOS_CTL, v2);
422 seq_ctrl = FIELD_GET(MT_RXD6_SEQ_CTRL, v2);
425 if ((u8 *)rxd - skb->data >= skb->len)
429 if (rxd0 & MT_RXD0_NORMAL_GROUP_1) {
430 u8 *data = (u8 *)rxd;
432 if (status->flag & RX_FLAG_DECRYPTED) {
433 switch (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2)) {
434 case MT_CIPHER_AES_CCMP:
435 case MT_CIPHER_CCMP_CCX:
436 case MT_CIPHER_CCMP_256:
438 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
441 case MT_CIPHER_TKIP_NO_MIC:
443 case MT_CIPHER_GCMP_256:
444 status->iv[0] = data[5];
445 status->iv[1] = data[4];
446 status->iv[2] = data[3];
447 status->iv[3] = data[2];
448 status->iv[4] = data[1];
449 status->iv[5] = data[0];
456 if ((u8 *)rxd - skb->data >= skb->len)
460 if (rxd0 & MT_RXD0_NORMAL_GROUP_2) {
461 status->timestamp = le32_to_cpu(rxd[0]);
462 status->flag |= RX_FLAG_MACTIME_START;
464 if (!(rxd2 & (MT_RXD2_NORMAL_NON_AMPDU_SUB |
465 MT_RXD2_NORMAL_NON_AMPDU))) {
466 status->flag |= RX_FLAG_AMPDU_DETAILS;
468 /* all subframes of an A-MPDU have the same timestamp */
469 if (phy->rx_ampdu_ts != status->timestamp) {
470 if (!++phy->ampdu_ref)
473 phy->rx_ampdu_ts = status->timestamp;
475 status->ampdu_ref = phy->ampdu_ref;
479 if ((u8 *)rxd - skb->data >= skb->len)
483 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
484 u32 rxdg5 = le32_to_cpu(rxd[5]);
487 * If both PHYs are on the same channel and we don't have a WCID,
488 * we need to figure out which PHY this packet was received on.
489 * On the primary PHY, the noise value for the chains belonging to the
490 * second PHY will be set to the noise value of the last packet from
494 int first_chain = ffs(phy2->mt76->chainmask) - 1;
496 phy_idx = ((rxdg5 >> (first_chain * 8)) & 0xff) == 0;
500 if (phy_idx == 1 && phy2) {
501 mphy = dev->mt76.phy2;
503 status->ext_phy = true;
506 if (!mt7615_firmware_offload(dev) && chfreq != phy->chfreq)
509 mt7615_get_status_freq_info(dev, mphy, status, chfreq);
510 if (status->band == NL80211_BAND_5GHZ)
511 sband = &mphy->sband_5g.sband;
513 sband = &mphy->sband_2g.sband;
515 if (!test_bit(MT76_STATE_RUNNING, &mphy->state))
518 if (!sband->channels)
521 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
522 u32 rxdg0 = le32_to_cpu(rxd[0]);
523 u32 rxdg1 = le32_to_cpu(rxd[1]);
524 u32 rxdg3 = le32_to_cpu(rxd[3]);
525 u8 stbc = FIELD_GET(MT_RXV1_HT_STBC, rxdg0);
528 i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0);
529 switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) {
530 case MT_PHY_TYPE_CCK:
533 case MT_PHY_TYPE_OFDM:
534 i = mt76_get_rate(&dev->mt76, sband, i, cck);
536 case MT_PHY_TYPE_HT_GF:
538 status->encoding = RX_ENC_HT;
542 case MT_PHY_TYPE_VHT:
543 status->nss = FIELD_GET(MT_RXV2_NSTS, rxdg1) + 1;
544 status->encoding = RX_ENC_VHT;
549 status->rate_idx = i;
551 switch (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0)) {
555 status->bw = RATE_INFO_BW_40;
558 status->bw = RATE_INFO_BW_80;
561 status->bw = RATE_INFO_BW_160;
567 if (rxdg0 & MT_RXV1_HT_SHORT_GI)
568 status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
569 if (rxdg0 & MT_RXV1_HT_AD_CODE)
570 status->enc_flags |= RX_ENC_FLAG_LDPC;
572 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
574 status->chains = mphy->antenna_mask;
575 status->chain_signal[0] = to_rssi(MT_RXV4_RCPI0, rxdg3);
576 status->chain_signal[1] = to_rssi(MT_RXV4_RCPI1, rxdg3);
577 status->chain_signal[2] = to_rssi(MT_RXV4_RCPI2, rxdg3);
578 status->chain_signal[3] = to_rssi(MT_RXV4_RCPI3, rxdg3);
580 mt7615_mac_fill_tm_rx(mphy->priv, rxd);
583 if ((u8 *)rxd - skb->data >= skb->len)
587 amsdu_info = FIELD_GET(MT_RXD1_NORMAL_PAYLOAD_FORMAT, rxd1);
588 status->amsdu = !!amsdu_info;
590 status->first_amsdu = amsdu_info == MT_RXD1_FIRST_AMSDU_FRAME;
591 status->last_amsdu = amsdu_info == MT_RXD1_LAST_AMSDU_FRAME;
594 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad;
595 if (hdr_trans && ieee80211_has_morefrags(fc)) {
596 if (mt7615_reverse_frag0_hdr_trans(skb, hdr_gap))
602 skb_pull(skb, hdr_gap);
603 if (!hdr_trans && status->amsdu) {
604 pad_start = ieee80211_get_hdrlen_from_skb(skb);
605 } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) {
607 * When header translation failure is indicated,
608 * the hardware will insert an extra 2-byte field
609 * containing the data length after the protocol
613 if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q)
616 if (get_unaligned_be16(skb->data + pad_start) !=
617 skb->len - pad_start - 2)
622 memmove(skb->data + 2, skb->data, pad_start);
627 if (insert_ccmp_hdr && !hdr_trans) {
628 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
630 mt76_insert_ccmp_hdr(skb, key_id);
634 hdr = (struct ieee80211_hdr *)skb->data;
635 fc = hdr->frame_control;
636 if (ieee80211_is_data_qos(fc)) {
637 seq_ctrl = le16_to_cpu(hdr->seq_ctrl);
638 qos_ctl = *ieee80211_get_qos_ctl(hdr);
641 status->flag |= RX_FLAG_8023;
644 if (!status->wcid || !ieee80211_is_data_qos(fc))
647 status->aggr = unicast &&
648 !ieee80211_is_qos_nullfunc(fc);
649 status->qos_ctl = qos_ctl;
650 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl);
655 void mt7615_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps)
658 EXPORT_SYMBOL_GPL(mt7615_sta_ps);
661 mt7615_mac_tx_rate_val(struct mt7615_dev *dev,
662 struct mt76_phy *mphy,
663 const struct ieee80211_tx_rate *rate,
666 u8 phy, nss, rate_idx;
671 if (rate->flags & IEEE80211_TX_RC_VHT_MCS) {
672 rate_idx = ieee80211_rate_get_vht_mcs(rate);
673 nss = ieee80211_rate_get_vht_nss(rate);
674 phy = MT_PHY_TYPE_VHT;
675 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
677 else if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH)
679 else if (rate->flags & IEEE80211_TX_RC_160_MHZ_WIDTH)
681 } else if (rate->flags & IEEE80211_TX_RC_MCS) {
682 rate_idx = rate->idx;
683 nss = 1 + (rate->idx >> 3);
684 phy = MT_PHY_TYPE_HT;
685 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD)
686 phy = MT_PHY_TYPE_HT_GF;
687 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
690 const struct ieee80211_rate *r;
691 int band = mphy->chandef.chan->band;
695 r = &mphy->hw->wiphy->bands[band]->bitrates[rate->idx];
696 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
697 val = r->hw_value_short;
702 rate_idx = val & 0xff;
705 if (stbc && nss == 1) {
707 rateval |= MT_TX_RATE_STBC;
710 rateval |= (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) |
711 FIELD_PREP(MT_TX_RATE_MODE, phy) |
712 FIELD_PREP(MT_TX_RATE_NSS, nss - 1));
717 int mt7615_mac_write_txwi(struct mt7615_dev *dev, __le32 *txwi,
718 struct sk_buff *skb, struct mt76_wcid *wcid,
719 struct ieee80211_sta *sta, int pid,
720 struct ieee80211_key_conf *key, bool beacon)
722 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
723 u8 fc_type, fc_stype, p_fmt, q_idx, omac_idx = 0, wmm_idx = 0;
724 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
725 struct ieee80211_tx_rate *rate = &info->control.rates[0];
726 bool ext_phy = info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY;
727 bool multicast = is_multicast_ether_addr(hdr->addr1);
728 struct ieee80211_vif *vif = info->control.vif;
729 bool is_mmio = mt76_is_mmio(&dev->mt76);
730 u32 val, sz_txd = is_mmio ? MT_TXD_SIZE : MT_USB_TXD_SIZE;
731 struct mt76_phy *mphy = &dev->mphy;
732 __le16 fc = hdr->frame_control;
737 struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv;
739 omac_idx = mvif->omac_idx;
740 wmm_idx = mvif->wmm_idx;
744 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv;
746 tx_count = msta->rate_count;
749 if (ext_phy && dev->mt76.phy2)
750 mphy = dev->mt76.phy2;
752 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2;
753 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4;
756 p_fmt = MT_TX_TYPE_FW;
757 q_idx = ext_phy ? MT_LMAC_BCN1 : MT_LMAC_BCN0;
758 } else if (skb_get_queue_mapping(skb) >= MT_TXQ_PSD) {
759 p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF;
760 q_idx = ext_phy ? MT_LMAC_ALTX1 : MT_LMAC_ALTX0;
762 p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF;
763 q_idx = wmm_idx * MT7615_MAX_WMM_SETS +
764 mt7615_lmac_mapping(dev, skb_get_queue_mapping(skb));
767 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + sz_txd) |
768 FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_LMAC) |
769 FIELD_PREP(MT_TXD0_Q_IDX, q_idx);
770 txwi[0] = cpu_to_le32(val);
772 val = MT_TXD1_LONG_FORMAT |
773 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) |
774 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
775 FIELD_PREP(MT_TXD1_HDR_INFO,
776 ieee80211_get_hdrlen_from_skb(skb) / 2) |
777 FIELD_PREP(MT_TXD1_TID,
778 skb->priority & IEEE80211_QOS_CTL_TID_MASK) |
779 FIELD_PREP(MT_TXD1_PKT_FMT, p_fmt) |
780 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx);
781 txwi[1] = cpu_to_le32(val);
783 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) |
784 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) |
785 FIELD_PREP(MT_TXD2_MULTICAST, multicast);
787 if (multicast && ieee80211_is_robust_mgmt_frame(skb) &&
788 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) {
792 txwi[3] = cpu_to_le32(MT_TXD3_PROTECT_FRAME);
797 txwi[2] = cpu_to_le32(val);
799 if (!(info->flags & IEEE80211_TX_CTL_AMPDU))
800 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
805 if (rate->idx >= 0 && rate->count &&
806 !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) {
807 bool stbc = info->flags & IEEE80211_TX_CTL_STBC;
809 u16 rateval = mt7615_mac_tx_rate_val(dev, mphy, rate, stbc,
812 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE);
814 val = MT_TXD6_FIXED_BW |
815 FIELD_PREP(MT_TXD6_BW, bw) |
816 FIELD_PREP(MT_TXD6_TX_RATE, rateval);
817 txwi[6] |= cpu_to_le32(val);
819 if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
820 txwi[6] |= cpu_to_le32(MT_TXD6_SGI);
822 if (info->flags & IEEE80211_TX_CTL_LDPC)
823 txwi[6] |= cpu_to_le32(MT_TXD6_LDPC);
825 if (!(rate->flags & (IEEE80211_TX_RC_MCS |
826 IEEE80211_TX_RC_VHT_MCS)))
827 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
829 tx_count = rate->count;
832 if (!ieee80211_is_beacon(fc)) {
833 struct ieee80211_hw *hw = mt76_hw(dev);
835 val = MT_TXD5_TX_STATUS_HOST | FIELD_PREP(MT_TXD5_PID, pid);
836 if (!ieee80211_hw_check(hw, SUPPORTS_PS))
837 val |= MT_TXD5_SW_POWER_MGMT;
838 txwi[5] = cpu_to_le32(val);
841 /* use maximum tx count for beacons */
845 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count);
846 if (info->flags & IEEE80211_TX_CTL_INJECTED) {
847 seqno = le16_to_cpu(hdr->seq_ctrl);
849 if (ieee80211_is_back_req(hdr->frame_control)) {
850 struct ieee80211_bar *bar;
852 bar = (struct ieee80211_bar *)skb->data;
853 seqno = le16_to_cpu(bar->start_seq_num);
856 val |= MT_TXD3_SN_VALID |
857 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno));
860 txwi[3] |= cpu_to_le32(val);
862 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
863 txwi[3] |= cpu_to_le32(MT_TXD3_NO_ACK);
865 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) |
866 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype) |
867 FIELD_PREP(MT_TXD7_SPE_IDX, 0x18);
868 txwi[7] = cpu_to_le32(val);
870 val = FIELD_PREP(MT_TXD8_L_TYPE, fc_type) |
871 FIELD_PREP(MT_TXD8_L_SUB_TYPE, fc_stype);
872 txwi[8] = cpu_to_le32(val);
877 EXPORT_SYMBOL_GPL(mt7615_mac_write_txwi);
879 bool mt7615_mac_wtbl_update(struct mt7615_dev *dev, int idx, u32 mask)
881 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
882 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
884 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY,
888 void mt7615_mac_sta_poll(struct mt7615_dev *dev)
890 static const u8 ac_to_tid[4] = {
891 [IEEE80211_AC_BE] = 0,
892 [IEEE80211_AC_BK] = 1,
893 [IEEE80211_AC_VI] = 4,
894 [IEEE80211_AC_VO] = 6
896 static const u8 hw_queue_map[] = {
897 [IEEE80211_AC_BK] = 0,
898 [IEEE80211_AC_BE] = 1,
899 [IEEE80211_AC_VI] = 2,
900 [IEEE80211_AC_VO] = 3,
902 struct ieee80211_sta *sta;
903 struct mt7615_sta *msta;
904 u32 addr, tx_time[4], rx_time[4];
905 struct list_head sta_poll_list;
908 INIT_LIST_HEAD(&sta_poll_list);
909 spin_lock_bh(&dev->sta_poll_lock);
910 list_splice_init(&dev->sta_poll_list, &sta_poll_list);
911 spin_unlock_bh(&dev->sta_poll_lock);
913 while (!list_empty(&sta_poll_list)) {
916 msta = list_first_entry(&sta_poll_list, struct mt7615_sta,
918 list_del_init(&msta->poll_list);
920 addr = mt7615_mac_wtbl_addr(dev, msta->wcid.idx) + 19 * 4;
922 for (i = 0; i < 4; i++, addr += 8) {
923 u32 tx_last = msta->airtime_ac[i];
924 u32 rx_last = msta->airtime_ac[i + 4];
926 msta->airtime_ac[i] = mt76_rr(dev, addr);
927 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4);
928 tx_time[i] = msta->airtime_ac[i] - tx_last;
929 rx_time[i] = msta->airtime_ac[i + 4] - rx_last;
931 if ((tx_last | rx_last) & BIT(30))
936 mt7615_mac_wtbl_update(dev, msta->wcid.idx,
937 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
938 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac));
944 sta = container_of((void *)msta, struct ieee80211_sta,
946 for (i = 0; i < 4; i++) {
947 u32 tx_cur = tx_time[i];
948 u32 rx_cur = rx_time[hw_queue_map[i]];
949 u8 tid = ac_to_tid[i];
951 if (!tx_cur && !rx_cur)
954 ieee80211_sta_register_airtime(sta, tid, tx_cur,
959 EXPORT_SYMBOL_GPL(mt7615_mac_sta_poll);
962 mt7615_mac_update_rate_desc(struct mt7615_phy *phy, struct mt7615_sta *sta,
963 struct ieee80211_tx_rate *probe_rate,
964 struct ieee80211_tx_rate *rates,
965 struct mt7615_rate_desc *rd)
967 struct mt7615_dev *dev = phy->dev;
968 struct mt76_phy *mphy = phy->mt76;
969 struct ieee80211_tx_rate *ref;
970 bool rateset, stbc = false;
971 int n_rates = sta->n_rates;
975 for (i = n_rates; i < 4; i++)
976 rates[i] = rates[n_rates - 1];
978 rateset = !(sta->rate_set_tsf & BIT(0));
979 memcpy(sta->rateset[rateset].rates, rates,
980 sizeof(sta->rateset[rateset].rates));
982 sta->rateset[rateset].probe_rate = *probe_rate;
983 ref = &sta->rateset[rateset].probe_rate;
985 sta->rateset[rateset].probe_rate.idx = -1;
986 ref = &sta->rateset[rateset].rates[0];
989 rates = sta->rateset[rateset].rates;
990 for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) {
992 * We don't support switching between short and long GI
993 * within the rate set. For accurate tx status reporting, we
994 * need to make sure that flags match.
995 * For improved performance, avoid duplicate entries by
996 * decrementing the MCS index if necessary
998 if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI)
999 rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI;
1001 for (j = 0; j < i; j++) {
1002 if (rates[i].idx != rates[j].idx)
1004 if ((rates[i].flags ^ rates[j].flags) &
1005 (IEEE80211_TX_RC_40_MHZ_WIDTH |
1006 IEEE80211_TX_RC_80_MHZ_WIDTH |
1007 IEEE80211_TX_RC_160_MHZ_WIDTH))
1017 rd->val[0] = mt7615_mac_tx_rate_val(dev, mphy, &rates[0], stbc, &bw);
1021 rd->probe_val = mt7615_mac_tx_rate_val(dev, mphy, probe_rate,
1028 rd->probe_val = rd->val[0];
1031 rd->val[1] = mt7615_mac_tx_rate_val(dev, mphy, &rates[1], stbc, &bw);
1037 rd->val[2] = mt7615_mac_tx_rate_val(dev, mphy, &rates[2], stbc, &bw);
1043 rd->val[3] = mt7615_mac_tx_rate_val(dev, mphy, &rates[3], stbc, &bw);
1047 rd->rateset = rateset;
1052 mt7615_mac_queue_rate_update(struct mt7615_phy *phy, struct mt7615_sta *sta,
1053 struct ieee80211_tx_rate *probe_rate,
1054 struct ieee80211_tx_rate *rates)
1056 struct mt7615_dev *dev = phy->dev;
1057 struct mt7615_wtbl_rate_desc *wrd;
1059 if (work_pending(&dev->rate_work))
1062 wrd = kzalloc(sizeof(*wrd), GFP_ATOMIC);
1067 mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates,
1069 list_add_tail(&wrd->node, &dev->wrd_head);
1070 queue_work(dev->mt76.wq, &dev->rate_work);
1075 u32 mt7615_mac_get_sta_tid_sn(struct mt7615_dev *dev, int wcid, u8 tid)
1077 u32 addr, val, val2;
1080 addr = mt7615_mac_wtbl_addr(dev, wcid) + 11 * 4;
1083 addr += 4 * (offset / 32);
1086 val = mt76_rr(dev, addr);
1091 val2 = mt76_rr(dev, addr);
1092 val |= val2 << (32 - offset);
1095 return val & GENMASK(11, 0);
1098 void mt7615_mac_set_rates(struct mt7615_phy *phy, struct mt7615_sta *sta,
1099 struct ieee80211_tx_rate *probe_rate,
1100 struct ieee80211_tx_rate *rates)
1102 int wcid = sta->wcid.idx, n_rates = sta->n_rates;
1103 struct mt7615_dev *dev = phy->dev;
1104 struct mt7615_rate_desc rd;
1106 u16 idx = sta->vif->mt76.omac_idx;
1108 if (!mt76_is_mmio(&dev->mt76)) {
1109 mt7615_mac_queue_rate_update(phy, sta, probe_rate, rates);
1113 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
1116 memset(&rd, 0, sizeof(struct mt7615_rate_desc));
1117 mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates, &rd);
1119 addr = mt7615_mac_wtbl_addr(dev, wcid);
1120 w27 = mt76_rr(dev, addr + 27 * 4);
1121 w27 &= ~MT_WTBL_W27_CC_BW_SEL;
1122 w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, rd.bw);
1124 w5 = mt76_rr(dev, addr + 5 * 4);
1125 w5 &= ~(MT_WTBL_W5_BW_CAP | MT_WTBL_W5_CHANGE_BW_RATE |
1126 MT_WTBL_W5_MPDU_OK_COUNT |
1127 MT_WTBL_W5_MPDU_FAIL_COUNT |
1128 MT_WTBL_W5_RATE_IDX);
1129 w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, rd.bw) |
1130 FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE,
1131 rd.bw_idx ? rd.bw_idx - 1 : 7);
1133 mt76_wr(dev, MT_WTBL_RIUCR0, w5);
1135 mt76_wr(dev, MT_WTBL_RIUCR1,
1136 FIELD_PREP(MT_WTBL_RIUCR1_RATE0, rd.probe_val) |
1137 FIELD_PREP(MT_WTBL_RIUCR1_RATE1, rd.val[0]) |
1138 FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, rd.val[1]));
1140 mt76_wr(dev, MT_WTBL_RIUCR2,
1141 FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, rd.val[1] >> 8) |
1142 FIELD_PREP(MT_WTBL_RIUCR2_RATE3, rd.val[1]) |
1143 FIELD_PREP(MT_WTBL_RIUCR2_RATE4, rd.val[2]) |
1144 FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, rd.val[2]));
1146 mt76_wr(dev, MT_WTBL_RIUCR3,
1147 FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, rd.val[2] >> 4) |
1148 FIELD_PREP(MT_WTBL_RIUCR3_RATE6, rd.val[3]) |
1149 FIELD_PREP(MT_WTBL_RIUCR3_RATE7, rd.val[3]));
1151 mt76_wr(dev, MT_WTBL_UPDATE,
1152 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) |
1153 MT_WTBL_UPDATE_RATE_UPDATE |
1154 MT_WTBL_UPDATE_TX_COUNT_CLEAR);
1156 mt76_wr(dev, addr + 27 * 4, w27);
1158 idx = idx > HW_BSSID_MAX ? HW_BSSID_0 : idx;
1159 addr = idx > 1 ? MT_LPON_TCR2(idx): MT_LPON_TCR0(idx);
1161 mt76_rmw(dev, addr, MT_LPON_TCR_MODE, MT_LPON_TCR_READ); /* TSF read */
1162 sta->rate_set_tsf = mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0);
1163 sta->rate_set_tsf |= rd.rateset;
1165 if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET))
1166 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
1168 sta->rate_count = 2 * MT7615_RATE_RETRY * n_rates;
1169 sta->wcid.tx_info |= MT_WCID_TX_INFO_SET;
1170 sta->rate_probe = !!probe_rate;
1172 EXPORT_SYMBOL_GPL(mt7615_mac_set_rates);
1175 mt7615_mac_wtbl_update_key(struct mt7615_dev *dev, struct mt76_wcid *wcid,
1176 struct ieee80211_key_conf *key,
1177 enum mt76_cipher_type cipher, u16 cipher_mask,
1178 enum set_key_cmd cmd)
1180 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx) + 30 * 4;
1183 if (key->keylen > sizeof(data))
1186 mt76_rr_copy(dev, addr, data, sizeof(data));
1187 if (cmd == SET_KEY) {
1188 if (cipher == MT_CIPHER_TKIP) {
1189 /* Rx/Tx MIC keys are swapped */
1190 memcpy(data, key->key, 16);
1191 memcpy(data + 16, key->key + 24, 8);
1192 memcpy(data + 24, key->key + 16, 8);
1194 if (cipher_mask == BIT(cipher))
1195 memcpy(data, key->key, key->keylen);
1196 else if (cipher != MT_CIPHER_BIP_CMAC_128)
1197 memcpy(data, key->key, 16);
1198 if (cipher == MT_CIPHER_BIP_CMAC_128)
1199 memcpy(data + 16, key->key, 16);
1202 if (cipher == MT_CIPHER_BIP_CMAC_128)
1203 memset(data + 16, 0, 16);
1204 else if (cipher_mask)
1205 memset(data, 0, 16);
1207 memset(data, 0, sizeof(data));
1210 mt76_wr_copy(dev, addr, data, sizeof(data));
1216 mt7615_mac_wtbl_update_pk(struct mt7615_dev *dev, struct mt76_wcid *wcid,
1217 enum mt76_cipher_type cipher, u16 cipher_mask,
1218 int keyidx, enum set_key_cmd cmd)
1220 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx), w0, w1;
1222 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
1225 w0 = mt76_rr(dev, addr);
1226 w1 = mt76_rr(dev, addr + 4);
1229 w0 |= MT_WTBL_W0_RX_KEY_VALID;
1231 w0 &= ~(MT_WTBL_W0_RX_KEY_VALID | MT_WTBL_W0_KEY_IDX);
1232 if (cipher_mask & BIT(MT_CIPHER_BIP_CMAC_128))
1233 w0 |= MT_WTBL_W0_RX_IK_VALID;
1235 w0 &= ~MT_WTBL_W0_RX_IK_VALID;
1237 if (cmd == SET_KEY &&
1238 (cipher != MT_CIPHER_BIP_CMAC_128 ||
1239 cipher_mask == BIT(cipher))) {
1240 w0 &= ~MT_WTBL_W0_KEY_IDX;
1241 w0 |= FIELD_PREP(MT_WTBL_W0_KEY_IDX, keyidx);
1244 mt76_wr(dev, MT_WTBL_RICR0, w0);
1245 mt76_wr(dev, MT_WTBL_RICR1, w1);
1247 if (!mt7615_mac_wtbl_update(dev, wcid->idx,
1248 MT_WTBL_UPDATE_RXINFO_UPDATE))
1255 mt7615_mac_wtbl_update_cipher(struct mt7615_dev *dev, struct mt76_wcid *wcid,
1256 enum mt76_cipher_type cipher, u16 cipher_mask,
1257 enum set_key_cmd cmd)
1259 u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx);
1262 mt76_clear(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE);
1269 if (cipher == MT_CIPHER_BIP_CMAC_128 &&
1270 cipher_mask & ~BIT(MT_CIPHER_BIP_CMAC_128))
1273 mt76_rmw(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE,
1274 FIELD_PREP(MT_WTBL_W2_KEY_TYPE, cipher));
1277 int __mt7615_mac_wtbl_set_key(struct mt7615_dev *dev,
1278 struct mt76_wcid *wcid,
1279 struct ieee80211_key_conf *key,
1280 enum set_key_cmd cmd)
1282 enum mt76_cipher_type cipher;
1283 u16 cipher_mask = wcid->cipher;
1286 cipher = mt7615_mac_get_cipher(key->cipher);
1287 if (cipher == MT_CIPHER_NONE)
1291 cipher_mask |= BIT(cipher);
1293 cipher_mask &= ~BIT(cipher);
1295 mt7615_mac_wtbl_update_cipher(dev, wcid, cipher, cipher_mask, cmd);
1296 err = mt7615_mac_wtbl_update_key(dev, wcid, key, cipher, cipher_mask,
1301 err = mt7615_mac_wtbl_update_pk(dev, wcid, cipher, cipher_mask,
1306 wcid->cipher = cipher_mask;
1311 int mt7615_mac_wtbl_set_key(struct mt7615_dev *dev,
1312 struct mt76_wcid *wcid,
1313 struct ieee80211_key_conf *key,
1314 enum set_key_cmd cmd)
1318 spin_lock_bh(&dev->mt76.lock);
1319 err = __mt7615_mac_wtbl_set_key(dev, wcid, key, cmd);
1320 spin_unlock_bh(&dev->mt76.lock);
1325 static bool mt7615_fill_txs(struct mt7615_dev *dev, struct mt7615_sta *sta,
1326 struct ieee80211_tx_info *info, __le32 *txs_data)
1328 struct ieee80211_supported_band *sband;
1329 struct mt7615_rate_set *rs;
1330 struct mt76_phy *mphy;
1331 int first_idx = 0, last_idx;
1333 bool fixed_rate, ack_timeout;
1334 bool ampdu, cck = false;
1337 u32 final_rate, final_rate_flags, final_nss, txs;
1339 txs = le32_to_cpu(txs_data[1]);
1340 ampdu = txs & MT_TXS1_AMPDU;
1342 txs = le32_to_cpu(txs_data[3]);
1343 count = FIELD_GET(MT_TXS3_TX_COUNT, txs);
1344 last_idx = FIELD_GET(MT_TXS3_LAST_TX_RATE, txs);
1346 txs = le32_to_cpu(txs_data[0]);
1347 fixed_rate = txs & MT_TXS0_FIXED_RATE;
1348 final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs);
1349 ack_timeout = txs & MT_TXS0_ACK_TIMEOUT;
1351 if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT))
1354 if (txs & MT_TXS0_QUEUE_TIMEOUT)
1358 info->flags |= IEEE80211_TX_STAT_ACK;
1360 info->status.ampdu_len = 1;
1361 info->status.ampdu_ack_len = !!(info->flags &
1362 IEEE80211_TX_STAT_ACK);
1364 if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU))
1365 info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU;
1367 first_idx = max_t(int, 0, last_idx - (count - 1) / MT7615_RATE_RETRY);
1370 info->status.rates[0].count = count;
1375 rate_set_tsf = READ_ONCE(sta->rate_set_tsf);
1376 rs_idx = !((u32)(le32_get_bits(txs_data[4], MT_TXS4_F0_TIMESTAMP) -
1377 rate_set_tsf) < 1000000);
1378 rs_idx ^= rate_set_tsf & BIT(0);
1379 rs = &sta->rateset[rs_idx];
1381 if (!first_idx && rs->probe_rate.idx >= 0) {
1382 info->status.rates[0] = rs->probe_rate;
1384 spin_lock_bh(&dev->mt76.lock);
1385 if (sta->rate_probe) {
1386 struct mt7615_phy *phy = &dev->phy;
1388 if (sta->wcid.ext_phy && dev->mt76.phy2)
1389 phy = dev->mt76.phy2->priv;
1391 mt7615_mac_set_rates(phy, sta, NULL, sta->rates);
1393 spin_unlock_bh(&dev->mt76.lock);
1395 info->status.rates[0] = rs->rates[first_idx / 2];
1397 info->status.rates[0].count = 0;
1399 for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) {
1400 struct ieee80211_tx_rate *cur_rate;
1403 cur_rate = &rs->rates[idx / 2];
1404 cur_count = min_t(int, MT7615_RATE_RETRY, count);
1407 if (idx && (cur_rate->idx != info->status.rates[i].idx ||
1408 cur_rate->flags != info->status.rates[i].flags)) {
1410 if (i == ARRAY_SIZE(info->status.rates)) {
1415 info->status.rates[i] = *cur_rate;
1416 info->status.rates[i].count = 0;
1419 info->status.rates[i].count += cur_count;
1423 final_rate_flags = info->status.rates[i].flags;
1425 switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) {
1426 case MT_PHY_TYPE_CCK:
1429 case MT_PHY_TYPE_OFDM:
1431 if (sta->wcid.ext_phy && dev->mt76.phy2)
1432 mphy = dev->mt76.phy2;
1434 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ)
1435 sband = &mphy->sband_5g.sband;
1437 sband = &mphy->sband_2g.sband;
1438 final_rate &= MT_TX_RATE_IDX;
1439 final_rate = mt76_get_rate(&dev->mt76, sband, final_rate,
1441 final_rate_flags = 0;
1443 case MT_PHY_TYPE_HT_GF:
1444 case MT_PHY_TYPE_HT:
1445 final_rate_flags |= IEEE80211_TX_RC_MCS;
1446 final_rate &= MT_TX_RATE_IDX;
1447 if (final_rate > 31)
1450 case MT_PHY_TYPE_VHT:
1451 final_nss = FIELD_GET(MT_TX_RATE_NSS, final_rate);
1453 if ((final_rate & MT_TX_RATE_STBC) && final_nss)
1456 final_rate_flags |= IEEE80211_TX_RC_VHT_MCS;
1457 final_rate = (final_rate & MT_TX_RATE_IDX) | (final_nss << 4);
1463 info->status.rates[i].idx = final_rate;
1464 info->status.rates[i].flags = final_rate_flags;
1469 static bool mt7615_mac_add_txs_skb(struct mt7615_dev *dev,
1470 struct mt7615_sta *sta, int pid,
1473 struct mt76_dev *mdev = &dev->mt76;
1474 struct sk_buff_head list;
1475 struct sk_buff *skb;
1477 if (pid < MT_PACKET_ID_FIRST)
1480 trace_mac_txdone(mdev, sta->wcid.idx, pid);
1482 mt76_tx_status_lock(mdev, &list);
1483 skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list);
1485 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1487 if (!mt7615_fill_txs(dev, sta, info, txs_data)) {
1488 info->status.rates[0].count = 0;
1489 info->status.rates[0].idx = -1;
1492 mt76_tx_status_skb_done(mdev, skb, &list);
1494 mt76_tx_status_unlock(mdev, &list);
1499 static void mt7615_mac_add_txs(struct mt7615_dev *dev, void *data)
1501 struct ieee80211_tx_info info = {};
1502 struct ieee80211_sta *sta = NULL;
1503 struct mt7615_sta *msta = NULL;
1504 struct mt76_wcid *wcid;
1505 struct mt76_phy *mphy = &dev->mt76.phy;
1506 __le32 *txs_data = data;
1510 pid = le32_get_bits(txs_data[0], MT_TXS0_PID);
1511 wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID);
1513 if (pid == MT_PACKET_ID_NO_ACK)
1516 if (wcidx >= MT7615_WTBL_SIZE)
1521 wcid = rcu_dereference(dev->mt76.wcid[wcidx]);
1525 msta = container_of(wcid, struct mt7615_sta, wcid);
1526 sta = wcid_to_sta(wcid);
1528 spin_lock_bh(&dev->sta_poll_lock);
1529 if (list_empty(&msta->poll_list))
1530 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
1531 spin_unlock_bh(&dev->sta_poll_lock);
1533 if (mt7615_mac_add_txs_skb(dev, msta, pid, txs_data))
1536 if (wcidx >= MT7615_WTBL_STA || !sta)
1539 if (wcid->ext_phy && dev->mt76.phy2)
1540 mphy = dev->mt76.phy2;
1542 if (mt7615_fill_txs(dev, msta, &info, txs_data))
1543 ieee80211_tx_status_noskb(mphy->hw, sta, &info);
1550 mt7615_txwi_free(struct mt7615_dev *dev, struct mt76_txwi_cache *txwi)
1552 struct mt76_dev *mdev = &dev->mt76;
1557 mt76_connac_txp_skb_unmap(mdev, txwi);
1561 txwi_data = (__le32 *)mt76_get_txwi_ptr(mdev, txwi);
1562 val = le32_to_cpu(txwi_data[1]);
1563 wcid = FIELD_GET(MT_TXD1_WLAN_IDX, val);
1564 mt76_tx_complete_skb(mdev, wcid, txwi->skb);
1568 mt76_put_txwi(mdev, txwi);
1572 mt7615_mac_tx_free_token(struct mt7615_dev *dev, u16 token)
1574 struct mt76_dev *mdev = &dev->mt76;
1575 struct mt76_txwi_cache *txwi;
1577 trace_mac_tx_free(dev, token);
1578 txwi = mt76_token_put(mdev, token);
1582 mt7615_txwi_free(dev, txwi);
1585 static void mt7615_mac_tx_free(struct mt7615_dev *dev, void *data, int len)
1587 struct mt76_connac_tx_free *free = data;
1588 void *tx_token = data + sizeof(*free);
1589 void *end = data + len;
1592 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false);
1593 if (is_mt7615(&dev->mt76)) {
1594 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false);
1596 for (i = 0; i < IEEE80211_NUM_ACS; i++)
1597 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false);
1600 count = le16_get_bits(free->ctrl, MT_TX_FREE_MSDU_ID_CNT);
1601 if (is_mt7615(&dev->mt76)) {
1602 __le16 *token = tx_token;
1604 if (WARN_ON_ONCE((void *)&token[count] > end))
1607 for (i = 0; i < count; i++)
1608 mt7615_mac_tx_free_token(dev, le16_to_cpu(token[i]));
1610 __le32 *token = tx_token;
1612 if (WARN_ON_ONCE((void *)&token[count] > end))
1615 for (i = 0; i < count; i++)
1616 mt7615_mac_tx_free_token(dev, le32_to_cpu(token[i]));
1620 mt7615_mac_sta_poll(dev);
1623 mt76_worker_schedule(&dev->mt76.tx_worker);
1626 bool mt7615_rx_check(struct mt76_dev *mdev, void *data, int len)
1628 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
1629 __le32 *rxd = (__le32 *)data;
1630 __le32 *end = (__le32 *)&rxd[len / 4];
1631 enum rx_pkt_type type;
1633 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE);
1636 case PKT_TYPE_TXRX_NOTIFY:
1637 mt7615_mac_tx_free(dev, data, len);
1640 for (rxd++; rxd + 7 <= end; rxd += 7)
1641 mt7615_mac_add_txs(dev, rxd);
1647 EXPORT_SYMBOL_GPL(mt7615_rx_check);
1649 void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1650 struct sk_buff *skb)
1652 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
1653 __le32 *rxd = (__le32 *)skb->data;
1654 __le32 *end = (__le32 *)&skb->data[skb->len];
1655 enum rx_pkt_type type;
1658 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE);
1659 flag = le32_get_bits(rxd[0], MT_RXD0_PKT_FLAG);
1660 if (type == PKT_TYPE_RX_EVENT && flag == 0x1)
1661 type = PKT_TYPE_NORMAL_MCU;
1665 for (rxd++; rxd + 7 <= end; rxd += 7)
1666 mt7615_mac_add_txs(dev, rxd);
1669 case PKT_TYPE_TXRX_NOTIFY:
1670 mt7615_mac_tx_free(dev, skb->data, skb->len);
1673 case PKT_TYPE_RX_EVENT:
1674 mt7615_mcu_rx_event(dev, skb);
1676 case PKT_TYPE_NORMAL_MCU:
1677 case PKT_TYPE_NORMAL:
1678 if (!mt7615_mac_fill_rx(dev, skb)) {
1679 mt76_rx(&dev->mt76, q, skb);
1688 EXPORT_SYMBOL_GPL(mt7615_queue_rx_skb);
1691 mt7615_mac_set_sensitivity(struct mt7615_phy *phy, int val, bool ofdm)
1693 struct mt7615_dev *dev = phy->dev;
1694 bool ext_phy = phy != &dev->phy;
1696 if (is_mt7663(&dev->mt76)) {
1698 mt76_rmw(dev, MT7663_WF_PHY_MIN_PRI_PWR(ext_phy),
1699 MT_WF_PHY_PD_OFDM_MASK(0),
1700 MT_WF_PHY_PD_OFDM(0, val));
1702 mt76_rmw(dev, MT7663_WF_PHY_RXTD_CCK_PD(ext_phy),
1703 MT_WF_PHY_PD_CCK_MASK(ext_phy),
1704 MT_WF_PHY_PD_CCK(ext_phy, val));
1709 mt76_rmw(dev, MT_WF_PHY_MIN_PRI_PWR(ext_phy),
1710 MT_WF_PHY_PD_OFDM_MASK(ext_phy),
1711 MT_WF_PHY_PD_OFDM(ext_phy, val));
1713 mt76_rmw(dev, MT_WF_PHY_RXTD_CCK_PD(ext_phy),
1714 MT_WF_PHY_PD_CCK_MASK(ext_phy),
1715 MT_WF_PHY_PD_CCK(ext_phy, val));
1719 mt7615_mac_set_default_sensitivity(struct mt7615_phy *phy)
1722 mt7615_mac_set_sensitivity(phy, 0x13c, true);
1724 mt7615_mac_set_sensitivity(phy, 0x92, false);
1726 phy->ofdm_sensitivity = -98;
1727 phy->cck_sensitivity = -110;
1728 phy->last_cca_adj = jiffies;
1731 void mt7615_mac_set_scs(struct mt7615_phy *phy, bool enable)
1733 struct mt7615_dev *dev = phy->dev;
1734 bool ext_phy = phy != &dev->phy;
1737 mt7615_mutex_acquire(dev);
1739 if (phy->scs_en == enable)
1742 if (is_mt7663(&dev->mt76)) {
1743 reg = MT7663_WF_PHY_MIN_PRI_PWR(ext_phy);
1744 mask = MT_WF_PHY_PD_BLK(0);
1746 reg = MT_WF_PHY_MIN_PRI_PWR(ext_phy);
1747 mask = MT_WF_PHY_PD_BLK(ext_phy);
1751 mt76_set(dev, reg, mask);
1752 if (is_mt7622(&dev->mt76)) {
1753 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7 << 8);
1754 mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7);
1757 mt76_clear(dev, reg, mask);
1760 mt7615_mac_set_default_sensitivity(phy);
1761 phy->scs_en = enable;
1764 mt7615_mutex_release(dev);
1767 void mt7615_mac_enable_nf(struct mt7615_dev *dev, bool ext_phy)
1771 if (is_mt7663(&dev->mt76))
1772 reg = MT7663_WF_PHY_R0_PHYMUX_5;
1774 reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy);
1777 rxtd = MT_WF_PHY_RXTD2(10);
1779 rxtd = MT_WF_PHY_RXTD(12);
1781 mt76_set(dev, rxtd, BIT(18) | BIT(29));
1782 mt76_set(dev, reg, 0x5 << 12);
1785 void mt7615_mac_cca_stats_reset(struct mt7615_phy *phy)
1787 struct mt7615_dev *dev = phy->dev;
1788 bool ext_phy = phy != &dev->phy;
1791 if (is_mt7663(&dev->mt76))
1792 reg = MT7663_WF_PHY_R0_PHYMUX_5;
1794 reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy);
1796 /* reset PD and MDRDY counters */
1797 mt76_clear(dev, reg, GENMASK(22, 20));
1798 mt76_set(dev, reg, BIT(22) | BIT(20));
1802 mt7615_mac_adjust_sensitivity(struct mt7615_phy *phy,
1803 u32 rts_err_rate, bool ofdm)
1805 struct mt7615_dev *dev = phy->dev;
1806 int false_cca = ofdm ? phy->false_cca_ofdm : phy->false_cca_cck;
1807 bool ext_phy = phy != &dev->phy;
1808 s16 def_th = ofdm ? -98 : -110;
1809 bool update = false;
1813 sensitivity = ofdm ? &phy->ofdm_sensitivity : &phy->cck_sensitivity;
1814 signal = mt76_get_min_avg_rssi(&dev->mt76, ext_phy);
1816 mt7615_mac_set_default_sensitivity(phy);
1820 signal = min(signal, -72);
1821 if (false_cca > 500) {
1822 if (rts_err_rate > MT_FRAC(40, 100))
1825 /* decrease coverage */
1826 if (*sensitivity == def_th && signal > -90) {
1829 } else if (*sensitivity + 2 < signal) {
1833 } else if ((false_cca > 0 && false_cca < 50) ||
1834 rts_err_rate > MT_FRAC(60, 100)) {
1835 /* increase coverage */
1836 if (*sensitivity - 2 >= def_th) {
1842 if (*sensitivity > signal) {
1843 *sensitivity = signal;
1848 u16 val = ofdm ? *sensitivity * 2 + 512 : *sensitivity + 256;
1850 mt7615_mac_set_sensitivity(phy, val, ofdm);
1851 phy->last_cca_adj = jiffies;
1856 mt7615_mac_scs_check(struct mt7615_phy *phy)
1858 struct mt7615_dev *dev = phy->dev;
1859 struct mib_stats *mib = &phy->mib;
1860 u32 val, rts_err_rate = 0;
1861 u32 mdrdy_cck, mdrdy_ofdm, pd_cck, pd_ofdm;
1862 bool ext_phy = phy != &dev->phy;
1867 if (is_mt7663(&dev->mt76))
1868 val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS0(ext_phy));
1870 val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS0(ext_phy));
1871 pd_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_CCK, val);
1872 pd_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_OFDM, val);
1874 if (is_mt7663(&dev->mt76))
1875 val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS5(ext_phy));
1877 val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS5(ext_phy));
1878 mdrdy_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_CCK, val);
1879 mdrdy_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_OFDM, val);
1881 phy->false_cca_ofdm = pd_ofdm - mdrdy_ofdm;
1882 phy->false_cca_cck = pd_cck - mdrdy_cck;
1883 mt7615_mac_cca_stats_reset(phy);
1885 if (mib->rts_cnt + mib->rts_retries_cnt)
1886 rts_err_rate = MT_FRAC(mib->rts_retries_cnt,
1887 mib->rts_cnt + mib->rts_retries_cnt);
1890 mt7615_mac_adjust_sensitivity(phy, rts_err_rate, false);
1892 mt7615_mac_adjust_sensitivity(phy, rts_err_rate, true);
1894 if (time_after(jiffies, phy->last_cca_adj + 10 * HZ))
1895 mt7615_mac_set_default_sensitivity(phy);
1899 mt7615_phy_get_nf(struct mt7615_dev *dev, int idx)
1901 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 };
1902 u32 reg, val, sum = 0, n = 0;
1905 if (is_mt7663(&dev->mt76))
1906 reg = MT7663_WF_PHY_RXTD(20);
1908 reg = idx ? MT_WF_PHY_RXTD2(17) : MT_WF_PHY_RXTD(20);
1910 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) {
1911 val = mt76_rr(dev, reg);
1912 sum += val * nf_power[i];
1923 mt7615_phy_update_channel(struct mt76_phy *mphy, int idx)
1925 struct mt7615_dev *dev = container_of(mphy->dev, struct mt7615_dev, mt76);
1926 struct mt7615_phy *phy = mphy->priv;
1927 struct mt76_channel_state *state;
1928 u64 busy_time, tx_time, rx_time, obss_time;
1929 u32 obss_reg = idx ? MT_WF_RMAC_MIB_TIME6 : MT_WF_RMAC_MIB_TIME5;
1932 busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx),
1933 MT_MIB_SDR9_BUSY_MASK);
1934 tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx),
1935 MT_MIB_SDR36_TXTIME_MASK);
1936 rx_time = mt76_get_field(dev, MT_MIB_SDR37(idx),
1937 MT_MIB_SDR37_RXTIME_MASK);
1938 obss_time = mt76_get_field(dev, obss_reg, MT_MIB_OBSSTIME_MASK);
1940 nf = mt7615_phy_get_nf(dev, idx);
1942 phy->noise = nf << 4;
1944 phy->noise += nf - (phy->noise >> 4);
1946 state = mphy->chan_state;
1947 state->cc_busy += busy_time;
1948 state->cc_tx += tx_time;
1949 state->cc_rx += rx_time + obss_time;
1950 state->cc_bss_rx += rx_time;
1951 state->noise = -(phy->noise >> 4);
1954 static void mt7615_update_survey(struct mt7615_dev *dev)
1956 struct mt76_dev *mdev = &dev->mt76;
1959 /* MT7615 can only update both phys simultaneously
1960 * since some reisters are shared across bands.
1963 mt7615_phy_update_channel(&mdev->phy, 0);
1965 mt7615_phy_update_channel(mdev->phy2, 1);
1967 cur_time = ktime_get_boottime();
1969 mt76_update_survey_active_time(&mdev->phy, cur_time);
1971 mt76_update_survey_active_time(mdev->phy2, cur_time);
1973 /* reset obss airtime */
1974 mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR);
1977 void mt7615_update_channel(struct mt76_phy *mphy)
1979 struct mt7615_dev *dev = container_of(mphy->dev, struct mt7615_dev, mt76);
1981 if (mt76_connac_pm_wake(&dev->mphy, &dev->pm))
1984 mt7615_update_survey(dev);
1985 mt76_connac_power_save_sched(&dev->mphy, &dev->pm);
1987 EXPORT_SYMBOL_GPL(mt7615_update_channel);
1990 mt7615_mac_update_mib_stats(struct mt7615_phy *phy)
1992 struct mt7615_dev *dev = phy->dev;
1993 struct mib_stats *mib = &phy->mib;
1994 bool ext_phy = phy != &dev->phy;
1998 mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(ext_phy),
1999 MT_MIB_SDR3_FCS_ERR_MASK);
2001 val = mt76_get_field(dev, MT_MIB_SDR14(ext_phy),
2002 MT_MIB_AMPDU_MPDU_COUNT);
2004 val2 = mt76_get_field(dev, MT_MIB_SDR15(ext_phy),
2005 MT_MIB_AMPDU_ACK_COUNT);
2006 mib->aggr_per = 1000 * (val - val2) / val;
2009 aggr = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0;
2010 for (i = 0; i < 4; i++) {
2011 val = mt76_rr(dev, MT_MIB_MB_SDR1(ext_phy, i));
2012 mib->ba_miss_cnt += FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val);
2013 mib->ack_fail_cnt += FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK,
2016 val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i));
2017 mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val);
2018 mib->rts_retries_cnt += FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK,
2021 val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i));
2022 dev->mt76.aggr_stats[aggr++] += val & 0xffff;
2023 dev->mt76.aggr_stats[aggr++] += val >> 16;
2027 void mt7615_pm_wake_work(struct work_struct *work)
2029 struct mt7615_dev *dev;
2030 struct mt76_phy *mphy;
2032 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev,
2034 mphy = dev->phy.mt76;
2036 if (!mt7615_mcu_set_drv_ctrl(dev)) {
2037 struct mt76_dev *mdev = &dev->mt76;
2040 if (mt76_is_sdio(mdev)) {
2041 mt76_connac_pm_dequeue_skbs(mphy, &dev->pm);
2042 mt76_worker_schedule(&mdev->sdio.txrx_worker);
2045 mt76_for_each_q_rx(mdev, i)
2046 napi_schedule(&mdev->napi[i]);
2048 mt76_connac_pm_dequeue_skbs(mphy, &dev->pm);
2049 mt76_queue_tx_cleanup(dev, mdev->q_mcu[MT_MCUQ_WM],
2053 if (test_bit(MT76_STATE_RUNNING, &mphy->state)) {
2054 unsigned long timeout;
2056 timeout = mt7615_get_macwork_timeout(dev);
2057 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work,
2062 ieee80211_wake_queues(mphy->hw);
2063 wake_up(&dev->pm.wait);
2066 void mt7615_pm_power_save_work(struct work_struct *work)
2068 struct mt7615_dev *dev;
2069 unsigned long delta;
2071 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev,
2074 delta = dev->pm.idle_timeout;
2075 if (test_bit(MT76_HW_SCANNING, &dev->mphy.state) ||
2076 test_bit(MT76_HW_SCHED_SCANNING, &dev->mphy.state))
2079 if (mutex_is_locked(&dev->mt76.mutex))
2080 /* if mt76 mutex is held we should not put the device
2081 * to sleep since we are currently accessing device
2082 * register map. We need to wait for the next power_save
2087 if (time_is_after_jiffies(dev->pm.last_activity + delta)) {
2088 delta = dev->pm.last_activity + delta - jiffies;
2092 if (!mt7615_mcu_set_fw_ctrl(dev))
2095 queue_delayed_work(dev->mt76.wq, &dev->pm.ps_work, delta);
2098 void mt7615_mac_work(struct work_struct *work)
2100 struct mt7615_phy *phy;
2101 struct mt76_phy *mphy;
2102 unsigned long timeout;
2104 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy,
2108 mt7615_mutex_acquire(phy->dev);
2110 mt7615_update_survey(phy->dev);
2111 if (++mphy->mac_work_count == 5) {
2112 mphy->mac_work_count = 0;
2114 mt7615_mac_update_mib_stats(phy);
2115 mt7615_mac_scs_check(phy);
2118 mt7615_mutex_release(phy->dev);
2120 mt76_tx_status_check(mphy->dev, false);
2122 timeout = mt7615_get_macwork_timeout(phy->dev);
2123 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, timeout);
2126 void mt7615_tx_token_put(struct mt7615_dev *dev)
2128 struct mt76_txwi_cache *txwi;
2131 spin_lock_bh(&dev->mt76.token_lock);
2132 idr_for_each_entry(&dev->mt76.token, txwi, id)
2133 mt7615_txwi_free(dev, txwi);
2134 spin_unlock_bh(&dev->mt76.token_lock);
2135 idr_destroy(&dev->mt76.token);
2137 EXPORT_SYMBOL_GPL(mt7615_tx_token_put);
2139 static void mt7615_dfs_stop_radar_detector(struct mt7615_phy *phy)
2141 struct mt7615_dev *dev = phy->dev;
2143 if (phy->rdd_state & BIT(0))
2144 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 0,
2146 if (phy->rdd_state & BIT(1))
2147 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 1,
2151 static int mt7615_dfs_start_rdd(struct mt7615_dev *dev, int chain)
2155 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_START, chain,
2160 return mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_DET_MODE, chain,
2164 static int mt7615_dfs_start_radar_detector(struct mt7615_phy *phy)
2166 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
2167 struct mt7615_dev *dev = phy->dev;
2168 bool ext_phy = phy != &dev->phy;
2172 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_START, ext_phy,
2177 err = mt7615_dfs_start_rdd(dev, ext_phy);
2181 phy->rdd_state |= BIT(ext_phy);
2183 if (chandef->width == NL80211_CHAN_WIDTH_160 ||
2184 chandef->width == NL80211_CHAN_WIDTH_80P80) {
2185 err = mt7615_dfs_start_rdd(dev, 1);
2189 phy->rdd_state |= BIT(1);
2196 mt7615_dfs_init_radar_specs(struct mt7615_phy *phy)
2198 const struct mt7615_dfs_radar_spec *radar_specs;
2199 struct mt7615_dev *dev = phy->dev;
2200 int err, i, lpn = 500;
2202 switch (dev->mt76.region) {
2203 case NL80211_DFS_FCC:
2204 radar_specs = &fcc_radar_specs;
2207 case NL80211_DFS_ETSI:
2208 radar_specs = &etsi_radar_specs;
2210 case NL80211_DFS_JP:
2211 radar_specs = &jp_radar_specs;
2217 /* avoid FCC radar detection in non-FCC region */
2218 err = mt7615_mcu_set_fcc5_lpn(dev, lpn);
2222 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) {
2223 err = mt7615_mcu_set_radar_th(dev, i,
2224 &radar_specs->radar_pattern[i]);
2229 return mt7615_mcu_set_pulse_th(dev, &radar_specs->pulse_th);
2232 int mt7615_dfs_init_radar_detector(struct mt7615_phy *phy)
2234 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
2235 struct mt7615_dev *dev = phy->dev;
2236 bool ext_phy = phy != &dev->phy;
2237 enum mt76_dfs_state dfs_state, prev_state;
2240 if (is_mt7663(&dev->mt76))
2243 prev_state = phy->mt76->dfs_state;
2244 dfs_state = mt76_phy_dfs_state(phy->mt76);
2245 if ((chandef->chan->flags & IEEE80211_CHAN_RADAR) &&
2246 dfs_state < MT_DFS_STATE_CAC)
2247 dfs_state = MT_DFS_STATE_ACTIVE;
2249 if (prev_state == dfs_state)
2252 if (dfs_state == MT_DFS_STATE_DISABLED)
2255 if (prev_state <= MT_DFS_STATE_DISABLED) {
2256 err = mt7615_dfs_init_radar_specs(phy);
2260 err = mt7615_dfs_start_radar_detector(phy);
2264 phy->mt76->dfs_state = MT_DFS_STATE_CAC;
2267 if (dfs_state == MT_DFS_STATE_CAC)
2270 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_END,
2271 ext_phy, MT_RX_SEL0, 0);
2273 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN;
2277 phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE;
2281 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_NORMAL_START, ext_phy,
2286 mt7615_dfs_stop_radar_detector(phy);
2287 phy->mt76->dfs_state = MT_DFS_STATE_DISABLED;
2292 int mt7615_mac_set_beacon_filter(struct mt7615_phy *phy,
2293 struct ieee80211_vif *vif,
2296 struct mt7615_dev *dev = phy->dev;
2297 bool ext_phy = phy != &dev->phy;
2300 if (!mt7615_firmware_offload(dev))
2303 switch (vif->type) {
2304 case NL80211_IFTYPE_MONITOR:
2306 case NL80211_IFTYPE_MESH_POINT:
2307 case NL80211_IFTYPE_ADHOC:
2308 case NL80211_IFTYPE_AP:
2310 phy->n_beacon_vif++;
2312 phy->n_beacon_vif--;
2318 err = mt7615_mcu_set_bss_pm(dev, vif, !phy->n_beacon_vif);
2322 if (phy->n_beacon_vif) {
2323 vif->driver_flags &= ~IEEE80211_VIF_BEACON_FILTER;
2324 mt76_clear(dev, MT_WF_RFCR(ext_phy),
2325 MT_WF_RFCR_DROP_OTHER_BEACON);
2327 vif->driver_flags |= IEEE80211_VIF_BEACON_FILTER;
2328 mt76_set(dev, MT_WF_RFCR(ext_phy),
2329 MT_WF_RFCR_DROP_OTHER_BEACON);
2335 void mt7615_coredump_work(struct work_struct *work)
2337 struct mt7615_dev *dev;
2340 dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev,
2341 coredump.work.work);
2343 if (time_is_after_jiffies(dev->coredump.last_activity +
2344 4 * MT76_CONNAC_COREDUMP_TIMEOUT)) {
2345 queue_delayed_work(dev->mt76.wq, &dev->coredump.work,
2346 MT76_CONNAC_COREDUMP_TIMEOUT);
2350 dump = vzalloc(MT76_CONNAC_COREDUMP_SZ);
2354 struct sk_buff *skb;
2356 spin_lock_bh(&dev->mt76.lock);
2357 skb = __skb_dequeue(&dev->coredump.msg_list);
2358 spin_unlock_bh(&dev->mt76.lock);
2363 skb_pull(skb, sizeof(struct mt7615_mcu_rxd));
2364 if (data + skb->len - dump > MT76_CONNAC_COREDUMP_SZ) {
2369 memcpy(data, skb->data, skb->len);
2374 dev_coredumpv(dev->mt76.dev, dump, MT76_CONNAC_COREDUMP_SZ,