drivers/net/wireless/intel/iwlwifi/pcie/tx.c

   1 /******************************************************************************
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   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  11  * Copyright(c) 2018 - 2019 Intel Corporation
  12  *
  13  * This program is free software; you can redistribute it and/or modify it
  14  * under the terms of version 2 of the GNU General Public License as
  15  * published by the Free Software Foundation.
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  23  * file called COPYING.
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  30  *
  31  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
  32  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  33  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  34  * Copyright(c) 2018 - 2019 Intel Corporation
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  38  * modification, are permitted provided that the following conditions
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  42  *    notice, this list of conditions and the following disclaimer.
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  45  *    the documentation and/or other materials provided with the
  46  *    distribution.
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  48  *    contributors may be used to endorse or promote products derived
  49  *    from this software without specific prior written permission.
  50  *
  51  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  52  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  53  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  54  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  55  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  61  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  62  *
  63  *****************************************************************************/
  64 #include <linux/etherdevice.h>
  65 #include <linux/ieee80211.h>
  66 #include <linux/slab.h>
  67 #include <linux/sched.h>
  68 #include <linux/pm_runtime.h>
  69 #include <net/ip6_checksum.h>
  70 #include <net/tso.h>
  71
  72 #include "iwl-debug.h"
  73 #include "iwl-csr.h"
  74 #include "iwl-prph.h"
  75 #include "iwl-io.h"
  76 #include "iwl-scd.h"
  77 #include "iwl-op-mode.h"
  78 #include "internal.h"
  79 #include "fw/api/tx.h"
  80
  81 #define IWL_TX_CRC_SIZE 4
  82 #define IWL_TX_DELIMITER_SIZE 4
  83
  84 /*************** DMA-QUEUE-GENERAL-FUNCTIONS  *****
  85  * DMA services
  86  *
  87  * Theory of operation
  88  *
  89  * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  90  * of buffer descriptors, each of which points to one or more data buffers for
  91  * the device to read from or fill.  Driver and device exchange status of each
  92  * queue via "read" and "write" pointers.  Driver keeps minimum of 2 empty
  93  * entries in each circular buffer, to protect against confusing empty and full
  94  * queue states.
  95  *
  96  * The device reads or writes the data in the queues via the device's several
  97  * DMA/FIFO channels.  Each queue is mapped to a single DMA channel.
  98  *
  99  * For Tx queue, there are low mark and high mark limits. If, after queuing
 100  * the packet for Tx, free space become < low mark, Tx queue stopped. When
 101  * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
 102  * Tx queue resumed.
 103  *
 104  ***************************************************/
 105
 106 int iwl_queue_space(struct iwl_trans *trans, const struct iwl_txq *q)
 107 {
 108         unsigned int max;
 109         unsigned int used;
 110
 111         /*
 112          * To avoid ambiguity between empty and completely full queues, there
 113          * should always be less than max_tfd_queue_size elements in the queue.
 114          * If q->n_window is smaller than max_tfd_queue_size, there is no need
 115          * to reserve any queue entries for this purpose.
 116          */
 117         if (q->n_window < trans->cfg->base_params->max_tfd_queue_size)
 118                 max = q->n_window;
 119         else
 120                 max = trans->cfg->base_params->max_tfd_queue_size - 1;
 121
 122         /*
 123          * max_tfd_queue_size is a power of 2, so the following is equivalent to
 124          * modulo by max_tfd_queue_size and is well defined.
 125          */
 126         used = (q->write_ptr - q->read_ptr) &
 127                 (trans->cfg->base_params->max_tfd_queue_size - 1);
 128
 129         if (WARN_ON(used > max))
 130                 return 0;
 131
 132         return max - used;
 133 }
 134
 135 /*
 136  * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
 137  */
 138 static int iwl_queue_init(struct iwl_txq *q, int slots_num)
 139 {
 140         q->n_window = slots_num;
 141
 142         /* slots_num must be power-of-two size, otherwise
 143          * iwl_pcie_get_cmd_index is broken. */
 144         if (WARN_ON(!is_power_of_2(slots_num)))
 145                 return -EINVAL;
 146
 147         q->low_mark = q->n_window / 4;
 148         if (q->low_mark < 4)
 149                 q->low_mark = 4;
 150
 151         q->high_mark = q->n_window / 8;
 152         if (q->high_mark < 2)
 153                 q->high_mark = 2;
 154
 155         q->write_ptr = 0;
 156         q->read_ptr = 0;
 157
 158         return 0;
 159 }
 160
 161 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
 162                            struct iwl_dma_ptr *ptr, size_t size)
 163 {
 164         if (WARN_ON(ptr->addr))
 165                 return -EINVAL;
 166
 167         ptr->addr = dma_alloc_coherent(trans->dev, size,
 168                                        &ptr->dma, GFP_KERNEL);
 169         if (!ptr->addr)
 170                 return -ENOMEM;
 171         ptr->size = size;
 172         return 0;
 173 }
 174
 175 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr)
 176 {
 177         if (unlikely(!ptr->addr))
 178                 return;
 179
 180         dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
 181         memset(ptr, 0, sizeof(*ptr));
 182 }
 183
 184 static void iwl_pcie_txq_stuck_timer(struct timer_list *t)
 185 {
 186         struct iwl_txq *txq = from_timer(txq, t, stuck_timer);
 187         struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
 188         struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
 189
 190         spin_lock(&txq->lock);
 191         /* check if triggered erroneously */
 192         if (txq->read_ptr == txq->write_ptr) {
 193                 spin_unlock(&txq->lock);
 194                 return;
 195         }
 196         spin_unlock(&txq->lock);
 197
 198         iwl_trans_pcie_log_scd_error(trans, txq);
 199
 200         iwl_force_nmi(trans);
 201 }
 202
 203 /*
 204  * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
 205  */
 206 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
 207                                              struct iwl_txq *txq, u16 byte_cnt,
 208                                              int num_tbs)
 209 {
 210         struct iwlagn_scd_bc_tbl *scd_bc_tbl;
 211         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 212         int write_ptr = txq->write_ptr;
 213         int txq_id = txq->id;
 214         u8 sec_ctl = 0;
 215         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
 216         __le16 bc_ent;
 217         struct iwl_tx_cmd *tx_cmd =
 218                 (void *)txq->entries[txq->write_ptr].cmd->payload;
 219         u8 sta_id = tx_cmd->sta_id;
 220
 221         scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
 222
 223         sec_ctl = tx_cmd->sec_ctl;
 224
 225         switch (sec_ctl & TX_CMD_SEC_MSK) {
 226         case TX_CMD_SEC_CCM:
 227                 len += IEEE80211_CCMP_MIC_LEN;
 228                 break;
 229         case TX_CMD_SEC_TKIP:
 230                 len += IEEE80211_TKIP_ICV_LEN;
 231                 break;
 232         case TX_CMD_SEC_WEP:
 233                 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
 234                 break;
 235         }
 236         if (trans_pcie->bc_table_dword)
 237                 len = DIV_ROUND_UP(len, 4);
 238
 239         if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX))
 240                 return;
 241
 242         bc_ent = cpu_to_le16(len | (sta_id << 12));
 243
 244         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
 245
 246         if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 247                 scd_bc_tbl[txq_id].
 248                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
 249 }
 250
 251 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
 252                                             struct iwl_txq *txq)
 253 {
 254         struct iwl_trans_pcie *trans_pcie =
 255                 IWL_TRANS_GET_PCIE_TRANS(trans);
 256         struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
 257         int txq_id = txq->id;
 258         int read_ptr = txq->read_ptr;
 259         u8 sta_id = 0;
 260         __le16 bc_ent;
 261         struct iwl_tx_cmd *tx_cmd =
 262                 (void *)txq->entries[read_ptr].cmd->payload;
 263
 264         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
 265
 266         if (txq_id != trans_pcie->cmd_queue)
 267                 sta_id = tx_cmd->sta_id;
 268
 269         bc_ent = cpu_to_le16(1 | (sta_id << 12));
 270
 271         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
 272
 273         if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
 274                 scd_bc_tbl[txq_id].
 275                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
 276 }
 277
 278 /*
 279  * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
 280  */
 281 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
 282                                     struct iwl_txq *txq)
 283 {
 284         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 285         u32 reg = 0;
 286         int txq_id = txq->id;
 287
 288         lockdep_assert_held(&txq->lock);
 289
 290         /*
 291          * explicitly wake up the NIC if:
 292          * 1. shadow registers aren't enabled
 293          * 2. NIC is woken up for CMD regardless of shadow outside this function
 294          * 3. there is a chance that the NIC is asleep
 295          */
 296         if (!trans->cfg->base_params->shadow_reg_enable &&
 297             txq_id != trans_pcie->cmd_queue &&
 298             test_bit(STATUS_TPOWER_PMI, &trans->status)) {
 299                 /*
 300                  * wake up nic if it's powered down ...
 301                  * uCode will wake up, and interrupt us again, so next
 302                  * time we'll skip this part.
 303                  */
 304                 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 305
 306                 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 307                         IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
 308                                        txq_id, reg);
 309                         iwl_set_bit(trans, CSR_GP_CNTRL,
 310                                     BIT(trans->cfg->csr->flag_mac_access_req));
 311                         txq->need_update = true;
 312                         return;
 313                 }
 314         }
 315
 316         /*
 317          * if not in power-save mode, uCode will never sleep when we're
 318          * trying to tx (during RFKILL, we're not trying to tx).
 319          */
 320         IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr);
 321         if (!txq->block)
 322                 iwl_write32(trans, HBUS_TARG_WRPTR,
 323                             txq->write_ptr | (txq_id << 8));
 324 }
 325
 326 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
 327 {
 328         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 329         int i;
 330
 331         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
 332                 struct iwl_txq *txq = trans_pcie->txq[i];
 333
 334                 if (!test_bit(i, trans_pcie->queue_used))
 335                         continue;
 336
 337                 spin_lock_bh(&txq->lock);
 338                 if (txq->need_update) {
 339                         iwl_pcie_txq_inc_wr_ptr(trans, txq);
 340                         txq->need_update = false;
 341                 }
 342                 spin_unlock_bh(&txq->lock);
 343         }
 344 }
 345
 346 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_trans *trans,
 347                                                   void *_tfd, u8 idx)
 348 {
 349
 350         if (trans->cfg->use_tfh) {
 351                 struct iwl_tfh_tfd *tfd = _tfd;
 352                 struct iwl_tfh_tb *tb = &tfd->tbs[idx];
 353
 354                 return (dma_addr_t)(le64_to_cpu(tb->addr));
 355         } else {
 356                 struct iwl_tfd *tfd = _tfd;
 357                 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 358                 dma_addr_t addr = get_unaligned_le32(&tb->lo);
 359                 dma_addr_t hi_len;
 360
 361                 if (sizeof(dma_addr_t) <= sizeof(u32))
 362                         return addr;
 363
 364                 hi_len = le16_to_cpu(tb->hi_n_len) & 0xF;
 365
 366                 /*
 367                  * shift by 16 twice to avoid warnings on 32-bit
 368                  * (where this code never runs anyway due to the
 369                  * if statement above)
 370                  */
 371                 return addr | ((hi_len << 16) << 16);
 372         }
 373 }
 374
 375 static inline void iwl_pcie_tfd_set_tb(struct iwl_trans *trans, void *tfd,
 376                                        u8 idx, dma_addr_t addr, u16 len)
 377 {
 378         struct iwl_tfd *tfd_fh = (void *)tfd;
 379         struct iwl_tfd_tb *tb = &tfd_fh->tbs[idx];
 380
 381         u16 hi_n_len = len << 4;
 382
 383         put_unaligned_le32(addr, &tb->lo);
 384         hi_n_len |= iwl_get_dma_hi_addr(addr);
 385
 386         tb->hi_n_len = cpu_to_le16(hi_n_len);
 387
 388         tfd_fh->num_tbs = idx + 1;
 389 }
 390
 391 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_trans *trans, void *_tfd)
 392 {
 393         if (trans->cfg->use_tfh) {
 394                 struct iwl_tfh_tfd *tfd = _tfd;
 395
 396                 return le16_to_cpu(tfd->num_tbs) & 0x1f;
 397         } else {
 398                 struct iwl_tfd *tfd = _tfd;
 399
 400                 return tfd->num_tbs & 0x1f;
 401         }
 402 }
 403
 404 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
 405                                struct iwl_cmd_meta *meta,
 406                                struct iwl_txq *txq, int index)
 407 {
 408         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 409         int i, num_tbs;
 410         void *tfd = iwl_pcie_get_tfd(trans, txq, index);
 411
 412         /* Sanity check on number of chunks */
 413         num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd);
 414
 415         if (num_tbs > trans_pcie->max_tbs) {
 416                 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
 417                 /* @todo issue fatal error, it is quite serious situation */
 418                 return;
 419         }
 420
 421         /* first TB is never freed - it's the bidirectional DMA data */
 422
 423         for (i = 1; i < num_tbs; i++) {
 424                 if (meta->tbs & BIT(i))
 425                         dma_unmap_page(trans->dev,
 426                                        iwl_pcie_tfd_tb_get_addr(trans, tfd, i),
 427                                        iwl_pcie_tfd_tb_get_len(trans, tfd, i),
 428                                        DMA_TO_DEVICE);
 429                 else
 430                         dma_unmap_single(trans->dev,
 431                                          iwl_pcie_tfd_tb_get_addr(trans, tfd,
 432                                                                   i),
 433                                          iwl_pcie_tfd_tb_get_len(trans, tfd,
 434                                                                  i),
 435                                          DMA_TO_DEVICE);
 436         }
 437
 438         if (trans->cfg->use_tfh) {
 439                 struct iwl_tfh_tfd *tfd_fh = (void *)tfd;
 440
 441                 tfd_fh->num_tbs = 0;
 442         } else {
 443                 struct iwl_tfd *tfd_fh = (void *)tfd;
 444
 445                 tfd_fh->num_tbs = 0;
 446         }
 447
 448 }
 449
 450 /*
 451  * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 452  * @trans - transport private data
 453  * @txq - tx queue
 454  * @dma_dir - the direction of the DMA mapping
 455  *
 456  * Does NOT advance any TFD circular buffer read/write indexes
 457  * Does NOT free the TFD itself (which is within circular buffer)
 458  */
 459 void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
 460 {
 461         /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
 462          * idx is bounded by n_window
 463          */
 464         int rd_ptr = txq->read_ptr;
 465         int idx = iwl_pcie_get_cmd_index(txq, rd_ptr);
 466
 467         lockdep_assert_held(&txq->lock);
 468
 469         /* We have only q->n_window txq->entries, but we use
 470          * TFD_QUEUE_SIZE_MAX tfds
 471          */
 472         iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, txq, rd_ptr);
 473
 474         /* free SKB */
 475         if (txq->entries) {
 476                 struct sk_buff *skb;
 477
 478                 skb = txq->entries[idx].skb;
 479
 480                 /* Can be called from irqs-disabled context
 481                  * If skb is not NULL, it means that the whole queue is being
 482                  * freed and that the queue is not empty - free the skb
 483                  */
 484                 if (skb) {
 485                         iwl_op_mode_free_skb(trans->op_mode, skb);
 486                         txq->entries[idx].skb = NULL;
 487                 }
 488         }
 489 }
 490
 491 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
 492                                   dma_addr_t addr, u16 len, bool reset)
 493 {
 494         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 495         void *tfd;
 496         u32 num_tbs;
 497
 498         tfd = txq->tfds + trans_pcie->tfd_size * txq->write_ptr;
 499
 500         if (reset)
 501                 memset(tfd, 0, trans_pcie->tfd_size);
 502
 503         num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd);
 504
 505         /* Each TFD can point to a maximum max_tbs Tx buffers */
 506         if (num_tbs >= trans_pcie->max_tbs) {
 507                 IWL_ERR(trans, "Error can not send more than %d chunks\n",
 508                         trans_pcie->max_tbs);
 509                 return -EINVAL;
 510         }
 511
 512         if (WARN(addr & ~IWL_TX_DMA_MASK,
 513                  "Unaligned address = %llx\n", (unsigned long long)addr))
 514                 return -EINVAL;
 515
 516         iwl_pcie_tfd_set_tb(trans, tfd, num_tbs, addr, len);
 517
 518         return num_tbs;
 519 }
 520
 521 int iwl_pcie_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq,
 522                        int slots_num, bool cmd_queue)
 523 {
 524         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 525         size_t tfd_sz = trans_pcie->tfd_size *
 526                 trans->cfg->base_params->max_tfd_queue_size;
 527         size_t tb0_buf_sz;
 528         int i;
 529
 530         if (WARN_ON(txq->entries || txq->tfds))
 531                 return -EINVAL;
 532
 533         if (trans->cfg->use_tfh)
 534                 tfd_sz = trans_pcie->tfd_size * slots_num;
 535
 536         timer_setup(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, 0);
 537         txq->trans_pcie = trans_pcie;
 538
 539         txq->n_window = slots_num;
 540
 541         txq->entries = kcalloc(slots_num,
 542                                sizeof(struct iwl_pcie_txq_entry),
 543                                GFP_KERNEL);
 544
 545         if (!txq->entries)
 546                 goto error;
 547
 548         if (cmd_queue)
 549                 for (i = 0; i < slots_num; i++) {
 550                         txq->entries[i].cmd =
 551                                 kmalloc(sizeof(struct iwl_device_cmd),
 552                                         GFP_KERNEL);
 553                         if (!txq->entries[i].cmd)
 554                                 goto error;
 555                 }
 556
 557         /* Circular buffer of transmit frame descriptors (TFDs),
 558          * shared with device */
 559         txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
 560                                        &txq->dma_addr, GFP_KERNEL);
 561         if (!txq->tfds)
 562                 goto error;
 563
 564         BUILD_BUG_ON(IWL_FIRST_TB_SIZE_ALIGN != sizeof(*txq->first_tb_bufs));
 565
 566         tb0_buf_sz = sizeof(*txq->first_tb_bufs) * slots_num;
 567
 568         txq->first_tb_bufs = dma_alloc_coherent(trans->dev, tb0_buf_sz,
 569                                               &txq->first_tb_dma,
 570                                               GFP_KERNEL);
 571         if (!txq->first_tb_bufs)
 572                 goto err_free_tfds;
 573
 574         return 0;
 575 err_free_tfds:
 576         dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->dma_addr);
 577 error:
 578         if (txq->entries && cmd_queue)
 579                 for (i = 0; i < slots_num; i++)
 580                         kfree(txq->entries[i].cmd);
 581         kfree(txq->entries);
 582         txq->entries = NULL;
 583
 584         return -ENOMEM;
 585
 586 }
 587
 588 int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
 589                       int slots_num, bool cmd_queue)
 590 {
 591         int ret;
 592         u32 tfd_queue_max_size = trans->cfg->base_params->max_tfd_queue_size;
 593
 594         txq->need_update = false;
 595
 596         /* max_tfd_queue_size must be power-of-two size, otherwise
 597          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 598         if (WARN_ONCE(tfd_queue_max_size & (tfd_queue_max_size - 1),
 599                       "Max tfd queue size must be a power of two, but is %d",
 600                       tfd_queue_max_size))
 601                 return -EINVAL;
 602
 603         /* Initialize queue's high/low-water marks, and head/tail indexes */
 604         ret = iwl_queue_init(txq, slots_num);
 605         if (ret)
 606                 return ret;
 607
 608         spin_lock_init(&txq->lock);
 609
 610         if (cmd_queue) {
 611                 static struct lock_class_key iwl_pcie_cmd_queue_lock_class;
 612
 613                 lockdep_set_class(&txq->lock, &iwl_pcie_cmd_queue_lock_class);
 614         }
 615
 616         __skb_queue_head_init(&txq->overflow_q);
 617
 618         return 0;
 619 }
 620
 621 void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie,
 622                             struct sk_buff *skb)
 623 {
 624         struct page **page_ptr;
 625
 626         page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs);
 627
 628         if (*page_ptr) {
 629                 __free_page(*page_ptr);
 630                 *page_ptr = NULL;
 631         }
 632 }
 633
 634 static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
 635 {
 636         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 637
 638         lockdep_assert_held(&trans_pcie->reg_lock);
 639
 640         if (trans_pcie->ref_cmd_in_flight) {
 641                 trans_pcie->ref_cmd_in_flight = false;
 642                 IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n");
 643                 iwl_trans_unref(trans);
 644         }
 645
 646         if (!trans->cfg->base_params->apmg_wake_up_wa)
 647                 return;
 648         if (WARN_ON(!trans_pcie->cmd_hold_nic_awake))
 649                 return;
 650
 651         trans_pcie->cmd_hold_nic_awake = false;
 652         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 653                                    BIT(trans->cfg->csr->flag_mac_access_req));
 654 }
 655
 656 /*
 657  * iwl_pcie_txq_unmap -  Unmap any remaining DMA mappings and free skb's
 658  */
 659 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
 660 {
 661         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 662         struct iwl_txq *txq = trans_pcie->txq[txq_id];
 663
 664         spin_lock_bh(&txq->lock);
 665         while (txq->write_ptr != txq->read_ptr) {
 666                 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
 667                                    txq_id, txq->read_ptr);
 668
 669                 if (txq_id != trans_pcie->cmd_queue) {
 670                         struct sk_buff *skb = txq->entries[txq->read_ptr].skb;
 671
 672                         if (WARN_ON_ONCE(!skb))
 673                                 continue;
 674
 675                         iwl_pcie_free_tso_page(trans_pcie, skb);
 676                 }
 677                 iwl_pcie_txq_free_tfd(trans, txq);
 678                 txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr);
 679
 680                 if (txq->read_ptr == txq->write_ptr) {
 681                         unsigned long flags;
 682
 683                         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
 684                         if (txq_id != trans_pcie->cmd_queue) {
 685                                 IWL_DEBUG_RPM(trans, "Q %d - last tx freed\n",
 686                                               txq->id);
 687                                 iwl_trans_unref(trans);
 688                         } else {
 689                                 iwl_pcie_clear_cmd_in_flight(trans);
 690                         }
 691                         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
 692                 }
 693         }
 694
 695         while (!skb_queue_empty(&txq->overflow_q)) {
 696                 struct sk_buff *skb = __skb_dequeue(&txq->overflow_q);
 697
 698                 iwl_op_mode_free_skb(trans->op_mode, skb);
 699         }
 700
 701         spin_unlock_bh(&txq->lock);
 702
 703         /* just in case - this queue may have been stopped */
 704         iwl_wake_queue(trans, txq);
 705 }
 706
 707 /*
 708  * iwl_pcie_txq_free - Deallocate DMA queue.
 709  * @txq: Transmit queue to deallocate.
 710  *
 711  * Empty queue by removing and destroying all BD's.
 712  * Free all buffers.
 713  * 0-fill, but do not free "txq" descriptor structure.
 714  */
 715 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
 716 {
 717         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 718         struct iwl_txq *txq = trans_pcie->txq[txq_id];
 719         struct device *dev = trans->dev;
 720         int i;
 721
 722         if (WARN_ON(!txq))
 723                 return;
 724
 725         iwl_pcie_txq_unmap(trans, txq_id);
 726
 727         /* De-alloc array of command/tx buffers */
 728         if (txq_id == trans_pcie->cmd_queue)
 729                 for (i = 0; i < txq->n_window; i++) {
 730                         kzfree(txq->entries[i].cmd);
 731                         kzfree(txq->entries[i].free_buf);
 732                 }
 733
 734         /* De-alloc circular buffer of TFDs */
 735         if (txq->tfds) {
 736                 dma_free_coherent(dev,
 737                                   trans_pcie->tfd_size *
 738                                   trans->cfg->base_params->max_tfd_queue_size,
 739                                   txq->tfds, txq->dma_addr);
 740                 txq->dma_addr = 0;
 741                 txq->tfds = NULL;
 742
 743                 dma_free_coherent(dev,
 744                                   sizeof(*txq->first_tb_bufs) * txq->n_window,
 745                                   txq->first_tb_bufs, txq->first_tb_dma);
 746         }
 747
 748         kfree(txq->entries);
 749         txq->entries = NULL;
 750
 751         del_timer_sync(&txq->stuck_timer);
 752
 753         /* 0-fill queue descriptor structure */
 754         memset(txq, 0, sizeof(*txq));
 755 }
 756
 757 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
 758 {
 759         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 760         int nq = trans->cfg->base_params->num_of_queues;
 761         int chan;
 762         u32 reg_val;
 763         int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
 764                                 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
 765
 766         /* make sure all queue are not stopped/used */
 767         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
 768         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
 769
 770         trans_pcie->scd_base_addr =
 771                 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
 772
 773         WARN_ON(scd_base_addr != 0 &&
 774                 scd_base_addr != trans_pcie->scd_base_addr);
 775
 776         /* reset context data, TX status and translation data */
 777         iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
 778                                    SCD_CONTEXT_MEM_LOWER_BOUND,
 779                             NULL, clear_dwords);
 780
 781         iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
 782                        trans_pcie->scd_bc_tbls.dma >> 10);
 783
 784         /* The chain extension of the SCD doesn't work well. This feature is
 785          * enabled by default by the HW, so we need to disable it manually.
 786          */
 787         if (trans->cfg->base_params->scd_chain_ext_wa)
 788                 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
 789
 790         iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
 791                                 trans_pcie->cmd_fifo,
 792                                 trans_pcie->cmd_q_wdg_timeout);
 793
 794         /* Activate all Tx DMA/FIFO channels */
 795         iwl_scd_activate_fifos(trans);
 796
 797         /* Enable DMA channel */
 798         for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
 799                 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 800                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 801                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 802
 803         /* Update FH chicken bits */
 804         reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
 805         iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
 806                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 807
 808         /* Enable L1-Active */
 809         if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000)
 810                 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 811                                     APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 812 }
 813
 814 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
 815 {
 816         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 817         int txq_id;
 818
 819         /*
 820          * we should never get here in gen2 trans mode return early to avoid
 821          * having invalid accesses
 822          */
 823         if (WARN_ON_ONCE(trans->cfg->gen2))
 824                 return;
 825
 826         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 827              txq_id++) {
 828                 struct iwl_txq *txq = trans_pcie->txq[txq_id];
 829                 if (trans->cfg->use_tfh)
 830                         iwl_write_direct64(trans,
 831                                            FH_MEM_CBBC_QUEUE(trans, txq_id),
 832                                            txq->dma_addr);
 833                 else
 834                         iwl_write_direct32(trans,
 835                                            FH_MEM_CBBC_QUEUE(trans, txq_id),
 836                                            txq->dma_addr >> 8);
 837                 iwl_pcie_txq_unmap(trans, txq_id);
 838                 txq->read_ptr = 0;
 839                 txq->write_ptr = 0;
 840         }
 841
 842         /* Tell NIC where to find the "keep warm" buffer */
 843         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 844                            trans_pcie->kw.dma >> 4);
 845
 846         /*
 847          * Send 0 as the scd_base_addr since the device may have be reset
 848          * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
 849          * contain garbage.
 850          */
 851         iwl_pcie_tx_start(trans, 0);
 852 }
 853
 854 static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
 855 {
 856         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 857         unsigned long flags;
 858         int ch, ret;
 859         u32 mask = 0;
 860
 861         spin_lock(&trans_pcie->irq_lock);
 862
 863         if (!iwl_trans_grab_nic_access(trans, &flags))
 864                 goto out;
 865
 866         /* Stop each Tx DMA channel */
 867         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
 868                 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
 869                 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch);
 870         }
 871
 872         /* Wait for DMA channels to be idle */
 873         ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000);
 874         if (ret < 0)
 875                 IWL_ERR(trans,
 876                         "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
 877                         ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
 878
 879         iwl_trans_release_nic_access(trans, &flags);
 880
 881 out:
 882         spin_unlock(&trans_pcie->irq_lock);
 883 }
 884
 885 /*
 886  * iwl_pcie_tx_stop - Stop all Tx DMA channels
 887  */
 888 int iwl_pcie_tx_stop(struct iwl_trans *trans)
 889 {
 890         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 891         int txq_id;
 892
 893         /* Turn off all Tx DMA fifos */
 894         iwl_scd_deactivate_fifos(trans);
 895
 896         /* Turn off all Tx DMA channels */
 897         iwl_pcie_tx_stop_fh(trans);
 898
 899         /*
 900          * This function can be called before the op_mode disabled the
 901          * queues. This happens when we have an rfkill interrupt.
 902          * Since we stop Tx altogether - mark the queues as stopped.
 903          */
 904         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
 905         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
 906
 907         /* This can happen: start_hw, stop_device */
 908         if (!trans_pcie->txq_memory)
 909                 return 0;
 910
 911         /* Unmap DMA from host system and free skb's */
 912         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 913              txq_id++)
 914                 iwl_pcie_txq_unmap(trans, txq_id);
 915
 916         return 0;
 917 }
 918
 919 /*
 920  * iwl_trans_tx_free - Free TXQ Context
 921  *
 922  * Destroy all TX DMA queues and structures
 923  */
 924 void iwl_pcie_tx_free(struct iwl_trans *trans)
 925 {
 926         int txq_id;
 927         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 928
 929         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
 930
 931         /* Tx queues */
 932         if (trans_pcie->txq_memory) {
 933                 for (txq_id = 0;
 934                      txq_id < trans->cfg->base_params->num_of_queues;
 935                      txq_id++) {
 936                         iwl_pcie_txq_free(trans, txq_id);
 937                         trans_pcie->txq[txq_id] = NULL;
 938                 }
 939         }
 940
 941         kfree(trans_pcie->txq_memory);
 942         trans_pcie->txq_memory = NULL;
 943
 944         iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
 945
 946         iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 947 }
 948
 949 /*
 950  * iwl_pcie_tx_alloc - allocate TX context
 951  * Allocate all Tx DMA structures and initialize them
 952  */
 953 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
 954 {
 955         int ret;
 956         int txq_id, slots_num;
 957         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 958         u16 bc_tbls_size = trans->cfg->base_params->num_of_queues;
 959
 960         bc_tbls_size *= (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) ?
 961                 sizeof(struct iwl_gen3_bc_tbl) :
 962                 sizeof(struct iwlagn_scd_bc_tbl);
 963
 964         /*It is not allowed to alloc twice, so warn when this happens.
 965          * We cannot rely on the previous allocation, so free and fail */
 966         if (WARN_ON(trans_pcie->txq_memory)) {
 967                 ret = -EINVAL;
 968                 goto error;
 969         }
 970
 971         ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 972                                      bc_tbls_size);
 973         if (ret) {
 974                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 975                 goto error;
 976         }
 977
 978         /* Alloc keep-warm buffer */
 979         ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 980         if (ret) {
 981                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 982                 goto error;
 983         }
 984
 985         trans_pcie->txq_memory = kcalloc(trans->cfg->base_params->num_of_queues,
 986                                          sizeof(struct iwl_txq), GFP_KERNEL);
 987         if (!trans_pcie->txq_memory) {
 988                 IWL_ERR(trans, "Not enough memory for txq\n");
 989                 ret = -ENOMEM;
 990                 goto error;
 991         }
 992
 993         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 994         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 995              txq_id++) {
 996                 bool cmd_queue = (txq_id == trans_pcie->cmd_queue);
 997
 998                 if (cmd_queue)
 999                         slots_num = max_t(u32, TFD_CMD_SLOTS,
1000                                           trans->cfg->min_txq_size);
1001                 else
1002                         slots_num = TFD_TX_CMD_SLOTS;
1003                 trans_pcie->txq[txq_id] = &trans_pcie->txq_memory[txq_id];
1004                 ret = iwl_pcie_txq_alloc(trans, trans_pcie->txq[txq_id],
1005                                          slots_num, cmd_queue);
1006                 if (ret) {
1007                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
1008                         goto error;
1009                 }
1010                 trans_pcie->txq[txq_id]->id = txq_id;
1011         }
1012
1013         return 0;
1014
1015 error:
1016         iwl_pcie_tx_free(trans);
1017
1018         return ret;
1019 }
1020
1021 int iwl_pcie_tx_init(struct iwl_trans *trans)
1022 {
1023         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1024         int ret;
1025         int txq_id, slots_num;
1026         bool alloc = false;
1027
1028         if (!trans_pcie->txq_memory) {
1029                 ret = iwl_pcie_tx_alloc(trans);
1030                 if (ret)
1031                         goto error;
1032                 alloc = true;
1033         }
1034
1035         spin_lock(&trans_pcie->irq_lock);
1036
1037         /* Turn off all Tx DMA fifos */
1038         iwl_scd_deactivate_fifos(trans);
1039
1040         /* Tell NIC where to find the "keep warm" buffer */
1041         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
1042                            trans_pcie->kw.dma >> 4);
1043
1044         spin_unlock(&trans_pcie->irq_lock);
1045
1046         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
1047         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
1048              txq_id++) {
1049                 bool cmd_queue = (txq_id == trans_pcie->cmd_queue);
1050
1051                 if (cmd_queue)
1052                         slots_num = max_t(u32, TFD_CMD_SLOTS,
1053                                           trans->cfg->min_txq_size);
1054                 else
1055                         slots_num = TFD_TX_CMD_SLOTS;
1056                 ret = iwl_pcie_txq_init(trans, trans_pcie->txq[txq_id],
1057                                         slots_num, cmd_queue);
1058                 if (ret) {
1059                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
1060                         goto error;
1061                 }
1062
1063                 /*
1064                  * Tell nic where to find circular buffer of TFDs for a
1065                  * given Tx queue, and enable the DMA channel used for that
1066                  * queue.
1067                  * Circular buffer (TFD queue in DRAM) physical base address
1068                  */
1069                 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id),
1070                                    trans_pcie->txq[txq_id]->dma_addr >> 8);
1071         }
1072
1073         iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);
1074         if (trans->cfg->base_params->num_of_queues > 20)
1075                 iwl_set_bits_prph(trans, SCD_GP_CTRL,
1076                                   SCD_GP_CTRL_ENABLE_31_QUEUES);
1077
1078         return 0;
1079 error:
1080         /*Upon error, free only if we allocated something */
1081         if (alloc)
1082                 iwl_pcie_tx_free(trans);
1083         return ret;
1084 }
1085
1086 static inline void iwl_pcie_txq_progress(struct iwl_txq *txq)
1087 {
1088         lockdep_assert_held(&txq->lock);
1089
1090         if (!txq->wd_timeout)
1091                 return;
1092
1093         /*
1094          * station is asleep and we send data - that must
1095          * be uAPSD or PS-Poll. Don't rearm the timer.
1096          */
1097         if (txq->frozen)
1098                 return;
1099
1100         /*
1101          * if empty delete timer, otherwise move timer forward
1102          * since we're making progress on this queue
1103          */
1104         if (txq->read_ptr == txq->write_ptr)
1105                 del_timer(&txq->stuck_timer);
1106         else
1107                 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1108 }
1109
1110 /* Frees buffers until index _not_ inclusive */
1111 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1112                             struct sk_buff_head *skbs)
1113 {
1114         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1115         struct iwl_txq *txq = trans_pcie->txq[txq_id];
1116         int tfd_num = iwl_pcie_get_cmd_index(txq, ssn);
1117         int read_ptr = iwl_pcie_get_cmd_index(txq, txq->read_ptr);
1118         int last_to_free;
1119
1120         /* This function is not meant to release cmd queue*/
1121         if (WARN_ON(txq_id == trans_pcie->cmd_queue))
1122                 return;
1123
1124         spin_lock_bh(&txq->lock);
1125
1126         if (!test_bit(txq_id, trans_pcie->queue_used)) {
1127                 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
1128                                     txq_id, ssn);
1129                 goto out;
1130         }
1131
1132         if (read_ptr == tfd_num)
1133                 goto out;
1134
1135         IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1136                            txq_id, txq->read_ptr, tfd_num, ssn);
1137
1138         /*Since we free until index _not_ inclusive, the one before index is
1139          * the last we will free. This one must be used */
1140         last_to_free = iwl_queue_dec_wrap(trans, tfd_num);
1141
1142         if (!iwl_queue_used(txq, last_to_free)) {
1143                 IWL_ERR(trans,
1144                         "%s: Read index for txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
1145                         __func__, txq_id, last_to_free,
1146                         trans->cfg->base_params->max_tfd_queue_size,
1147                         txq->write_ptr, txq->read_ptr);
1148                 goto out;
1149         }
1150
1151         if (WARN_ON(!skb_queue_empty(skbs)))
1152                 goto out;
1153
1154         for (;
1155              read_ptr != tfd_num;
1156              txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr),
1157              read_ptr = iwl_pcie_get_cmd_index(txq, txq->read_ptr)) {
1158                 struct sk_buff *skb = txq->entries[read_ptr].skb;
1159
1160                 if (WARN_ON_ONCE(!skb))
1161                         continue;
1162
1163                 iwl_pcie_free_tso_page(trans_pcie, skb);
1164
1165                 __skb_queue_tail(skbs, skb);
1166
1167                 txq->entries[read_ptr].skb = NULL;
1168
1169                 if (!trans->cfg->use_tfh)
1170                         iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
1171
1172                 iwl_pcie_txq_free_tfd(trans, txq);
1173         }
1174
1175         iwl_pcie_txq_progress(txq);
1176
1177         if (iwl_queue_space(trans, txq) > txq->low_mark &&
1178             test_bit(txq_id, trans_pcie->queue_stopped)) {
1179                 struct sk_buff_head overflow_skbs;
1180
1181                 __skb_queue_head_init(&overflow_skbs);
1182                 skb_queue_splice_init(&txq->overflow_q, &overflow_skbs);
1183
1184                 /*
1185                  * We are going to transmit from the overflow queue.
1186                  * Remember this state so that wait_for_txq_empty will know we
1187                  * are adding more packets to the TFD queue. It cannot rely on
1188                  * the state of &txq->overflow_q, as we just emptied it, but
1189                  * haven't TXed the content yet.
1190                  */
1191                 txq->overflow_tx = true;
1192
1193                 /*
1194                  * This is tricky: we are in reclaim path which is non
1195                  * re-entrant, so noone will try to take the access the
1196                  * txq data from that path. We stopped tx, so we can't
1197                  * have tx as well. Bottom line, we can unlock and re-lock
1198                  * later.
1199                  */
1200                 spin_unlock_bh(&txq->lock);
1201
1202                 while (!skb_queue_empty(&overflow_skbs)) {
1203                         struct sk_buff *skb = __skb_dequeue(&overflow_skbs);
1204                         struct iwl_device_cmd *dev_cmd_ptr;
1205
1206                         dev_cmd_ptr = *(void **)((u8 *)skb->cb +
1207                                                  trans_pcie->dev_cmd_offs);
1208
1209                         /*
1210                          * Note that we can very well be overflowing again.
1211                          * In that case, iwl_queue_space will be small again
1212                          * and we won't wake mac80211's queue.
1213                          */
1214                         iwl_trans_tx(trans, skb, dev_cmd_ptr, txq_id);
1215                 }
1216
1217                 if (iwl_queue_space(trans, txq) > txq->low_mark)
1218                         iwl_wake_queue(trans, txq);
1219
1220                 spin_lock_bh(&txq->lock);
1221                 txq->overflow_tx = false;
1222         }
1223
1224         if (txq->read_ptr == txq->write_ptr) {
1225                 IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", txq->id);
1226                 iwl_trans_unref(trans);
1227         }
1228
1229 out:
1230         spin_unlock_bh(&txq->lock);
1231 }
1232
1233 static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans,
1234                                       const struct iwl_host_cmd *cmd)
1235 {
1236         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1237         const struct iwl_cfg *cfg = trans->cfg;
1238         int ret;
1239
1240         lockdep_assert_held(&trans_pcie->reg_lock);
1241
1242         /* Make sure the NIC is still alive in the bus */
1243         if (test_bit(STATUS_TRANS_DEAD, &trans->status))
1244                 return -ENODEV;
1245
1246         if (!(cmd->flags & CMD_SEND_IN_IDLE) &&
1247             !trans_pcie->ref_cmd_in_flight) {
1248                 trans_pcie->ref_cmd_in_flight = true;
1249                 IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n");
1250                 iwl_trans_ref(trans);
1251         }
1252
1253         /*
1254          * wake up the NIC to make sure that the firmware will see the host
1255          * command - we will let the NIC sleep once all the host commands
1256          * returned. This needs to be done only on NICs that have
1257          * apmg_wake_up_wa set.
1258          */
1259         if (cfg->base_params->apmg_wake_up_wa &&
1260             !trans_pcie->cmd_hold_nic_awake) {
1261                 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1262                                          BIT(cfg->csr->flag_mac_access_req));
1263
1264                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1265                                    BIT(cfg->csr->flag_val_mac_access_en),
1266                                    (BIT(cfg->csr->flag_mac_clock_ready) |
1267                                     CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
1268                                    15000);
1269                 if (ret < 0) {
1270                         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1271                                         BIT(cfg->csr->flag_mac_access_req));
1272                         IWL_ERR(trans, "Failed to wake NIC for hcmd\n");
1273                         return -EIO;
1274                 }
1275                 trans_pcie->cmd_hold_nic_awake = true;
1276         }
1277
1278         return 0;
1279 }
1280
1281 /*
1282  * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1283  *
1284  * When FW advances 'R' index, all entries between old and new 'R' index
1285  * need to be reclaimed. As result, some free space forms.  If there is
1286  * enough free space (> low mark), wake the stack that feeds us.
1287  */
1288 void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1289 {
1290         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1291         struct iwl_txq *txq = trans_pcie->txq[txq_id];
1292         unsigned long flags;
1293         int nfreed = 0;
1294         u16 r;
1295
1296         lockdep_assert_held(&txq->lock);
1297
1298         idx = iwl_pcie_get_cmd_index(txq, idx);
1299         r = iwl_pcie_get_cmd_index(txq, txq->read_ptr);
1300
1301         if (idx >= trans->cfg->base_params->max_tfd_queue_size ||
1302             (!iwl_queue_used(txq, idx))) {
1303                 WARN_ONCE(test_bit(txq_id, trans_pcie->queue_used),
1304                           "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1305                           __func__, txq_id, idx,
1306                           trans->cfg->base_params->max_tfd_queue_size,
1307                           txq->write_ptr, txq->read_ptr);
1308                 return;
1309         }
1310
1311         for (idx = iwl_queue_inc_wrap(trans, idx); r != idx;
1312              r = iwl_queue_inc_wrap(trans, r)) {
1313                 txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr);
1314
1315                 if (nfreed++ > 0) {
1316                         IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1317                                 idx, txq->write_ptr, r);
1318                         iwl_force_nmi(trans);
1319                 }
1320         }
1321
1322         if (txq->read_ptr == txq->write_ptr) {
1323                 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1324                 iwl_pcie_clear_cmd_in_flight(trans);
1325                 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1326         }
1327
1328         iwl_pcie_txq_progress(txq);
1329 }
1330
1331 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1332                                  u16 txq_id)
1333 {
1334         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1335         u32 tbl_dw_addr;
1336         u32 tbl_dw;
1337         u16 scd_q2ratid;
1338
1339         scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1340
1341         tbl_dw_addr = trans_pcie->scd_base_addr +
1342                         SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1343
1344         tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1345
1346         if (txq_id & 0x1)
1347                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1348         else
1349                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1350
1351         iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1352
1353         return 0;
1354 }
1355
1356 /* Receiver address (actually, Rx station's index into station table),
1357  * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1358 #define BUILD_RAxTID(sta_id, tid)       (((sta_id) << 4) + (tid))
1359
1360 bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
1361                                const struct iwl_trans_txq_scd_cfg *cfg,
1362                                unsigned int wdg_timeout)
1363 {
1364         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1365         struct iwl_txq *txq = trans_pcie->txq[txq_id];
1366         int fifo = -1;
1367         bool scd_bug = false;
1368
1369         if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1370                 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1371
1372         txq->wd_timeout = msecs_to_jiffies(wdg_timeout);
1373
1374         if (cfg) {
1375                 fifo = cfg->fifo;
1376
1377                 /* Disable the scheduler prior configuring the cmd queue */
1378                 if (txq_id == trans_pcie->cmd_queue &&
1379                     trans_pcie->scd_set_active)
1380                         iwl_scd_enable_set_active(trans, 0);
1381
1382                 /* Stop this Tx queue before configuring it */
1383                 iwl_scd_txq_set_inactive(trans, txq_id);
1384
1385                 /* Set this queue as a chain-building queue unless it is CMD */
1386                 if (txq_id != trans_pcie->cmd_queue)
1387                         iwl_scd_txq_set_chain(trans, txq_id);
1388
1389                 if (cfg->aggregate) {
1390                         u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
1391
1392                         /* Map receiver-address / traffic-ID to this queue */
1393                         iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1394
1395                         /* enable aggregations for the queue */
1396                         iwl_scd_txq_enable_agg(trans, txq_id);
1397                         txq->ampdu = true;
1398                 } else {
1399                         /*
1400                          * disable aggregations for the queue, this will also
1401                          * make the ra_tid mapping configuration irrelevant
1402                          * since it is now a non-AGG queue.
1403                          */
1404                         iwl_scd_txq_disable_agg(trans, txq_id);
1405
1406                         ssn = txq->read_ptr;
1407                 }
1408         } else {
1409                 /*
1410                  * If we need to move the SCD write pointer by steps of
1411                  * 0x40, 0x80 or 0xc0, it gets stuck. Avoids this and let
1412                  * the op_mode know by returning true later.
1413                  * Do this only in case cfg is NULL since this trick can
1414                  * be done only if we have DQA enabled which is true for mvm
1415                  * only. And mvm never sets a cfg pointer.
1416                  * This is really ugly, but this is the easiest way out for
1417                  * this sad hardware issue.
1418                  * This bug has been fixed on devices 9000 and up.
1419                  */
1420                 scd_bug = !trans->cfg->mq_rx_supported &&
1421                         !((ssn - txq->write_ptr) & 0x3f) &&
1422                         (ssn != txq->write_ptr);
1423                 if (scd_bug)
1424                         ssn++;
1425         }
1426
1427         /* Place first TFD at index corresponding to start sequence number.
1428          * Assumes that ssn_idx is valid (!= 0xFFF) */
1429         txq->read_ptr = (ssn & 0xff);
1430         txq->write_ptr = (ssn & 0xff);
1431         iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1432                            (ssn & 0xff) | (txq_id << 8));
1433
1434         if (cfg) {
1435                 u8 frame_limit = cfg->frame_limit;
1436
1437                 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1438
1439                 /* Set up Tx window size and frame limit for this queue */
1440                 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1441                                 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1442                 iwl_trans_write_mem32(trans,
1443                         trans_pcie->scd_base_addr +
1444                         SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1445                         SCD_QUEUE_CTX_REG2_VAL(WIN_SIZE, frame_limit) |
1446                         SCD_QUEUE_CTX_REG2_VAL(FRAME_LIMIT, frame_limit));
1447
1448                 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1449                 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1450                                (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1451                                (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1452                                (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1453                                SCD_QUEUE_STTS_REG_MSK);
1454
1455                 /* enable the scheduler for this queue (only) */
1456                 if (txq_id == trans_pcie->cmd_queue &&
1457                     trans_pcie->scd_set_active)
1458                         iwl_scd_enable_set_active(trans, BIT(txq_id));
1459
1460                 IWL_DEBUG_TX_QUEUES(trans,
1461                                     "Activate queue %d on FIFO %d WrPtr: %d\n",
1462                                     txq_id, fifo, ssn & 0xff);
1463         } else {
1464                 IWL_DEBUG_TX_QUEUES(trans,
1465                                     "Activate queue %d WrPtr: %d\n",
1466                                     txq_id, ssn & 0xff);
1467         }
1468
1469         return scd_bug;
1470 }
1471
1472 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
1473                                         bool shared_mode)
1474 {
1475         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1476         struct iwl_txq *txq = trans_pcie->txq[txq_id];
1477
1478         txq->ampdu = !shared_mode;
1479 }
1480
1481 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
1482                                 bool configure_scd)
1483 {
1484         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1485         u32 stts_addr = trans_pcie->scd_base_addr +
1486                         SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1487         static const u32 zero_val[4] = {};
1488
1489         trans_pcie->txq[txq_id]->frozen_expiry_remainder = 0;
1490         trans_pcie->txq[txq_id]->frozen = false;
1491
1492         /*
1493          * Upon HW Rfkill - we stop the device, and then stop the queues
1494          * in the op_mode. Just for the sake of the simplicity of the op_mode,
1495          * allow the op_mode to call txq_disable after it already called
1496          * stop_device.
1497          */
1498         if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1499                 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1500                           "queue %d not used", txq_id);
1501                 return;
1502         }
1503
1504         if (configure_scd) {
1505                 iwl_scd_txq_set_inactive(trans, txq_id);
1506
1507                 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1508                                     ARRAY_SIZE(zero_val));
1509         }
1510
1511         iwl_pcie_txq_unmap(trans, txq_id);
1512         trans_pcie->txq[txq_id]->ampdu = false;
1513
1514         IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1515 }
1516
1517 /*************** HOST COMMAND QUEUE FUNCTIONS   *****/
1518
1519 /*
1520  * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1521  * @priv: device private data point
1522  * @cmd: a pointer to the ucode command structure
1523  *
1524  * The function returns < 0 values to indicate the operation
1525  * failed. On success, it returns the index (>= 0) of command in the
1526  * command queue.
1527  */
1528 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1529                                  struct iwl_host_cmd *cmd)
1530 {
1531         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1532         struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1533         struct iwl_device_cmd *out_cmd;
1534         struct iwl_cmd_meta *out_meta;
1535         unsigned long flags;
1536         void *dup_buf = NULL;
1537         dma_addr_t phys_addr;
1538         int idx;
1539         u16 copy_size, cmd_size, tb0_size;
1540         bool had_nocopy = false;
1541         u8 group_id = iwl_cmd_groupid(cmd->id);
1542         int i, ret;
1543         u32 cmd_pos;
1544         const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1545         u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1546
1547         if (WARN(!trans->wide_cmd_header &&
1548                  group_id > IWL_ALWAYS_LONG_GROUP,
1549                  "unsupported wide command %#x\n", cmd->id))
1550                 return -EINVAL;
1551
1552         if (group_id != 0) {
1553                 copy_size = sizeof(struct iwl_cmd_header_wide);
1554                 cmd_size = sizeof(struct iwl_cmd_header_wide);
1555         } else {
1556                 copy_size = sizeof(struct iwl_cmd_header);
1557                 cmd_size = sizeof(struct iwl_cmd_header);
1558         }
1559
1560         /* need one for the header if the first is NOCOPY */
1561         BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1562
1563         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1564                 cmddata[i] = cmd->data[i];
1565                 cmdlen[i] = cmd->len[i];
1566
1567                 if (!cmd->len[i])
1568                         continue;
1569
1570                 /* need at least IWL_FIRST_TB_SIZE copied */
1571                 if (copy_size < IWL_FIRST_TB_SIZE) {
1572                         int copy = IWL_FIRST_TB_SIZE - copy_size;
1573
1574                         if (copy > cmdlen[i])
1575                                 copy = cmdlen[i];
1576                         cmdlen[i] -= copy;
1577                         cmddata[i] += copy;
1578                         copy_size += copy;
1579                 }
1580
1581                 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1582                         had_nocopy = true;
1583                         if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1584                                 idx = -EINVAL;
1585                                 goto free_dup_buf;
1586                         }
1587                 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1588                         /*
1589                          * This is also a chunk that isn't copied
1590                          * to the static buffer so set had_nocopy.
1591                          */
1592                         had_nocopy = true;
1593
1594                         /* only allowed once */
1595                         if (WARN_ON(dup_buf)) {
1596                                 idx = -EINVAL;
1597                                 goto free_dup_buf;
1598                         }
1599
1600                         dup_buf = kmemdup(cmddata[i], cmdlen[i],
1601                                           GFP_ATOMIC);
1602                         if (!dup_buf)
1603                                 return -ENOMEM;
1604                 } else {
1605                         /* NOCOPY must not be followed by normal! */
1606                         if (WARN_ON(had_nocopy)) {
1607                                 idx = -EINVAL;
1608                                 goto free_dup_buf;
1609                         }
1610                         copy_size += cmdlen[i];
1611                 }
1612                 cmd_size += cmd->len[i];
1613         }
1614
1615         /*
1616          * If any of the command structures end up being larger than
1617          * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1618          * allocated into separate TFDs, then we will need to
1619          * increase the size of the buffers.
1620          */
1621         if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1622                  "Command %s (%#x) is too large (%d bytes)\n",
1623                  iwl_get_cmd_string(trans, cmd->id),
1624                  cmd->id, copy_size)) {
1625                 idx = -EINVAL;
1626                 goto free_dup_buf;
1627         }
1628
1629         spin_lock_bh(&txq->lock);
1630
1631         if (iwl_queue_space(trans, txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1632                 spin_unlock_bh(&txq->lock);
1633
1634                 IWL_ERR(trans, "No space in command queue\n");
1635                 iwl_op_mode_cmd_queue_full(trans->op_mode);
1636                 idx = -ENOSPC;
1637                 goto free_dup_buf;
1638         }
1639
1640         idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
1641         out_cmd = txq->entries[idx].cmd;
1642         out_meta = &txq->entries[idx].meta;
1643
1644         memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1645         if (cmd->flags & CMD_WANT_SKB)
1646                 out_meta->source = cmd;
1647
1648         /* set up the header */
1649         if (group_id != 0) {
1650                 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id);
1651                 out_cmd->hdr_wide.group_id = group_id;
1652                 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id);
1653                 out_cmd->hdr_wide.length =
1654                         cpu_to_le16(cmd_size -
1655                                     sizeof(struct iwl_cmd_header_wide));
1656                 out_cmd->hdr_wide.reserved = 0;
1657                 out_cmd->hdr_wide.sequence =
1658                         cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1659                                                  INDEX_TO_SEQ(txq->write_ptr));
1660
1661                 cmd_pos = sizeof(struct iwl_cmd_header_wide);
1662                 copy_size = sizeof(struct iwl_cmd_header_wide);
1663         } else {
1664                 out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id);
1665                 out_cmd->hdr.sequence =
1666                         cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1667                                                  INDEX_TO_SEQ(txq->write_ptr));
1668                 out_cmd->hdr.group_id = 0;
1669
1670                 cmd_pos = sizeof(struct iwl_cmd_header);
1671                 copy_size = sizeof(struct iwl_cmd_header);
1672         }
1673
1674         /* and copy the data that needs to be copied */
1675         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1676                 int copy;
1677
1678                 if (!cmd->len[i])
1679                         continue;
1680
1681                 /* copy everything if not nocopy/dup */
1682                 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1683                                            IWL_HCMD_DFL_DUP))) {
1684                         copy = cmd->len[i];
1685
1686                         memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1687                         cmd_pos += copy;
1688                         copy_size += copy;
1689                         continue;
1690                 }
1691
1692                 /*
1693                  * Otherwise we need at least IWL_FIRST_TB_SIZE copied
1694                  * in total (for bi-directional DMA), but copy up to what
1695                  * we can fit into the payload for debug dump purposes.
1696                  */
1697                 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1698
1699                 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1700                 cmd_pos += copy;
1701
1702                 /* However, treat copy_size the proper way, we need it below */
1703                 if (copy_size < IWL_FIRST_TB_SIZE) {
1704                         copy = IWL_FIRST_TB_SIZE - copy_size;
1705
1706                         if (copy > cmd->len[i])
1707                                 copy = cmd->len[i];
1708                         copy_size += copy;
1709                 }
1710         }
1711
1712         IWL_DEBUG_HC(trans,
1713                      "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1714                      iwl_get_cmd_string(trans, cmd->id),
1715                      group_id, out_cmd->hdr.cmd,
1716                      le16_to_cpu(out_cmd->hdr.sequence),
1717                      cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue);
1718
1719         /* start the TFD with the minimum copy bytes */
1720         tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE);
1721         memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size);
1722         iwl_pcie_txq_build_tfd(trans, txq,
1723                                iwl_pcie_get_first_tb_dma(txq, idx),
1724                                tb0_size, true);
1725
1726         /* map first command fragment, if any remains */
1727         if (copy_size > tb0_size) {
1728                 phys_addr = dma_map_single(trans->dev,
1729                                            ((u8 *)&out_cmd->hdr) + tb0_size,
1730                                            copy_size - tb0_size,
1731                                            DMA_TO_DEVICE);
1732                 if (dma_mapping_error(trans->dev, phys_addr)) {
1733                         iwl_pcie_tfd_unmap(trans, out_meta, txq,
1734                                            txq->write_ptr);
1735                         idx = -ENOMEM;
1736                         goto out;
1737                 }
1738
1739                 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1740                                        copy_size - tb0_size, false);
1741         }
1742
1743         /* map the remaining (adjusted) nocopy/dup fragments */
1744         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1745                 const void *data = cmddata[i];
1746
1747                 if (!cmdlen[i])
1748                         continue;
1749                 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1750                                            IWL_HCMD_DFL_DUP)))
1751                         continue;
1752                 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1753                         data = dup_buf;
1754                 phys_addr = dma_map_single(trans->dev, (void *)data,
1755                                            cmdlen[i], DMA_TO_DEVICE);
1756                 if (dma_mapping_error(trans->dev, phys_addr)) {
1757                         iwl_pcie_tfd_unmap(trans, out_meta, txq,
1758                                            txq->write_ptr);
1759                         idx = -ENOMEM;
1760                         goto out;
1761                 }
1762
1763                 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
1764         }
1765
1766         BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE);
1767         out_meta->flags = cmd->flags;
1768         if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1769                 kzfree(txq->entries[idx].free_buf);
1770         txq->entries[idx].free_buf = dup_buf;
1771
1772         trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide);
1773
1774         /* start timer if queue currently empty */
1775         if (txq->read_ptr == txq->write_ptr && txq->wd_timeout)
1776                 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1777
1778         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1779         ret = iwl_pcie_set_cmd_in_flight(trans, cmd);
1780         if (ret < 0) {
1781                 idx = ret;
1782                 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1783                 goto out;
1784         }
1785
1786         /* Increment and update queue's write index */
1787         txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr);
1788         iwl_pcie_txq_inc_wr_ptr(trans, txq);
1789
1790         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1791
1792  out:
1793         spin_unlock_bh(&txq->lock);
1794  free_dup_buf:
1795         if (idx < 0)
1796                 kfree(dup_buf);
1797         return idx;
1798 }
1799
1800 /*
1801  * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1802  * @rxb: Rx buffer to reclaim
1803  */
1804 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1805                             struct iwl_rx_cmd_buffer *rxb)
1806 {
1807         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1808         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1809         u8 group_id;
1810         u32 cmd_id;
1811         int txq_id = SEQ_TO_QUEUE(sequence);
1812         int index = SEQ_TO_INDEX(sequence);
1813         int cmd_index;
1814         struct iwl_device_cmd *cmd;
1815         struct iwl_cmd_meta *meta;
1816         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1817         struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1818
1819         /* If a Tx command is being handled and it isn't in the actual
1820          * command queue then there a command routing bug has been introduced
1821          * in the queue management code. */
1822         if (WARN(txq_id != trans_pcie->cmd_queue,
1823                  "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1824                  txq_id, trans_pcie->cmd_queue, sequence, txq->read_ptr,
1825                  txq->write_ptr)) {
1826                 iwl_print_hex_error(trans, pkt, 32);
1827                 return;
1828         }
1829
1830         spin_lock_bh(&txq->lock);
1831
1832         cmd_index = iwl_pcie_get_cmd_index(txq, index);
1833         cmd = txq->entries[cmd_index].cmd;
1834         meta = &txq->entries[cmd_index].meta;
1835         group_id = cmd->hdr.group_id;
1836         cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0);
1837
1838         iwl_pcie_tfd_unmap(trans, meta, txq, index);
1839
1840         /* Input error checking is done when commands are added to queue. */
1841         if (meta->flags & CMD_WANT_SKB) {
1842                 struct page *p = rxb_steal_page(rxb);
1843
1844                 meta->source->resp_pkt = pkt;
1845                 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1846                 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1847         }
1848
1849         if (meta->flags & CMD_WANT_ASYNC_CALLBACK)
1850                 iwl_op_mode_async_cb(trans->op_mode, cmd);
1851
1852         iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1853
1854         if (!(meta->flags & CMD_ASYNC)) {
1855                 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
1856                         IWL_WARN(trans,
1857                                  "HCMD_ACTIVE already clear for command %s\n",
1858                                  iwl_get_cmd_string(trans, cmd_id));
1859                 }
1860                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1861                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1862                                iwl_get_cmd_string(trans, cmd_id));
1863                 wake_up(&trans_pcie->wait_command_queue);
1864         }
1865
1866         if (meta->flags & CMD_MAKE_TRANS_IDLE) {
1867                 IWL_DEBUG_INFO(trans, "complete %s - mark trans as idle\n",
1868                                iwl_get_cmd_string(trans, cmd->hdr.cmd));
1869                 set_bit(STATUS_TRANS_IDLE, &trans->status);
1870                 wake_up(&trans_pcie->d0i3_waitq);
1871         }
1872
1873         if (meta->flags & CMD_WAKE_UP_TRANS) {
1874                 IWL_DEBUG_INFO(trans, "complete %s - clear trans idle flag\n",
1875                                iwl_get_cmd_string(trans, cmd->hdr.cmd));
1876                 clear_bit(STATUS_TRANS_IDLE, &trans->status);
1877                 wake_up(&trans_pcie->d0i3_waitq);
1878         }
1879
1880         meta->flags = 0;
1881
1882         spin_unlock_bh(&txq->lock);
1883 }
1884
1885 #define HOST_COMPLETE_TIMEOUT   (2 * HZ)
1886
1887 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1888                                     struct iwl_host_cmd *cmd)
1889 {
1890         int ret;
1891
1892         /* An asynchronous command can not expect an SKB to be set. */
1893         if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1894                 return -EINVAL;
1895
1896         ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1897         if (ret < 0) {
1898                 IWL_ERR(trans,
1899                         "Error sending %s: enqueue_hcmd failed: %d\n",
1900                         iwl_get_cmd_string(trans, cmd->id), ret);
1901                 return ret;
1902         }
1903         return 0;
1904 }
1905
1906 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1907                                    struct iwl_host_cmd *cmd)
1908 {
1909         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1910         struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1911         int cmd_idx;
1912         int ret;
1913
1914         IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1915                        iwl_get_cmd_string(trans, cmd->id));
1916
1917         if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
1918                                   &trans->status),
1919                  "Command %s: a command is already active!\n",
1920                  iwl_get_cmd_string(trans, cmd->id)))
1921                 return -EIO;
1922
1923         IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1924                        iwl_get_cmd_string(trans, cmd->id));
1925
1926         if (pm_runtime_suspended(&trans_pcie->pci_dev->dev)) {
1927                 ret = wait_event_timeout(trans_pcie->d0i3_waitq,
1928                                  pm_runtime_active(&trans_pcie->pci_dev->dev),
1929                                  msecs_to_jiffies(IWL_TRANS_IDLE_TIMEOUT));
1930                 if (!ret) {
1931                         IWL_ERR(trans, "Timeout exiting D0i3 before hcmd\n");
1932                         return -ETIMEDOUT;
1933                 }
1934         }
1935
1936         cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1937         if (cmd_idx < 0) {
1938                 ret = cmd_idx;
1939                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1940                 IWL_ERR(trans,
1941                         "Error sending %s: enqueue_hcmd failed: %d\n",
1942                         iwl_get_cmd_string(trans, cmd->id), ret);
1943                 return ret;
1944         }
1945
1946         ret = wait_event_timeout(trans_pcie->wait_command_queue,
1947                                  !test_bit(STATUS_SYNC_HCMD_ACTIVE,
1948                                            &trans->status),
1949                                  HOST_COMPLETE_TIMEOUT);
1950         if (!ret) {
1951                 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
1952                         iwl_get_cmd_string(trans, cmd->id),
1953                         jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1954
1955                 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
1956                         txq->read_ptr, txq->write_ptr);
1957
1958                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1959                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1960                                iwl_get_cmd_string(trans, cmd->id));
1961                 ret = -ETIMEDOUT;
1962
1963                 iwl_trans_sync_nmi(trans);
1964                 goto cancel;
1965         }
1966
1967         if (test_bit(STATUS_FW_ERROR, &trans->status)) {
1968                 iwl_trans_pcie_dump_regs(trans);
1969                 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1970                         iwl_get_cmd_string(trans, cmd->id));
1971                 dump_stack();
1972                 ret = -EIO;
1973                 goto cancel;
1974         }
1975
1976         if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1977             test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
1978                 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1979                 ret = -ERFKILL;
1980                 goto cancel;
1981         }
1982
1983         if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1984                 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1985                         iwl_get_cmd_string(trans, cmd->id));
1986                 ret = -EIO;
1987                 goto cancel;
1988         }
1989
1990         return 0;
1991
1992 cancel:
1993         if (cmd->flags & CMD_WANT_SKB) {
1994                 /*
1995                  * Cancel the CMD_WANT_SKB flag for the cmd in the
1996                  * TX cmd queue. Otherwise in case the cmd comes
1997                  * in later, it will possibly set an invalid
1998                  * address (cmd->meta.source).
1999                  */
2000                 txq->entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
2001         }
2002
2003         if (cmd->resp_pkt) {
2004                 iwl_free_resp(cmd);
2005                 cmd->resp_pkt = NULL;
2006         }
2007
2008         return ret;
2009 }
2010
2011 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
2012 {
2013         /* Make sure the NIC is still alive in the bus */
2014         if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2015                 return -ENODEV;
2016
2017         if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
2018             test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
2019                 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
2020                                   cmd->id);
2021                 return -ERFKILL;
2022         }
2023
2024         if (cmd->flags & CMD_ASYNC)
2025                 return iwl_pcie_send_hcmd_async(trans, cmd);
2026
2027         /* We still can fail on RFKILL that can be asserted while we wait */
2028         return iwl_pcie_send_hcmd_sync(trans, cmd);
2029 }
2030
2031 static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb,
2032                              struct iwl_txq *txq, u8 hdr_len,
2033                              struct iwl_cmd_meta *out_meta)
2034 {
2035         u16 head_tb_len;
2036         int i;
2037
2038         /*
2039          * Set up TFD's third entry to point directly to remainder
2040          * of skb's head, if any
2041          */
2042         head_tb_len = skb_headlen(skb) - hdr_len;
2043
2044         if (head_tb_len > 0) {
2045                 dma_addr_t tb_phys = dma_map_single(trans->dev,
2046                                                     skb->data + hdr_len,
2047                                                     head_tb_len, DMA_TO_DEVICE);
2048                 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
2049                         return -EINVAL;
2050                 trace_iwlwifi_dev_tx_tb(trans->dev, skb,
2051                                         skb->data + hdr_len,
2052                                         head_tb_len);
2053                 iwl_pcie_txq_build_tfd(trans, txq, tb_phys, head_tb_len, false);
2054         }
2055
2056         /* set up the remaining entries to point to the data */
2057         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2058                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2059                 dma_addr_t tb_phys;
2060                 int tb_idx;
2061
2062                 if (!skb_frag_size(frag))
2063                         continue;
2064
2065                 tb_phys = skb_frag_dma_map(trans->dev, frag, 0,
2066                                            skb_frag_size(frag), DMA_TO_DEVICE);
2067
2068                 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
2069                         return -EINVAL;
2070                 trace_iwlwifi_dev_tx_tb(trans->dev, skb,
2071                                         skb_frag_address(frag),
2072                                         skb_frag_size(frag));
2073                 tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
2074                                                 skb_frag_size(frag), false);
2075                 if (tb_idx < 0)
2076                         return tb_idx;
2077
2078                 out_meta->tbs |= BIT(tb_idx);
2079         }
2080
2081         return 0;
2082 }
2083
2084 #ifdef CONFIG_INET
2085 struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len)
2086 {
2087         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2088         struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page);
2089
2090         if (!p->page)
2091                 goto alloc;
2092
2093         /* enough room on this page */
2094         if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE)
2095                 return p;
2096
2097         /* We don't have enough room on this page, get a new one. */
2098         __free_page(p->page);
2099
2100 alloc:
2101         p->page = alloc_page(GFP_ATOMIC);
2102         if (!p->page)
2103                 return NULL;
2104         p->pos = page_address(p->page);
2105         return p;
2106 }
2107
2108 static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph,
2109                                         bool ipv6, unsigned int len)
2110 {
2111         if (ipv6) {
2112                 struct ipv6hdr *iphv6 = iph;
2113
2114                 tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr,
2115                                                len + tcph->doff * 4,
2116                                                IPPROTO_TCP, 0);
2117         } else {
2118                 struct iphdr *iphv4 = iph;
2119
2120                 ip_send_check(iphv4);
2121                 tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr,
2122                                                  len + tcph->doff * 4,
2123                                                  IPPROTO_TCP, 0);
2124         }
2125 }
2126
2127 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2128                                    struct iwl_txq *txq, u8 hdr_len,
2129                                    struct iwl_cmd_meta *out_meta,
2130                                    struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2131 {
2132         struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload;
2133         struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
2134         struct ieee80211_hdr *hdr = (void *)skb->data;
2135         unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room;
2136         unsigned int mss = skb_shinfo(skb)->gso_size;
2137         u16 length, iv_len, amsdu_pad;
2138         u8 *start_hdr;
2139         struct iwl_tso_hdr_page *hdr_page;
2140         struct page **page_ptr;
2141         struct tso_t tso;
2142
2143         /* if the packet is protected, then it must be CCMP or GCMP */
2144         BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN);
2145         iv_len = ieee80211_has_protected(hdr->frame_control) ?
2146                 IEEE80211_CCMP_HDR_LEN : 0;
2147
2148         trace_iwlwifi_dev_tx(trans->dev, skb,
2149                              iwl_pcie_get_tfd(trans, txq, txq->write_ptr),
2150                              trans_pcie->tfd_size,
2151                              &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 0);
2152
2153         ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb);
2154         snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb);
2155         total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len;
2156         amsdu_pad = 0;
2157
2158         /* total amount of header we may need for this A-MSDU */
2159         hdr_room = DIV_ROUND_UP(total_len, mss) *
2160                 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len;
2161
2162         /* Our device supports 9 segments at most, it will fit in 1 page */
2163         hdr_page = get_page_hdr(trans, hdr_room);
2164         if (!hdr_page)
2165                 return -ENOMEM;
2166
2167         get_page(hdr_page->page);
2168         start_hdr = hdr_page->pos;
2169         page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs);
2170         *page_ptr = hdr_page->page;
2171         memcpy(hdr_page->pos, skb->data + hdr_len, iv_len);
2172         hdr_page->pos += iv_len;
2173
2174         /*
2175          * Pull the ieee80211 header + IV to be able to use TSO core,
2176          * we will restore it for the tx_status flow.
2177          */
2178         skb_pull(skb, hdr_len + iv_len);
2179
2180         /*
2181          * Remove the length of all the headers that we don't actually
2182          * have in the MPDU by themselves, but that we duplicate into
2183          * all the different MSDUs inside the A-MSDU.
2184          */
2185         le16_add_cpu(&tx_cmd->len, -snap_ip_tcp_hdrlen);
2186
2187         tso_start(skb, &tso);
2188
2189         while (total_len) {
2190                 /* this is the data left for this subframe */
2191                 unsigned int data_left =
2192                         min_t(unsigned int, mss, total_len);
2193                 struct sk_buff *csum_skb = NULL;
2194                 unsigned int hdr_tb_len;
2195                 dma_addr_t hdr_tb_phys;
2196                 struct tcphdr *tcph;
2197                 u8 *iph, *subf_hdrs_start = hdr_page->pos;
2198
2199                 total_len -= data_left;
2200
2201                 memset(hdr_page->pos, 0, amsdu_pad);
2202                 hdr_page->pos += amsdu_pad;
2203                 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen +
2204                                   data_left)) & 0x3;
2205                 ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr));
2206                 hdr_page->pos += ETH_ALEN;
2207                 ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr));
2208                 hdr_page->pos += ETH_ALEN;
2209
2210                 length = snap_ip_tcp_hdrlen + data_left;
2211                 *((__be16 *)hdr_page->pos) = cpu_to_be16(length);
2212                 hdr_page->pos += sizeof(length);
2213
2214                 /*
2215                  * This will copy the SNAP as well which will be considered
2216                  * as MAC header.
2217                  */
2218                 tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len);
2219                 iph = hdr_page->pos + 8;
2220                 tcph = (void *)(iph + ip_hdrlen);
2221
2222                 /* For testing on current hardware only */
2223                 if (trans_pcie->sw_csum_tx) {
2224                         csum_skb = alloc_skb(data_left + tcp_hdrlen(skb),
2225                                              GFP_ATOMIC);
2226                         if (!csum_skb)
2227                                 return -ENOMEM;
2228
2229                         iwl_compute_pseudo_hdr_csum(iph, tcph,
2230                                                     skb->protocol ==
2231                                                         htons(ETH_P_IPV6),
2232                                                     data_left);
2233
2234                         skb_put_data(csum_skb, tcph, tcp_hdrlen(skb));
2235                         skb_reset_transport_header(csum_skb);
2236                         csum_skb->csum_start =
2237                                 (unsigned char *)tcp_hdr(csum_skb) -
2238                                                  csum_skb->head;
2239                 }
2240
2241                 hdr_page->pos += snap_ip_tcp_hdrlen;
2242
2243                 hdr_tb_len = hdr_page->pos - start_hdr;
2244                 hdr_tb_phys = dma_map_single(trans->dev, start_hdr,
2245                                              hdr_tb_len, DMA_TO_DEVICE);
2246                 if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) {
2247                         dev_kfree_skb(csum_skb);
2248                         return -EINVAL;
2249                 }
2250                 iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys,
2251                                        hdr_tb_len, false);
2252                 trace_iwlwifi_dev_tx_tb(trans->dev, skb, start_hdr,
2253                                         hdr_tb_len);
2254                 /* add this subframe's headers' length to the tx_cmd */
2255                 le16_add_cpu(&tx_cmd->len, hdr_page->pos - subf_hdrs_start);
2256
2257                 /* prepare the start_hdr for the next subframe */
2258                 start_hdr = hdr_page->pos;
2259
2260                 /* put the payload */
2261                 while (data_left) {
2262                         unsigned int size = min_t(unsigned int, tso.size,
2263                                                   data_left);
2264                         dma_addr_t tb_phys;
2265
2266                         if (trans_pcie->sw_csum_tx)
2267                                 skb_put_data(csum_skb, tso.data, size);
2268
2269                         tb_phys = dma_map_single(trans->dev, tso.data,
2270                                                  size, DMA_TO_DEVICE);
2271                         if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
2272                                 dev_kfree_skb(csum_skb);
2273                                 return -EINVAL;
2274                         }
2275
2276                         iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
2277                                                size, false);
2278                         trace_iwlwifi_dev_tx_tb(trans->dev, skb, tso.data,
2279                                                 size);
2280
2281                         data_left -= size;
2282                         tso_build_data(skb, &tso, size);
2283                 }
2284
2285                 /* For testing on early hardware only */
2286                 if (trans_pcie->sw_csum_tx) {
2287                         __wsum csum;
2288
2289                         csum = skb_checksum(csum_skb,
2290                                             skb_checksum_start_offset(csum_skb),
2291                                             csum_skb->len -
2292                                             skb_checksum_start_offset(csum_skb),
2293                                             0);
2294                         dev_kfree_skb(csum_skb);
2295                         dma_sync_single_for_cpu(trans->dev, hdr_tb_phys,
2296                                                 hdr_tb_len, DMA_TO_DEVICE);
2297                         tcph->check = csum_fold(csum);
2298                         dma_sync_single_for_device(trans->dev, hdr_tb_phys,
2299                                                    hdr_tb_len, DMA_TO_DEVICE);
2300                 }
2301         }
2302
2303         /* re -add the WiFi header and IV */
2304         skb_push(skb, hdr_len + iv_len);
2305
2306         return 0;
2307 }
2308 #else /* CONFIG_INET */
2309 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2310                                    struct iwl_txq *txq, u8 hdr_len,
2311                                    struct iwl_cmd_meta *out_meta,
2312                                    struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2313 {
2314         /* No A-MSDU without CONFIG_INET */
2315         WARN_ON(1);
2316
2317         return -1;
2318 }
2319 #endif /* CONFIG_INET */
2320
2321 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
2322                       struct iwl_device_cmd *dev_cmd, int txq_id)
2323 {
2324         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2325         struct ieee80211_hdr *hdr;
2326         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
2327         struct iwl_cmd_meta *out_meta;
2328         struct iwl_txq *txq;
2329         dma_addr_t tb0_phys, tb1_phys, scratch_phys;
2330         void *tb1_addr;
2331         void *tfd;
2332         u16 len, tb1_len;
2333         bool wait_write_ptr;
2334         __le16 fc;
2335         u8 hdr_len;
2336         u16 wifi_seq;
2337         bool amsdu;
2338
2339         txq = trans_pcie->txq[txq_id];
2340
2341         if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
2342                       "TX on unused queue %d\n", txq_id))
2343                 return -EINVAL;
2344
2345         if (unlikely(trans_pcie->sw_csum_tx &&
2346                      skb->ip_summed == CHECKSUM_PARTIAL)) {
2347                 int offs = skb_checksum_start_offset(skb);
2348                 int csum_offs = offs + skb->csum_offset;
2349                 __wsum csum;
2350
2351                 if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16)))
2352                         return -1;
2353
2354                 csum = skb_checksum(skb, offs, skb->len - offs, 0);
2355                 *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum);
2356
2357                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2358         }
2359
2360         if (skb_is_nonlinear(skb) &&
2361             skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) &&
2362             __skb_linearize(skb))
2363                 return -ENOMEM;
2364
2365         /* mac80211 always puts the full header into the SKB's head,
2366          * so there's no need to check if it's readable there
2367          */
2368         hdr = (struct ieee80211_hdr *)skb->data;
2369         fc = hdr->frame_control;
2370         hdr_len = ieee80211_hdrlen(fc);
2371
2372         spin_lock(&txq->lock);
2373
2374         if (iwl_queue_space(trans, txq) < txq->high_mark) {
2375                 iwl_stop_queue(trans, txq);
2376
2377                 /* don't put the packet on the ring, if there is no room */
2378                 if (unlikely(iwl_queue_space(trans, txq) < 3)) {
2379                         struct iwl_device_cmd **dev_cmd_ptr;
2380
2381                         dev_cmd_ptr = (void *)((u8 *)skb->cb +
2382                                                trans_pcie->dev_cmd_offs);
2383
2384                         *dev_cmd_ptr = dev_cmd;
2385                         __skb_queue_tail(&txq->overflow_q, skb);
2386
2387                         spin_unlock(&txq->lock);
2388                         return 0;
2389                 }
2390         }
2391
2392         /* In AGG mode, the index in the ring must correspond to the WiFi
2393          * sequence number. This is a HW requirements to help the SCD to parse
2394          * the BA.
2395          * Check here that the packets are in the right place on the ring.
2396          */
2397         wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
2398         WARN_ONCE(txq->ampdu &&
2399                   (wifi_seq & 0xff) != txq->write_ptr,
2400                   "Q: %d WiFi Seq %d tfdNum %d",
2401                   txq_id, wifi_seq, txq->write_ptr);
2402
2403         /* Set up driver data for this TFD */
2404         txq->entries[txq->write_ptr].skb = skb;
2405         txq->entries[txq->write_ptr].cmd = dev_cmd;
2406
2407         dev_cmd->hdr.sequence =
2408                 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
2409                             INDEX_TO_SEQ(txq->write_ptr)));
2410
2411         tb0_phys = iwl_pcie_get_first_tb_dma(txq, txq->write_ptr);
2412         scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
2413                        offsetof(struct iwl_tx_cmd, scratch);
2414
2415         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
2416         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
2417
2418         /* Set up first empty entry in queue's array of Tx/cmd buffers */
2419         out_meta = &txq->entries[txq->write_ptr].meta;
2420         out_meta->flags = 0;
2421
2422         /*
2423          * The second TB (tb1) points to the remainder of the TX command
2424          * and the 802.11 header - dword aligned size
2425          * (This calculation modifies the TX command, so do it before the
2426          * setup of the first TB)
2427          */
2428         len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
2429               hdr_len - IWL_FIRST_TB_SIZE;
2430         /* do not align A-MSDU to dword as the subframe header aligns it */
2431         amsdu = ieee80211_is_data_qos(fc) &&
2432                 (*ieee80211_get_qos_ctl(hdr) &
2433                  IEEE80211_QOS_CTL_A_MSDU_PRESENT);
2434         if (trans_pcie->sw_csum_tx || !amsdu) {
2435                 tb1_len = ALIGN(len, 4);
2436                 /* Tell NIC about any 2-byte padding after MAC header */
2437                 if (tb1_len != len)
2438                         tx_cmd->tx_flags |= cpu_to_le32(TX_CMD_FLG_MH_PAD);
2439         } else {
2440                 tb1_len = len;
2441         }
2442
2443         /*
2444          * The first TB points to bi-directional DMA data, we'll
2445          * memcpy the data into it later.
2446          */
2447         iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
2448                                IWL_FIRST_TB_SIZE, true);
2449
2450         /* there must be data left over for TB1 or this code must be changed */
2451         BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE);
2452
2453         /* map the data for TB1 */
2454         tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE;
2455         tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
2456         if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
2457                 goto out_err;
2458         iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
2459
2460         trace_iwlwifi_dev_tx(trans->dev, skb,
2461                              iwl_pcie_get_tfd(trans, txq,
2462                                               txq->write_ptr),
2463                              trans_pcie->tfd_size,
2464                              &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len,
2465                              hdr_len);
2466
2467         /*
2468          * If gso_size wasn't set, don't give the frame "amsdu treatment"
2469          * (adding subframes, etc.).
2470          * This can happen in some testing flows when the amsdu was already
2471          * pre-built, and we just need to send the resulting skb.
2472          */
2473         if (amsdu && skb_shinfo(skb)->gso_size) {
2474                 if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len,
2475                                                      out_meta, dev_cmd,
2476                                                      tb1_len)))
2477                         goto out_err;
2478         } else {
2479                 struct sk_buff *frag;
2480
2481                 if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len,
2482                                                out_meta)))
2483                         goto out_err;
2484
2485                 skb_walk_frags(skb, frag) {
2486                         if (unlikely(iwl_fill_data_tbs(trans, frag, txq, 0,
2487                                                        out_meta)))
2488                                 goto out_err;
2489                 }
2490         }
2491
2492         /* building the A-MSDU might have changed this data, so memcpy it now */
2493         memcpy(&txq->first_tb_bufs[txq->write_ptr], dev_cmd, IWL_FIRST_TB_SIZE);
2494
2495         tfd = iwl_pcie_get_tfd(trans, txq, txq->write_ptr);
2496         /* Set up entry for this TFD in Tx byte-count array */
2497         iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len),
2498                                          iwl_pcie_tfd_get_num_tbs(trans, tfd));
2499
2500         wait_write_ptr = ieee80211_has_morefrags(fc);
2501
2502         /* start timer if queue currently empty */
2503         if (txq->read_ptr == txq->write_ptr) {
2504                 if (txq->wd_timeout) {
2505                         /*
2506                          * If the TXQ is active, then set the timer, if not,
2507                          * set the timer in remainder so that the timer will
2508                          * be armed with the right value when the station will
2509                          * wake up.
2510                          */
2511                         if (!txq->frozen)
2512                                 mod_timer(&txq->stuck_timer,
2513                                           jiffies + txq->wd_timeout);
2514                         else
2515                                 txq->frozen_expiry_remainder = txq->wd_timeout;
2516                 }
2517                 IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", txq->id);
2518                 iwl_trans_ref(trans);
2519         }
2520
2521         /* Tell device the write index *just past* this latest filled TFD */
2522         txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr);
2523         if (!wait_write_ptr)
2524                 iwl_pcie_txq_inc_wr_ptr(trans, txq);
2525
2526         /*
2527          * At this point the frame is "transmitted" successfully
2528          * and we will get a TX status notification eventually.
2529          */
2530         spin_unlock(&txq->lock);
2531         return 0;
2532 out_err:
2533         iwl_pcie_tfd_unmap(trans, out_meta, txq, txq->write_ptr);
2534         spin_unlock(&txq->lock);
2535         return -1;
2536 }