1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2005-2014, 2018-2020 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
7 #ifndef __iwl_fw_api_debug_h__
8 #define __iwl_fw_api_debug_h__
11 * enum iwl_debug_cmds - debug commands
16 * LMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and
17 * &struct iwl_dbg_mem_access_rsp
22 * UMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and
23 * &struct iwl_dbg_mem_access_rsp
28 * updates the enabled event severities
29 * &struct iwl_dbg_host_event_cfg_cmd
33 * @DBGC_SUSPEND_RESUME:
34 * DBGC suspend/resume commad. Uses a single dword as data:
35 * 0 - resume DBGC recording
36 * 1 - suspend DBGC recording
38 DBGC_SUSPEND_RESUME = 0x7,
41 * passes DRAM buffers to a DBGC
42 * &struct iwl_buf_alloc_cmd
44 BUFFER_ALLOCATION = 0x8,
46 * @MFU_ASSERT_DUMP_NTF:
47 * &struct iwl_mfu_assert_dump_notif
49 MFU_ASSERT_DUMP_NTF = 0xFE,
52 /* Error response/notification */
54 FW_ERR_UNKNOWN_CMD = 0x0,
55 FW_ERR_INVALID_CMD_PARAM = 0x1,
57 FW_ERR_ARC_MEMORY = 0x3,
58 FW_ERR_ARC_CODE = 0x4,
59 FW_ERR_WATCH_DOG = 0x5,
60 FW_ERR_WEP_GRP_KEY_INDX = 0x10,
61 FW_ERR_WEP_KEY_SIZE = 0x11,
62 FW_ERR_OBSOLETE_FUNC = 0x12,
63 FW_ERR_UNEXPECTED = 0xFE,
67 /** enum iwl_dbg_suspend_resume_cmds - dbgc suspend resume operations
68 * dbgc suspend resume command operations
69 * @DBGC_RESUME_CMD: resume dbgc recording
70 * @DBGC_SUSPEND_CMD: stop dbgc recording
72 enum iwl_dbg_suspend_resume_cmds {
78 * struct iwl_error_resp - FW error indication
79 * ( REPLY_ERROR = 0x2 )
80 * @error_type: one of FW_ERR_*
81 * @cmd_id: the command ID for which the error occurred
82 * @reserved1: reserved
83 * @bad_cmd_seq_num: sequence number of the erroneous command
84 * @error_service: which service created the error, applicable only if
85 * error_type = 2, otherwise 0
86 * @timestamp: TSF in usecs.
88 struct iwl_error_resp {
92 __le16 bad_cmd_seq_num;
97 #define TX_FIFO_MAX_NUM_9000 8
98 #define TX_FIFO_MAX_NUM 15
99 #define RX_FIFO_MAX_NUM 2
100 #define TX_FIFO_INTERNAL_MAX_NUM 6
103 * struct iwl_shared_mem_cfg_v2 - Shared memory configuration information
105 * @shared_mem_addr: shared memory addr (pre 8000 HW set to 0x0 as MARBH is not
107 * @shared_mem_size: shared memory size
108 * @sample_buff_addr: internal sample (mon/adc) buff addr (pre 8000 HW set to
109 * 0x0 as accessible only via DBGM RDAT)
110 * @sample_buff_size: internal sample buff size
111 * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB), (pre
112 * 8000 HW set to 0x0 as not accessible)
113 * @txfifo_size: size of TXF0 ... TXF7
114 * @rxfifo_size: RXF1, RXF2 sizes. If there is no RXF2, it'll have a value of 0
115 * @page_buff_addr: used by UMAC and performance debug (page miss analysis),
116 * when paging is not supported this should be 0
117 * @page_buff_size: size of %page_buff_addr
118 * @rxfifo_addr: Start address of rxFifo
119 * @internal_txfifo_addr: start address of internalFifo
120 * @internal_txfifo_size: internal fifos' size
122 * NOTE: on firmware that don't have IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG
123 * set, the last 3 members don't exist.
125 struct iwl_shared_mem_cfg_v2 {
126 __le32 shared_mem_addr;
127 __le32 shared_mem_size;
128 __le32 sample_buff_addr;
129 __le32 sample_buff_size;
131 __le32 txfifo_size[TX_FIFO_MAX_NUM_9000];
132 __le32 rxfifo_size[RX_FIFO_MAX_NUM];
133 __le32 page_buff_addr;
134 __le32 page_buff_size;
136 __le32 internal_txfifo_addr;
137 __le32 internal_txfifo_size[TX_FIFO_INTERNAL_MAX_NUM];
138 } __packed; /* SHARED_MEM_ALLOC_API_S_VER_2 */
141 * struct iwl_shared_mem_lmac_cfg - LMAC shared memory configuration
143 * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB)
144 * @txfifo_size: size of TX FIFOs
145 * @rxfifo1_addr: RXF1 addr
146 * @rxfifo1_size: RXF1 size
148 struct iwl_shared_mem_lmac_cfg {
150 __le32 txfifo_size[TX_FIFO_MAX_NUM];
154 } __packed; /* SHARED_MEM_ALLOC_LMAC_API_S_VER_1 */
157 * struct iwl_shared_mem_cfg - Shared memory configuration information
159 * @shared_mem_addr: shared memory address
160 * @shared_mem_size: shared memory size
161 * @sample_buff_addr: internal sample (mon/adc) buff addr
162 * @sample_buff_size: internal sample buff size
163 * @rxfifo2_addr: start addr of RXF2
164 * @rxfifo2_size: size of RXF2
165 * @page_buff_addr: used by UMAC and performance debug (page miss analysis),
166 * when paging is not supported this should be 0
167 * @page_buff_size: size of %page_buff_addr
168 * @lmac_num: number of LMACs (1 or 2)
169 * @lmac_smem: per - LMAC smem data
170 * @rxfifo2_control_addr: start addr of RXF2C
171 * @rxfifo2_control_size: size of RXF2C
173 struct iwl_shared_mem_cfg {
174 __le32 shared_mem_addr;
175 __le32 shared_mem_size;
176 __le32 sample_buff_addr;
177 __le32 sample_buff_size;
180 __le32 page_buff_addr;
181 __le32 page_buff_size;
183 struct iwl_shared_mem_lmac_cfg lmac_smem[3];
184 __le32 rxfifo2_control_addr;
185 __le32 rxfifo2_control_size;
186 } __packed; /* SHARED_MEM_ALLOC_API_S_VER_4 */
189 * struct iwl_mfuart_load_notif - mfuart image version & status
190 * ( MFUART_LOAD_NOTIFICATION = 0xb1 )
191 * @installed_ver: installed image version
192 * @external_ver: external image version
193 * @status: MFUART loading status
194 * @duration: MFUART loading time
195 * @image_size: MFUART image size in bytes
197 struct iwl_mfuart_load_notif {
198 __le32 installed_ver;
202 /* image size valid only in v2 of the command */
204 } __packed; /* MFU_LOADER_NTFY_API_S_VER_2 */
207 * struct iwl_mfu_assert_dump_notif - mfuart dump logs
208 * ( MFU_ASSERT_DUMP_NTF = 0xfe )
209 * @assert_id: mfuart assert id that cause the notif
210 * @curr_reset_num: number of asserts since uptime
211 * @index_num: current chunk id
212 * @parts_num: total number of chunks
213 * @data_size: number of data bytes sent
216 struct iwl_mfu_assert_dump_notif {
218 __le32 curr_reset_num;
223 } __packed; /* MFU_DUMP_ASSERT_API_S_VER_1 */
226 * enum iwl_mvm_marker_id - marker ids
228 * The ids for different type of markers to insert into the usniffer logs
230 * @MARKER_ID_TX_FRAME_LATENCY: TX latency marker
231 * @MARKER_ID_SYNC_CLOCK: sync FW time and systime
233 enum iwl_mvm_marker_id {
234 MARKER_ID_TX_FRAME_LATENCY = 1,
235 MARKER_ID_SYNC_CLOCK = 2,
236 }; /* MARKER_ID_API_E_VER_2 */
239 * struct iwl_mvm_marker - mark info into the usniffer logs
241 * (MARKER_CMD = 0xcb)
243 * Mark the UTC time stamp into the usniffer logs together with additional
244 * metadata, so the usniffer output can be parsed.
245 * In the command response the ucode will return the GP2 time.
247 * @dw_len: The amount of dwords following this byte including this byte.
248 * @marker_id: A unique marker id (iwl_mvm_marker_id).
249 * @reserved: reserved.
250 * @timestamp: in milliseconds since 1970-01-01 00:00:00 UTC
251 * @metadata: additional meta data that will be written to the unsiffer log
253 struct iwl_mvm_marker {
259 } __packed; /* MARKER_API_S_VER_1 */
262 * struct iwl_mvm_marker_rsp - Response to marker cmd
264 * @gp2: The gp2 clock value in the FW
266 struct iwl_mvm_marker_rsp {
270 /* Operation types for the debug mem access */
272 DEBUG_MEM_OP_READ = 0,
273 DEBUG_MEM_OP_WRITE = 1,
274 DEBUG_MEM_OP_WRITE_BYTES = 2,
277 #define DEBUG_MEM_MAX_SIZE_DWORDS 32
280 * struct iwl_dbg_mem_access_cmd - Request the device to read/write memory
281 * @op: DEBUG_MEM_OP_*
282 * @addr: address to read/write from/to
283 * @len: in dwords, to read/write
284 * @data: for write opeations, contains the source buffer
286 struct iwl_dbg_mem_access_cmd {
291 } __packed; /* DEBUG_(U|L)MAC_RD_WR_CMD_API_S_VER_1 */
293 /* Status responses for the debug mem access */
295 DEBUG_MEM_STATUS_SUCCESS = 0x0,
296 DEBUG_MEM_STATUS_FAILED = 0x1,
297 DEBUG_MEM_STATUS_LOCKED = 0x2,
298 DEBUG_MEM_STATUS_HIDDEN = 0x3,
299 DEBUG_MEM_STATUS_LENGTH = 0x4,
303 * struct iwl_dbg_mem_access_rsp - Response to debug mem commands
304 * @status: DEBUG_MEM_STATUS_*
305 * @len: read dwords (0 for write operations)
306 * @data: contains the read DWs
308 struct iwl_dbg_mem_access_rsp {
312 } __packed; /* DEBUG_(U|L)MAC_RD_WR_RSP_API_S_VER_1 */
315 * struct iwl_dbg_suspend_resume_cmd - dbgc suspend resume command
316 * @operation: suspend or resume operation, uses
317 * &enum iwl_dbg_suspend_resume_cmds
319 struct iwl_dbg_suspend_resume_cmd {
323 #define BUF_ALLOC_MAX_NUM_FRAGS 16
326 * struct iwl_buf_alloc_frag - a DBGC fragment
327 * @addr: base address of the fragment
328 * @size: size of the fragment
330 struct iwl_buf_alloc_frag {
333 } __packed; /* FRAGMENT_STRUCTURE_API_S_VER_1 */
336 * struct iwl_buf_alloc_cmd - buffer allocation command
337 * @alloc_id: &enum iwl_fw_ini_allocation_id
338 * @buf_location: &enum iwl_fw_ini_buffer_location
339 * @num_frags: number of fragments
340 * @frags: fragments array
342 struct iwl_buf_alloc_cmd {
346 struct iwl_buf_alloc_frag frags[BUF_ALLOC_MAX_NUM_FRAGS];
347 } __packed; /* BUFFER_ALLOCATION_CMD_API_S_VER_2 */
350 * struct iwl_dbg_host_event_cfg_cmd
351 * @enabled_severities: enabled severities
353 struct iwl_dbg_host_event_cfg_cmd {
354 __le32 enabled_severities;
355 } __packed; /* DEBUG_HOST_EVENT_CFG_CMD_API_S_VER_1 */
357 #endif /* __iwl_fw_api_debug_h__ */