2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 static u16 bits_per_symbol[][2] = {
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq,
54 struct ieee80211_sta *sta);
55 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
56 struct ath_txq *txq, struct list_head *bf_q,
57 struct ieee80211_sta *sta,
58 struct ath_tx_status *ts, int txok);
59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
60 struct list_head *head, bool internal);
61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_tx_status *ts, int nframes, int nbad,
64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
68 struct ath_atx_tid *tid,
70 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
71 struct ath_tx_control *txctl);
80 /*********************/
81 /* Aggregation logic */
82 /*********************/
84 static void ath_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb)
86 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
87 struct ieee80211_sta *sta = info->status.status_driver_data[0];
89 if (info->flags & (IEEE80211_TX_CTL_REQ_TX_STATUS |
90 IEEE80211_TX_STATUS_EOSP)) {
91 ieee80211_tx_status(hw, skb);
96 ieee80211_tx_status_noskb(hw, sta, info);
101 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
102 __releases(&txq->axq_lock)
104 struct ieee80211_hw *hw = sc->hw;
105 struct sk_buff_head q;
108 __skb_queue_head_init(&q);
109 skb_queue_splice_init(&txq->complete_q, &q);
110 spin_unlock_bh(&txq->axq_lock);
112 while ((skb = __skb_dequeue(&q)))
113 ath_tx_status(hw, skb);
116 void ath_tx_queue_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
118 struct ieee80211_txq *queue =
119 container_of((void *)tid, struct ieee80211_txq, drv_priv);
121 ieee80211_schedule_txq(sc->hw, queue);
124 void ath9k_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *queue)
126 struct ath_softc *sc = hw->priv;
127 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
128 struct ath_atx_tid *tid = (struct ath_atx_tid *) queue->drv_priv;
129 struct ath_txq *txq = tid->txq;
131 ath_dbg(common, QUEUE, "Waking TX queue: %pM (%d)\n",
132 queue->sta ? queue->sta->addr : queue->vif->addr,
135 ath_txq_lock(sc, txq);
136 ath_txq_schedule(sc, txq);
137 ath_txq_unlock(sc, txq);
140 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
142 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
143 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
144 sizeof(tx_info->rate_driver_data));
145 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
148 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
153 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
154 seqno << IEEE80211_SEQ_SEQ_SHIFT);
157 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
160 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
161 ARRAY_SIZE(bf->rates));
164 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
167 struct ath_frame_info *fi = get_frame_info(skb);
173 txq = sc->tx.txq_map[q];
174 if (WARN_ON(--txq->pending_frames < 0))
175 txq->pending_frames = 0;
179 static struct ath_atx_tid *
180 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
182 u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
183 return ATH_AN_2_TID(an, tidno);
187 ath_tid_pull(struct ath_atx_tid *tid, struct sk_buff **skbuf)
189 struct ieee80211_txq *txq = container_of((void*)tid, struct ieee80211_txq, drv_priv);
190 struct ath_softc *sc = tid->an->sc;
191 struct ieee80211_hw *hw = sc->hw;
192 struct ath_tx_control txctl = {
197 struct ath_frame_info *fi;
200 skb = ieee80211_tx_dequeue(hw, txq);
204 ret = ath_tx_prepare(hw, skb, &txctl);
206 ieee80211_free_txskb(hw, skb);
210 q = skb_get_queue_mapping(skb);
211 if (tid->txq == sc->tx.txq_map[q]) {
212 fi = get_frame_info(skb);
214 ++tid->txq->pending_frames;
221 static int ath_tid_dequeue(struct ath_atx_tid *tid,
222 struct sk_buff **skb)
225 *skb = __skb_dequeue(&tid->retry_q);
227 ret = ath_tid_pull(tid, skb);
232 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
234 struct ath_txq *txq = tid->txq;
237 struct list_head bf_head;
238 struct ath_tx_status ts;
239 struct ath_frame_info *fi;
240 bool sendbar = false;
242 INIT_LIST_HEAD(&bf_head);
244 memset(&ts, 0, sizeof(ts));
246 while ((skb = __skb_dequeue(&tid->retry_q))) {
247 fi = get_frame_info(skb);
250 ath_txq_skb_done(sc, txq, skb);
251 ieee80211_free_txskb(sc->hw, skb);
255 if (fi->baw_tracked) {
256 ath_tx_update_baw(sc, tid, bf);
260 list_add_tail(&bf->list, &bf_head);
261 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
265 ath_txq_unlock(sc, txq);
266 ath_send_bar(tid, tid->seq_start);
267 ath_txq_lock(sc, txq);
271 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
274 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
275 u16 seqno = bf->bf_state.seqno;
278 if (!fi->baw_tracked)
281 index = ATH_BA_INDEX(tid->seq_start, seqno);
282 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
284 __clear_bit(cindex, tid->tx_buf);
286 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
287 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
288 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
289 if (tid->bar_index >= 0)
294 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
297 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
298 u16 seqno = bf->bf_state.seqno;
304 index = ATH_BA_INDEX(tid->seq_start, seqno);
305 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
306 __set_bit(cindex, tid->tx_buf);
309 if (index >= ((tid->baw_tail - tid->baw_head) &
310 (ATH_TID_MAX_BUFS - 1))) {
311 tid->baw_tail = cindex;
312 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
316 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
317 struct ath_atx_tid *tid)
322 struct list_head bf_head;
323 struct ath_tx_status ts;
324 struct ath_frame_info *fi;
327 memset(&ts, 0, sizeof(ts));
328 INIT_LIST_HEAD(&bf_head);
330 while ((ret = ath_tid_dequeue(tid, &skb)) == 0) {
331 fi = get_frame_info(skb);
335 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq, NULL);
339 list_add_tail(&bf->list, &bf_head);
340 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
344 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
345 struct sk_buff *skb, int count)
347 struct ath_frame_info *fi = get_frame_info(skb);
348 struct ath_buf *bf = fi->bf;
349 struct ieee80211_hdr *hdr;
350 int prev = fi->retries;
352 TX_STAT_INC(sc, txq->axq_qnum, a_retries);
353 fi->retries += count;
358 hdr = (struct ieee80211_hdr *)skb->data;
359 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
360 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
361 sizeof(*hdr), DMA_TO_DEVICE);
364 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
366 struct ath_buf *bf = NULL;
368 spin_lock_bh(&sc->tx.txbuflock);
370 if (unlikely(list_empty(&sc->tx.txbuf))) {
371 spin_unlock_bh(&sc->tx.txbuflock);
375 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
378 spin_unlock_bh(&sc->tx.txbuflock);
383 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
385 spin_lock_bh(&sc->tx.txbuflock);
386 list_add_tail(&bf->list, &sc->tx.txbuf);
387 spin_unlock_bh(&sc->tx.txbuflock);
390 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
394 tbf = ath_tx_get_buffer(sc);
398 ATH_TXBUF_RESET(tbf);
400 tbf->bf_mpdu = bf->bf_mpdu;
401 tbf->bf_buf_addr = bf->bf_buf_addr;
402 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
403 tbf->bf_state = bf->bf_state;
404 tbf->bf_state.stale = false;
409 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
410 struct ath_tx_status *ts, int txok,
411 int *nframes, int *nbad)
413 struct ath_frame_info *fi;
415 u32 ba[WME_BA_BMP_SIZE >> 5];
422 isaggr = bf_isaggr(bf);
424 seq_st = ts->ts_seqnum;
425 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
429 fi = get_frame_info(bf->bf_mpdu);
430 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
433 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
441 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
442 struct ath_buf *bf, struct list_head *bf_q,
443 struct ieee80211_sta *sta,
444 struct ath_atx_tid *tid,
445 struct ath_tx_status *ts, int txok)
447 struct ath_node *an = NULL;
449 struct ieee80211_hdr *hdr;
450 struct ieee80211_tx_info *tx_info;
451 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
452 struct list_head bf_head;
453 struct sk_buff_head bf_pending;
454 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
455 u32 ba[WME_BA_BMP_SIZE >> 5];
456 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
457 bool rc_update = true, isba;
458 struct ieee80211_tx_rate rates[4];
459 struct ath_frame_info *fi;
461 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
466 hdr = (struct ieee80211_hdr *)skb->data;
468 tx_info = IEEE80211_SKB_CB(skb);
470 memcpy(rates, bf->rates, sizeof(rates));
472 retries = ts->ts_longretry + 1;
473 for (i = 0; i < ts->ts_rateindex; i++)
474 retries += rates[i].count;
477 INIT_LIST_HEAD(&bf_head);
479 bf_next = bf->bf_next;
481 if (!bf->bf_state.stale || bf_next != NULL)
482 list_move_tail(&bf->list, &bf_head);
484 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, ts, 0);
491 an = (struct ath_node *)sta->drv_priv;
492 seq_first = tid->seq_start;
493 isba = ts->ts_flags & ATH9K_TX_BA;
496 * The hardware occasionally sends a tx status for the wrong TID.
497 * In this case, the BA status cannot be considered valid and all
498 * subframes need to be retransmitted
500 * Only BlockAcks have a TID and therefore normal Acks cannot be
503 if (isba && tid->tidno != ts->tid)
506 isaggr = bf_isaggr(bf);
507 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
509 if (isaggr && txok) {
510 if (ts->ts_flags & ATH9K_TX_BA) {
511 seq_st = ts->ts_seqnum;
512 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
515 * AR5416 can become deaf/mute when BA
516 * issue happens. Chip needs to be reset.
517 * But AP code may have sychronization issues
518 * when perform internal reset in this routine.
519 * Only enable reset in STA mode for now.
521 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
526 __skb_queue_head_init(&bf_pending);
528 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
530 u16 seqno = bf->bf_state.seqno;
532 txfail = txpending = sendbar = 0;
533 bf_next = bf->bf_next;
536 tx_info = IEEE80211_SKB_CB(skb);
537 fi = get_frame_info(skb);
539 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
542 * Outside of the current BlockAck window,
543 * maybe part of a previous session
546 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
547 /* transmit completion, subframe is
548 * acked by block ack */
550 } else if (!isaggr && txok) {
551 /* transmit completion */
555 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
556 if (txok || !an->sleeping)
557 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
564 bar_index = max_t(int, bar_index,
565 ATH_BA_INDEX(seq_first, seqno));
569 * Make sure the last desc is reclaimed if it
570 * not a holding desc.
572 INIT_LIST_HEAD(&bf_head);
573 if (bf_next != NULL || !bf_last->bf_state.stale)
574 list_move_tail(&bf->list, &bf_head);
578 * complete the acked-ones/xretried ones; update
581 ath_tx_update_baw(sc, tid, bf);
583 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
584 memcpy(tx_info->control.rates, rates, sizeof(rates));
585 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
587 if (bf == bf->bf_lastbf)
588 ath_dynack_sample_tx_ts(sc->sc_ah,
593 ath_tx_complete_buf(sc, bf, txq, &bf_head, sta, ts,
596 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
597 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
598 ieee80211_sta_eosp(sta);
600 /* retry the un-acked ones */
601 if (bf->bf_next == NULL && bf_last->bf_state.stale) {
604 tbf = ath_clone_txbuf(sc, bf_last);
606 * Update tx baw and complete the
607 * frame with failed status if we
611 ath_tx_update_baw(sc, tid, bf);
613 ath_tx_complete_buf(sc, bf, txq,
616 bar_index = max_t(int, bar_index,
617 ATH_BA_INDEX(seq_first, seqno));
625 * Put this buffer to the temporary pending
626 * queue to retain ordering
628 __skb_queue_tail(&bf_pending, skb);
634 /* prepend un-acked frames to the beginning of the pending frame queue */
635 if (!skb_queue_empty(&bf_pending)) {
637 ieee80211_sta_set_buffered(sta, tid->tidno, true);
639 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
641 ath_tx_queue_tid(sc, tid);
642 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
643 tid->clear_ps_filter = true;
647 if (bar_index >= 0) {
648 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
650 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
651 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
653 ath_txq_unlock(sc, txq);
654 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
655 ath_txq_lock(sc, txq);
659 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
662 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
664 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
665 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
668 static void ath_tx_count_airtime(struct ath_softc *sc,
669 struct ieee80211_sta *sta,
671 struct ath_tx_status *ts)
676 airtime += ts->duration * (ts->ts_longretry + 1);
677 for(i = 0; i < ts->ts_rateindex; i++) {
678 int rate_dur = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc, i);
679 airtime += rate_dur * bf->rates[i].count;
682 ieee80211_sta_register_airtime(sta, ts->tid, airtime, 0);
685 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
686 struct ath_tx_status *ts, struct ath_buf *bf,
687 struct list_head *bf_head)
689 struct ieee80211_hw *hw = sc->hw;
690 struct ieee80211_tx_info *info;
691 struct ieee80211_sta *sta;
692 struct ieee80211_hdr *hdr;
693 struct ath_atx_tid *tid = NULL;
696 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
697 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
698 txq->axq_tx_inprogress = false;
701 if (bf_is_ampdu_not_probing(bf))
702 txq->axq_ampdu_depth--;
704 ts->duration = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc,
707 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
708 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
710 struct ath_node *an = (struct ath_node *)sta->drv_priv;
711 tid = ath_get_skb_tid(sc, an, bf->bf_mpdu);
712 ath_tx_count_airtime(sc, sta, bf, ts);
713 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
714 tid->clear_ps_filter = true;
717 if (!bf_isampdu(bf)) {
719 info = IEEE80211_SKB_CB(bf->bf_mpdu);
720 memcpy(info->control.rates, bf->rates,
721 sizeof(info->control.rates));
722 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
723 ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts,
726 ath_tx_complete_buf(sc, bf, txq, bf_head, sta, ts, txok);
728 ath_tx_complete_aggr(sc, txq, bf, bf_head, sta, tid, ts, txok);
731 ath_txq_schedule(sc, txq);
734 static bool ath_lookup_legacy(struct ath_buf *bf)
737 struct ieee80211_tx_info *tx_info;
738 struct ieee80211_tx_rate *rates;
742 tx_info = IEEE80211_SKB_CB(skb);
743 rates = tx_info->control.rates;
745 for (i = 0; i < 4; i++) {
746 if (!rates[i].count || rates[i].idx < 0)
749 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
756 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
757 struct ath_atx_tid *tid)
760 struct ieee80211_tx_info *tx_info;
761 struct ieee80211_tx_rate *rates;
762 u32 max_4ms_framelen, frmlen;
763 u16 aggr_limit, bt_aggr_limit, legacy = 0;
764 int q = tid->txq->mac80211_qnum;
768 tx_info = IEEE80211_SKB_CB(skb);
772 * Find the lowest frame length among the rate series that will have a
773 * 4ms (or TXOP limited) transmit duration.
775 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
777 for (i = 0; i < 4; i++) {
783 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
788 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
793 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
796 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
797 max_4ms_framelen = min(max_4ms_framelen, frmlen);
801 * limit aggregate size by the minimum rate if rate selected is
802 * not a probe rate, if rate selected is a probe rate then
803 * avoid aggregation of this packet.
805 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
808 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
811 * Override the default aggregation limit for BTCOEX.
813 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
815 aggr_limit = bt_aggr_limit;
817 if (tid->an->maxampdu)
818 aggr_limit = min(aggr_limit, tid->an->maxampdu);
824 * Returns the number of delimiters to be added to
825 * meet the minimum required mpdudensity.
827 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
828 struct ath_buf *bf, u16 frmlen,
831 #define FIRST_DESC_NDELIMS 60
832 u32 nsymbits, nsymbols;
835 int width, streams, half_gi, ndelim, mindelim;
836 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
838 /* Select standard number of delimiters based on frame length alone */
839 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
842 * If encryption enabled, hardware requires some more padding between
844 * TODO - this could be improved to be dependent on the rate.
845 * The hardware can keep up at lower rates, but not higher rates
847 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
848 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
849 ndelim += ATH_AGGR_ENCRYPTDELIM;
852 * Add delimiter when using RTS/CTS with aggregation
853 * and non enterprise AR9003 card
855 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
856 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
857 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
860 * Convert desired mpdu density from microeconds to bytes based
861 * on highest rate in rate series (i.e. first rate) to determine
862 * required minimum length for subframe. Take into account
863 * whether high rate is 20 or 40Mhz and half or full GI.
865 * If there is no mpdu density restriction, no further calculation
869 if (tid->an->mpdudensity == 0)
872 rix = bf->rates[0].idx;
873 flags = bf->rates[0].flags;
874 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
875 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
878 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
880 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
885 streams = HT_RC_2_STREAMS(rix);
886 nsymbits = bits_per_symbol[rix % 8][width] * streams;
887 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
889 if (frmlen < minlen) {
890 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
891 ndelim = max(mindelim, ndelim);
898 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
899 struct ath_atx_tid *tid, struct ath_buf **buf)
901 struct ieee80211_tx_info *tx_info;
902 struct ath_frame_info *fi;
904 struct sk_buff *skb, *first_skb = NULL;
909 ret = ath_tid_dequeue(tid, &skb);
913 fi = get_frame_info(skb);
916 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
918 bf->bf_state.stale = false;
921 ath_txq_skb_done(sc, txq, skb);
922 ieee80211_free_txskb(sc->hw, skb);
929 tx_info = IEEE80211_SKB_CB(skb);
930 tx_info->flags &= ~(IEEE80211_TX_CTL_CLEAR_PS_FILT |
931 IEEE80211_TX_STATUS_EOSP);
934 * No aggregation session is running, but there may be frames
935 * from a previous session or a failed attempt in the queue.
936 * Send them out as normal data frames
939 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
941 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
942 bf->bf_state.bf_type = 0;
946 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
947 seqno = bf->bf_state.seqno;
949 /* do not step over block-ack window */
950 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
951 __skb_queue_tail(&tid->retry_q, skb);
953 /* If there are other skbs in the retry q, they are
954 * probably within the BAW, so loop immediately to get
955 * one of them. Otherwise the queue can get stuck. */
956 if (!skb_queue_is_first(&tid->retry_q, skb) &&
957 !WARN_ON(skb == first_skb)) {
958 if(!first_skb) /* infinite loop prevention */
965 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
966 struct ath_tx_status ts = {};
967 struct list_head bf_head;
969 INIT_LIST_HEAD(&bf_head);
970 list_add(&bf->list, &bf_head);
971 ath_tx_update_baw(sc, tid, bf);
972 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
977 ath_tx_addto_baw(sc, tid, bf);
987 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
988 struct ath_atx_tid *tid, struct list_head *bf_q,
989 struct ath_buf *bf_first)
991 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
992 struct ath_buf *bf = bf_first, *bf_prev = NULL;
993 int nframes = 0, ndelim, ret;
994 u16 aggr_limit = 0, al = 0, bpad = 0,
995 al_delta, h_baw = tid->baw_size / 2;
996 struct ieee80211_tx_info *tx_info;
997 struct ath_frame_info *fi;
1002 aggr_limit = ath_lookup_rate(sc, bf, tid);
1007 fi = get_frame_info(skb);
1009 /* do not exceed aggregation limit */
1010 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
1012 if (aggr_limit < al + bpad + al_delta ||
1013 ath_lookup_legacy(bf) || nframes >= h_baw)
1016 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1017 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
1018 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
1022 /* add padding for previous frame to aggregation length */
1023 al += bpad + al_delta;
1026 * Get the delimiters needed to meet the MPDU
1027 * density for this node.
1029 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
1031 bpad = PADBYTES(al_delta) + (ndelim << 2);
1036 /* link buffers of this frame to the aggregate */
1037 bf->bf_state.ndelim = ndelim;
1039 list_add_tail(&bf->list, bf_q);
1041 bf_prev->bf_next = bf;
1045 ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf);
1051 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1054 bf->bf_lastbf = bf_prev;
1056 if (bf == bf_prev) {
1057 al = get_frame_info(bf->bf_mpdu)->framelen;
1058 bf->bf_state.bf_type = BUF_AMPDU;
1060 TX_STAT_INC(sc, txq->axq_qnum, a_aggr);
1069 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1070 * width - 0 for 20 MHz, 1 for 40 MHz
1071 * half_gi - to use 4us v/s 3.6 us for symbol time
1073 u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1074 int width, int half_gi, bool shortPreamble)
1076 u32 nbits, nsymbits, duration, nsymbols;
1079 /* find number of symbols: PLCP + data */
1080 streams = HT_RC_2_STREAMS(rix);
1081 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1082 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1083 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1086 duration = SYMBOL_TIME(nsymbols);
1088 duration = SYMBOL_TIME_HALFGI(nsymbols);
1090 /* addup duration for legacy/ht training and signal fields */
1091 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1096 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1098 int streams = HT_RC_2_STREAMS(mcs);
1102 usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1103 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1104 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1105 bits -= OFDM_PLCP_BITS;
1113 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1115 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1118 /* 4ms is the default (and maximum) duration */
1119 if (!txop || txop > 4096)
1122 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1123 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1124 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1125 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1126 for (mcs = 0; mcs < 32; mcs++) {
1127 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1128 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1129 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1130 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1134 static u8 ath_get_rate_txpower(struct ath_softc *sc, struct ath_buf *bf,
1135 u8 rateidx, bool is_40, bool is_cck)
1138 struct sk_buff *skb;
1139 struct ath_frame_info *fi;
1140 struct ieee80211_tx_info *info;
1141 struct ath_hw *ah = sc->sc_ah;
1143 if (sc->tx99_state || !ah->tpc_enabled)
1144 return MAX_RATE_POWER;
1147 fi = get_frame_info(skb);
1148 info = IEEE80211_SKB_CB(skb);
1150 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1151 int txpower = fi->tx_power;
1155 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1156 u16 eeprom_rev = ah->eep_ops->get_eeprom_rev(ah);
1158 if (eeprom_rev >= AR5416_EEP_MINOR_VER_2) {
1160 struct modal_eep_header *pmodal;
1162 is_2ghz = info->band == NL80211_BAND_2GHZ;
1163 pmodal = &eep->modalHeader[is_2ghz];
1164 power_ht40delta = pmodal->ht40PowerIncForPdadc;
1166 power_ht40delta = 2;
1168 txpower += power_ht40delta;
1171 if (AR_SREV_9287(ah) || AR_SREV_9285(ah) ||
1173 txpower -= 2 * AR9287_PWR_TABLE_OFFSET_DB;
1174 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
1177 power_offset = ah->eep_ops->get_eeprom(ah,
1178 EEP_PWR_TABLE_OFFSET);
1179 txpower -= 2 * power_offset;
1182 if (OLC_FOR_AR9280_20_LATER && is_cck)
1185 txpower = max(txpower, 0);
1186 max_power = min_t(u8, ah->tx_power[rateidx], txpower);
1188 /* XXX: clamp minimum TX power at 1 for AR9160 since if
1189 * max_power is set to 0, frames are transmitted at max
1192 if (!max_power && !AR_SREV_9280_20_OR_LATER(ah))
1194 } else if (!bf->bf_state.bfs_paprd) {
1195 if (rateidx < 8 && (info->flags & IEEE80211_TX_CTL_STBC))
1196 max_power = min_t(u8, ah->tx_power_stbc[rateidx],
1199 max_power = min_t(u8, ah->tx_power[rateidx],
1202 max_power = ah->paprd_training_power;
1208 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1209 struct ath_tx_info *info, int len, bool rts)
1211 struct ath_hw *ah = sc->sc_ah;
1212 struct ath_common *common = ath9k_hw_common(ah);
1213 struct sk_buff *skb;
1214 struct ieee80211_tx_info *tx_info;
1215 struct ieee80211_tx_rate *rates;
1216 const struct ieee80211_rate *rate;
1217 struct ieee80211_hdr *hdr;
1218 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1219 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1224 tx_info = IEEE80211_SKB_CB(skb);
1226 hdr = (struct ieee80211_hdr *)skb->data;
1228 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1229 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1230 info->rtscts_rate = fi->rtscts_rate;
1232 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1233 bool is_40, is_sgi, is_sp, is_cck;
1236 if (!rates[i].count || (rates[i].idx < 0))
1240 info->rates[i].Tries = rates[i].count;
1243 * Handle RTS threshold for unaggregated HT frames.
1245 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1246 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1247 unlikely(rts_thresh != (u32) -1)) {
1248 if (!rts_thresh || (len > rts_thresh))
1252 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1253 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1254 info->flags |= ATH9K_TXDESC_RTSENA;
1255 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1256 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1257 info->flags |= ATH9K_TXDESC_CTSENA;
1260 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1261 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1262 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1263 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1265 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1266 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1267 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1269 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1271 info->rates[i].Rate = rix | 0x80;
1272 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1273 ah->txchainmask, info->rates[i].Rate);
1274 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1275 is_40, is_sgi, is_sp);
1276 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1277 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1279 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix,
1285 rate = &common->sbands[tx_info->band].bitrates[rates[i].idx];
1286 if ((tx_info->band == NL80211_BAND_2GHZ) &&
1287 !(rate->flags & IEEE80211_RATE_ERP_G))
1288 phy = WLAN_RC_PHY_CCK;
1290 phy = WLAN_RC_PHY_OFDM;
1292 info->rates[i].Rate = rate->hw_value;
1293 if (rate->hw_value_short) {
1294 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1295 info->rates[i].Rate |= rate->hw_value_short;
1300 if (bf->bf_state.bfs_paprd)
1301 info->rates[i].ChSel = ah->txchainmask;
1303 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1304 ah->txchainmask, info->rates[i].Rate);
1306 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1307 phy, rate->bitrate * 100, len, rix, is_sp);
1309 is_cck = IS_CCK_RATE(info->rates[i].Rate);
1310 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, false,
1314 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1315 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1316 info->flags &= ~ATH9K_TXDESC_RTSENA;
1318 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1319 if (info->flags & ATH9K_TXDESC_RTSENA)
1320 info->flags &= ~ATH9K_TXDESC_CTSENA;
1323 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1325 struct ieee80211_hdr *hdr;
1326 enum ath9k_pkt_type htype;
1329 hdr = (struct ieee80211_hdr *)skb->data;
1330 fc = hdr->frame_control;
1332 if (ieee80211_is_beacon(fc))
1333 htype = ATH9K_PKT_TYPE_BEACON;
1334 else if (ieee80211_is_probe_resp(fc))
1335 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1336 else if (ieee80211_is_atim(fc))
1337 htype = ATH9K_PKT_TYPE_ATIM;
1338 else if (ieee80211_is_pspoll(fc))
1339 htype = ATH9K_PKT_TYPE_PSPOLL;
1341 htype = ATH9K_PKT_TYPE_NORMAL;
1346 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1347 struct ath_txq *txq, int len)
1349 struct ath_hw *ah = sc->sc_ah;
1350 struct ath_buf *bf_first = NULL;
1351 struct ath_tx_info info;
1352 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1355 memset(&info, 0, sizeof(info));
1356 info.is_first = true;
1357 info.is_last = true;
1358 info.qcu = txq->axq_qnum;
1361 struct sk_buff *skb = bf->bf_mpdu;
1362 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1363 struct ath_frame_info *fi = get_frame_info(skb);
1364 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1366 info.type = get_hw_packet_type(skb);
1368 info.link = bf->bf_next->bf_daddr;
1370 info.link = (sc->tx99_state) ? bf->bf_daddr : 0;
1375 if (!sc->tx99_state)
1376 info.flags = ATH9K_TXDESC_INTREQ;
1377 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1378 txq == sc->tx.uapsdq)
1379 info.flags |= ATH9K_TXDESC_CLRDMASK;
1381 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1382 info.flags |= ATH9K_TXDESC_NOACK;
1383 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1384 info.flags |= ATH9K_TXDESC_LDPC;
1386 if (bf->bf_state.bfs_paprd)
1387 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1388 ATH9K_TXDESC_PAPRD_S;
1391 * mac80211 doesn't handle RTS threshold for HT because
1392 * the decision has to be taken based on AMPDU length
1393 * and aggregation is done entirely inside ath9k.
1394 * Set the RTS/CTS flag for the first subframe based
1397 if (aggr && (bf == bf_first) &&
1398 unlikely(rts_thresh != (u32) -1)) {
1400 * "len" is the size of the entire AMPDU.
1402 if (!rts_thresh || (len > rts_thresh))
1409 ath_buf_set_rate(sc, bf, &info, len, rts);
1412 info.buf_addr[0] = bf->bf_buf_addr;
1413 info.buf_len[0] = skb->len;
1414 info.pkt_len = fi->framelen;
1415 info.keyix = fi->keyix;
1416 info.keytype = fi->keytype;
1420 info.aggr = AGGR_BUF_FIRST;
1421 else if (bf == bf_first->bf_lastbf)
1422 info.aggr = AGGR_BUF_LAST;
1424 info.aggr = AGGR_BUF_MIDDLE;
1426 info.ndelim = bf->bf_state.ndelim;
1427 info.aggr_len = len;
1430 if (bf == bf_first->bf_lastbf)
1433 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1439 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1440 struct ath_atx_tid *tid, struct list_head *bf_q,
1441 struct ath_buf *bf_first)
1443 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1444 int nframes = 0, ret;
1447 struct ieee80211_tx_info *tx_info;
1450 list_add_tail(&bf->list, bf_q);
1452 bf_prev->bf_next = bf;
1458 ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf);
1462 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1463 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
1464 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1468 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1472 static int ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1473 struct ath_atx_tid *tid)
1475 struct ath_buf *bf = NULL;
1476 struct ieee80211_tx_info *tx_info;
1477 struct list_head bf_q;
1478 int aggr_len = 0, ret;
1481 INIT_LIST_HEAD(&bf_q);
1483 ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf);
1487 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1488 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1489 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1490 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1491 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1495 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1497 aggr_len = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf);
1499 ath_tx_form_burst(sc, txq, tid, &bf_q, bf);
1501 if (list_empty(&bf_q))
1504 if (tid->clear_ps_filter || tid->an->no_ps_filter) {
1505 tid->clear_ps_filter = false;
1506 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1509 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1510 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1514 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1517 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1518 struct ath_atx_tid *txtid;
1519 struct ath_txq *txq;
1520 struct ath_node *an;
1523 ath_dbg(common, XMIT, "%s called\n", __func__);
1525 an = (struct ath_node *)sta->drv_priv;
1526 txtid = ATH_AN_2_TID(an, tid);
1529 ath_txq_lock(sc, txq);
1531 /* update ampdu factor/density, they may have changed. This may happen
1532 * in HT IBSS when a beacon with HT-info is received after the station
1533 * has already been added.
1535 if (sta->ht_cap.ht_supported) {
1536 an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1537 sta->ht_cap.ampdu_factor)) - 1;
1538 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1539 an->mpdudensity = density;
1542 txtid->active = true;
1543 *ssn = txtid->seq_start = txtid->seq_next;
1544 txtid->bar_index = -1;
1546 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1547 txtid->baw_head = txtid->baw_tail = 0;
1549 ath_txq_unlock_complete(sc, txq);
1554 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1556 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1557 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1558 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1559 struct ath_txq *txq = txtid->txq;
1561 ath_dbg(common, XMIT, "%s called\n", __func__);
1563 ath_txq_lock(sc, txq);
1564 txtid->active = false;
1565 ath_tx_flush_tid(sc, txtid);
1566 ath_txq_unlock_complete(sc, txq);
1569 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1570 struct ath_node *an)
1572 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1573 struct ath_atx_tid *tid;
1576 ath_dbg(common, XMIT, "%s called\n", __func__);
1578 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
1579 tid = ath_node_to_tid(an, tidno);
1581 if (!skb_queue_empty(&tid->retry_q))
1582 ieee80211_sta_set_buffered(sta, tid->tidno, true);
1587 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1589 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1590 struct ath_atx_tid *tid;
1591 struct ath_txq *txq;
1594 ath_dbg(common, XMIT, "%s called\n", __func__);
1596 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
1597 tid = ath_node_to_tid(an, tidno);
1600 ath_txq_lock(sc, txq);
1601 tid->clear_ps_filter = true;
1602 if (!skb_queue_empty(&tid->retry_q)) {
1603 ath_tx_queue_tid(sc, tid);
1604 ath_txq_schedule(sc, txq);
1606 ath_txq_unlock_complete(sc, txq);
1613 ath9k_set_moredata(struct ath_softc *sc, struct ath_buf *bf, bool val)
1615 struct ieee80211_hdr *hdr;
1616 u16 mask = cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1617 u16 mask_val = mask * val;
1619 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
1620 if ((hdr->frame_control & mask) != mask_val) {
1621 hdr->frame_control = (hdr->frame_control & ~mask) | mask_val;
1622 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
1623 sizeof(*hdr), DMA_TO_DEVICE);
1627 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1628 struct ieee80211_sta *sta,
1629 u16 tids, int nframes,
1630 enum ieee80211_frame_release_type reason,
1633 struct ath_softc *sc = hw->priv;
1634 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1635 struct ath_txq *txq = sc->tx.uapsdq;
1636 struct ieee80211_tx_info *info;
1637 struct list_head bf_q;
1638 struct ath_buf *bf_tail = NULL, *bf = NULL;
1642 INIT_LIST_HEAD(&bf_q);
1643 for (i = 0; tids && nframes; i++, tids >>= 1) {
1644 struct ath_atx_tid *tid;
1649 tid = ATH_AN_2_TID(an, i);
1651 ath_txq_lock(sc, tid->txq);
1652 while (nframes > 0) {
1653 ret = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq,
1658 ath9k_set_moredata(sc, bf, true);
1659 list_add_tail(&bf->list, &bf_q);
1660 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1662 bf->bf_state.bf_type &= ~BUF_AGGR;
1664 bf_tail->bf_next = bf;
1669 TX_STAT_INC(sc, txq->axq_qnum, a_queued_hw);
1671 if (an->sta && skb_queue_empty(&tid->retry_q))
1672 ieee80211_sta_set_buffered(an->sta, i, false);
1674 ath_txq_unlock_complete(sc, tid->txq);
1677 if (list_empty(&bf_q))
1681 ath9k_set_moredata(sc, bf_tail, false);
1683 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1684 info->flags |= IEEE80211_TX_STATUS_EOSP;
1686 bf = list_first_entry(&bf_q, struct ath_buf, list);
1687 ath_txq_lock(sc, txq);
1688 ath_tx_fill_desc(sc, bf, txq, 0);
1689 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1690 ath_txq_unlock(sc, txq);
1693 /********************/
1694 /* Queue Management */
1695 /********************/
1697 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1699 struct ath_hw *ah = sc->sc_ah;
1700 struct ath9k_tx_queue_info qi;
1701 static const int subtype_txq_to_hwq[] = {
1702 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1703 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1704 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1705 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1709 memset(&qi, 0, sizeof(qi));
1710 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1711 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1712 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1713 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1714 qi.tqi_physCompBuf = 0;
1717 * Enable interrupts only for EOL and DESC conditions.
1718 * We mark tx descriptors to receive a DESC interrupt
1719 * when a tx queue gets deep; otherwise waiting for the
1720 * EOL to reap descriptors. Note that this is done to
1721 * reduce interrupt load and this only defers reaping
1722 * descriptors, never transmitting frames. Aside from
1723 * reducing interrupts this also permits more concurrency.
1724 * The only potential downside is if the tx queue backs
1725 * up in which case the top half of the kernel may backup
1726 * due to a lack of tx descriptors.
1728 * The UAPSD queue is an exception, since we take a desc-
1729 * based intr on the EOSP frames.
1731 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1732 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1734 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1735 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1737 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1738 TXQ_FLAG_TXDESCINT_ENABLE;
1740 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1741 if (axq_qnum == -1) {
1743 * NB: don't print a message, this happens
1744 * normally on parts with too few tx queues
1748 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1749 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1751 txq->axq_qnum = axq_qnum;
1752 txq->mac80211_qnum = -1;
1753 txq->axq_link = NULL;
1754 __skb_queue_head_init(&txq->complete_q);
1755 INIT_LIST_HEAD(&txq->axq_q);
1756 spin_lock_init(&txq->axq_lock);
1758 txq->axq_ampdu_depth = 0;
1759 txq->axq_tx_inprogress = false;
1760 sc->tx.txqsetup |= 1<<axq_qnum;
1762 txq->txq_headidx = txq->txq_tailidx = 0;
1763 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1764 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1766 return &sc->tx.txq[axq_qnum];
1769 int ath_txq_update(struct ath_softc *sc, int qnum,
1770 struct ath9k_tx_queue_info *qinfo)
1772 struct ath_hw *ah = sc->sc_ah;
1774 struct ath9k_tx_queue_info qi;
1776 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1778 ath9k_hw_get_txq_props(ah, qnum, &qi);
1779 qi.tqi_aifs = qinfo->tqi_aifs;
1780 qi.tqi_cwmin = qinfo->tqi_cwmin;
1781 qi.tqi_cwmax = qinfo->tqi_cwmax;
1782 qi.tqi_burstTime = qinfo->tqi_burstTime;
1783 qi.tqi_readyTime = qinfo->tqi_readyTime;
1785 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1786 ath_err(ath9k_hw_common(sc->sc_ah),
1787 "Unable to update hardware queue %u!\n", qnum);
1790 ath9k_hw_resettxqueue(ah, qnum);
1796 int ath_cabq_update(struct ath_softc *sc)
1798 struct ath9k_tx_queue_info qi;
1799 struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon;
1800 int qnum = sc->beacon.cabq->axq_qnum;
1802 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1804 qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) *
1805 ATH_CABQ_READY_TIME) / 100;
1806 ath_txq_update(sc, qnum, &qi);
1811 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1812 struct list_head *list)
1814 struct ath_buf *bf, *lastbf;
1815 struct list_head bf_head;
1816 struct ath_tx_status ts;
1818 memset(&ts, 0, sizeof(ts));
1819 ts.ts_status = ATH9K_TX_FLUSH;
1820 INIT_LIST_HEAD(&bf_head);
1822 while (!list_empty(list)) {
1823 bf = list_first_entry(list, struct ath_buf, list);
1825 if (bf->bf_state.stale) {
1826 list_del(&bf->list);
1828 ath_tx_return_buffer(sc, bf);
1832 lastbf = bf->bf_lastbf;
1833 list_cut_position(&bf_head, list, &lastbf->list);
1834 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1839 * Drain a given TX queue (could be Beacon or Data)
1841 * This assumes output has been stopped and
1842 * we do not need to block ath_tx_tasklet.
1844 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1847 ath_txq_lock(sc, txq);
1849 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1850 int idx = txq->txq_tailidx;
1852 while (!list_empty(&txq->txq_fifo[idx])) {
1853 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1855 INCR(idx, ATH_TXFIFO_DEPTH);
1857 txq->txq_tailidx = idx;
1860 txq->axq_link = NULL;
1861 txq->axq_tx_inprogress = false;
1862 ath_drain_txq_list(sc, txq, &txq->axq_q);
1864 ath_txq_unlock_complete(sc, txq);
1868 bool ath_drain_all_txq(struct ath_softc *sc)
1870 struct ath_hw *ah = sc->sc_ah;
1871 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1872 struct ath_txq *txq;
1876 if (test_bit(ATH_OP_INVALID, &common->op_flags))
1879 ath9k_hw_abort_tx_dma(ah);
1881 /* Check if any queue remains active */
1882 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1883 if (!ATH_TXQ_SETUP(sc, i))
1886 if (!sc->tx.txq[i].axq_depth)
1889 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1894 RESET_STAT_INC(sc, RESET_TX_DMA_ERROR);
1895 ath_dbg(common, RESET,
1896 "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1899 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1900 if (!ATH_TXQ_SETUP(sc, i))
1903 txq = &sc->tx.txq[i];
1904 ath_draintxq(sc, txq);
1910 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1912 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1913 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1916 /* For each acq entry, for each tid, try to schedule packets
1917 * for transmit until ampdu_depth has reached min Q depth.
1919 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1921 struct ieee80211_hw *hw = sc->hw;
1922 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1923 struct ieee80211_txq *queue;
1924 struct ath_atx_tid *tid;
1927 if (txq->mac80211_qnum < 0)
1930 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
1933 ieee80211_txq_schedule_start(hw, txq->mac80211_qnum);
1934 spin_lock_bh(&sc->chan_lock);
1937 if (sc->cur_chan->stopped)
1940 while ((queue = ieee80211_next_txq(hw, txq->mac80211_qnum))) {
1943 tid = (struct ath_atx_tid *)queue->drv_priv;
1945 ret = ath_tx_sched_aggr(sc, txq, tid);
1946 ath_dbg(common, QUEUE, "ath_tx_sched_aggr returned %d\n", ret);
1948 force = !skb_queue_empty(&tid->retry_q);
1949 ieee80211_return_txq(hw, queue, force);
1954 spin_unlock_bh(&sc->chan_lock);
1955 ieee80211_txq_schedule_end(hw, txq->mac80211_qnum);
1958 void ath_txq_schedule_all(struct ath_softc *sc)
1960 struct ath_txq *txq;
1963 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
1964 txq = sc->tx.txq_map[i];
1966 spin_lock_bh(&txq->axq_lock);
1967 ath_txq_schedule(sc, txq);
1968 spin_unlock_bh(&txq->axq_lock);
1977 * Insert a chain of ath_buf (descriptors) on a txq and
1978 * assume the descriptors are already chained together by caller.
1980 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1981 struct list_head *head, bool internal)
1983 struct ath_hw *ah = sc->sc_ah;
1984 struct ath_common *common = ath9k_hw_common(ah);
1985 struct ath_buf *bf, *bf_last;
1986 bool puttxbuf = false;
1990 * Insert the frame on the outbound list and
1991 * pass it on to the hardware.
1994 if (list_empty(head))
1997 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1998 bf = list_first_entry(head, struct ath_buf, list);
1999 bf_last = list_entry(head->prev, struct ath_buf, list);
2001 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
2002 txq->axq_qnum, txq->axq_depth);
2004 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
2005 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
2006 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
2009 list_splice_tail_init(head, &txq->axq_q);
2011 if (txq->axq_link) {
2012 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
2013 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
2014 txq->axq_qnum, txq->axq_link,
2015 ito64(bf->bf_daddr), bf->bf_desc);
2019 txq->axq_link = bf_last->bf_desc;
2023 TX_STAT_INC(sc, txq->axq_qnum, puttxbuf);
2024 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
2025 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
2026 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
2029 if (!edma || sc->tx99_state) {
2030 TX_STAT_INC(sc, txq->axq_qnum, txstart);
2031 ath9k_hw_txstart(ah, txq->axq_qnum);
2037 if (bf_is_ampdu_not_probing(bf))
2038 txq->axq_ampdu_depth++;
2040 bf_last = bf->bf_lastbf;
2041 bf = bf_last->bf_next;
2042 bf_last->bf_next = NULL;
2047 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
2048 struct ath_atx_tid *tid, struct sk_buff *skb)
2050 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2051 struct ath_frame_info *fi = get_frame_info(skb);
2052 struct list_head bf_head;
2053 struct ath_buf *bf = fi->bf;
2055 INIT_LIST_HEAD(&bf_head);
2056 list_add_tail(&bf->list, &bf_head);
2057 bf->bf_state.bf_type = 0;
2058 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
2059 bf->bf_state.bf_type = BUF_AMPDU;
2060 ath_tx_addto_baw(sc, tid, bf);
2065 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
2066 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
2067 TX_STAT_INC(sc, txq->axq_qnum, queued);
2070 static void setup_frame_info(struct ieee80211_hw *hw,
2071 struct ieee80211_sta *sta,
2072 struct sk_buff *skb,
2075 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2076 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
2077 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2078 const struct ieee80211_rate *rate;
2079 struct ath_frame_info *fi = get_frame_info(skb);
2080 struct ath_node *an = NULL;
2081 enum ath9k_key_type keytype;
2082 bool short_preamble = false;
2086 * We check if Short Preamble is needed for the CTS rate by
2087 * checking the BSS's global flag.
2088 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2090 if (tx_info->control.vif &&
2091 tx_info->control.vif->bss_conf.use_short_preamble)
2092 short_preamble = true;
2094 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2095 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
2098 an = (struct ath_node *) sta->drv_priv;
2100 if (tx_info->control.vif) {
2101 struct ieee80211_vif *vif = tx_info->control.vif;
2103 txpower = 2 * vif->bss_conf.txpower;
2105 struct ath_softc *sc = hw->priv;
2107 txpower = sc->cur_chan->cur_txpower;
2110 memset(fi, 0, sizeof(*fi));
2113 fi->keyix = hw_key->hw_key_idx;
2114 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2115 fi->keyix = an->ps_key;
2117 fi->keyix = ATH9K_TXKEYIX_INVALID;
2118 fi->keytype = keytype;
2119 fi->framelen = framelen;
2120 fi->tx_power = txpower;
2124 fi->rtscts_rate = rate->hw_value;
2126 fi->rtscts_rate |= rate->hw_value_short;
2129 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2131 struct ath_hw *ah = sc->sc_ah;
2132 struct ath9k_channel *curchan = ah->curchan;
2134 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
2135 (chainmask == 0x7) && (rate < 0x90))
2137 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2145 * Assign a descriptor (and sequence number if necessary,
2146 * and map buffer for DMA. Frees skb on error
2148 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2149 struct ath_txq *txq,
2150 struct ath_atx_tid *tid,
2151 struct sk_buff *skb)
2153 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2154 struct ath_frame_info *fi = get_frame_info(skb);
2155 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2160 bf = ath_tx_get_buffer(sc);
2162 ath_dbg(common, XMIT, "TX buffers are full\n");
2166 ATH_TXBUF_RESET(bf);
2168 if (tid && ieee80211_is_data_present(hdr->frame_control)) {
2169 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2170 seqno = tid->seq_next;
2171 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2174 hdr->seq_ctrl |= cpu_to_le16(fragno);
2176 if (!ieee80211_has_morefrags(hdr->frame_control))
2177 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2179 bf->bf_state.seqno = seqno;
2184 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2185 skb->len, DMA_TO_DEVICE);
2186 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2188 bf->bf_buf_addr = 0;
2189 ath_err(ath9k_hw_common(sc->sc_ah),
2190 "dma_mapping_error() on TX\n");
2191 ath_tx_return_buffer(sc, bf);
2200 void ath_assign_seq(struct ath_common *common, struct sk_buff *skb)
2202 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2203 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2204 struct ieee80211_vif *vif = info->control.vif;
2205 struct ath_vif *avp;
2207 if (!(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ))
2213 avp = (struct ath_vif *)vif->drv_priv;
2215 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2216 avp->seq_no += 0x10;
2218 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2219 hdr->seq_ctrl |= cpu_to_le16(avp->seq_no);
2222 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2223 struct ath_tx_control *txctl)
2225 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2226 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2227 struct ieee80211_sta *sta = txctl->sta;
2228 struct ieee80211_vif *vif = info->control.vif;
2229 struct ath_vif *avp;
2230 struct ath_softc *sc = hw->priv;
2231 int frmlen = skb->len + FCS_LEN;
2232 int padpos, padsize;
2234 /* NOTE: sta can be NULL according to net/mac80211.h */
2236 txctl->an = (struct ath_node *)sta->drv_priv;
2237 else if (vif && ieee80211_is_data(hdr->frame_control)) {
2238 avp = (void *)vif->drv_priv;
2239 txctl->an = &avp->mcast_node;
2242 if (info->control.hw_key)
2243 frmlen += info->control.hw_key->icv_len;
2245 ath_assign_seq(ath9k_hw_common(sc->sc_ah), skb);
2247 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2248 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2249 !ieee80211_is_data(hdr->frame_control))
2250 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2252 /* Add the padding after the header if this is not already done */
2253 padpos = ieee80211_hdrlen(hdr->frame_control);
2254 padsize = padpos & 3;
2255 if (padsize && skb->len > padpos) {
2256 if (skb_headroom(skb) < padsize)
2259 skb_push(skb, padsize);
2260 memmove(skb->data, skb->data + padsize, padpos);
2263 setup_frame_info(hw, sta, skb, frmlen);
2268 /* Upon failure caller should free skb */
2269 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2270 struct ath_tx_control *txctl)
2272 struct ieee80211_hdr *hdr;
2273 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2274 struct ieee80211_sta *sta = txctl->sta;
2275 struct ieee80211_vif *vif = info->control.vif;
2276 struct ath_frame_info *fi = get_frame_info(skb);
2277 struct ath_vif *avp = NULL;
2278 struct ath_softc *sc = hw->priv;
2279 struct ath_txq *txq = txctl->txq;
2280 struct ath_atx_tid *tid = NULL;
2281 struct ath_node *an = NULL;
2287 avp = (void *)vif->drv_priv;
2289 ps_resp = !!(info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE);
2291 ret = ath_tx_prepare(hw, skb, txctl);
2295 hdr = (struct ieee80211_hdr *) skb->data;
2297 * At this point, the vif, hw_key and sta pointers in the tx control
2298 * info are no longer valid (overwritten by the ath_frame_info data.
2301 q = skb_get_queue_mapping(skb);
2304 txq = sc->tx.uapsdq;
2307 an = (struct ath_node *) sta->drv_priv;
2308 tid = ath_get_skb_tid(sc, an, skb);
2311 ath_txq_lock(sc, txq);
2312 if (txq == sc->tx.txq_map[q]) {
2314 ++txq->pending_frames;
2317 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2319 ath_txq_skb_done(sc, txq, skb);
2321 dev_kfree_skb_any(skb);
2323 ieee80211_free_txskb(sc->hw, skb);
2327 bf->bf_state.bfs_paprd = txctl->paprd;
2330 bf->bf_state.bfs_paprd_timestamp = jiffies;
2332 ath_set_rates(vif, sta, bf);
2333 ath_tx_send_normal(sc, txq, tid, skb);
2336 ath_txq_unlock(sc, txq);
2341 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2342 struct sk_buff *skb)
2344 struct ath_softc *sc = hw->priv;
2345 struct ath_tx_control txctl = {
2346 .txq = sc->beacon.cabq
2348 struct ath_tx_info info = {};
2349 struct ath_buf *bf_tail = NULL;
2356 sc->cur_chan->beacon.beacon_interval * 1000 *
2357 sc->cur_chan->beacon.dtim_period / ATH_BCBUF;
2360 struct ath_frame_info *fi = get_frame_info(skb);
2362 if (ath_tx_prepare(hw, skb, &txctl))
2365 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2370 ath_set_rates(vif, NULL, bf);
2371 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2372 duration += info.rates[0].PktDuration;
2374 bf_tail->bf_next = bf;
2376 list_add_tail(&bf->list, &bf_q);
2380 if (duration > max_duration)
2383 skb = ieee80211_get_buffered_bc(hw, vif);
2387 ieee80211_free_txskb(hw, skb);
2389 if (list_empty(&bf_q))
2392 bf = list_last_entry(&bf_q, struct ath_buf, list);
2393 ath9k_set_moredata(sc, bf, false);
2395 bf = list_first_entry(&bf_q, struct ath_buf, list);
2396 ath_txq_lock(sc, txctl.txq);
2397 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2398 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2399 TX_STAT_INC(sc, txctl.txq->axq_qnum, queued);
2400 ath_txq_unlock(sc, txctl.txq);
2407 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2408 int tx_flags, struct ath_txq *txq,
2409 struct ieee80211_sta *sta)
2411 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2412 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2413 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2414 int padpos, padsize;
2415 unsigned long flags;
2417 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2419 if (sc->sc_ah->caldata)
2420 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
2422 if (!(tx_flags & ATH_TX_ERROR)) {
2423 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
2424 tx_info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
2426 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2429 if (tx_info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) {
2430 padpos = ieee80211_hdrlen(hdr->frame_control);
2431 padsize = padpos & 3;
2432 if (padsize && skb->len>padpos+padsize) {
2434 * Remove MAC header padding before giving the frame back to
2437 memmove(skb->data + padsize, skb->data, padpos);
2438 skb_pull(skb, padsize);
2442 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2443 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2444 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2446 "Going back to sleep after having received TX status (0x%lx)\n",
2447 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2449 PS_WAIT_FOR_PSPOLL_DATA |
2450 PS_WAIT_FOR_TX_ACK));
2452 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2454 ath_txq_skb_done(sc, txq, skb);
2455 tx_info->status.status_driver_data[0] = sta;
2456 __skb_queue_tail(&txq->complete_q, skb);
2459 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2460 struct ath_txq *txq, struct list_head *bf_q,
2461 struct ieee80211_sta *sta,
2462 struct ath_tx_status *ts, int txok)
2464 struct sk_buff *skb = bf->bf_mpdu;
2465 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2466 unsigned long flags;
2470 tx_flags |= ATH_TX_ERROR;
2472 if (ts->ts_status & ATH9K_TXERR_FILT)
2473 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2475 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2476 bf->bf_buf_addr = 0;
2478 goto skip_tx_complete;
2480 if (bf->bf_state.bfs_paprd) {
2481 if (time_after(jiffies,
2482 bf->bf_state.bfs_paprd_timestamp +
2483 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2484 dev_kfree_skb_any(skb);
2486 complete(&sc->paprd_complete);
2488 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2489 ath_tx_complete(sc, skb, tx_flags, txq, sta);
2492 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2493 * accidentally reference it later.
2498 * Return the list of ath_buf of this mpdu to free queue
2500 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2501 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2502 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2505 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2506 struct ath_tx_status *ts, int nframes, int nbad,
2509 struct sk_buff *skb = bf->bf_mpdu;
2510 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2511 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2512 struct ieee80211_hw *hw = sc->hw;
2513 struct ath_hw *ah = sc->sc_ah;
2517 tx_info->status.ack_signal = ts->ts_rssi;
2519 tx_rateindex = ts->ts_rateindex;
2520 WARN_ON(tx_rateindex >= hw->max_rates);
2522 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2523 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2525 BUG_ON(nbad > nframes);
2527 tx_info->status.ampdu_len = nframes;
2528 tx_info->status.ampdu_ack_len = nframes - nbad;
2530 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2531 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2533 * If an underrun error is seen assume it as an excessive
2534 * retry only if max frame trigger level has been reached
2535 * (2 KB for single stream, and 4 KB for dual stream).
2536 * Adjust the long retry as if the frame was tried
2537 * hw->max_rate_tries times to affect how rate control updates
2538 * PER for the failed rate.
2539 * In case of congestion on the bus penalizing this type of
2540 * underruns should help hardware actually transmit new frames
2541 * successfully by eventually preferring slower rates.
2542 * This itself should also alleviate congestion on the bus.
2544 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2545 ATH9K_TX_DELIM_UNDERRUN)) &&
2546 ieee80211_is_data(hdr->frame_control) &&
2547 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2548 tx_info->status.rates[tx_rateindex].count =
2552 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2553 tx_info->status.rates[i].count = 0;
2554 tx_info->status.rates[i].idx = -1;
2557 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2559 /* we report airtime in ath_tx_count_airtime(), don't report twice */
2560 tx_info->status.tx_time = 0;
2563 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2565 struct ath_hw *ah = sc->sc_ah;
2566 struct ath_common *common = ath9k_hw_common(ah);
2567 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2568 struct list_head bf_head;
2569 struct ath_desc *ds;
2570 struct ath_tx_status ts;
2573 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2574 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2577 ath_txq_lock(sc, txq);
2579 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2582 if (list_empty(&txq->axq_q)) {
2583 txq->axq_link = NULL;
2584 ath_txq_schedule(sc, txq);
2587 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2590 * There is a race condition that a BH gets scheduled
2591 * after sw writes TxE and before hw re-load the last
2592 * descriptor to get the newly chained one.
2593 * Software must keep the last DONE descriptor as a
2594 * holding descriptor - software does so by marking
2595 * it with the STALE flag.
2598 if (bf->bf_state.stale) {
2600 if (list_is_last(&bf_held->list, &txq->axq_q))
2603 bf = list_entry(bf_held->list.next, struct ath_buf,
2607 lastbf = bf->bf_lastbf;
2608 ds = lastbf->bf_desc;
2610 memset(&ts, 0, sizeof(ts));
2611 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2612 if (status == -EINPROGRESS)
2615 TX_STAT_INC(sc, txq->axq_qnum, txprocdesc);
2618 * Remove ath_buf's of the same transmit unit from txq,
2619 * however leave the last descriptor back as the holding
2620 * descriptor for hw.
2622 lastbf->bf_state.stale = true;
2623 INIT_LIST_HEAD(&bf_head);
2624 if (!list_is_singular(&lastbf->list))
2625 list_cut_position(&bf_head,
2626 &txq->axq_q, lastbf->list.prev);
2629 list_del(&bf_held->list);
2630 ath_tx_return_buffer(sc, bf_held);
2633 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2635 ath_txq_unlock_complete(sc, txq);
2638 void ath_tx_tasklet(struct ath_softc *sc)
2640 struct ath_hw *ah = sc->sc_ah;
2641 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2645 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2646 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2647 ath_tx_processq(sc, &sc->tx.txq[i]);
2652 void ath_tx_edma_tasklet(struct ath_softc *sc)
2654 struct ath_tx_status ts;
2655 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2656 struct ath_hw *ah = sc->sc_ah;
2657 struct ath_txq *txq;
2658 struct ath_buf *bf, *lastbf;
2659 struct list_head bf_head;
2660 struct list_head *fifo_list;
2665 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2668 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2669 if (status == -EINPROGRESS)
2671 if (status == -EIO) {
2672 ath_dbg(common, XMIT, "Error processing tx status\n");
2676 /* Process beacon completions separately */
2677 if (ts.qid == sc->beacon.beaconq) {
2678 sc->beacon.tx_processed = true;
2679 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2681 if (ath9k_is_chanctx_enabled()) {
2682 ath_chanctx_event(sc, NULL,
2683 ATH_CHANCTX_EVENT_BEACON_SENT);
2686 ath9k_csa_update(sc);
2690 txq = &sc->tx.txq[ts.qid];
2692 ath_txq_lock(sc, txq);
2694 TX_STAT_INC(sc, txq->axq_qnum, txprocdesc);
2696 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2697 if (list_empty(fifo_list)) {
2698 ath_txq_unlock(sc, txq);
2702 bf = list_first_entry(fifo_list, struct ath_buf, list);
2703 if (bf->bf_state.stale) {
2704 list_del(&bf->list);
2705 ath_tx_return_buffer(sc, bf);
2706 bf = list_first_entry(fifo_list, struct ath_buf, list);
2709 lastbf = bf->bf_lastbf;
2711 INIT_LIST_HEAD(&bf_head);
2712 if (list_is_last(&lastbf->list, fifo_list)) {
2713 list_splice_tail_init(fifo_list, &bf_head);
2714 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2716 if (!list_empty(&txq->axq_q)) {
2717 struct list_head bf_q;
2719 INIT_LIST_HEAD(&bf_q);
2720 txq->axq_link = NULL;
2721 list_splice_tail_init(&txq->axq_q, &bf_q);
2722 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2725 lastbf->bf_state.stale = true;
2727 list_cut_position(&bf_head, fifo_list,
2731 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2732 ath_txq_unlock_complete(sc, txq);
2741 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2743 struct ath_descdma *dd = &sc->txsdma;
2744 u8 txs_len = sc->sc_ah->caps.txs_len;
2746 dd->dd_desc_len = size * txs_len;
2747 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2748 &dd->dd_desc_paddr, GFP_KERNEL);
2755 static int ath_tx_edma_init(struct ath_softc *sc)
2759 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2761 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2762 sc->txsdma.dd_desc_paddr,
2763 ATH_TXSTATUS_RING_SIZE);
2768 int ath_tx_init(struct ath_softc *sc, int nbufs)
2770 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2773 spin_lock_init(&sc->tx.txbuflock);
2775 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2779 "Failed to allocate tx descriptors: %d\n", error);
2783 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2784 "beacon", ATH_BCBUF, 1, 1);
2787 "Failed to allocate beacon descriptors: %d\n", error);
2791 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2792 error = ath_tx_edma_init(sc);
2797 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2799 struct ath_atx_tid *tid;
2802 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
2803 tid = ath_node_to_tid(an, tidno);
2806 tid->seq_start = tid->seq_next = 0;
2807 tid->baw_size = WME_MAX_BA;
2808 tid->baw_head = tid->baw_tail = 0;
2809 tid->active = false;
2810 tid->clear_ps_filter = true;
2811 __skb_queue_head_init(&tid->retry_q);
2812 INIT_LIST_HEAD(&tid->list);
2813 acno = TID_TO_WME_AC(tidno);
2814 tid->txq = sc->tx.txq_map[acno];
2817 break; /* just one multicast ath_atx_tid */
2821 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2823 struct ath_atx_tid *tid;
2824 struct ath_txq *txq;
2829 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
2830 tid = ath_node_to_tid(an, tidno);
2833 ath_txq_lock(sc, txq);
2835 if (!list_empty(&tid->list))
2836 list_del_init(&tid->list);
2838 ath_tid_drain(sc, txq, tid);
2839 tid->active = false;
2841 ath_txq_unlock(sc, txq);
2844 break; /* just one multicast ath_atx_tid */
2850 #ifdef CONFIG_ATH9K_TX99
2852 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
2853 struct ath_tx_control *txctl)
2855 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2856 struct ath_frame_info *fi = get_frame_info(skb);
2857 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2859 int padpos, padsize;
2861 padpos = ieee80211_hdrlen(hdr->frame_control);
2862 padsize = padpos & 3;
2864 if (padsize && skb->len > padpos) {
2865 if (skb_headroom(skb) < padsize) {
2866 ath_dbg(common, XMIT,
2867 "tx99 padding failed\n");
2871 skb_push(skb, padsize);
2872 memmove(skb->data, skb->data + padsize, padpos);
2875 fi->keyix = ATH9K_TXKEYIX_INVALID;
2876 fi->framelen = skb->len + FCS_LEN;
2877 fi->keytype = ATH9K_KEY_TYPE_CLEAR;
2879 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb);
2881 ath_dbg(common, XMIT, "tx99 buffer setup failed\n");
2885 ath_set_rates(sc->tx99_vif, NULL, bf);
2887 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr);
2888 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum);
2890 ath_tx_send_normal(sc, txctl->txq, NULL, skb);
2895 #endif /* CONFIG_ATH9K_TX99 */