drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*******************************************************************************
   3   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   4   ST Ethernet IPs are built around a Synopsys IP Core.
   5
   6         Copyright(C) 2007-2011 STMicroelectronics Ltd
   7
   8
   9   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  10
  11   Documentation available at:
  12         http://www.stlinux.com
  13   Support available at:
  14         https://bugzilla.stlinux.com/
  15 *******************************************************************************/
  16
  17 #include <linux/clk.h>
  18 #include <linux/kernel.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ip.h>
  21 #include <linux/tcp.h>
  22 #include <linux/skbuff.h>
  23 #include <linux/ethtool.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/crc32.h>
  26 #include <linux/mii.h>
  27 #include <linux/if.h>
  28 #include <linux/if_vlan.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/slab.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/prefetch.h>
  33 #include <linux/pinctrl/consumer.h>
  34 #ifdef CONFIG_DEBUG_FS
  35 #include <linux/debugfs.h>
  36 #include <linux/seq_file.h>
  37 #endif /* CONFIG_DEBUG_FS */
  38 #include <linux/net_tstamp.h>
  39 #include <linux/phylink.h>
  40 #include <linux/udp.h>
  41 #include <linux/bpf_trace.h>
  42 #include <net/pkt_cls.h>
  43 #include <net/xdp_sock_drv.h>
  44 #include "stmmac_ptp.h"
  45 #include "stmmac.h"
  46 #include "stmmac_xdp.h"
  47 #include <linux/reset.h>
  48 #include <linux/of_mdio.h>
  49 #include "dwmac1000.h"
  50 #include "dwxgmac2.h"
  51 #include "hwif.h"
  52
  53 #define STMMAC_ALIGN(x)         ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16)
  54 #define TSO_MAX_BUFF_SIZE       (SZ_16K - 1)
  55
  56 /* Module parameters */
  57 #define TX_TIMEO        5000
  58 static int watchdog = TX_TIMEO;
  59 module_param(watchdog, int, 0644);
  60 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  61
  62 static int debug = -1;
  63 module_param(debug, int, 0644);
  64 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  65
  66 static int phyaddr = -1;
  67 module_param(phyaddr, int, 0444);
  68 MODULE_PARM_DESC(phyaddr, "Physical device address");
  69
  70 #define STMMAC_TX_THRESH(x)     ((x)->dma_tx_size / 4)
  71 #define STMMAC_RX_THRESH(x)     ((x)->dma_rx_size / 4)
  72
  73 /* Limit to make sure XDP TX and slow path can coexist */
  74 #define STMMAC_XSK_TX_BUDGET_MAX        256
  75 #define STMMAC_TX_XSK_AVAIL             16
  76 #define STMMAC_RX_FILL_BATCH            16
  77
  78 #define STMMAC_XDP_PASS         0
  79 #define STMMAC_XDP_CONSUMED     BIT(0)
  80 #define STMMAC_XDP_TX           BIT(1)
  81 #define STMMAC_XDP_REDIRECT     BIT(2)
  82
  83 static int flow_ctrl = FLOW_AUTO;
  84 module_param(flow_ctrl, int, 0644);
  85 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  86
  87 static int pause = PAUSE_TIME;
  88 module_param(pause, int, 0644);
  89 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  90
  91 #define TC_DEFAULT 64
  92 static int tc = TC_DEFAULT;
  93 module_param(tc, int, 0644);
  94 MODULE_PARM_DESC(tc, "DMA threshold control value");
  95
  96 #define DEFAULT_BUFSIZE 1536
  97 static int buf_sz = DEFAULT_BUFSIZE;
  98 module_param(buf_sz, int, 0644);
  99 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 100
 101 #define STMMAC_RX_COPYBREAK     256
 102
 103 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 104                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 105                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 106
 107 #define STMMAC_DEFAULT_LPI_TIMER        1000
 108 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 109 module_param(eee_timer, int, 0644);
 110 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 111 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x))
 112
 113 /* By default the driver will use the ring mode to manage tx and rx descriptors,
 114  * but allow user to force to use the chain instead of the ring
 115  */
 116 static unsigned int chain_mode;
 117 module_param(chain_mode, int, 0444);
 118 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 119
 120 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 121 /* For MSI interrupts handling */
 122 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id);
 123 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id);
 124 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data);
 125 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data);
 126 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue);
 127 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue);
 128
 129 #ifdef CONFIG_DEBUG_FS
 130 static const struct net_device_ops stmmac_netdev_ops;
 131 static void stmmac_init_fs(struct net_device *dev);
 132 static void stmmac_exit_fs(struct net_device *dev);
 133 #endif
 134
 135 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC))
 136
 137 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled)
 138 {
 139         int ret = 0;
 140
 141         if (enabled) {
 142                 ret = clk_prepare_enable(priv->plat->stmmac_clk);
 143                 if (ret)
 144                         return ret;
 145                 ret = clk_prepare_enable(priv->plat->pclk);
 146                 if (ret) {
 147                         clk_disable_unprepare(priv->plat->stmmac_clk);
 148                         return ret;
 149                 }
 150                 if (priv->plat->clks_config) {
 151                         ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled);
 152                         if (ret) {
 153                                 clk_disable_unprepare(priv->plat->stmmac_clk);
 154                                 clk_disable_unprepare(priv->plat->pclk);
 155                                 return ret;
 156                         }
 157                 }
 158         } else {
 159                 clk_disable_unprepare(priv->plat->stmmac_clk);
 160                 clk_disable_unprepare(priv->plat->pclk);
 161                 if (priv->plat->clks_config)
 162                         priv->plat->clks_config(priv->plat->bsp_priv, enabled);
 163         }
 164
 165         return ret;
 166 }
 167 EXPORT_SYMBOL_GPL(stmmac_bus_clks_config);
 168
 169 /**
 170  * stmmac_verify_args - verify the driver parameters.
 171  * Description: it checks the driver parameters and set a default in case of
 172  * errors.
 173  */
 174 static void stmmac_verify_args(void)
 175 {
 176         if (unlikely(watchdog < 0))
 177                 watchdog = TX_TIMEO;
 178         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
 179                 buf_sz = DEFAULT_BUFSIZE;
 180         if (unlikely(flow_ctrl > 1))
 181                 flow_ctrl = FLOW_AUTO;
 182         else if (likely(flow_ctrl < 0))
 183                 flow_ctrl = FLOW_OFF;
 184         if (unlikely((pause < 0) || (pause > 0xffff)))
 185                 pause = PAUSE_TIME;
 186         if (eee_timer < 0)
 187                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 188 }
 189
 190 static void __stmmac_disable_all_queues(struct stmmac_priv *priv)
 191 {
 192         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 193         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 194         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 195         u32 queue;
 196
 197         for (queue = 0; queue < maxq; queue++) {
 198                 struct stmmac_channel *ch = &priv->channel[queue];
 199
 200                 if (stmmac_xdp_is_enabled(priv) &&
 201                     test_bit(queue, priv->af_xdp_zc_qps)) {
 202                         napi_disable(&ch->rxtx_napi);
 203                         continue;
 204                 }
 205
 206                 if (queue < rx_queues_cnt)
 207                         napi_disable(&ch->rx_napi);
 208                 if (queue < tx_queues_cnt)
 209                         napi_disable(&ch->tx_napi);
 210         }
 211 }
 212
 213 /**
 214  * stmmac_disable_all_queues - Disable all queues
 215  * @priv: driver private structure
 216  */
 217 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
 218 {
 219         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 220         struct stmmac_rx_queue *rx_q;
 221         u32 queue;
 222
 223         /* synchronize_rcu() needed for pending XDP buffers to drain */
 224         for (queue = 0; queue < rx_queues_cnt; queue++) {
 225                 rx_q = &priv->rx_queue[queue];
 226                 if (rx_q->xsk_pool) {
 227                         synchronize_rcu();
 228                         break;
 229                 }
 230         }
 231
 232         __stmmac_disable_all_queues(priv);
 233 }
 234
 235 /**
 236  * stmmac_enable_all_queues - Enable all queues
 237  * @priv: driver private structure
 238  */
 239 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
 240 {
 241         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 242         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 243         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 244         u32 queue;
 245
 246         for (queue = 0; queue < maxq; queue++) {
 247                 struct stmmac_channel *ch = &priv->channel[queue];
 248
 249                 if (stmmac_xdp_is_enabled(priv) &&
 250                     test_bit(queue, priv->af_xdp_zc_qps)) {
 251                         napi_enable(&ch->rxtx_napi);
 252                         continue;
 253                 }
 254
 255                 if (queue < rx_queues_cnt)
 256                         napi_enable(&ch->rx_napi);
 257                 if (queue < tx_queues_cnt)
 258                         napi_enable(&ch->tx_napi);
 259         }
 260 }
 261
 262 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
 263 {
 264         if (!test_bit(STMMAC_DOWN, &priv->state) &&
 265             !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
 266                 queue_work(priv->wq, &priv->service_task);
 267 }
 268
 269 static void stmmac_global_err(struct stmmac_priv *priv)
 270 {
 271         netif_carrier_off(priv->dev);
 272         set_bit(STMMAC_RESET_REQUESTED, &priv->state);
 273         stmmac_service_event_schedule(priv);
 274 }
 275
 276 /**
 277  * stmmac_clk_csr_set - dynamically set the MDC clock
 278  * @priv: driver private structure
 279  * Description: this is to dynamically set the MDC clock according to the csr
 280  * clock input.
 281  * Note:
 282  *      If a specific clk_csr value is passed from the platform
 283  *      this means that the CSR Clock Range selection cannot be
 284  *      changed at run-time and it is fixed (as reported in the driver
 285  *      documentation). Viceversa the driver will try to set the MDC
 286  *      clock dynamically according to the actual clock input.
 287  */
 288 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 289 {
 290         u32 clk_rate;
 291
 292         clk_rate = clk_get_rate(priv->plat->stmmac_clk);
 293
 294         /* Platform provided default clk_csr would be assumed valid
 295          * for all other cases except for the below mentioned ones.
 296          * For values higher than the IEEE 802.3 specified frequency
 297          * we can not estimate the proper divider as it is not known
 298          * the frequency of clk_csr_i. So we do not change the default
 299          * divider.
 300          */
 301         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 302                 if (clk_rate < CSR_F_35M)
 303                         priv->clk_csr = STMMAC_CSR_20_35M;
 304                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 305                         priv->clk_csr = STMMAC_CSR_35_60M;
 306                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 307                         priv->clk_csr = STMMAC_CSR_60_100M;
 308                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 309                         priv->clk_csr = STMMAC_CSR_100_150M;
 310                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 311                         priv->clk_csr = STMMAC_CSR_150_250M;
 312                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 313                         priv->clk_csr = STMMAC_CSR_250_300M;
 314         }
 315
 316         if (priv->plat->has_sun8i) {
 317                 if (clk_rate > 160000000)
 318                         priv->clk_csr = 0x03;
 319                 else if (clk_rate > 80000000)
 320                         priv->clk_csr = 0x02;
 321                 else if (clk_rate > 40000000)
 322                         priv->clk_csr = 0x01;
 323                 else
 324                         priv->clk_csr = 0;
 325         }
 326
 327         if (priv->plat->has_xgmac) {
 328                 if (clk_rate > 400000000)
 329                         priv->clk_csr = 0x5;
 330                 else if (clk_rate > 350000000)
 331                         priv->clk_csr = 0x4;
 332                 else if (clk_rate > 300000000)
 333                         priv->clk_csr = 0x3;
 334                 else if (clk_rate > 250000000)
 335                         priv->clk_csr = 0x2;
 336                 else if (clk_rate > 150000000)
 337                         priv->clk_csr = 0x1;
 338                 else
 339                         priv->clk_csr = 0x0;
 340         }
 341 }
 342
 343 static void print_pkt(unsigned char *buf, int len)
 344 {
 345         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
 346         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
 347 }
 348
 349 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
 350 {
 351         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 352         u32 avail;
 353
 354         if (tx_q->dirty_tx > tx_q->cur_tx)
 355                 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
 356         else
 357                 avail = priv->dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1;
 358
 359         return avail;
 360 }
 361
 362 /**
 363  * stmmac_rx_dirty - Get RX queue dirty
 364  * @priv: driver private structure
 365  * @queue: RX queue index
 366  */
 367 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
 368 {
 369         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
 370         u32 dirty;
 371
 372         if (rx_q->dirty_rx <= rx_q->cur_rx)
 373                 dirty = rx_q->cur_rx - rx_q->dirty_rx;
 374         else
 375                 dirty = priv->dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx;
 376
 377         return dirty;
 378 }
 379
 380 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en)
 381 {
 382         int tx_lpi_timer;
 383
 384         /* Clear/set the SW EEE timer flag based on LPI ET enablement */
 385         priv->eee_sw_timer_en = en ? 0 : 1;
 386         tx_lpi_timer  = en ? priv->tx_lpi_timer : 0;
 387         stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer);
 388 }
 389
 390 /**
 391  * stmmac_enable_eee_mode - check and enter in LPI mode
 392  * @priv: driver private structure
 393  * Description: this function is to verify and enter in LPI mode in case of
 394  * EEE.
 395  */
 396 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 397 {
 398         u32 tx_cnt = priv->plat->tx_queues_to_use;
 399         u32 queue;
 400
 401         /* check if all TX queues have the work finished */
 402         for (queue = 0; queue < tx_cnt; queue++) {
 403                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 404
 405                 if (tx_q->dirty_tx != tx_q->cur_tx)
 406                         return; /* still unfinished work */
 407         }
 408
 409         /* Check and enter in LPI mode */
 410         if (!priv->tx_path_in_lpi_mode)
 411                 stmmac_set_eee_mode(priv, priv->hw,
 412                                 priv->plat->en_tx_lpi_clockgating);
 413 }
 414
 415 /**
 416  * stmmac_disable_eee_mode - disable and exit from LPI mode
 417  * @priv: driver private structure
 418  * Description: this function is to exit and disable EEE in case of
 419  * LPI state is true. This is called by the xmit.
 420  */
 421 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 422 {
 423         if (!priv->eee_sw_timer_en) {
 424                 stmmac_lpi_entry_timer_config(priv, 0);
 425                 return;
 426         }
 427
 428         stmmac_reset_eee_mode(priv, priv->hw);
 429         del_timer_sync(&priv->eee_ctrl_timer);
 430         priv->tx_path_in_lpi_mode = false;
 431 }
 432
 433 /**
 434  * stmmac_eee_ctrl_timer - EEE TX SW timer.
 435  * @t:  timer_list struct containing private info
 436  * Description:
 437  *  if there is no data transfer and if we are not in LPI state,
 438  *  then MAC Transmitter can be moved to LPI state.
 439  */
 440 static void stmmac_eee_ctrl_timer(struct timer_list *t)
 441 {
 442         struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
 443
 444         stmmac_enable_eee_mode(priv);
 445         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer));
 446 }
 447
 448 /**
 449  * stmmac_eee_init - init EEE
 450  * @priv: driver private structure
 451  * Description:
 452  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 453  *  can also manage EEE, this function enable the LPI state and start related
 454  *  timer.
 455  */
 456 bool stmmac_eee_init(struct stmmac_priv *priv)
 457 {
 458         int eee_tw_timer = priv->eee_tw_timer;
 459
 460         /* Using PCS we cannot dial with the phy registers at this stage
 461          * so we do not support extra feature like EEE.
 462          */
 463         if (priv->hw->pcs == STMMAC_PCS_TBI ||
 464             priv->hw->pcs == STMMAC_PCS_RTBI)
 465                 return false;
 466
 467         /* Check if MAC core supports the EEE feature. */
 468         if (!priv->dma_cap.eee)
 469                 return false;
 470
 471         mutex_lock(&priv->lock);
 472
 473         /* Check if it needs to be deactivated */
 474         if (!priv->eee_active) {
 475                 if (priv->eee_enabled) {
 476                         netdev_dbg(priv->dev, "disable EEE\n");
 477                         stmmac_lpi_entry_timer_config(priv, 0);
 478                         del_timer_sync(&priv->eee_ctrl_timer);
 479                         stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer);
 480                 }
 481                 mutex_unlock(&priv->lock);
 482                 return false;
 483         }
 484
 485         if (priv->eee_active && !priv->eee_enabled) {
 486                 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0);
 487                 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
 488                                      eee_tw_timer);
 489         }
 490
 491         if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) {
 492                 del_timer_sync(&priv->eee_ctrl_timer);
 493                 priv->tx_path_in_lpi_mode = false;
 494                 stmmac_lpi_entry_timer_config(priv, 1);
 495         } else {
 496                 stmmac_lpi_entry_timer_config(priv, 0);
 497                 mod_timer(&priv->eee_ctrl_timer,
 498                           STMMAC_LPI_T(priv->tx_lpi_timer));
 499         }
 500
 501         mutex_unlock(&priv->lock);
 502         netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
 503         return true;
 504 }
 505
 506 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
 507  * @priv: driver private structure
 508  * @p : descriptor pointer
 509  * @skb : the socket buffer
 510  * Description :
 511  * This function will read timestamp from the descriptor & pass it to stack.
 512  * and also perform some sanity checks.
 513  */
 514 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 515                                    struct dma_desc *p, struct sk_buff *skb)
 516 {
 517         struct skb_shared_hwtstamps shhwtstamp;
 518         bool found = false;
 519         s64 adjust = 0;
 520         u64 ns = 0;
 521
 522         if (!priv->hwts_tx_en)
 523                 return;
 524
 525         /* exit if skb doesn't support hw tstamp */
 526         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 527                 return;
 528
 529         /* check tx tstamp status */
 530         if (stmmac_get_tx_timestamp_status(priv, p)) {
 531                 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
 532                 found = true;
 533         } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) {
 534                 found = true;
 535         }
 536
 537         if (found) {
 538                 /* Correct the clk domain crossing(CDC) error */
 539                 if (priv->plat->has_gmac4 && priv->plat->clk_ptp_rate) {
 540                         adjust += -(2 * (NSEC_PER_SEC /
 541                                          priv->plat->clk_ptp_rate));
 542                         ns += adjust;
 543                 }
 544
 545                 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 546                 shhwtstamp.hwtstamp = ns_to_ktime(ns);
 547
 548                 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
 549                 /* pass tstamp to stack */
 550                 skb_tstamp_tx(skb, &shhwtstamp);
 551         }
 552 }
 553
 554 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
 555  * @priv: driver private structure
 556  * @p : descriptor pointer
 557  * @np : next descriptor pointer
 558  * @skb : the socket buffer
 559  * Description :
 560  * This function will read received packet's timestamp from the descriptor
 561  * and pass it to stack. It also perform some sanity checks.
 562  */
 563 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
 564                                    struct dma_desc *np, struct sk_buff *skb)
 565 {
 566         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 567         struct dma_desc *desc = p;
 568         u64 adjust = 0;
 569         u64 ns = 0;
 570
 571         if (!priv->hwts_rx_en)
 572                 return;
 573         /* For GMAC4, the valid timestamp is from CTX next desc. */
 574         if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
 575                 desc = np;
 576
 577         /* Check if timestamp is available */
 578         if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
 579                 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
 580
 581                 /* Correct the clk domain crossing(CDC) error */
 582                 if (priv->plat->has_gmac4 && priv->plat->clk_ptp_rate) {
 583                         adjust += 2 * (NSEC_PER_SEC / priv->plat->clk_ptp_rate);
 584                         ns -= adjust;
 585                 }
 586
 587                 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
 588                 shhwtstamp = skb_hwtstamps(skb);
 589                 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 590                 shhwtstamp->hwtstamp = ns_to_ktime(ns);
 591         } else  {
 592                 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
 593         }
 594 }
 595
 596 /**
 597  *  stmmac_hwtstamp_set - control hardware timestamping.
 598  *  @dev: device pointer.
 599  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 600  *  a proprietary structure used to pass information to the driver.
 601  *  Description:
 602  *  This function configures the MAC to enable/disable both outgoing(TX)
 603  *  and incoming(RX) packets time stamping based on user input.
 604  *  Return Value:
 605  *  0 on success and an appropriate -ve integer on failure.
 606  */
 607 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
 608 {
 609         struct stmmac_priv *priv = netdev_priv(dev);
 610         struct hwtstamp_config config;
 611         struct timespec64 now;
 612         u64 temp = 0;
 613         u32 ptp_v2 = 0;
 614         u32 tstamp_all = 0;
 615         u32 ptp_over_ipv4_udp = 0;
 616         u32 ptp_over_ipv6_udp = 0;
 617         u32 ptp_over_ethernet = 0;
 618         u32 snap_type_sel = 0;
 619         u32 ts_master_en = 0;
 620         u32 ts_event_en = 0;
 621         u32 sec_inc = 0;
 622         u32 value = 0;
 623         bool xmac;
 624
 625         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 626
 627         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 628                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 629                 priv->hwts_tx_en = 0;
 630                 priv->hwts_rx_en = 0;
 631
 632                 return -EOPNOTSUPP;
 633         }
 634
 635         if (copy_from_user(&config, ifr->ifr_data,
 636                            sizeof(config)))
 637                 return -EFAULT;
 638
 639         netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 640                    __func__, config.flags, config.tx_type, config.rx_filter);
 641
 642         /* reserved for future extensions */
 643         if (config.flags)
 644                 return -EINVAL;
 645
 646         if (config.tx_type != HWTSTAMP_TX_OFF &&
 647             config.tx_type != HWTSTAMP_TX_ON)
 648                 return -ERANGE;
 649
 650         if (priv->adv_ts) {
 651                 switch (config.rx_filter) {
 652                 case HWTSTAMP_FILTER_NONE:
 653                         /* time stamp no incoming packet at all */
 654                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 655                         break;
 656
 657                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 658                         /* PTP v1, UDP, any kind of event packet */
 659                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 660                         /* 'xmac' hardware can support Sync, Pdelay_Req and
 661                          * Pdelay_resp by setting bit14 and bits17/16 to 01
 662                          * This leaves Delay_Req timestamps out.
 663                          * Enable all events *and* general purpose message
 664                          * timestamping
 665                          */
 666                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 667                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 668                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 669                         break;
 670
 671                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 672                         /* PTP v1, UDP, Sync packet */
 673                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 674                         /* take time stamp for SYNC messages only */
 675                         ts_event_en = PTP_TCR_TSEVNTENA;
 676
 677                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 678                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 679                         break;
 680
 681                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 682                         /* PTP v1, UDP, Delay_req packet */
 683                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 684                         /* take time stamp for Delay_Req messages only */
 685                         ts_master_en = PTP_TCR_TSMSTRENA;
 686                         ts_event_en = PTP_TCR_TSEVNTENA;
 687
 688                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 689                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 690                         break;
 691
 692                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 693                         /* PTP v2, UDP, any kind of event packet */
 694                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 695                         ptp_v2 = PTP_TCR_TSVER2ENA;
 696                         /* take time stamp for all event messages */
 697                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 698
 699                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 700                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 701                         break;
 702
 703                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 704                         /* PTP v2, UDP, Sync packet */
 705                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 706                         ptp_v2 = PTP_TCR_TSVER2ENA;
 707                         /* take time stamp for SYNC messages only */
 708                         ts_event_en = PTP_TCR_TSEVNTENA;
 709
 710                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 711                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 712                         break;
 713
 714                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 715                         /* PTP v2, UDP, Delay_req packet */
 716                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 717                         ptp_v2 = PTP_TCR_TSVER2ENA;
 718                         /* take time stamp for Delay_Req messages only */
 719                         ts_master_en = PTP_TCR_TSMSTRENA;
 720                         ts_event_en = PTP_TCR_TSEVNTENA;
 721
 722                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 723                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 724                         break;
 725
 726                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 727                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 728                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 729                         ptp_v2 = PTP_TCR_TSVER2ENA;
 730                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 731                         if (priv->synopsys_id != DWMAC_CORE_5_10)
 732                                 ts_event_en = PTP_TCR_TSEVNTENA;
 733                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 734                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 735                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 736                         break;
 737
 738                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 739                         /* PTP v2/802.AS1, any layer, Sync packet */
 740                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 741                         ptp_v2 = PTP_TCR_TSVER2ENA;
 742                         /* take time stamp for SYNC messages only */
 743                         ts_event_en = PTP_TCR_TSEVNTENA;
 744
 745                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 746                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 747                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 748                         break;
 749
 750                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 751                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 752                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 753                         ptp_v2 = PTP_TCR_TSVER2ENA;
 754                         /* take time stamp for Delay_Req messages only */
 755                         ts_master_en = PTP_TCR_TSMSTRENA;
 756                         ts_event_en = PTP_TCR_TSEVNTENA;
 757
 758                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 759                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 760                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 761                         break;
 762
 763                 case HWTSTAMP_FILTER_NTP_ALL:
 764                 case HWTSTAMP_FILTER_ALL:
 765                         /* time stamp any incoming packet */
 766                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 767                         tstamp_all = PTP_TCR_TSENALL;
 768                         break;
 769
 770                 default:
 771                         return -ERANGE;
 772                 }
 773         } else {
 774                 switch (config.rx_filter) {
 775                 case HWTSTAMP_FILTER_NONE:
 776                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 777                         break;
 778                 default:
 779                         /* PTP v1, UDP, any kind of event packet */
 780                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 781                         break;
 782                 }
 783         }
 784         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 785         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 786
 787         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 788                 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0);
 789         else {
 790                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 791                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 792                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 793                          ts_master_en | snap_type_sel);
 794                 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value);
 795
 796                 /* program Sub Second Increment reg */
 797                 stmmac_config_sub_second_increment(priv,
 798                                 priv->ptpaddr, priv->plat->clk_ptp_rate,
 799                                 xmac, &sec_inc);
 800                 temp = div_u64(1000000000ULL, sec_inc);
 801
 802                 /* Store sub second increment and flags for later use */
 803                 priv->sub_second_inc = sec_inc;
 804                 priv->systime_flags = value;
 805
 806                 /* calculate default added value:
 807                  * formula is :
 808                  * addend = (2^32)/freq_div_ratio;
 809                  * where, freq_div_ratio = 1e9ns/sec_inc
 810                  */
 811                 temp = (u64)(temp << 32);
 812                 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
 813                 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
 814
 815                 /* initialize system time */
 816                 ktime_get_real_ts64(&now);
 817
 818                 /* lower 32 bits of tv_sec are safe until y2106 */
 819                 stmmac_init_systime(priv, priv->ptpaddr,
 820                                 (u32)now.tv_sec, now.tv_nsec);
 821         }
 822
 823         memcpy(&priv->tstamp_config, &config, sizeof(config));
 824
 825         return copy_to_user(ifr->ifr_data, &config,
 826                             sizeof(config)) ? -EFAULT : 0;
 827 }
 828
 829 /**
 830  *  stmmac_hwtstamp_get - read hardware timestamping.
 831  *  @dev: device pointer.
 832  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 833  *  a proprietary structure used to pass information to the driver.
 834  *  Description:
 835  *  This function obtain the current hardware timestamping settings
 836  *  as requested.
 837  */
 838 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
 839 {
 840         struct stmmac_priv *priv = netdev_priv(dev);
 841         struct hwtstamp_config *config = &priv->tstamp_config;
 842
 843         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 844                 return -EOPNOTSUPP;
 845
 846         return copy_to_user(ifr->ifr_data, config,
 847                             sizeof(*config)) ? -EFAULT : 0;
 848 }
 849
 850 /**
 851  * stmmac_init_ptp - init PTP
 852  * @priv: driver private structure
 853  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
 854  * This is done by looking at the HW cap. register.
 855  * This function also registers the ptp driver.
 856  */
 857 static int stmmac_init_ptp(struct stmmac_priv *priv)
 858 {
 859         bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 860
 861         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 862                 return -EOPNOTSUPP;
 863
 864         priv->adv_ts = 0;
 865         /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
 866         if (xmac && priv->dma_cap.atime_stamp)
 867                 priv->adv_ts = 1;
 868         /* Dwmac 3.x core with extend_desc can support adv_ts */
 869         else if (priv->extend_desc && priv->dma_cap.atime_stamp)
 870                 priv->adv_ts = 1;
 871
 872         if (priv->dma_cap.time_stamp)
 873                 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
 874
 875         if (priv->adv_ts)
 876                 netdev_info(priv->dev,
 877                             "IEEE 1588-2008 Advanced Timestamp supported\n");
 878
 879         priv->hwts_tx_en = 0;
 880         priv->hwts_rx_en = 0;
 881
 882         stmmac_ptp_register(priv);
 883
 884         return 0;
 885 }
 886
 887 static void stmmac_release_ptp(struct stmmac_priv *priv)
 888 {
 889         clk_disable_unprepare(priv->plat->clk_ptp_ref);
 890         stmmac_ptp_unregister(priv);
 891 }
 892
 893 /**
 894  *  stmmac_mac_flow_ctrl - Configure flow control in all queues
 895  *  @priv: driver private structure
 896  *  @duplex: duplex passed to the next function
 897  *  Description: It is used for configuring the flow control in all queues
 898  */
 899 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
 900 {
 901         u32 tx_cnt = priv->plat->tx_queues_to_use;
 902
 903         stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
 904                         priv->pause, tx_cnt);
 905 }
 906
 907 static void stmmac_validate(struct phylink_config *config,
 908                             unsigned long *supported,
 909                             struct phylink_link_state *state)
 910 {
 911         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 912         __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, };
 913         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 914         int tx_cnt = priv->plat->tx_queues_to_use;
 915         int max_speed = priv->plat->max_speed;
 916
 917         phylink_set(mac_supported, 10baseT_Half);
 918         phylink_set(mac_supported, 10baseT_Full);
 919         phylink_set(mac_supported, 100baseT_Half);
 920         phylink_set(mac_supported, 100baseT_Full);
 921         phylink_set(mac_supported, 1000baseT_Half);
 922         phylink_set(mac_supported, 1000baseT_Full);
 923         phylink_set(mac_supported, 1000baseKX_Full);
 924
 925         phylink_set(mac_supported, Autoneg);
 926         phylink_set(mac_supported, Pause);
 927         phylink_set(mac_supported, Asym_Pause);
 928         phylink_set_port_modes(mac_supported);
 929
 930         /* Cut down 1G if asked to */
 931         if ((max_speed > 0) && (max_speed < 1000)) {
 932                 phylink_set(mask, 1000baseT_Full);
 933                 phylink_set(mask, 1000baseX_Full);
 934         } else if (priv->plat->has_gmac4) {
 935                 if (!max_speed || max_speed >= 2500) {
 936                         phylink_set(mac_supported, 2500baseT_Full);
 937                         phylink_set(mac_supported, 2500baseX_Full);
 938                 }
 939         } else if (priv->plat->has_xgmac) {
 940                 if (!max_speed || (max_speed >= 2500)) {
 941                         phylink_set(mac_supported, 2500baseT_Full);
 942                         phylink_set(mac_supported, 2500baseX_Full);
 943                 }
 944                 if (!max_speed || (max_speed >= 5000)) {
 945                         phylink_set(mac_supported, 5000baseT_Full);
 946                 }
 947                 if (!max_speed || (max_speed >= 10000)) {
 948                         phylink_set(mac_supported, 10000baseSR_Full);
 949                         phylink_set(mac_supported, 10000baseLR_Full);
 950                         phylink_set(mac_supported, 10000baseER_Full);
 951                         phylink_set(mac_supported, 10000baseLRM_Full);
 952                         phylink_set(mac_supported, 10000baseT_Full);
 953                         phylink_set(mac_supported, 10000baseKX4_Full);
 954                         phylink_set(mac_supported, 10000baseKR_Full);
 955                 }
 956                 if (!max_speed || (max_speed >= 25000)) {
 957                         phylink_set(mac_supported, 25000baseCR_Full);
 958                         phylink_set(mac_supported, 25000baseKR_Full);
 959                         phylink_set(mac_supported, 25000baseSR_Full);
 960                 }
 961                 if (!max_speed || (max_speed >= 40000)) {
 962                         phylink_set(mac_supported, 40000baseKR4_Full);
 963                         phylink_set(mac_supported, 40000baseCR4_Full);
 964                         phylink_set(mac_supported, 40000baseSR4_Full);
 965                         phylink_set(mac_supported, 40000baseLR4_Full);
 966                 }
 967                 if (!max_speed || (max_speed >= 50000)) {
 968                         phylink_set(mac_supported, 50000baseCR2_Full);
 969                         phylink_set(mac_supported, 50000baseKR2_Full);
 970                         phylink_set(mac_supported, 50000baseSR2_Full);
 971                         phylink_set(mac_supported, 50000baseKR_Full);
 972                         phylink_set(mac_supported, 50000baseSR_Full);
 973                         phylink_set(mac_supported, 50000baseCR_Full);
 974                         phylink_set(mac_supported, 50000baseLR_ER_FR_Full);
 975                         phylink_set(mac_supported, 50000baseDR_Full);
 976                 }
 977                 if (!max_speed || (max_speed >= 100000)) {
 978                         phylink_set(mac_supported, 100000baseKR4_Full);
 979                         phylink_set(mac_supported, 100000baseSR4_Full);
 980                         phylink_set(mac_supported, 100000baseCR4_Full);
 981                         phylink_set(mac_supported, 100000baseLR4_ER4_Full);
 982                         phylink_set(mac_supported, 100000baseKR2_Full);
 983                         phylink_set(mac_supported, 100000baseSR2_Full);
 984                         phylink_set(mac_supported, 100000baseCR2_Full);
 985                         phylink_set(mac_supported, 100000baseLR2_ER2_FR2_Full);
 986                         phylink_set(mac_supported, 100000baseDR2_Full);
 987                 }
 988         }
 989
 990         /* Half-Duplex can only work with single queue */
 991         if (tx_cnt > 1) {
 992                 phylink_set(mask, 10baseT_Half);
 993                 phylink_set(mask, 100baseT_Half);
 994                 phylink_set(mask, 1000baseT_Half);
 995         }
 996
 997         linkmode_and(supported, supported, mac_supported);
 998         linkmode_andnot(supported, supported, mask);
 999
1000         linkmode_and(state->advertising, state->advertising, mac_supported);
1001         linkmode_andnot(state->advertising, state->advertising, mask);
1002
1003         /* If PCS is supported, check which modes it supports. */
1004         if (priv->hw->xpcs)
1005                 xpcs_validate(priv->hw->xpcs, supported, state);
1006 }
1007
1008 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
1009                               const struct phylink_link_state *state)
1010 {
1011         /* Nothing to do, xpcs_config() handles everything */
1012 }
1013
1014 static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up)
1015 {
1016         struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
1017         enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
1018         enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
1019         bool *hs_enable = &fpe_cfg->hs_enable;
1020
1021         if (is_up && *hs_enable) {
1022                 stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY);
1023         } else {
1024                 *lo_state = FPE_STATE_OFF;
1025                 *lp_state = FPE_STATE_OFF;
1026         }
1027 }
1028
1029 static void stmmac_mac_link_down(struct phylink_config *config,
1030                                  unsigned int mode, phy_interface_t interface)
1031 {
1032         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
1033
1034         stmmac_mac_set(priv, priv->ioaddr, false);
1035         priv->eee_active = false;
1036         priv->tx_lpi_enabled = false;
1037         stmmac_eee_init(priv);
1038         stmmac_set_eee_pls(priv, priv->hw, false);
1039
1040         if (priv->dma_cap.fpesel)
1041                 stmmac_fpe_link_state_handle(priv, false);
1042 }
1043
1044 static void stmmac_mac_link_up(struct phylink_config *config,
1045                                struct phy_device *phy,
1046                                unsigned int mode, phy_interface_t interface,
1047                                int speed, int duplex,
1048                                bool tx_pause, bool rx_pause)
1049 {
1050         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
1051         u32 ctrl;
1052
1053         ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
1054         ctrl &= ~priv->hw->link.speed_mask;
1055
1056         if (interface == PHY_INTERFACE_MODE_USXGMII) {
1057                 switch (speed) {
1058                 case SPEED_10000:
1059                         ctrl |= priv->hw->link.xgmii.speed10000;
1060                         break;
1061                 case SPEED_5000:
1062                         ctrl |= priv->hw->link.xgmii.speed5000;
1063                         break;
1064                 case SPEED_2500:
1065                         ctrl |= priv->hw->link.xgmii.speed2500;
1066                         break;
1067                 default:
1068                         return;
1069                 }
1070         } else if (interface == PHY_INTERFACE_MODE_XLGMII) {
1071                 switch (speed) {
1072                 case SPEED_100000:
1073                         ctrl |= priv->hw->link.xlgmii.speed100000;
1074                         break;
1075                 case SPEED_50000:
1076                         ctrl |= priv->hw->link.xlgmii.speed50000;
1077                         break;
1078                 case SPEED_40000:
1079                         ctrl |= priv->hw->link.xlgmii.speed40000;
1080                         break;
1081                 case SPEED_25000:
1082                         ctrl |= priv->hw->link.xlgmii.speed25000;
1083                         break;
1084                 case SPEED_10000:
1085                         ctrl |= priv->hw->link.xgmii.speed10000;
1086                         break;
1087                 case SPEED_2500:
1088                         ctrl |= priv->hw->link.speed2500;
1089                         break;
1090                 case SPEED_1000:
1091                         ctrl |= priv->hw->link.speed1000;
1092                         break;
1093                 default:
1094                         return;
1095                 }
1096         } else {
1097                 switch (speed) {
1098                 case SPEED_2500:
1099                         ctrl |= priv->hw->link.speed2500;
1100                         break;
1101                 case SPEED_1000:
1102                         ctrl |= priv->hw->link.speed1000;
1103                         break;
1104                 case SPEED_100:
1105                         ctrl |= priv->hw->link.speed100;
1106                         break;
1107                 case SPEED_10:
1108                         ctrl |= priv->hw->link.speed10;
1109                         break;
1110                 default:
1111                         return;
1112                 }
1113         }
1114
1115         priv->speed = speed;
1116
1117         if (priv->plat->fix_mac_speed)
1118                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed);
1119
1120         if (!duplex)
1121                 ctrl &= ~priv->hw->link.duplex;
1122         else
1123                 ctrl |= priv->hw->link.duplex;
1124
1125         /* Flow Control operation */
1126         if (tx_pause && rx_pause)
1127                 stmmac_mac_flow_ctrl(priv, duplex);
1128
1129         writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
1130
1131         stmmac_mac_set(priv, priv->ioaddr, true);
1132         if (phy && priv->dma_cap.eee) {
1133                 priv->eee_active = phy_init_eee(phy, 1) >= 0;
1134                 priv->eee_enabled = stmmac_eee_init(priv);
1135                 priv->tx_lpi_enabled = priv->eee_enabled;
1136                 stmmac_set_eee_pls(priv, priv->hw, true);
1137         }
1138
1139         if (priv->dma_cap.fpesel)
1140                 stmmac_fpe_link_state_handle(priv, true);
1141 }
1142
1143 static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
1144         .validate = stmmac_validate,
1145         .mac_config = stmmac_mac_config,
1146         .mac_link_down = stmmac_mac_link_down,
1147         .mac_link_up = stmmac_mac_link_up,
1148 };
1149
1150 /**
1151  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
1152  * @priv: driver private structure
1153  * Description: this is to verify if the HW supports the PCS.
1154  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
1155  * configured for the TBI, RTBI, or SGMII PHY interface.
1156  */
1157 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
1158 {
1159         int interface = priv->plat->interface;
1160
1161         if (priv->dma_cap.pcs) {
1162                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
1163                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1164                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1165                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
1166                         netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
1167                         priv->hw->pcs = STMMAC_PCS_RGMII;
1168                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
1169                         netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
1170                         priv->hw->pcs = STMMAC_PCS_SGMII;
1171                 }
1172         }
1173 }
1174
1175 /**
1176  * stmmac_init_phy - PHY initialization
1177  * @dev: net device structure
1178  * Description: it initializes the driver's PHY state, and attaches the PHY
1179  * to the mac driver.
1180  *  Return value:
1181  *  0 on success
1182  */
1183 static int stmmac_init_phy(struct net_device *dev)
1184 {
1185         struct stmmac_priv *priv = netdev_priv(dev);
1186         struct device_node *node;
1187         int ret;
1188
1189         node = priv->plat->phylink_node;
1190
1191         if (node)
1192                 ret = phylink_of_phy_connect(priv->phylink, node, 0);
1193
1194         /* Some DT bindings do not set-up the PHY handle. Let's try to
1195          * manually parse it
1196          */
1197         if (!node || ret) {
1198                 int addr = priv->plat->phy_addr;
1199                 struct phy_device *phydev;
1200
1201                 phydev = mdiobus_get_phy(priv->mii, addr);
1202                 if (!phydev) {
1203                         netdev_err(priv->dev, "no phy at addr %d\n", addr);
1204                         return -ENODEV;
1205                 }
1206
1207                 ret = phylink_connect_phy(priv->phylink, phydev);
1208         }
1209
1210         if (!priv->plat->pmt) {
1211                 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
1212
1213                 phylink_ethtool_get_wol(priv->phylink, &wol);
1214                 device_set_wakeup_capable(priv->device, !!wol.supported);
1215         }
1216
1217         return ret;
1218 }
1219
1220 static int stmmac_phy_setup(struct stmmac_priv *priv)
1221 {
1222         struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
1223         struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
1224         int mode = priv->plat->phy_interface;
1225         struct phylink *phylink;
1226
1227         priv->phylink_config.dev = &priv->dev->dev;
1228         priv->phylink_config.type = PHYLINK_NETDEV;
1229         priv->phylink_config.pcs_poll = true;
1230         if (priv->plat->mdio_bus_data)
1231                 priv->phylink_config.ovr_an_inband =
1232                         mdio_bus_data->xpcs_an_inband;
1233
1234         if (!fwnode)
1235                 fwnode = dev_fwnode(priv->device);
1236
1237         phylink = phylink_create(&priv->phylink_config, fwnode,
1238                                  mode, &stmmac_phylink_mac_ops);
1239         if (IS_ERR(phylink))
1240                 return PTR_ERR(phylink);
1241
1242         if (priv->hw->xpcs)
1243                 phylink_set_pcs(phylink, &priv->hw->xpcs->pcs);
1244
1245         priv->phylink = phylink;
1246         return 0;
1247 }
1248
1249 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
1250 {
1251         u32 rx_cnt = priv->plat->rx_queues_to_use;
1252         unsigned int desc_size;
1253         void *head_rx;
1254         u32 queue;
1255
1256         /* Display RX rings */
1257         for (queue = 0; queue < rx_cnt; queue++) {
1258                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1259
1260                 pr_info("\tRX Queue %u rings\n", queue);
1261
1262                 if (priv->extend_desc) {
1263                         head_rx = (void *)rx_q->dma_erx;
1264                         desc_size = sizeof(struct dma_extended_desc);
1265                 } else {
1266                         head_rx = (void *)rx_q->dma_rx;
1267                         desc_size = sizeof(struct dma_desc);
1268                 }
1269
1270                 /* Display RX ring */
1271                 stmmac_display_ring(priv, head_rx, priv->dma_rx_size, true,
1272                                     rx_q->dma_rx_phy, desc_size);
1273         }
1274 }
1275
1276 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1277 {
1278         u32 tx_cnt = priv->plat->tx_queues_to_use;
1279         unsigned int desc_size;
1280         void *head_tx;
1281         u32 queue;
1282
1283         /* Display TX rings */
1284         for (queue = 0; queue < tx_cnt; queue++) {
1285                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1286
1287                 pr_info("\tTX Queue %d rings\n", queue);
1288
1289                 if (priv->extend_desc) {
1290                         head_tx = (void *)tx_q->dma_etx;
1291                         desc_size = sizeof(struct dma_extended_desc);
1292                 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) {
1293                         head_tx = (void *)tx_q->dma_entx;
1294                         desc_size = sizeof(struct dma_edesc);
1295                 } else {
1296                         head_tx = (void *)tx_q->dma_tx;
1297                         desc_size = sizeof(struct dma_desc);
1298                 }
1299
1300                 stmmac_display_ring(priv, head_tx, priv->dma_tx_size, false,
1301                                     tx_q->dma_tx_phy, desc_size);
1302         }
1303 }
1304
1305 static void stmmac_display_rings(struct stmmac_priv *priv)
1306 {
1307         /* Display RX ring */
1308         stmmac_display_rx_rings(priv);
1309
1310         /* Display TX ring */
1311         stmmac_display_tx_rings(priv);
1312 }
1313
1314 static int stmmac_set_bfsize(int mtu, int bufsize)
1315 {
1316         int ret = bufsize;
1317
1318         if (mtu >= BUF_SIZE_8KiB)
1319                 ret = BUF_SIZE_16KiB;
1320         else if (mtu >= BUF_SIZE_4KiB)
1321                 ret = BUF_SIZE_8KiB;
1322         else if (mtu >= BUF_SIZE_2KiB)
1323                 ret = BUF_SIZE_4KiB;
1324         else if (mtu > DEFAULT_BUFSIZE)
1325                 ret = BUF_SIZE_2KiB;
1326         else
1327                 ret = DEFAULT_BUFSIZE;
1328
1329         return ret;
1330 }
1331
1332 /**
1333  * stmmac_clear_rx_descriptors - clear RX descriptors
1334  * @priv: driver private structure
1335  * @queue: RX queue index
1336  * Description: this function is called to clear the RX descriptors
1337  * in case of both basic and extended descriptors are used.
1338  */
1339 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1340 {
1341         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1342         int i;
1343
1344         /* Clear the RX descriptors */
1345         for (i = 0; i < priv->dma_rx_size; i++)
1346                 if (priv->extend_desc)
1347                         stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1348                                         priv->use_riwt, priv->mode,
1349                                         (i == priv->dma_rx_size - 1),
1350                                         priv->dma_buf_sz);
1351                 else
1352                         stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1353                                         priv->use_riwt, priv->mode,
1354                                         (i == priv->dma_rx_size - 1),
1355                                         priv->dma_buf_sz);
1356 }
1357
1358 /**
1359  * stmmac_clear_tx_descriptors - clear tx descriptors
1360  * @priv: driver private structure
1361  * @queue: TX queue index.
1362  * Description: this function is called to clear the TX descriptors
1363  * in case of both basic and extended descriptors are used.
1364  */
1365 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1366 {
1367         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1368         int i;
1369
1370         /* Clear the TX descriptors */
1371         for (i = 0; i < priv->dma_tx_size; i++) {
1372                 int last = (i == (priv->dma_tx_size - 1));
1373                 struct dma_desc *p;
1374
1375                 if (priv->extend_desc)
1376                         p = &tx_q->dma_etx[i].basic;
1377                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1378                         p = &tx_q->dma_entx[i].basic;
1379                 else
1380                         p = &tx_q->dma_tx[i];
1381
1382                 stmmac_init_tx_desc(priv, p, priv->mode, last);
1383         }
1384 }
1385
1386 /**
1387  * stmmac_clear_descriptors - clear descriptors
1388  * @priv: driver private structure
1389  * Description: this function is called to clear the TX and RX descriptors
1390  * in case of both basic and extended descriptors are used.
1391  */
1392 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1393 {
1394         u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1395         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1396         u32 queue;
1397
1398         /* Clear the RX descriptors */
1399         for (queue = 0; queue < rx_queue_cnt; queue++)
1400                 stmmac_clear_rx_descriptors(priv, queue);
1401
1402         /* Clear the TX descriptors */
1403         for (queue = 0; queue < tx_queue_cnt; queue++)
1404                 stmmac_clear_tx_descriptors(priv, queue);
1405 }
1406
1407 /**
1408  * stmmac_init_rx_buffers - init the RX descriptor buffer.
1409  * @priv: driver private structure
1410  * @p: descriptor pointer
1411  * @i: descriptor index
1412  * @flags: gfp flag
1413  * @queue: RX queue index
1414  * Description: this function is called to allocate a receive buffer, perform
1415  * the DMA mapping and init the descriptor.
1416  */
1417 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1418                                   int i, gfp_t flags, u32 queue)
1419 {
1420         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1421         struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1422
1423         if (!buf->page) {
1424                 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
1425                 if (!buf->page)
1426                         return -ENOMEM;
1427                 buf->page_offset = stmmac_rx_offset(priv);
1428         }
1429
1430         if (priv->sph && !buf->sec_page) {
1431                 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
1432                 if (!buf->sec_page)
1433                         return -ENOMEM;
1434
1435                 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
1436                 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true);
1437         } else {
1438                 buf->sec_page = NULL;
1439                 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false);
1440         }
1441
1442         buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset;
1443
1444         stmmac_set_desc_addr(priv, p, buf->addr);
1445         if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1446                 stmmac_init_desc3(priv, p);
1447
1448         return 0;
1449 }
1450
1451 /**
1452  * stmmac_free_rx_buffer - free RX dma buffers
1453  * @priv: private structure
1454  * @queue: RX queue index
1455  * @i: buffer index.
1456  */
1457 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1458 {
1459         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1460         struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1461
1462         if (buf->page)
1463                 page_pool_put_full_page(rx_q->page_pool, buf->page, false);
1464         buf->page = NULL;
1465
1466         if (buf->sec_page)
1467                 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false);
1468         buf->sec_page = NULL;
1469 }
1470
1471 /**
1472  * stmmac_free_tx_buffer - free RX dma buffers
1473  * @priv: private structure
1474  * @queue: RX queue index
1475  * @i: buffer index.
1476  */
1477 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1478 {
1479         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1480
1481         if (tx_q->tx_skbuff_dma[i].buf &&
1482             tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) {
1483                 if (tx_q->tx_skbuff_dma[i].map_as_page)
1484                         dma_unmap_page(priv->device,
1485                                        tx_q->tx_skbuff_dma[i].buf,
1486                                        tx_q->tx_skbuff_dma[i].len,
1487                                        DMA_TO_DEVICE);
1488                 else
1489                         dma_unmap_single(priv->device,
1490                                          tx_q->tx_skbuff_dma[i].buf,
1491                                          tx_q->tx_skbuff_dma[i].len,
1492                                          DMA_TO_DEVICE);
1493         }
1494
1495         if (tx_q->xdpf[i] &&
1496             (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX ||
1497              tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) {
1498                 xdp_return_frame(tx_q->xdpf[i]);
1499                 tx_q->xdpf[i] = NULL;
1500         }
1501
1502         if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX)
1503                 tx_q->xsk_frames_done++;
1504
1505         if (tx_q->tx_skbuff[i] &&
1506             tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) {
1507                 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1508                 tx_q->tx_skbuff[i] = NULL;
1509         }
1510
1511         tx_q->tx_skbuff_dma[i].buf = 0;
1512         tx_q->tx_skbuff_dma[i].map_as_page = false;
1513 }
1514
1515 /**
1516  * dma_free_rx_skbufs - free RX dma buffers
1517  * @priv: private structure
1518  * @queue: RX queue index
1519  */
1520 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1521 {
1522         int i;
1523
1524         for (i = 0; i < priv->dma_rx_size; i++)
1525                 stmmac_free_rx_buffer(priv, queue, i);
1526 }
1527
1528 static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv, u32 queue,
1529                                    gfp_t flags)
1530 {
1531         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1532         int i;
1533
1534         for (i = 0; i < priv->dma_rx_size; i++) {
1535                 struct dma_desc *p;
1536                 int ret;
1537
1538                 if (priv->extend_desc)
1539                         p = &((rx_q->dma_erx + i)->basic);
1540                 else
1541                         p = rx_q->dma_rx + i;
1542
1543                 ret = stmmac_init_rx_buffers(priv, p, i, flags,
1544                                              queue);
1545                 if (ret)
1546                         return ret;
1547
1548                 rx_q->buf_alloc_num++;
1549         }
1550
1551         return 0;
1552 }
1553
1554 /**
1555  * dma_free_rx_xskbufs - free RX dma buffers from XSK pool
1556  * @priv: private structure
1557  * @queue: RX queue index
1558  */
1559 static void dma_free_rx_xskbufs(struct stmmac_priv *priv, u32 queue)
1560 {
1561         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1562         int i;
1563
1564         for (i = 0; i < priv->dma_rx_size; i++) {
1565                 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1566
1567                 if (!buf->xdp)
1568                         continue;
1569
1570                 xsk_buff_free(buf->xdp);
1571                 buf->xdp = NULL;
1572         }
1573 }
1574
1575 static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, u32 queue)
1576 {
1577         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1578         int i;
1579
1580         for (i = 0; i < priv->dma_rx_size; i++) {
1581                 struct stmmac_rx_buffer *buf;
1582                 dma_addr_t dma_addr;
1583                 struct dma_desc *p;
1584
1585                 if (priv->extend_desc)
1586                         p = (struct dma_desc *)(rx_q->dma_erx + i);
1587                 else
1588                         p = rx_q->dma_rx + i;
1589
1590                 buf = &rx_q->buf_pool[i];
1591
1592                 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool);
1593                 if (!buf->xdp)
1594                         return -ENOMEM;
1595
1596                 dma_addr = xsk_buff_xdp_get_dma(buf->xdp);
1597                 stmmac_set_desc_addr(priv, p, dma_addr);
1598                 rx_q->buf_alloc_num++;
1599         }
1600
1601         return 0;
1602 }
1603
1604 static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue)
1605 {
1606         if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps))
1607                 return NULL;
1608
1609         return xsk_get_pool_from_qid(priv->dev, queue);
1610 }
1611
1612 /**
1613  * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue)
1614  * @priv: driver private structure
1615  * @queue: RX queue index
1616  * @flags: gfp flag.
1617  * Description: this function initializes the DMA RX descriptors
1618  * and allocates the socket buffers. It supports the chained and ring
1619  * modes.
1620  */
1621 static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, u32 queue, gfp_t flags)
1622 {
1623         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1624         int ret;
1625
1626         netif_dbg(priv, probe, priv->dev,
1627                   "(%s) dma_rx_phy=0x%08x\n", __func__,
1628                   (u32)rx_q->dma_rx_phy);
1629
1630         stmmac_clear_rx_descriptors(priv, queue);
1631
1632         xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq);
1633
1634         rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue);
1635
1636         if (rx_q->xsk_pool) {
1637                 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq,
1638                                                    MEM_TYPE_XSK_BUFF_POOL,
1639                                                    NULL));
1640                 netdev_info(priv->dev,
1641                             "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n",
1642                             rx_q->queue_index);
1643                 xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq);
1644         } else {
1645                 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq,
1646                                                    MEM_TYPE_PAGE_POOL,
1647                                                    rx_q->page_pool));
1648                 netdev_info(priv->dev,
1649                             "Register MEM_TYPE_PAGE_POOL RxQ-%d\n",
1650                             rx_q->queue_index);
1651         }
1652
1653         if (rx_q->xsk_pool) {
1654                 /* RX XDP ZC buffer pool may not be populated, e.g.
1655                  * xdpsock TX-only.
1656                  */
1657                 stmmac_alloc_rx_buffers_zc(priv, queue);
1658         } else {
1659                 ret = stmmac_alloc_rx_buffers(priv, queue, flags);
1660                 if (ret < 0)
1661                         return -ENOMEM;
1662         }
1663
1664         rx_q->cur_rx = 0;
1665         rx_q->dirty_rx = 0;
1666
1667         /* Setup the chained descriptor addresses */
1668         if (priv->mode == STMMAC_CHAIN_MODE) {
1669                 if (priv->extend_desc)
1670                         stmmac_mode_init(priv, rx_q->dma_erx,
1671                                          rx_q->dma_rx_phy,
1672                                          priv->dma_rx_size, 1);
1673                 else
1674                         stmmac_mode_init(priv, rx_q->dma_rx,
1675                                          rx_q->dma_rx_phy,
1676                                          priv->dma_rx_size, 0);
1677         }
1678
1679         return 0;
1680 }
1681
1682 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1683 {
1684         struct stmmac_priv *priv = netdev_priv(dev);
1685         u32 rx_count = priv->plat->rx_queues_to_use;
1686         u32 queue;
1687         int ret;
1688
1689         /* RX INITIALIZATION */
1690         netif_dbg(priv, probe, priv->dev,
1691                   "SKB addresses:\nskb\t\tskb data\tdma data\n");
1692
1693         for (queue = 0; queue < rx_count; queue++) {
1694                 ret = __init_dma_rx_desc_rings(priv, queue, flags);
1695                 if (ret)
1696                         goto err_init_rx_buffers;
1697         }
1698
1699         return 0;
1700
1701 err_init_rx_buffers:
1702         while (queue >= 0) {
1703                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1704
1705                 if (rx_q->xsk_pool)
1706                         dma_free_rx_xskbufs(priv, queue);
1707                 else
1708                         dma_free_rx_skbufs(priv, queue);
1709
1710                 rx_q->buf_alloc_num = 0;
1711                 rx_q->xsk_pool = NULL;
1712
1713                 if (queue == 0)
1714                         break;
1715
1716                 queue--;
1717         }
1718
1719         return ret;
1720 }
1721
1722 /**
1723  * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue)
1724  * @priv: driver private structure
1725  * @queue : TX queue index
1726  * Description: this function initializes the DMA TX descriptors
1727  * and allocates the socket buffers. It supports the chained and ring
1728  * modes.
1729  */
1730 static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, u32 queue)
1731 {
1732         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1733         int i;
1734
1735         netif_dbg(priv, probe, priv->dev,
1736                   "(%s) dma_tx_phy=0x%08x\n", __func__,
1737                   (u32)tx_q->dma_tx_phy);
1738
1739         /* Setup the chained descriptor addresses */
1740         if (priv->mode == STMMAC_CHAIN_MODE) {
1741                 if (priv->extend_desc)
1742                         stmmac_mode_init(priv, tx_q->dma_etx,
1743                                          tx_q->dma_tx_phy,
1744                                          priv->dma_tx_size, 1);
1745                 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL))
1746                         stmmac_mode_init(priv, tx_q->dma_tx,
1747                                          tx_q->dma_tx_phy,
1748                                          priv->dma_tx_size, 0);
1749         }
1750
1751         tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue);
1752
1753         for (i = 0; i < priv->dma_tx_size; i++) {
1754                 struct dma_desc *p;
1755
1756                 if (priv->extend_desc)
1757                         p = &((tx_q->dma_etx + i)->basic);
1758                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1759                         p = &((tx_q->dma_entx + i)->basic);
1760                 else
1761                         p = tx_q->dma_tx + i;
1762
1763                 stmmac_clear_desc(priv, p);
1764
1765                 tx_q->tx_skbuff_dma[i].buf = 0;
1766                 tx_q->tx_skbuff_dma[i].map_as_page = false;
1767                 tx_q->tx_skbuff_dma[i].len = 0;
1768                 tx_q->tx_skbuff_dma[i].last_segment = false;
1769                 tx_q->tx_skbuff[i] = NULL;
1770         }
1771
1772         tx_q->dirty_tx = 0;
1773         tx_q->cur_tx = 0;
1774         tx_q->mss = 0;
1775
1776         netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1777
1778         return 0;
1779 }
1780
1781 static int init_dma_tx_desc_rings(struct net_device *dev)
1782 {
1783         struct stmmac_priv *priv = netdev_priv(dev);
1784         u32 tx_queue_cnt;
1785         u32 queue;
1786
1787         tx_queue_cnt = priv->plat->tx_queues_to_use;
1788
1789         for (queue = 0; queue < tx_queue_cnt; queue++)
1790                 __init_dma_tx_desc_rings(priv, queue);
1791
1792         return 0;
1793 }
1794
1795 /**
1796  * init_dma_desc_rings - init the RX/TX descriptor rings
1797  * @dev: net device structure
1798  * @flags: gfp flag.
1799  * Description: this function initializes the DMA RX/TX descriptors
1800  * and allocates the socket buffers. It supports the chained and ring
1801  * modes.
1802  */
1803 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1804 {
1805         struct stmmac_priv *priv = netdev_priv(dev);
1806         int ret;
1807
1808         ret = init_dma_rx_desc_rings(dev, flags);
1809         if (ret)
1810                 return ret;
1811
1812         ret = init_dma_tx_desc_rings(dev);
1813
1814         stmmac_clear_descriptors(priv);
1815
1816         if (netif_msg_hw(priv))
1817                 stmmac_display_rings(priv);
1818
1819         return ret;
1820 }
1821
1822 /**
1823  * dma_free_tx_skbufs - free TX dma buffers
1824  * @priv: private structure
1825  * @queue: TX queue index
1826  */
1827 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1828 {
1829         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1830         int i;
1831
1832         tx_q->xsk_frames_done = 0;
1833
1834         for (i = 0; i < priv->dma_tx_size; i++)
1835                 stmmac_free_tx_buffer(priv, queue, i);
1836
1837         if (tx_q->xsk_pool && tx_q->xsk_frames_done) {
1838                 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done);
1839                 tx_q->xsk_frames_done = 0;
1840                 tx_q->xsk_pool = NULL;
1841         }
1842 }
1843
1844 /**
1845  * stmmac_free_tx_skbufs - free TX skb buffers
1846  * @priv: private structure
1847  */
1848 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv)
1849 {
1850         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1851         u32 queue;
1852
1853         for (queue = 0; queue < tx_queue_cnt; queue++)
1854                 dma_free_tx_skbufs(priv, queue);
1855 }
1856
1857 /**
1858  * __free_dma_rx_desc_resources - free RX dma desc resources (per queue)
1859  * @priv: private structure
1860  * @queue: RX queue index
1861  */
1862 static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue)
1863 {
1864         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1865
1866         /* Release the DMA RX socket buffers */
1867         if (rx_q->xsk_pool)
1868                 dma_free_rx_xskbufs(priv, queue);
1869         else
1870                 dma_free_rx_skbufs(priv, queue);
1871
1872         rx_q->buf_alloc_num = 0;
1873         rx_q->xsk_pool = NULL;
1874
1875         /* Free DMA regions of consistent memory previously allocated */
1876         if (!priv->extend_desc)
1877                 dma_free_coherent(priv->device, priv->dma_rx_size *
1878                                   sizeof(struct dma_desc),
1879                                   rx_q->dma_rx, rx_q->dma_rx_phy);
1880         else
1881                 dma_free_coherent(priv->device, priv->dma_rx_size *
1882                                   sizeof(struct dma_extended_desc),
1883                                   rx_q->dma_erx, rx_q->dma_rx_phy);
1884
1885         if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq))
1886                 xdp_rxq_info_unreg(&rx_q->xdp_rxq);
1887
1888         kfree(rx_q->buf_pool);
1889         if (rx_q->page_pool)
1890                 page_pool_destroy(rx_q->page_pool);
1891 }
1892
1893 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1894 {
1895         u32 rx_count = priv->plat->rx_queues_to_use;
1896         u32 queue;
1897
1898         /* Free RX queue resources */
1899         for (queue = 0; queue < rx_count; queue++)
1900                 __free_dma_rx_desc_resources(priv, queue);
1901 }
1902
1903 /**
1904  * __free_dma_tx_desc_resources - free TX dma desc resources (per queue)
1905  * @priv: private structure
1906  * @queue: TX queue index
1907  */
1908 static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue)
1909 {
1910         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1911         size_t size;
1912         void *addr;
1913
1914         /* Release the DMA TX socket buffers */
1915         dma_free_tx_skbufs(priv, queue);
1916
1917         if (priv->extend_desc) {
1918                 size = sizeof(struct dma_extended_desc);
1919                 addr = tx_q->dma_etx;
1920         } else if (tx_q->tbs & STMMAC_TBS_AVAIL) {
1921                 size = sizeof(struct dma_edesc);
1922                 addr = tx_q->dma_entx;
1923         } else {
1924                 size = sizeof(struct dma_desc);
1925                 addr = tx_q->dma_tx;
1926         }
1927
1928         size *= priv->dma_tx_size;
1929
1930         dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy);
1931
1932         kfree(tx_q->tx_skbuff_dma);
1933         kfree(tx_q->tx_skbuff);
1934 }
1935
1936 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1937 {
1938         u32 tx_count = priv->plat->tx_queues_to_use;
1939         u32 queue;
1940
1941         /* Free TX queue resources */
1942         for (queue = 0; queue < tx_count; queue++)
1943                 __free_dma_tx_desc_resources(priv, queue);
1944 }
1945
1946 /**
1947  * __alloc_dma_rx_desc_resources - alloc RX resources (per queue).
1948  * @priv: private structure
1949  * @queue: RX queue index
1950  * Description: according to which descriptor can be used (extend or basic)
1951  * this function allocates the resources for TX and RX paths. In case of
1952  * reception, for example, it pre-allocated the RX socket buffer in order to
1953  * allow zero-copy mechanism.
1954  */
1955 static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue)
1956 {
1957         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1958         struct stmmac_channel *ch = &priv->channel[queue];
1959         bool xdp_prog = stmmac_xdp_is_enabled(priv);
1960         struct page_pool_params pp_params = { 0 };
1961         unsigned int num_pages;
1962         unsigned int napi_id;
1963         int ret;
1964
1965         rx_q->queue_index = queue;
1966         rx_q->priv_data = priv;
1967
1968         pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV;
1969         pp_params.pool_size = priv->dma_rx_size;
1970         num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE);
1971         pp_params.order = ilog2(num_pages);
1972         pp_params.nid = dev_to_node(priv->device);
1973         pp_params.dev = priv->device;
1974         pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
1975         pp_params.offset = stmmac_rx_offset(priv);
1976         pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages);
1977
1978         rx_q->page_pool = page_pool_create(&pp_params);
1979         if (IS_ERR(rx_q->page_pool)) {
1980                 ret = PTR_ERR(rx_q->page_pool);
1981                 rx_q->page_pool = NULL;
1982                 return ret;
1983         }
1984
1985         rx_q->buf_pool = kcalloc(priv->dma_rx_size,
1986                                  sizeof(*rx_q->buf_pool),
1987                                  GFP_KERNEL);
1988         if (!rx_q->buf_pool)
1989                 return -ENOMEM;
1990
1991         if (priv->extend_desc) {
1992                 rx_q->dma_erx = dma_alloc_coherent(priv->device,
1993                                                    priv->dma_rx_size *
1994                                                    sizeof(struct dma_extended_desc),
1995                                                    &rx_q->dma_rx_phy,
1996                                                    GFP_KERNEL);
1997                 if (!rx_q->dma_erx)
1998                         return -ENOMEM;
1999
2000         } else {
2001                 rx_q->dma_rx = dma_alloc_coherent(priv->device,
2002                                                   priv->dma_rx_size *
2003                                                   sizeof(struct dma_desc),
2004                                                   &rx_q->dma_rx_phy,
2005                                                   GFP_KERNEL);
2006                 if (!rx_q->dma_rx)
2007                         return -ENOMEM;
2008         }
2009
2010         if (stmmac_xdp_is_enabled(priv) &&
2011             test_bit(queue, priv->af_xdp_zc_qps))
2012                 napi_id = ch->rxtx_napi.napi_id;
2013         else
2014                 napi_id = ch->rx_napi.napi_id;
2015
2016         ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev,
2017                                rx_q->queue_index,
2018                                napi_id);
2019         if (ret) {
2020                 netdev_err(priv->dev, "Failed to register xdp rxq info\n");
2021                 return -EINVAL;
2022         }
2023
2024         return 0;
2025 }
2026
2027 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
2028 {
2029         u32 rx_count = priv->plat->rx_queues_to_use;
2030         u32 queue;
2031         int ret;
2032
2033         /* RX queues buffers and DMA */
2034         for (queue = 0; queue < rx_count; queue++) {
2035                 ret = __alloc_dma_rx_desc_resources(priv, queue);
2036                 if (ret)
2037                         goto err_dma;
2038         }
2039
2040         return 0;
2041
2042 err_dma:
2043         free_dma_rx_desc_resources(priv);
2044
2045         return ret;
2046 }
2047
2048 /**
2049  * __alloc_dma_tx_desc_resources - alloc TX resources (per queue).
2050  * @priv: private structure
2051  * @queue: TX queue index
2052  * Description: according to which descriptor can be used (extend or basic)
2053  * this function allocates the resources for TX and RX paths. In case of
2054  * reception, for example, it pre-allocated the RX socket buffer in order to
2055  * allow zero-copy mechanism.
2056  */
2057 static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue)
2058 {
2059         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2060         size_t size;
2061         void *addr;
2062
2063         tx_q->queue_index = queue;
2064         tx_q->priv_data = priv;
2065
2066         tx_q->tx_skbuff_dma = kcalloc(priv->dma_tx_size,
2067                                       sizeof(*tx_q->tx_skbuff_dma),
2068                                       GFP_KERNEL);
2069         if (!tx_q->tx_skbuff_dma)
2070                 return -ENOMEM;
2071
2072         tx_q->tx_skbuff = kcalloc(priv->dma_tx_size,
2073                                   sizeof(struct sk_buff *),
2074                                   GFP_KERNEL);
2075         if (!tx_q->tx_skbuff)
2076                 return -ENOMEM;
2077
2078         if (priv->extend_desc)
2079                 size = sizeof(struct dma_extended_desc);
2080         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2081                 size = sizeof(struct dma_edesc);
2082         else
2083                 size = sizeof(struct dma_desc);
2084
2085         size *= priv->dma_tx_size;
2086
2087         addr = dma_alloc_coherent(priv->device, size,
2088                                   &tx_q->dma_tx_phy, GFP_KERNEL);
2089         if (!addr)
2090                 return -ENOMEM;
2091
2092         if (priv->extend_desc)
2093                 tx_q->dma_etx = addr;
2094         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2095                 tx_q->dma_entx = addr;
2096         else
2097                 tx_q->dma_tx = addr;
2098
2099         return 0;
2100 }
2101
2102 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
2103 {
2104         u32 tx_count = priv->plat->tx_queues_to_use;
2105         u32 queue;
2106         int ret;
2107
2108         /* TX queues buffers and DMA */
2109         for (queue = 0; queue < tx_count; queue++) {
2110                 ret = __alloc_dma_tx_desc_resources(priv, queue);
2111                 if (ret)
2112                         goto err_dma;
2113         }
2114
2115         return 0;
2116
2117 err_dma:
2118         free_dma_tx_desc_resources(priv);
2119         return ret;
2120 }
2121
2122 /**
2123  * alloc_dma_desc_resources - alloc TX/RX resources.
2124  * @priv: private structure
2125  * Description: according to which descriptor can be used (extend or basic)
2126  * this function allocates the resources for TX and RX paths. In case of
2127  * reception, for example, it pre-allocated the RX socket buffer in order to
2128  * allow zero-copy mechanism.
2129  */
2130 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
2131 {
2132         /* RX Allocation */
2133         int ret = alloc_dma_rx_desc_resources(priv);
2134
2135         if (ret)
2136                 return ret;
2137
2138         ret = alloc_dma_tx_desc_resources(priv);
2139
2140         return ret;
2141 }
2142
2143 /**
2144  * free_dma_desc_resources - free dma desc resources
2145  * @priv: private structure
2146  */
2147 static void free_dma_desc_resources(struct stmmac_priv *priv)
2148 {
2149         /* Release the DMA TX socket buffers */
2150         free_dma_tx_desc_resources(priv);
2151
2152         /* Release the DMA RX socket buffers later
2153          * to ensure all pending XDP_TX buffers are returned.
2154          */
2155         free_dma_rx_desc_resources(priv);
2156 }
2157
2158 /**
2159  *  stmmac_mac_enable_rx_queues - Enable MAC rx queues
2160  *  @priv: driver private structure
2161  *  Description: It is used for enabling the rx queues in the MAC
2162  */
2163 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
2164 {
2165         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2166         int queue;
2167         u8 mode;
2168
2169         for (queue = 0; queue < rx_queues_count; queue++) {
2170                 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
2171                 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
2172         }
2173 }
2174
2175 /**
2176  * stmmac_start_rx_dma - start RX DMA channel
2177  * @priv: driver private structure
2178  * @chan: RX channel index
2179  * Description:
2180  * This starts a RX DMA channel
2181  */
2182 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
2183 {
2184         netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
2185         stmmac_start_rx(priv, priv->ioaddr, chan);
2186 }
2187
2188 /**
2189  * stmmac_start_tx_dma - start TX DMA channel
2190  * @priv: driver private structure
2191  * @chan: TX channel index
2192  * Description:
2193  * This starts a TX DMA channel
2194  */
2195 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
2196 {
2197         netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
2198         stmmac_start_tx(priv, priv->ioaddr, chan);
2199 }
2200
2201 /**
2202  * stmmac_stop_rx_dma - stop RX DMA channel
2203  * @priv: driver private structure
2204  * @chan: RX channel index
2205  * Description:
2206  * This stops a RX DMA channel
2207  */
2208 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
2209 {
2210         netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
2211         stmmac_stop_rx(priv, priv->ioaddr, chan);
2212 }
2213
2214 /**
2215  * stmmac_stop_tx_dma - stop TX DMA channel
2216  * @priv: driver private structure
2217  * @chan: TX channel index
2218  * Description:
2219  * This stops a TX DMA channel
2220  */
2221 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
2222 {
2223         netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
2224         stmmac_stop_tx(priv, priv->ioaddr, chan);
2225 }
2226
2227 /**
2228  * stmmac_start_all_dma - start all RX and TX DMA channels
2229  * @priv: driver private structure
2230  * Description:
2231  * This starts all the RX and TX DMA channels
2232  */
2233 static void stmmac_start_all_dma(struct stmmac_priv *priv)
2234 {
2235         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2236         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2237         u32 chan = 0;
2238
2239         for (chan = 0; chan < rx_channels_count; chan++)
2240                 stmmac_start_rx_dma(priv, chan);
2241
2242         for (chan = 0; chan < tx_channels_count; chan++)
2243                 stmmac_start_tx_dma(priv, chan);
2244 }
2245
2246 /**
2247  * stmmac_stop_all_dma - stop all RX and TX DMA channels
2248  * @priv: driver private structure
2249  * Description:
2250  * This stops the RX and TX DMA channels
2251  */
2252 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
2253 {
2254         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2255         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2256         u32 chan = 0;
2257
2258         for (chan = 0; chan < rx_channels_count; chan++)
2259                 stmmac_stop_rx_dma(priv, chan);
2260
2261         for (chan = 0; chan < tx_channels_count; chan++)
2262                 stmmac_stop_tx_dma(priv, chan);
2263 }
2264
2265 /**
2266  *  stmmac_dma_operation_mode - HW DMA operation mode
2267  *  @priv: driver private structure
2268  *  Description: it is used for configuring the DMA operation mode register in
2269  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
2270  */
2271 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
2272 {
2273         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2274         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2275         int rxfifosz = priv->plat->rx_fifo_size;
2276         int txfifosz = priv->plat->tx_fifo_size;
2277         u32 txmode = 0;
2278         u32 rxmode = 0;
2279         u32 chan = 0;
2280         u8 qmode = 0;
2281
2282         if (rxfifosz == 0)
2283                 rxfifosz = priv->dma_cap.rx_fifo_size;
2284         if (txfifosz == 0)
2285                 txfifosz = priv->dma_cap.tx_fifo_size;
2286
2287         /* Adjust for real per queue fifo size */
2288         rxfifosz /= rx_channels_count;
2289         txfifosz /= tx_channels_count;
2290
2291         if (priv->plat->force_thresh_dma_mode) {
2292                 txmode = tc;
2293                 rxmode = tc;
2294         } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
2295                 /*
2296                  * In case of GMAC, SF mode can be enabled
2297                  * to perform the TX COE in HW. This depends on:
2298                  * 1) TX COE if actually supported
2299                  * 2) There is no bugged Jumbo frame support
2300                  *    that needs to not insert csum in the TDES.
2301                  */
2302                 txmode = SF_DMA_MODE;
2303                 rxmode = SF_DMA_MODE;
2304                 priv->xstats.threshold = SF_DMA_MODE;
2305         } else {
2306                 txmode = tc;
2307                 rxmode = SF_DMA_MODE;
2308         }
2309
2310         /* configure all channels */
2311         for (chan = 0; chan < rx_channels_count; chan++) {
2312                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan];
2313                 u32 buf_size;
2314
2315                 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2316
2317                 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
2318                                 rxfifosz, qmode);
2319
2320                 if (rx_q->xsk_pool) {
2321                         buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
2322                         stmmac_set_dma_bfsize(priv, priv->ioaddr,
2323                                               buf_size,
2324                                               chan);
2325                 } else {
2326                         stmmac_set_dma_bfsize(priv, priv->ioaddr,
2327                                               priv->dma_buf_sz,
2328                                               chan);
2329                 }
2330         }
2331
2332         for (chan = 0; chan < tx_channels_count; chan++) {
2333                 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2334
2335                 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
2336                                 txfifosz, qmode);
2337         }
2338 }
2339
2340 static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
2341 {
2342         struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue);
2343         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2344         struct xsk_buff_pool *pool = tx_q->xsk_pool;
2345         unsigned int entry = tx_q->cur_tx;
2346         struct dma_desc *tx_desc = NULL;
2347         struct xdp_desc xdp_desc;
2348         bool work_done = true;
2349
2350         /* Avoids TX time-out as we are sharing with slow path */
2351         nq->trans_start = jiffies;
2352
2353         budget = min(budget, stmmac_tx_avail(priv, queue));
2354
2355         while (budget-- > 0) {
2356                 dma_addr_t dma_addr;
2357                 bool set_ic;
2358
2359                 /* We are sharing with slow path and stop XSK TX desc submission when
2360                  * available TX ring is less than threshold.
2361                  */
2362                 if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) ||
2363                     !netif_carrier_ok(priv->dev)) {
2364                         work_done = false;
2365                         break;
2366                 }
2367
2368                 if (!xsk_tx_peek_desc(pool, &xdp_desc))
2369                         break;
2370
2371                 if (likely(priv->extend_desc))
2372                         tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry);
2373                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2374                         tx_desc = &tx_q->dma_entx[entry].basic;
2375                 else
2376                         tx_desc = tx_q->dma_tx + entry;
2377
2378                 dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr);
2379                 xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len);
2380
2381                 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX;
2382
2383                 /* To return XDP buffer to XSK pool, we simple call
2384                  * xsk_tx_completed(), so we don't need to fill up
2385                  * 'buf' and 'xdpf'.
2386                  */
2387                 tx_q->tx_skbuff_dma[entry].buf = 0;
2388                 tx_q->xdpf[entry] = NULL;
2389
2390                 tx_q->tx_skbuff_dma[entry].map_as_page = false;
2391                 tx_q->tx_skbuff_dma[entry].len = xdp_desc.len;
2392                 tx_q->tx_skbuff_dma[entry].last_segment = true;
2393                 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
2394
2395                 stmmac_set_desc_addr(priv, tx_desc, dma_addr);
2396
2397                 tx_q->tx_count_frames++;
2398
2399                 if (!priv->tx_coal_frames[queue])
2400                         set_ic = false;
2401                 else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0)
2402                         set_ic = true;
2403                 else
2404                         set_ic = false;
2405
2406                 if (set_ic) {
2407                         tx_q->tx_count_frames = 0;
2408                         stmmac_set_tx_ic(priv, tx_desc);
2409                         priv->xstats.tx_set_ic_bit++;
2410                 }
2411
2412                 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len,
2413                                        true, priv->mode, true, true,
2414                                        xdp_desc.len);
2415
2416                 stmmac_enable_dma_transmission(priv, priv->ioaddr);
2417
2418                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size);
2419                 entry = tx_q->cur_tx;
2420         }
2421
2422         if (tx_desc) {
2423                 stmmac_flush_tx_descriptors(priv, queue);
2424                 xsk_tx_release(pool);
2425         }
2426
2427         /* Return true if all of the 3 conditions are met
2428          *  a) TX Budget is still available
2429          *  b) work_done = true when XSK TX desc peek is empty (no more
2430          *     pending XSK TX for transmission)
2431          */
2432         return !!budget && work_done;
2433 }
2434
2435 /**
2436  * stmmac_tx_clean - to manage the transmission completion
2437  * @priv: driver private structure
2438  * @budget: napi budget limiting this functions packet handling
2439  * @queue: TX queue index
2440  * Description: it reclaims the transmit resources after transmission completes.
2441  */
2442 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
2443 {
2444         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2445         unsigned int bytes_compl = 0, pkts_compl = 0;
2446         unsigned int entry, xmits = 0, count = 0;
2447
2448         __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
2449
2450         priv->xstats.tx_clean++;
2451
2452         tx_q->xsk_frames_done = 0;
2453
2454         entry = tx_q->dirty_tx;
2455
2456         /* Try to clean all TX complete frame in 1 shot */
2457         while ((entry != tx_q->cur_tx) && count < priv->dma_tx_size) {
2458                 struct xdp_frame *xdpf;
2459                 struct sk_buff *skb;
2460                 struct dma_desc *p;
2461                 int status;
2462
2463                 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX ||
2464                     tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) {
2465                         xdpf = tx_q->xdpf[entry];
2466                         skb = NULL;
2467                 } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) {
2468                         xdpf = NULL;
2469                         skb = tx_q->tx_skbuff[entry];
2470                 } else {
2471                         xdpf = NULL;
2472                         skb = NULL;
2473                 }
2474
2475                 if (priv->extend_desc)
2476                         p = (struct dma_desc *)(tx_q->dma_etx + entry);
2477                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2478                         p = &tx_q->dma_entx[entry].basic;
2479                 else
2480                         p = tx_q->dma_tx + entry;
2481
2482                 status = stmmac_tx_status(priv, &priv->dev->stats,
2483                                 &priv->xstats, p, priv->ioaddr);
2484                 /* Check if the descriptor is owned by the DMA */
2485                 if (unlikely(status & tx_dma_own))
2486                         break;
2487
2488                 count++;
2489
2490                 /* Make sure descriptor fields are read after reading
2491                  * the own bit.
2492                  */
2493                 dma_rmb();
2494
2495                 /* Just consider the last segment and ...*/
2496                 if (likely(!(status & tx_not_ls))) {
2497                         /* ... verify the status error condition */
2498                         if (unlikely(status & tx_err)) {
2499                                 priv->dev->stats.tx_errors++;
2500                         } else {
2501                                 priv->dev->stats.tx_packets++;
2502                                 priv->xstats.tx_pkt_n++;
2503                                 priv->xstats.txq_stats[queue].tx_pkt_n++;
2504                         }
2505                         if (skb)
2506                                 stmmac_get_tx_hwtstamp(priv, p, skb);
2507                 }
2508
2509                 if (likely(tx_q->tx_skbuff_dma[entry].buf &&
2510                            tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) {
2511                         if (tx_q->tx_skbuff_dma[entry].map_as_page)
2512                                 dma_unmap_page(priv->device,
2513                                                tx_q->tx_skbuff_dma[entry].buf,
2514                                                tx_q->tx_skbuff_dma[entry].len,
2515                                                DMA_TO_DEVICE);
2516                         else
2517                                 dma_unmap_single(priv->device,
2518                                                  tx_q->tx_skbuff_dma[entry].buf,
2519                                                  tx_q->tx_skbuff_dma[entry].len,
2520                                                  DMA_TO_DEVICE);
2521                         tx_q->tx_skbuff_dma[entry].buf = 0;
2522                         tx_q->tx_skbuff_dma[entry].len = 0;
2523                         tx_q->tx_skbuff_dma[entry].map_as_page = false;
2524                 }
2525
2526                 stmmac_clean_desc3(priv, tx_q, p);
2527
2528                 tx_q->tx_skbuff_dma[entry].last_segment = false;
2529                 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
2530
2531                 if (xdpf &&
2532                     tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) {
2533                         xdp_return_frame_rx_napi(xdpf);
2534                         tx_q->xdpf[entry] = NULL;
2535                 }
2536
2537                 if (xdpf &&
2538                     tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) {
2539                         xdp_return_frame(xdpf);
2540                         tx_q->xdpf[entry] = NULL;
2541                 }
2542
2543                 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX)
2544                         tx_q->xsk_frames_done++;
2545
2546                 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) {
2547                         if (likely(skb)) {
2548                                 pkts_compl++;
2549                                 bytes_compl += skb->len;
2550                                 dev_consume_skb_any(skb);
2551                                 tx_q->tx_skbuff[entry] = NULL;
2552                         }
2553                 }
2554
2555                 stmmac_release_tx_desc(priv, p, priv->mode);
2556
2557                 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
2558         }
2559         tx_q->dirty_tx = entry;
2560
2561         netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
2562                                   pkts_compl, bytes_compl);
2563
2564         if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
2565                                                                 queue))) &&
2566             stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) {
2567
2568                 netif_dbg(priv, tx_done, priv->dev,
2569                           "%s: restart transmit\n", __func__);
2570                 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
2571         }
2572
2573         if (tx_q->xsk_pool) {
2574                 bool work_done;
2575
2576                 if (tx_q->xsk_frames_done)
2577                         xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done);
2578
2579                 if (xsk_uses_need_wakeup(tx_q->xsk_pool))
2580                         xsk_set_tx_need_wakeup(tx_q->xsk_pool);
2581
2582                 /* For XSK TX, we try to send as many as possible.
2583                  * If XSK work done (XSK TX desc empty and budget still
2584                  * available), return "budget - 1" to reenable TX IRQ.
2585                  * Else, return "budget" to make NAPI continue polling.
2586                  */
2587                 work_done = stmmac_xdp_xmit_zc(priv, queue,
2588                                                STMMAC_XSK_TX_BUDGET_MAX);
2589                 if (work_done)
2590                         xmits = budget - 1;
2591                 else
2592                         xmits = budget;
2593         }
2594
2595         if (priv->eee_enabled && !priv->tx_path_in_lpi_mode &&
2596             priv->eee_sw_timer_en) {
2597                 stmmac_enable_eee_mode(priv);
2598                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer));
2599         }
2600
2601         /* We still have pending packets, let's call for a new scheduling */
2602         if (tx_q->dirty_tx != tx_q->cur_tx)
2603                 hrtimer_start(&tx_q->txtimer,
2604                               STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]),
2605                               HRTIMER_MODE_REL);
2606
2607         __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
2608
2609         /* Combine decisions from TX clean and XSK TX */
2610         return max(count, xmits);
2611 }
2612
2613 /**
2614  * stmmac_tx_err - to manage the tx error
2615  * @priv: driver private structure
2616  * @chan: channel index
2617  * Description: it cleans the descriptors and restarts the transmission
2618  * in case of transmission errors.
2619  */
2620 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
2621 {
2622         struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2623
2624         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
2625
2626         stmmac_stop_tx_dma(priv, chan);
2627         dma_free_tx_skbufs(priv, chan);
2628         stmmac_clear_tx_descriptors(priv, chan);
2629         tx_q->dirty_tx = 0;
2630         tx_q->cur_tx = 0;
2631         tx_q->mss = 0;
2632         netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
2633         stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2634                             tx_q->dma_tx_phy, chan);
2635         stmmac_start_tx_dma(priv, chan);
2636
2637         priv->dev->stats.tx_errors++;
2638         netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
2639 }
2640
2641 /**
2642  *  stmmac_set_dma_operation_mode - Set DMA operation mode by channel
2643  *  @priv: driver private structure
2644  *  @txmode: TX operating mode
2645  *  @rxmode: RX operating mode
2646  *  @chan: channel index
2647  *  Description: it is used for configuring of the DMA operation mode in
2648  *  runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
2649  *  mode.
2650  */
2651 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
2652                                           u32 rxmode, u32 chan)
2653 {
2654         u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2655         u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2656         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2657         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2658         int rxfifosz = priv->plat->rx_fifo_size;
2659         int txfifosz = priv->plat->tx_fifo_size;
2660
2661         if (rxfifosz == 0)
2662                 rxfifosz = priv->dma_cap.rx_fifo_size;
2663         if (txfifosz == 0)
2664                 txfifosz = priv->dma_cap.tx_fifo_size;
2665
2666         /* Adjust for real per queue fifo size */
2667         rxfifosz /= rx_channels_count;
2668         txfifosz /= tx_channels_count;
2669
2670         stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
2671         stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
2672 }
2673
2674 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
2675 {
2676         int ret;
2677
2678         ret = stmmac_safety_feat_irq_status(priv, priv->dev,
2679                         priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
2680         if (ret && (ret != -EINVAL)) {
2681                 stmmac_global_err(priv);
2682                 return true;
2683         }
2684
2685         return false;
2686 }
2687
2688 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir)
2689 {
2690         int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2691                                                  &priv->xstats, chan, dir);
2692         struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan];
2693         struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2694         struct stmmac_channel *ch = &priv->channel[chan];
2695         struct napi_struct *rx_napi;
2696         struct napi_struct *tx_napi;
2697         unsigned long flags;
2698
2699         rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi;
2700         tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi;
2701
2702         if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2703                 if (napi_schedule_prep(rx_napi)) {
2704                         spin_lock_irqsave(&ch->lock, flags);
2705                         stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0);
2706                         spin_unlock_irqrestore(&ch->lock, flags);
2707                         __napi_schedule(rx_napi);
2708                 }
2709         }
2710
2711         if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) {
2712                 if (napi_schedule_prep(tx_napi)) {
2713                         spin_lock_irqsave(&ch->lock, flags);
2714                         stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1);
2715                         spin_unlock_irqrestore(&ch->lock, flags);
2716                         __napi_schedule(tx_napi);
2717                 }
2718         }
2719
2720         return status;
2721 }
2722
2723 /**
2724  * stmmac_dma_interrupt - DMA ISR
2725  * @priv: driver private structure
2726  * Description: this is the DMA ISR. It is called by the main ISR.
2727  * It calls the dwmac dma routine and schedule poll method in case of some
2728  * work can be done.
2729  */
2730 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2731 {
2732         u32 tx_channel_count = priv->plat->tx_queues_to_use;
2733         u32 rx_channel_count = priv->plat->rx_queues_to_use;
2734         u32 channels_to_check = tx_channel_count > rx_channel_count ?
2735                                 tx_channel_count : rx_channel_count;
2736         u32 chan;
2737         int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2738
2739         /* Make sure we never check beyond our status buffer. */
2740         if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2741                 channels_to_check = ARRAY_SIZE(status);
2742
2743         for (chan = 0; chan < channels_to_check; chan++)
2744                 status[chan] = stmmac_napi_check(priv, chan,
2745                                                  DMA_DIR_RXTX);
2746
2747         for (chan = 0; chan < tx_channel_count; chan++) {
2748                 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2749                         /* Try to bump up the dma threshold on this failure */
2750                         if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
2751                             (tc <= 256)) {
2752                                 tc += 64;
2753                                 if (priv->plat->force_thresh_dma_mode)
2754                                         stmmac_set_dma_operation_mode(priv,
2755                                                                       tc,
2756                                                                       tc,
2757                                                                       chan);
2758                                 else
2759                                         stmmac_set_dma_operation_mode(priv,
2760                                                                     tc,
2761                                                                     SF_DMA_MODE,
2762                                                                     chan);
2763                                 priv->xstats.threshold = tc;
2764                         }
2765                 } else if (unlikely(status[chan] == tx_hard_error)) {
2766                         stmmac_tx_err(priv, chan);
2767                 }
2768         }
2769 }
2770
2771 /**
2772  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2773  * @priv: driver private structure
2774  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2775  */
2776 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2777 {
2778         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2779                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2780
2781         stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
2782
2783         if (priv->dma_cap.rmon) {
2784                 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
2785                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2786         } else
2787                 netdev_info(priv->dev, "No MAC Management Counters available\n");
2788 }
2789
2790 /**
2791  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2792  * @priv: driver private structure
2793  * Description:
2794  *  new GMAC chip generations have a new register to indicate the
2795  *  presence of the optional feature/functions.
2796  *  This can be also used to override the value passed through the
2797  *  platform and necessary for old MAC10/100 and GMAC chips.
2798  */
2799 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2800 {
2801         return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2802 }
2803
2804 /**
2805  * stmmac_check_ether_addr - check if the MAC addr is valid
2806  * @priv: driver private structure
2807  * Description:
2808  * it is to verify if the MAC address is valid, in case of failures it
2809  * generates a random MAC address
2810  */
2811 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2812 {
2813         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2814                 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0);
2815                 if (!is_valid_ether_addr(priv->dev->dev_addr))
2816                         eth_hw_addr_random(priv->dev);
2817                 dev_info(priv->device, "device MAC address %pM\n",
2818                          priv->dev->dev_addr);
2819         }
2820 }
2821
2822 /**
2823  * stmmac_init_dma_engine - DMA init.
2824  * @priv: driver private structure
2825  * Description:
2826  * It inits the DMA invoking the specific MAC/GMAC callback.
2827  * Some DMA parameters can be passed from the platform;
2828  * in case of these are not passed a default is kept for the MAC or GMAC.
2829  */
2830 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2831 {
2832         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2833         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2834         u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2835         struct stmmac_rx_queue *rx_q;
2836         struct stmmac_tx_queue *tx_q;
2837         u32 chan = 0;
2838         int atds = 0;
2839         int ret = 0;
2840
2841         if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2842                 dev_err(priv->device, "Invalid DMA configuration\n");
2843                 return -EINVAL;
2844         }
2845
2846         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2847                 atds = 1;
2848
2849         ret = stmmac_reset(priv, priv->ioaddr);
2850         if (ret) {
2851                 dev_err(priv->device, "Failed to reset the dma\n");
2852                 return ret;
2853         }
2854
2855         /* DMA Configuration */
2856         stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2857
2858         if (priv->plat->axi)
2859                 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2860
2861         /* DMA CSR Channel configuration */
2862         for (chan = 0; chan < dma_csr_ch; chan++)
2863                 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2864
2865         /* DMA RX Channel Configuration */
2866         for (chan = 0; chan < rx_channels_count; chan++) {
2867                 rx_q = &priv->rx_queue[chan];
2868
2869                 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2870                                     rx_q->dma_rx_phy, chan);
2871
2872                 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2873                                      (rx_q->buf_alloc_num *
2874                                       sizeof(struct dma_desc));
2875                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2876                                        rx_q->rx_tail_addr, chan);
2877         }
2878
2879         /* DMA TX Channel Configuration */
2880         for (chan = 0; chan < tx_channels_count; chan++) {
2881                 tx_q = &priv->tx_queue[chan];
2882
2883                 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2884                                     tx_q->dma_tx_phy, chan);
2885
2886                 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2887                 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2888                                        tx_q->tx_tail_addr, chan);
2889         }
2890
2891         return ret;
2892 }
2893
2894 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2895 {
2896         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2897
2898         hrtimer_start(&tx_q->txtimer,
2899                       STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]),
2900                       HRTIMER_MODE_REL);
2901 }
2902
2903 /**
2904  * stmmac_tx_timer - mitigation sw timer for tx.
2905  * @t: data pointer
2906  * Description:
2907  * This is the timer handler to directly invoke the stmmac_tx_clean.
2908  */
2909 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t)
2910 {
2911         struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer);
2912         struct stmmac_priv *priv = tx_q->priv_data;
2913         struct stmmac_channel *ch;
2914         struct napi_struct *napi;
2915
2916         ch = &priv->channel[tx_q->queue_index];
2917         napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi;
2918
2919         if (likely(napi_schedule_prep(napi))) {
2920                 unsigned long flags;
2921
2922                 spin_lock_irqsave(&ch->lock, flags);
2923                 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1);
2924                 spin_unlock_irqrestore(&ch->lock, flags);
2925                 __napi_schedule(napi);
2926         }
2927
2928         return HRTIMER_NORESTART;
2929 }
2930
2931 /**
2932  * stmmac_init_coalesce - init mitigation options.
2933  * @priv: driver private structure
2934  * Description:
2935  * This inits the coalesce parameters: i.e. timer rate,
2936  * timer handler and default threshold used for enabling the
2937  * interrupt on completion bit.
2938  */
2939 static void stmmac_init_coalesce(struct stmmac_priv *priv)
2940 {
2941         u32 tx_channel_count = priv->plat->tx_queues_to_use;
2942         u32 rx_channel_count = priv->plat->rx_queues_to_use;
2943         u32 chan;
2944
2945         for (chan = 0; chan < tx_channel_count; chan++) {
2946                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2947
2948                 priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES;
2949                 priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER;
2950
2951                 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2952                 tx_q->txtimer.function = stmmac_tx_timer;
2953         }
2954
2955         for (chan = 0; chan < rx_channel_count; chan++)
2956                 priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES;
2957 }
2958
2959 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2960 {
2961         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2962         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2963         u32 chan;
2964
2965         /* set TX ring length */
2966         for (chan = 0; chan < tx_channels_count; chan++)
2967                 stmmac_set_tx_ring_len(priv, priv->ioaddr,
2968                                        (priv->dma_tx_size - 1), chan);
2969
2970         /* set RX ring length */
2971         for (chan = 0; chan < rx_channels_count; chan++)
2972                 stmmac_set_rx_ring_len(priv, priv->ioaddr,
2973                                        (priv->dma_rx_size - 1), chan);
2974 }
2975
2976 /**
2977  *  stmmac_set_tx_queue_weight - Set TX queue weight
2978  *  @priv: driver private structure
2979  *  Description: It is used for setting TX queues weight
2980  */
2981 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2982 {
2983         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2984         u32 weight;
2985         u32 queue;
2986
2987         for (queue = 0; queue < tx_queues_count; queue++) {
2988                 weight = priv->plat->tx_queues_cfg[queue].weight;
2989                 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
2990         }
2991 }
2992
2993 /**
2994  *  stmmac_configure_cbs - Configure CBS in TX queue
2995  *  @priv: driver private structure
2996  *  Description: It is used for configuring CBS in AVB TX queues
2997  */
2998 static void stmmac_configure_cbs(struct stmmac_priv *priv)
2999 {
3000         u32 tx_queues_count = priv->plat->tx_queues_to_use;
3001         u32 mode_to_use;
3002         u32 queue;
3003
3004         /* queue 0 is reserved for legacy traffic */
3005         for (queue = 1; queue < tx_queues_count; queue++) {
3006                 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
3007                 if (mode_to_use == MTL_QUEUE_DCB)
3008                         continue;
3009
3010                 stmmac_config_cbs(priv, priv->hw,
3011                                 priv->plat->tx_queues_cfg[queue].send_slope,
3012                                 priv->plat->tx_queues_cfg[queue].idle_slope,
3013                                 priv->plat->tx_queues_cfg[queue].high_credit,
3014                                 priv->plat->tx_queues_cfg[queue].low_credit,
3015                                 queue);
3016         }
3017 }
3018
3019 /**
3020  *  stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
3021  *  @priv: driver private structure
3022  *  Description: It is used for mapping RX queues to RX dma channels
3023  */
3024 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
3025 {
3026         u32 rx_queues_count = priv->plat->rx_queues_to_use;
3027         u32 queue;
3028         u32 chan;
3029
3030         for (queue = 0; queue < rx_queues_count; queue++) {
3031                 chan = priv->plat->rx_queues_cfg[queue].chan;
3032                 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
3033         }
3034 }
3035
3036 /**
3037  *  stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
3038  *  @priv: driver private structure
3039  *  Description: It is used for configuring the RX Queue Priority
3040  */
3041 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
3042 {
3043         u32 rx_queues_count = priv->plat->rx_queues_to_use;
3044         u32 queue;
3045         u32 prio;
3046
3047         for (queue = 0; queue < rx_queues_count; queue++) {
3048                 if (!priv->plat->rx_queues_cfg[queue].use_prio)
3049                         continue;
3050
3051                 prio = priv->plat->rx_queues_cfg[queue].prio;
3052                 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
3053         }
3054 }
3055
3056 /**
3057  *  stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
3058  *  @priv: driver private structure
3059  *  Description: It is used for configuring the TX Queue Priority
3060  */
3061 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
3062 {
3063         u32 tx_queues_count = priv->plat->tx_queues_to_use;
3064         u32 queue;
3065         u32 prio;
3066
3067         for (queue = 0; queue < tx_queues_count; queue++) {
3068                 if (!priv->plat->tx_queues_cfg[queue].use_prio)
3069                         continue;
3070
3071                 prio = priv->plat->tx_queues_cfg[queue].prio;
3072                 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
3073         }
3074 }
3075
3076 /**
3077  *  stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
3078  *  @priv: driver private structure
3079  *  Description: It is used for configuring the RX queue routing
3080  */
3081 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
3082 {
3083         u32 rx_queues_count = priv->plat->rx_queues_to_use;
3084         u32 queue;
3085         u8 packet;
3086
3087         for (queue = 0; queue < rx_queues_count; queue++) {
3088                 /* no specific packet type routing specified for the queue */
3089                 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
3090                         continue;
3091
3092                 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
3093                 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
3094         }
3095 }
3096
3097 static void stmmac_mac_config_rss(struct stmmac_priv *priv)
3098 {
3099         if (!priv->dma_cap.rssen || !priv->plat->rss_en) {
3100                 priv->rss.enable = false;
3101                 return;
3102         }
3103
3104         if (priv->dev->features & NETIF_F_RXHASH)
3105                 priv->rss.enable = true;
3106         else
3107                 priv->rss.enable = false;
3108
3109         stmmac_rss_configure(priv, priv->hw, &priv->rss,
3110                              priv->plat->rx_queues_to_use);
3111 }
3112
3113 /**
3114  *  stmmac_mtl_configuration - Configure MTL
3115  *  @priv: driver private structure
3116  *  Description: It is used for configurring MTL
3117  */
3118 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
3119 {
3120         u32 rx_queues_count = priv->plat->rx_queues_to_use;
3121         u32 tx_queues_count = priv->plat->tx_queues_to_use;
3122
3123         if (tx_queues_count > 1)
3124                 stmmac_set_tx_queue_weight(priv);
3125
3126         /* Configure MTL RX algorithms */
3127         if (rx_queues_count > 1)
3128                 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
3129                                 priv->plat->rx_sched_algorithm);
3130
3131         /* Configure MTL TX algorithms */
3132         if (tx_queues_count > 1)
3133                 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
3134                                 priv->plat->tx_sched_algorithm);
3135
3136         /* Configure CBS in AVB TX queues */
3137         if (tx_queues_count > 1)
3138                 stmmac_configure_cbs(priv);
3139
3140         /* Map RX MTL to DMA channels */
3141         stmmac_rx_queue_dma_chan_map(priv);
3142
3143         /* Enable MAC RX Queues */
3144         stmmac_mac_enable_rx_queues(priv);
3145
3146         /* Set RX priorities */
3147         if (rx_queues_count > 1)
3148                 stmmac_mac_config_rx_queues_prio(priv);
3149
3150         /* Set TX priorities */
3151         if (tx_queues_count > 1)
3152                 stmmac_mac_config_tx_queues_prio(priv);
3153
3154         /* Set RX routing */
3155         if (rx_queues_count > 1)
3156                 stmmac_mac_config_rx_queues_routing(priv);
3157
3158         /* Receive Side Scaling */
3159         if (rx_queues_count > 1)
3160                 stmmac_mac_config_rss(priv);
3161 }
3162
3163 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
3164 {
3165         if (priv->dma_cap.asp) {
3166                 netdev_info(priv->dev, "Enabling Safety Features\n");
3167                 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp,
3168                                           priv->plat->safety_feat_cfg);
3169         } else {
3170                 netdev_info(priv->dev, "No Safety Features support found\n");
3171         }
3172 }
3173
3174 static int stmmac_fpe_start_wq(struct stmmac_priv *priv)
3175 {
3176         char *name;
3177
3178         clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state);
3179         clear_bit(__FPE_REMOVING,  &priv->fpe_task_state);
3180
3181         name = priv->wq_name;
3182         sprintf(name, "%s-fpe", priv->dev->name);
3183
3184         priv->fpe_wq = create_singlethread_workqueue(name);
3185         if (!priv->fpe_wq) {
3186                 netdev_err(priv->dev, "%s: Failed to create workqueue\n", name);
3187
3188                 return -ENOMEM;
3189         }
3190         netdev_info(priv->dev, "FPE workqueue start");
3191
3192         return 0;
3193 }
3194
3195 /**
3196  * stmmac_hw_setup - setup mac in a usable state.
3197  *  @dev : pointer to the device structure.
3198  *  @init_ptp: initialize PTP if set
3199  *  Description:
3200  *  this is the main function to setup the HW in a usable state because the
3201  *  dma engine is reset, the core registers are configured (e.g. AXI,
3202  *  Checksum features, timers). The DMA is ready to start receiving and
3203  *  transmitting.
3204  *  Return value:
3205  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3206  *  file on failure.
3207  */
3208 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
3209 {
3210         struct stmmac_priv *priv = netdev_priv(dev);
3211         u32 rx_cnt = priv->plat->rx_queues_to_use;
3212         u32 tx_cnt = priv->plat->tx_queues_to_use;
3213         bool sph_en;
3214         u32 chan;
3215         int ret;
3216
3217         /* DMA initialization and SW reset */
3218         ret = stmmac_init_dma_engine(priv);
3219         if (ret < 0) {
3220                 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
3221                            __func__);
3222                 return ret;
3223         }
3224
3225         /* Copy the MAC addr into the HW  */
3226         stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
3227
3228         /* PS and related bits will be programmed according to the speed */
3229         if (priv->hw->pcs) {
3230                 int speed = priv->plat->mac_port_sel_speed;
3231
3232                 if ((speed == SPEED_10) || (speed == SPEED_100) ||
3233                     (speed == SPEED_1000)) {
3234                         priv->hw->ps = speed;
3235                 } else {
3236                         dev_warn(priv->device, "invalid port speed\n");
3237                         priv->hw->ps = 0;
3238                 }
3239         }
3240
3241         /* Initialize the MAC Core */
3242         stmmac_core_init(priv, priv->hw, dev);
3243
3244         /* Initialize MTL*/
3245         stmmac_mtl_configuration(priv);
3246
3247         /* Initialize Safety Features */
3248         stmmac_safety_feat_configuration(priv);
3249
3250         ret = stmmac_rx_ipc(priv, priv->hw);
3251         if (!ret) {
3252                 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
3253                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
3254                 priv->hw->rx_csum = 0;
3255         }
3256
3257         /* Enable the MAC Rx/Tx */
3258         stmmac_mac_set(priv, priv->ioaddr, true);
3259
3260         /* Set the HW DMA mode and the COE */
3261         stmmac_dma_operation_mode(priv);
3262
3263         stmmac_mmc_setup(priv);
3264
3265         if (init_ptp) {
3266                 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
3267                 if (ret < 0)
3268                         netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
3269
3270                 ret = stmmac_init_ptp(priv);
3271                 if (ret == -EOPNOTSUPP)
3272                         netdev_warn(priv->dev, "PTP not supported by HW\n");
3273                 else if (ret)
3274                         netdev_warn(priv->dev, "PTP init failed\n");
3275         }
3276
3277         priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS;
3278
3279         /* Convert the timer from msec to usec */
3280         if (!priv->tx_lpi_timer)
3281                 priv->tx_lpi_timer = eee_timer * 1000;
3282
3283         if (priv->use_riwt) {
3284                 u32 queue;
3285
3286                 for (queue = 0; queue < rx_cnt; queue++) {
3287                         if (!priv->rx_riwt[queue])
3288                                 priv->rx_riwt[queue] = DEF_DMA_RIWT;
3289
3290                         stmmac_rx_watchdog(priv, priv->ioaddr,
3291                                            priv->rx_riwt[queue], queue);
3292                 }
3293         }
3294
3295         if (priv->hw->pcs)
3296                 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0);
3297
3298         /* set TX and RX rings length */
3299         stmmac_set_rings_length(priv);
3300
3301         /* Enable TSO */
3302         if (priv->tso) {
3303                 for (chan = 0; chan < tx_cnt; chan++) {
3304                         struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
3305
3306                         /* TSO and TBS cannot co-exist */
3307                         if (tx_q->tbs & STMMAC_TBS_AVAIL)
3308                                 continue;
3309
3310                         stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
3311                 }
3312         }
3313
3314         /* Enable Split Header */
3315         sph_en = (priv->hw->rx_csum > 0) && priv->sph;
3316         for (chan = 0; chan < rx_cnt; chan++)
3317                 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
3318
3319
3320         /* VLAN Tag Insertion */
3321         if (priv->dma_cap.vlins)
3322                 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT);
3323
3324         /* TBS */
3325         for (chan = 0; chan < tx_cnt; chan++) {
3326                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
3327                 int enable = tx_q->tbs & STMMAC_TBS_AVAIL;
3328
3329                 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan);
3330         }
3331
3332         /* Configure real RX and TX queues */
3333         netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use);
3334         netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use);
3335
3336         /* Start the ball rolling... */
3337         stmmac_start_all_dma(priv);
3338
3339         if (priv->dma_cap.fpesel) {
3340                 stmmac_fpe_start_wq(priv);
3341
3342                 if (priv->plat->fpe_cfg->enable)
3343                         stmmac_fpe_handshake(priv, true);
3344         }
3345
3346         return 0;
3347 }
3348
3349 static void stmmac_hw_teardown(struct net_device *dev)
3350 {
3351         struct stmmac_priv *priv = netdev_priv(dev);
3352
3353         clk_disable_unprepare(priv->plat->clk_ptp_ref);
3354 }
3355
3356 static void stmmac_free_irq(struct net_device *dev,
3357                             enum request_irq_err irq_err, int irq_idx)
3358 {
3359         struct stmmac_priv *priv = netdev_priv(dev);
3360         int j;
3361
3362         switch (irq_err) {
3363         case REQ_IRQ_ERR_ALL:
3364                 irq_idx = priv->plat->tx_queues_to_use;
3365                 fallthrough;
3366         case REQ_IRQ_ERR_TX:
3367                 for (j = irq_idx - 1; j >= 0; j--) {
3368                         if (priv->tx_irq[j] > 0) {
3369                                 irq_set_affinity_hint(priv->tx_irq[j], NULL);
3370                                 free_irq(priv->tx_irq[j], &priv->tx_queue[j]);
3371                         }
3372                 }
3373                 irq_idx = priv->plat->rx_queues_to_use;
3374                 fallthrough;
3375         case REQ_IRQ_ERR_RX:
3376                 for (j = irq_idx - 1; j >= 0; j--) {
3377                         if (priv->rx_irq[j] > 0) {
3378                                 irq_set_affinity_hint(priv->rx_irq[j], NULL);
3379                                 free_irq(priv->rx_irq[j], &priv->rx_queue[j]);
3380                         }
3381                 }
3382
3383                 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq)
3384                         free_irq(priv->sfty_ue_irq, dev);
3385                 fallthrough;
3386         case REQ_IRQ_ERR_SFTY_UE:
3387                 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq)
3388                         free_irq(priv->sfty_ce_irq, dev);
3389                 fallthrough;
3390         case REQ_IRQ_ERR_SFTY_CE:
3391                 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq)
3392                         free_irq(priv->lpi_irq, dev);
3393                 fallthrough;
3394         case REQ_IRQ_ERR_LPI:
3395                 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq)
3396                         free_irq(priv->wol_irq, dev);
3397                 fallthrough;
3398         case REQ_IRQ_ERR_WOL:
3399                 free_irq(dev->irq, dev);
3400                 fallthrough;
3401         case REQ_IRQ_ERR_MAC:
3402         case REQ_IRQ_ERR_NO:
3403                 /* If MAC IRQ request error, no more IRQ to free */
3404                 break;
3405         }
3406 }
3407
3408 static int stmmac_request_irq_multi_msi(struct net_device *dev)
3409 {
3410         struct stmmac_priv *priv = netdev_priv(dev);
3411         enum request_irq_err irq_err;
3412         cpumask_t cpu_mask;
3413         int irq_idx = 0;
3414         char *int_name;
3415         int ret;
3416         int i;
3417
3418         /* For common interrupt */
3419         int_name = priv->int_name_mac;
3420         sprintf(int_name, "%s:%s", dev->name, "mac");
3421         ret = request_irq(dev->irq, stmmac_mac_interrupt,
3422                           0, int_name, dev);
3423         if (unlikely(ret < 0)) {
3424                 netdev_err(priv->dev,
3425                            "%s: alloc mac MSI %d (error: %d)\n",
3426                            __func__, dev->irq, ret);
3427                 irq_err = REQ_IRQ_ERR_MAC;
3428                 goto irq_error;
3429         }
3430
3431         /* Request the Wake IRQ in case of another line
3432          * is used for WoL
3433          */
3434         if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) {
3435                 int_name = priv->int_name_wol;
3436                 sprintf(int_name, "%s:%s", dev->name, "wol");
3437                 ret = request_irq(priv->wol_irq,
3438                                   stmmac_mac_interrupt,
3439                                   0, int_name, dev);
3440                 if (unlikely(ret < 0)) {
3441                         netdev_err(priv->dev,
3442                                    "%s: alloc wol MSI %d (error: %d)\n",
3443                                    __func__, priv->wol_irq, ret);
3444                         irq_err = REQ_IRQ_ERR_WOL;
3445                         goto irq_error;
3446                 }
3447         }
3448
3449         /* Request the LPI IRQ in case of another line
3450          * is used for LPI
3451          */
3452         if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) {
3453                 int_name = priv->int_name_lpi;
3454                 sprintf(int_name, "%s:%s", dev->name, "lpi");
3455                 ret = request_irq(priv->lpi_irq,
3456                                   stmmac_mac_interrupt,
3457                                   0, int_name, dev);
3458                 if (unlikely(ret < 0)) {
3459                         netdev_err(priv->dev,
3460                                    "%s: alloc lpi MSI %d (error: %d)\n",
3461                                    __func__, priv->lpi_irq, ret);
3462                         irq_err = REQ_IRQ_ERR_LPI;
3463                         goto irq_error;
3464                 }
3465         }
3466
3467         /* Request the Safety Feature Correctible Error line in
3468          * case of another line is used
3469          */
3470         if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) {
3471                 int_name = priv->int_name_sfty_ce;
3472                 sprintf(int_name, "%s:%s", dev->name, "safety-ce");
3473                 ret = request_irq(priv->sfty_ce_irq,
3474                                   stmmac_safety_interrupt,
3475                                   0, int_name, dev);
3476                 if (unlikely(ret < 0)) {
3477                         netdev_err(priv->dev,
3478                                    "%s: alloc sfty ce MSI %d (error: %d)\n",
3479                                    __func__, priv->sfty_ce_irq, ret);
3480                         irq_err = REQ_IRQ_ERR_SFTY_CE;
3481                         goto irq_error;
3482                 }
3483         }
3484
3485         /* Request the Safety Feature Uncorrectible Error line in
3486          * case of another line is used
3487          */
3488         if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) {
3489                 int_name = priv->int_name_sfty_ue;
3490                 sprintf(int_name, "%s:%s", dev->name, "safety-ue");
3491                 ret = request_irq(priv->sfty_ue_irq,
3492                                   stmmac_safety_interrupt,
3493                                   0, int_name, dev);
3494                 if (unlikely(ret < 0)) {
3495                         netdev_err(priv->dev,
3496                                    "%s: alloc sfty ue MSI %d (error: %d)\n",
3497                                    __func__, priv->sfty_ue_irq, ret);
3498                         irq_err = REQ_IRQ_ERR_SFTY_UE;
3499                         goto irq_error;
3500                 }
3501         }
3502
3503         /* Request Rx MSI irq */
3504         for (i = 0; i < priv->plat->rx_queues_to_use; i++) {
3505                 if (priv->rx_irq[i] == 0)
3506                         continue;
3507
3508                 int_name = priv->int_name_rx_irq[i];
3509                 sprintf(int_name, "%s:%s-%d", dev->name, "rx", i);
3510                 ret = request_irq(priv->rx_irq[i],
3511                                   stmmac_msi_intr_rx,
3512                                   0, int_name, &priv->rx_queue[i]);
3513                 if (unlikely(ret < 0)) {
3514                         netdev_err(priv->dev,
3515                                    "%s: alloc rx-%d  MSI %d (error: %d)\n",
3516                                    __func__, i, priv->rx_irq[i], ret);
3517                         irq_err = REQ_IRQ_ERR_RX;
3518                         irq_idx = i;
3519                         goto irq_error;
3520                 }
3521                 cpumask_clear(&cpu_mask);
3522                 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask);
3523                 irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask);
3524         }
3525
3526         /* Request Tx MSI irq */
3527         for (i = 0; i < priv->plat->tx_queues_to_use; i++) {
3528                 if (priv->tx_irq[i] == 0)
3529                         continue;
3530
3531                 int_name = priv->int_name_tx_irq[i];
3532                 sprintf(int_name, "%s:%s-%d", dev->name, "tx", i);
3533                 ret = request_irq(priv->tx_irq[i],
3534                                   stmmac_msi_intr_tx,
3535                                   0, int_name, &priv->tx_queue[i]);
3536                 if (unlikely(ret < 0)) {
3537                         netdev_err(priv->dev,
3538                                    "%s: alloc tx-%d  MSI %d (error: %d)\n",
3539                                    __func__, i, priv->tx_irq[i], ret);
3540                         irq_err = REQ_IRQ_ERR_TX;
3541                         irq_idx = i;
3542                         goto irq_error;
3543                 }
3544                 cpumask_clear(&cpu_mask);
3545                 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask);
3546                 irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask);
3547         }
3548
3549         return 0;
3550
3551 irq_error:
3552         stmmac_free_irq(dev, irq_err, irq_idx);
3553         return ret;
3554 }
3555
3556 static int stmmac_request_irq_single(struct net_device *dev)
3557 {
3558         struct stmmac_priv *priv = netdev_priv(dev);
3559         enum request_irq_err irq_err;
3560         int ret;
3561
3562         ret = request_irq(dev->irq, stmmac_interrupt,
3563                           IRQF_SHARED, dev->name, dev);
3564         if (unlikely(ret < 0)) {
3565                 netdev_err(priv->dev,
3566                            "%s: ERROR: allocating the IRQ %d (error: %d)\n",
3567                            __func__, dev->irq, ret);
3568                 irq_err = REQ_IRQ_ERR_MAC;
3569                 goto irq_error;
3570         }
3571
3572         /* Request the Wake IRQ in case of another line
3573          * is used for WoL
3574          */
3575         if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) {
3576                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
3577                                   IRQF_SHARED, dev->name, dev);
3578                 if (unlikely(ret < 0)) {
3579                         netdev_err(priv->dev,
3580                                    "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
3581                                    __func__, priv->wol_irq, ret);
3582                         irq_err = REQ_IRQ_ERR_WOL;
3583                         goto irq_error;
3584                 }
3585         }
3586
3587         /* Request the IRQ lines */
3588         if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) {
3589                 ret = request_irq(priv->lpi_irq, stmmac_interrupt,
3590                                   IRQF_SHARED, dev->name, dev);
3591                 if (unlikely(ret < 0)) {
3592                         netdev_err(priv->dev,
3593                                    "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
3594                                    __func__, priv->lpi_irq, ret);
3595                         irq_err = REQ_IRQ_ERR_LPI;
3596                         goto irq_error;
3597                 }
3598         }
3599
3600         return 0;
3601
3602 irq_error:
3603         stmmac_free_irq(dev, irq_err, 0);
3604         return ret;
3605 }
3606
3607 static int stmmac_request_irq(struct net_device *dev)
3608 {
3609         struct stmmac_priv *priv = netdev_priv(dev);
3610         int ret;
3611
3612         /* Request the IRQ lines */
3613         if (priv->plat->multi_msi_en)
3614                 ret = stmmac_request_irq_multi_msi(dev);
3615         else
3616                 ret = stmmac_request_irq_single(dev);
3617
3618         return ret;
3619 }
3620
3621 /**
3622  *  stmmac_open - open entry point of the driver
3623  *  @dev : pointer to the device structure.
3624  *  Description:
3625  *  This function is the open entry point of the driver.
3626  *  Return value:
3627  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3628  *  file on failure.
3629  */
3630 int stmmac_open(struct net_device *dev)
3631 {
3632         struct stmmac_priv *priv = netdev_priv(dev);
3633         int mode = priv->plat->phy_interface;
3634         int bfsize = 0;
3635         u32 chan;
3636         int ret;
3637
3638         ret = pm_runtime_get_sync(priv->device);
3639         if (ret < 0) {
3640                 pm_runtime_put_noidle(priv->device);
3641                 return ret;
3642         }
3643
3644         if (priv->hw->pcs != STMMAC_PCS_TBI &&
3645             priv->hw->pcs != STMMAC_PCS_RTBI &&
3646             (!priv->hw->xpcs ||
3647              xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73)) {
3648                 ret = stmmac_init_phy(dev);
3649                 if (ret) {
3650                         netdev_err(priv->dev,
3651                                    "%s: Cannot attach to PHY (error: %d)\n",
3652                                    __func__, ret);
3653                         goto init_phy_error;
3654                 }
3655         }
3656
3657         /* Extra statistics */
3658         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
3659         priv->xstats.threshold = tc;
3660
3661         bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
3662         if (bfsize < 0)
3663                 bfsize = 0;
3664
3665         if (bfsize < BUF_SIZE_16KiB)
3666                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
3667
3668         priv->dma_buf_sz = bfsize;
3669         buf_sz = bfsize;
3670
3671         priv->rx_copybreak = STMMAC_RX_COPYBREAK;
3672
3673         if (!priv->dma_tx_size)
3674                 priv->dma_tx_size = DMA_DEFAULT_TX_SIZE;
3675         if (!priv->dma_rx_size)
3676                 priv->dma_rx_size = DMA_DEFAULT_RX_SIZE;
3677
3678         /* Earlier check for TBS */
3679         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) {
3680                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
3681                 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en;
3682
3683                 /* Setup per-TXQ tbs flag before TX descriptor alloc */
3684                 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0;
3685         }
3686
3687         ret = alloc_dma_desc_resources(priv);
3688         if (ret < 0) {
3689                 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
3690                            __func__);
3691                 goto dma_desc_error;
3692         }
3693
3694         ret = init_dma_desc_rings(dev, GFP_KERNEL);
3695         if (ret < 0) {
3696                 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
3697                            __func__);
3698                 goto init_error;
3699         }
3700
3701         ret = stmmac_hw_setup(dev, true);
3702         if (ret < 0) {
3703                 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
3704                 goto init_error;
3705         }
3706
3707         stmmac_init_coalesce(priv);
3708
3709         phylink_start(priv->phylink);
3710         /* We may have called phylink_speed_down before */
3711         phylink_speed_up(priv->phylink);
3712
3713         ret = stmmac_request_irq(dev);
3714         if (ret)
3715                 goto irq_error;
3716
3717         stmmac_enable_all_queues(priv);
3718         netif_tx_start_all_queues(priv->dev);
3719
3720         return 0;
3721
3722 irq_error:
3723         phylink_stop(priv->phylink);
3724
3725         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
3726                 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
3727
3728         stmmac_hw_teardown(dev);
3729 init_error:
3730         free_dma_desc_resources(priv);
3731 dma_desc_error:
3732         phylink_disconnect_phy(priv->phylink);
3733 init_phy_error:
3734         pm_runtime_put(priv->device);
3735         return ret;
3736 }
3737
3738 static void stmmac_fpe_stop_wq(struct stmmac_priv *priv)
3739 {
3740         set_bit(__FPE_REMOVING, &priv->fpe_task_state);
3741
3742         if (priv->fpe_wq)
3743                 destroy_workqueue(priv->fpe_wq);
3744
3745         netdev_info(priv->dev, "FPE workqueue stop");
3746 }
3747
3748 /**
3749  *  stmmac_release - close entry point of the driver
3750  *  @dev : device pointer.
3751  *  Description:
3752  *  This is the stop entry point of the driver.
3753  */
3754 int stmmac_release(struct net_device *dev)
3755 {
3756         struct stmmac_priv *priv = netdev_priv(dev);
3757         u32 chan;
3758
3759         if (device_may_wakeup(priv->device))
3760                 phylink_speed_down(priv->phylink, false);
3761         /* Stop and disconnect the PHY */
3762         phylink_stop(priv->phylink);
3763         phylink_disconnect_phy(priv->phylink);
3764
3765         stmmac_disable_all_queues(priv);
3766
3767         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
3768                 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
3769
3770         /* Free the IRQ lines */
3771         stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0);
3772
3773         if (priv->eee_enabled) {
3774                 priv->tx_path_in_lpi_mode = false;
3775                 del_timer_sync(&priv->eee_ctrl_timer);
3776         }
3777
3778         /* Stop TX/RX DMA and clear the descriptors */
3779         stmmac_stop_all_dma(priv);
3780
3781         /* Release and free the Rx/Tx resources */
3782         free_dma_desc_resources(priv);
3783
3784         /* Disable the MAC Rx/Tx */
3785         stmmac_mac_set(priv, priv->ioaddr, false);
3786
3787         netif_carrier_off(dev);
3788
3789         stmmac_release_ptp(priv);
3790
3791         pm_runtime_put(priv->device);
3792
3793         if (priv->dma_cap.fpesel)
3794                 stmmac_fpe_stop_wq(priv);
3795
3796         return 0;
3797 }
3798
3799 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb,
3800                                struct stmmac_tx_queue *tx_q)
3801 {
3802         u16 tag = 0x0, inner_tag = 0x0;
3803         u32 inner_type = 0x0;
3804         struct dma_desc *p;
3805
3806         if (!priv->dma_cap.vlins)
3807                 return false;
3808         if (!skb_vlan_tag_present(skb))
3809                 return false;
3810         if (skb->vlan_proto == htons(ETH_P_8021AD)) {
3811                 inner_tag = skb_vlan_tag_get(skb);
3812                 inner_type = STMMAC_VLAN_INSERT;
3813         }
3814
3815         tag = skb_vlan_tag_get(skb);
3816
3817         if (tx_q->tbs & STMMAC_TBS_AVAIL)
3818                 p = &tx_q->dma_entx[tx_q->cur_tx].basic;
3819         else
3820                 p = &tx_q->dma_tx[tx_q->cur_tx];
3821
3822         if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type))
3823                 return false;
3824
3825         stmmac_set_tx_owner(priv, p);
3826         tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size);
3827         return true;
3828 }
3829
3830 /**
3831  *  stmmac_tso_allocator - close entry point of the driver
3832  *  @priv: driver private structure
3833  *  @des: buffer start address
3834  *  @total_len: total length to fill in descriptors
3835  *  @last_segment: condition for the last descriptor
3836  *  @queue: TX queue index
3837  *  Description:
3838  *  This function fills descriptor and request new descriptors according to
3839  *  buffer length to fill
3840  */
3841 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,
3842                                  int total_len, bool last_segment, u32 queue)
3843 {
3844         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3845         struct dma_desc *desc;
3846         u32 buff_size;
3847         int tmp_len;
3848
3849         tmp_len = total_len;
3850
3851         while (tmp_len > 0) {
3852                 dma_addr_t curr_addr;
3853
3854                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
3855                                                 priv->dma_tx_size);
3856                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
3857
3858                 if (tx_q->tbs & STMMAC_TBS_AVAIL)
3859                         desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
3860                 else
3861                         desc = &tx_q->dma_tx[tx_q->cur_tx];
3862
3863                 curr_addr = des + (total_len - tmp_len);
3864                 if (priv->dma_cap.addr64 <= 32)
3865                         desc->des0 = cpu_to_le32(curr_addr);
3866                 else
3867                         stmmac_set_desc_addr(priv, desc, curr_addr);
3868
3869                 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
3870                             TSO_MAX_BUFF_SIZE : tmp_len;
3871
3872                 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
3873                                 0, 1,
3874                                 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
3875                                 0, 0);
3876
3877                 tmp_len -= TSO_MAX_BUFF_SIZE;
3878         }
3879 }
3880
3881 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue)
3882 {
3883         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3884         int desc_size;
3885
3886         if (likely(priv->extend_desc))
3887                 desc_size = sizeof(struct dma_extended_desc);
3888         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
3889                 desc_size = sizeof(struct dma_edesc);
3890         else
3891                 desc_size = sizeof(struct dma_desc);
3892
3893         /* The own bit must be the latest setting done when prepare the
3894          * descriptor and then barrier is needed to make sure that
3895          * all is coherent before granting the DMA engine.
3896          */
3897         wmb();
3898
3899         tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size);
3900         stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3901 }
3902
3903 /**
3904  *  stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
3905  *  @skb : the socket buffer
3906  *  @dev : device pointer
3907  *  Description: this is the transmit function that is called on TSO frames
3908  *  (support available on GMAC4 and newer chips).
3909  *  Diagram below show the ring programming in case of TSO frames:
3910  *
3911  *  First Descriptor
3912  *   --------
3913  *   | DES0 |---> buffer1 = L2/L3/L4 header
3914  *   | DES1 |---> TCP Payload (can continue on next descr...)
3915  *   | DES2 |---> buffer 1 and 2 len
3916  *   | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
3917  *   --------
3918  *      |
3919  *     ...
3920  *      |
3921  *   --------
3922  *   | DES0 | --| Split TCP Payload on Buffers 1 and 2
3923  *   | DES1 | --|
3924  *   | DES2 | --> buffer 1 and 2 len
3925  *   | DES3 |
3926  *   --------
3927  *
3928  * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
3929  */
3930 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
3931 {
3932         struct dma_desc *desc, *first, *mss_desc = NULL;
3933         struct stmmac_priv *priv = netdev_priv(dev);
3934         int nfrags = skb_shinfo(skb)->nr_frags;
3935         u32 queue = skb_get_queue_mapping(skb);
3936         unsigned int first_entry, tx_packets;
3937         int tmp_pay_len = 0, first_tx;
3938         struct stmmac_tx_queue *tx_q;
3939         bool has_vlan, set_ic;
3940         u8 proto_hdr_len, hdr;
3941         u32 pay_len, mss;
3942         dma_addr_t des;
3943         int i;
3944
3945         tx_q = &priv->tx_queue[queue];
3946         first_tx = tx_q->cur_tx;
3947
3948         /* Compute header lengths */
3949         if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
3950                 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr);
3951                 hdr = sizeof(struct udphdr);
3952         } else {
3953                 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
3954                 hdr = tcp_hdrlen(skb);
3955         }
3956
3957         /* Desc availability based on threshold should be enough safe */
3958         if (unlikely(stmmac_tx_avail(priv, queue) <
3959                 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
3960                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3961                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3962                                                                 queue));
3963                         /* This is a hard error, log it. */
3964                         netdev_err(priv->dev,
3965                                    "%s: Tx Ring full when queue awake\n",
3966                                    __func__);
3967                 }
3968                 return NETDEV_TX_BUSY;
3969         }
3970
3971         pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
3972
3973         mss = skb_shinfo(skb)->gso_size;
3974
3975         /* set new MSS value if needed */
3976         if (mss != tx_q->mss) {
3977                 if (tx_q->tbs & STMMAC_TBS_AVAIL)
3978                         mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
3979                 else
3980                         mss_desc = &tx_q->dma_tx[tx_q->cur_tx];
3981
3982                 stmmac_set_mss(priv, mss_desc, mss);
3983                 tx_q->mss = mss;
3984                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
3985                                                 priv->dma_tx_size);
3986                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
3987         }
3988
3989         if (netif_msg_tx_queued(priv)) {
3990                 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
3991                         __func__, hdr, proto_hdr_len, pay_len, mss);
3992                 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
3993                         skb->data_len);
3994         }
3995
3996         /* Check if VLAN can be inserted by HW */
3997         has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
3998
3999         first_entry = tx_q->cur_tx;
4000         WARN_ON(tx_q->tx_skbuff[first_entry]);
4001
4002         if (tx_q->tbs & STMMAC_TBS_AVAIL)
4003                 desc = &tx_q->dma_entx[first_entry].basic;
4004         else
4005                 desc = &tx_q->dma_tx[first_entry];
4006         first = desc;
4007
4008         if (has_vlan)
4009                 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
4010
4011         /* first descriptor: fill Headers on Buf1 */
4012         des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
4013                              DMA_TO_DEVICE);
4014         if (dma_mapping_error(priv->device, des))
4015                 goto dma_map_err;
4016
4017         tx_q->tx_skbuff_dma[first_entry].buf = des;
4018         tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
4019         tx_q->tx_skbuff_dma[first_entry].map_as_page = false;
4020         tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB;
4021
4022         if (priv->dma_cap.addr64 <= 32) {
4023                 first->des0 = cpu_to_le32(des);
4024
4025                 /* Fill start of payload in buff2 of first descriptor */
4026                 if (pay_len)
4027                         first->des1 = cpu_to_le32(des + proto_hdr_len);
4028
4029                 /* If needed take extra descriptors to fill the remaining payload */
4030                 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
4031         } else {
4032                 stmmac_set_desc_addr(priv, first, des);
4033                 tmp_pay_len = pay_len;
4034                 des += proto_hdr_len;
4035                 pay_len = 0;
4036         }
4037
4038         stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
4039
4040         /* Prepare fragments */
4041         for (i = 0; i < nfrags; i++) {
4042                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4043
4044                 des = skb_frag_dma_map(priv->device, frag, 0,
4045                                        skb_frag_size(frag),
4046                                        DMA_TO_DEVICE);
4047                 if (dma_mapping_error(priv->device, des))
4048                         goto dma_map_err;
4049
4050                 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
4051                                      (i == nfrags - 1), queue);
4052
4053                 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
4054                 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
4055                 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
4056                 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB;
4057         }
4058
4059         tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
4060
4061         /* Only the last descriptor gets to point to the skb. */
4062         tx_q->tx_skbuff[tx_q->cur_tx] = skb;
4063         tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB;
4064
4065         /* Manage tx mitigation */
4066         tx_packets = (tx_q->cur_tx + 1) - first_tx;
4067         tx_q->tx_count_frames += tx_packets;
4068
4069         if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
4070                 set_ic = true;
4071         else if (!priv->tx_coal_frames[queue])
4072                 set_ic = false;
4073         else if (tx_packets > priv->tx_coal_frames[queue])
4074                 set_ic = true;
4075         else if ((tx_q->tx_count_frames %
4076                   priv->tx_coal_frames[queue]) < tx_packets)
4077                 set_ic = true;
4078         else
4079                 set_ic = false;
4080
4081         if (set_ic) {
4082                 if (tx_q->tbs & STMMAC_TBS_AVAIL)
4083                         desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
4084                 else
4085                         desc = &tx_q->dma_tx[tx_q->cur_tx];
4086
4087                 tx_q->tx_count_frames = 0;
4088                 stmmac_set_tx_ic(priv, desc);
4089                 priv->xstats.tx_set_ic_bit++;
4090         }
4091
4092         /* We've used all descriptors we need for this skb, however,
4093          * advance cur_tx so that it references a fresh descriptor.
4094          * ndo_start_xmit will fill this descriptor the next time it's
4095          * called and stmmac_tx_clean may clean up to this descriptor.
4096          */
4097         tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size);
4098
4099         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
4100                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
4101                           __func__);
4102                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
4103         }
4104
4105         dev->stats.tx_bytes += skb->len;
4106         priv->xstats.tx_tso_frames++;
4107         priv->xstats.tx_tso_nfrags += nfrags;
4108
4109         if (priv->sarc_type)
4110                 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
4111
4112         skb_tx_timestamp(skb);
4113
4114         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4115                      priv->hwts_tx_en)) {
4116                 /* declare that device is doing timestamping */
4117                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4118                 stmmac_enable_tx_timestamp(priv, first);
4119         }
4120
4121         /* Complete the first descriptor before granting the DMA */
4122         stmmac_prepare_tso_tx_desc(priv, first, 1,
4123                         proto_hdr_len,
4124                         pay_len,
4125                         1, tx_q->tx_skbuff_dma[first_entry].last_segment,
4126                         hdr / 4, (skb->len - proto_hdr_len));
4127
4128         /* If context desc is used to change MSS */
4129         if (mss_desc) {
4130                 /* Make sure that first descriptor has been completely
4131                  * written, including its own bit. This is because MSS is
4132                  * actually before first descriptor, so we need to make
4133                  * sure that MSS's own bit is the last thing written.
4134                  */
4135                 dma_wmb();
4136                 stmmac_set_tx_owner(priv, mss_desc);
4137         }
4138
4139         if (netif_msg_pktdata(priv)) {
4140                 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
4141                         __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
4142                         tx_q->cur_tx, first, nfrags);
4143                 pr_info(">>> frame to be transmitted: ");
4144                 print_pkt(skb->data, skb_headlen(skb));
4145         }
4146
4147         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
4148
4149         stmmac_flush_tx_descriptors(priv, queue);
4150         stmmac_tx_timer_arm(priv, queue);
4151
4152         return NETDEV_TX_OK;
4153
4154 dma_map_err:
4155         dev_err(priv->device, "Tx dma map failed\n");
4156         dev_kfree_skb(skb);
4157         priv->dev->stats.tx_dropped++;
4158         return NETDEV_TX_OK;
4159 }
4160
4161 /**
4162  *  stmmac_xmit - Tx entry point of the driver
4163  *  @skb : the socket buffer
4164  *  @dev : device pointer
4165  *  Description : this is the tx entry point of the driver.
4166  *  It programs the chain or the ring and supports oversized frames
4167  *  and SG feature.
4168  */
4169 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
4170 {
4171         unsigned int first_entry, tx_packets, enh_desc;
4172         struct stmmac_priv *priv = netdev_priv(dev);
4173         unsigned int nopaged_len = skb_headlen(skb);
4174         int i, csum_insertion = 0, is_jumbo = 0;
4175         u32 queue = skb_get_queue_mapping(skb);
4176         int nfrags = skb_shinfo(skb)->nr_frags;
4177         int gso = skb_shinfo(skb)->gso_type;
4178         struct dma_edesc *tbs_desc = NULL;
4179         struct dma_desc *desc, *first;
4180         struct stmmac_tx_queue *tx_q;
4181         bool has_vlan, set_ic;
4182         int entry, first_tx;
4183         dma_addr_t des;
4184
4185         tx_q = &priv->tx_queue[queue];
4186         first_tx = tx_q->cur_tx;
4187
4188         if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en)
4189                 stmmac_disable_eee_mode(priv);
4190
4191         /* Manage oversized TCP frames for GMAC4 device */
4192         if (skb_is_gso(skb) && priv->tso) {
4193                 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6))
4194                         return stmmac_tso_xmit(skb, dev);
4195                 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4))
4196                         return stmmac_tso_xmit(skb, dev);
4197         }
4198
4199         if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
4200                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
4201                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
4202                                                                 queue));
4203                         /* This is a hard error, log it. */
4204                         netdev_err(priv->dev,
4205                                    "%s: Tx Ring full when queue awake\n",
4206                                    __func__);
4207                 }
4208                 return NETDEV_TX_BUSY;
4209         }
4210
4211         /* Check if VLAN can be inserted by HW */
4212         has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
4213
4214         entry = tx_q->cur_tx;
4215         first_entry = entry;
4216         WARN_ON(tx_q->tx_skbuff[first_entry]);
4217
4218         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
4219
4220         if (likely(priv->extend_desc))
4221                 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4222         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4223                 desc = &tx_q->dma_entx[entry].basic;
4224         else
4225                 desc = tx_q->dma_tx + entry;
4226
4227         first = desc;
4228
4229         if (has_vlan)
4230                 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
4231
4232         enh_desc = priv->plat->enh_desc;
4233         /* To program the descriptors according to the size of the frame */
4234         if (enh_desc)
4235                 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
4236
4237         if (unlikely(is_jumbo)) {
4238                 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
4239                 if (unlikely(entry < 0) && (entry != -EINVAL))
4240                         goto dma_map_err;
4241         }
4242
4243         for (i = 0; i < nfrags; i++) {
4244                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4245                 int len = skb_frag_size(frag);
4246                 bool last_segment = (i == (nfrags - 1));
4247
4248                 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
4249                 WARN_ON(tx_q->tx_skbuff[entry]);
4250
4251                 if (likely(priv->extend_desc))
4252                         desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4253                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4254                         desc = &tx_q->dma_entx[entry].basic;
4255                 else
4256                         desc = tx_q->dma_tx + entry;
4257
4258                 des = skb_frag_dma_map(priv->device, frag, 0, len,
4259                                        DMA_TO_DEVICE);
4260                 if (dma_mapping_error(priv->device, des))
4261                         goto dma_map_err; /* should reuse desc w/o issues */
4262
4263                 tx_q->tx_skbuff_dma[entry].buf = des;
4264
4265                 stmmac_set_desc_addr(priv, desc, des);
4266
4267                 tx_q->tx_skbuff_dma[entry].map_as_page = true;
4268                 tx_q->tx_skbuff_dma[entry].len = len;
4269                 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
4270                 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB;
4271
4272                 /* Prepare the descriptor and set the own bit too */
4273                 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
4274                                 priv->mode, 1, last_segment, skb->len);
4275         }
4276
4277         /* Only the last descriptor gets to point to the skb. */
4278         tx_q->tx_skbuff[entry] = skb;
4279         tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB;
4280
4281         /* According to the coalesce parameter the IC bit for the latest
4282          * segment is reset and the timer re-started to clean the tx status.
4283          * This approach takes care about the fragments: desc is the first
4284          * element in case of no SG.
4285          */
4286         tx_packets = (entry + 1) - first_tx;
4287         tx_q->tx_count_frames += tx_packets;
4288
4289         if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
4290                 set_ic = true;
4291         else if (!priv->tx_coal_frames[queue])
4292                 set_ic = false;
4293         else if (tx_packets > priv->tx_coal_frames[queue])
4294                 set_ic = true;
4295         else if ((tx_q->tx_count_frames %
4296                   priv->tx_coal_frames[queue]) < tx_packets)
4297                 set_ic = true;
4298         else
4299                 set_ic = false;
4300
4301         if (set_ic) {
4302                 if (likely(priv->extend_desc))
4303                         desc = &tx_q->dma_etx[entry].basic;
4304                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4305                         desc = &tx_q->dma_entx[entry].basic;
4306                 else
4307                         desc = &tx_q->dma_tx[entry];
4308
4309                 tx_q->tx_count_frames = 0;
4310                 stmmac_set_tx_ic(priv, desc);
4311                 priv->xstats.tx_set_ic_bit++;
4312         }
4313
4314         /* We've used all descriptors we need for this skb, however,
4315          * advance cur_tx so that it references a fresh descriptor.
4316          * ndo_start_xmit will fill this descriptor the next time it's
4317          * called and stmmac_tx_clean may clean up to this descriptor.
4318          */
4319         entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
4320         tx_q->cur_tx = entry;
4321
4322         if (netif_msg_pktdata(priv)) {
4323                 netdev_dbg(priv->dev,
4324                            "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
4325                            __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
4326                            entry, first, nfrags);
4327
4328                 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
4329                 print_pkt(skb->data, skb->len);
4330         }
4331
4332         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
4333                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
4334                           __func__);
4335                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
4336         }
4337
4338         dev->stats.tx_bytes += skb->len;
4339
4340         if (priv->sarc_type)
4341                 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
4342
4343         skb_tx_timestamp(skb);
4344
4345         /* Ready to fill the first descriptor and set the OWN bit w/o any
4346          * problems because all the descriptors are actually ready to be
4347          * passed to the DMA engine.
4348          */
4349         if (likely(!is_jumbo)) {
4350                 bool last_segment = (nfrags == 0);
4351
4352                 des = dma_map_single(priv->device, skb->data,
4353                                      nopaged_len, DMA_TO_DEVICE);
4354                 if (dma_mapping_error(priv->device, des))
4355                         goto dma_map_err;
4356
4357                 tx_q->tx_skbuff_dma[first_entry].buf = des;
4358                 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB;
4359                 tx_q->tx_skbuff_dma[first_entry].map_as_page = false;
4360
4361                 stmmac_set_desc_addr(priv, first, des);
4362
4363                 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
4364                 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
4365
4366                 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4367                              priv->hwts_tx_en)) {
4368                         /* declare that device is doing timestamping */
4369                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4370                         stmmac_enable_tx_timestamp(priv, first);
4371                 }
4372
4373                 /* Prepare the first descriptor setting the OWN bit too */
4374                 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
4375                                 csum_insertion, priv->mode, 0, last_segment,
4376                                 skb->len);
4377         }
4378
4379         if (tx_q->tbs & STMMAC_TBS_EN) {
4380                 struct timespec64 ts = ns_to_timespec64(skb->tstamp);
4381
4382                 tbs_desc = &tx_q->dma_entx[first_entry];
4383                 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec);
4384         }
4385
4386         stmmac_set_tx_owner(priv, first);
4387
4388         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
4389
4390         stmmac_enable_dma_transmission(priv, priv->ioaddr);
4391
4392         stmmac_flush_tx_descriptors(priv, queue);
4393         stmmac_tx_timer_arm(priv, queue);
4394
4395         return NETDEV_TX_OK;
4396
4397 dma_map_err:
4398         netdev_err(priv->dev, "Tx DMA map failed\n");
4399         dev_kfree_skb(skb);
4400         priv->dev->stats.tx_dropped++;
4401         return NETDEV_TX_OK;
4402 }
4403
4404 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
4405 {
4406         struct vlan_ethhdr *veth;
4407         __be16 vlan_proto;
4408         u16 vlanid;
4409
4410         veth = (struct vlan_ethhdr *)skb->data;
4411         vlan_proto = veth->h_vlan_proto;
4412
4413         if ((vlan_proto == htons(ETH_P_8021Q) &&
4414              dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
4415             (vlan_proto == htons(ETH_P_8021AD) &&
4416              dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
4417                 /* pop the vlan tag */
4418                 vlanid = ntohs(veth->h_vlan_TCI);
4419                 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
4420                 skb_pull(skb, VLAN_HLEN);
4421                 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
4422         }
4423 }
4424
4425 /**
4426  * stmmac_rx_refill - refill used skb preallocated buffers
4427  * @priv: driver private structure
4428  * @queue: RX queue index
4429  * Description : this is to reallocate the skb for the reception process
4430  * that is based on zero-copy.
4431  */
4432 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
4433 {
4434         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4435         int dirty = stmmac_rx_dirty(priv, queue);
4436         unsigned int entry = rx_q->dirty_rx;
4437
4438         while (dirty-- > 0) {
4439                 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
4440                 struct dma_desc *p;
4441                 bool use_rx_wd;
4442
4443                 if (priv->extend_desc)
4444                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
4445                 else
4446                         p = rx_q->dma_rx + entry;
4447
4448                 if (!buf->page) {
4449                         buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
4450                         if (!buf->page)
4451                                 break;
4452                 }
4453
4454                 if (priv->sph && !buf->sec_page) {
4455                         buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
4456                         if (!buf->sec_page)
4457                                 break;
4458
4459                         buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
4460                 }
4461
4462                 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset;
4463
4464                 stmmac_set_desc_addr(priv, p, buf->addr);
4465                 if (priv->sph)
4466                         stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true);
4467                 else
4468                         stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false);
4469                 stmmac_refill_desc3(priv, rx_q, p);
4470
4471                 rx_q->rx_count_frames++;
4472                 rx_q->rx_count_frames += priv->rx_coal_frames[queue];
4473                 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue])
4474                         rx_q->rx_count_frames = 0;
4475
4476                 use_rx_wd = !priv->rx_coal_frames[queue];
4477                 use_rx_wd |= rx_q->rx_count_frames > 0;
4478                 if (!priv->use_riwt)
4479                         use_rx_wd = false;
4480
4481                 dma_wmb();
4482                 stmmac_set_rx_owner(priv, p, use_rx_wd);
4483
4484                 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size);
4485         }
4486         rx_q->dirty_rx = entry;
4487         rx_q->rx_tail_addr = rx_q->dma_rx_phy +
4488                             (rx_q->dirty_rx * sizeof(struct dma_desc));
4489         stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
4490 }
4491
4492 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv,
4493                                        struct dma_desc *p,
4494                                        int status, unsigned int len)
4495 {
4496         unsigned int plen = 0, hlen = 0;
4497         int coe = priv->hw->rx_csum;
4498
4499         /* Not first descriptor, buffer is always zero */
4500         if (priv->sph && len)
4501                 return 0;
4502
4503         /* First descriptor, get split header length */
4504         stmmac_get_rx_header_len(priv, p, &hlen);
4505         if (priv->sph && hlen) {
4506                 priv->xstats.rx_split_hdr_pkt_n++;
4507                 return hlen;
4508         }
4509
4510         /* First descriptor, not last descriptor and not split header */
4511         if (status & rx_not_ls)
4512                 return priv->dma_buf_sz;
4513
4514         plen = stmmac_get_rx_frame_len(priv, p, coe);
4515
4516         /* First descriptor and last descriptor and not split header */
4517         return min_t(unsigned int, priv->dma_buf_sz, plen);
4518 }
4519
4520 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv,
4521                                        struct dma_desc *p,
4522                                        int status, unsigned int len)
4523 {
4524         int coe = priv->hw->rx_csum;
4525         unsigned int plen = 0;
4526
4527         /* Not split header, buffer is not available */
4528         if (!priv->sph)
4529                 return 0;
4530
4531         /* Not last descriptor */
4532         if (status & rx_not_ls)
4533                 return priv->dma_buf_sz;
4534
4535         plen = stmmac_get_rx_frame_len(priv, p, coe);
4536
4537         /* Last descriptor */
4538         return plen - len;
4539 }
4540
4541 static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue,
4542                                 struct xdp_frame *xdpf, bool dma_map)
4543 {
4544         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4545         unsigned int entry = tx_q->cur_tx;
4546         struct dma_desc *tx_desc;
4547         dma_addr_t dma_addr;
4548         bool set_ic;
4549
4550         if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv))
4551                 return STMMAC_XDP_CONSUMED;
4552
4553         if (likely(priv->extend_desc))
4554                 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4555         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4556                 tx_desc = &tx_q->dma_entx[entry].basic;
4557         else
4558                 tx_desc = tx_q->dma_tx + entry;
4559
4560         if (dma_map) {
4561                 dma_addr = dma_map_single(priv->device, xdpf->data,
4562                                           xdpf->len, DMA_TO_DEVICE);
4563                 if (dma_mapping_error(priv->device, dma_addr))
4564                         return STMMAC_XDP_CONSUMED;
4565
4566                 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO;
4567         } else {
4568                 struct page *page = virt_to_page(xdpf->data);
4569
4570                 dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) +
4571                            xdpf->headroom;
4572                 dma_sync_single_for_device(priv->device, dma_addr,
4573                                            xdpf->len, DMA_BIDIRECTIONAL);
4574
4575                 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX;
4576         }
4577
4578         tx_q->tx_skbuff_dma[entry].buf = dma_addr;
4579         tx_q->tx_skbuff_dma[entry].map_as_page = false;
4580         tx_q->tx_skbuff_dma[entry].len = xdpf->len;
4581         tx_q->tx_skbuff_dma[entry].last_segment = true;
4582         tx_q->tx_skbuff_dma[entry].is_jumbo = false;
4583
4584         tx_q->xdpf[entry] = xdpf;
4585
4586         stmmac_set_desc_addr(priv, tx_desc, dma_addr);
4587
4588         stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len,
4589                                true, priv->mode, true, true,
4590                                xdpf->len);
4591
4592         tx_q->tx_count_frames++;
4593
4594         if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0)
4595                 set_ic = true;
4596         else
4597                 set_ic = false;
4598
4599         if (set_ic) {
4600                 tx_q->tx_count_frames = 0;
4601                 stmmac_set_tx_ic(priv, tx_desc);
4602                 priv->xstats.tx_set_ic_bit++;
4603         }
4604
4605         stmmac_enable_dma_transmission(priv, priv->ioaddr);
4606
4607         entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
4608         tx_q->cur_tx = entry;
4609
4610         return STMMAC_XDP_TX;
4611 }
4612
4613 static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv,
4614                                    int cpu)
4615 {
4616         int index = cpu;
4617
4618         if (unlikely(index < 0))
4619                 index = 0;
4620
4621         while (index >= priv->plat->tx_queues_to_use)
4622                 index -= priv->plat->tx_queues_to_use;
4623
4624         return index;
4625 }
4626
4627 static int stmmac_xdp_xmit_back(struct stmmac_priv *priv,
4628                                 struct xdp_buff *xdp)
4629 {
4630         struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
4631         int cpu = smp_processor_id();
4632         struct netdev_queue *nq;
4633         int queue;
4634         int res;
4635
4636         if (unlikely(!xdpf))
4637                 return STMMAC_XDP_CONSUMED;
4638
4639         queue = stmmac_xdp_get_tx_queue(priv, cpu);
4640         nq = netdev_get_tx_queue(priv->dev, queue);
4641
4642         __netif_tx_lock(nq, cpu);
4643         /* Avoids TX time-out as we are sharing with slow path */
4644         nq->trans_start = jiffies;
4645
4646         res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false);
4647         if (res == STMMAC_XDP_TX)
4648                 stmmac_flush_tx_descriptors(priv, queue);
4649
4650         __netif_tx_unlock(nq);
4651
4652         return res;
4653 }
4654
4655 static int __stmmac_xdp_run_prog(struct stmmac_priv *priv,
4656                                  struct bpf_prog *prog,
4657                                  struct xdp_buff *xdp)
4658 {
4659         u32 act;
4660         int res;
4661
4662         act = bpf_prog_run_xdp(prog, xdp);
4663         switch (act) {
4664         case XDP_PASS:
4665                 res = STMMAC_XDP_PASS;
4666                 break;
4667         case XDP_TX:
4668                 res = stmmac_xdp_xmit_back(priv, xdp);
4669                 break;
4670         case XDP_REDIRECT:
4671                 if (xdp_do_redirect(priv->dev, xdp, prog) < 0)
4672                         res = STMMAC_XDP_CONSUMED;
4673                 else
4674                         res = STMMAC_XDP_REDIRECT;
4675                 break;
4676         default:
4677                 bpf_warn_invalid_xdp_action(act);
4678                 fallthrough;
4679         case XDP_ABORTED:
4680                 trace_xdp_exception(priv->dev, prog, act);
4681                 fallthrough;
4682         case XDP_DROP:
4683                 res = STMMAC_XDP_CONSUMED;
4684                 break;
4685         }
4686
4687         return res;
4688 }
4689
4690 static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv,
4691                                            struct xdp_buff *xdp)
4692 {
4693         struct bpf_prog *prog;
4694         int res;
4695
4696         prog = READ_ONCE(priv->xdp_prog);
4697         if (!prog) {
4698                 res = STMMAC_XDP_PASS;
4699                 goto out;
4700         }
4701
4702         res = __stmmac_xdp_run_prog(priv, prog, xdp);
4703 out:
4704         return ERR_PTR(-res);
4705 }
4706
4707 static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv,
4708                                    int xdp_status)
4709 {
4710         int cpu = smp_processor_id();
4711         int queue;
4712
4713         queue = stmmac_xdp_get_tx_queue(priv, cpu);
4714
4715         if (xdp_status & STMMAC_XDP_TX)
4716                 stmmac_tx_timer_arm(priv, queue);
4717
4718         if (xdp_status & STMMAC_XDP_REDIRECT)
4719                 xdp_do_flush();
4720 }
4721
4722 static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch,
4723                                                struct xdp_buff *xdp)
4724 {
4725         unsigned int metasize = xdp->data - xdp->data_meta;
4726         unsigned int datasize = xdp->data_end - xdp->data;
4727         struct sk_buff *skb;
4728
4729         skb = __napi_alloc_skb(&ch->rxtx_napi,
4730                                xdp->data_end - xdp->data_hard_start,
4731                                GFP_ATOMIC | __GFP_NOWARN);
4732         if (unlikely(!skb))
4733                 return NULL;
4734
4735         skb_reserve(skb, xdp->data - xdp->data_hard_start);
4736         memcpy(__skb_put(skb, datasize), xdp->data, datasize);
4737         if (metasize)
4738                 skb_metadata_set(skb, metasize);
4739
4740         return skb;
4741 }
4742
4743 static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue,
4744                                    struct dma_desc *p, struct dma_desc *np,
4745                                    struct xdp_buff *xdp)
4746 {
4747         struct stmmac_channel *ch = &priv->channel[queue];
4748         unsigned int len = xdp->data_end - xdp->data;
4749         enum pkt_hash_types hash_type;
4750         int coe = priv->hw->rx_csum;
4751         struct sk_buff *skb;
4752         u32 hash;
4753
4754         skb = stmmac_construct_skb_zc(ch, xdp);
4755         if (!skb) {
4756                 priv->dev->stats.rx_dropped++;
4757                 return;
4758         }
4759
4760         stmmac_get_rx_hwtstamp(priv, p, np, skb);
4761         stmmac_rx_vlan(priv->dev, skb);
4762         skb->protocol = eth_type_trans(skb, priv->dev);
4763
4764         if (unlikely(!coe))
4765                 skb_checksum_none_assert(skb);
4766         else
4767                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4768
4769         if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
4770                 skb_set_hash(skb, hash, hash_type);
4771
4772         skb_record_rx_queue(skb, queue);
4773         napi_gro_receive(&ch->rxtx_napi, skb);
4774
4775         priv->dev->stats.rx_packets++;
4776         priv->dev->stats.rx_bytes += len;
4777 }
4778
4779 static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
4780 {
4781         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4782         unsigned int entry = rx_q->dirty_rx;
4783         struct dma_desc *rx_desc = NULL;
4784         bool ret = true;
4785
4786         budget = min(budget, stmmac_rx_dirty(priv, queue));
4787
4788         while (budget-- > 0 && entry != rx_q->cur_rx) {
4789                 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
4790                 dma_addr_t dma_addr;
4791                 bool use_rx_wd;
4792
4793                 if (!buf->xdp) {
4794                         buf->xdp = xsk_buff_alloc(rx_q->xsk_pool);
4795                         if (!buf->xdp) {
4796                                 ret = false;
4797                                 break;
4798                         }
4799                 }
4800
4801                 if (priv->extend_desc)
4802                         rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry);
4803                 else
4804                         rx_desc = rx_q->dma_rx + entry;
4805
4806                 dma_addr = xsk_buff_xdp_get_dma(buf->xdp);
4807                 stmmac_set_desc_addr(priv, rx_desc, dma_addr);
4808                 stmmac_set_desc_sec_addr(priv, rx_desc, 0, false);
4809                 stmmac_refill_desc3(priv, rx_q, rx_desc);
4810
4811                 rx_q->rx_count_frames++;
4812                 rx_q->rx_count_frames += priv->rx_coal_frames[queue];
4813                 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue])
4814                         rx_q->rx_count_frames = 0;
4815
4816                 use_rx_wd = !priv->rx_coal_frames[queue];
4817                 use_rx_wd |= rx_q->rx_count_frames > 0;
4818                 if (!priv->use_riwt)
4819                         use_rx_wd = false;
4820
4821                 dma_wmb();
4822                 stmmac_set_rx_owner(priv, rx_desc, use_rx_wd);
4823
4824                 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size);
4825         }
4826
4827         if (rx_desc) {
4828                 rx_q->dirty_rx = entry;
4829                 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
4830                                      (rx_q->dirty_rx * sizeof(struct dma_desc));
4831                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
4832         }
4833
4834         return ret;
4835 }
4836
4837 static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue)
4838 {
4839         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4840         unsigned int count = 0, error = 0, len = 0;
4841         int dirty = stmmac_rx_dirty(priv, queue);
4842         unsigned int next_entry = rx_q->cur_rx;
4843         unsigned int desc_size;
4844         struct bpf_prog *prog;
4845         bool failure = false;
4846         int xdp_status = 0;
4847         int status = 0;
4848
4849         if (netif_msg_rx_status(priv)) {
4850                 void *rx_head;
4851
4852                 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
4853                 if (priv->extend_desc) {
4854                         rx_head = (void *)rx_q->dma_erx;
4855                         desc_size = sizeof(struct dma_extended_desc);
4856                 } else {
4857                         rx_head = (void *)rx_q->dma_rx;
4858                         desc_size = sizeof(struct dma_desc);
4859                 }
4860
4861                 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true,
4862                                     rx_q->dma_rx_phy, desc_size);
4863         }
4864         while (count < limit) {
4865                 struct stmmac_rx_buffer *buf;
4866                 unsigned int buf1_len = 0;
4867                 struct dma_desc *np, *p;
4868                 int entry;
4869                 int res;
4870
4871                 if (!count && rx_q->state_saved) {
4872                         error = rx_q->state.error;
4873                         len = rx_q->state.len;
4874                 } else {
4875                         rx_q->state_saved = false;
4876                         error = 0;
4877                         len = 0;
4878                 }
4879
4880                 if (count >= limit)
4881                         break;
4882
4883 read_again:
4884                 buf1_len = 0;
4885                 entry = next_entry;
4886                 buf = &rx_q->buf_pool[entry];
4887
4888                 if (dirty >= STMMAC_RX_FILL_BATCH) {
4889                         failure = failure ||
4890                                   !stmmac_rx_refill_zc(priv, queue, dirty);
4891                         dirty = 0;
4892                 }
4893
4894                 if (priv->extend_desc)
4895                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
4896                 else
4897                         p = rx_q->dma_rx + entry;
4898
4899                 /* read the status of the incoming frame */
4900                 status = stmmac_rx_status(priv, &priv->dev->stats,
4901                                           &priv->xstats, p);
4902                 /* check if managed by the DMA otherwise go ahead */
4903                 if (unlikely(status & dma_own))
4904                         break;
4905
4906                 /* Prefetch the next RX descriptor */
4907                 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
4908                                                 priv->dma_rx_size);
4909                 next_entry = rx_q->cur_rx;
4910
4911                 if (priv->extend_desc)
4912                         np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
4913                 else
4914                         np = rx_q->dma_rx + next_entry;
4915
4916                 prefetch(np);
4917
4918                 /* Ensure a valid XSK buffer before proceed */
4919                 if (!buf->xdp)
4920                         break;
4921
4922                 if (priv->extend_desc)
4923                         stmmac_rx_extended_status(priv, &priv->dev->stats,
4924                                                   &priv->xstats,
4925                                                   rx_q->dma_erx + entry);
4926                 if (unlikely(status == discard_frame)) {
4927                         xsk_buff_free(buf->xdp);
4928                         buf->xdp = NULL;
4929                         dirty++;
4930                         error = 1;
4931                         if (!priv->hwts_rx_en)
4932                                 priv->dev->stats.rx_errors++;
4933                 }
4934
4935                 if (unlikely(error && (status & rx_not_ls)))
4936                         goto read_again;
4937                 if (unlikely(error)) {
4938                         count++;
4939                         continue;
4940                 }
4941
4942                 /* XSK pool expects RX frame 1:1 mapped to XSK buffer */
4943                 if (likely(status & rx_not_ls)) {
4944                         xsk_buff_free(buf->xdp);
4945                         buf->xdp = NULL;
4946                         dirty++;
4947                         count++;
4948                         goto read_again;
4949                 }
4950
4951                 /* XDP ZC Frame only support primary buffers for now */
4952                 buf1_len = stmmac_rx_buf1_len(priv, p, status, len);
4953                 len += buf1_len;
4954
4955                 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
4956                  * Type frames (LLC/LLC-SNAP)
4957                  *
4958                  * llc_snap is never checked in GMAC >= 4, so this ACS
4959                  * feature is always disabled and packets need to be
4960                  * stripped manually.
4961                  */
4962                 if (likely(!(status & rx_not_ls)) &&
4963                     (likely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
4964                      unlikely(status != llc_snap))) {
4965                         buf1_len -= ETH_FCS_LEN;
4966                         len -= ETH_FCS_LEN;
4967                 }
4968
4969                 /* RX buffer is good and fit into a XSK pool buffer */
4970                 buf->xdp->data_end = buf->xdp->data + buf1_len;
4971                 xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool);
4972
4973                 prog = READ_ONCE(priv->xdp_prog);
4974                 res = __stmmac_xdp_run_prog(priv, prog, buf->xdp);
4975
4976                 switch (res) {
4977                 case STMMAC_XDP_PASS:
4978                         stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp);
4979                         xsk_buff_free(buf->xdp);
4980                         break;
4981                 case STMMAC_XDP_CONSUMED:
4982                         xsk_buff_free(buf->xdp);
4983                         priv->dev->stats.rx_dropped++;
4984                         break;
4985                 case STMMAC_XDP_TX:
4986                 case STMMAC_XDP_REDIRECT:
4987                         xdp_status |= res;
4988                         break;
4989                 }
4990
4991                 buf->xdp = NULL;
4992                 dirty++;
4993                 count++;
4994         }
4995
4996         if (status & rx_not_ls) {
4997                 rx_q->state_saved = true;
4998                 rx_q->state.error = error;
4999                 rx_q->state.len = len;
5000         }
5001
5002         stmmac_finalize_xdp_rx(priv, xdp_status);
5003
5004         priv->xstats.rx_pkt_n += count;
5005         priv->xstats.rxq_stats[queue].rx_pkt_n += count;
5006
5007         if (xsk_uses_need_wakeup(rx_q->xsk_pool)) {
5008                 if (failure || stmmac_rx_dirty(priv, queue) > 0)
5009                         xsk_set_rx_need_wakeup(rx_q->xsk_pool);
5010                 else
5011                         xsk_clear_rx_need_wakeup(rx_q->xsk_pool);
5012
5013                 return (int)count;
5014         }
5015
5016         return failure ? limit : (int)count;
5017 }
5018
5019 /**
5020  * stmmac_rx - manage the receive process
5021  * @priv: driver private structure
5022  * @limit: napi bugget
5023  * @queue: RX queue index.
5024  * Description :  this the function called by the napi poll method.
5025  * It gets all the frames inside the ring.
5026  */
5027 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
5028 {
5029         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
5030         struct stmmac_channel *ch = &priv->channel[queue];
5031         unsigned int count = 0, error = 0, len = 0;
5032         int status = 0, coe = priv->hw->rx_csum;
5033         unsigned int next_entry = rx_q->cur_rx;
5034         enum dma_data_direction dma_dir;
5035         unsigned int desc_size;
5036         struct sk_buff *skb = NULL;
5037         struct xdp_buff xdp;
5038         int xdp_status = 0;
5039         int buf_sz;
5040
5041         dma_dir = page_pool_get_dma_dir(rx_q->page_pool);
5042         buf_sz = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE;
5043
5044         if (netif_msg_rx_status(priv)) {
5045                 void *rx_head;
5046
5047                 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
5048                 if (priv->extend_desc) {
5049                         rx_head = (void *)rx_q->dma_erx;
5050                         desc_size = sizeof(struct dma_extended_desc);
5051                 } else {
5052                         rx_head = (void *)rx_q->dma_rx;
5053                         desc_size = sizeof(struct dma_desc);
5054                 }
5055
5056                 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true,
5057                                     rx_q->dma_rx_phy, desc_size);
5058         }
5059         while (count < limit) {
5060                 unsigned int buf1_len = 0, buf2_len = 0;
5061                 enum pkt_hash_types hash_type;
5062                 struct stmmac_rx_buffer *buf;
5063                 struct dma_desc *np, *p;
5064                 int entry;
5065                 u32 hash;
5066
5067                 if (!count && rx_q->state_saved) {
5068                         skb = rx_q->state.skb;
5069                         error = rx_q->state.error;
5070                         len = rx_q->state.len;
5071                 } else {
5072                         rx_q->state_saved = false;
5073                         skb = NULL;
5074                         error = 0;
5075                         len = 0;
5076                 }
5077
5078                 if (count >= limit)
5079                         break;
5080
5081 read_again:
5082                 buf1_len = 0;
5083                 buf2_len = 0;
5084                 entry = next_entry;
5085                 buf = &rx_q->buf_pool[entry];
5086
5087                 if (priv->extend_desc)
5088                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
5089                 else
5090                         p = rx_q->dma_rx + entry;
5091
5092                 /* read the status of the incoming frame */
5093                 status = stmmac_rx_status(priv, &priv->dev->stats,
5094                                 &priv->xstats, p);
5095                 /* check if managed by the DMA otherwise go ahead */
5096                 if (unlikely(status & dma_own))
5097                         break;
5098
5099                 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
5100                                                 priv->dma_rx_size);
5101                 next_entry = rx_q->cur_rx;
5102
5103                 if (priv->extend_desc)
5104                         np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
5105                 else
5106                         np = rx_q->dma_rx + next_entry;
5107
5108                 prefetch(np);
5109
5110                 if (priv->extend_desc)
5111                         stmmac_rx_extended_status(priv, &priv->dev->stats,
5112                                         &priv->xstats, rx_q->dma_erx + entry);
5113                 if (unlikely(status == discard_frame)) {
5114                         page_pool_recycle_direct(rx_q->page_pool, buf->page);
5115                         buf->page = NULL;
5116                         error = 1;
5117                         if (!priv->hwts_rx_en)
5118                                 priv->dev->stats.rx_errors++;
5119                 }
5120
5121                 if (unlikely(error && (status & rx_not_ls)))
5122                         goto read_again;
5123                 if (unlikely(error)) {
5124                         dev_kfree_skb(skb);
5125                         skb = NULL;
5126                         count++;
5127                         continue;
5128                 }
5129
5130                 /* Buffer is good. Go on. */
5131
5132                 prefetch(page_address(buf->page) + buf->page_offset);
5133                 if (buf->sec_page)
5134                         prefetch(page_address(buf->sec_page));
5135
5136                 buf1_len = stmmac_rx_buf1_len(priv, p, status, len);
5137                 len += buf1_len;
5138                 buf2_len = stmmac_rx_buf2_len(priv, p, status, len);
5139                 len += buf2_len;
5140
5141                 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
5142                  * Type frames (LLC/LLC-SNAP)
5143                  *
5144                  * llc_snap is never checked in GMAC >= 4, so this ACS
5145                  * feature is always disabled and packets need to be
5146                  * stripped manually.
5147                  */
5148                 if (likely(!(status & rx_not_ls)) &&
5149                     (likely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
5150                      unlikely(status != llc_snap))) {
5151                         if (buf2_len)
5152                                 buf2_len -= ETH_FCS_LEN;
5153                         else
5154                                 buf1_len -= ETH_FCS_LEN;
5155
5156                         len -= ETH_FCS_LEN;
5157                 }
5158
5159                 if (!skb) {
5160                         unsigned int pre_len, sync_len;
5161
5162                         dma_sync_single_for_cpu(priv->device, buf->addr,
5163                                                 buf1_len, dma_dir);
5164
5165                         xdp_init_buff(&xdp, buf_sz, &rx_q->xdp_rxq);
5166                         xdp_prepare_buff(&xdp, page_address(buf->page),
5167                                          buf->page_offset, buf1_len, false);
5168
5169                         pre_len = xdp.data_end - xdp.data_hard_start -
5170                                   buf->page_offset;
5171                         skb = stmmac_xdp_run_prog(priv, &xdp);
5172                         /* Due xdp_adjust_tail: DMA sync for_device
5173                          * cover max len CPU touch
5174                          */
5175                         sync_len = xdp.data_end - xdp.data_hard_start -
5176                                    buf->page_offset;
5177                         sync_len = max(sync_len, pre_len);
5178
5179                         /* For Not XDP_PASS verdict */
5180                         if (IS_ERR(skb)) {
5181                                 unsigned int xdp_res = -PTR_ERR(skb);
5182
5183                                 if (xdp_res & STMMAC_XDP_CONSUMED) {
5184                                         page_pool_put_page(rx_q->page_pool,
5185                                                            virt_to_head_page(xdp.data),
5186                                                            sync_len, true);
5187                                         buf->page = NULL;
5188                                         priv->dev->stats.rx_dropped++;
5189
5190                                         /* Clear skb as it was set as
5191                                          * status by XDP program.
5192                                          */
5193                                         skb = NULL;
5194
5195                                         if (unlikely((status & rx_not_ls)))
5196                                                 goto read_again;
5197
5198                                         count++;
5199                                         continue;
5200                                 } else if (xdp_res & (STMMAC_XDP_TX |
5201                                                       STMMAC_XDP_REDIRECT)) {
5202                                         xdp_status |= xdp_res;
5203                                         buf->page = NULL;
5204                                         skb = NULL;
5205                                         count++;
5206                                         continue;
5207                                 }
5208                         }
5209                 }
5210
5211                 if (!skb) {
5212                         /* XDP program may expand or reduce tail */
5213                         buf1_len = xdp.data_end - xdp.data;
5214
5215                         skb = napi_alloc_skb(&ch->rx_napi, buf1_len);
5216                         if (!skb) {
5217                                 priv->dev->stats.rx_dropped++;
5218                                 count++;
5219                                 goto drain_data;
5220                         }
5221
5222                         /* XDP program may adjust header */
5223                         skb_copy_to_linear_data(skb, xdp.data, buf1_len);
5224                         skb_put(skb, buf1_len);
5225
5226                         /* Data payload copied into SKB, page ready for recycle */
5227                         page_pool_recycle_direct(rx_q->page_pool, buf->page);
5228                         buf->page = NULL;
5229                 } else if (buf1_len) {
5230                         dma_sync_single_for_cpu(priv->device, buf->addr,
5231                                                 buf1_len, dma_dir);
5232                         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
5233                                         buf->page, buf->page_offset, buf1_len,
5234                                         priv->dma_buf_sz);
5235
5236                         /* Data payload appended into SKB */
5237                         page_pool_release_page(rx_q->page_pool, buf->page);
5238                         buf->page = NULL;
5239                 }
5240
5241                 if (buf2_len) {
5242                         dma_sync_single_for_cpu(priv->device, buf->sec_addr,
5243                                                 buf2_len, dma_dir);
5244                         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
5245                                         buf->sec_page, 0, buf2_len,
5246                                         priv->dma_buf_sz);
5247
5248                         /* Data payload appended into SKB */
5249                         page_pool_release_page(rx_q->page_pool, buf->sec_page);
5250                         buf->sec_page = NULL;
5251                 }
5252
5253 drain_data:
5254                 if (likely(status & rx_not_ls))
5255                         goto read_again;
5256                 if (!skb)
5257                         continue;
5258
5259                 /* Got entire packet into SKB. Finish it. */
5260
5261                 stmmac_get_rx_hwtstamp(priv, p, np, skb);
5262                 stmmac_rx_vlan(priv->dev, skb);
5263                 skb->protocol = eth_type_trans(skb, priv->dev);
5264
5265                 if (unlikely(!coe))
5266                         skb_checksum_none_assert(skb);
5267                 else
5268                         skb->ip_summed = CHECKSUM_UNNECESSARY;
5269
5270                 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
5271                         skb_set_hash(skb, hash, hash_type);
5272
5273                 skb_record_rx_queue(skb, queue);
5274                 napi_gro_receive(&ch->rx_napi, skb);
5275                 skb = NULL;
5276
5277                 priv->dev->stats.rx_packets++;
5278                 priv->dev->stats.rx_bytes += len;
5279                 count++;
5280         }
5281
5282         if (status & rx_not_ls || skb) {
5283                 rx_q->state_saved = true;
5284                 rx_q->state.skb = skb;
5285                 rx_q->state.error = error;
5286                 rx_q->state.len = len;
5287         }
5288
5289         stmmac_finalize_xdp_rx(priv, xdp_status);
5290
5291         stmmac_rx_refill(priv, queue);
5292
5293         priv->xstats.rx_pkt_n += count;
5294         priv->xstats.rxq_stats[queue].rx_pkt_n += count;
5295
5296         return count;
5297 }
5298
5299 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
5300 {
5301         struct stmmac_channel *ch =
5302                 container_of(napi, struct stmmac_channel, rx_napi);
5303         struct stmmac_priv *priv = ch->priv_data;
5304         u32 chan = ch->index;
5305         int work_done;
5306
5307         priv->xstats.napi_poll++;
5308
5309         work_done = stmmac_rx(priv, budget, chan);
5310         if (work_done < budget && napi_complete_done(napi, work_done)) {
5311                 unsigned long flags;
5312
5313                 spin_lock_irqsave(&ch->lock, flags);
5314                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0);
5315                 spin_unlock_irqrestore(&ch->lock, flags);
5316         }
5317
5318         return work_done;
5319 }
5320
5321 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
5322 {
5323         struct stmmac_channel *ch =
5324                 container_of(napi, struct stmmac_channel, tx_napi);
5325         struct stmmac_priv *priv = ch->priv_data;
5326         u32 chan = ch->index;
5327         int work_done;
5328
5329         priv->xstats.napi_poll++;
5330
5331         work_done = stmmac_tx_clean(priv, budget, chan);
5332         work_done = min(work_done, budget);
5333
5334         if (work_done < budget && napi_complete_done(napi, work_done)) {
5335                 unsigned long flags;
5336
5337                 spin_lock_irqsave(&ch->lock, flags);
5338                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1);
5339                 spin_unlock_irqrestore(&ch->lock, flags);
5340         }
5341
5342         return work_done;
5343 }
5344
5345 static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget)
5346 {
5347         struct stmmac_channel *ch =
5348                 container_of(napi, struct stmmac_channel, rxtx_napi);
5349         struct stmmac_priv *priv = ch->priv_data;
5350         int rx_done, tx_done, rxtx_done;
5351         u32 chan = ch->index;
5352
5353         priv->xstats.napi_poll++;
5354
5355         tx_done = stmmac_tx_clean(priv, budget, chan);
5356         tx_done = min(tx_done, budget);
5357
5358         rx_done = stmmac_rx_zc(priv, budget, chan);
5359
5360         rxtx_done = max(tx_done, rx_done);
5361
5362         /* If either TX or RX work is not complete, return budget
5363          * and keep pooling
5364          */
5365         if (rxtx_done >= budget)
5366                 return budget;
5367
5368         /* all work done, exit the polling mode */
5369         if (napi_complete_done(napi, rxtx_done)) {
5370                 unsigned long flags;
5371
5372                 spin_lock_irqsave(&ch->lock, flags);
5373                 /* Both RX and TX work done are compelte,
5374                  * so enable both RX & TX IRQs.
5375                  */
5376                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
5377                 spin_unlock_irqrestore(&ch->lock, flags);
5378         }
5379
5380         return min(rxtx_done, budget - 1);
5381 }
5382
5383 /**
5384  *  stmmac_tx_timeout
5385  *  @dev : Pointer to net device structure
5386  *  @txqueue: the index of the hanging transmit queue
5387  *  Description: this function is called when a packet transmission fails to
5388  *   complete within a reasonable time. The driver will mark the error in the
5389  *   netdev structure and arrange for the device to be reset to a sane state
5390  *   in order to transmit a new packet.
5391  */
5392 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue)
5393 {
5394         struct stmmac_priv *priv = netdev_priv(dev);
5395
5396         stmmac_global_err(priv);
5397 }
5398
5399 /**
5400  *  stmmac_set_rx_mode - entry point for multicast addressing
5401  *  @dev : pointer to the device structure
5402  *  Description:
5403  *  This function is a driver entry point which gets called by the kernel
5404  *  whenever multicast addresses must be enabled/disabled.
5405  *  Return value:
5406  *  void.
5407  */
5408 static void stmmac_set_rx_mode(struct net_device *dev)
5409 {
5410         struct stmmac_priv *priv = netdev_priv(dev);
5411
5412         stmmac_set_filter(priv, priv->hw, dev);
5413 }
5414
5415 /**
5416  *  stmmac_change_mtu - entry point to change MTU size for the device.
5417  *  @dev : device pointer.
5418  *  @new_mtu : the new MTU size for the device.
5419  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
5420  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
5421  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
5422  *  Return value:
5423  *  0 on success and an appropriate (-)ve integer as defined in errno.h
5424  *  file on failure.
5425  */
5426 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
5427 {
5428         struct stmmac_priv *priv = netdev_priv(dev);
5429         int txfifosz = priv->plat->tx_fifo_size;
5430         const int mtu = new_mtu;
5431
5432         if (txfifosz == 0)
5433                 txfifosz = priv->dma_cap.tx_fifo_size;
5434
5435         txfifosz /= priv->plat->tx_queues_to_use;
5436
5437         if (netif_running(dev)) {
5438                 netdev_err(priv->dev, "must be stopped to change its MTU\n");
5439                 return -EBUSY;
5440         }
5441
5442         if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) {
5443                 netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n");
5444                 return -EINVAL;
5445         }
5446
5447         new_mtu = STMMAC_ALIGN(new_mtu);
5448
5449         /* If condition true, FIFO is too small or MTU too large */
5450         if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB))
5451                 return -EINVAL;
5452
5453         dev->mtu = mtu;
5454
5455         netdev_update_features(dev);
5456
5457         return 0;
5458 }
5459
5460 static netdev_features_t stmmac_fix_features(struct net_device *dev,
5461                                              netdev_features_t features)
5462 {
5463         struct stmmac_priv *priv = netdev_priv(dev);
5464
5465         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
5466                 features &= ~NETIF_F_RXCSUM;
5467
5468         if (!priv->plat->tx_coe)
5469                 features &= ~NETIF_F_CSUM_MASK;
5470
5471         /* Some GMAC devices have a bugged Jumbo frame support that
5472          * needs to have the Tx COE disabled for oversized frames
5473          * (due to limited buffer sizes). In this case we disable
5474          * the TX csum insertion in the TDES and not use SF.
5475          */
5476         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
5477                 features &= ~NETIF_F_CSUM_MASK;
5478
5479         /* Disable tso if asked by ethtool */
5480         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
5481                 if (features & NETIF_F_TSO)
5482                         priv->tso = true;
5483                 else
5484                         priv->tso = false;
5485         }
5486
5487         return features;
5488 }
5489
5490 static int stmmac_set_features(struct net_device *netdev,
5491                                netdev_features_t features)
5492 {
5493         struct stmmac_priv *priv = netdev_priv(netdev);
5494         bool sph_en;
5495         u32 chan;
5496
5497         /* Keep the COE Type in case of csum is supporting */
5498         if (features & NETIF_F_RXCSUM)
5499                 priv->hw->rx_csum = priv->plat->rx_coe;
5500         else
5501                 priv->hw->rx_csum = 0;
5502         /* No check needed because rx_coe has been set before and it will be
5503          * fixed in case of issue.
5504          */
5505         stmmac_rx_ipc(priv, priv->hw);
5506
5507         sph_en = (priv->hw->rx_csum > 0) && priv->sph;
5508
5509         for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++)
5510                 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
5511
5512         return 0;
5513 }
5514
5515 static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status)
5516 {
5517         struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
5518         enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
5519         enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
5520         bool *hs_enable = &fpe_cfg->hs_enable;
5521
5522         if (status == FPE_EVENT_UNKNOWN || !*hs_enable)
5523                 return;
5524
5525         /* If LP has sent verify mPacket, LP is FPE capable */
5526         if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) {
5527                 if (*lp_state < FPE_STATE_CAPABLE)
5528                         *lp_state = FPE_STATE_CAPABLE;
5529
5530                 /* If user has requested FPE enable, quickly response */
5531                 if (*hs_enable)
5532                         stmmac_fpe_send_mpacket(priv, priv->ioaddr,
5533                                                 MPACKET_RESPONSE);
5534         }
5535
5536         /* If Local has sent verify mPacket, Local is FPE capable */
5537         if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) {
5538                 if (*lo_state < FPE_STATE_CAPABLE)
5539                         *lo_state = FPE_STATE_CAPABLE;
5540         }
5541
5542         /* If LP has sent response mPacket, LP is entering FPE ON */
5543         if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP)
5544                 *lp_state = FPE_STATE_ENTERING_ON;
5545
5546         /* If Local has sent response mPacket, Local is entering FPE ON */
5547         if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP)
5548                 *lo_state = FPE_STATE_ENTERING_ON;
5549
5550         if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) &&
5551             !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) &&
5552             priv->fpe_wq) {
5553                 queue_work(priv->fpe_wq, &priv->fpe_task);
5554         }
5555 }
5556
5557 static void stmmac_common_interrupt(struct stmmac_priv *priv)
5558 {
5559         u32 rx_cnt = priv->plat->rx_queues_to_use;
5560         u32 tx_cnt = priv->plat->tx_queues_to_use;
5561         u32 queues_count;
5562         u32 queue;
5563         bool xmac;
5564
5565         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
5566         queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
5567
5568         if (priv->irq_wake)
5569                 pm_wakeup_event(priv->device, 0);
5570
5571         if (priv->dma_cap.estsel)
5572                 stmmac_est_irq_status(priv, priv->ioaddr, priv->dev,
5573                                       &priv->xstats, tx_cnt);
5574
5575         if (priv->dma_cap.fpesel) {
5576                 int status = stmmac_fpe_irq_status(priv, priv->ioaddr,
5577                                                    priv->dev);
5578
5579                 stmmac_fpe_event_status(priv, status);
5580         }
5581
5582         /* To handle GMAC own interrupts */
5583         if ((priv->plat->has_gmac) || xmac) {
5584                 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
5585
5586                 if (unlikely(status)) {
5587                         /* For LPI we need to save the tx status */
5588                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
5589                                 priv->tx_path_in_lpi_mode = true;
5590                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
5591                                 priv->tx_path_in_lpi_mode = false;
5592                 }
5593
5594                 for (queue = 0; queue < queues_count; queue++) {
5595                         status = stmmac_host_mtl_irq_status(priv, priv->hw,
5596                                                             queue);
5597                 }
5598
5599                 /* PCS link status */
5600                 if (priv->hw->pcs) {
5601                         if (priv->xstats.pcs_link)
5602                                 netif_carrier_on(priv->dev);
5603                         else
5604                                 netif_carrier_off(priv->dev);
5605                 }
5606
5607                 stmmac_timestamp_interrupt(priv, priv);
5608         }
5609 }
5610
5611 /**
5612  *  stmmac_interrupt - main ISR
5613  *  @irq: interrupt number.
5614  *  @dev_id: to pass the net device pointer.
5615  *  Description: this is the main driver interrupt service routine.
5616  *  It can call:
5617  *  o DMA service routine (to manage incoming frame reception and transmission
5618  *    status)
5619  *  o Core interrupts to manage: remote wake-up, management counter, LPI
5620  *    interrupts.
5621  */
5622 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
5623 {
5624         struct net_device *dev = (struct net_device *)dev_id;
5625         struct stmmac_priv *priv = netdev_priv(dev);
5626
5627         /* Check if adapter is up */
5628         if (test_bit(STMMAC_DOWN, &priv->state))
5629                 return IRQ_HANDLED;
5630
5631         /* Check if a fatal error happened */
5632         if (stmmac_safety_feat_interrupt(priv))
5633                 return IRQ_HANDLED;
5634
5635         /* To handle Common interrupts */
5636         stmmac_common_interrupt(priv);
5637
5638         /* To handle DMA interrupts */
5639         stmmac_dma_interrupt(priv);
5640
5641         return IRQ_HANDLED;
5642 }
5643
5644 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id)
5645 {
5646         struct net_device *dev = (struct net_device *)dev_id;
5647         struct stmmac_priv *priv = netdev_priv(dev);
5648
5649         if (unlikely(!dev)) {
5650                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5651                 return IRQ_NONE;
5652         }
5653
5654         /* Check if adapter is up */
5655         if (test_bit(STMMAC_DOWN, &priv->state))
5656                 return IRQ_HANDLED;
5657
5658         /* To handle Common interrupts */
5659         stmmac_common_interrupt(priv);
5660
5661         return IRQ_HANDLED;
5662 }
5663
5664 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id)
5665 {
5666         struct net_device *dev = (struct net_device *)dev_id;
5667         struct stmmac_priv *priv = netdev_priv(dev);
5668
5669         if (unlikely(!dev)) {
5670                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5671                 return IRQ_NONE;
5672         }
5673
5674         /* Check if adapter is up */
5675         if (test_bit(STMMAC_DOWN, &priv->state))
5676                 return IRQ_HANDLED;
5677
5678         /* Check if a fatal error happened */
5679         stmmac_safety_feat_interrupt(priv);
5680
5681         return IRQ_HANDLED;
5682 }
5683
5684 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data)
5685 {
5686         struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data;
5687         int chan = tx_q->queue_index;
5688         struct stmmac_priv *priv;
5689         int status;
5690
5691         priv = container_of(tx_q, struct stmmac_priv, tx_queue[chan]);
5692
5693         if (unlikely(!data)) {
5694                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5695                 return IRQ_NONE;
5696         }
5697
5698         /* Check if adapter is up */
5699         if (test_bit(STMMAC_DOWN, &priv->state))
5700                 return IRQ_HANDLED;
5701
5702         status = stmmac_napi_check(priv, chan, DMA_DIR_TX);
5703
5704         if (unlikely(status & tx_hard_error_bump_tc)) {
5705                 /* Try to bump up the dma threshold on this failure */
5706                 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
5707                     tc <= 256) {
5708                         tc += 64;
5709                         if (priv->plat->force_thresh_dma_mode)
5710                                 stmmac_set_dma_operation_mode(priv,
5711                                                               tc,
5712                                                               tc,
5713                                                               chan);
5714                         else
5715                                 stmmac_set_dma_operation_mode(priv,
5716                                                               tc,
5717                                                               SF_DMA_MODE,
5718                                                               chan);
5719                         priv->xstats.threshold = tc;
5720                 }
5721         } else if (unlikely(status == tx_hard_error)) {
5722                 stmmac_tx_err(priv, chan);
5723         }
5724
5725         return IRQ_HANDLED;
5726 }
5727
5728 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data)
5729 {
5730         struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data;
5731         int chan = rx_q->queue_index;
5732         struct stmmac_priv *priv;
5733
5734         priv = container_of(rx_q, struct stmmac_priv, rx_queue[chan]);
5735
5736         if (unlikely(!data)) {
5737                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5738                 return IRQ_NONE;
5739         }
5740
5741         /* Check if adapter is up */
5742         if (test_bit(STMMAC_DOWN, &priv->state))
5743                 return IRQ_HANDLED;
5744
5745         stmmac_napi_check(priv, chan, DMA_DIR_RX);
5746
5747         return IRQ_HANDLED;
5748 }
5749
5750 #ifdef CONFIG_NET_POLL_CONTROLLER
5751 /* Polling receive - used by NETCONSOLE and other diagnostic tools
5752  * to allow network I/O with interrupts disabled.
5753  */
5754 static void stmmac_poll_controller(struct net_device *dev)
5755 {
5756         struct stmmac_priv *priv = netdev_priv(dev);
5757         int i;
5758
5759         /* If adapter is down, do nothing */
5760         if (test_bit(STMMAC_DOWN, &priv->state))
5761                 return;
5762
5763         if (priv->plat->multi_msi_en) {
5764                 for (i = 0; i < priv->plat->rx_queues_to_use; i++)
5765                         stmmac_msi_intr_rx(0, &priv->rx_queue[i]);
5766
5767                 for (i = 0; i < priv->plat->tx_queues_to_use; i++)
5768                         stmmac_msi_intr_tx(0, &priv->tx_queue[i]);
5769         } else {
5770                 disable_irq(dev->irq);
5771                 stmmac_interrupt(dev->irq, dev);
5772                 enable_irq(dev->irq);
5773         }
5774 }
5775 #endif
5776
5777 /**
5778  *  stmmac_ioctl - Entry point for the Ioctl
5779  *  @dev: Device pointer.
5780  *  @rq: An IOCTL specefic structure, that can contain a pointer to
5781  *  a proprietary structure used to pass information to the driver.
5782  *  @cmd: IOCTL command
5783  *  Description:
5784  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
5785  */
5786 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5787 {
5788         struct stmmac_priv *priv = netdev_priv (dev);
5789         int ret = -EOPNOTSUPP;
5790
5791         if (!netif_running(dev))
5792                 return -EINVAL;
5793
5794         switch (cmd) {
5795         case SIOCGMIIPHY:
5796         case SIOCGMIIREG:
5797         case SIOCSMIIREG:
5798                 ret = phylink_mii_ioctl(priv->phylink, rq, cmd);
5799                 break;
5800         case SIOCSHWTSTAMP:
5801                 ret = stmmac_hwtstamp_set(dev, rq);
5802                 break;
5803         case SIOCGHWTSTAMP:
5804                 ret = stmmac_hwtstamp_get(dev, rq);
5805                 break;
5806         default:
5807                 break;
5808         }
5809
5810         return ret;
5811 }
5812
5813 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5814                                     void *cb_priv)
5815 {
5816         struct stmmac_priv *priv = cb_priv;
5817         int ret = -EOPNOTSUPP;
5818
5819         if (!tc_cls_can_offload_and_chain0(priv->dev, type_data))
5820                 return ret;
5821
5822         __stmmac_disable_all_queues(priv);
5823
5824         switch (type) {
5825         case TC_SETUP_CLSU32:
5826                 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
5827                 break;
5828         case TC_SETUP_CLSFLOWER:
5829                 ret = stmmac_tc_setup_cls(priv, priv, type_data);
5830                 break;
5831         default:
5832                 break;
5833         }
5834
5835         stmmac_enable_all_queues(priv);
5836         return ret;
5837 }
5838
5839 static LIST_HEAD(stmmac_block_cb_list);
5840
5841 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
5842                            void *type_data)
5843 {
5844         struct stmmac_priv *priv = netdev_priv(ndev);
5845
5846         switch (type) {
5847         case TC_SETUP_BLOCK:
5848                 return flow_block_cb_setup_simple(type_data,
5849                                                   &stmmac_block_cb_list,
5850                                                   stmmac_setup_tc_block_cb,
5851                                                   priv, priv, true);
5852         case TC_SETUP_QDISC_CBS:
5853                 return stmmac_tc_setup_cbs(priv, priv, type_data);
5854         case TC_SETUP_QDISC_TAPRIO:
5855                 return stmmac_tc_setup_taprio(priv, priv, type_data);
5856         case TC_SETUP_QDISC_ETF:
5857                 return stmmac_tc_setup_etf(priv, priv, type_data);
5858         default:
5859                 return -EOPNOTSUPP;
5860         }
5861 }
5862
5863 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb,
5864                                struct net_device *sb_dev)
5865 {
5866         int gso = skb_shinfo(skb)->gso_type;
5867
5868         if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) {
5869                 /*
5870                  * There is no way to determine the number of TSO/USO
5871                  * capable Queues. Let's use always the Queue 0
5872                  * because if TSO/USO is supported then at least this
5873                  * one will be capable.
5874                  */
5875                 return 0;
5876         }
5877
5878         return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
5879 }
5880
5881 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
5882 {
5883         struct stmmac_priv *priv = netdev_priv(ndev);
5884         int ret = 0;
5885
5886         ret = pm_runtime_get_sync(priv->device);
5887         if (ret < 0) {
5888                 pm_runtime_put_noidle(priv->device);
5889                 return ret;
5890         }
5891
5892         ret = eth_mac_addr(ndev, addr);
5893         if (ret)
5894                 goto set_mac_error;
5895
5896         stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
5897
5898 set_mac_error:
5899         pm_runtime_put(priv->device);
5900
5901         return ret;
5902 }
5903
5904 #ifdef CONFIG_DEBUG_FS
5905 static struct dentry *stmmac_fs_dir;
5906
5907 static void sysfs_display_ring(void *head, int size, int extend_desc,
5908                                struct seq_file *seq, dma_addr_t dma_phy_addr)
5909 {
5910         int i;
5911         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
5912         struct dma_desc *p = (struct dma_desc *)head;
5913         dma_addr_t dma_addr;
5914
5915         for (i = 0; i < size; i++) {
5916                 if (extend_desc) {
5917                         dma_addr = dma_phy_addr + i * sizeof(*ep);
5918                         seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
5919                                    i, &dma_addr,
5920                                    le32_to_cpu(ep->basic.des0),
5921                                    le32_to_cpu(ep->basic.des1),
5922                                    le32_to_cpu(ep->basic.des2),
5923                                    le32_to_cpu(ep->basic.des3));
5924                         ep++;
5925                 } else {
5926                         dma_addr = dma_phy_addr + i * sizeof(*p);
5927                         seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
5928                                    i, &dma_addr,
5929                                    le32_to_cpu(p->des0), le32_to_cpu(p->des1),
5930                                    le32_to_cpu(p->des2), le32_to_cpu(p->des3));
5931                         p++;
5932                 }
5933                 seq_printf(seq, "\n");
5934         }
5935 }
5936
5937 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
5938 {
5939         struct net_device *dev = seq->private;
5940         struct stmmac_priv *priv = netdev_priv(dev);
5941         u32 rx_count = priv->plat->rx_queues_to_use;
5942         u32 tx_count = priv->plat->tx_queues_to_use;
5943         u32 queue;
5944
5945         if ((dev->flags & IFF_UP) == 0)
5946                 return 0;
5947
5948         for (queue = 0; queue < rx_count; queue++) {
5949                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
5950
5951                 seq_printf(seq, "RX Queue %d:\n", queue);
5952
5953                 if (priv->extend_desc) {
5954                         seq_printf(seq, "Extended descriptor ring:\n");
5955                         sysfs_display_ring((void *)rx_q->dma_erx,
5956                                            priv->dma_rx_size, 1, seq, rx_q->dma_rx_phy);
5957                 } else {
5958                         seq_printf(seq, "Descriptor ring:\n");
5959                         sysfs_display_ring((void *)rx_q->dma_rx,
5960                                            priv->dma_rx_size, 0, seq, rx_q->dma_rx_phy);
5961                 }
5962         }
5963
5964         for (queue = 0; queue < tx_count; queue++) {
5965                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
5966
5967                 seq_printf(seq, "TX Queue %d:\n", queue);
5968
5969                 if (priv->extend_desc) {
5970                         seq_printf(seq, "Extended descriptor ring:\n");
5971                         sysfs_display_ring((void *)tx_q->dma_etx,
5972                                            priv->dma_tx_size, 1, seq, tx_q->dma_tx_phy);
5973                 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) {
5974                         seq_printf(seq, "Descriptor ring:\n");
5975                         sysfs_display_ring((void *)tx_q->dma_tx,
5976                                            priv->dma_tx_size, 0, seq, tx_q->dma_tx_phy);
5977                 }
5978         }
5979
5980         return 0;
5981 }
5982 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
5983
5984 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
5985 {
5986         struct net_device *dev = seq->private;
5987         struct stmmac_priv *priv = netdev_priv(dev);
5988
5989         if (!priv->hw_cap_support) {
5990                 seq_printf(seq, "DMA HW features not supported\n");
5991                 return 0;
5992         }
5993
5994         seq_printf(seq, "==============================\n");
5995         seq_printf(seq, "\tDMA HW features\n");
5996         seq_printf(seq, "==============================\n");
5997
5998         seq_printf(seq, "\t10/100 Mbps: %s\n",
5999                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
6000         seq_printf(seq, "\t1000 Mbps: %s\n",
6001                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
6002         seq_printf(seq, "\tHalf duplex: %s\n",
6003                    (priv->dma_cap.half_duplex) ? "Y" : "N");
6004         seq_printf(seq, "\tHash Filter: %s\n",
6005                    (priv->dma_cap.hash_filter) ? "Y" : "N");
6006         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
6007                    (priv->dma_cap.multi_addr) ? "Y" : "N");
6008         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
6009                    (priv->dma_cap.pcs) ? "Y" : "N");
6010         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
6011                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
6012         seq_printf(seq, "\tPMT Remote wake up: %s\n",
6013                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
6014         seq_printf(seq, "\tPMT Magic Frame: %s\n",
6015                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
6016         seq_printf(seq, "\tRMON module: %s\n",
6017                    (priv->dma_cap.rmon) ? "Y" : "N");
6018         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
6019                    (priv->dma_cap.time_stamp) ? "Y" : "N");
6020         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
6021                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
6022         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
6023                    (priv->dma_cap.eee) ? "Y" : "N");
6024         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
6025         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
6026                    (priv->dma_cap.tx_coe) ? "Y" : "N");
6027         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
6028                 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
6029                            (priv->dma_cap.rx_coe) ? "Y" : "N");
6030         } else {
6031                 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
6032                            (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
6033                 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
6034                            (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
6035         }
6036         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
6037                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
6038         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
6039                    priv->dma_cap.number_rx_channel);
6040         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
6041                    priv->dma_cap.number_tx_channel);
6042         seq_printf(seq, "\tNumber of Additional RX queues: %d\n",
6043                    priv->dma_cap.number_rx_queues);
6044         seq_printf(seq, "\tNumber of Additional TX queues: %d\n",
6045                    priv->dma_cap.number_tx_queues);
6046         seq_printf(seq, "\tEnhanced descriptors: %s\n",
6047                    (priv->dma_cap.enh_desc) ? "Y" : "N");
6048         seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size);
6049         seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size);
6050         seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz);
6051         seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N");
6052         seq_printf(seq, "\tNumber of PPS Outputs: %d\n",
6053                    priv->dma_cap.pps_out_num);
6054         seq_printf(seq, "\tSafety Features: %s\n",
6055                    priv->dma_cap.asp ? "Y" : "N");
6056         seq_printf(seq, "\tFlexible RX Parser: %s\n",
6057                    priv->dma_cap.frpsel ? "Y" : "N");
6058         seq_printf(seq, "\tEnhanced Addressing: %d\n",
6059                    priv->dma_cap.addr64);
6060         seq_printf(seq, "\tReceive Side Scaling: %s\n",
6061                    priv->dma_cap.rssen ? "Y" : "N");
6062         seq_printf(seq, "\tVLAN Hash Filtering: %s\n",
6063                    priv->dma_cap.vlhash ? "Y" : "N");
6064         seq_printf(seq, "\tSplit Header: %s\n",
6065                    priv->dma_cap.sphen ? "Y" : "N");
6066         seq_printf(seq, "\tVLAN TX Insertion: %s\n",
6067                    priv->dma_cap.vlins ? "Y" : "N");
6068         seq_printf(seq, "\tDouble VLAN: %s\n",
6069                    priv->dma_cap.dvlan ? "Y" : "N");
6070         seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n",
6071                    priv->dma_cap.l3l4fnum);
6072         seq_printf(seq, "\tARP Offloading: %s\n",
6073                    priv->dma_cap.arpoffsel ? "Y" : "N");
6074         seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n",
6075                    priv->dma_cap.estsel ? "Y" : "N");
6076         seq_printf(seq, "\tFrame Preemption (FPE): %s\n",
6077                    priv->dma_cap.fpesel ? "Y" : "N");
6078         seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n",
6079                    priv->dma_cap.tbssel ? "Y" : "N");
6080         return 0;
6081 }
6082 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
6083
6084 /* Use network device events to rename debugfs file entries.
6085  */
6086 static int stmmac_device_event(struct notifier_block *unused,
6087                                unsigned long event, void *ptr)
6088 {
6089         struct net_device *dev = netdev_notifier_info_to_dev(ptr);
6090         struct stmmac_priv *priv = netdev_priv(dev);
6091
6092         if (dev->netdev_ops != &stmmac_netdev_ops)
6093                 goto done;
6094
6095         switch (event) {
6096         case NETDEV_CHANGENAME:
6097                 if (priv->dbgfs_dir)
6098                         priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir,
6099                                                          priv->dbgfs_dir,
6100                                                          stmmac_fs_dir,
6101                                                          dev->name);
6102                 break;
6103         }
6104 done:
6105         return NOTIFY_DONE;
6106 }
6107
6108 static struct notifier_block stmmac_notifier = {
6109         .notifier_call = stmmac_device_event,
6110 };
6111
6112 static void stmmac_init_fs(struct net_device *dev)
6113 {
6114         struct stmmac_priv *priv = netdev_priv(dev);
6115
6116         rtnl_lock();
6117
6118         /* Create per netdev entries */
6119         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
6120
6121         /* Entry to report DMA RX/TX rings */
6122         debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev,
6123                             &stmmac_rings_status_fops);
6124
6125         /* Entry to report the DMA HW features */
6126         debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev,
6127                             &stmmac_dma_cap_fops);
6128
6129         rtnl_unlock();
6130 }
6131
6132 static void stmmac_exit_fs(struct net_device *dev)
6133 {
6134         struct stmmac_priv *priv = netdev_priv(dev);
6135
6136         debugfs_remove_recursive(priv->dbgfs_dir);
6137 }
6138 #endif /* CONFIG_DEBUG_FS */
6139
6140 static u32 stmmac_vid_crc32_le(__le16 vid_le)
6141 {
6142         unsigned char *data = (unsigned char *)&vid_le;
6143         unsigned char data_byte = 0;
6144         u32 crc = ~0x0;
6145         u32 temp = 0;
6146         int i, bits;
6147
6148         bits = get_bitmask_order(VLAN_VID_MASK);
6149         for (i = 0; i < bits; i++) {
6150                 if ((i % 8) == 0)
6151                         data_byte = data[i / 8];
6152
6153                 temp = ((crc & 1) ^ data_byte) & 1;
6154                 crc >>= 1;
6155                 data_byte >>= 1;
6156
6157                 if (temp)
6158                         crc ^= 0xedb88320;
6159         }
6160
6161         return crc;
6162 }
6163
6164 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double)
6165 {
6166         u32 crc, hash = 0;
6167         __le16 pmatch = 0;
6168         int count = 0;
6169         u16 vid = 0;
6170
6171         for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
6172                 __le16 vid_le = cpu_to_le16(vid);
6173                 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28;
6174                 hash |= (1 << crc);
6175                 count++;
6176         }
6177
6178         if (!priv->dma_cap.vlhash) {
6179                 if (count > 2) /* VID = 0 always passes filter */
6180                         return -EOPNOTSUPP;
6181
6182                 pmatch = cpu_to_le16(vid);
6183                 hash = 0;
6184         }
6185
6186         return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double);
6187 }
6188
6189 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
6190 {
6191         struct stmmac_priv *priv = netdev_priv(ndev);
6192         bool is_double = false;
6193         int ret;
6194
6195         if (be16_to_cpu(proto) == ETH_P_8021AD)
6196                 is_double = true;
6197
6198         set_bit(vid, priv->active_vlans);
6199         ret = stmmac_vlan_update(priv, is_double);
6200         if (ret) {
6201                 clear_bit(vid, priv->active_vlans);
6202                 return ret;
6203         }
6204
6205         if (priv->hw->num_vlan) {
6206                 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid);
6207                 if (ret)
6208                         return ret;
6209         }
6210
6211         return 0;
6212 }
6213
6214 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
6215 {
6216         struct stmmac_priv *priv = netdev_priv(ndev);
6217         bool is_double = false;
6218         int ret;
6219
6220         ret = pm_runtime_get_sync(priv->device);
6221         if (ret < 0) {
6222                 pm_runtime_put_noidle(priv->device);
6223                 return ret;
6224         }
6225
6226         if (be16_to_cpu(proto) == ETH_P_8021AD)
6227                 is_double = true;
6228
6229         clear_bit(vid, priv->active_vlans);
6230
6231         if (priv->hw->num_vlan) {
6232                 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid);
6233                 if (ret)
6234                         goto del_vlan_error;
6235         }
6236
6237         ret = stmmac_vlan_update(priv, is_double);
6238
6239 del_vlan_error:
6240         pm_runtime_put(priv->device);
6241
6242         return ret;
6243 }
6244
6245 static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf)
6246 {
6247         struct stmmac_priv *priv = netdev_priv(dev);
6248
6249         switch (bpf->command) {
6250         case XDP_SETUP_PROG:
6251                 return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack);
6252         case XDP_SETUP_XSK_POOL:
6253                 return stmmac_xdp_setup_pool(priv, bpf->xsk.pool,
6254                                              bpf->xsk.queue_id);
6255         default:
6256                 return -EOPNOTSUPP;
6257         }
6258 }
6259
6260 static int stmmac_xdp_xmit(struct net_device *dev, int num_frames,
6261                            struct xdp_frame **frames, u32 flags)
6262 {
6263         struct stmmac_priv *priv = netdev_priv(dev);
6264         int cpu = smp_processor_id();
6265         struct netdev_queue *nq;
6266         int i, nxmit = 0;
6267         int queue;
6268
6269         if (unlikely(test_bit(STMMAC_DOWN, &priv->state)))
6270                 return -ENETDOWN;
6271
6272         if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
6273                 return -EINVAL;
6274
6275         queue = stmmac_xdp_get_tx_queue(priv, cpu);
6276         nq = netdev_get_tx_queue(priv->dev, queue);
6277
6278         __netif_tx_lock(nq, cpu);
6279         /* Avoids TX time-out as we are sharing with slow path */
6280         nq->trans_start = jiffies;
6281
6282         for (i = 0; i < num_frames; i++) {
6283                 int res;
6284
6285                 res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true);
6286                 if (res == STMMAC_XDP_CONSUMED)
6287                         break;
6288
6289                 nxmit++;
6290         }
6291
6292         if (flags & XDP_XMIT_FLUSH) {
6293                 stmmac_flush_tx_descriptors(priv, queue);
6294                 stmmac_tx_timer_arm(priv, queue);
6295         }
6296
6297         __netif_tx_unlock(nq);
6298
6299         return nxmit;
6300 }
6301
6302 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue)
6303 {
6304         struct stmmac_channel *ch = &priv->channel[queue];
6305         unsigned long flags;
6306
6307         spin_lock_irqsave(&ch->lock, flags);
6308         stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0);
6309         spin_unlock_irqrestore(&ch->lock, flags);
6310
6311         stmmac_stop_rx_dma(priv, queue);
6312         __free_dma_rx_desc_resources(priv, queue);
6313 }
6314
6315 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue)
6316 {
6317         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
6318         struct stmmac_channel *ch = &priv->channel[queue];
6319         unsigned long flags;
6320         u32 buf_size;
6321         int ret;
6322
6323         ret = __alloc_dma_rx_desc_resources(priv, queue);
6324         if (ret) {
6325                 netdev_err(priv->dev, "Failed to alloc RX desc.\n");
6326                 return;
6327         }
6328
6329         ret = __init_dma_rx_desc_rings(priv, queue, GFP_KERNEL);
6330         if (ret) {
6331                 __free_dma_rx_desc_resources(priv, queue);
6332                 netdev_err(priv->dev, "Failed to init RX desc.\n");
6333                 return;
6334         }
6335
6336         stmmac_clear_rx_descriptors(priv, queue);
6337
6338         stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6339                             rx_q->dma_rx_phy, rx_q->queue_index);
6340
6341         rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num *
6342                              sizeof(struct dma_desc));
6343         stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
6344                                rx_q->rx_tail_addr, rx_q->queue_index);
6345
6346         if (rx_q->xsk_pool && rx_q->buf_alloc_num) {
6347                 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
6348                 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6349                                       buf_size,
6350                                       rx_q->queue_index);
6351         } else {
6352                 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6353                                       priv->dma_buf_sz,
6354                                       rx_q->queue_index);
6355         }
6356
6357         stmmac_start_rx_dma(priv, queue);
6358
6359         spin_lock_irqsave(&ch->lock, flags);
6360         stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0);
6361         spin_unlock_irqrestore(&ch->lock, flags);
6362 }
6363
6364 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue)
6365 {
6366         struct stmmac_channel *ch = &priv->channel[queue];
6367         unsigned long flags;
6368
6369         spin_lock_irqsave(&ch->lock, flags);
6370         stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1);
6371         spin_unlock_irqrestore(&ch->lock, flags);
6372
6373         stmmac_stop_tx_dma(priv, queue);
6374         __free_dma_tx_desc_resources(priv, queue);
6375 }
6376
6377 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue)
6378 {
6379         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
6380         struct stmmac_channel *ch = &priv->channel[queue];
6381         unsigned long flags;
6382         int ret;
6383
6384         ret = __alloc_dma_tx_desc_resources(priv, queue);
6385         if (ret) {
6386                 netdev_err(priv->dev, "Failed to alloc TX desc.\n");
6387                 return;
6388         }
6389
6390         ret = __init_dma_tx_desc_rings(priv, queue);
6391         if (ret) {
6392                 __free_dma_tx_desc_resources(priv, queue);
6393                 netdev_err(priv->dev, "Failed to init TX desc.\n");
6394                 return;
6395         }
6396
6397         stmmac_clear_tx_descriptors(priv, queue);
6398
6399         stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6400                             tx_q->dma_tx_phy, tx_q->queue_index);
6401
6402         if (tx_q->tbs & STMMAC_TBS_AVAIL)
6403                 stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index);
6404
6405         tx_q->tx_tail_addr = tx_q->dma_tx_phy;
6406         stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
6407                                tx_q->tx_tail_addr, tx_q->queue_index);
6408
6409         stmmac_start_tx_dma(priv, queue);
6410
6411         spin_lock_irqsave(&ch->lock, flags);
6412         stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1);
6413         spin_unlock_irqrestore(&ch->lock, flags);
6414 }
6415
6416 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags)
6417 {
6418         struct stmmac_priv *priv = netdev_priv(dev);
6419         struct stmmac_rx_queue *rx_q;
6420         struct stmmac_tx_queue *tx_q;
6421         struct stmmac_channel *ch;
6422
6423         if (test_bit(STMMAC_DOWN, &priv->state) ||
6424             !netif_carrier_ok(priv->dev))
6425                 return -ENETDOWN;
6426
6427         if (!stmmac_xdp_is_enabled(priv))
6428                 return -ENXIO;
6429
6430         if (queue >= priv->plat->rx_queues_to_use ||
6431             queue >= priv->plat->tx_queues_to_use)
6432                 return -EINVAL;
6433
6434         rx_q = &priv->rx_queue[queue];
6435         tx_q = &priv->tx_queue[queue];
6436         ch = &priv->channel[queue];
6437
6438         if (!rx_q->xsk_pool && !tx_q->xsk_pool)
6439                 return -ENXIO;
6440
6441         if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) {
6442                 /* EQoS does not have per-DMA channel SW interrupt,
6443                  * so we schedule RX Napi straight-away.
6444                  */
6445                 if (likely(napi_schedule_prep(&ch->rxtx_napi)))
6446                         __napi_schedule(&ch->rxtx_napi);
6447         }
6448
6449         return 0;
6450 }
6451
6452 static const struct net_device_ops stmmac_netdev_ops = {
6453         .ndo_open = stmmac_open,
6454         .ndo_start_xmit = stmmac_xmit,
6455         .ndo_stop = stmmac_release,
6456         .ndo_change_mtu = stmmac_change_mtu,
6457         .ndo_fix_features = stmmac_fix_features,
6458         .ndo_set_features = stmmac_set_features,
6459         .ndo_set_rx_mode = stmmac_set_rx_mode,
6460         .ndo_tx_timeout = stmmac_tx_timeout,
6461         .ndo_eth_ioctl = stmmac_ioctl,
6462         .ndo_setup_tc = stmmac_setup_tc,
6463         .ndo_select_queue = stmmac_select_queue,
6464 #ifdef CONFIG_NET_POLL_CONTROLLER
6465         .ndo_poll_controller = stmmac_poll_controller,
6466 #endif
6467         .ndo_set_mac_address = stmmac_set_mac_address,
6468         .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid,
6469         .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid,
6470         .ndo_bpf = stmmac_bpf,
6471         .ndo_xdp_xmit = stmmac_xdp_xmit,
6472         .ndo_xsk_wakeup = stmmac_xsk_wakeup,
6473 };
6474
6475 static void stmmac_reset_subtask(struct stmmac_priv *priv)
6476 {
6477         if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
6478                 return;
6479         if (test_bit(STMMAC_DOWN, &priv->state))
6480                 return;
6481
6482         netdev_err(priv->dev, "Reset adapter.\n");
6483
6484         rtnl_lock();
6485         netif_trans_update(priv->dev);
6486         while (test_and_set_bit(STMMAC_RESETING, &priv->state))
6487                 usleep_range(1000, 2000);
6488
6489         set_bit(STMMAC_DOWN, &priv->state);
6490         dev_close(priv->dev);
6491         dev_open(priv->dev, NULL);
6492         clear_bit(STMMAC_DOWN, &priv->state);
6493         clear_bit(STMMAC_RESETING, &priv->state);
6494         rtnl_unlock();
6495 }
6496
6497 static void stmmac_service_task(struct work_struct *work)
6498 {
6499         struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
6500                         service_task);
6501
6502         stmmac_reset_subtask(priv);
6503         clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
6504 }
6505
6506 /**
6507  *  stmmac_hw_init - Init the MAC device
6508  *  @priv: driver private structure
6509  *  Description: this function is to configure the MAC device according to
6510  *  some platform parameters or the HW capability register. It prepares the
6511  *  driver to use either ring or chain modes and to setup either enhanced or
6512  *  normal descriptors.
6513  */
6514 static int stmmac_hw_init(struct stmmac_priv *priv)
6515 {
6516         int ret;
6517
6518         /* dwmac-sun8i only work in chain mode */
6519         if (priv->plat->has_sun8i)
6520                 chain_mode = 1;
6521         priv->chain_mode = chain_mode;
6522
6523         /* Initialize HW Interface */
6524         ret = stmmac_hwif_init(priv);
6525         if (ret)
6526                 return ret;
6527
6528         /* Get the HW capability (new GMAC newer than 3.50a) */
6529         priv->hw_cap_support = stmmac_get_hw_features(priv);
6530         if (priv->hw_cap_support) {
6531                 dev_info(priv->device, "DMA HW capability register supported\n");
6532
6533                 /* We can override some gmac/dma configuration fields: e.g.
6534                  * enh_desc, tx_coe (e.g. that are passed through the
6535                  * platform) with the values from the HW capability
6536                  * register (if supported).
6537                  */
6538                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
6539                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up &&
6540                                 !priv->plat->use_phy_wol;
6541                 priv->hw->pmt = priv->plat->pmt;
6542                 if (priv->dma_cap.hash_tb_sz) {
6543                         priv->hw->multicast_filter_bins =
6544                                         (BIT(priv->dma_cap.hash_tb_sz) << 5);
6545                         priv->hw->mcast_bits_log2 =
6546                                         ilog2(priv->hw->multicast_filter_bins);
6547                 }
6548
6549                 /* TXCOE doesn't work in thresh DMA mode */
6550                 if (priv->plat->force_thresh_dma_mode)
6551                         priv->plat->tx_coe = 0;
6552                 else
6553                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
6554
6555                 /* In case of GMAC4 rx_coe is from HW cap register. */
6556                 priv->plat->rx_coe = priv->dma_cap.rx_coe;
6557
6558                 if (priv->dma_cap.rx_coe_type2)
6559                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
6560                 else if (priv->dma_cap.rx_coe_type1)
6561                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
6562
6563         } else {
6564                 dev_info(priv->device, "No HW DMA feature register supported\n");
6565         }
6566
6567         if (priv->plat->rx_coe) {
6568                 priv->hw->rx_csum = priv->plat->rx_coe;
6569                 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
6570                 if (priv->synopsys_id < DWMAC_CORE_4_00)
6571                         dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
6572         }
6573         if (priv->plat->tx_coe)
6574                 dev_info(priv->device, "TX Checksum insertion supported\n");
6575
6576         if (priv->plat->pmt) {
6577                 dev_info(priv->device, "Wake-Up On Lan supported\n");
6578                 device_set_wakeup_capable(priv->device, 1);
6579         }
6580
6581         if (priv->dma_cap.tsoen)
6582                 dev_info(priv->device, "TSO supported\n");
6583
6584         priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en;
6585         priv->hw->vlan_fail_q = priv->plat->vlan_fail_q;
6586
6587         /* Run HW quirks, if any */
6588         if (priv->hwif_quirks) {
6589                 ret = priv->hwif_quirks(priv);
6590                 if (ret)
6591                         return ret;
6592         }
6593
6594         /* Rx Watchdog is available in the COREs newer than the 3.40.
6595          * In some case, for example on bugged HW this feature
6596          * has to be disable and this can be done by passing the
6597          * riwt_off field from the platform.
6598          */
6599         if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
6600             (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
6601                 priv->use_riwt = 1;
6602                 dev_info(priv->device,
6603                          "Enable RX Mitigation via HW Watchdog Timer\n");
6604         }
6605
6606         return 0;
6607 }
6608
6609 static void stmmac_napi_add(struct net_device *dev)
6610 {
6611         struct stmmac_priv *priv = netdev_priv(dev);
6612         u32 queue, maxq;
6613
6614         maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
6615
6616         for (queue = 0; queue < maxq; queue++) {
6617                 struct stmmac_channel *ch = &priv->channel[queue];
6618
6619                 ch->priv_data = priv;
6620                 ch->index = queue;
6621                 spin_lock_init(&ch->lock);
6622
6623                 if (queue < priv->plat->rx_queues_to_use) {
6624                         netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx,
6625                                        NAPI_POLL_WEIGHT);
6626                 }
6627                 if (queue < priv->plat->tx_queues_to_use) {
6628                         netif_tx_napi_add(dev, &ch->tx_napi,
6629                                           stmmac_napi_poll_tx,
6630                                           NAPI_POLL_WEIGHT);
6631                 }
6632                 if (queue < priv->plat->rx_queues_to_use &&
6633                     queue < priv->plat->tx_queues_to_use) {
6634                         netif_napi_add(dev, &ch->rxtx_napi,
6635                                        stmmac_napi_poll_rxtx,
6636                                        NAPI_POLL_WEIGHT);
6637                 }
6638         }
6639 }
6640
6641 static void stmmac_napi_del(struct net_device *dev)
6642 {
6643         struct stmmac_priv *priv = netdev_priv(dev);
6644         u32 queue, maxq;
6645
6646         maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
6647
6648         for (queue = 0; queue < maxq; queue++) {
6649                 struct stmmac_channel *ch = &priv->channel[queue];
6650
6651                 if (queue < priv->plat->rx_queues_to_use)
6652                         netif_napi_del(&ch->rx_napi);
6653                 if (queue < priv->plat->tx_queues_to_use)
6654                         netif_napi_del(&ch->tx_napi);
6655                 if (queue < priv->plat->rx_queues_to_use &&
6656                     queue < priv->plat->tx_queues_to_use) {
6657                         netif_napi_del(&ch->rxtx_napi);
6658                 }
6659         }
6660 }
6661
6662 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt)
6663 {
6664         struct stmmac_priv *priv = netdev_priv(dev);
6665         int ret = 0;
6666
6667         if (netif_running(dev))
6668                 stmmac_release(dev);
6669
6670         stmmac_napi_del(dev);
6671
6672         priv->plat->rx_queues_to_use = rx_cnt;
6673         priv->plat->tx_queues_to_use = tx_cnt;
6674
6675         stmmac_napi_add(dev);
6676
6677         if (netif_running(dev))
6678                 ret = stmmac_open(dev);
6679
6680         return ret;
6681 }
6682
6683 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size)
6684 {
6685         struct stmmac_priv *priv = netdev_priv(dev);
6686         int ret = 0;
6687
6688         if (netif_running(dev))
6689                 stmmac_release(dev);
6690
6691         priv->dma_rx_size = rx_size;
6692         priv->dma_tx_size = tx_size;
6693
6694         if (netif_running(dev))
6695                 ret = stmmac_open(dev);
6696
6697         return ret;
6698 }
6699
6700 #define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n"
6701 static void stmmac_fpe_lp_task(struct work_struct *work)
6702 {
6703         struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
6704                                                 fpe_task);
6705         struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
6706         enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
6707         enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
6708         bool *hs_enable = &fpe_cfg->hs_enable;
6709         bool *enable = &fpe_cfg->enable;
6710         int retries = 20;
6711
6712         while (retries-- > 0) {
6713                 /* Bail out immediately if FPE handshake is OFF */
6714                 if (*lo_state == FPE_STATE_OFF || !*hs_enable)
6715                         break;
6716
6717                 if (*lo_state == FPE_STATE_ENTERING_ON &&
6718                     *lp_state == FPE_STATE_ENTERING_ON) {
6719                         stmmac_fpe_configure(priv, priv->ioaddr,
6720                                              priv->plat->tx_queues_to_use,
6721                                              priv->plat->rx_queues_to_use,
6722                                              *enable);
6723
6724                         netdev_info(priv->dev, "configured FPE\n");
6725
6726                         *lo_state = FPE_STATE_ON;
6727                         *lp_state = FPE_STATE_ON;
6728                         netdev_info(priv->dev, "!!! BOTH FPE stations ON\n");
6729                         break;
6730                 }
6731
6732                 if ((*lo_state == FPE_STATE_CAPABLE ||
6733                      *lo_state == FPE_STATE_ENTERING_ON) &&
6734                      *lp_state != FPE_STATE_ON) {
6735                         netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT,
6736                                     *lo_state, *lp_state);
6737                         stmmac_fpe_send_mpacket(priv, priv->ioaddr,
6738                                                 MPACKET_VERIFY);
6739                 }
6740                 /* Sleep then retry */
6741                 msleep(500);
6742         }
6743
6744         clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state);
6745 }
6746
6747 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable)
6748 {
6749         if (priv->plat->fpe_cfg->hs_enable != enable) {
6750                 if (enable) {
6751                         stmmac_fpe_send_mpacket(priv, priv->ioaddr,
6752                                                 MPACKET_VERIFY);
6753                 } else {
6754                         priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF;
6755                         priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF;
6756                 }
6757
6758                 priv->plat->fpe_cfg->hs_enable = enable;
6759         }
6760 }
6761
6762 /**
6763  * stmmac_dvr_probe
6764  * @device: device pointer
6765  * @plat_dat: platform data pointer
6766  * @res: stmmac resource pointer
6767  * Description: this is the main probe function used to
6768  * call the alloc_etherdev, allocate the priv structure.
6769  * Return:
6770  * returns 0 on success, otherwise errno.
6771  */
6772 int stmmac_dvr_probe(struct device *device,
6773                      struct plat_stmmacenet_data *plat_dat,
6774                      struct stmmac_resources *res)
6775 {
6776         struct net_device *ndev = NULL;
6777         struct stmmac_priv *priv;
6778         u32 rxq;
6779         int i, ret = 0;
6780
6781         ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv),
6782                                        MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES);
6783         if (!ndev)
6784                 return -ENOMEM;
6785
6786         SET_NETDEV_DEV(ndev, device);
6787
6788         priv = netdev_priv(ndev);
6789         priv->device = device;
6790         priv->dev = ndev;
6791
6792         stmmac_set_ethtool_ops(ndev);
6793         priv->pause = pause;
6794         priv->plat = plat_dat;
6795         priv->ioaddr = res->addr;
6796         priv->dev->base_addr = (unsigned long)res->addr;
6797         priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en;
6798
6799         priv->dev->irq = res->irq;
6800         priv->wol_irq = res->wol_irq;
6801         priv->lpi_irq = res->lpi_irq;
6802         priv->sfty_ce_irq = res->sfty_ce_irq;
6803         priv->sfty_ue_irq = res->sfty_ue_irq;
6804         for (i = 0; i < MTL_MAX_RX_QUEUES; i++)
6805                 priv->rx_irq[i] = res->rx_irq[i];
6806         for (i = 0; i < MTL_MAX_TX_QUEUES; i++)
6807                 priv->tx_irq[i] = res->tx_irq[i];
6808
6809         if (!is_zero_ether_addr(res->mac))
6810                 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
6811
6812         dev_set_drvdata(device, priv->dev);
6813
6814         /* Verify driver arguments */
6815         stmmac_verify_args();
6816
6817         priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL);
6818         if (!priv->af_xdp_zc_qps)
6819                 return -ENOMEM;
6820
6821         /* Allocate workqueue */
6822         priv->wq = create_singlethread_workqueue("stmmac_wq");
6823         if (!priv->wq) {
6824                 dev_err(priv->device, "failed to create workqueue\n");
6825                 return -ENOMEM;
6826         }
6827
6828         INIT_WORK(&priv->service_task, stmmac_service_task);
6829
6830         /* Initialize Link Partner FPE workqueue */
6831         INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task);
6832
6833         /* Override with kernel parameters if supplied XXX CRS XXX
6834          * this needs to have multiple instances
6835          */
6836         if ((phyaddr >= 0) && (phyaddr <= 31))
6837                 priv->plat->phy_addr = phyaddr;
6838
6839         if (priv->plat->stmmac_rst) {
6840                 ret = reset_control_assert(priv->plat->stmmac_rst);
6841                 reset_control_deassert(priv->plat->stmmac_rst);
6842                 /* Some reset controllers have only reset callback instead of
6843                  * assert + deassert callbacks pair.
6844                  */
6845                 if (ret == -ENOTSUPP)
6846                         reset_control_reset(priv->plat->stmmac_rst);
6847         }
6848
6849         ret = reset_control_deassert(priv->plat->stmmac_ahb_rst);
6850         if (ret == -ENOTSUPP)
6851                 dev_err(priv->device, "unable to bring out of ahb reset: %pe\n",
6852                         ERR_PTR(ret));
6853
6854         /* Init MAC and get the capabilities */
6855         ret = stmmac_hw_init(priv);
6856         if (ret)
6857                 goto error_hw_init;
6858
6859         /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch.
6860          */
6861         if (priv->synopsys_id < DWMAC_CORE_5_20)
6862                 priv->plat->dma_cfg->dche = false;
6863
6864         stmmac_check_ether_addr(priv);
6865
6866         ndev->netdev_ops = &stmmac_netdev_ops;
6867
6868         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6869                             NETIF_F_RXCSUM;
6870
6871         ret = stmmac_tc_init(priv, priv);
6872         if (!ret) {
6873                 ndev->hw_features |= NETIF_F_HW_TC;
6874         }
6875
6876         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
6877                 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
6878                 if (priv->plat->has_gmac4)
6879                         ndev->hw_features |= NETIF_F_GSO_UDP_L4;
6880                 priv->tso = true;
6881                 dev_info(priv->device, "TSO feature enabled\n");
6882         }
6883
6884         if (priv->dma_cap.sphen) {
6885                 ndev->hw_features |= NETIF_F_GRO;
6886                 priv->sph_cap = true;
6887                 priv->sph = priv->sph_cap;
6888                 dev_info(priv->device, "SPH feature enabled\n");
6889         }
6890
6891         /* The current IP register MAC_HW_Feature1[ADDR64] only define
6892          * 32/40/64 bit width, but some SOC support others like i.MX8MP
6893          * support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64].
6894          * So overwrite dma_cap.addr64 according to HW real design.
6895          */
6896         if (priv->plat->addr64)
6897                 priv->dma_cap.addr64 = priv->plat->addr64;
6898
6899         if (priv->dma_cap.addr64) {
6900                 ret = dma_set_mask_and_coherent(device,
6901                                 DMA_BIT_MASK(priv->dma_cap.addr64));
6902                 if (!ret) {
6903                         dev_info(priv->device, "Using %d bits DMA width\n",
6904                                  priv->dma_cap.addr64);
6905
6906                         /*
6907                          * If more than 32 bits can be addressed, make sure to
6908                          * enable enhanced addressing mode.
6909                          */
6910                         if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
6911                                 priv->plat->dma_cfg->eame = true;
6912                 } else {
6913                         ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32));
6914                         if (ret) {
6915                                 dev_err(priv->device, "Failed to set DMA Mask\n");
6916                                 goto error_hw_init;
6917                         }
6918
6919                         priv->dma_cap.addr64 = 32;
6920                 }
6921         }
6922
6923         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
6924         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
6925 #ifdef STMMAC_VLAN_TAG_USED
6926         /* Both mac100 and gmac support receive VLAN tag detection */
6927         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
6928         if (priv->dma_cap.vlhash) {
6929                 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
6930                 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
6931         }
6932         if (priv->dma_cap.vlins) {
6933                 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX;
6934                 if (priv->dma_cap.dvlan)
6935                         ndev->features |= NETIF_F_HW_VLAN_STAG_TX;
6936         }
6937 #endif
6938         priv->msg_enable = netif_msg_init(debug, default_msg_level);
6939
6940         /* Initialize RSS */
6941         rxq = priv->plat->rx_queues_to_use;
6942         netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key));
6943         for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
6944                 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq);
6945
6946         if (priv->dma_cap.rssen && priv->plat->rss_en)
6947                 ndev->features |= NETIF_F_RXHASH;
6948
6949         /* MTU range: 46 - hw-specific max */
6950         ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
6951         if (priv->plat->has_xgmac)
6952                 ndev->max_mtu = XGMAC_JUMBO_LEN;
6953         else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
6954                 ndev->max_mtu = JUMBO_LEN;
6955         else
6956                 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
6957         /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
6958          * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
6959          */
6960         if ((priv->plat->maxmtu < ndev->max_mtu) &&
6961             (priv->plat->maxmtu >= ndev->min_mtu))
6962                 ndev->max_mtu = priv->plat->maxmtu;
6963         else if (priv->plat->maxmtu < ndev->min_mtu)
6964                 dev_warn(priv->device,
6965                          "%s: warning: maxmtu having invalid value (%d)\n",
6966                          __func__, priv->plat->maxmtu);
6967
6968         if (flow_ctrl)
6969                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
6970
6971         /* Setup channels NAPI */
6972         stmmac_napi_add(ndev);
6973
6974         mutex_init(&priv->lock);
6975
6976         /* If a specific clk_csr value is passed from the platform
6977          * this means that the CSR Clock Range selection cannot be
6978          * changed at run-time and it is fixed. Viceversa the driver'll try to
6979          * set the MDC clock dynamically according to the csr actual
6980          * clock input.
6981          */
6982         if (priv->plat->clk_csr >= 0)
6983                 priv->clk_csr = priv->plat->clk_csr;
6984         else
6985                 stmmac_clk_csr_set(priv);
6986
6987         stmmac_check_pcs_mode(priv);
6988
6989         pm_runtime_get_noresume(device);
6990         pm_runtime_set_active(device);
6991         pm_runtime_enable(device);
6992
6993         if (priv->hw->pcs != STMMAC_PCS_TBI &&
6994             priv->hw->pcs != STMMAC_PCS_RTBI) {
6995                 /* MDIO bus Registration */
6996                 ret = stmmac_mdio_register(ndev);
6997                 if (ret < 0) {
6998                         dev_err(priv->device,
6999                                 "%s: MDIO bus (id: %d) registration failed",
7000                                 __func__, priv->plat->bus_id);
7001                         goto error_mdio_register;
7002                 }
7003         }
7004
7005         if (priv->plat->speed_mode_2500)
7006                 priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv);
7007
7008         if (priv->plat->mdio_bus_data && priv->plat->mdio_bus_data->has_xpcs) {
7009                 ret = stmmac_xpcs_setup(priv->mii);
7010                 if (ret)
7011                         goto error_xpcs_setup;
7012         }
7013
7014         ret = stmmac_phy_setup(priv);
7015         if (ret) {
7016                 netdev_err(ndev, "failed to setup phy (%d)\n", ret);
7017                 goto error_phy_setup;
7018         }
7019
7020         ret = register_netdev(ndev);
7021         if (ret) {
7022                 dev_err(priv->device, "%s: ERROR %i registering the device\n",
7023                         __func__, ret);
7024                 goto error_netdev_register;
7025         }
7026
7027         if (priv->plat->serdes_powerup) {
7028                 ret = priv->plat->serdes_powerup(ndev,
7029                                                  priv->plat->bsp_priv);
7030
7031                 if (ret < 0)
7032                         goto error_serdes_powerup;
7033         }
7034
7035 #ifdef CONFIG_DEBUG_FS
7036         stmmac_init_fs(ndev);
7037 #endif
7038
7039         /* Let pm_runtime_put() disable the clocks.
7040          * If CONFIG_PM is not enabled, the clocks will stay powered.
7041          */
7042         pm_runtime_put(device);
7043
7044         return ret;
7045
7046 error_serdes_powerup:
7047         unregister_netdev(ndev);
7048 error_netdev_register:
7049         phylink_destroy(priv->phylink);
7050 error_xpcs_setup:
7051 error_phy_setup:
7052         if (priv->hw->pcs != STMMAC_PCS_TBI &&
7053             priv->hw->pcs != STMMAC_PCS_RTBI)
7054                 stmmac_mdio_unregister(ndev);
7055 error_mdio_register:
7056         stmmac_napi_del(ndev);
7057 error_hw_init:
7058         destroy_workqueue(priv->wq);
7059         bitmap_free(priv->af_xdp_zc_qps);
7060
7061         return ret;
7062 }
7063 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
7064
7065 /**
7066  * stmmac_dvr_remove
7067  * @dev: device pointer
7068  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
7069  * changes the link status, releases the DMA descriptor rings.
7070  */
7071 int stmmac_dvr_remove(struct device *dev)
7072 {
7073         struct net_device *ndev = dev_get_drvdata(dev);
7074         struct stmmac_priv *priv = netdev_priv(ndev);
7075
7076         netdev_info(priv->dev, "%s: removing driver", __func__);
7077
7078         stmmac_stop_all_dma(priv);
7079         stmmac_mac_set(priv, priv->ioaddr, false);
7080         netif_carrier_off(ndev);
7081         unregister_netdev(ndev);
7082
7083         /* Serdes power down needs to happen after VLAN filter
7084          * is deleted that is triggered by unregister_netdev().
7085          */
7086         if (priv->plat->serdes_powerdown)
7087                 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv);
7088
7089 #ifdef CONFIG_DEBUG_FS
7090         stmmac_exit_fs(ndev);
7091 #endif
7092         phylink_destroy(priv->phylink);
7093         if (priv->plat->stmmac_rst)
7094                 reset_control_assert(priv->plat->stmmac_rst);
7095         reset_control_assert(priv->plat->stmmac_ahb_rst);
7096         pm_runtime_put(dev);
7097         pm_runtime_disable(dev);
7098         if (priv->hw->pcs != STMMAC_PCS_TBI &&
7099             priv->hw->pcs != STMMAC_PCS_RTBI)
7100                 stmmac_mdio_unregister(ndev);
7101         destroy_workqueue(priv->wq);
7102         mutex_destroy(&priv->lock);
7103         bitmap_free(priv->af_xdp_zc_qps);
7104
7105         return 0;
7106 }
7107 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
7108
7109 /**
7110  * stmmac_suspend - suspend callback
7111  * @dev: device pointer
7112  * Description: this is the function to suspend the device and it is called
7113  * by the platform driver to stop the network queue, release the resources,
7114  * program the PMT register (for WoL), clean and release driver resources.
7115  */
7116 int stmmac_suspend(struct device *dev)
7117 {
7118         struct net_device *ndev = dev_get_drvdata(dev);
7119         struct stmmac_priv *priv = netdev_priv(ndev);
7120         u32 chan;
7121         int ret;
7122
7123         if (!ndev || !netif_running(ndev))
7124                 return 0;
7125
7126         mutex_lock(&priv->lock);
7127
7128         netif_device_detach(ndev);
7129
7130         stmmac_disable_all_queues(priv);
7131
7132         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
7133                 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
7134
7135         if (priv->eee_enabled) {
7136                 priv->tx_path_in_lpi_mode = false;
7137                 del_timer_sync(&priv->eee_ctrl_timer);
7138         }
7139
7140         /* Stop TX/RX DMA */
7141         stmmac_stop_all_dma(priv);
7142
7143         if (priv->plat->serdes_powerdown)
7144                 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv);
7145
7146         /* Enable Power down mode by programming the PMT regs */
7147         if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7148                 stmmac_pmt(priv, priv->hw, priv->wolopts);
7149                 priv->irq_wake = 1;
7150         } else {
7151                 stmmac_mac_set(priv, priv->ioaddr, false);
7152                 pinctrl_pm_select_sleep_state(priv->device);
7153                 /* Disable clock in case of PWM is off */
7154                 clk_disable_unprepare(priv->plat->clk_ptp_ref);
7155                 ret = pm_runtime_force_suspend(dev);
7156                 if (ret) {
7157                         mutex_unlock(&priv->lock);
7158                         return ret;
7159                 }
7160         }
7161
7162         mutex_unlock(&priv->lock);
7163
7164         rtnl_lock();
7165         if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7166                 phylink_suspend(priv->phylink, true);
7167         } else {
7168                 if (device_may_wakeup(priv->device))
7169                         phylink_speed_down(priv->phylink, false);
7170                 phylink_suspend(priv->phylink, false);
7171         }
7172         rtnl_unlock();
7173
7174         if (priv->dma_cap.fpesel) {
7175                 /* Disable FPE */
7176                 stmmac_fpe_configure(priv, priv->ioaddr,
7177                                      priv->plat->tx_queues_to_use,
7178                                      priv->plat->rx_queues_to_use, false);
7179
7180                 stmmac_fpe_handshake(priv, false);
7181                 stmmac_fpe_stop_wq(priv);
7182         }
7183
7184         priv->speed = SPEED_UNKNOWN;
7185         return 0;
7186 }
7187 EXPORT_SYMBOL_GPL(stmmac_suspend);
7188
7189 /**
7190  * stmmac_reset_queues_param - reset queue parameters
7191  * @priv: device pointer
7192  */
7193 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
7194 {
7195         u32 rx_cnt = priv->plat->rx_queues_to_use;
7196         u32 tx_cnt = priv->plat->tx_queues_to_use;
7197         u32 queue;
7198
7199         for (queue = 0; queue < rx_cnt; queue++) {
7200                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
7201
7202                 rx_q->cur_rx = 0;
7203                 rx_q->dirty_rx = 0;
7204         }
7205
7206         for (queue = 0; queue < tx_cnt; queue++) {
7207                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
7208
7209                 tx_q->cur_tx = 0;
7210                 tx_q->dirty_tx = 0;
7211                 tx_q->mss = 0;
7212
7213                 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
7214         }
7215 }
7216
7217 /**
7218  * stmmac_resume - resume callback
7219  * @dev: device pointer
7220  * Description: when resume this function is invoked to setup the DMA and CORE
7221  * in a usable state.
7222  */
7223 int stmmac_resume(struct device *dev)
7224 {
7225         struct net_device *ndev = dev_get_drvdata(dev);
7226         struct stmmac_priv *priv = netdev_priv(ndev);
7227         int ret;
7228
7229         if (!netif_running(ndev))
7230                 return 0;
7231
7232         /* Power Down bit, into the PM register, is cleared
7233          * automatically as soon as a magic packet or a Wake-up frame
7234          * is received. Anyway, it's better to manually clear
7235          * this bit because it can generate problems while resuming
7236          * from another devices (e.g. serial console).
7237          */
7238         if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7239                 mutex_lock(&priv->lock);
7240                 stmmac_pmt(priv, priv->hw, 0);
7241                 mutex_unlock(&priv->lock);
7242                 priv->irq_wake = 0;
7243         } else {
7244                 pinctrl_pm_select_default_state(priv->device);
7245                 /* enable the clk previously disabled */
7246                 ret = pm_runtime_force_resume(dev);
7247                 if (ret)
7248                         return ret;
7249                 if (priv->plat->clk_ptp_ref)
7250                         clk_prepare_enable(priv->plat->clk_ptp_ref);
7251                 /* reset the phy so that it's ready */
7252                 if (priv->mii)
7253                         stmmac_mdio_reset(priv->mii);
7254         }
7255
7256         if (priv->plat->serdes_powerup) {
7257                 ret = priv->plat->serdes_powerup(ndev,
7258                                                  priv->plat->bsp_priv);
7259
7260                 if (ret < 0)
7261                         return ret;
7262         }
7263
7264         rtnl_lock();
7265         if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7266                 phylink_resume(priv->phylink);
7267         } else {
7268                 phylink_resume(priv->phylink);
7269                 if (device_may_wakeup(priv->device))
7270                         phylink_speed_up(priv->phylink);
7271         }
7272         rtnl_unlock();
7273
7274         rtnl_lock();
7275         mutex_lock(&priv->lock);
7276
7277         stmmac_reset_queues_param(priv);
7278
7279         stmmac_free_tx_skbufs(priv);
7280         stmmac_clear_descriptors(priv);
7281
7282         stmmac_hw_setup(ndev, false);
7283         stmmac_init_coalesce(priv);
7284         stmmac_set_rx_mode(ndev);
7285
7286         stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw);
7287
7288         stmmac_enable_all_queues(priv);
7289
7290         mutex_unlock(&priv->lock);
7291         rtnl_unlock();
7292
7293         netif_device_attach(ndev);
7294
7295         return 0;
7296 }
7297 EXPORT_SYMBOL_GPL(stmmac_resume);
7298
7299 #ifndef MODULE
7300 static int __init stmmac_cmdline_opt(char *str)
7301 {
7302         char *opt;
7303
7304         if (!str || !*str)
7305                 return -EINVAL;
7306         while ((opt = strsep(&str, ",")) != NULL) {
7307                 if (!strncmp(opt, "debug:", 6)) {
7308                         if (kstrtoint(opt + 6, 0, &debug))
7309                                 goto err;
7310                 } else if (!strncmp(opt, "phyaddr:", 8)) {
7311                         if (kstrtoint(opt + 8, 0, &phyaddr))
7312                                 goto err;
7313                 } else if (!strncmp(opt, "buf_sz:", 7)) {
7314                         if (kstrtoint(opt + 7, 0, &buf_sz))
7315                                 goto err;
7316                 } else if (!strncmp(opt, "tc:", 3)) {
7317                         if (kstrtoint(opt + 3, 0, &tc))
7318                                 goto err;
7319                 } else if (!strncmp(opt, "watchdog:", 9)) {
7320                         if (kstrtoint(opt + 9, 0, &watchdog))
7321                                 goto err;
7322                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
7323                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
7324                                 goto err;
7325                 } else if (!strncmp(opt, "pause:", 6)) {
7326                         if (kstrtoint(opt + 6, 0, &pause))
7327                                 goto err;
7328                 } else if (!strncmp(opt, "eee_timer:", 10)) {
7329                         if (kstrtoint(opt + 10, 0, &eee_timer))
7330                                 goto err;
7331                 } else if (!strncmp(opt, "chain_mode:", 11)) {
7332                         if (kstrtoint(opt + 11, 0, &chain_mode))
7333                                 goto err;
7334                 }
7335         }
7336         return 0;
7337
7338 err:
7339         pr_err("%s: ERROR broken module parameter conversion", __func__);
7340         return -EINVAL;
7341 }
7342
7343 __setup("stmmaceth=", stmmac_cmdline_opt);
7344 #endif /* MODULE */
7345
7346 static int __init stmmac_init(void)
7347 {
7348 #ifdef CONFIG_DEBUG_FS
7349         /* Create debugfs main directory if it doesn't exist yet */
7350         if (!stmmac_fs_dir)
7351                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
7352         register_netdevice_notifier(&stmmac_notifier);
7353 #endif
7354
7355         return 0;
7356 }
7357
7358 static void __exit stmmac_exit(void)
7359 {
7360 #ifdef CONFIG_DEBUG_FS
7361         unregister_netdevice_notifier(&stmmac_notifier);
7362         debugfs_remove_recursive(stmmac_fs_dir);
7363 #endif
7364 }
7365
7366 module_init(stmmac_init)
7367 module_exit(stmmac_exit)
7368
7369 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
7370 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
7371 MODULE_LICENSE("GPL");