drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /**
   3  * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
   4  *
   5  * Copyright (C) 2014 Chen-Zhi (Roger Chen)
   6  *
   7  * Chen-Zhi (Roger Chen)  <roger.chen@rock-chips.com>
   8  */
   9
  10 #include <linux/stmmac.h>
  11 #include <linux/bitops.h>
  12 #include <linux/clk.h>
  13 #include <linux/phy.h>
  14 #include <linux/of_net.h>
  15 #include <linux/gpio.h>
  16 #include <linux/module.h>
  17 #include <linux/of_gpio.h>
  18 #include <linux/of_device.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/regulator/consumer.h>
  21 #include <linux/delay.h>
  22 #include <linux/mfd/syscon.h>
  23 #include <linux/regmap.h>
  24
  25 #include "stmmac_platform.h"
  26
  27 struct rk_priv_data;
  28 struct rk_gmac_ops {
  29         void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
  30                              int tx_delay, int rx_delay);
  31         void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
  32         void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
  33         void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
  34         void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);
  35         u32 regs[];
  36 };
  37
  38 struct rk_priv_data {
  39         struct platform_device *pdev;
  40         phy_interface_t phy_iface;
  41         int id;
  42         struct regulator *regulator;
  43         bool suspended;
  44         const struct rk_gmac_ops *ops;
  45
  46         bool clk_enabled;
  47         bool clock_input;
  48         bool integrated_phy;
  49
  50         struct clk *clk_mac;
  51         struct clk *gmac_clkin;
  52         struct clk *mac_clk_rx;
  53         struct clk *mac_clk_tx;
  54         struct clk *clk_mac_ref;
  55         struct clk *clk_mac_refout;
  56         struct clk *clk_mac_speed;
  57         struct clk *aclk_mac;
  58         struct clk *pclk_mac;
  59         struct clk *clk_phy;
  60
  61         struct reset_control *phy_reset;
  62
  63         int tx_delay;
  64         int rx_delay;
  65
  66         struct regmap *grf;
  67 };
  68
  69 #define HIWORD_UPDATE(val, mask, shift) \
  70                 ((val) << (shift) | (mask) << ((shift) + 16))
  71
  72 #define GRF_BIT(nr)     (BIT(nr) | BIT(nr+16))
  73 #define GRF_CLR_BIT(nr) (BIT(nr+16))
  74
  75 #define DELAY_ENABLE(soc, tx, rx) \
  76         (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
  77          ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
  78
  79 #define PX30_GRF_GMAC_CON1              0x0904
  80
  81 /* PX30_GRF_GMAC_CON1 */
  82 #define PX30_GMAC_PHY_INTF_SEL_RMII     (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
  83                                          GRF_BIT(6))
  84 #define PX30_GMAC_SPEED_10M             GRF_CLR_BIT(2)
  85 #define PX30_GMAC_SPEED_100M            GRF_BIT(2)
  86
  87 static void px30_set_to_rmii(struct rk_priv_data *bsp_priv)
  88 {
  89         struct device *dev = &bsp_priv->pdev->dev;
  90
  91         if (IS_ERR(bsp_priv->grf)) {
  92                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
  93                 return;
  94         }
  95
  96         regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
  97                      PX30_GMAC_PHY_INTF_SEL_RMII);
  98 }
  99
 100 static void px30_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 101 {
 102         struct device *dev = &bsp_priv->pdev->dev;
 103         int ret;
 104
 105         if (IS_ERR(bsp_priv->clk_mac_speed)) {
 106                 dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__);
 107                 return;
 108         }
 109
 110         if (speed == 10) {
 111                 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
 112                              PX30_GMAC_SPEED_10M);
 113
 114                 ret = clk_set_rate(bsp_priv->clk_mac_speed, 2500000);
 115                 if (ret)
 116                         dev_err(dev, "%s: set clk_mac_speed rate 2500000 failed: %d\n",
 117                                 __func__, ret);
 118         } else if (speed == 100) {
 119                 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
 120                              PX30_GMAC_SPEED_100M);
 121
 122                 ret = clk_set_rate(bsp_priv->clk_mac_speed, 25000000);
 123                 if (ret)
 124                         dev_err(dev, "%s: set clk_mac_speed rate 25000000 failed: %d\n",
 125                                 __func__, ret);
 126
 127         } else {
 128                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 129         }
 130 }
 131
 132 static const struct rk_gmac_ops px30_ops = {
 133         .set_to_rmii = px30_set_to_rmii,
 134         .set_rmii_speed = px30_set_rmii_speed,
 135 };
 136
 137 #define RK3128_GRF_MAC_CON0     0x0168
 138 #define RK3128_GRF_MAC_CON1     0x016c
 139
 140 /* RK3128_GRF_MAC_CON0 */
 141 #define RK3128_GMAC_TXCLK_DLY_ENABLE   GRF_BIT(14)
 142 #define RK3128_GMAC_TXCLK_DLY_DISABLE  GRF_CLR_BIT(14)
 143 #define RK3128_GMAC_RXCLK_DLY_ENABLE   GRF_BIT(15)
 144 #define RK3128_GMAC_RXCLK_DLY_DISABLE  GRF_CLR_BIT(15)
 145 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
 146 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
 147
 148 /* RK3128_GRF_MAC_CON1 */
 149 #define RK3128_GMAC_PHY_INTF_SEL_RGMII  \
 150                 (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8))
 151 #define RK3128_GMAC_PHY_INTF_SEL_RMII   \
 152                 (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8))
 153 #define RK3128_GMAC_FLOW_CTRL          GRF_BIT(9)
 154 #define RK3128_GMAC_FLOW_CTRL_CLR      GRF_CLR_BIT(9)
 155 #define RK3128_GMAC_SPEED_10M          GRF_CLR_BIT(10)
 156 #define RK3128_GMAC_SPEED_100M         GRF_BIT(10)
 157 #define RK3128_GMAC_RMII_CLK_25M       GRF_BIT(11)
 158 #define RK3128_GMAC_RMII_CLK_2_5M      GRF_CLR_BIT(11)
 159 #define RK3128_GMAC_CLK_125M           (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
 160 #define RK3128_GMAC_CLK_25M            (GRF_BIT(12) | GRF_BIT(13))
 161 #define RK3128_GMAC_CLK_2_5M           (GRF_CLR_BIT(12) | GRF_BIT(13))
 162 #define RK3128_GMAC_RMII_MODE          GRF_BIT(14)
 163 #define RK3128_GMAC_RMII_MODE_CLR      GRF_CLR_BIT(14)
 164
 165 static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
 166                                 int tx_delay, int rx_delay)
 167 {
 168         struct device *dev = &bsp_priv->pdev->dev;
 169
 170         if (IS_ERR(bsp_priv->grf)) {
 171                 dev_err(dev, "Missing rockchip,grf property\n");
 172                 return;
 173         }
 174
 175         regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 176                      RK3128_GMAC_PHY_INTF_SEL_RGMII |
 177                      RK3128_GMAC_RMII_MODE_CLR);
 178         regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0,
 179                      DELAY_ENABLE(RK3128, tx_delay, rx_delay) |
 180                      RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) |
 181                      RK3128_GMAC_CLK_TX_DL_CFG(tx_delay));
 182 }
 183
 184 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
 185 {
 186         struct device *dev = &bsp_priv->pdev->dev;
 187
 188         if (IS_ERR(bsp_priv->grf)) {
 189                 dev_err(dev, "Missing rockchip,grf property\n");
 190                 return;
 191         }
 192
 193         regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 194                      RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE);
 195 }
 196
 197 static void rk3128_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 198 {
 199         struct device *dev = &bsp_priv->pdev->dev;
 200
 201         if (IS_ERR(bsp_priv->grf)) {
 202                 dev_err(dev, "Missing rockchip,grf property\n");
 203                 return;
 204         }
 205
 206         if (speed == 10)
 207                 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 208                              RK3128_GMAC_CLK_2_5M);
 209         else if (speed == 100)
 210                 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 211                              RK3128_GMAC_CLK_25M);
 212         else if (speed == 1000)
 213                 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 214                              RK3128_GMAC_CLK_125M);
 215         else
 216                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 217 }
 218
 219 static void rk3128_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 220 {
 221         struct device *dev = &bsp_priv->pdev->dev;
 222
 223         if (IS_ERR(bsp_priv->grf)) {
 224                 dev_err(dev, "Missing rockchip,grf property\n");
 225                 return;
 226         }
 227
 228         if (speed == 10) {
 229                 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 230                              RK3128_GMAC_RMII_CLK_2_5M |
 231                              RK3128_GMAC_SPEED_10M);
 232         } else if (speed == 100) {
 233                 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 234                              RK3128_GMAC_RMII_CLK_25M |
 235                              RK3128_GMAC_SPEED_100M);
 236         } else {
 237                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 238         }
 239 }
 240
 241 static const struct rk_gmac_ops rk3128_ops = {
 242         .set_to_rgmii = rk3128_set_to_rgmii,
 243         .set_to_rmii = rk3128_set_to_rmii,
 244         .set_rgmii_speed = rk3128_set_rgmii_speed,
 245         .set_rmii_speed = rk3128_set_rmii_speed,
 246 };
 247
 248 #define RK3228_GRF_MAC_CON0     0x0900
 249 #define RK3228_GRF_MAC_CON1     0x0904
 250
 251 #define RK3228_GRF_CON_MUX      0x50
 252
 253 /* RK3228_GRF_MAC_CON0 */
 254 #define RK3228_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
 255 #define RK3228_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 256
 257 /* RK3228_GRF_MAC_CON1 */
 258 #define RK3228_GMAC_PHY_INTF_SEL_RGMII  \
 259                 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
 260 #define RK3228_GMAC_PHY_INTF_SEL_RMII   \
 261                 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
 262 #define RK3228_GMAC_FLOW_CTRL           GRF_BIT(3)
 263 #define RK3228_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(3)
 264 #define RK3228_GMAC_SPEED_10M           GRF_CLR_BIT(2)
 265 #define RK3228_GMAC_SPEED_100M          GRF_BIT(2)
 266 #define RK3228_GMAC_RMII_CLK_25M        GRF_BIT(7)
 267 #define RK3228_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(7)
 268 #define RK3228_GMAC_CLK_125M            (GRF_CLR_BIT(8) | GRF_CLR_BIT(9))
 269 #define RK3228_GMAC_CLK_25M             (GRF_BIT(8) | GRF_BIT(9))
 270 #define RK3228_GMAC_CLK_2_5M            (GRF_CLR_BIT(8) | GRF_BIT(9))
 271 #define RK3228_GMAC_RMII_MODE           GRF_BIT(10)
 272 #define RK3228_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(10)
 273 #define RK3228_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(0)
 274 #define RK3228_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(0)
 275 #define RK3228_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(1)
 276 #define RK3228_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(1)
 277
 278 /* RK3228_GRF_COM_MUX */
 279 #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY  GRF_BIT(15)
 280
 281 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
 282                                 int tx_delay, int rx_delay)
 283 {
 284         struct device *dev = &bsp_priv->pdev->dev;
 285
 286         if (IS_ERR(bsp_priv->grf)) {
 287                 dev_err(dev, "Missing rockchip,grf property\n");
 288                 return;
 289         }
 290
 291         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 292                      RK3228_GMAC_PHY_INTF_SEL_RGMII |
 293                      RK3228_GMAC_RMII_MODE_CLR |
 294                      DELAY_ENABLE(RK3228, tx_delay, rx_delay));
 295
 296         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
 297                      RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) |
 298                      RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
 299 }
 300
 301 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
 302 {
 303         struct device *dev = &bsp_priv->pdev->dev;
 304
 305         if (IS_ERR(bsp_priv->grf)) {
 306                 dev_err(dev, "Missing rockchip,grf property\n");
 307                 return;
 308         }
 309
 310         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 311                      RK3228_GMAC_PHY_INTF_SEL_RMII |
 312                      RK3228_GMAC_RMII_MODE);
 313
 314         /* set MAC to RMII mode */
 315         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
 316 }
 317
 318 static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 319 {
 320         struct device *dev = &bsp_priv->pdev->dev;
 321
 322         if (IS_ERR(bsp_priv->grf)) {
 323                 dev_err(dev, "Missing rockchip,grf property\n");
 324                 return;
 325         }
 326
 327         if (speed == 10)
 328                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 329                              RK3228_GMAC_CLK_2_5M);
 330         else if (speed == 100)
 331                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 332                              RK3228_GMAC_CLK_25M);
 333         else if (speed == 1000)
 334                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 335                              RK3228_GMAC_CLK_125M);
 336         else
 337                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 338 }
 339
 340 static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 341 {
 342         struct device *dev = &bsp_priv->pdev->dev;
 343
 344         if (IS_ERR(bsp_priv->grf)) {
 345                 dev_err(dev, "Missing rockchip,grf property\n");
 346                 return;
 347         }
 348
 349         if (speed == 10)
 350                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 351                              RK3228_GMAC_RMII_CLK_2_5M |
 352                              RK3228_GMAC_SPEED_10M);
 353         else if (speed == 100)
 354                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 355                              RK3228_GMAC_RMII_CLK_25M |
 356                              RK3228_GMAC_SPEED_100M);
 357         else
 358                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 359 }
 360
 361 static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
 362 {
 363         regmap_write(priv->grf, RK3228_GRF_CON_MUX,
 364                      RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
 365 }
 366
 367 static const struct rk_gmac_ops rk3228_ops = {
 368         .set_to_rgmii = rk3228_set_to_rgmii,
 369         .set_to_rmii = rk3228_set_to_rmii,
 370         .set_rgmii_speed = rk3228_set_rgmii_speed,
 371         .set_rmii_speed = rk3228_set_rmii_speed,
 372         .integrated_phy_powerup =  rk3228_integrated_phy_powerup,
 373 };
 374
 375 #define RK3288_GRF_SOC_CON1     0x0248
 376 #define RK3288_GRF_SOC_CON3     0x0250
 377
 378 /*RK3288_GRF_SOC_CON1*/
 379 #define RK3288_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(6) | GRF_CLR_BIT(7) | \
 380                                          GRF_CLR_BIT(8))
 381 #define RK3288_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \
 382                                          GRF_BIT(8))
 383 #define RK3288_GMAC_FLOW_CTRL           GRF_BIT(9)
 384 #define RK3288_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(9)
 385 #define RK3288_GMAC_SPEED_10M           GRF_CLR_BIT(10)
 386 #define RK3288_GMAC_SPEED_100M          GRF_BIT(10)
 387 #define RK3288_GMAC_RMII_CLK_25M        GRF_BIT(11)
 388 #define RK3288_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(11)
 389 #define RK3288_GMAC_CLK_125M            (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
 390 #define RK3288_GMAC_CLK_25M             (GRF_BIT(12) | GRF_BIT(13))
 391 #define RK3288_GMAC_CLK_2_5M            (GRF_CLR_BIT(12) | GRF_BIT(13))
 392 #define RK3288_GMAC_RMII_MODE           GRF_BIT(14)
 393 #define RK3288_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(14)
 394
 395 /*RK3288_GRF_SOC_CON3*/
 396 #define RK3288_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(14)
 397 #define RK3288_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(14)
 398 #define RK3288_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 399 #define RK3288_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 400 #define RK3288_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
 401 #define RK3288_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 402
 403 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
 404                                 int tx_delay, int rx_delay)
 405 {
 406         struct device *dev = &bsp_priv->pdev->dev;
 407
 408         if (IS_ERR(bsp_priv->grf)) {
 409                 dev_err(dev, "Missing rockchip,grf property\n");
 410                 return;
 411         }
 412
 413         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 414                      RK3288_GMAC_PHY_INTF_SEL_RGMII |
 415                      RK3288_GMAC_RMII_MODE_CLR);
 416         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
 417                      DELAY_ENABLE(RK3288, tx_delay, rx_delay) |
 418                      RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
 419                      RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
 420 }
 421
 422 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
 423 {
 424         struct device *dev = &bsp_priv->pdev->dev;
 425
 426         if (IS_ERR(bsp_priv->grf)) {
 427                 dev_err(dev, "Missing rockchip,grf property\n");
 428                 return;
 429         }
 430
 431         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 432                      RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE);
 433 }
 434
 435 static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 436 {
 437         struct device *dev = &bsp_priv->pdev->dev;
 438
 439         if (IS_ERR(bsp_priv->grf)) {
 440                 dev_err(dev, "Missing rockchip,grf property\n");
 441                 return;
 442         }
 443
 444         if (speed == 10)
 445                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 446                              RK3288_GMAC_CLK_2_5M);
 447         else if (speed == 100)
 448                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 449                              RK3288_GMAC_CLK_25M);
 450         else if (speed == 1000)
 451                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 452                              RK3288_GMAC_CLK_125M);
 453         else
 454                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 455 }
 456
 457 static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 458 {
 459         struct device *dev = &bsp_priv->pdev->dev;
 460
 461         if (IS_ERR(bsp_priv->grf)) {
 462                 dev_err(dev, "Missing rockchip,grf property\n");
 463                 return;
 464         }
 465
 466         if (speed == 10) {
 467                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 468                              RK3288_GMAC_RMII_CLK_2_5M |
 469                              RK3288_GMAC_SPEED_10M);
 470         } else if (speed == 100) {
 471                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 472                              RK3288_GMAC_RMII_CLK_25M |
 473                              RK3288_GMAC_SPEED_100M);
 474         } else {
 475                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 476         }
 477 }
 478
 479 static const struct rk_gmac_ops rk3288_ops = {
 480         .set_to_rgmii = rk3288_set_to_rgmii,
 481         .set_to_rmii = rk3288_set_to_rmii,
 482         .set_rgmii_speed = rk3288_set_rgmii_speed,
 483         .set_rmii_speed = rk3288_set_rmii_speed,
 484 };
 485
 486 #define RK3308_GRF_MAC_CON0             0x04a0
 487
 488 /* RK3308_GRF_MAC_CON0 */
 489 #define RK3308_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(2) | GRF_CLR_BIT(3) | \
 490                                         GRF_BIT(4))
 491 #define RK3308_GMAC_FLOW_CTRL           GRF_BIT(3)
 492 #define RK3308_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(3)
 493 #define RK3308_GMAC_SPEED_10M           GRF_CLR_BIT(0)
 494 #define RK3308_GMAC_SPEED_100M          GRF_BIT(0)
 495
 496 static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
 497 {
 498         struct device *dev = &bsp_priv->pdev->dev;
 499
 500         if (IS_ERR(bsp_priv->grf)) {
 501                 dev_err(dev, "Missing rockchip,grf property\n");
 502                 return;
 503         }
 504
 505         regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
 506                      RK3308_GMAC_PHY_INTF_SEL_RMII);
 507 }
 508
 509 static void rk3308_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 510 {
 511         struct device *dev = &bsp_priv->pdev->dev;
 512
 513         if (IS_ERR(bsp_priv->grf)) {
 514                 dev_err(dev, "Missing rockchip,grf property\n");
 515                 return;
 516         }
 517
 518         if (speed == 10) {
 519                 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
 520                              RK3308_GMAC_SPEED_10M);
 521         } else if (speed == 100) {
 522                 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
 523                              RK3308_GMAC_SPEED_100M);
 524         } else {
 525                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 526         }
 527 }
 528
 529 static const struct rk_gmac_ops rk3308_ops = {
 530         .set_to_rmii = rk3308_set_to_rmii,
 531         .set_rmii_speed = rk3308_set_rmii_speed,
 532 };
 533
 534 #define RK3328_GRF_MAC_CON0     0x0900
 535 #define RK3328_GRF_MAC_CON1     0x0904
 536 #define RK3328_GRF_MAC_CON2     0x0908
 537 #define RK3328_GRF_MACPHY_CON1  0xb04
 538
 539 /* RK3328_GRF_MAC_CON0 */
 540 #define RK3328_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
 541 #define RK3328_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 542
 543 /* RK3328_GRF_MAC_CON1 */
 544 #define RK3328_GMAC_PHY_INTF_SEL_RGMII  \
 545                 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
 546 #define RK3328_GMAC_PHY_INTF_SEL_RMII   \
 547                 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
 548 #define RK3328_GMAC_FLOW_CTRL           GRF_BIT(3)
 549 #define RK3328_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(3)
 550 #define RK3328_GMAC_SPEED_10M           GRF_CLR_BIT(2)
 551 #define RK3328_GMAC_SPEED_100M          GRF_BIT(2)
 552 #define RK3328_GMAC_RMII_CLK_25M        GRF_BIT(7)
 553 #define RK3328_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(7)
 554 #define RK3328_GMAC_CLK_125M            (GRF_CLR_BIT(11) | GRF_CLR_BIT(12))
 555 #define RK3328_GMAC_CLK_25M             (GRF_BIT(11) | GRF_BIT(12))
 556 #define RK3328_GMAC_CLK_2_5M            (GRF_CLR_BIT(11) | GRF_BIT(12))
 557 #define RK3328_GMAC_RMII_MODE           GRF_BIT(9)
 558 #define RK3328_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(9)
 559 #define RK3328_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(0)
 560 #define RK3328_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(0)
 561 #define RK3328_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(1)
 562 #define RK3328_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(0)
 563
 564 /* RK3328_GRF_MACPHY_CON1 */
 565 #define RK3328_MACPHY_RMII_MODE         GRF_BIT(9)
 566
 567 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
 568                                 int tx_delay, int rx_delay)
 569 {
 570         struct device *dev = &bsp_priv->pdev->dev;
 571
 572         if (IS_ERR(bsp_priv->grf)) {
 573                 dev_err(dev, "Missing rockchip,grf property\n");
 574                 return;
 575         }
 576
 577         regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 578                      RK3328_GMAC_PHY_INTF_SEL_RGMII |
 579                      RK3328_GMAC_RMII_MODE_CLR |
 580                      RK3328_GMAC_RXCLK_DLY_ENABLE |
 581                      RK3328_GMAC_TXCLK_DLY_ENABLE);
 582
 583         regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0,
 584                      RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) |
 585                      RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
 586 }
 587
 588 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
 589 {
 590         struct device *dev = &bsp_priv->pdev->dev;
 591         unsigned int reg;
 592
 593         if (IS_ERR(bsp_priv->grf)) {
 594                 dev_err(dev, "Missing rockchip,grf property\n");
 595                 return;
 596         }
 597
 598         reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
 599                   RK3328_GRF_MAC_CON1;
 600
 601         regmap_write(bsp_priv->grf, reg,
 602                      RK3328_GMAC_PHY_INTF_SEL_RMII |
 603                      RK3328_GMAC_RMII_MODE);
 604 }
 605
 606 static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 607 {
 608         struct device *dev = &bsp_priv->pdev->dev;
 609
 610         if (IS_ERR(bsp_priv->grf)) {
 611                 dev_err(dev, "Missing rockchip,grf property\n");
 612                 return;
 613         }
 614
 615         if (speed == 10)
 616                 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 617                              RK3328_GMAC_CLK_2_5M);
 618         else if (speed == 100)
 619                 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 620                              RK3328_GMAC_CLK_25M);
 621         else if (speed == 1000)
 622                 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 623                              RK3328_GMAC_CLK_125M);
 624         else
 625                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 626 }
 627
 628 static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 629 {
 630         struct device *dev = &bsp_priv->pdev->dev;
 631         unsigned int reg;
 632
 633         if (IS_ERR(bsp_priv->grf)) {
 634                 dev_err(dev, "Missing rockchip,grf property\n");
 635                 return;
 636         }
 637
 638         reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
 639                   RK3328_GRF_MAC_CON1;
 640
 641         if (speed == 10)
 642                 regmap_write(bsp_priv->grf, reg,
 643                              RK3328_GMAC_RMII_CLK_2_5M |
 644                              RK3328_GMAC_SPEED_10M);
 645         else if (speed == 100)
 646                 regmap_write(bsp_priv->grf, reg,
 647                              RK3328_GMAC_RMII_CLK_25M |
 648                              RK3328_GMAC_SPEED_100M);
 649         else
 650                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 651 }
 652
 653 static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
 654 {
 655         regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
 656                      RK3328_MACPHY_RMII_MODE);
 657 }
 658
 659 static const struct rk_gmac_ops rk3328_ops = {
 660         .set_to_rgmii = rk3328_set_to_rgmii,
 661         .set_to_rmii = rk3328_set_to_rmii,
 662         .set_rgmii_speed = rk3328_set_rgmii_speed,
 663         .set_rmii_speed = rk3328_set_rmii_speed,
 664         .integrated_phy_powerup =  rk3328_integrated_phy_powerup,
 665 };
 666
 667 #define RK3366_GRF_SOC_CON6     0x0418
 668 #define RK3366_GRF_SOC_CON7     0x041c
 669
 670 /* RK3366_GRF_SOC_CON6 */
 671 #define RK3366_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
 672                                          GRF_CLR_BIT(11))
 673 #define RK3366_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
 674                                          GRF_BIT(11))
 675 #define RK3366_GMAC_FLOW_CTRL           GRF_BIT(8)
 676 #define RK3366_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(8)
 677 #define RK3366_GMAC_SPEED_10M           GRF_CLR_BIT(7)
 678 #define RK3366_GMAC_SPEED_100M          GRF_BIT(7)
 679 #define RK3366_GMAC_RMII_CLK_25M        GRF_BIT(3)
 680 #define RK3366_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(3)
 681 #define RK3366_GMAC_CLK_125M            (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
 682 #define RK3366_GMAC_CLK_25M             (GRF_BIT(4) | GRF_BIT(5))
 683 #define RK3366_GMAC_CLK_2_5M            (GRF_CLR_BIT(4) | GRF_BIT(5))
 684 #define RK3366_GMAC_RMII_MODE           GRF_BIT(6)
 685 #define RK3366_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(6)
 686
 687 /* RK3366_GRF_SOC_CON7 */
 688 #define RK3366_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
 689 #define RK3366_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
 690 #define RK3366_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 691 #define RK3366_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 692 #define RK3366_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
 693 #define RK3366_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 694
 695 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
 696                                 int tx_delay, int rx_delay)
 697 {
 698         struct device *dev = &bsp_priv->pdev->dev;
 699
 700         if (IS_ERR(bsp_priv->grf)) {
 701                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 702                 return;
 703         }
 704
 705         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 706                      RK3366_GMAC_PHY_INTF_SEL_RGMII |
 707                      RK3366_GMAC_RMII_MODE_CLR);
 708         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
 709                      DELAY_ENABLE(RK3366, tx_delay, rx_delay) |
 710                      RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
 711                      RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
 712 }
 713
 714 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
 715 {
 716         struct device *dev = &bsp_priv->pdev->dev;
 717
 718         if (IS_ERR(bsp_priv->grf)) {
 719                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 720                 return;
 721         }
 722
 723         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 724                      RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE);
 725 }
 726
 727 static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 728 {
 729         struct device *dev = &bsp_priv->pdev->dev;
 730
 731         if (IS_ERR(bsp_priv->grf)) {
 732                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 733                 return;
 734         }
 735
 736         if (speed == 10)
 737                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 738                              RK3366_GMAC_CLK_2_5M);
 739         else if (speed == 100)
 740                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 741                              RK3366_GMAC_CLK_25M);
 742         else if (speed == 1000)
 743                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 744                              RK3366_GMAC_CLK_125M);
 745         else
 746                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 747 }
 748
 749 static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 750 {
 751         struct device *dev = &bsp_priv->pdev->dev;
 752
 753         if (IS_ERR(bsp_priv->grf)) {
 754                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 755                 return;
 756         }
 757
 758         if (speed == 10) {
 759                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 760                              RK3366_GMAC_RMII_CLK_2_5M |
 761                              RK3366_GMAC_SPEED_10M);
 762         } else if (speed == 100) {
 763                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 764                              RK3366_GMAC_RMII_CLK_25M |
 765                              RK3366_GMAC_SPEED_100M);
 766         } else {
 767                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 768         }
 769 }
 770
 771 static const struct rk_gmac_ops rk3366_ops = {
 772         .set_to_rgmii = rk3366_set_to_rgmii,
 773         .set_to_rmii = rk3366_set_to_rmii,
 774         .set_rgmii_speed = rk3366_set_rgmii_speed,
 775         .set_rmii_speed = rk3366_set_rmii_speed,
 776 };
 777
 778 #define RK3368_GRF_SOC_CON15    0x043c
 779 #define RK3368_GRF_SOC_CON16    0x0440
 780
 781 /* RK3368_GRF_SOC_CON15 */
 782 #define RK3368_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
 783                                          GRF_CLR_BIT(11))
 784 #define RK3368_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
 785                                          GRF_BIT(11))
 786 #define RK3368_GMAC_FLOW_CTRL           GRF_BIT(8)
 787 #define RK3368_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(8)
 788 #define RK3368_GMAC_SPEED_10M           GRF_CLR_BIT(7)
 789 #define RK3368_GMAC_SPEED_100M          GRF_BIT(7)
 790 #define RK3368_GMAC_RMII_CLK_25M        GRF_BIT(3)
 791 #define RK3368_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(3)
 792 #define RK3368_GMAC_CLK_125M            (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
 793 #define RK3368_GMAC_CLK_25M             (GRF_BIT(4) | GRF_BIT(5))
 794 #define RK3368_GMAC_CLK_2_5M            (GRF_CLR_BIT(4) | GRF_BIT(5))
 795 #define RK3368_GMAC_RMII_MODE           GRF_BIT(6)
 796 #define RK3368_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(6)
 797
 798 /* RK3368_GRF_SOC_CON16 */
 799 #define RK3368_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
 800 #define RK3368_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
 801 #define RK3368_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 802 #define RK3368_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 803 #define RK3368_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
 804 #define RK3368_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 805
 806 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
 807                                 int tx_delay, int rx_delay)
 808 {
 809         struct device *dev = &bsp_priv->pdev->dev;
 810
 811         if (IS_ERR(bsp_priv->grf)) {
 812                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 813                 return;
 814         }
 815
 816         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 817                      RK3368_GMAC_PHY_INTF_SEL_RGMII |
 818                      RK3368_GMAC_RMII_MODE_CLR);
 819         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
 820                      DELAY_ENABLE(RK3368, tx_delay, rx_delay) |
 821                      RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
 822                      RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
 823 }
 824
 825 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
 826 {
 827         struct device *dev = &bsp_priv->pdev->dev;
 828
 829         if (IS_ERR(bsp_priv->grf)) {
 830                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 831                 return;
 832         }
 833
 834         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 835                      RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE);
 836 }
 837
 838 static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 839 {
 840         struct device *dev = &bsp_priv->pdev->dev;
 841
 842         if (IS_ERR(bsp_priv->grf)) {
 843                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 844                 return;
 845         }
 846
 847         if (speed == 10)
 848                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 849                              RK3368_GMAC_CLK_2_5M);
 850         else if (speed == 100)
 851                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 852                              RK3368_GMAC_CLK_25M);
 853         else if (speed == 1000)
 854                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 855                              RK3368_GMAC_CLK_125M);
 856         else
 857                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 858 }
 859
 860 static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 861 {
 862         struct device *dev = &bsp_priv->pdev->dev;
 863
 864         if (IS_ERR(bsp_priv->grf)) {
 865                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 866                 return;
 867         }
 868
 869         if (speed == 10) {
 870                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 871                              RK3368_GMAC_RMII_CLK_2_5M |
 872                              RK3368_GMAC_SPEED_10M);
 873         } else if (speed == 100) {
 874                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 875                              RK3368_GMAC_RMII_CLK_25M |
 876                              RK3368_GMAC_SPEED_100M);
 877         } else {
 878                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 879         }
 880 }
 881
 882 static const struct rk_gmac_ops rk3368_ops = {
 883         .set_to_rgmii = rk3368_set_to_rgmii,
 884         .set_to_rmii = rk3368_set_to_rmii,
 885         .set_rgmii_speed = rk3368_set_rgmii_speed,
 886         .set_rmii_speed = rk3368_set_rmii_speed,
 887 };
 888
 889 #define RK3399_GRF_SOC_CON5     0xc214
 890 #define RK3399_GRF_SOC_CON6     0xc218
 891
 892 /* RK3399_GRF_SOC_CON5 */
 893 #define RK3399_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
 894                                          GRF_CLR_BIT(11))
 895 #define RK3399_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
 896                                          GRF_BIT(11))
 897 #define RK3399_GMAC_FLOW_CTRL           GRF_BIT(8)
 898 #define RK3399_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(8)
 899 #define RK3399_GMAC_SPEED_10M           GRF_CLR_BIT(7)
 900 #define RK3399_GMAC_SPEED_100M          GRF_BIT(7)
 901 #define RK3399_GMAC_RMII_CLK_25M        GRF_BIT(3)
 902 #define RK3399_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(3)
 903 #define RK3399_GMAC_CLK_125M            (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
 904 #define RK3399_GMAC_CLK_25M             (GRF_BIT(4) | GRF_BIT(5))
 905 #define RK3399_GMAC_CLK_2_5M            (GRF_CLR_BIT(4) | GRF_BIT(5))
 906 #define RK3399_GMAC_RMII_MODE           GRF_BIT(6)
 907 #define RK3399_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(6)
 908
 909 /* RK3399_GRF_SOC_CON6 */
 910 #define RK3399_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
 911 #define RK3399_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
 912 #define RK3399_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 913 #define RK3399_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 914 #define RK3399_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
 915 #define RK3399_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 916
 917 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
 918                                 int tx_delay, int rx_delay)
 919 {
 920         struct device *dev = &bsp_priv->pdev->dev;
 921
 922         if (IS_ERR(bsp_priv->grf)) {
 923                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 924                 return;
 925         }
 926
 927         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 928                      RK3399_GMAC_PHY_INTF_SEL_RGMII |
 929                      RK3399_GMAC_RMII_MODE_CLR);
 930         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
 931                      DELAY_ENABLE(RK3399, tx_delay, rx_delay) |
 932                      RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |
 933                      RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
 934 }
 935
 936 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
 937 {
 938         struct device *dev = &bsp_priv->pdev->dev;
 939
 940         if (IS_ERR(bsp_priv->grf)) {
 941                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 942                 return;
 943         }
 944
 945         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 946                      RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE);
 947 }
 948
 949 static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 950 {
 951         struct device *dev = &bsp_priv->pdev->dev;
 952
 953         if (IS_ERR(bsp_priv->grf)) {
 954                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 955                 return;
 956         }
 957
 958         if (speed == 10)
 959                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 960                              RK3399_GMAC_CLK_2_5M);
 961         else if (speed == 100)
 962                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 963                              RK3399_GMAC_CLK_25M);
 964         else if (speed == 1000)
 965                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 966                              RK3399_GMAC_CLK_125M);
 967         else
 968                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 969 }
 970
 971 static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 972 {
 973         struct device *dev = &bsp_priv->pdev->dev;
 974
 975         if (IS_ERR(bsp_priv->grf)) {
 976                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 977                 return;
 978         }
 979
 980         if (speed == 10) {
 981                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 982                              RK3399_GMAC_RMII_CLK_2_5M |
 983                              RK3399_GMAC_SPEED_10M);
 984         } else if (speed == 100) {
 985                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 986                              RK3399_GMAC_RMII_CLK_25M |
 987                              RK3399_GMAC_SPEED_100M);
 988         } else {
 989                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 990         }
 991 }
 992
 993 static const struct rk_gmac_ops rk3399_ops = {
 994         .set_to_rgmii = rk3399_set_to_rgmii,
 995         .set_to_rmii = rk3399_set_to_rmii,
 996         .set_rgmii_speed = rk3399_set_rgmii_speed,
 997         .set_rmii_speed = rk3399_set_rmii_speed,
 998 };
 999
1000 #define RK3568_GRF_GMAC0_CON0           0x0380
1001 #define RK3568_GRF_GMAC0_CON1           0x0384
1002 #define RK3568_GRF_GMAC1_CON0           0x0388
1003 #define RK3568_GRF_GMAC1_CON1           0x038c
1004
1005 /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
1006 #define RK3568_GMAC_PHY_INTF_SEL_RGMII  \
1007                 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
1008 #define RK3568_GMAC_PHY_INTF_SEL_RMII   \
1009                 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
1010 #define RK3568_GMAC_FLOW_CTRL                   GRF_BIT(3)
1011 #define RK3568_GMAC_FLOW_CTRL_CLR               GRF_CLR_BIT(3)
1012 #define RK3568_GMAC_RXCLK_DLY_ENABLE            GRF_BIT(1)
1013 #define RK3568_GMAC_RXCLK_DLY_DISABLE           GRF_CLR_BIT(1)
1014 #define RK3568_GMAC_TXCLK_DLY_ENABLE            GRF_BIT(0)
1015 #define RK3568_GMAC_TXCLK_DLY_DISABLE           GRF_CLR_BIT(0)
1016
1017 /* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */
1018 #define RK3568_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
1019 #define RK3568_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
1020
1021 static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv,
1022                                 int tx_delay, int rx_delay)
1023 {
1024         struct device *dev = &bsp_priv->pdev->dev;
1025         u32 con0, con1;
1026
1027         if (IS_ERR(bsp_priv->grf)) {
1028                 dev_err(dev, "Missing rockchip,grf property\n");
1029                 return;
1030         }
1031
1032         con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 :
1033                                      RK3568_GRF_GMAC0_CON0;
1034         con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
1035                                      RK3568_GRF_GMAC0_CON1;
1036
1037         regmap_write(bsp_priv->grf, con0,
1038                      RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) |
1039                      RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
1040
1041         regmap_write(bsp_priv->grf, con1,
1042                      RK3568_GMAC_PHY_INTF_SEL_RGMII |
1043                      RK3568_GMAC_RXCLK_DLY_ENABLE |
1044                      RK3568_GMAC_TXCLK_DLY_ENABLE);
1045 }
1046
1047 static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv)
1048 {
1049         struct device *dev = &bsp_priv->pdev->dev;
1050         u32 con1;
1051
1052         if (IS_ERR(bsp_priv->grf)) {
1053                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1054                 return;
1055         }
1056
1057         con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
1058                                      RK3568_GRF_GMAC0_CON1;
1059         regmap_write(bsp_priv->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII);
1060 }
1061
1062 static void rk3568_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
1063 {
1064         struct device *dev = &bsp_priv->pdev->dev;
1065         unsigned long rate;
1066         int ret;
1067
1068         switch (speed) {
1069         case 10:
1070                 rate = 2500000;
1071                 break;
1072         case 100:
1073                 rate = 25000000;
1074                 break;
1075         case 1000:
1076                 rate = 125000000;
1077                 break;
1078         default:
1079                 dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1080                 return;
1081         }
1082
1083         ret = clk_set_rate(bsp_priv->clk_mac_speed, rate);
1084         if (ret)
1085                 dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
1086                         __func__, rate, ret);
1087 }
1088
1089 static const struct rk_gmac_ops rk3568_ops = {
1090         .set_to_rgmii = rk3568_set_to_rgmii,
1091         .set_to_rmii = rk3568_set_to_rmii,
1092         .set_rgmii_speed = rk3568_set_gmac_speed,
1093         .set_rmii_speed = rk3568_set_gmac_speed,
1094         .regs = {
1095                 0xfe2a0000, /* gmac0 */
1096                 0xfe010000, /* gmac1 */
1097                 0x0, /* sentinel */
1098         },
1099 };
1100
1101 #define RV1108_GRF_GMAC_CON0            0X0900
1102
1103 /* RV1108_GRF_GMAC_CON0 */
1104 #define RV1108_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
1105                                         GRF_BIT(6))
1106 #define RV1108_GMAC_FLOW_CTRL           GRF_BIT(3)
1107 #define RV1108_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(3)
1108 #define RV1108_GMAC_SPEED_10M           GRF_CLR_BIT(2)
1109 #define RV1108_GMAC_SPEED_100M          GRF_BIT(2)
1110 #define RV1108_GMAC_RMII_CLK_25M        GRF_BIT(7)
1111 #define RV1108_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(7)
1112
1113 static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
1114 {
1115         struct device *dev = &bsp_priv->pdev->dev;
1116
1117         if (IS_ERR(bsp_priv->grf)) {
1118                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1119                 return;
1120         }
1121
1122         regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
1123                      RV1108_GMAC_PHY_INTF_SEL_RMII);
1124 }
1125
1126 static void rv1108_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
1127 {
1128         struct device *dev = &bsp_priv->pdev->dev;
1129
1130         if (IS_ERR(bsp_priv->grf)) {
1131                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1132                 return;
1133         }
1134
1135         if (speed == 10) {
1136                 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
1137                              RV1108_GMAC_RMII_CLK_2_5M |
1138                              RV1108_GMAC_SPEED_10M);
1139         } else if (speed == 100) {
1140                 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
1141                              RV1108_GMAC_RMII_CLK_25M |
1142                              RV1108_GMAC_SPEED_100M);
1143         } else {
1144                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
1145         }
1146 }
1147
1148 static const struct rk_gmac_ops rv1108_ops = {
1149         .set_to_rmii = rv1108_set_to_rmii,
1150         .set_rmii_speed = rv1108_set_rmii_speed,
1151 };
1152
1153 #define RK_GRF_MACPHY_CON0              0xb00
1154 #define RK_GRF_MACPHY_CON1              0xb04
1155 #define RK_GRF_MACPHY_CON2              0xb08
1156 #define RK_GRF_MACPHY_CON3              0xb0c
1157
1158 #define RK_MACPHY_ENABLE                GRF_BIT(0)
1159 #define RK_MACPHY_DISABLE               GRF_CLR_BIT(0)
1160 #define RK_MACPHY_CFG_CLK_50M           GRF_BIT(14)
1161 #define RK_GMAC2PHY_RMII_MODE           (GRF_BIT(6) | GRF_CLR_BIT(7))
1162 #define RK_GRF_CON2_MACPHY_ID           HIWORD_UPDATE(0x1234, 0xffff, 0)
1163 #define RK_GRF_CON3_MACPHY_ID           HIWORD_UPDATE(0x35, 0x3f, 0)
1164
1165 static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)
1166 {
1167         if (priv->ops->integrated_phy_powerup)
1168                 priv->ops->integrated_phy_powerup(priv);
1169
1170         regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
1171         regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
1172
1173         regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
1174         regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
1175
1176         if (priv->phy_reset) {
1177                 /* PHY needs to be disabled before trying to reset it */
1178                 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1179                 if (priv->phy_reset)
1180                         reset_control_assert(priv->phy_reset);
1181                 usleep_range(10, 20);
1182                 if (priv->phy_reset)
1183                         reset_control_deassert(priv->phy_reset);
1184                 usleep_range(10, 20);
1185                 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
1186                 msleep(30);
1187         }
1188 }
1189
1190 static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)
1191 {
1192         regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1193         if (priv->phy_reset)
1194                 reset_control_assert(priv->phy_reset);
1195 }
1196
1197 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
1198 {
1199         struct rk_priv_data *bsp_priv = plat->bsp_priv;
1200         struct device *dev = &bsp_priv->pdev->dev;
1201         int ret;
1202
1203         bsp_priv->clk_enabled = false;
1204
1205         bsp_priv->mac_clk_rx = devm_clk_get(dev, "mac_clk_rx");
1206         if (IS_ERR(bsp_priv->mac_clk_rx))
1207                 dev_err(dev, "cannot get clock %s\n",
1208                         "mac_clk_rx");
1209
1210         bsp_priv->mac_clk_tx = devm_clk_get(dev, "mac_clk_tx");
1211         if (IS_ERR(bsp_priv->mac_clk_tx))
1212                 dev_err(dev, "cannot get clock %s\n",
1213                         "mac_clk_tx");
1214
1215         bsp_priv->aclk_mac = devm_clk_get(dev, "aclk_mac");
1216         if (IS_ERR(bsp_priv->aclk_mac))
1217                 dev_err(dev, "cannot get clock %s\n",
1218                         "aclk_mac");
1219
1220         bsp_priv->pclk_mac = devm_clk_get(dev, "pclk_mac");
1221         if (IS_ERR(bsp_priv->pclk_mac))
1222                 dev_err(dev, "cannot get clock %s\n",
1223                         "pclk_mac");
1224
1225         bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth");
1226         if (IS_ERR(bsp_priv->clk_mac))
1227                 dev_err(dev, "cannot get clock %s\n",
1228                         "stmmaceth");
1229
1230         if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
1231                 bsp_priv->clk_mac_ref = devm_clk_get(dev, "clk_mac_ref");
1232                 if (IS_ERR(bsp_priv->clk_mac_ref))
1233                         dev_err(dev, "cannot get clock %s\n",
1234                                 "clk_mac_ref");
1235
1236                 if (!bsp_priv->clock_input) {
1237                         bsp_priv->clk_mac_refout =
1238                                 devm_clk_get(dev, "clk_mac_refout");
1239                         if (IS_ERR(bsp_priv->clk_mac_refout))
1240                                 dev_err(dev, "cannot get clock %s\n",
1241                                         "clk_mac_refout");
1242                 }
1243         }
1244
1245         bsp_priv->clk_mac_speed = devm_clk_get(dev, "clk_mac_speed");
1246         if (IS_ERR(bsp_priv->clk_mac_speed))
1247                 dev_err(dev, "cannot get clock %s\n", "clk_mac_speed");
1248
1249         if (bsp_priv->clock_input) {
1250                 dev_info(dev, "clock input from PHY\n");
1251         } else {
1252                 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1253                         clk_set_rate(bsp_priv->clk_mac, 50000000);
1254         }
1255
1256         if (plat->phy_node && bsp_priv->integrated_phy) {
1257                 bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0);
1258                 if (IS_ERR(bsp_priv->clk_phy)) {
1259                         ret = PTR_ERR(bsp_priv->clk_phy);
1260                         dev_err(dev, "Cannot get PHY clock: %d\n", ret);
1261                         return -EINVAL;
1262                 }
1263                 clk_set_rate(bsp_priv->clk_phy, 50000000);
1264         }
1265
1266         return 0;
1267 }
1268
1269 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
1270 {
1271         int phy_iface = bsp_priv->phy_iface;
1272
1273         if (enable) {
1274                 if (!bsp_priv->clk_enabled) {
1275                         if (phy_iface == PHY_INTERFACE_MODE_RMII) {
1276                                 if (!IS_ERR(bsp_priv->mac_clk_rx))
1277                                         clk_prepare_enable(
1278                                                 bsp_priv->mac_clk_rx);
1279
1280                                 if (!IS_ERR(bsp_priv->clk_mac_ref))
1281                                         clk_prepare_enable(
1282                                                 bsp_priv->clk_mac_ref);
1283
1284                                 if (!IS_ERR(bsp_priv->clk_mac_refout))
1285                                         clk_prepare_enable(
1286                                                 bsp_priv->clk_mac_refout);
1287                         }
1288
1289                         if (!IS_ERR(bsp_priv->clk_phy))
1290                                 clk_prepare_enable(bsp_priv->clk_phy);
1291
1292                         if (!IS_ERR(bsp_priv->aclk_mac))
1293                                 clk_prepare_enable(bsp_priv->aclk_mac);
1294
1295                         if (!IS_ERR(bsp_priv->pclk_mac))
1296                                 clk_prepare_enable(bsp_priv->pclk_mac);
1297
1298                         if (!IS_ERR(bsp_priv->mac_clk_tx))
1299                                 clk_prepare_enable(bsp_priv->mac_clk_tx);
1300
1301                         if (!IS_ERR(bsp_priv->clk_mac_speed))
1302                                 clk_prepare_enable(bsp_priv->clk_mac_speed);
1303
1304                         /**
1305                          * if (!IS_ERR(bsp_priv->clk_mac))
1306                          *      clk_prepare_enable(bsp_priv->clk_mac);
1307                          */
1308                         mdelay(5);
1309                         bsp_priv->clk_enabled = true;
1310                 }
1311         } else {
1312                 if (bsp_priv->clk_enabled) {
1313                         if (phy_iface == PHY_INTERFACE_MODE_RMII) {
1314                                 clk_disable_unprepare(bsp_priv->mac_clk_rx);
1315
1316                                 clk_disable_unprepare(bsp_priv->clk_mac_ref);
1317
1318                                 clk_disable_unprepare(bsp_priv->clk_mac_refout);
1319                         }
1320
1321                         clk_disable_unprepare(bsp_priv->clk_phy);
1322
1323                         clk_disable_unprepare(bsp_priv->aclk_mac);
1324
1325                         clk_disable_unprepare(bsp_priv->pclk_mac);
1326
1327                         clk_disable_unprepare(bsp_priv->mac_clk_tx);
1328
1329                         clk_disable_unprepare(bsp_priv->clk_mac_speed);
1330                         /**
1331                          * if (!IS_ERR(bsp_priv->clk_mac))
1332                          *      clk_disable_unprepare(bsp_priv->clk_mac);
1333                          */
1334                         bsp_priv->clk_enabled = false;
1335                 }
1336         }
1337
1338         return 0;
1339 }
1340
1341 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
1342 {
1343         struct regulator *ldo = bsp_priv->regulator;
1344         int ret;
1345         struct device *dev = &bsp_priv->pdev->dev;
1346
1347         if (!ldo)
1348                 return 0;
1349
1350         if (enable) {
1351                 ret = regulator_enable(ldo);
1352                 if (ret)
1353                         dev_err(dev, "fail to enable phy-supply\n");
1354         } else {
1355                 ret = regulator_disable(ldo);
1356                 if (ret)
1357                         dev_err(dev, "fail to disable phy-supply\n");
1358         }
1359
1360         return 0;
1361 }
1362
1363 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
1364                                           struct plat_stmmacenet_data *plat,
1365                                           const struct rk_gmac_ops *ops)
1366 {
1367         struct rk_priv_data *bsp_priv;
1368         struct device *dev = &pdev->dev;
1369         struct resource *res;
1370         int ret;
1371         const char *strings = NULL;
1372         int value;
1373
1374         bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
1375         if (!bsp_priv)
1376                 return ERR_PTR(-ENOMEM);
1377
1378         of_get_phy_mode(dev->of_node, &bsp_priv->phy_iface);
1379         bsp_priv->ops = ops;
1380
1381         /* Some SoCs have multiple MAC controllers, which need
1382          * to be distinguished.
1383          */
1384         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1385         if (res) {
1386                 int i = 0;
1387
1388                 while (ops->regs[i]) {
1389                         if (ops->regs[i] == res->start) {
1390                                 bsp_priv->id = i;
1391                                 break;
1392                         }
1393                         i++;
1394                 }
1395         }
1396
1397         bsp_priv->regulator = devm_regulator_get_optional(dev, "phy");
1398         if (IS_ERR(bsp_priv->regulator)) {
1399                 if (PTR_ERR(bsp_priv->regulator) == -EPROBE_DEFER) {
1400                         dev_err(dev, "phy regulator is not available yet, deferred probing\n");
1401                         return ERR_PTR(-EPROBE_DEFER);
1402                 }
1403                 dev_err(dev, "no regulator found\n");
1404                 bsp_priv->regulator = NULL;
1405         }
1406
1407         ret = of_property_read_string(dev->of_node, "clock_in_out", &strings);
1408         if (ret) {
1409                 dev_err(dev, "Can not read property: clock_in_out.\n");
1410                 bsp_priv->clock_input = true;
1411         } else {
1412                 dev_info(dev, "clock input or output? (%s).\n",
1413                          strings);
1414                 if (!strcmp(strings, "input"))
1415                         bsp_priv->clock_input = true;
1416                 else
1417                         bsp_priv->clock_input = false;
1418         }
1419
1420         ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
1421         if (ret) {
1422                 bsp_priv->tx_delay = 0x30;
1423                 dev_err(dev, "Can not read property: tx_delay.");
1424                 dev_err(dev, "set tx_delay to 0x%x\n",
1425                         bsp_priv->tx_delay);
1426         } else {
1427                 dev_info(dev, "TX delay(0x%x).\n", value);
1428                 bsp_priv->tx_delay = value;
1429         }
1430
1431         ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
1432         if (ret) {
1433                 bsp_priv->rx_delay = 0x10;
1434                 dev_err(dev, "Can not read property: rx_delay.");
1435                 dev_err(dev, "set rx_delay to 0x%x\n",
1436                         bsp_priv->rx_delay);
1437         } else {
1438                 dev_info(dev, "RX delay(0x%x).\n", value);
1439                 bsp_priv->rx_delay = value;
1440         }
1441
1442         bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1443                                                         "rockchip,grf");
1444
1445         if (plat->phy_node) {
1446                 bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node,
1447                                                                  "phy-is-integrated");
1448                 if (bsp_priv->integrated_phy) {
1449                         bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL);
1450                         if (IS_ERR(bsp_priv->phy_reset)) {
1451                                 dev_err(&pdev->dev, "No PHY reset control found.\n");
1452                                 bsp_priv->phy_reset = NULL;
1453                         }
1454                 }
1455         }
1456         dev_info(dev, "integrated PHY? (%s).\n",
1457                  bsp_priv->integrated_phy ? "yes" : "no");
1458
1459         bsp_priv->pdev = pdev;
1460
1461         return bsp_priv;
1462 }
1463
1464 static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv)
1465 {
1466         switch (bsp_priv->phy_iface) {
1467         case PHY_INTERFACE_MODE_RGMII:
1468         case PHY_INTERFACE_MODE_RGMII_ID:
1469         case PHY_INTERFACE_MODE_RGMII_RXID:
1470         case PHY_INTERFACE_MODE_RGMII_TXID:
1471                 if (!bsp_priv->ops->set_to_rgmii)
1472                         return -EINVAL;
1473                 break;
1474         case PHY_INTERFACE_MODE_RMII:
1475                 if (!bsp_priv->ops->set_to_rmii)
1476                         return -EINVAL;
1477                 break;
1478         default:
1479                 dev_err(&bsp_priv->pdev->dev,
1480                         "unsupported interface %d", bsp_priv->phy_iface);
1481         }
1482         return 0;
1483 }
1484
1485 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
1486 {
1487         int ret;
1488         struct device *dev = &bsp_priv->pdev->dev;
1489
1490         ret = rk_gmac_check_ops(bsp_priv);
1491         if (ret)
1492                 return ret;
1493
1494         ret = gmac_clk_enable(bsp_priv, true);
1495         if (ret)
1496                 return ret;
1497
1498         /*rmii or rgmii*/
1499         switch (bsp_priv->phy_iface) {
1500         case PHY_INTERFACE_MODE_RGMII:
1501                 dev_info(dev, "init for RGMII\n");
1502                 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay,
1503                                             bsp_priv->rx_delay);
1504                 break;
1505         case PHY_INTERFACE_MODE_RGMII_ID:
1506                 dev_info(dev, "init for RGMII_ID\n");
1507                 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
1508                 break;
1509         case PHY_INTERFACE_MODE_RGMII_RXID:
1510                 dev_info(dev, "init for RGMII_RXID\n");
1511                 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0);
1512                 break;
1513         case PHY_INTERFACE_MODE_RGMII_TXID:
1514                 dev_info(dev, "init for RGMII_TXID\n");
1515                 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay);
1516                 break;
1517         case PHY_INTERFACE_MODE_RMII:
1518                 dev_info(dev, "init for RMII\n");
1519                 bsp_priv->ops->set_to_rmii(bsp_priv);
1520                 break;
1521         default:
1522                 dev_err(dev, "NO interface defined!\n");
1523         }
1524
1525         ret = phy_power_on(bsp_priv, true);
1526         if (ret) {
1527                 gmac_clk_enable(bsp_priv, false);
1528                 return ret;
1529         }
1530
1531         if (bsp_priv->integrated_phy)
1532                 rk_gmac_integrated_phy_powerup(bsp_priv);
1533
1534         return 0;
1535 }
1536
1537 static void rk_gmac_powerdown(struct rk_priv_data *gmac)
1538 {
1539         if (gmac->integrated_phy)
1540                 rk_gmac_integrated_phy_powerdown(gmac);
1541
1542         phy_power_on(gmac, false);
1543         gmac_clk_enable(gmac, false);
1544 }
1545
1546 static void rk_fix_speed(void *priv, unsigned int speed)
1547 {
1548         struct rk_priv_data *bsp_priv = priv;
1549         struct device *dev = &bsp_priv->pdev->dev;
1550
1551         switch (bsp_priv->phy_iface) {
1552         case PHY_INTERFACE_MODE_RGMII:
1553         case PHY_INTERFACE_MODE_RGMII_ID:
1554         case PHY_INTERFACE_MODE_RGMII_RXID:
1555         case PHY_INTERFACE_MODE_RGMII_TXID:
1556                 if (bsp_priv->ops->set_rgmii_speed)
1557                         bsp_priv->ops->set_rgmii_speed(bsp_priv, speed);
1558                 break;
1559         case PHY_INTERFACE_MODE_RMII:
1560                 if (bsp_priv->ops->set_rmii_speed)
1561                         bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
1562                 break;
1563         default:
1564                 dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
1565         }
1566 }
1567
1568 static int rk_gmac_probe(struct platform_device *pdev)
1569 {
1570         struct plat_stmmacenet_data *plat_dat;
1571         struct stmmac_resources stmmac_res;
1572         const struct rk_gmac_ops *data;
1573         int ret;
1574
1575         data = of_device_get_match_data(&pdev->dev);
1576         if (!data) {
1577                 dev_err(&pdev->dev, "no of match data provided\n");
1578                 return -EINVAL;
1579         }
1580
1581         ret = stmmac_get_platform_resources(pdev, &stmmac_res);
1582         if (ret)
1583                 return ret;
1584
1585         plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
1586         if (IS_ERR(plat_dat))
1587                 return PTR_ERR(plat_dat);
1588
1589         /* If the stmmac is not already selected as gmac4,
1590          * then make sure we fallback to gmac.
1591          */
1592         if (!plat_dat->has_gmac4)
1593                 plat_dat->has_gmac = true;
1594         plat_dat->fix_mac_speed = rk_fix_speed;
1595
1596         plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data);
1597         if (IS_ERR(plat_dat->bsp_priv)) {
1598                 ret = PTR_ERR(plat_dat->bsp_priv);
1599                 goto err_remove_config_dt;
1600         }
1601
1602         ret = rk_gmac_clk_init(plat_dat);
1603         if (ret)
1604                 goto err_remove_config_dt;
1605
1606         ret = rk_gmac_powerup(plat_dat->bsp_priv);
1607         if (ret)
1608                 goto err_remove_config_dt;
1609
1610         ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
1611         if (ret)
1612                 goto err_gmac_powerdown;
1613
1614         return 0;
1615
1616 err_gmac_powerdown:
1617         rk_gmac_powerdown(plat_dat->bsp_priv);
1618 err_remove_config_dt:
1619         stmmac_remove_config_dt(pdev, plat_dat);
1620
1621         return ret;
1622 }
1623
1624 static int rk_gmac_remove(struct platform_device *pdev)
1625 {
1626         struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(&pdev->dev);
1627         int ret = stmmac_dvr_remove(&pdev->dev);
1628
1629         rk_gmac_powerdown(bsp_priv);
1630
1631         return ret;
1632 }
1633
1634 #ifdef CONFIG_PM_SLEEP
1635 static int rk_gmac_suspend(struct device *dev)
1636 {
1637         struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
1638         int ret = stmmac_suspend(dev);
1639
1640         /* Keep the PHY up if we use Wake-on-Lan. */
1641         if (!device_may_wakeup(dev)) {
1642                 rk_gmac_powerdown(bsp_priv);
1643                 bsp_priv->suspended = true;
1644         }
1645
1646         return ret;
1647 }
1648
1649 static int rk_gmac_resume(struct device *dev)
1650 {
1651         struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
1652
1653         /* The PHY was up for Wake-on-Lan. */
1654         if (bsp_priv->suspended) {
1655                 rk_gmac_powerup(bsp_priv);
1656                 bsp_priv->suspended = false;
1657         }
1658
1659         return stmmac_resume(dev);
1660 }
1661 #endif /* CONFIG_PM_SLEEP */
1662
1663 static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume);
1664
1665 static const struct of_device_id rk_gmac_dwmac_match[] = {
1666         { .compatible = "rockchip,px30-gmac",   .data = &px30_ops   },
1667         { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
1668         { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
1669         { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
1670         { .compatible = "rockchip,rk3308-gmac", .data = &rk3308_ops },
1671         { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
1672         { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
1673         { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
1674         { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
1675         { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
1676         { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
1677         { }
1678 };
1679 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
1680
1681 static struct platform_driver rk_gmac_dwmac_driver = {
1682         .probe  = rk_gmac_probe,
1683         .remove = rk_gmac_remove,
1684         .driver = {
1685                 .name           = "rk_gmac-dwmac",
1686                 .pm             = &rk_gmac_pm_ops,
1687                 .of_match_table = rk_gmac_dwmac_match,
1688         },
1689 };
1690 module_platform_driver(rk_gmac_dwmac_driver);
1691
1692 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
1693 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");
1694 MODULE_LICENSE("GPL");