1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2020, Intel Corporation
5 #include <linux/clk-provider.h>
10 /* This struct is used to associate PCI Function of MAC controller on a board,
11 * discovered via DMI, with the address of PHY connected to the MAC. The
12 * negative value of the address means that MAC controller is not connected
15 struct stmmac_pci_func_data {
20 struct stmmac_pci_dmi_data {
21 const struct stmmac_pci_func_data *func;
25 struct stmmac_pci_info {
26 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
29 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev,
30 const struct dmi_system_id *dmi_list)
32 const struct stmmac_pci_func_data *func_data;
33 const struct stmmac_pci_dmi_data *dmi_data;
34 const struct dmi_system_id *dmi_id;
35 int func = PCI_FUNC(pdev->devfn);
38 dmi_id = dmi_first_match(dmi_list);
42 dmi_data = dmi_id->driver_data;
43 func_data = dmi_data->func;
45 for (n = 0; n < dmi_data->nfuncs; n++, func_data++)
46 if (func_data->func == func)
47 return func_data->phy_addr;
52 static void common_default_data(struct plat_stmmacenet_data *plat)
54 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
56 plat->force_sf_dma_mode = 1;
58 plat->mdio_bus_data->needs_reset = true;
60 /* Set default value for multicast hash bins */
61 plat->multicast_filter_bins = HASH_TABLE_SIZE;
63 /* Set default value for unicast filter entries */
64 plat->unicast_filter_entries = 1;
66 /* Set the maxmtu to a default of JUMBO_LEN */
67 plat->maxmtu = JUMBO_LEN;
69 /* Set default number of RX and TX queues to use */
70 plat->tx_queues_to_use = 1;
71 plat->rx_queues_to_use = 1;
73 /* Disable Priority config by default */
74 plat->tx_queues_cfg[0].use_prio = false;
75 plat->rx_queues_cfg[0].use_prio = false;
77 /* Disable RX queues routing by default */
78 plat->rx_queues_cfg[0].pkt_route = 0x0;
81 static int intel_mgbe_common_data(struct pci_dev *pdev,
82 struct plat_stmmacenet_data *plat)
89 plat->force_sf_dma_mode = 0;
92 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
94 for (i = 0; i < plat->rx_queues_to_use; i++) {
95 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
96 plat->rx_queues_cfg[i].chan = i;
98 /* Disable Priority config by default */
99 plat->rx_queues_cfg[i].use_prio = false;
101 /* Disable RX queues routing by default */
102 plat->rx_queues_cfg[i].pkt_route = 0x0;
105 for (i = 0; i < plat->tx_queues_to_use; i++) {
106 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
108 /* Disable Priority config by default */
109 plat->tx_queues_cfg[i].use_prio = false;
112 /* FIFO size is 4096 bytes for 1 tx/rx queue */
113 plat->tx_fifo_size = plat->tx_queues_to_use * 4096;
114 plat->rx_fifo_size = plat->rx_queues_to_use * 4096;
116 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR;
117 plat->tx_queues_cfg[0].weight = 0x09;
118 plat->tx_queues_cfg[1].weight = 0x0A;
119 plat->tx_queues_cfg[2].weight = 0x0B;
120 plat->tx_queues_cfg[3].weight = 0x0C;
121 plat->tx_queues_cfg[4].weight = 0x0D;
122 plat->tx_queues_cfg[5].weight = 0x0E;
123 plat->tx_queues_cfg[6].weight = 0x0F;
124 plat->tx_queues_cfg[7].weight = 0x10;
126 plat->dma_cfg->pbl = 32;
127 plat->dma_cfg->pblx8 = true;
128 plat->dma_cfg->fixed_burst = 0;
129 plat->dma_cfg->mixed_burst = 0;
130 plat->dma_cfg->aal = 0;
132 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi),
137 plat->axi->axi_lpi_en = 0;
138 plat->axi->axi_xit_frm = 0;
139 plat->axi->axi_wr_osr_lmt = 1;
140 plat->axi->axi_rd_osr_lmt = 1;
141 plat->axi->axi_blen[0] = 4;
142 plat->axi->axi_blen[1] = 8;
143 plat->axi->axi_blen[2] = 16;
145 plat->ptp_max_adj = plat->clk_ptp_rate;
147 /* Set system clock */
148 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev,
149 "stmmac-clk", NULL, 0,
152 if (IS_ERR(plat->stmmac_clk)) {
153 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n");
154 plat->stmmac_clk = NULL;
156 clk_prepare_enable(plat->stmmac_clk);
158 /* Set default value for multicast hash bins */
159 plat->multicast_filter_bins = HASH_TABLE_SIZE;
161 /* Set default value for unicast filter entries */
162 plat->unicast_filter_entries = 1;
164 /* Set the maxmtu to a default of JUMBO_LEN */
165 plat->maxmtu = JUMBO_LEN;
170 static int ehl_common_data(struct pci_dev *pdev,
171 struct plat_stmmacenet_data *plat)
175 plat->rx_queues_to_use = 8;
176 plat->tx_queues_to_use = 8;
177 plat->clk_ptp_rate = 200000000;
178 ret = intel_mgbe_common_data(pdev, plat);
185 static int ehl_sgmii_data(struct pci_dev *pdev,
186 struct plat_stmmacenet_data *plat)
190 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
192 return ehl_common_data(pdev, plat);
195 static struct stmmac_pci_info ehl_sgmii1g_pci_info = {
196 .setup = ehl_sgmii_data,
199 static int ehl_rgmii_data(struct pci_dev *pdev,
200 struct plat_stmmacenet_data *plat)
204 plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
206 return ehl_common_data(pdev, plat);
209 static struct stmmac_pci_info ehl_rgmii1g_pci_info = {
210 .setup = ehl_rgmii_data,
213 static int ehl_pse0_common_data(struct pci_dev *pdev,
214 struct plat_stmmacenet_data *plat)
218 return ehl_common_data(pdev, plat);
221 static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev,
222 struct plat_stmmacenet_data *plat)
224 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
225 return ehl_pse0_common_data(pdev, plat);
228 static struct stmmac_pci_info ehl_pse0_rgmii1g_pci_info = {
229 .setup = ehl_pse0_rgmii1g_data,
232 static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev,
233 struct plat_stmmacenet_data *plat)
235 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
236 return ehl_pse0_common_data(pdev, plat);
239 static struct stmmac_pci_info ehl_pse0_sgmii1g_pci_info = {
240 .setup = ehl_pse0_sgmii1g_data,
243 static int ehl_pse1_common_data(struct pci_dev *pdev,
244 struct plat_stmmacenet_data *plat)
248 return ehl_common_data(pdev, plat);
251 static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev,
252 struct plat_stmmacenet_data *plat)
254 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
255 return ehl_pse1_common_data(pdev, plat);
258 static struct stmmac_pci_info ehl_pse1_rgmii1g_pci_info = {
259 .setup = ehl_pse1_rgmii1g_data,
262 static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev,
263 struct plat_stmmacenet_data *plat)
265 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
266 return ehl_pse1_common_data(pdev, plat);
269 static struct stmmac_pci_info ehl_pse1_sgmii1g_pci_info = {
270 .setup = ehl_pse1_sgmii1g_data,
273 static int tgl_common_data(struct pci_dev *pdev,
274 struct plat_stmmacenet_data *plat)
278 plat->rx_queues_to_use = 6;
279 plat->tx_queues_to_use = 4;
280 plat->clk_ptp_rate = 200000000;
281 ret = intel_mgbe_common_data(pdev, plat);
288 static int tgl_sgmii_data(struct pci_dev *pdev,
289 struct plat_stmmacenet_data *plat)
293 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
294 return tgl_common_data(pdev, plat);
297 static struct stmmac_pci_info tgl_sgmii1g_pci_info = {
298 .setup = tgl_sgmii_data,
301 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = {
308 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = {
309 .func = galileo_stmmac_func_data,
310 .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data),
313 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = {
324 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = {
325 .func = iot2040_stmmac_func_data,
326 .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data),
329 static const struct dmi_system_id quark_pci_dmi[] = {
332 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
334 .driver_data = (void *)&galileo_stmmac_dmi_data,
338 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
340 .driver_data = (void *)&galileo_stmmac_dmi_data,
342 /* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040.
343 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which
344 * has only one pci network device while other asset tags are
345 * for IOT2040 which has two.
349 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
350 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG,
351 "6ES7647-0AA00-0YA2"),
353 .driver_data = (void *)&galileo_stmmac_dmi_data,
357 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
359 .driver_data = (void *)&iot2040_stmmac_dmi_data,
364 static int quark_default_data(struct pci_dev *pdev,
365 struct plat_stmmacenet_data *plat)
369 /* Set common default data first */
370 common_default_data(plat);
372 /* Refuse to load the driver and register net device if MAC controller
373 * does not connect to any PHY interface.
375 ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi);
377 /* Return error to the caller on DMI enabled boards. */
378 if (dmi_get_system_info(DMI_BOARD_NAME))
381 /* Galileo boards with old firmware don't support DMI. We always
382 * use 1 here as PHY address, so at least the first found MAC
383 * controller would be probed.
388 plat->bus_id = pci_dev_id(pdev);
389 plat->phy_addr = ret;
390 plat->phy_interface = PHY_INTERFACE_MODE_RMII;
392 plat->dma_cfg->pbl = 16;
393 plat->dma_cfg->pblx8 = true;
394 plat->dma_cfg->fixed_burst = 1;
400 static const struct stmmac_pci_info quark_pci_info = {
401 .setup = quark_default_data,
405 * intel_eth_pci_probe
407 * @pdev: pci device pointer
408 * @id: pointer to table of device id/id's.
410 * Description: This probing function gets called for all PCI devices which
411 * match the ID table and are not "owned" by other driver yet. This function
412 * gets passed a "struct pci_dev *" for each device whose entry in the ID table
413 * matches the device. The probe functions returns zero when the driver choose
414 * to take "ownership" of the device or an error code(-ve no) otherwise.
416 static int intel_eth_pci_probe(struct pci_dev *pdev,
417 const struct pci_device_id *id)
419 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data;
420 struct plat_stmmacenet_data *plat;
421 struct stmmac_resources res;
425 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
429 plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
430 sizeof(*plat->mdio_bus_data),
432 if (!plat->mdio_bus_data)
435 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
440 /* Enable pci device */
441 ret = pci_enable_device(pdev);
443 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n",
448 /* Get the base address of device */
449 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
450 if (pci_resource_len(pdev, i) == 0)
452 ret = pcim_iomap_regions(pdev, BIT(i), pci_name(pdev));
458 pci_set_master(pdev);
460 ret = info->setup(pdev, plat);
464 pci_enable_msi(pdev);
466 memset(&res, 0, sizeof(res));
467 res.addr = pcim_iomap_table(pdev)[i];
468 res.wol_irq = pdev->irq;
471 return stmmac_dvr_probe(&pdev->dev, plat, &res);
475 * intel_eth_pci_remove
477 * @pdev: platform device pointer
478 * Description: this function calls the main to free the net resources
479 * and releases the PCI resources.
481 static void intel_eth_pci_remove(struct pci_dev *pdev)
483 struct net_device *ndev = dev_get_drvdata(&pdev->dev);
484 struct stmmac_priv *priv = netdev_priv(ndev);
487 stmmac_dvr_remove(&pdev->dev);
489 if (priv->plat->stmmac_clk)
490 clk_unregister_fixed_rate(priv->plat->stmmac_clk);
492 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
493 if (pci_resource_len(pdev, i) == 0)
495 pcim_iounmap_regions(pdev, BIT(i));
499 pci_disable_device(pdev);
502 static int __maybe_unused intel_eth_pci_suspend(struct device *dev)
504 struct pci_dev *pdev = to_pci_dev(dev);
507 ret = stmmac_suspend(dev);
511 ret = pci_save_state(pdev);
515 pci_disable_device(pdev);
516 pci_wake_from_d3(pdev, true);
520 static int __maybe_unused intel_eth_pci_resume(struct device *dev)
522 struct pci_dev *pdev = to_pci_dev(dev);
525 pci_restore_state(pdev);
526 pci_set_power_state(pdev, PCI_D0);
528 ret = pci_enable_device(pdev);
532 pci_set_master(pdev);
534 return stmmac_resume(dev);
537 static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend,
538 intel_eth_pci_resume);
540 #define PCI_DEVICE_ID_INTEL_QUARK_ID 0x0937
541 #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G_ID 0x4b30
542 #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G_ID 0x4b31
543 #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5_ID 0x4b32
544 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC
545 * which are named PSE0 and PSE1
547 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G_ID 0x4ba0
548 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G_ID 0x4ba1
549 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5_ID 0x4ba2
550 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G_ID 0x4bb0
551 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G_ID 0x4bb1
552 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5_ID 0x4bb2
553 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID 0xa0ac
555 static const struct pci_device_id intel_eth_pci_id_table[] = {
556 { PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_pci_info) },
557 { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_pci_info) },
558 { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_pci_info) },
559 { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5_ID, &ehl_sgmii1g_pci_info) },
560 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID,
561 &ehl_pse0_rgmii1g_pci_info) },
562 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID,
563 &ehl_pse0_sgmii1g_pci_info) },
564 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5_ID,
565 &ehl_pse0_sgmii1g_pci_info) },
566 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID,
567 &ehl_pse1_rgmii1g_pci_info) },
568 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID,
569 &ehl_pse1_sgmii1g_pci_info) },
570 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5_ID,
571 &ehl_pse1_sgmii1g_pci_info) },
572 { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_pci_info) },
576 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table);
578 static struct pci_driver intel_eth_pci_driver = {
579 .name = "intel-eth-pci",
580 .id_table = intel_eth_pci_id_table,
581 .probe = intel_eth_pci_probe,
582 .remove = intel_eth_pci_remove,
584 .pm = &intel_eth_pm_ops,
588 module_pci_driver(intel_eth_pci_driver);
590 MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver");
591 MODULE_AUTHOR("Voon Weifeng <weifeng.voon@intel.com>");
592 MODULE_LICENSE("GPL v2");