1 // SPDX-License-Identifier: GPL-2.0
2 /* SuperH Ethernet device driver
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
6 * Copyright (C) 2008-2014 Renesas Solutions Corp.
7 * Copyright (C) 2013-2017 Cogent Embedded, Inc.
8 * Copyright (C) 2014 Codethink Limited
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/spinlock.h>
14 #include <linux/interrupt.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/etherdevice.h>
17 #include <linux/delay.h>
18 #include <linux/platform_device.h>
19 #include <linux/mdio-bitbang.h>
20 #include <linux/netdevice.h>
22 #include <linux/of_device.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_net.h>
25 #include <linux/phy.h>
26 #include <linux/cache.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/slab.h>
30 #include <linux/ethtool.h>
31 #include <linux/if_vlan.h>
32 #include <linux/sh_eth.h>
33 #include <linux/of_mdio.h>
37 #define SH_ETH_DEF_MSG_ENABLE \
43 #define SH_ETH_OFFSET_INVALID ((u16)~0)
45 #define SH_ETH_OFFSET_DEFAULTS \
46 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
48 /* use some intentionally tricky logic here to initialize the whole struct to
49 * 0xffff, but then override certain fields, requiring us to indicate that we
50 * "know" that there are overrides in this structure, and we'll need to disable
51 * that warning from W=1 builds. GCC has supported this option since 4.2.X, but
52 * the macros available to do this only define GCC 8.
55 __diag_ignore(GCC, 8, "-Woverride-init",
56 "logic to initialize all and then override some is OK");
57 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
58 SH_ETH_OFFSET_DEFAULTS,
113 [TSU_CTRST] = 0x0004,
114 [TSU_FWEN0] = 0x0010,
115 [TSU_FWEN1] = 0x0014,
117 [TSU_BSYSL0] = 0x0020,
118 [TSU_BSYSL1] = 0x0024,
119 [TSU_PRISL0] = 0x0028,
120 [TSU_PRISL1] = 0x002c,
121 [TSU_FWSL0] = 0x0030,
122 [TSU_FWSL1] = 0x0034,
123 [TSU_FWSLC] = 0x0038,
124 [TSU_QTAGM0] = 0x0040,
125 [TSU_QTAGM1] = 0x0044,
127 [TSU_FWINMK] = 0x0054,
128 [TSU_ADQT0] = 0x0048,
129 [TSU_ADQT1] = 0x004c,
130 [TSU_VTAG0] = 0x0058,
131 [TSU_VTAG1] = 0x005c,
132 [TSU_ADSBSY] = 0x0060,
134 [TSU_POST1] = 0x0070,
135 [TSU_POST2] = 0x0074,
136 [TSU_POST3] = 0x0078,
137 [TSU_POST4] = 0x007c,
138 [TSU_ADRH0] = 0x0100,
154 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
155 SH_ETH_OFFSET_DEFAULTS,
202 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
203 SH_ETH_OFFSET_DEFAULTS,
256 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
257 SH_ETH_OFFSET_DEFAULTS,
305 [TSU_CTRST] = 0x0004,
306 [TSU_FWEN0] = 0x0010,
307 [TSU_FWEN1] = 0x0014,
309 [TSU_BSYSL0] = 0x0020,
310 [TSU_BSYSL1] = 0x0024,
311 [TSU_PRISL0] = 0x0028,
312 [TSU_PRISL1] = 0x002c,
313 [TSU_FWSL0] = 0x0030,
314 [TSU_FWSL1] = 0x0034,
315 [TSU_FWSLC] = 0x0038,
316 [TSU_QTAGM0] = 0x0040,
317 [TSU_QTAGM1] = 0x0044,
318 [TSU_ADQT0] = 0x0048,
319 [TSU_ADQT1] = 0x004c,
321 [TSU_FWINMK] = 0x0054,
322 [TSU_ADSBSY] = 0x0060,
324 [TSU_POST1] = 0x0070,
325 [TSU_POST2] = 0x0074,
326 [TSU_POST3] = 0x0078,
327 [TSU_POST4] = 0x007c,
342 [TSU_ADRH0] = 0x0100,
346 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
347 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
349 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
351 struct sh_eth_private *mdp = netdev_priv(ndev);
352 u16 offset = mdp->reg_offset[enum_index];
354 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
357 iowrite32(data, mdp->addr + offset);
360 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
362 struct sh_eth_private *mdp = netdev_priv(ndev);
363 u16 offset = mdp->reg_offset[enum_index];
365 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
368 return ioread32(mdp->addr + offset);
371 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
374 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
378 static u16 sh_eth_tsu_get_offset(struct sh_eth_private *mdp, int enum_index)
380 return mdp->reg_offset[enum_index];
383 static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data,
386 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index);
388 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
391 iowrite32(data, mdp->tsu_addr + offset);
394 static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
396 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index);
398 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
401 return ioread32(mdp->tsu_addr + offset);
404 static void sh_eth_soft_swap(char *src, int len)
406 #ifdef __LITTLE_ENDIAN
408 u32 *maxp = p + DIV_ROUND_UP(len, sizeof(u32));
410 for (; p < maxp; p++)
415 static void sh_eth_select_mii(struct net_device *ndev)
417 struct sh_eth_private *mdp = netdev_priv(ndev);
420 switch (mdp->phy_interface) {
421 case PHY_INTERFACE_MODE_RGMII ... PHY_INTERFACE_MODE_RGMII_TXID:
424 case PHY_INTERFACE_MODE_GMII:
427 case PHY_INTERFACE_MODE_MII:
430 case PHY_INTERFACE_MODE_RMII:
435 "PHY interface mode was not setup. Set to MII.\n");
440 sh_eth_write(ndev, value, RMII_MII);
443 static void sh_eth_set_duplex(struct net_device *ndev)
445 struct sh_eth_private *mdp = netdev_priv(ndev);
447 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
450 static void sh_eth_chip_reset(struct net_device *ndev)
452 struct sh_eth_private *mdp = netdev_priv(ndev);
455 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
459 static int sh_eth_soft_reset(struct net_device *ndev)
461 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
463 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
468 static int sh_eth_check_soft_reset(struct net_device *ndev)
472 for (cnt = 100; cnt > 0; cnt--) {
473 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
478 netdev_err(ndev, "Device reset failed\n");
482 static int sh_eth_soft_reset_gether(struct net_device *ndev)
484 struct sh_eth_private *mdp = netdev_priv(ndev);
487 sh_eth_write(ndev, EDSR_ENALL, EDSR);
488 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
490 ret = sh_eth_check_soft_reset(ndev);
495 sh_eth_write(ndev, 0, TDLAR);
496 sh_eth_write(ndev, 0, TDFAR);
497 sh_eth_write(ndev, 0, TDFXR);
498 sh_eth_write(ndev, 0, TDFFR);
499 sh_eth_write(ndev, 0, RDLAR);
500 sh_eth_write(ndev, 0, RDFAR);
501 sh_eth_write(ndev, 0, RDFXR);
502 sh_eth_write(ndev, 0, RDFFR);
504 /* Reset HW CRC register */
506 sh_eth_write(ndev, 0, CSMR);
508 /* Select MII mode */
509 if (mdp->cd->select_mii)
510 sh_eth_select_mii(ndev);
515 static void sh_eth_set_rate_gether(struct net_device *ndev)
517 struct sh_eth_private *mdp = netdev_priv(ndev);
519 if (WARN_ON(!mdp->cd->gecmr))
522 switch (mdp->speed) {
523 case 10: /* 10BASE */
524 sh_eth_write(ndev, GECMR_10, GECMR);
526 case 100:/* 100BASE */
527 sh_eth_write(ndev, GECMR_100, GECMR);
529 case 1000: /* 1000BASE */
530 sh_eth_write(ndev, GECMR_1000, GECMR);
537 static struct sh_eth_cpu_data r7s72100_data = {
538 .soft_reset = sh_eth_soft_reset_gether,
540 .chip_reset = sh_eth_chip_reset,
541 .set_duplex = sh_eth_set_duplex,
543 .register_type = SH_ETH_REG_GIGABIT,
545 .edtrr_trns = EDTRR_TRNS_GETHER,
546 .ecsr_value = ECSR_ICD,
547 .ecsipr_value = ECSIPR_ICDIP,
548 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP |
549 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP |
551 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
552 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
553 EESIPR_RMAFIP | EESIPR_RRFIP |
554 EESIPR_RTLFIP | EESIPR_RTSFIP |
555 EESIPR_PREIP | EESIPR_CERFIP,
557 .tx_check = EESR_TC1 | EESR_FTC,
558 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
559 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
561 .fdr_value = 0x0000070f,
563 .trscer_err_mask = TRSCER_RMAFCE | TRSCER_RRFCE,
580 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
582 sh_eth_chip_reset(ndev);
584 sh_eth_select_mii(ndev);
588 static struct sh_eth_cpu_data r8a7740_data = {
589 .soft_reset = sh_eth_soft_reset_gether,
591 .chip_reset = sh_eth_chip_reset_r8a7740,
592 .set_duplex = sh_eth_set_duplex,
593 .set_rate = sh_eth_set_rate_gether,
595 .register_type = SH_ETH_REG_GIGABIT,
597 .edtrr_trns = EDTRR_TRNS_GETHER,
598 .ecsr_value = ECSR_ICD | ECSR_MPD,
599 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
600 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
601 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
602 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
603 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
604 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
605 EESIPR_CEEFIP | EESIPR_CELFIP |
606 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
607 EESIPR_PREIP | EESIPR_CERFIP,
609 .tx_check = EESR_TC1 | EESR_FTC,
610 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
611 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
613 .fdr_value = 0x0000070f,
633 /* There is CPU dependent code */
634 static void sh_eth_set_rate_rcar(struct net_device *ndev)
636 struct sh_eth_private *mdp = netdev_priv(ndev);
638 switch (mdp->speed) {
639 case 10: /* 10BASE */
640 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
642 case 100:/* 100BASE */
643 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
649 static struct sh_eth_cpu_data rcar_gen1_data = {
650 .soft_reset = sh_eth_soft_reset,
652 .set_duplex = sh_eth_set_duplex,
653 .set_rate = sh_eth_set_rate_rcar,
655 .register_type = SH_ETH_REG_FAST_RCAR,
657 .edtrr_trns = EDTRR_TRNS_ETHER,
658 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
659 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
660 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
661 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
662 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
663 EESIPR_RMAFIP | EESIPR_RRFIP |
664 EESIPR_RTLFIP | EESIPR_RTSFIP |
665 EESIPR_PREIP | EESIPR_CERFIP,
667 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
668 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
669 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
670 .fdr_value = 0x00000f0f,
679 /* R-Car Gen2 and RZ/G1 */
680 static struct sh_eth_cpu_data rcar_gen2_data = {
681 .soft_reset = sh_eth_soft_reset,
683 .set_duplex = sh_eth_set_duplex,
684 .set_rate = sh_eth_set_rate_rcar,
686 .register_type = SH_ETH_REG_FAST_RCAR,
688 .edtrr_trns = EDTRR_TRNS_ETHER,
689 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
690 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
692 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
693 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
694 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
695 EESIPR_RMAFIP | EESIPR_RRFIP |
696 EESIPR_RTLFIP | EESIPR_RTSFIP |
697 EESIPR_PREIP | EESIPR_CERFIP,
699 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
700 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
701 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
702 .fdr_value = 0x00000f0f,
704 .trscer_err_mask = TRSCER_RMAFCE,
716 static struct sh_eth_cpu_data r8a77980_data = {
717 .soft_reset = sh_eth_soft_reset_gether,
719 .set_duplex = sh_eth_set_duplex,
720 .set_rate = sh_eth_set_rate_gether,
722 .register_type = SH_ETH_REG_GIGABIT,
724 .edtrr_trns = EDTRR_TRNS_GETHER,
725 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
726 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
728 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
729 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
730 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
731 EESIPR_RMAFIP | EESIPR_RRFIP |
732 EESIPR_RTLFIP | EESIPR_RTSFIP |
733 EESIPR_PREIP | EESIPR_CERFIP,
735 .tx_check = EESR_FTC | EESR_CD | EESR_TRO,
736 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
737 EESR_RFE | EESR_RDE | EESR_RFRMER |
738 EESR_TFE | EESR_TDE | EESR_ECI,
739 .fdr_value = 0x0000070f,
760 static struct sh_eth_cpu_data r7s9210_data = {
761 .soft_reset = sh_eth_soft_reset,
763 .set_duplex = sh_eth_set_duplex,
764 .set_rate = sh_eth_set_rate_rcar,
766 .register_type = SH_ETH_REG_FAST_SH4,
768 .edtrr_trns = EDTRR_TRNS_ETHER,
769 .ecsr_value = ECSR_ICD,
770 .ecsipr_value = ECSIPR_ICDIP,
771 .eesipr_value = EESIPR_TWBIP | EESIPR_TABTIP | EESIPR_RABTIP |
772 EESIPR_RFCOFIP | EESIPR_ECIIP | EESIPR_FTCIP |
773 EESIPR_TDEIP | EESIPR_TFUFIP | EESIPR_FRIP |
774 EESIPR_RDEIP | EESIPR_RFOFIP | EESIPR_CNDIP |
775 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
776 EESIPR_RMAFIP | EESIPR_RRFIP | EESIPR_RTLFIP |
777 EESIPR_RTSFIP | EESIPR_PREIP | EESIPR_CERFIP,
779 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
780 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
781 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
783 .fdr_value = 0x0000070f,
785 .trscer_err_mask = TRSCER_RMAFCE | TRSCER_RRFCE,
795 #endif /* CONFIG_OF */
797 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
799 struct sh_eth_private *mdp = netdev_priv(ndev);
801 switch (mdp->speed) {
802 case 10: /* 10BASE */
803 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
805 case 100:/* 100BASE */
806 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
812 static struct sh_eth_cpu_data sh7724_data = {
813 .soft_reset = sh_eth_soft_reset,
815 .set_duplex = sh_eth_set_duplex,
816 .set_rate = sh_eth_set_rate_sh7724,
818 .register_type = SH_ETH_REG_FAST_SH4,
820 .edtrr_trns = EDTRR_TRNS_ETHER,
821 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
822 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
823 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
824 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
825 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
826 EESIPR_RMAFIP | EESIPR_RRFIP |
827 EESIPR_RTLFIP | EESIPR_RTSFIP |
828 EESIPR_PREIP | EESIPR_CERFIP,
830 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
831 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
832 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
841 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
843 struct sh_eth_private *mdp = netdev_priv(ndev);
845 switch (mdp->speed) {
846 case 10: /* 10BASE */
847 sh_eth_write(ndev, 0, RTRATE);
849 case 100:/* 100BASE */
850 sh_eth_write(ndev, 1, RTRATE);
856 static struct sh_eth_cpu_data sh7757_data = {
857 .soft_reset = sh_eth_soft_reset,
859 .set_duplex = sh_eth_set_duplex,
860 .set_rate = sh_eth_set_rate_sh7757,
862 .register_type = SH_ETH_REG_FAST_SH4,
864 .edtrr_trns = EDTRR_TRNS_ETHER,
865 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
866 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
867 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
868 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
869 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
870 EESIPR_CEEFIP | EESIPR_CELFIP |
871 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
872 EESIPR_PREIP | EESIPR_CERFIP,
874 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
875 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
876 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
878 .irq_flags = IRQF_SHARED,
889 #define SH_GIGA_ETH_BASE 0xfee00000UL
890 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
891 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
892 static void sh_eth_chip_reset_giga(struct net_device *ndev)
894 u32 mahr[2], malr[2];
897 /* save MAHR and MALR */
898 for (i = 0; i < 2; i++) {
899 malr[i] = ioread32((void *)GIGA_MALR(i));
900 mahr[i] = ioread32((void *)GIGA_MAHR(i));
903 sh_eth_chip_reset(ndev);
905 /* restore MAHR and MALR */
906 for (i = 0; i < 2; i++) {
907 iowrite32(malr[i], (void *)GIGA_MALR(i));
908 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
912 static void sh_eth_set_rate_giga(struct net_device *ndev)
914 struct sh_eth_private *mdp = netdev_priv(ndev);
916 if (WARN_ON(!mdp->cd->gecmr))
919 switch (mdp->speed) {
920 case 10: /* 10BASE */
921 sh_eth_write(ndev, 0x00000000, GECMR);
923 case 100:/* 100BASE */
924 sh_eth_write(ndev, 0x00000010, GECMR);
926 case 1000: /* 1000BASE */
927 sh_eth_write(ndev, 0x00000020, GECMR);
932 /* SH7757(GETHERC) */
933 static struct sh_eth_cpu_data sh7757_data_giga = {
934 .soft_reset = sh_eth_soft_reset_gether,
936 .chip_reset = sh_eth_chip_reset_giga,
937 .set_duplex = sh_eth_set_duplex,
938 .set_rate = sh_eth_set_rate_giga,
940 .register_type = SH_ETH_REG_GIGABIT,
942 .edtrr_trns = EDTRR_TRNS_GETHER,
943 .ecsr_value = ECSR_ICD | ECSR_MPD,
944 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
945 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
946 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
947 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
948 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
949 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
950 EESIPR_CEEFIP | EESIPR_CELFIP |
951 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
952 EESIPR_PREIP | EESIPR_CERFIP,
954 .tx_check = EESR_TC1 | EESR_FTC,
955 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
956 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
958 .fdr_value = 0x0000072f,
960 .irq_flags = IRQF_SHARED,
977 static struct sh_eth_cpu_data sh7734_data = {
978 .soft_reset = sh_eth_soft_reset_gether,
980 .chip_reset = sh_eth_chip_reset,
981 .set_duplex = sh_eth_set_duplex,
982 .set_rate = sh_eth_set_rate_gether,
984 .register_type = SH_ETH_REG_GIGABIT,
986 .edtrr_trns = EDTRR_TRNS_GETHER,
987 .ecsr_value = ECSR_ICD | ECSR_MPD,
988 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
989 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
990 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
991 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
992 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
993 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
994 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
995 EESIPR_PREIP | EESIPR_CERFIP,
997 .tx_check = EESR_TC1 | EESR_FTC,
998 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
999 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
1020 static struct sh_eth_cpu_data sh7763_data = {
1021 .soft_reset = sh_eth_soft_reset_gether,
1023 .chip_reset = sh_eth_chip_reset,
1024 .set_duplex = sh_eth_set_duplex,
1025 .set_rate = sh_eth_set_rate_gether,
1027 .register_type = SH_ETH_REG_GIGABIT,
1029 .edtrr_trns = EDTRR_TRNS_GETHER,
1030 .ecsr_value = ECSR_ICD | ECSR_MPD,
1031 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
1032 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1033 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1034 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1035 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
1036 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
1037 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1038 EESIPR_PREIP | EESIPR_CERFIP,
1040 .tx_check = EESR_TC1 | EESR_FTC,
1041 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
1042 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
1054 .irq_flags = IRQF_SHARED,
1061 static struct sh_eth_cpu_data sh7619_data = {
1062 .soft_reset = sh_eth_soft_reset,
1064 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1066 .edtrr_trns = EDTRR_TRNS_ETHER,
1067 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1068 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1069 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1070 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1071 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1072 EESIPR_CEEFIP | EESIPR_CELFIP |
1073 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1074 EESIPR_PREIP | EESIPR_CERFIP,
1082 static struct sh_eth_cpu_data sh771x_data = {
1083 .soft_reset = sh_eth_soft_reset,
1085 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1087 .edtrr_trns = EDTRR_TRNS_ETHER,
1088 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1089 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1090 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1091 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1092 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1093 EESIPR_CEEFIP | EESIPR_CELFIP |
1094 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1095 EESIPR_PREIP | EESIPR_CERFIP,
1097 .trscer_err_mask = TRSCER_RMAFCE,
1103 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
1105 if (!cd->ecsr_value)
1106 cd->ecsr_value = DEFAULT_ECSR_INIT;
1108 if (!cd->ecsipr_value)
1109 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
1111 if (!cd->fcftr_value)
1112 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
1113 DEFAULT_FIFO_F_D_RFD;
1116 cd->fdr_value = DEFAULT_FDR_INIT;
1119 cd->tx_check = DEFAULT_TX_CHECK;
1121 if (!cd->eesr_err_check)
1122 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
1124 if (!cd->trscer_err_mask)
1125 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
1128 static void sh_eth_set_receive_align(struct sk_buff *skb)
1130 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
1133 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
1136 /* Program the hardware MAC address from dev->dev_addr. */
1137 static void update_mac_address(struct net_device *ndev)
1140 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
1141 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
1143 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
1146 /* Get MAC address from SuperH MAC address register
1148 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1149 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1150 * When you want use this device, you must set MAC address in bootloader.
1153 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
1155 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
1156 memcpy(ndev->dev_addr, mac, ETH_ALEN);
1158 u32 mahr = sh_eth_read(ndev, MAHR);
1159 u32 malr = sh_eth_read(ndev, MALR);
1161 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
1162 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
1163 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
1164 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
1165 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
1166 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
1171 void (*set_gate)(void *addr);
1172 struct mdiobb_ctrl ctrl;
1176 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1178 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1181 if (bitbang->set_gate)
1182 bitbang->set_gate(bitbang->addr);
1184 pir = ioread32(bitbang->addr);
1189 iowrite32(pir, bitbang->addr);
1192 /* Data I/O pin control */
1193 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1195 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1199 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1201 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1205 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1207 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1209 if (bitbang->set_gate)
1210 bitbang->set_gate(bitbang->addr);
1212 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1215 /* MDC pin control */
1216 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1218 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1221 /* mdio bus control struct */
1222 static const struct mdiobb_ops bb_ops = {
1223 .owner = THIS_MODULE,
1224 .set_mdc = sh_mdc_ctrl,
1225 .set_mdio_dir = sh_mmd_ctrl,
1226 .set_mdio_data = sh_set_mdio,
1227 .get_mdio_data = sh_get_mdio,
1230 /* free Tx skb function */
1231 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
1233 struct sh_eth_private *mdp = netdev_priv(ndev);
1234 struct sh_eth_txdesc *txdesc;
1239 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1240 entry = mdp->dirty_tx % mdp->num_tx_ring;
1241 txdesc = &mdp->tx_ring[entry];
1242 sent = !(txdesc->status & cpu_to_le32(TD_TACT));
1243 if (sent_only && !sent)
1245 /* TACT bit must be checked before all the following reads */
1247 netif_info(mdp, tx_done, ndev,
1248 "tx entry %d status 0x%08x\n",
1249 entry, le32_to_cpu(txdesc->status));
1250 /* Free the original skb. */
1251 if (mdp->tx_skbuff[entry]) {
1252 dma_unmap_single(&mdp->pdev->dev,
1253 le32_to_cpu(txdesc->addr),
1254 le32_to_cpu(txdesc->len) >> 16,
1256 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1257 mdp->tx_skbuff[entry] = NULL;
1260 txdesc->status = cpu_to_le32(TD_TFP);
1261 if (entry >= mdp->num_tx_ring - 1)
1262 txdesc->status |= cpu_to_le32(TD_TDLE);
1265 ndev->stats.tx_packets++;
1266 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1272 /* free skb and descriptor buffer */
1273 static void sh_eth_ring_free(struct net_device *ndev)
1275 struct sh_eth_private *mdp = netdev_priv(ndev);
1279 for (i = 0; i < mdp->num_rx_ring; i++) {
1280 if (mdp->rx_skbuff[i]) {
1281 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
1283 dma_unmap_single(&mdp->pdev->dev,
1284 le32_to_cpu(rxdesc->addr),
1285 ALIGN(mdp->rx_buf_sz, 32),
1289 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1290 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring,
1292 mdp->rx_ring = NULL;
1295 /* Free Rx skb ringbuffer */
1296 if (mdp->rx_skbuff) {
1297 for (i = 0; i < mdp->num_rx_ring; i++)
1298 dev_kfree_skb(mdp->rx_skbuff[i]);
1300 kfree(mdp->rx_skbuff);
1301 mdp->rx_skbuff = NULL;
1304 sh_eth_tx_free(ndev, false);
1306 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1307 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring,
1309 mdp->tx_ring = NULL;
1312 /* Free Tx skb ringbuffer */
1313 kfree(mdp->tx_skbuff);
1314 mdp->tx_skbuff = NULL;
1317 /* format skb and descriptor buffer */
1318 static void sh_eth_ring_format(struct net_device *ndev)
1320 struct sh_eth_private *mdp = netdev_priv(ndev);
1322 struct sk_buff *skb;
1323 struct sh_eth_rxdesc *rxdesc = NULL;
1324 struct sh_eth_txdesc *txdesc = NULL;
1325 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1326 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1327 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1328 dma_addr_t dma_addr;
1336 memset(mdp->rx_ring, 0, rx_ringsize);
1338 /* build Rx ring buffer */
1339 for (i = 0; i < mdp->num_rx_ring; i++) {
1341 mdp->rx_skbuff[i] = NULL;
1342 skb = netdev_alloc_skb(ndev, skbuff_size);
1345 sh_eth_set_receive_align(skb);
1347 /* The size of the buffer is a multiple of 32 bytes. */
1348 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1349 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len,
1351 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1355 mdp->rx_skbuff[i] = skb;
1358 rxdesc = &mdp->rx_ring[i];
1359 rxdesc->len = cpu_to_le32(buf_len << 16);
1360 rxdesc->addr = cpu_to_le32(dma_addr);
1361 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1363 /* Rx descriptor address set */
1365 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1366 if (mdp->cd->xdfar_rw)
1367 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1371 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1373 /* Mark the last entry as wrapping the ring. */
1375 rxdesc->status |= cpu_to_le32(RD_RDLE);
1377 memset(mdp->tx_ring, 0, tx_ringsize);
1379 /* build Tx ring buffer */
1380 for (i = 0; i < mdp->num_tx_ring; i++) {
1381 mdp->tx_skbuff[i] = NULL;
1382 txdesc = &mdp->tx_ring[i];
1383 txdesc->status = cpu_to_le32(TD_TFP);
1384 txdesc->len = cpu_to_le32(0);
1386 /* Tx descriptor address set */
1387 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1388 if (mdp->cd->xdfar_rw)
1389 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1393 txdesc->status |= cpu_to_le32(TD_TDLE);
1396 /* Get skb and descriptor buffer */
1397 static int sh_eth_ring_init(struct net_device *ndev)
1399 struct sh_eth_private *mdp = netdev_priv(ndev);
1400 int rx_ringsize, tx_ringsize;
1402 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1403 * card needs room to do 8 byte alignment, +2 so we can reserve
1404 * the first 2 bytes, and +16 gets room for the status word from the
1407 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1408 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1409 if (mdp->cd->rpadir)
1410 mdp->rx_buf_sz += NET_IP_ALIGN;
1412 /* Allocate RX and TX skb rings */
1413 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1415 if (!mdp->rx_skbuff)
1418 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1420 if (!mdp->tx_skbuff)
1423 /* Allocate all Rx descriptors. */
1424 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1425 mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize,
1426 &mdp->rx_desc_dma, GFP_KERNEL);
1432 /* Allocate all Tx descriptors. */
1433 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1434 mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize,
1435 &mdp->tx_desc_dma, GFP_KERNEL);
1441 /* Free Rx and Tx skb ring buffer and DMA buffer */
1442 sh_eth_ring_free(ndev);
1447 static int sh_eth_dev_init(struct net_device *ndev)
1449 struct sh_eth_private *mdp = netdev_priv(ndev);
1453 ret = mdp->cd->soft_reset(ndev);
1457 if (mdp->cd->rmiimode)
1458 sh_eth_write(ndev, 0x1, RMIIMODE);
1460 /* Descriptor format */
1461 sh_eth_ring_format(ndev);
1462 if (mdp->cd->rpadir)
1463 sh_eth_write(ndev, NET_IP_ALIGN << 16, RPADIR);
1465 /* all sh_eth int mask */
1466 sh_eth_write(ndev, 0, EESIPR);
1468 #if defined(__LITTLE_ENDIAN)
1469 if (mdp->cd->hw_swap)
1470 sh_eth_write(ndev, EDMR_EL, EDMR);
1473 sh_eth_write(ndev, 0, EDMR);
1476 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1477 sh_eth_write(ndev, 0, TFTR);
1479 /* Frame recv control (enable multiple-packets per rx irq) */
1480 sh_eth_write(ndev, RMCR_RNC, RMCR);
1482 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1484 /* DMA transfer burst mode */
1486 sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST);
1488 /* Burst cycle count upper-limit */
1490 sh_eth_write(ndev, 0x800, BCULR);
1492 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1494 if (!mdp->cd->no_trimd)
1495 sh_eth_write(ndev, 0, TRIMD);
1497 /* Recv frame limit set register */
1498 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1501 sh_eth_modify(ndev, EESR, 0, 0);
1502 mdp->irq_enabled = true;
1503 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1505 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
1506 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1507 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
1508 ECMR_TE | ECMR_RE, ECMR);
1510 if (mdp->cd->set_rate)
1511 mdp->cd->set_rate(ndev);
1513 /* E-MAC Status Register clear */
1514 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1516 /* E-MAC Interrupt Enable register */
1517 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1519 /* Set MAC address */
1520 update_mac_address(ndev);
1524 sh_eth_write(ndev, 1, APR);
1526 sh_eth_write(ndev, 1, MPR);
1527 if (mdp->cd->tpauser)
1528 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1530 /* Setting the Rx mode will start the Rx process. */
1531 sh_eth_write(ndev, EDRRR_R, EDRRR);
1536 static void sh_eth_dev_exit(struct net_device *ndev)
1538 struct sh_eth_private *mdp = netdev_priv(ndev);
1541 /* Deactivate all TX descriptors, so DMA should stop at next
1542 * packet boundary if it's currently running
1544 for (i = 0; i < mdp->num_tx_ring; i++)
1545 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1547 /* Disable TX FIFO egress to MAC */
1548 sh_eth_rcv_snd_disable(ndev);
1550 /* Stop RX DMA at next packet boundary */
1551 sh_eth_write(ndev, 0, EDRRR);
1553 /* Aside from TX DMA, we can't tell when the hardware is
1554 * really stopped, so we need to reset to make sure.
1555 * Before doing that, wait for long enough to *probably*
1556 * finish transmitting the last packet and poll stats.
1558 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1559 sh_eth_get_stats(ndev);
1560 mdp->cd->soft_reset(ndev);
1562 /* Set the RMII mode again if required */
1563 if (mdp->cd->rmiimode)
1564 sh_eth_write(ndev, 0x1, RMIIMODE);
1566 /* Set MAC address again */
1567 update_mac_address(ndev);
1570 static void sh_eth_rx_csum(struct sk_buff *skb)
1574 /* The hardware checksum is 2 bytes appended to packet data */
1575 if (unlikely(skb->len < sizeof(__sum16)))
1577 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16);
1578 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
1579 skb->ip_summed = CHECKSUM_COMPLETE;
1580 skb_trim(skb, skb->len - sizeof(__sum16));
1583 /* Packet receive function */
1584 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1586 struct sh_eth_private *mdp = netdev_priv(ndev);
1587 struct sh_eth_rxdesc *rxdesc;
1589 int entry = mdp->cur_rx % mdp->num_rx_ring;
1590 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1592 struct sk_buff *skb;
1594 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1595 dma_addr_t dma_addr;
1599 boguscnt = min(boguscnt, *quota);
1601 rxdesc = &mdp->rx_ring[entry];
1602 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1603 /* RACT bit must be checked before all the following reads */
1605 desc_status = le32_to_cpu(rxdesc->status);
1606 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1611 netif_info(mdp, rx_status, ndev,
1612 "rx entry %d status 0x%08x len %d\n",
1613 entry, desc_status, pkt_len);
1615 if (!(desc_status & RDFEND))
1616 ndev->stats.rx_length_errors++;
1618 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1619 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1620 * bit 0. However, in case of the R8A7740 and R7S72100
1621 * the RFS bits are from bit 25 to bit 16. So, the
1622 * driver needs right shifting by 16.
1627 skb = mdp->rx_skbuff[entry];
1628 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1629 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1630 ndev->stats.rx_errors++;
1631 if (desc_status & RD_RFS1)
1632 ndev->stats.rx_crc_errors++;
1633 if (desc_status & RD_RFS2)
1634 ndev->stats.rx_frame_errors++;
1635 if (desc_status & RD_RFS3)
1636 ndev->stats.rx_length_errors++;
1637 if (desc_status & RD_RFS4)
1638 ndev->stats.rx_length_errors++;
1639 if (desc_status & RD_RFS6)
1640 ndev->stats.rx_missed_errors++;
1641 if (desc_status & RD_RFS10)
1642 ndev->stats.rx_over_errors++;
1644 dma_addr = le32_to_cpu(rxdesc->addr);
1645 if (!mdp->cd->hw_swap)
1647 phys_to_virt(ALIGN(dma_addr, 4)),
1649 mdp->rx_skbuff[entry] = NULL;
1650 if (mdp->cd->rpadir)
1651 skb_reserve(skb, NET_IP_ALIGN);
1652 dma_unmap_single(&mdp->pdev->dev, dma_addr,
1653 ALIGN(mdp->rx_buf_sz, 32),
1655 skb_put(skb, pkt_len);
1656 skb->protocol = eth_type_trans(skb, ndev);
1657 if (ndev->features & NETIF_F_RXCSUM)
1658 sh_eth_rx_csum(skb);
1659 netif_receive_skb(skb);
1660 ndev->stats.rx_packets++;
1661 ndev->stats.rx_bytes += pkt_len;
1662 if (desc_status & RD_RFS8)
1663 ndev->stats.multicast++;
1665 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1666 rxdesc = &mdp->rx_ring[entry];
1669 /* Refill the Rx ring buffers. */
1670 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1671 entry = mdp->dirty_rx % mdp->num_rx_ring;
1672 rxdesc = &mdp->rx_ring[entry];
1673 /* The size of the buffer is 32 byte boundary. */
1674 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1675 rxdesc->len = cpu_to_le32(buf_len << 16);
1677 if (mdp->rx_skbuff[entry] == NULL) {
1678 skb = netdev_alloc_skb(ndev, skbuff_size);
1680 break; /* Better luck next round. */
1681 sh_eth_set_receive_align(skb);
1682 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data,
1683 buf_len, DMA_FROM_DEVICE);
1684 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1688 mdp->rx_skbuff[entry] = skb;
1690 skb_checksum_none_assert(skb);
1691 rxdesc->addr = cpu_to_le32(dma_addr);
1693 dma_wmb(); /* RACT bit must be set after all the above writes */
1694 if (entry >= mdp->num_rx_ring - 1)
1696 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1698 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1701 /* Restart Rx engine if stopped. */
1702 /* If we don't need to check status, don't. -KDU */
1703 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1704 /* fix the values for the next receiving if RDE is set */
1705 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) {
1706 u32 count = (sh_eth_read(ndev, RDFAR) -
1707 sh_eth_read(ndev, RDLAR)) >> 4;
1709 mdp->cur_rx = count;
1710 mdp->dirty_rx = count;
1712 sh_eth_write(ndev, EDRRR_R, EDRRR);
1715 *quota -= limit - boguscnt - 1;
1720 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1722 /* disable tx and rx */
1723 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1726 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1728 /* enable tx and rx */
1729 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1732 /* E-MAC interrupt handler */
1733 static void sh_eth_emac_interrupt(struct net_device *ndev)
1735 struct sh_eth_private *mdp = netdev_priv(ndev);
1739 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
1740 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1741 if (felic_stat & ECSR_ICD)
1742 ndev->stats.tx_carrier_errors++;
1743 if (felic_stat & ECSR_MPD)
1744 pm_wakeup_event(&mdp->pdev->dev, 0);
1745 if (felic_stat & ECSR_LCHNG) {
1747 if (mdp->cd->no_psr || mdp->no_ether_link)
1749 link_stat = sh_eth_read(ndev, PSR);
1750 if (mdp->ether_link_active_low)
1751 link_stat = ~link_stat;
1752 if (!(link_stat & PSR_LMON)) {
1753 sh_eth_rcv_snd_disable(ndev);
1756 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0);
1758 sh_eth_modify(ndev, ECSR, 0, 0);
1759 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP);
1760 /* enable tx and rx */
1761 sh_eth_rcv_snd_enable(ndev);
1766 /* error control function */
1767 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1769 struct sh_eth_private *mdp = netdev_priv(ndev);
1772 if (intr_status & EESR_TWB) {
1773 /* Unused write back interrupt */
1774 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1775 ndev->stats.tx_aborted_errors++;
1776 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1780 if (intr_status & EESR_RABT) {
1781 /* Receive Abort int */
1782 if (intr_status & EESR_RFRMER) {
1783 /* Receive Frame Overflow int */
1784 ndev->stats.rx_frame_errors++;
1788 if (intr_status & EESR_TDE) {
1789 /* Transmit Descriptor Empty int */
1790 ndev->stats.tx_fifo_errors++;
1791 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1794 if (intr_status & EESR_TFE) {
1795 /* FIFO under flow */
1796 ndev->stats.tx_fifo_errors++;
1797 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1800 if (intr_status & EESR_RDE) {
1801 /* Receive Descriptor Empty int */
1802 ndev->stats.rx_over_errors++;
1805 if (intr_status & EESR_RFE) {
1806 /* Receive FIFO Overflow int */
1807 ndev->stats.rx_fifo_errors++;
1810 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1812 ndev->stats.tx_fifo_errors++;
1813 netif_err(mdp, tx_err, ndev, "Address Error\n");
1816 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1817 if (mdp->cd->no_ade)
1819 if (intr_status & mask) {
1821 u32 edtrr = sh_eth_read(ndev, EDTRR);
1824 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1825 intr_status, mdp->cur_tx, mdp->dirty_tx,
1826 (u32)ndev->state, edtrr);
1827 /* dirty buffer free */
1828 sh_eth_tx_free(ndev, true);
1831 if (edtrr ^ mdp->cd->edtrr_trns) {
1833 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
1836 netif_wake_queue(ndev);
1840 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1842 struct net_device *ndev = netdev;
1843 struct sh_eth_private *mdp = netdev_priv(ndev);
1844 struct sh_eth_cpu_data *cd = mdp->cd;
1845 irqreturn_t ret = IRQ_NONE;
1846 u32 intr_status, intr_enable;
1848 spin_lock(&mdp->lock);
1850 /* Get interrupt status */
1851 intr_status = sh_eth_read(ndev, EESR);
1852 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1853 * enabled since it's the one that comes thru regardless of the mask,
1854 * and we need to fully handle it in sh_eth_emac_interrupt() in order
1855 * to quench it as it doesn't get cleared by just writing 1 to the ECI
1858 intr_enable = sh_eth_read(ndev, EESIPR);
1859 intr_status &= intr_enable | EESIPR_ECIIP;
1860 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
1861 cd->eesr_err_check))
1866 if (unlikely(!mdp->irq_enabled)) {
1867 sh_eth_write(ndev, 0, EESIPR);
1871 if (intr_status & EESR_RX_CHECK) {
1872 if (napi_schedule_prep(&mdp->napi)) {
1873 /* Mask Rx interrupts */
1874 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1876 __napi_schedule(&mdp->napi);
1879 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1880 intr_status, intr_enable);
1885 if (intr_status & cd->tx_check) {
1886 /* Clear Tx interrupts */
1887 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1889 sh_eth_tx_free(ndev, true);
1890 netif_wake_queue(ndev);
1893 /* E-MAC interrupt */
1894 if (intr_status & EESR_ECI)
1895 sh_eth_emac_interrupt(ndev);
1897 if (intr_status & cd->eesr_err_check) {
1898 /* Clear error interrupts */
1899 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1901 sh_eth_error(ndev, intr_status);
1905 spin_unlock(&mdp->lock);
1910 static int sh_eth_poll(struct napi_struct *napi, int budget)
1912 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1914 struct net_device *ndev = napi->dev;
1919 intr_status = sh_eth_read(ndev, EESR);
1920 if (!(intr_status & EESR_RX_CHECK))
1922 /* Clear Rx interrupts */
1923 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1925 if (sh_eth_rx(ndev, intr_status, "a))
1929 napi_complete(napi);
1931 /* Reenable Rx interrupts */
1932 if (mdp->irq_enabled)
1933 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1935 return budget - quota;
1938 /* PHY state control function */
1939 static void sh_eth_adjust_link(struct net_device *ndev)
1941 struct sh_eth_private *mdp = netdev_priv(ndev);
1942 struct phy_device *phydev = ndev->phydev;
1943 unsigned long flags;
1946 spin_lock_irqsave(&mdp->lock, flags);
1948 /* Disable TX and RX right over here, if E-MAC change is ignored */
1949 if (mdp->cd->no_psr || mdp->no_ether_link)
1950 sh_eth_rcv_snd_disable(ndev);
1953 if (phydev->duplex != mdp->duplex) {
1955 mdp->duplex = phydev->duplex;
1956 if (mdp->cd->set_duplex)
1957 mdp->cd->set_duplex(ndev);
1960 if (phydev->speed != mdp->speed) {
1962 mdp->speed = phydev->speed;
1963 if (mdp->cd->set_rate)
1964 mdp->cd->set_rate(ndev);
1967 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1969 mdp->link = phydev->link;
1971 } else if (mdp->link) {
1978 /* Enable TX and RX right over here, if E-MAC change is ignored */
1979 if ((mdp->cd->no_psr || mdp->no_ether_link) && phydev->link)
1980 sh_eth_rcv_snd_enable(ndev);
1982 spin_unlock_irqrestore(&mdp->lock, flags);
1984 if (new_state && netif_msg_link(mdp))
1985 phy_print_status(phydev);
1988 /* PHY init function */
1989 static int sh_eth_phy_init(struct net_device *ndev)
1991 struct device_node *np = ndev->dev.parent->of_node;
1992 struct sh_eth_private *mdp = netdev_priv(ndev);
1993 struct phy_device *phydev;
1999 /* Try connect to PHY */
2001 struct device_node *pn;
2003 pn = of_parse_phandle(np, "phy-handle", 0);
2004 phydev = of_phy_connect(ndev, pn,
2005 sh_eth_adjust_link, 0,
2006 mdp->phy_interface);
2010 phydev = ERR_PTR(-ENOENT);
2012 char phy_id[MII_BUS_ID_SIZE + 3];
2014 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2015 mdp->mii_bus->id, mdp->phy_id);
2017 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
2018 mdp->phy_interface);
2021 if (IS_ERR(phydev)) {
2022 netdev_err(ndev, "failed to connect PHY\n");
2023 return PTR_ERR(phydev);
2026 /* mask with MAC supported features */
2027 if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) {
2028 int err = phy_set_max_speed(phydev, SPEED_100);
2030 netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n");
2031 phy_disconnect(phydev);
2036 phy_attached_info(phydev);
2041 /* PHY control start function */
2042 static int sh_eth_phy_start(struct net_device *ndev)
2046 ret = sh_eth_phy_init(ndev);
2050 phy_start(ndev->phydev);
2055 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
2056 * version must be bumped as well. Just adding registers up to that
2057 * limit is fine, as long as the existing register indices don't
2060 #define SH_ETH_REG_DUMP_VERSION 1
2061 #define SH_ETH_REG_DUMP_MAX_REGS 256
2063 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
2065 struct sh_eth_private *mdp = netdev_priv(ndev);
2066 struct sh_eth_cpu_data *cd = mdp->cd;
2070 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
2072 /* Dump starts with a bitmap that tells ethtool which
2073 * registers are defined for this chip.
2075 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
2083 /* Add a register to the dump, if it has a defined offset.
2084 * This automatically skips most undefined registers, but for
2085 * some it is also necessary to check a capability flag in
2086 * struct sh_eth_cpu_data.
2088 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
2089 #define add_reg_from(reg, read_expr) do { \
2090 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
2092 mark_reg_valid(reg); \
2093 *buf++ = read_expr; \
2098 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2099 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2155 if (!cd->no_tx_cntrs) {
2178 add_tsu_reg(TSU_CTRST);
2179 if (cd->dual_port) {
2180 add_tsu_reg(TSU_FWEN0);
2181 add_tsu_reg(TSU_FWEN1);
2182 add_tsu_reg(TSU_FCM);
2183 add_tsu_reg(TSU_BSYSL0);
2184 add_tsu_reg(TSU_BSYSL1);
2185 add_tsu_reg(TSU_PRISL0);
2186 add_tsu_reg(TSU_PRISL1);
2187 add_tsu_reg(TSU_FWSL0);
2188 add_tsu_reg(TSU_FWSL1);
2190 add_tsu_reg(TSU_FWSLC);
2191 if (cd->dual_port) {
2192 add_tsu_reg(TSU_QTAGM0);
2193 add_tsu_reg(TSU_QTAGM1);
2194 add_tsu_reg(TSU_FWSR);
2195 add_tsu_reg(TSU_FWINMK);
2196 add_tsu_reg(TSU_ADQT0);
2197 add_tsu_reg(TSU_ADQT1);
2198 add_tsu_reg(TSU_VTAG0);
2199 add_tsu_reg(TSU_VTAG1);
2201 add_tsu_reg(TSU_ADSBSY);
2202 add_tsu_reg(TSU_TEN);
2203 add_tsu_reg(TSU_POST1);
2204 add_tsu_reg(TSU_POST2);
2205 add_tsu_reg(TSU_POST3);
2206 add_tsu_reg(TSU_POST4);
2207 /* This is the start of a table, not just a single register. */
2211 mark_reg_valid(TSU_ADRH0);
2212 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2213 *buf++ = ioread32(mdp->tsu_addr +
2214 mdp->reg_offset[TSU_ADRH0] +
2217 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2220 #undef mark_reg_valid
2228 static int sh_eth_get_regs_len(struct net_device *ndev)
2230 return __sh_eth_get_regs(ndev, NULL);
2233 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2236 struct sh_eth_private *mdp = netdev_priv(ndev);
2238 regs->version = SH_ETH_REG_DUMP_VERSION;
2240 pm_runtime_get_sync(&mdp->pdev->dev);
2241 __sh_eth_get_regs(ndev, buf);
2242 pm_runtime_put_sync(&mdp->pdev->dev);
2245 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2247 struct sh_eth_private *mdp = netdev_priv(ndev);
2248 return mdp->msg_enable;
2251 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2253 struct sh_eth_private *mdp = netdev_priv(ndev);
2254 mdp->msg_enable = value;
2257 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2258 "rx_current", "tx_current",
2259 "rx_dirty", "tx_dirty",
2261 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2263 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2267 return SH_ETH_STATS_LEN;
2273 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2274 struct ethtool_stats *stats, u64 *data)
2276 struct sh_eth_private *mdp = netdev_priv(ndev);
2279 /* device-specific stats */
2280 data[i++] = mdp->cur_rx;
2281 data[i++] = mdp->cur_tx;
2282 data[i++] = mdp->dirty_rx;
2283 data[i++] = mdp->dirty_tx;
2286 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2288 switch (stringset) {
2290 memcpy(data, sh_eth_gstrings_stats,
2291 sizeof(sh_eth_gstrings_stats));
2296 static void sh_eth_get_ringparam(struct net_device *ndev,
2297 struct ethtool_ringparam *ring)
2299 struct sh_eth_private *mdp = netdev_priv(ndev);
2301 ring->rx_max_pending = RX_RING_MAX;
2302 ring->tx_max_pending = TX_RING_MAX;
2303 ring->rx_pending = mdp->num_rx_ring;
2304 ring->tx_pending = mdp->num_tx_ring;
2307 static int sh_eth_set_ringparam(struct net_device *ndev,
2308 struct ethtool_ringparam *ring)
2310 struct sh_eth_private *mdp = netdev_priv(ndev);
2313 if (ring->tx_pending > TX_RING_MAX ||
2314 ring->rx_pending > RX_RING_MAX ||
2315 ring->tx_pending < TX_RING_MIN ||
2316 ring->rx_pending < RX_RING_MIN)
2318 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2321 if (netif_running(ndev)) {
2322 netif_device_detach(ndev);
2323 netif_tx_disable(ndev);
2325 /* Serialise with the interrupt handler and NAPI, then
2326 * disable interrupts. We have to clear the
2327 * irq_enabled flag first to ensure that interrupts
2328 * won't be re-enabled.
2330 mdp->irq_enabled = false;
2331 synchronize_irq(ndev->irq);
2332 napi_synchronize(&mdp->napi);
2333 sh_eth_write(ndev, 0x0000, EESIPR);
2335 sh_eth_dev_exit(ndev);
2337 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2338 sh_eth_ring_free(ndev);
2341 /* Set new parameters */
2342 mdp->num_rx_ring = ring->rx_pending;
2343 mdp->num_tx_ring = ring->tx_pending;
2345 if (netif_running(ndev)) {
2346 ret = sh_eth_ring_init(ndev);
2348 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2352 ret = sh_eth_dev_init(ndev);
2354 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2359 netif_device_attach(ndev);
2365 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2367 struct sh_eth_private *mdp = netdev_priv(ndev);
2372 if (mdp->cd->magic) {
2373 wol->supported = WAKE_MAGIC;
2374 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
2378 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2380 struct sh_eth_private *mdp = netdev_priv(ndev);
2382 if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC)
2385 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
2387 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled);
2392 static const struct ethtool_ops sh_eth_ethtool_ops = {
2393 .get_regs_len = sh_eth_get_regs_len,
2394 .get_regs = sh_eth_get_regs,
2395 .nway_reset = phy_ethtool_nway_reset,
2396 .get_msglevel = sh_eth_get_msglevel,
2397 .set_msglevel = sh_eth_set_msglevel,
2398 .get_link = ethtool_op_get_link,
2399 .get_strings = sh_eth_get_strings,
2400 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2401 .get_sset_count = sh_eth_get_sset_count,
2402 .get_ringparam = sh_eth_get_ringparam,
2403 .set_ringparam = sh_eth_set_ringparam,
2404 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2405 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2406 .get_wol = sh_eth_get_wol,
2407 .set_wol = sh_eth_set_wol,
2410 /* network device open function */
2411 static int sh_eth_open(struct net_device *ndev)
2413 struct sh_eth_private *mdp = netdev_priv(ndev);
2416 pm_runtime_get_sync(&mdp->pdev->dev);
2418 napi_enable(&mdp->napi);
2420 ret = request_irq(ndev->irq, sh_eth_interrupt,
2421 mdp->cd->irq_flags, ndev->name, ndev);
2423 netdev_err(ndev, "Can not assign IRQ number\n");
2427 /* Descriptor set */
2428 ret = sh_eth_ring_init(ndev);
2433 ret = sh_eth_dev_init(ndev);
2437 /* PHY control start*/
2438 ret = sh_eth_phy_start(ndev);
2442 netif_start_queue(ndev);
2449 free_irq(ndev->irq, ndev);
2451 napi_disable(&mdp->napi);
2452 pm_runtime_put_sync(&mdp->pdev->dev);
2456 /* Timeout function */
2457 static void sh_eth_tx_timeout(struct net_device *ndev, unsigned int txqueue)
2459 struct sh_eth_private *mdp = netdev_priv(ndev);
2460 struct sh_eth_rxdesc *rxdesc;
2463 netif_stop_queue(ndev);
2465 netif_err(mdp, timer, ndev,
2466 "transmit timed out, status %8.8x, resetting...\n",
2467 sh_eth_read(ndev, EESR));
2469 /* tx_errors count up */
2470 ndev->stats.tx_errors++;
2472 /* Free all the skbuffs in the Rx queue. */
2473 for (i = 0; i < mdp->num_rx_ring; i++) {
2474 rxdesc = &mdp->rx_ring[i];
2475 rxdesc->status = cpu_to_le32(0);
2476 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2477 dev_kfree_skb(mdp->rx_skbuff[i]);
2478 mdp->rx_skbuff[i] = NULL;
2480 for (i = 0; i < mdp->num_tx_ring; i++) {
2481 dev_kfree_skb(mdp->tx_skbuff[i]);
2482 mdp->tx_skbuff[i] = NULL;
2486 sh_eth_dev_init(ndev);
2488 netif_start_queue(ndev);
2491 /* Packet transmit function */
2492 static netdev_tx_t sh_eth_start_xmit(struct sk_buff *skb,
2493 struct net_device *ndev)
2495 struct sh_eth_private *mdp = netdev_priv(ndev);
2496 struct sh_eth_txdesc *txdesc;
2497 dma_addr_t dma_addr;
2499 unsigned long flags;
2501 spin_lock_irqsave(&mdp->lock, flags);
2502 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2503 if (!sh_eth_tx_free(ndev, true)) {
2504 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2505 netif_stop_queue(ndev);
2506 spin_unlock_irqrestore(&mdp->lock, flags);
2507 return NETDEV_TX_BUSY;
2510 spin_unlock_irqrestore(&mdp->lock, flags);
2512 if (skb_put_padto(skb, ETH_ZLEN))
2513 return NETDEV_TX_OK;
2515 entry = mdp->cur_tx % mdp->num_tx_ring;
2516 mdp->tx_skbuff[entry] = skb;
2517 txdesc = &mdp->tx_ring[entry];
2519 if (!mdp->cd->hw_swap)
2520 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2521 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len,
2523 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
2525 return NETDEV_TX_OK;
2527 txdesc->addr = cpu_to_le32(dma_addr);
2528 txdesc->len = cpu_to_le32(skb->len << 16);
2530 dma_wmb(); /* TACT bit must be set after all the above writes */
2531 if (entry >= mdp->num_tx_ring - 1)
2532 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2534 txdesc->status |= cpu_to_le32(TD_TACT);
2538 if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns))
2539 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
2541 return NETDEV_TX_OK;
2544 /* The statistics registers have write-clear behaviour, which means we
2545 * will lose any increment between the read and write. We mitigate
2546 * this by only clearing when we read a non-zero value, so we will
2547 * never falsely report a total of zero.
2550 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2552 u32 delta = sh_eth_read(ndev, reg);
2556 sh_eth_write(ndev, 0, reg);
2560 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2562 struct sh_eth_private *mdp = netdev_priv(ndev);
2564 if (mdp->cd->no_tx_cntrs)
2565 return &ndev->stats;
2567 if (!mdp->is_opened)
2568 return &ndev->stats;
2570 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2571 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2572 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2574 if (mdp->cd->cexcr) {
2575 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2577 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2580 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2584 return &ndev->stats;
2587 /* device close function */
2588 static int sh_eth_close(struct net_device *ndev)
2590 struct sh_eth_private *mdp = netdev_priv(ndev);
2592 netif_stop_queue(ndev);
2594 /* Serialise with the interrupt handler and NAPI, then disable
2595 * interrupts. We have to clear the irq_enabled flag first to
2596 * ensure that interrupts won't be re-enabled.
2598 mdp->irq_enabled = false;
2599 synchronize_irq(ndev->irq);
2600 napi_disable(&mdp->napi);
2601 sh_eth_write(ndev, 0x0000, EESIPR);
2603 sh_eth_dev_exit(ndev);
2605 /* PHY Disconnect */
2607 phy_stop(ndev->phydev);
2608 phy_disconnect(ndev->phydev);
2611 free_irq(ndev->irq, ndev);
2613 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2614 sh_eth_ring_free(ndev);
2618 pm_runtime_put(&mdp->pdev->dev);
2623 static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu)
2625 if (netif_running(ndev))
2628 ndev->mtu = new_mtu;
2629 netdev_update_features(ndev);
2634 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2635 static u32 sh_eth_tsu_get_post_mask(int entry)
2637 return 0x0f << (28 - ((entry % 8) * 4));
2640 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2642 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2645 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2648 struct sh_eth_private *mdp = netdev_priv(ndev);
2649 int reg = TSU_POST1 + entry / 8;
2652 tmp = sh_eth_tsu_read(mdp, reg);
2653 sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg);
2656 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2659 struct sh_eth_private *mdp = netdev_priv(ndev);
2660 int reg = TSU_POST1 + entry / 8;
2661 u32 post_mask, ref_mask, tmp;
2663 post_mask = sh_eth_tsu_get_post_mask(entry);
2664 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2666 tmp = sh_eth_tsu_read(mdp, reg);
2667 sh_eth_tsu_write(mdp, tmp & ~post_mask, reg);
2669 /* If other port enables, the function returns "true" */
2670 return tmp & ref_mask;
2673 static int sh_eth_tsu_busy(struct net_device *ndev)
2675 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2676 struct sh_eth_private *mdp = netdev_priv(ndev);
2678 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2682 netdev_err(ndev, "%s: timeout\n", __func__);
2690 static int sh_eth_tsu_write_entry(struct net_device *ndev, u16 offset,
2693 struct sh_eth_private *mdp = netdev_priv(ndev);
2696 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2697 iowrite32(val, mdp->tsu_addr + offset);
2698 if (sh_eth_tsu_busy(ndev) < 0)
2701 val = addr[4] << 8 | addr[5];
2702 iowrite32(val, mdp->tsu_addr + offset + 4);
2703 if (sh_eth_tsu_busy(ndev) < 0)
2709 static void sh_eth_tsu_read_entry(struct net_device *ndev, u16 offset, u8 *addr)
2711 struct sh_eth_private *mdp = netdev_priv(ndev);
2714 val = ioread32(mdp->tsu_addr + offset);
2715 addr[0] = (val >> 24) & 0xff;
2716 addr[1] = (val >> 16) & 0xff;
2717 addr[2] = (val >> 8) & 0xff;
2718 addr[3] = val & 0xff;
2719 val = ioread32(mdp->tsu_addr + offset + 4);
2720 addr[4] = (val >> 8) & 0xff;
2721 addr[5] = val & 0xff;
2725 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2727 struct sh_eth_private *mdp = netdev_priv(ndev);
2728 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2730 u8 c_addr[ETH_ALEN];
2732 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2733 sh_eth_tsu_read_entry(ndev, reg_offset, c_addr);
2734 if (ether_addr_equal(addr, c_addr))
2741 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2746 memset(blank, 0, sizeof(blank));
2747 entry = sh_eth_tsu_find_entry(ndev, blank);
2748 return (entry < 0) ? -ENOMEM : entry;
2751 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2754 struct sh_eth_private *mdp = netdev_priv(ndev);
2755 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2759 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2760 ~(1 << (31 - entry)), TSU_TEN);
2762 memset(blank, 0, sizeof(blank));
2763 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2769 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2771 struct sh_eth_private *mdp = netdev_priv(ndev);
2772 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2778 i = sh_eth_tsu_find_entry(ndev, addr);
2780 /* No entry found, create one */
2781 i = sh_eth_tsu_find_empty(ndev);
2784 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2788 /* Enable the entry */
2789 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2790 (1 << (31 - i)), TSU_TEN);
2793 /* Entry found or created, enable POST */
2794 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2799 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2801 struct sh_eth_private *mdp = netdev_priv(ndev);
2807 i = sh_eth_tsu_find_entry(ndev, addr);
2810 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2813 /* Disable the entry if both ports was disabled */
2814 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2822 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2824 struct sh_eth_private *mdp = netdev_priv(ndev);
2830 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2831 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2834 /* Disable the entry if both ports was disabled */
2835 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2843 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2845 struct sh_eth_private *mdp = netdev_priv(ndev);
2846 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2853 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2854 sh_eth_tsu_read_entry(ndev, reg_offset, addr);
2855 if (is_multicast_ether_addr(addr))
2856 sh_eth_tsu_del_entry(ndev, addr);
2860 /* Update promiscuous flag and multicast filter */
2861 static void sh_eth_set_rx_mode(struct net_device *ndev)
2863 struct sh_eth_private *mdp = netdev_priv(ndev);
2866 unsigned long flags;
2868 spin_lock_irqsave(&mdp->lock, flags);
2869 /* Initial condition is MCT = 1, PRM = 0.
2870 * Depending on ndev->flags, set PRM or clear MCT
2872 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2874 ecmr_bits |= ECMR_MCT;
2876 if (!(ndev->flags & IFF_MULTICAST)) {
2877 sh_eth_tsu_purge_mcast(ndev);
2880 if (ndev->flags & IFF_ALLMULTI) {
2881 sh_eth_tsu_purge_mcast(ndev);
2882 ecmr_bits &= ~ECMR_MCT;
2886 if (ndev->flags & IFF_PROMISC) {
2887 sh_eth_tsu_purge_all(ndev);
2888 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2889 } else if (mdp->cd->tsu) {
2890 struct netdev_hw_addr *ha;
2891 netdev_for_each_mc_addr(ha, ndev) {
2892 if (mcast_all && is_multicast_ether_addr(ha->addr))
2895 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2897 sh_eth_tsu_purge_mcast(ndev);
2898 ecmr_bits &= ~ECMR_MCT;
2905 /* update the ethernet mode */
2906 sh_eth_write(ndev, ecmr_bits, ECMR);
2908 spin_unlock_irqrestore(&mdp->lock, flags);
2911 static void sh_eth_set_rx_csum(struct net_device *ndev, bool enable)
2913 struct sh_eth_private *mdp = netdev_priv(ndev);
2914 unsigned long flags;
2916 spin_lock_irqsave(&mdp->lock, flags);
2918 /* Disable TX and RX */
2919 sh_eth_rcv_snd_disable(ndev);
2921 /* Modify RX Checksum setting */
2922 sh_eth_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
2924 /* Enable TX and RX */
2925 sh_eth_rcv_snd_enable(ndev);
2927 spin_unlock_irqrestore(&mdp->lock, flags);
2930 static int sh_eth_set_features(struct net_device *ndev,
2931 netdev_features_t features)
2933 netdev_features_t changed = ndev->features ^ features;
2934 struct sh_eth_private *mdp = netdev_priv(ndev);
2936 if (changed & NETIF_F_RXCSUM && mdp->cd->rx_csum)
2937 sh_eth_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
2939 ndev->features = features;
2944 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2952 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2953 __be16 proto, u16 vid)
2955 struct sh_eth_private *mdp = netdev_priv(ndev);
2956 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2958 if (unlikely(!mdp->cd->tsu))
2961 /* No filtering if vid = 0 */
2965 mdp->vlan_num_ids++;
2967 /* The controller has one VLAN tag HW filter. So, if the filter is
2968 * already enabled, the driver disables it and the filte
2970 if (mdp->vlan_num_ids > 1) {
2971 /* disable VLAN filter */
2972 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2976 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2982 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2983 __be16 proto, u16 vid)
2985 struct sh_eth_private *mdp = netdev_priv(ndev);
2986 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2988 if (unlikely(!mdp->cd->tsu))
2991 /* No filtering if vid = 0 */
2995 mdp->vlan_num_ids--;
2996 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
3001 /* SuperH's TSU register init function */
3002 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
3004 if (!mdp->cd->dual_port) {
3005 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
3006 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
3007 TSU_FWSLC); /* Enable POST registers */
3011 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
3012 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
3013 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
3014 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
3015 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
3016 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
3017 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
3018 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
3019 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
3020 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
3021 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
3022 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
3023 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
3024 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
3025 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
3026 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
3027 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
3028 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
3029 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
3032 /* MDIO bus release function */
3033 static int sh_mdio_release(struct sh_eth_private *mdp)
3035 /* unregister mdio bus */
3036 mdiobus_unregister(mdp->mii_bus);
3038 /* free bitbang info */
3039 free_mdio_bitbang(mdp->mii_bus);
3044 static int sh_mdiobb_read(struct mii_bus *bus, int phy, int reg)
3048 pm_runtime_get_sync(bus->parent);
3049 res = mdiobb_read(bus, phy, reg);
3050 pm_runtime_put(bus->parent);
3055 static int sh_mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val)
3059 pm_runtime_get_sync(bus->parent);
3060 res = mdiobb_write(bus, phy, reg, val);
3061 pm_runtime_put(bus->parent);
3066 /* MDIO bus init function */
3067 static int sh_mdio_init(struct sh_eth_private *mdp,
3068 struct sh_eth_plat_data *pd)
3071 struct bb_info *bitbang;
3072 struct platform_device *pdev = mdp->pdev;
3073 struct device *dev = &mdp->pdev->dev;
3075 /* create bit control struct for PHY */
3076 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
3081 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
3082 bitbang->set_gate = pd->set_mdio_gate;
3083 bitbang->ctrl.ops = &bb_ops;
3085 /* MII controller setting */
3086 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
3090 /* Wrap accessors with Runtime PM-aware ops */
3091 mdp->mii_bus->read = sh_mdiobb_read;
3092 mdp->mii_bus->write = sh_mdiobb_write;
3094 /* Hook up MII support for ethtool */
3095 mdp->mii_bus->name = "sh_mii";
3096 mdp->mii_bus->parent = dev;
3097 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
3098 pdev->name, pdev->id);
3100 /* register MDIO bus */
3101 if (pd->phy_irq > 0)
3102 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
3104 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
3111 free_mdio_bitbang(mdp->mii_bus);
3115 static const u16 *sh_eth_get_register_offset(int register_type)
3117 const u16 *reg_offset = NULL;
3119 switch (register_type) {
3120 case SH_ETH_REG_GIGABIT:
3121 reg_offset = sh_eth_offset_gigabit;
3123 case SH_ETH_REG_FAST_RCAR:
3124 reg_offset = sh_eth_offset_fast_rcar;
3126 case SH_ETH_REG_FAST_SH4:
3127 reg_offset = sh_eth_offset_fast_sh4;
3129 case SH_ETH_REG_FAST_SH3_SH2:
3130 reg_offset = sh_eth_offset_fast_sh3_sh2;
3137 static const struct net_device_ops sh_eth_netdev_ops = {
3138 .ndo_open = sh_eth_open,
3139 .ndo_stop = sh_eth_close,
3140 .ndo_start_xmit = sh_eth_start_xmit,
3141 .ndo_get_stats = sh_eth_get_stats,
3142 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3143 .ndo_tx_timeout = sh_eth_tx_timeout,
3144 .ndo_do_ioctl = phy_do_ioctl_running,
3145 .ndo_change_mtu = sh_eth_change_mtu,
3146 .ndo_validate_addr = eth_validate_addr,
3147 .ndo_set_mac_address = eth_mac_addr,
3148 .ndo_set_features = sh_eth_set_features,
3151 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3152 .ndo_open = sh_eth_open,
3153 .ndo_stop = sh_eth_close,
3154 .ndo_start_xmit = sh_eth_start_xmit,
3155 .ndo_get_stats = sh_eth_get_stats,
3156 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3157 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
3158 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
3159 .ndo_tx_timeout = sh_eth_tx_timeout,
3160 .ndo_do_ioctl = phy_do_ioctl_running,
3161 .ndo_change_mtu = sh_eth_change_mtu,
3162 .ndo_validate_addr = eth_validate_addr,
3163 .ndo_set_mac_address = eth_mac_addr,
3164 .ndo_set_features = sh_eth_set_features,
3168 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3170 struct device_node *np = dev->of_node;
3171 struct sh_eth_plat_data *pdata;
3172 phy_interface_t interface;
3175 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3179 ret = of_get_phy_mode(np, &interface);
3182 pdata->phy_interface = interface;
3184 of_get_mac_address(np, pdata->mac_addr);
3186 pdata->no_ether_link =
3187 of_property_read_bool(np, "renesas,no-ether-link");
3188 pdata->ether_link_active_low =
3189 of_property_read_bool(np, "renesas,ether-link-active-low");
3194 static const struct of_device_id sh_eth_match_table[] = {
3195 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3196 { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data },
3197 { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data },
3198 { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data },
3199 { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data },
3200 { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data },
3201 { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data },
3202 { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data },
3203 { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data },
3204 { .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data },
3205 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3206 { .compatible = "renesas,ether-r7s9210", .data = &r7s9210_data },
3207 { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data },
3208 { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data },
3211 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3213 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3219 static int sh_eth_drv_probe(struct platform_device *pdev)
3221 struct resource *res;
3222 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3223 const struct platform_device_id *id = platform_get_device_id(pdev);
3224 struct sh_eth_private *mdp;
3225 struct net_device *ndev;
3229 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3231 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3235 pm_runtime_enable(&pdev->dev);
3236 pm_runtime_get_sync(&pdev->dev);
3238 ret = platform_get_irq(pdev, 0);
3243 SET_NETDEV_DEV(ndev, &pdev->dev);
3245 mdp = netdev_priv(ndev);
3246 mdp->num_tx_ring = TX_RING_SIZE;
3247 mdp->num_rx_ring = RX_RING_SIZE;
3248 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3249 if (IS_ERR(mdp->addr)) {
3250 ret = PTR_ERR(mdp->addr);
3254 ndev->base_addr = res->start;
3256 spin_lock_init(&mdp->lock);
3259 if (pdev->dev.of_node)
3260 pd = sh_eth_parse_dt(&pdev->dev);
3262 dev_err(&pdev->dev, "no platform data\n");
3268 mdp->phy_id = pd->phy;
3269 mdp->phy_interface = pd->phy_interface;
3270 mdp->no_ether_link = pd->no_ether_link;
3271 mdp->ether_link_active_low = pd->ether_link_active_low;
3275 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3277 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3279 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3280 if (!mdp->reg_offset) {
3281 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3282 mdp->cd->register_type);
3286 sh_eth_set_default_cpu_data(mdp->cd);
3288 /* User's manual states max MTU should be 2048 but due to the
3289 * alignment calculations in sh_eth_ring_init() the practical
3290 * MTU is a bit less. Maybe this can be optimized some more.
3292 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
3293 ndev->min_mtu = ETH_MIN_MTU;
3295 if (mdp->cd->rx_csum) {
3296 ndev->features = NETIF_F_RXCSUM;
3297 ndev->hw_features = NETIF_F_RXCSUM;
3302 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3304 ndev->netdev_ops = &sh_eth_netdev_ops;
3305 ndev->ethtool_ops = &sh_eth_ethtool_ops;
3306 ndev->watchdog_timeo = TX_TIMEOUT;
3308 /* debug message level */
3309 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3311 /* read and set MAC address */
3312 read_mac_address(ndev, pd->mac_addr);
3313 if (!is_valid_ether_addr(ndev->dev_addr)) {
3314 dev_warn(&pdev->dev,
3315 "no valid MAC address supplied, using a random one.\n");
3316 eth_hw_addr_random(ndev);
3320 int port = pdev->id < 0 ? 0 : pdev->id % 2;
3321 struct resource *rtsu;
3323 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3325 dev_err(&pdev->dev, "no TSU resource\n");
3329 /* We can only request the TSU region for the first port
3330 * of the two sharing this TSU for the probe to succeed...
3333 !devm_request_mem_region(&pdev->dev, rtsu->start,
3334 resource_size(rtsu),
3335 dev_name(&pdev->dev))) {
3336 dev_err(&pdev->dev, "can't request TSU resource.\n");
3340 /* ioremap the TSU registers */
3341 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start,
3342 resource_size(rtsu));
3343 if (!mdp->tsu_addr) {
3344 dev_err(&pdev->dev, "TSU region ioremap() failed.\n");
3349 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3351 /* Need to init only the first port of the two sharing a TSU */
3353 if (mdp->cd->chip_reset)
3354 mdp->cd->chip_reset(ndev);
3356 /* TSU init (Init only)*/
3357 sh_eth_tsu_init(mdp);
3361 if (mdp->cd->rmiimode)
3362 sh_eth_write(ndev, 0x1, RMIIMODE);
3365 ret = sh_mdio_init(mdp, pd);
3367 if (ret != -EPROBE_DEFER)
3368 dev_err(&pdev->dev, "MDIO init failed: %d\n", ret);
3372 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3374 /* network device register */
3375 ret = register_netdev(ndev);
3380 device_set_wakeup_capable(&pdev->dev, 1);
3382 /* print device information */
3383 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3384 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3386 pm_runtime_put(&pdev->dev);
3387 platform_set_drvdata(pdev, ndev);
3392 netif_napi_del(&mdp->napi);
3393 sh_mdio_release(mdp);
3399 pm_runtime_put(&pdev->dev);
3400 pm_runtime_disable(&pdev->dev);
3404 static int sh_eth_drv_remove(struct platform_device *pdev)
3406 struct net_device *ndev = platform_get_drvdata(pdev);
3407 struct sh_eth_private *mdp = netdev_priv(ndev);
3409 unregister_netdev(ndev);
3410 netif_napi_del(&mdp->napi);
3411 sh_mdio_release(mdp);
3412 pm_runtime_disable(&pdev->dev);
3419 #ifdef CONFIG_PM_SLEEP
3420 static int sh_eth_wol_setup(struct net_device *ndev)
3422 struct sh_eth_private *mdp = netdev_priv(ndev);
3424 /* Only allow ECI interrupts */
3425 synchronize_irq(ndev->irq);
3426 napi_disable(&mdp->napi);
3427 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);
3429 /* Enable MagicPacket */
3430 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
3432 return enable_irq_wake(ndev->irq);
3435 static int sh_eth_wol_restore(struct net_device *ndev)
3437 struct sh_eth_private *mdp = netdev_priv(ndev);
3440 napi_enable(&mdp->napi);
3442 /* Disable MagicPacket */
3443 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0);
3445 /* The device needs to be reset to restore MagicPacket logic
3446 * for next wakeup. If we close and open the device it will
3447 * both be reset and all registers restored. This is what
3448 * happens during suspend and resume without WoL enabled.
3450 ret = sh_eth_close(ndev);
3453 ret = sh_eth_open(ndev);
3457 return disable_irq_wake(ndev->irq);
3460 static int sh_eth_suspend(struct device *dev)
3462 struct net_device *ndev = dev_get_drvdata(dev);
3463 struct sh_eth_private *mdp = netdev_priv(ndev);
3466 if (!netif_running(ndev))
3469 netif_device_detach(ndev);
3471 if (mdp->wol_enabled)
3472 ret = sh_eth_wol_setup(ndev);
3474 ret = sh_eth_close(ndev);
3479 static int sh_eth_resume(struct device *dev)
3481 struct net_device *ndev = dev_get_drvdata(dev);
3482 struct sh_eth_private *mdp = netdev_priv(ndev);
3485 if (!netif_running(ndev))
3488 if (mdp->wol_enabled)
3489 ret = sh_eth_wol_restore(ndev);
3491 ret = sh_eth_open(ndev);
3496 netif_device_attach(ndev);
3502 static int sh_eth_runtime_nop(struct device *dev)
3504 /* Runtime PM callback shared between ->runtime_suspend()
3505 * and ->runtime_resume(). Simply returns success.
3507 * This driver re-initializes all registers after
3508 * pm_runtime_get_sync() anyway so there is no need
3509 * to save and restore registers here.
3514 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3515 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3516 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3518 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3520 #define SH_ETH_PM_OPS NULL
3523 static const struct platform_device_id sh_eth_id_table[] = {
3524 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3525 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3526 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3527 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3528 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3529 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3530 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3533 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3535 static struct platform_driver sh_eth_driver = {
3536 .probe = sh_eth_drv_probe,
3537 .remove = sh_eth_drv_remove,
3538 .id_table = sh_eth_id_table,
3541 .pm = SH_ETH_PM_OPS,
3542 .of_match_table = of_match_ptr(sh_eth_match_table),
3546 module_platform_driver(sh_eth_driver);
3548 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3549 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3550 MODULE_LICENSE("GPL v2");