1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 /* QLogic qede NIC Driver
3 * Copyright (c) 2015-2017 QLogic Corporation
7 #define QEDE_PTP_TX_TIMEOUT (2 * HZ)
10 const struct qed_eth_ptp_ops *ops;
11 struct ptp_clock_info clock_info;
12 struct cyclecounter cc;
13 struct timecounter tc;
14 struct ptp_clock *clock;
15 struct work_struct work;
16 unsigned long ptp_tx_start;
17 struct qede_dev *edev;
18 struct sk_buff *tx_skb;
20 /* ptp spinlock is used for protecting the cycle/time counter fields
21 * and, also for serializing the qed PTP API invocations.
24 bool hw_ts_ioctl_called;
31 * @ptp: the ptp clock structure
32 * @ppb: parts per billion adjustment from base
34 * Adjust the frequency of the ptp cycle counter by the
35 * indicated ppb from the base frequency.
37 static int qede_ptp_adjfreq(struct ptp_clock_info *info, s32 ppb)
39 struct qede_ptp *ptp = container_of(info, struct qede_ptp, clock_info);
40 struct qede_dev *edev = ptp->edev;
44 if (edev->state == QEDE_STATE_OPEN) {
45 spin_lock_bh(&ptp->lock);
46 rc = ptp->ops->adjfreq(edev->cdev, ppb);
47 spin_unlock_bh(&ptp->lock);
49 DP_ERR(edev, "PTP adjfreq called while interface is down\n");
57 static int qede_ptp_adjtime(struct ptp_clock_info *info, s64 delta)
59 struct qede_dev *edev;
62 ptp = container_of(info, struct qede_ptp, clock_info);
65 DP_VERBOSE(edev, QED_MSG_DEBUG, "PTP adjtime called, delta = %llx\n",
68 spin_lock_bh(&ptp->lock);
69 timecounter_adjtime(&ptp->tc, delta);
70 spin_unlock_bh(&ptp->lock);
75 static int qede_ptp_gettime(struct ptp_clock_info *info, struct timespec64 *ts)
77 struct qede_dev *edev;
81 ptp = container_of(info, struct qede_ptp, clock_info);
84 spin_lock_bh(&ptp->lock);
85 ns = timecounter_read(&ptp->tc);
86 spin_unlock_bh(&ptp->lock);
88 DP_VERBOSE(edev, QED_MSG_DEBUG, "PTP gettime called, ns = %llu\n", ns);
90 *ts = ns_to_timespec64(ns);
95 static int qede_ptp_settime(struct ptp_clock_info *info,
96 const struct timespec64 *ts)
98 struct qede_dev *edev;
102 ptp = container_of(info, struct qede_ptp, clock_info);
105 ns = timespec64_to_ns(ts);
107 DP_VERBOSE(edev, QED_MSG_DEBUG, "PTP settime called, ns = %llu\n", ns);
109 /* Re-init the timecounter */
110 spin_lock_bh(&ptp->lock);
111 timecounter_init(&ptp->tc, &ptp->cc, ns);
112 spin_unlock_bh(&ptp->lock);
117 /* Enable (or disable) ancillary features of the phc subsystem */
118 static int qede_ptp_ancillary_feature_enable(struct ptp_clock_info *info,
119 struct ptp_clock_request *rq,
122 struct qede_dev *edev;
123 struct qede_ptp *ptp;
125 ptp = container_of(info, struct qede_ptp, clock_info);
128 DP_ERR(edev, "PHC ancillary features are not supported\n");
133 static void qede_ptp_task(struct work_struct *work)
135 struct skb_shared_hwtstamps shhwtstamps;
136 struct qede_dev *edev;
137 struct qede_ptp *ptp;
142 ptp = container_of(work, struct qede_ptp, work);
144 timedout = time_is_before_jiffies(ptp->ptp_tx_start +
145 QEDE_PTP_TX_TIMEOUT);
147 /* Read Tx timestamp registers */
148 spin_lock_bh(&ptp->lock);
149 rc = ptp->ops->read_tx_ts(edev->cdev, ×tamp);
150 spin_unlock_bh(&ptp->lock);
152 if (unlikely(timedout)) {
153 DP_INFO(edev, "Tx timestamp is not recorded\n");
154 dev_kfree_skb_any(ptp->tx_skb);
156 clear_bit_unlock(QEDE_FLAGS_PTP_TX_IN_PRORGESS,
158 edev->ptp_skip_txts++;
160 /* Reschedule to keep checking for a valid TS value */
161 schedule_work(&ptp->work);
166 ns = timecounter_cyc2time(&ptp->tc, timestamp);
167 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
168 shhwtstamps.hwtstamp = ns_to_ktime(ns);
169 skb_tstamp_tx(ptp->tx_skb, &shhwtstamps);
170 dev_kfree_skb_any(ptp->tx_skb);
172 clear_bit_unlock(QEDE_FLAGS_PTP_TX_IN_PRORGESS, &edev->flags);
174 DP_VERBOSE(edev, QED_MSG_DEBUG,
175 "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
179 /* Read the PHC. This API is invoked with ptp_lock held. */
180 static u64 qede_ptp_read_cc(const struct cyclecounter *cc)
182 struct qede_dev *edev;
183 struct qede_ptp *ptp;
187 ptp = container_of(cc, struct qede_ptp, cc);
189 rc = ptp->ops->read_cc(edev->cdev, &phc_cycles);
191 WARN_ONCE(1, "PHC read err %d\n", rc);
193 DP_VERBOSE(edev, QED_MSG_DEBUG, "PHC read cycles = %llu\n", phc_cycles);
198 static int qede_ptp_cfg_filters(struct qede_dev *edev)
200 enum qed_ptp_hwtstamp_tx_type tx_type = QED_PTP_HWTSTAMP_TX_ON;
201 enum qed_ptp_filter_type rx_filter = QED_PTP_FILTER_NONE;
202 struct qede_ptp *ptp = edev->ptp;
207 if (!ptp->hw_ts_ioctl_called) {
208 DP_INFO(edev, "TS IOCTL not called\n");
212 switch (ptp->tx_type) {
214 set_bit(QEDE_FLAGS_TX_TIMESTAMPING_EN, &edev->flags);
215 tx_type = QED_PTP_HWTSTAMP_TX_ON;
218 case HWTSTAMP_TX_OFF:
219 clear_bit(QEDE_FLAGS_TX_TIMESTAMPING_EN, &edev->flags);
220 tx_type = QED_PTP_HWTSTAMP_TX_OFF;
223 case HWTSTAMP_TX_ONESTEP_SYNC:
224 case HWTSTAMP_TX_ONESTEP_P2P:
225 DP_ERR(edev, "One-step timestamping is not supported\n");
229 spin_lock_bh(&ptp->lock);
230 switch (ptp->rx_filter) {
231 case HWTSTAMP_FILTER_NONE:
232 rx_filter = QED_PTP_FILTER_NONE;
234 case HWTSTAMP_FILTER_ALL:
235 case HWTSTAMP_FILTER_SOME:
236 case HWTSTAMP_FILTER_NTP_ALL:
237 ptp->rx_filter = HWTSTAMP_FILTER_NONE;
238 rx_filter = QED_PTP_FILTER_ALL;
240 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
241 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
242 rx_filter = QED_PTP_FILTER_V1_L4_EVENT;
244 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
245 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
246 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
247 /* Initialize PTP detection for UDP/IPv4 events */
248 rx_filter = QED_PTP_FILTER_V1_L4_GEN;
250 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
251 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
252 rx_filter = QED_PTP_FILTER_V2_L4_EVENT;
254 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
255 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
256 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
257 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
258 rx_filter = QED_PTP_FILTER_V2_L4_GEN;
260 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
261 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
262 rx_filter = QED_PTP_FILTER_V2_L2_EVENT;
264 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
265 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
266 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
267 /* Initialize PTP detection L2 events */
268 rx_filter = QED_PTP_FILTER_V2_L2_GEN;
270 case HWTSTAMP_FILTER_PTP_V2_EVENT:
271 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
272 rx_filter = QED_PTP_FILTER_V2_EVENT;
274 case HWTSTAMP_FILTER_PTP_V2_SYNC:
275 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
276 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
277 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
278 rx_filter = QED_PTP_FILTER_V2_GEN;
282 ptp->ops->cfg_filters(edev->cdev, rx_filter, tx_type);
284 spin_unlock_bh(&ptp->lock);
289 int qede_ptp_hw_ts(struct qede_dev *edev, struct ifreq *ifr)
291 struct hwtstamp_config config;
292 struct qede_ptp *ptp;
299 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
302 DP_VERBOSE(edev, QED_MSG_DEBUG,
303 "HWTSTAMP IOCTL: Requested tx_type = %d, requested rx_filters = %d\n",
304 config.tx_type, config.rx_filter);
307 DP_ERR(edev, "config.flags is reserved for future use\n");
311 ptp->hw_ts_ioctl_called = 1;
312 ptp->tx_type = config.tx_type;
313 ptp->rx_filter = config.rx_filter;
315 rc = qede_ptp_cfg_filters(edev);
319 config.rx_filter = ptp->rx_filter;
321 return copy_to_user(ifr->ifr_data, &config,
322 sizeof(config)) ? -EFAULT : 0;
325 int qede_ptp_get_ts_info(struct qede_dev *edev, struct ethtool_ts_info *info)
327 struct qede_ptp *ptp = edev->ptp;
330 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
331 SOF_TIMESTAMPING_RX_SOFTWARE |
332 SOF_TIMESTAMPING_SOFTWARE;
333 info->phc_index = -1;
338 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
339 SOF_TIMESTAMPING_RX_SOFTWARE |
340 SOF_TIMESTAMPING_SOFTWARE |
341 SOF_TIMESTAMPING_TX_HARDWARE |
342 SOF_TIMESTAMPING_RX_HARDWARE |
343 SOF_TIMESTAMPING_RAW_HARDWARE;
346 info->phc_index = ptp_clock_index(ptp->clock);
348 info->phc_index = -1;
350 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
351 BIT(HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
352 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
353 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
354 BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
355 BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
356 BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
357 BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
358 BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
359 BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
360 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) |
361 BIT(HWTSTAMP_FILTER_PTP_V2_SYNC) |
362 BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ);
364 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON);
369 void qede_ptp_disable(struct qede_dev *edev)
371 struct qede_ptp *ptp;
378 ptp_clock_unregister(ptp->clock);
382 /* Cancel PTP work queue. Should be done after the Tx queues are
383 * drained to prevent additional scheduling.
385 cancel_work_sync(&ptp->work);
387 dev_kfree_skb_any(ptp->tx_skb);
389 clear_bit_unlock(QEDE_FLAGS_PTP_TX_IN_PRORGESS, &edev->flags);
392 /* Disable PTP in HW */
393 spin_lock_bh(&ptp->lock);
394 ptp->ops->disable(edev->cdev);
395 spin_unlock_bh(&ptp->lock);
401 static int qede_ptp_init(struct qede_dev *edev)
403 struct qede_ptp *ptp;
410 spin_lock_init(&ptp->lock);
412 /* Configure PTP in HW */
413 rc = ptp->ops->enable(edev->cdev);
415 DP_INFO(edev, "PTP HW enable failed\n");
419 /* Init work queue for Tx timestamping */
420 INIT_WORK(&ptp->work, qede_ptp_task);
422 /* Init cyclecounter and timecounter */
423 memset(&ptp->cc, 0, sizeof(ptp->cc));
424 ptp->cc.read = qede_ptp_read_cc;
425 ptp->cc.mask = CYCLECOUNTER_MASK(64);
429 timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real()));
434 int qede_ptp_enable(struct qede_dev *edev)
436 struct qede_ptp *ptp;
439 ptp = kzalloc(sizeof(*ptp), GFP_KERNEL);
441 DP_INFO(edev, "Failed to allocate struct for PTP\n");
446 ptp->ops = edev->ops->ptp;
448 DP_INFO(edev, "PTP enable failed\n");
455 rc = qede_ptp_init(edev);
459 qede_ptp_cfg_filters(edev);
461 /* Fill the ptp_clock_info struct and register PTP clock */
462 ptp->clock_info.owner = THIS_MODULE;
463 snprintf(ptp->clock_info.name, 16, "%s", edev->ndev->name);
464 ptp->clock_info.max_adj = QED_MAX_PHC_DRIFT_PPB;
465 ptp->clock_info.n_alarm = 0;
466 ptp->clock_info.n_ext_ts = 0;
467 ptp->clock_info.n_per_out = 0;
468 ptp->clock_info.pps = 0;
469 ptp->clock_info.adjfreq = qede_ptp_adjfreq;
470 ptp->clock_info.adjtime = qede_ptp_adjtime;
471 ptp->clock_info.gettime64 = qede_ptp_gettime;
472 ptp->clock_info.settime64 = qede_ptp_settime;
473 ptp->clock_info.enable = qede_ptp_ancillary_feature_enable;
475 ptp->clock = ptp_clock_register(&ptp->clock_info, &edev->pdev->dev);
476 if (IS_ERR(ptp->clock)) {
477 DP_ERR(edev, "PTP clock registration failed\n");
478 qede_ptp_disable(edev);
493 void qede_ptp_tx_ts(struct qede_dev *edev, struct sk_buff *skb)
495 struct qede_ptp *ptp;
501 if (test_and_set_bit_lock(QEDE_FLAGS_PTP_TX_IN_PRORGESS,
503 DP_ERR(edev, "Timestamping in progress\n");
504 edev->ptp_skip_txts++;
508 if (unlikely(!test_bit(QEDE_FLAGS_TX_TIMESTAMPING_EN, &edev->flags))) {
510 "Tx timestamping was not enabled, this packet will not be timestamped\n");
511 clear_bit_unlock(QEDE_FLAGS_PTP_TX_IN_PRORGESS, &edev->flags);
512 edev->ptp_skip_txts++;
513 } else if (unlikely(ptp->tx_skb)) {
515 "The device supports only a single outstanding packet to timestamp, this packet will not be timestamped\n");
516 clear_bit_unlock(QEDE_FLAGS_PTP_TX_IN_PRORGESS, &edev->flags);
517 edev->ptp_skip_txts++;
519 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
520 /* schedule check for Tx timestamp */
521 ptp->tx_skb = skb_get(skb);
522 ptp->ptp_tx_start = jiffies;
523 schedule_work(&ptp->work);
527 void qede_ptp_rx_ts(struct qede_dev *edev, struct sk_buff *skb)
529 struct qede_ptp *ptp;
537 spin_lock_bh(&ptp->lock);
538 rc = ptp->ops->read_rx_ts(edev->cdev, ×tamp);
540 spin_unlock_bh(&ptp->lock);
541 DP_INFO(edev, "Invalid Rx timestamp\n");
545 ns = timecounter_cyc2time(&ptp->tc, timestamp);
546 spin_unlock_bh(&ptp->lock);
547 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
548 DP_VERBOSE(edev, QED_MSG_DEBUG,
549 "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",