drivers/net/ethernet/qlogic/qed/qed_mcp.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/types.h>
  34 #include <asm/byteorder.h>
  35 #include <linux/delay.h>
  36 #include <linux/errno.h>
  37 #include <linux/kernel.h>
  38 #include <linux/slab.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/string.h>
  41 #include <linux/etherdevice.h>
  42 #include "qed.h"
  43 #include "qed_cxt.h"
  44 #include "qed_dcbx.h"
  45 #include "qed_hsi.h"
  46 #include "qed_hw.h"
  47 #include "qed_mcp.h"
  48 #include "qed_reg_addr.h"
  49 #include "qed_sriov.h"
  50
  51 #define GRCBASE_MCP     0xe00000
  52
  53 #define QED_MCP_RESP_ITER_US    10
  54
  55 #define QED_DRV_MB_MAX_RETRIES  (500 * 1000)    /* Account for 5 sec */
  56 #define QED_MCP_RESET_RETRIES   (50 * 1000)     /* Account for 500 msec */
  57
  58 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val)           \
  59         qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
  60                _val)
  61
  62 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
  63         qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
  64
  65 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val)  \
  66         DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
  67                      offsetof(struct public_drv_mb, _field), _val)
  68
  69 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field)         \
  70         DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
  71                      offsetof(struct public_drv_mb, _field))
  72
  73 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
  74                   DRV_ID_PDA_COMP_VER_SHIFT)
  75
  76 #define MCP_BYTES_PER_MBIT_SHIFT 17
  77
  78 bool qed_mcp_is_init(struct qed_hwfn *p_hwfn)
  79 {
  80         if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
  81                 return false;
  82         return true;
  83 }
  84
  85 void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
  86 {
  87         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
  88                                         PUBLIC_PORT);
  89         u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr);
  90
  91         p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
  92                                                    MFW_PORT(p_hwfn));
  93         DP_VERBOSE(p_hwfn, QED_MSG_SP,
  94                    "port_addr = 0x%x, port_id 0x%02x\n",
  95                    p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
  96 }
  97
  98 void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
  99 {
 100         u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
 101         u32 tmp, i;
 102
 103         if (!p_hwfn->mcp_info->public_base)
 104                 return;
 105
 106         for (i = 0; i < length; i++) {
 107                 tmp = qed_rd(p_hwfn, p_ptt,
 108                              p_hwfn->mcp_info->mfw_mb_addr +
 109                              (i << 2) + sizeof(u32));
 110
 111                 /* The MB data is actually BE; Need to force it to cpu */
 112                 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
 113                         be32_to_cpu((__force __be32)tmp);
 114         }
 115 }
 116
 117 struct qed_mcp_cmd_elem {
 118         struct list_head list;
 119         struct qed_mcp_mb_params *p_mb_params;
 120         u16 expected_seq_num;
 121         bool b_is_completed;
 122 };
 123
 124 /* Must be called while cmd_lock is acquired */
 125 static struct qed_mcp_cmd_elem *
 126 qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn,
 127                      struct qed_mcp_mb_params *p_mb_params,
 128                      u16 expected_seq_num)
 129 {
 130         struct qed_mcp_cmd_elem *p_cmd_elem = NULL;
 131
 132         p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC);
 133         if (!p_cmd_elem)
 134                 goto out;
 135
 136         p_cmd_elem->p_mb_params = p_mb_params;
 137         p_cmd_elem->expected_seq_num = expected_seq_num;
 138         list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
 139 out:
 140         return p_cmd_elem;
 141 }
 142
 143 /* Must be called while cmd_lock is acquired */
 144 static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn,
 145                                  struct qed_mcp_cmd_elem *p_cmd_elem)
 146 {
 147         list_del(&p_cmd_elem->list);
 148         kfree(p_cmd_elem);
 149 }
 150
 151 /* Must be called while cmd_lock is acquired */
 152 static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn,
 153                                                      u16 seq_num)
 154 {
 155         struct qed_mcp_cmd_elem *p_cmd_elem = NULL;
 156
 157         list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) {
 158                 if (p_cmd_elem->expected_seq_num == seq_num)
 159                         return p_cmd_elem;
 160         }
 161
 162         return NULL;
 163 }
 164
 165 int qed_mcp_free(struct qed_hwfn *p_hwfn)
 166 {
 167         if (p_hwfn->mcp_info) {
 168                 struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp;
 169
 170                 kfree(p_hwfn->mcp_info->mfw_mb_cur);
 171                 kfree(p_hwfn->mcp_info->mfw_mb_shadow);
 172
 173                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 174                 list_for_each_entry_safe(p_cmd_elem,
 175                                          p_tmp,
 176                                          &p_hwfn->mcp_info->cmd_list, list) {
 177                         qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 178                 }
 179                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 180         }
 181
 182         kfree(p_hwfn->mcp_info);
 183         p_hwfn->mcp_info = NULL;
 184
 185         return 0;
 186 }
 187
 188 /* Maximum of 1 sec to wait for the SHMEM ready indication */
 189 #define QED_MCP_SHMEM_RDY_MAX_RETRIES   20
 190 #define QED_MCP_SHMEM_RDY_ITER_MS       50
 191
 192 static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 193 {
 194         struct qed_mcp_info *p_info = p_hwfn->mcp_info;
 195         u8 cnt = QED_MCP_SHMEM_RDY_MAX_RETRIES;
 196         u8 msec = QED_MCP_SHMEM_RDY_ITER_MS;
 197         u32 drv_mb_offsize, mfw_mb_offsize;
 198         u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
 199
 200         p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
 201         if (!p_info->public_base) {
 202                 DP_NOTICE(p_hwfn,
 203                           "The address of the MCP scratch-pad is not configured\n");
 204                 return -EINVAL;
 205         }
 206
 207         p_info->public_base |= GRCBASE_MCP;
 208
 209         /* Get the MFW MB address and number of supported messages */
 210         mfw_mb_offsize = qed_rd(p_hwfn, p_ptt,
 211                                 SECTION_OFFSIZE_ADDR(p_info->public_base,
 212                                                      PUBLIC_MFW_MB));
 213         p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
 214         p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt,
 215                                             p_info->mfw_mb_addr +
 216                                             offsetof(struct public_mfw_mb,
 217                                                      sup_msgs));
 218
 219         /* The driver can notify that there was an MCP reset, and might read the
 220          * SHMEM values before the MFW has completed initializing them.
 221          * To avoid this, the "sup_msgs" field in the MFW mailbox is used as a
 222          * data ready indication.
 223          */
 224         while (!p_info->mfw_mb_length && --cnt) {
 225                 msleep(msec);
 226                 p_info->mfw_mb_length =
 227                         (u16)qed_rd(p_hwfn, p_ptt,
 228                                     p_info->mfw_mb_addr +
 229                                     offsetof(struct public_mfw_mb, sup_msgs));
 230         }
 231
 232         if (!cnt) {
 233                 DP_NOTICE(p_hwfn,
 234                           "Failed to get the SHMEM ready notification after %d msec\n",
 235                           QED_MCP_SHMEM_RDY_MAX_RETRIES * msec);
 236                 return -EBUSY;
 237         }
 238
 239         /* Calculate the driver and MFW mailbox address */
 240         drv_mb_offsize = qed_rd(p_hwfn, p_ptt,
 241                                 SECTION_OFFSIZE_ADDR(p_info->public_base,
 242                                                      PUBLIC_DRV_MB));
 243         p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
 244         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 245                    "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n",
 246                    drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
 247
 248         /* Get the current driver mailbox sequence before sending
 249          * the first command
 250          */
 251         p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 252                              DRV_MSG_SEQ_NUMBER_MASK;
 253
 254         /* Get current FW pulse sequence */
 255         p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
 256                                 DRV_PULSE_SEQ_MASK;
 257
 258         p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 259
 260         return 0;
 261 }
 262
 263 int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 264 {
 265         struct qed_mcp_info *p_info;
 266         u32 size;
 267
 268         /* Allocate mcp_info structure */
 269         p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL);
 270         if (!p_hwfn->mcp_info)
 271                 goto err;
 272         p_info = p_hwfn->mcp_info;
 273
 274         /* Initialize the MFW spinlock */
 275         spin_lock_init(&p_info->cmd_lock);
 276         spin_lock_init(&p_info->link_lock);
 277
 278         INIT_LIST_HEAD(&p_info->cmd_list);
 279
 280         if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) {
 281                 DP_NOTICE(p_hwfn, "MCP is not initialized\n");
 282                 /* Do not free mcp_info here, since public_base indicate that
 283                  * the MCP is not initialized
 284                  */
 285                 return 0;
 286         }
 287
 288         size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
 289         p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL);
 290         p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL);
 291         if (!p_info->mfw_mb_cur || !p_info->mfw_mb_shadow)
 292                 goto err;
 293
 294         return 0;
 295
 296 err:
 297         qed_mcp_free(p_hwfn);
 298         return -ENOMEM;
 299 }
 300
 301 static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn,
 302                                    struct qed_ptt *p_ptt)
 303 {
 304         u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 305
 306         /* Use MCP history register to check if MCP reset occurred between init
 307          * time and now.
 308          */
 309         if (p_hwfn->mcp_info->mcp_hist != generic_por_0) {
 310                 DP_VERBOSE(p_hwfn,
 311                            QED_MSG_SP,
 312                            "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n",
 313                            p_hwfn->mcp_info->mcp_hist, generic_por_0);
 314
 315                 qed_load_mcp_offsets(p_hwfn, p_ptt);
 316                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
 317         }
 318 }
 319
 320 int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 321 {
 322         u32 org_mcp_reset_seq, seq, delay = QED_MCP_RESP_ITER_US, cnt = 0;
 323         int rc = 0;
 324
 325         if (p_hwfn->mcp_info->b_block_cmd) {
 326                 DP_NOTICE(p_hwfn,
 327                           "The MFW is not responsive. Avoid sending MCP_RESET mailbox command.\n");
 328                 return -EBUSY;
 329         }
 330
 331         /* Ensure that only a single thread is accessing the mailbox */
 332         spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 333
 334         org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 335
 336         /* Set drv command along with the updated sequence */
 337         qed_mcp_reread_offsets(p_hwfn, p_ptt);
 338         seq = ++p_hwfn->mcp_info->drv_mb_seq;
 339         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
 340
 341         do {
 342                 /* Wait for MFW response */
 343                 udelay(delay);
 344                 /* Give the FW up to 500 second (50*1000*10usec) */
 345         } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt,
 346                                               MISCS_REG_GENERIC_POR_0)) &&
 347                  (cnt++ < QED_MCP_RESET_RETRIES));
 348
 349         if (org_mcp_reset_seq !=
 350             qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 351                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
 352                            "MCP was reset after %d usec\n", cnt * delay);
 353         } else {
 354                 DP_ERR(p_hwfn, "Failed to reset MCP\n");
 355                 rc = -EAGAIN;
 356         }
 357
 358         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 359
 360         return rc;
 361 }
 362
 363 /* Must be called while cmd_lock is acquired */
 364 static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn)
 365 {
 366         struct qed_mcp_cmd_elem *p_cmd_elem;
 367
 368         /* There is at most one pending command at a certain time, and if it
 369          * exists - it is placed at the HEAD of the list.
 370          */
 371         if (!list_empty(&p_hwfn->mcp_info->cmd_list)) {
 372                 p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list,
 373                                               struct qed_mcp_cmd_elem, list);
 374                 return !p_cmd_elem->b_is_completed;
 375         }
 376
 377         return false;
 378 }
 379
 380 /* Must be called while cmd_lock is acquired */
 381 static int
 382 qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 383 {
 384         struct qed_mcp_mb_params *p_mb_params;
 385         struct qed_mcp_cmd_elem *p_cmd_elem;
 386         u32 mcp_resp;
 387         u16 seq_num;
 388
 389         mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
 390         seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK);
 391
 392         /* Return if no new non-handled response has been received */
 393         if (seq_num != p_hwfn->mcp_info->drv_mb_seq)
 394                 return -EAGAIN;
 395
 396         p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num);
 397         if (!p_cmd_elem) {
 398                 DP_ERR(p_hwfn,
 399                        "Failed to find a pending mailbox cmd that expects sequence number %d\n",
 400                        seq_num);
 401                 return -EINVAL;
 402         }
 403
 404         p_mb_params = p_cmd_elem->p_mb_params;
 405
 406         /* Get the MFW response along with the sequence number */
 407         p_mb_params->mcp_resp = mcp_resp;
 408
 409         /* Get the MFW param */
 410         p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
 411
 412         /* Get the union data */
 413         if (p_mb_params->p_data_dst != NULL && p_mb_params->data_dst_size) {
 414                 u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 415                                       offsetof(struct public_drv_mb,
 416                                                union_data);
 417                 qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
 418                                 union_data_addr, p_mb_params->data_dst_size);
 419         }
 420
 421         p_cmd_elem->b_is_completed = true;
 422
 423         return 0;
 424 }
 425
 426 /* Must be called while cmd_lock is acquired */
 427 static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
 428                                     struct qed_ptt *p_ptt,
 429                                     struct qed_mcp_mb_params *p_mb_params,
 430                                     u16 seq_num)
 431 {
 432         union drv_union_data union_data;
 433         u32 union_data_addr;
 434
 435         /* Set the union data */
 436         union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 437                           offsetof(struct public_drv_mb, union_data);
 438         memset(&union_data, 0, sizeof(union_data));
 439         if (p_mb_params->p_data_src != NULL && p_mb_params->data_src_size)
 440                 memcpy(&union_data, p_mb_params->p_data_src,
 441                        p_mb_params->data_src_size);
 442         qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
 443                       sizeof(union_data));
 444
 445         /* Set the drv param */
 446         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param);
 447
 448         /* Set the drv command along with the sequence number */
 449         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num));
 450
 451         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 452                    "MFW mailbox: command 0x%08x param 0x%08x\n",
 453                    (p_mb_params->cmd | seq_num), p_mb_params->param);
 454 }
 455
 456 static void qed_mcp_cmd_set_blocking(struct qed_hwfn *p_hwfn, bool block_cmd)
 457 {
 458         p_hwfn->mcp_info->b_block_cmd = block_cmd;
 459
 460         DP_INFO(p_hwfn, "%s sending of mailbox commands to the MFW\n",
 461                 block_cmd ? "Block" : "Unblock");
 462 }
 463
 464 static void qed_mcp_print_cpu_info(struct qed_hwfn *p_hwfn,
 465                                    struct qed_ptt *p_ptt)
 466 {
 467         u32 cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2;
 468         u32 delay = QED_MCP_RESP_ITER_US;
 469
 470         cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
 471         cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
 472         cpu_pc_0 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER);
 473         udelay(delay);
 474         cpu_pc_1 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER);
 475         udelay(delay);
 476         cpu_pc_2 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER);
 477
 478         DP_NOTICE(p_hwfn,
 479                   "MCP CPU info: mode 0x%08x, state 0x%08x, pc {0x%08x, 0x%08x, 0x%08x}\n",
 480                   cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2);
 481 }
 482
 483 static int
 484 _qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
 485                        struct qed_ptt *p_ptt,
 486                        struct qed_mcp_mb_params *p_mb_params,
 487                        u32 max_retries, u32 usecs)
 488 {
 489         u32 cnt = 0, msecs = DIV_ROUND_UP(usecs, 1000);
 490         struct qed_mcp_cmd_elem *p_cmd_elem;
 491         u16 seq_num;
 492         int rc = 0;
 493
 494         /* Wait until the mailbox is non-occupied */
 495         do {
 496                 /* Exit the loop if there is no pending command, or if the
 497                  * pending command is completed during this iteration.
 498                  * The spinlock stays locked until the command is sent.
 499                  */
 500
 501                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 502
 503                 if (!qed_mcp_has_pending_cmd(p_hwfn))
 504                         break;
 505
 506                 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt);
 507                 if (!rc)
 508                         break;
 509                 else if (rc != -EAGAIN)
 510                         goto err;
 511
 512                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 513
 514                 if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP))
 515                         msleep(msecs);
 516                 else
 517                         udelay(usecs);
 518         } while (++cnt < max_retries);
 519
 520         if (cnt >= max_retries) {
 521                 DP_NOTICE(p_hwfn,
 522                           "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n",
 523                           p_mb_params->cmd, p_mb_params->param);
 524                 return -EAGAIN;
 525         }
 526
 527         /* Send the mailbox command */
 528         qed_mcp_reread_offsets(p_hwfn, p_ptt);
 529         seq_num = ++p_hwfn->mcp_info->drv_mb_seq;
 530         p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num);
 531         if (!p_cmd_elem) {
 532                 rc = -ENOMEM;
 533                 goto err;
 534         }
 535
 536         __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num);
 537         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 538
 539         /* Wait for the MFW response */
 540         do {
 541                 /* Exit the loop if the command is already completed, or if the
 542                  * command is completed during this iteration.
 543                  * The spinlock stays locked until the list element is removed.
 544                  */
 545
 546                 if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP))
 547                         msleep(msecs);
 548                 else
 549                         udelay(usecs);
 550
 551                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 552
 553                 if (p_cmd_elem->b_is_completed)
 554                         break;
 555
 556                 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt);
 557                 if (!rc)
 558                         break;
 559                 else if (rc != -EAGAIN)
 560                         goto err;
 561
 562                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 563         } while (++cnt < max_retries);
 564
 565         if (cnt >= max_retries) {
 566                 DP_NOTICE(p_hwfn,
 567                           "The MFW failed to respond to command 0x%08x [param 0x%08x].\n",
 568                           p_mb_params->cmd, p_mb_params->param);
 569                 qed_mcp_print_cpu_info(p_hwfn, p_ptt);
 570
 571                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 572                 qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 573                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 574
 575                 if (!QED_MB_FLAGS_IS_SET(p_mb_params, AVOID_BLOCK))
 576                         qed_mcp_cmd_set_blocking(p_hwfn, true);
 577
 578                 qed_hw_err_notify(p_hwfn, p_ptt,
 579                                   QED_HW_ERR_MFW_RESP_FAIL, NULL);
 580                 return -EAGAIN;
 581         }
 582
 583         qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 584         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 585
 586         DP_VERBOSE(p_hwfn,
 587                    QED_MSG_SP,
 588                    "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n",
 589                    p_mb_params->mcp_resp,
 590                    p_mb_params->mcp_param,
 591                    (cnt * usecs) / 1000, (cnt * usecs) % 1000);
 592
 593         /* Clear the sequence number from the MFW response */
 594         p_mb_params->mcp_resp &= FW_MSG_CODE_MASK;
 595
 596         return 0;
 597
 598 err:
 599         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 600         return rc;
 601 }
 602
 603 static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
 604                                  struct qed_ptt *p_ptt,
 605                                  struct qed_mcp_mb_params *p_mb_params)
 606 {
 607         size_t union_data_size = sizeof(union drv_union_data);
 608         u32 max_retries = QED_DRV_MB_MAX_RETRIES;
 609         u32 usecs = QED_MCP_RESP_ITER_US;
 610
 611         /* MCP not initialized */
 612         if (!qed_mcp_is_init(p_hwfn)) {
 613                 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
 614                 return -EBUSY;
 615         }
 616
 617         if (p_hwfn->mcp_info->b_block_cmd) {
 618                 DP_NOTICE(p_hwfn,
 619                           "The MFW is not responsive. Avoid sending mailbox command 0x%08x [param 0x%08x].\n",
 620                           p_mb_params->cmd, p_mb_params->param);
 621                 return -EBUSY;
 622         }
 623
 624         if (p_mb_params->data_src_size > union_data_size ||
 625             p_mb_params->data_dst_size > union_data_size) {
 626                 DP_ERR(p_hwfn,
 627                        "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
 628                        p_mb_params->data_src_size,
 629                        p_mb_params->data_dst_size, union_data_size);
 630                 return -EINVAL;
 631         }
 632
 633         if (QED_MB_FLAGS_IS_SET(p_mb_params, CAN_SLEEP)) {
 634                 max_retries = DIV_ROUND_UP(max_retries, 1000);
 635                 usecs *= 1000;
 636         }
 637
 638         return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries,
 639                                       usecs);
 640 }
 641
 642 int qed_mcp_cmd(struct qed_hwfn *p_hwfn,
 643                 struct qed_ptt *p_ptt,
 644                 u32 cmd,
 645                 u32 param,
 646                 u32 *o_mcp_resp,
 647                 u32 *o_mcp_param)
 648 {
 649         struct qed_mcp_mb_params mb_params;
 650         int rc;
 651
 652         memset(&mb_params, 0, sizeof(mb_params));
 653         mb_params.cmd = cmd;
 654         mb_params.param = param;
 655
 656         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 657         if (rc)
 658                 return rc;
 659
 660         *o_mcp_resp = mb_params.mcp_resp;
 661         *o_mcp_param = mb_params.mcp_param;
 662
 663         return 0;
 664 }
 665
 666 static int
 667 qed_mcp_nvm_wr_cmd(struct qed_hwfn *p_hwfn,
 668                    struct qed_ptt *p_ptt,
 669                    u32 cmd,
 670                    u32 param,
 671                    u32 *o_mcp_resp,
 672                    u32 *o_mcp_param, u32 i_txn_size, u32 *i_buf)
 673 {
 674         struct qed_mcp_mb_params mb_params;
 675         int rc;
 676
 677         memset(&mb_params, 0, sizeof(mb_params));
 678         mb_params.cmd = cmd;
 679         mb_params.param = param;
 680         mb_params.p_data_src = i_buf;
 681         mb_params.data_src_size = (u8)i_txn_size;
 682         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 683         if (rc)
 684                 return rc;
 685
 686         *o_mcp_resp = mb_params.mcp_resp;
 687         *o_mcp_param = mb_params.mcp_param;
 688
 689         /* nvm_info needs to be updated */
 690         p_hwfn->nvm_info.valid = false;
 691
 692         return 0;
 693 }
 694
 695 int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn,
 696                        struct qed_ptt *p_ptt,
 697                        u32 cmd,
 698                        u32 param,
 699                        u32 *o_mcp_resp,
 700                        u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf)
 701 {
 702         struct qed_mcp_mb_params mb_params;
 703         u8 raw_data[MCP_DRV_NVM_BUF_LEN];
 704         int rc;
 705
 706         memset(&mb_params, 0, sizeof(mb_params));
 707         mb_params.cmd = cmd;
 708         mb_params.param = param;
 709         mb_params.p_data_dst = raw_data;
 710
 711         /* Use the maximal value since the actual one is part of the response */
 712         mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
 713
 714         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 715         if (rc)
 716                 return rc;
 717
 718         *o_mcp_resp = mb_params.mcp_resp;
 719         *o_mcp_param = mb_params.mcp_param;
 720
 721         *o_txn_size = *o_mcp_param;
 722         memcpy(o_buf, raw_data, *o_txn_size);
 723
 724         return 0;
 725 }
 726
 727 static bool
 728 qed_mcp_can_force_load(u8 drv_role,
 729                        u8 exist_drv_role,
 730                        enum qed_override_force_load override_force_load)
 731 {
 732         bool can_force_load = false;
 733
 734         switch (override_force_load) {
 735         case QED_OVERRIDE_FORCE_LOAD_ALWAYS:
 736                 can_force_load = true;
 737                 break;
 738         case QED_OVERRIDE_FORCE_LOAD_NEVER:
 739                 can_force_load = false;
 740                 break;
 741         default:
 742                 can_force_load = (drv_role == DRV_ROLE_OS &&
 743                                   exist_drv_role == DRV_ROLE_PREBOOT) ||
 744                                  (drv_role == DRV_ROLE_KDUMP &&
 745                                   exist_drv_role == DRV_ROLE_OS);
 746                 break;
 747         }
 748
 749         return can_force_load;
 750 }
 751
 752 static int qed_mcp_cancel_load_req(struct qed_hwfn *p_hwfn,
 753                                    struct qed_ptt *p_ptt)
 754 {
 755         u32 resp = 0, param = 0;
 756         int rc;
 757
 758         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
 759                          &resp, &param);
 760         if (rc)
 761                 DP_NOTICE(p_hwfn,
 762                           "Failed to send cancel load request, rc = %d\n", rc);
 763
 764         return rc;
 765 }
 766
 767 #define CONFIG_QEDE_BITMAP_IDX          BIT(0)
 768 #define CONFIG_QED_SRIOV_BITMAP_IDX     BIT(1)
 769 #define CONFIG_QEDR_BITMAP_IDX          BIT(2)
 770 #define CONFIG_QEDF_BITMAP_IDX          BIT(4)
 771 #define CONFIG_QEDI_BITMAP_IDX          BIT(5)
 772 #define CONFIG_QED_LL2_BITMAP_IDX       BIT(6)
 773
 774 static u32 qed_get_config_bitmap(void)
 775 {
 776         u32 config_bitmap = 0x0;
 777
 778         if (IS_ENABLED(CONFIG_QEDE))
 779                 config_bitmap |= CONFIG_QEDE_BITMAP_IDX;
 780
 781         if (IS_ENABLED(CONFIG_QED_SRIOV))
 782                 config_bitmap |= CONFIG_QED_SRIOV_BITMAP_IDX;
 783
 784         if (IS_ENABLED(CONFIG_QED_RDMA))
 785                 config_bitmap |= CONFIG_QEDR_BITMAP_IDX;
 786
 787         if (IS_ENABLED(CONFIG_QED_FCOE))
 788                 config_bitmap |= CONFIG_QEDF_BITMAP_IDX;
 789
 790         if (IS_ENABLED(CONFIG_QED_ISCSI))
 791                 config_bitmap |= CONFIG_QEDI_BITMAP_IDX;
 792
 793         if (IS_ENABLED(CONFIG_QED_LL2))
 794                 config_bitmap |= CONFIG_QED_LL2_BITMAP_IDX;
 795
 796         return config_bitmap;
 797 }
 798
 799 struct qed_load_req_in_params {
 800         u8 hsi_ver;
 801 #define QED_LOAD_REQ_HSI_VER_DEFAULT    0
 802 #define QED_LOAD_REQ_HSI_VER_1          1
 803         u32 drv_ver_0;
 804         u32 drv_ver_1;
 805         u32 fw_ver;
 806         u8 drv_role;
 807         u8 timeout_val;
 808         u8 force_cmd;
 809         bool avoid_eng_reset;
 810 };
 811
 812 struct qed_load_req_out_params {
 813         u32 load_code;
 814         u32 exist_drv_ver_0;
 815         u32 exist_drv_ver_1;
 816         u32 exist_fw_ver;
 817         u8 exist_drv_role;
 818         u8 mfw_hsi_ver;
 819         bool drv_exists;
 820 };
 821
 822 static int
 823 __qed_mcp_load_req(struct qed_hwfn *p_hwfn,
 824                    struct qed_ptt *p_ptt,
 825                    struct qed_load_req_in_params *p_in_params,
 826                    struct qed_load_req_out_params *p_out_params)
 827 {
 828         struct qed_mcp_mb_params mb_params;
 829         struct load_req_stc load_req;
 830         struct load_rsp_stc load_rsp;
 831         u32 hsi_ver;
 832         int rc;
 833
 834         memset(&load_req, 0, sizeof(load_req));
 835         load_req.drv_ver_0 = p_in_params->drv_ver_0;
 836         load_req.drv_ver_1 = p_in_params->drv_ver_1;
 837         load_req.fw_ver = p_in_params->fw_ver;
 838         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role);
 839         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
 840                           p_in_params->timeout_val);
 841         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE,
 842                           p_in_params->force_cmd);
 843         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
 844                           p_in_params->avoid_eng_reset);
 845
 846         hsi_ver = (p_in_params->hsi_ver == QED_LOAD_REQ_HSI_VER_DEFAULT) ?
 847                   DRV_ID_MCP_HSI_VER_CURRENT :
 848                   (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT);
 849
 850         memset(&mb_params, 0, sizeof(mb_params));
 851         mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
 852         mb_params.param = PDA_COMP | hsi_ver | p_hwfn->cdev->drv_type;
 853         mb_params.p_data_src = &load_req;
 854         mb_params.data_src_size = sizeof(load_req);
 855         mb_params.p_data_dst = &load_rsp;
 856         mb_params.data_dst_size = sizeof(load_rsp);
 857         mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK;
 858
 859         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 860                    "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
 861                    mb_params.param,
 862                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
 863                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
 864                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
 865                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
 866
 867         if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1) {
 868                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
 869                            "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
 870                            load_req.drv_ver_0,
 871                            load_req.drv_ver_1,
 872                            load_req.fw_ver,
 873                            load_req.misc0,
 874                            QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE),
 875                            QED_MFW_GET_FIELD(load_req.misc0,
 876                                              LOAD_REQ_LOCK_TO),
 877                            QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE),
 878                            QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0));
 879         }
 880
 881         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 882         if (rc) {
 883                 DP_NOTICE(p_hwfn, "Failed to send load request, rc = %d\n", rc);
 884                 return rc;
 885         }
 886
 887         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 888                    "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
 889         p_out_params->load_code = mb_params.mcp_resp;
 890
 891         if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1 &&
 892             p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 893                 DP_VERBOSE(p_hwfn,
 894                            QED_MSG_SP,
 895                            "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
 896                            load_rsp.drv_ver_0,
 897                            load_rsp.drv_ver_1,
 898                            load_rsp.fw_ver,
 899                            load_rsp.misc0,
 900                            QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
 901                            QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
 902                            QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0));
 903
 904                 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
 905                 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
 906                 p_out_params->exist_fw_ver = load_rsp.fw_ver;
 907                 p_out_params->exist_drv_role =
 908                     QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
 909                 p_out_params->mfw_hsi_ver =
 910                     QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
 911                 p_out_params->drv_exists =
 912                     QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
 913                     LOAD_RSP_FLAGS0_DRV_EXISTS;
 914         }
 915
 916         return 0;
 917 }
 918
 919 static int eocre_get_mfw_drv_role(struct qed_hwfn *p_hwfn,
 920                                   enum qed_drv_role drv_role,
 921                                   u8 *p_mfw_drv_role)
 922 {
 923         switch (drv_role) {
 924         case QED_DRV_ROLE_OS:
 925                 *p_mfw_drv_role = DRV_ROLE_OS;
 926                 break;
 927         case QED_DRV_ROLE_KDUMP:
 928                 *p_mfw_drv_role = DRV_ROLE_KDUMP;
 929                 break;
 930         default:
 931                 DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role);
 932                 return -EINVAL;
 933         }
 934
 935         return 0;
 936 }
 937
 938 enum qed_load_req_force {
 939         QED_LOAD_REQ_FORCE_NONE,
 940         QED_LOAD_REQ_FORCE_PF,
 941         QED_LOAD_REQ_FORCE_ALL,
 942 };
 943
 944 static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn,
 945
 946                                   enum qed_load_req_force force_cmd,
 947                                   u8 *p_mfw_force_cmd)
 948 {
 949         switch (force_cmd) {
 950         case QED_LOAD_REQ_FORCE_NONE:
 951                 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
 952                 break;
 953         case QED_LOAD_REQ_FORCE_PF:
 954                 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
 955                 break;
 956         case QED_LOAD_REQ_FORCE_ALL:
 957                 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
 958                 break;
 959         }
 960 }
 961
 962 int qed_mcp_load_req(struct qed_hwfn *p_hwfn,
 963                      struct qed_ptt *p_ptt,
 964                      struct qed_load_req_params *p_params)
 965 {
 966         struct qed_load_req_out_params out_params;
 967         struct qed_load_req_in_params in_params;
 968         u8 mfw_drv_role, mfw_force_cmd;
 969         int rc;
 970
 971         memset(&in_params, 0, sizeof(in_params));
 972         in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_DEFAULT;
 973         in_params.drv_ver_0 = QED_VERSION;
 974         in_params.drv_ver_1 = qed_get_config_bitmap();
 975         in_params.fw_ver = STORM_FW_VERSION;
 976         rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role);
 977         if (rc)
 978                 return rc;
 979
 980         in_params.drv_role = mfw_drv_role;
 981         in_params.timeout_val = p_params->timeout_val;
 982         qed_get_mfw_force_cmd(p_hwfn,
 983                               QED_LOAD_REQ_FORCE_NONE, &mfw_force_cmd);
 984
 985         in_params.force_cmd = mfw_force_cmd;
 986         in_params.avoid_eng_reset = p_params->avoid_eng_reset;
 987
 988         memset(&out_params, 0, sizeof(out_params));
 989         rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
 990         if (rc)
 991                 return rc;
 992
 993         /* First handle cases where another load request should/might be sent:
 994          * - MFW expects the old interface [HSI version = 1]
 995          * - MFW responds that a force load request is required
 996          */
 997         if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 998                 DP_INFO(p_hwfn,
 999                         "MFW refused a load request due to HSI > 1. Resending with HSI = 1\n");
1000
1001                 in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_1;
1002                 memset(&out_params, 0, sizeof(out_params));
1003                 rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
1004                 if (rc)
1005                         return rc;
1006         } else if (out_params.load_code ==
1007                    FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
1008                 if (qed_mcp_can_force_load(in_params.drv_role,
1009                                            out_params.exist_drv_role,
1010                                            p_params->override_force_load)) {
1011                         DP_INFO(p_hwfn,
1012                                 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}]\n",
1013                                 in_params.drv_role, in_params.fw_ver,
1014                                 in_params.drv_ver_0, in_params.drv_ver_1,
1015                                 out_params.exist_drv_role,
1016                                 out_params.exist_fw_ver,
1017                                 out_params.exist_drv_ver_0,
1018                                 out_params.exist_drv_ver_1);
1019
1020                         qed_get_mfw_force_cmd(p_hwfn,
1021                                               QED_LOAD_REQ_FORCE_ALL,
1022                                               &mfw_force_cmd);
1023
1024                         in_params.force_cmd = mfw_force_cmd;
1025                         memset(&out_params, 0, sizeof(out_params));
1026                         rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params,
1027                                                 &out_params);
1028                         if (rc)
1029                                 return rc;
1030                 } else {
1031                         DP_NOTICE(p_hwfn,
1032                                   "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n",
1033                                   in_params.drv_role, in_params.fw_ver,
1034                                   in_params.drv_ver_0, in_params.drv_ver_1,
1035                                   out_params.exist_drv_role,
1036                                   out_params.exist_fw_ver,
1037                                   out_params.exist_drv_ver_0,
1038                                   out_params.exist_drv_ver_1);
1039                         DP_NOTICE(p_hwfn,
1040                                   "Avoid sending a force load request to prevent disruption of active PFs\n");
1041
1042                         qed_mcp_cancel_load_req(p_hwfn, p_ptt);
1043                         return -EBUSY;
1044                 }
1045         }
1046
1047         /* Now handle the other types of responses.
1048          * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not
1049          * expected here after the additional revised load requests were sent.
1050          */
1051         switch (out_params.load_code) {
1052         case FW_MSG_CODE_DRV_LOAD_ENGINE:
1053         case FW_MSG_CODE_DRV_LOAD_PORT:
1054         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1055                 if (out_params.mfw_hsi_ver != QED_LOAD_REQ_HSI_VER_1 &&
1056                     out_params.drv_exists) {
1057                         /* The role and fw/driver version match, but the PF is
1058                          * already loaded and has not been unloaded gracefully.
1059                          */
1060                         DP_NOTICE(p_hwfn,
1061                                   "PF is already loaded\n");
1062                         return -EINVAL;
1063                 }
1064                 break;
1065         default:
1066                 DP_NOTICE(p_hwfn,
1067                           "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n",
1068                           out_params.load_code);
1069                 return -EBUSY;
1070         }
1071
1072         p_params->load_code = out_params.load_code;
1073
1074         return 0;
1075 }
1076
1077 int qed_mcp_load_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1078 {
1079         u32 resp = 0, param = 0;
1080         int rc;
1081
1082         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp,
1083                          &param);
1084         if (rc) {
1085                 DP_NOTICE(p_hwfn,
1086                           "Failed to send a LOAD_DONE command, rc = %d\n", rc);
1087                 return rc;
1088         }
1089
1090         /* Check if there is a DID mismatch between nvm-cfg/efuse */
1091         if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1092                 DP_NOTICE(p_hwfn,
1093                           "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1094
1095         return 0;
1096 }
1097
1098 int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1099 {
1100         struct qed_mcp_mb_params mb_params;
1101         u32 wol_param;
1102
1103         switch (p_hwfn->cdev->wol_config) {
1104         case QED_OV_WOL_DISABLED:
1105                 wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED;
1106                 break;
1107         case QED_OV_WOL_ENABLED:
1108                 wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED;
1109                 break;
1110         default:
1111                 DP_NOTICE(p_hwfn,
1112                           "Unknown WoL configuration %02x\n",
1113                           p_hwfn->cdev->wol_config);
1114                 /* Fallthrough */
1115         case QED_OV_WOL_DEFAULT:
1116                 wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
1117         }
1118
1119         memset(&mb_params, 0, sizeof(mb_params));
1120         mb_params.cmd = DRV_MSG_CODE_UNLOAD_REQ;
1121         mb_params.param = wol_param;
1122         mb_params.flags = QED_MB_FLAG_CAN_SLEEP | QED_MB_FLAG_AVOID_BLOCK;
1123
1124         return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1125 }
1126
1127 int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1128 {
1129         struct qed_mcp_mb_params mb_params;
1130         struct mcp_mac wol_mac;
1131
1132         memset(&mb_params, 0, sizeof(mb_params));
1133         mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
1134
1135         /* Set the primary MAC if WoL is enabled */
1136         if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) {
1137                 u8 *p_mac = p_hwfn->cdev->wol_mac;
1138
1139                 memset(&wol_mac, 0, sizeof(wol_mac));
1140                 wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1];
1141                 wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 |
1142                                     p_mac[4] << 8 | p_mac[5];
1143
1144                 DP_VERBOSE(p_hwfn,
1145                            (QED_MSG_SP | NETIF_MSG_IFDOWN),
1146                            "Setting WoL MAC: %pM --> [%08x,%08x]\n",
1147                            p_mac, wol_mac.mac_upper, wol_mac.mac_lower);
1148
1149                 mb_params.p_data_src = &wol_mac;
1150                 mb_params.data_src_size = sizeof(wol_mac);
1151         }
1152
1153         return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1154 }
1155
1156 static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn,
1157                                   struct qed_ptt *p_ptt)
1158 {
1159         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1160                                         PUBLIC_PATH);
1161         u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
1162         u32 path_addr = SECTION_ADDR(mfw_path_offsize,
1163                                      QED_PATH_ID(p_hwfn));
1164         u32 disabled_vfs[VF_MAX_STATIC / 32];
1165         int i;
1166
1167         DP_VERBOSE(p_hwfn,
1168                    QED_MSG_SP,
1169                    "Reading Disabled VF information from [offset %08x], path_addr %08x\n",
1170                    mfw_path_offsize, path_addr);
1171
1172         for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
1173                 disabled_vfs[i] = qed_rd(p_hwfn, p_ptt,
1174                                          path_addr +
1175                                          offsetof(struct public_path,
1176                                                   mcp_vf_disabled) +
1177                                          sizeof(u32) * i);
1178                 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV),
1179                            "FLR-ed VFs [%08x,...,%08x] - %08x\n",
1180                            i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
1181         }
1182
1183         if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs))
1184                 qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG);
1185 }
1186
1187 int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn,
1188                        struct qed_ptt *p_ptt, u32 *vfs_to_ack)
1189 {
1190         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1191                                         PUBLIC_FUNC);
1192         u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr);
1193         u32 func_addr = SECTION_ADDR(mfw_func_offsize,
1194                                      MCP_PF_ID(p_hwfn));
1195         struct qed_mcp_mb_params mb_params;
1196         int rc;
1197         int i;
1198
1199         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1200                 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV),
1201                            "Acking VFs [%08x,...,%08x] - %08x\n",
1202                            i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
1203
1204         memset(&mb_params, 0, sizeof(mb_params));
1205         mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
1206         mb_params.p_data_src = vfs_to_ack;
1207         mb_params.data_src_size = VF_MAX_STATIC / 8;
1208         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1209         if (rc) {
1210                 DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n");
1211                 return -EBUSY;
1212         }
1213
1214         /* Clear the ACK bits */
1215         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1216                 qed_wr(p_hwfn, p_ptt,
1217                        func_addr +
1218                        offsetof(struct public_func, drv_ack_vf_disabled) +
1219                        i * sizeof(u32), 0);
1220
1221         return rc;
1222 }
1223
1224 static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn,
1225                                               struct qed_ptt *p_ptt)
1226 {
1227         u32 transceiver_state;
1228
1229         transceiver_state = qed_rd(p_hwfn, p_ptt,
1230                                    p_hwfn->mcp_info->port_addr +
1231                                    offsetof(struct public_port,
1232                                             transceiver_data));
1233
1234         DP_VERBOSE(p_hwfn,
1235                    (NETIF_MSG_HW | QED_MSG_SP),
1236                    "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n",
1237                    transceiver_state,
1238                    (u32)(p_hwfn->mcp_info->port_addr +
1239                           offsetof(struct public_port, transceiver_data)));
1240
1241         transceiver_state = GET_FIELD(transceiver_state,
1242                                       ETH_TRANSCEIVER_STATE);
1243
1244         if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1245                 DP_NOTICE(p_hwfn, "Transceiver is present.\n");
1246         else
1247                 DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n");
1248 }
1249
1250 static void qed_mcp_read_eee_config(struct qed_hwfn *p_hwfn,
1251                                     struct qed_ptt *p_ptt,
1252                                     struct qed_mcp_link_state *p_link)
1253 {
1254         u32 eee_status, val;
1255
1256         p_link->eee_adv_caps = 0;
1257         p_link->eee_lp_adv_caps = 0;
1258         eee_status = qed_rd(p_hwfn,
1259                             p_ptt,
1260                             p_hwfn->mcp_info->port_addr +
1261                             offsetof(struct public_port, eee_status));
1262         p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT);
1263         val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET;
1264         if (val & EEE_1G_ADV)
1265                 p_link->eee_adv_caps |= QED_EEE_1G_ADV;
1266         if (val & EEE_10G_ADV)
1267                 p_link->eee_adv_caps |= QED_EEE_10G_ADV;
1268         val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET;
1269         if (val & EEE_1G_ADV)
1270                 p_link->eee_lp_adv_caps |= QED_EEE_1G_ADV;
1271         if (val & EEE_10G_ADV)
1272                 p_link->eee_lp_adv_caps |= QED_EEE_10G_ADV;
1273 }
1274
1275 static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn,
1276                                   struct qed_ptt *p_ptt,
1277                                   struct public_func *p_data, int pfid)
1278 {
1279         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1280                                         PUBLIC_FUNC);
1281         u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
1282         u32 func_addr;
1283         u32 i, size;
1284
1285         func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1286         memset(p_data, 0, sizeof(*p_data));
1287
1288         size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize));
1289         for (i = 0; i < size / sizeof(u32); i++)
1290                 ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt,
1291                                             func_addr + (i << 2));
1292         return size;
1293 }
1294
1295 static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn,
1296                                   struct public_func *p_shmem_info)
1297 {
1298         struct qed_mcp_function_info *p_info;
1299
1300         p_info = &p_hwfn->mcp_info->func_info;
1301
1302         p_info->bandwidth_min = QED_MFW_GET_FIELD(p_shmem_info->config,
1303                                                   FUNC_MF_CFG_MIN_BW);
1304         if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1305                 DP_INFO(p_hwfn,
1306                         "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1307                         p_info->bandwidth_min);
1308                 p_info->bandwidth_min = 1;
1309         }
1310
1311         p_info->bandwidth_max = QED_MFW_GET_FIELD(p_shmem_info->config,
1312                                                   FUNC_MF_CFG_MAX_BW);
1313         if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1314                 DP_INFO(p_hwfn,
1315                         "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1316                         p_info->bandwidth_max);
1317                 p_info->bandwidth_max = 100;
1318         }
1319 }
1320
1321 static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn,
1322                                        struct qed_ptt *p_ptt, bool b_reset)
1323 {
1324         struct qed_mcp_link_state *p_link;
1325         u8 max_bw, min_bw;
1326         u32 status = 0;
1327
1328         /* Prevent SW/attentions from doing this at the same time */
1329         spin_lock_bh(&p_hwfn->mcp_info->link_lock);
1330
1331         p_link = &p_hwfn->mcp_info->link_output;
1332         memset(p_link, 0, sizeof(*p_link));
1333         if (!b_reset) {
1334                 status = qed_rd(p_hwfn, p_ptt,
1335                                 p_hwfn->mcp_info->port_addr +
1336                                 offsetof(struct public_port, link_status));
1337                 DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP),
1338                            "Received link update [0x%08x] from mfw [Addr 0x%x]\n",
1339                            status,
1340                            (u32)(p_hwfn->mcp_info->port_addr +
1341                                  offsetof(struct public_port, link_status)));
1342         } else {
1343                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1344                            "Resetting link indications\n");
1345                 goto out;
1346         }
1347
1348         if (p_hwfn->b_drv_link_init) {
1349                 /* Link indication with modern MFW arrives as per-PF
1350                  * indication.
1351                  */
1352                 if (p_hwfn->mcp_info->capabilities &
1353                     FW_MB_PARAM_FEATURE_SUPPORT_VLINK) {
1354                         struct public_func shmem_info;
1355
1356                         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
1357                                                MCP_PF_ID(p_hwfn));
1358                         p_link->link_up = !!(shmem_info.status &
1359                                              FUNC_STATUS_VIRTUAL_LINK_UP);
1360                         qed_read_pf_bandwidth(p_hwfn, &shmem_info);
1361                         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1362                                    "Virtual link_up = %d\n", p_link->link_up);
1363                 } else {
1364                         p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1365                         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1366                                    "Physical link_up = %d\n", p_link->link_up);
1367                 }
1368         } else {
1369                 p_link->link_up = false;
1370         }
1371
1372         p_link->full_duplex = true;
1373         switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1374         case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1375                 p_link->speed = 100000;
1376                 break;
1377         case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1378                 p_link->speed = 50000;
1379                 break;
1380         case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1381                 p_link->speed = 40000;
1382                 break;
1383         case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1384                 p_link->speed = 25000;
1385                 break;
1386         case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1387                 p_link->speed = 20000;
1388                 break;
1389         case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1390                 p_link->speed = 10000;
1391                 break;
1392         case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1393                 p_link->full_duplex = false;
1394         /* Fall-through */
1395         case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1396                 p_link->speed = 1000;
1397                 break;
1398         default:
1399                 p_link->speed = 0;
1400                 p_link->link_up = 0;
1401         }
1402
1403         if (p_link->link_up && p_link->speed)
1404                 p_link->line_speed = p_link->speed;
1405         else
1406                 p_link->line_speed = 0;
1407
1408         max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1409         min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1410
1411         /* Max bandwidth configuration */
1412         __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw);
1413
1414         /* Min bandwidth configuration */
1415         __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw);
1416         qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt,
1417                                             p_link->min_pf_rate);
1418
1419         p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1420         p_link->an_complete = !!(status &
1421                                  LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1422         p_link->parallel_detection = !!(status &
1423                                         LINK_STATUS_PARALLEL_DETECTION_USED);
1424         p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1425
1426         p_link->partner_adv_speed |=
1427                 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1428                 QED_LINK_PARTNER_SPEED_1G_FD : 0;
1429         p_link->partner_adv_speed |=
1430                 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1431                 QED_LINK_PARTNER_SPEED_1G_HD : 0;
1432         p_link->partner_adv_speed |=
1433                 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1434                 QED_LINK_PARTNER_SPEED_10G : 0;
1435         p_link->partner_adv_speed |=
1436                 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1437                 QED_LINK_PARTNER_SPEED_20G : 0;
1438         p_link->partner_adv_speed |=
1439                 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1440                 QED_LINK_PARTNER_SPEED_25G : 0;
1441         p_link->partner_adv_speed |=
1442                 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1443                 QED_LINK_PARTNER_SPEED_40G : 0;
1444         p_link->partner_adv_speed |=
1445                 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1446                 QED_LINK_PARTNER_SPEED_50G : 0;
1447         p_link->partner_adv_speed |=
1448                 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1449                 QED_LINK_PARTNER_SPEED_100G : 0;
1450
1451         p_link->partner_tx_flow_ctrl_en =
1452                 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1453         p_link->partner_rx_flow_ctrl_en =
1454                 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1455
1456         switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1457         case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1458                 p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE;
1459                 break;
1460         case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1461                 p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE;
1462                 break;
1463         case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1464                 p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE;
1465                 break;
1466         default:
1467                 p_link->partner_adv_pause = 0;
1468         }
1469
1470         p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1471
1472         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE)
1473                 qed_mcp_read_eee_config(p_hwfn, p_ptt, p_link);
1474
1475         qed_link_update(p_hwfn, p_ptt);
1476 out:
1477         spin_unlock_bh(&p_hwfn->mcp_info->link_lock);
1478 }
1479
1480 int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up)
1481 {
1482         struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1483         struct qed_mcp_mb_params mb_params;
1484         struct eth_phy_cfg phy_cfg;
1485         int rc = 0;
1486         u32 cmd;
1487
1488         /* Set the shmem configuration according to params */
1489         memset(&phy_cfg, 0, sizeof(phy_cfg));
1490         cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1491         if (!params->speed.autoneg)
1492                 phy_cfg.speed = params->speed.forced_speed;
1493         phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1494         phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1495         phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1496         phy_cfg.adv_speed = params->speed.advertised_speeds;
1497         phy_cfg.loopback_mode = params->loopback_mode;
1498
1499         /* There are MFWs that share this capability regardless of whether
1500          * this is feasible or not. And given that at the very least adv_caps
1501          * would be set internally by qed, we want to make sure LFA would
1502          * still work.
1503          */
1504         if ((p_hwfn->mcp_info->capabilities &
1505              FW_MB_PARAM_FEATURE_SUPPORT_EEE) && params->eee.enable) {
1506                 phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED;
1507                 if (params->eee.tx_lpi_enable)
1508                         phy_cfg.eee_cfg |= EEE_CFG_TX_LPI;
1509                 if (params->eee.adv_caps & QED_EEE_1G_ADV)
1510                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G;
1511                 if (params->eee.adv_caps & QED_EEE_10G_ADV)
1512                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G;
1513                 phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer <<
1514                                     EEE_TX_TIMER_USEC_OFFSET) &
1515                                    EEE_TX_TIMER_USEC_MASK;
1516         }
1517
1518         p_hwfn->b_drv_link_init = b_up;
1519
1520         if (b_up) {
1521                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1522                            "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n",
1523                            phy_cfg.speed,
1524                            phy_cfg.pause,
1525                            phy_cfg.adv_speed,
1526                            phy_cfg.loopback_mode,
1527                            phy_cfg.feature_config_flags);
1528         } else {
1529                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1530                            "Resetting link\n");
1531         }
1532
1533         memset(&mb_params, 0, sizeof(mb_params));
1534         mb_params.cmd = cmd;
1535         mb_params.p_data_src = &phy_cfg;
1536         mb_params.data_src_size = sizeof(phy_cfg);
1537         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1538
1539         /* if mcp fails to respond we must abort */
1540         if (rc) {
1541                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1542                 return rc;
1543         }
1544
1545         /* Mimic link-change attention, done for several reasons:
1546          *  - On reset, there's no guarantee MFW would trigger
1547          *    an attention.
1548          *  - On initialization, older MFWs might not indicate link change
1549          *    during LFA, so we'll never get an UP indication.
1550          */
1551         qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up);
1552
1553         return 0;
1554 }
1555
1556 u32 qed_get_process_kill_counter(struct qed_hwfn *p_hwfn,
1557                                  struct qed_ptt *p_ptt)
1558 {
1559         u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
1560
1561         if (IS_VF(p_hwfn->cdev))
1562                 return -EINVAL;
1563
1564         path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1565                                                  PUBLIC_PATH);
1566         path_offsize = qed_rd(p_hwfn, p_ptt, path_offsize_addr);
1567         path_addr = SECTION_ADDR(path_offsize, QED_PATH_ID(p_hwfn));
1568
1569         proc_kill_cnt = qed_rd(p_hwfn, p_ptt,
1570                                path_addr +
1571                                offsetof(struct public_path, process_kill)) &
1572                         PROCESS_KILL_COUNTER_MASK;
1573
1574         return proc_kill_cnt;
1575 }
1576
1577 static void qed_mcp_handle_process_kill(struct qed_hwfn *p_hwfn,
1578                                         struct qed_ptt *p_ptt)
1579 {
1580         struct qed_dev *cdev = p_hwfn->cdev;
1581         u32 proc_kill_cnt;
1582
1583         /* Prevent possible attentions/interrupts during the recovery handling
1584          * and till its load phase, during which they will be re-enabled.
1585          */
1586         qed_int_igu_disable_int(p_hwfn, p_ptt);
1587
1588         DP_NOTICE(p_hwfn, "Received a process kill indication\n");
1589
1590         /* The following operations should be done once, and thus in CMT mode
1591          * are carried out by only the first HW function.
1592          */
1593         if (p_hwfn != QED_LEADING_HWFN(cdev))
1594                 return;
1595
1596         if (cdev->recov_in_prog) {
1597                 DP_NOTICE(p_hwfn,
1598                           "Ignoring the indication since a recovery process is already in progress\n");
1599                 return;
1600         }
1601
1602         cdev->recov_in_prog = true;
1603
1604         proc_kill_cnt = qed_get_process_kill_counter(p_hwfn, p_ptt);
1605         DP_NOTICE(p_hwfn, "Process kill counter: %d\n", proc_kill_cnt);
1606
1607         qed_schedule_recovery_handler(p_hwfn);
1608 }
1609
1610 static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn,
1611                                         struct qed_ptt *p_ptt,
1612                                         enum MFW_DRV_MSG_TYPE type)
1613 {
1614         enum qed_mcp_protocol_type stats_type;
1615         union qed_mcp_protocol_stats stats;
1616         struct qed_mcp_mb_params mb_params;
1617         u32 hsi_param;
1618
1619         switch (type) {
1620         case MFW_DRV_MSG_GET_LAN_STATS:
1621                 stats_type = QED_MCP_LAN_STATS;
1622                 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1623                 break;
1624         case MFW_DRV_MSG_GET_FCOE_STATS:
1625                 stats_type = QED_MCP_FCOE_STATS;
1626                 hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE;
1627                 break;
1628         case MFW_DRV_MSG_GET_ISCSI_STATS:
1629                 stats_type = QED_MCP_ISCSI_STATS;
1630                 hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI;
1631                 break;
1632         case MFW_DRV_MSG_GET_RDMA_STATS:
1633                 stats_type = QED_MCP_RDMA_STATS;
1634                 hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA;
1635                 break;
1636         default:
1637                 DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type);
1638                 return;
1639         }
1640
1641         qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats);
1642
1643         memset(&mb_params, 0, sizeof(mb_params));
1644         mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1645         mb_params.param = hsi_param;
1646         mb_params.p_data_src = &stats;
1647         mb_params.data_src_size = sizeof(stats);
1648         qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1649 }
1650
1651 static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1652 {
1653         struct qed_mcp_function_info *p_info;
1654         struct public_func shmem_info;
1655         u32 resp = 0, param = 0;
1656
1657         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1658
1659         qed_read_pf_bandwidth(p_hwfn, &shmem_info);
1660
1661         p_info = &p_hwfn->mcp_info->func_info;
1662
1663         qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min);
1664         qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max);
1665
1666         /* Acknowledge the MFW */
1667         qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1668                     &param);
1669 }
1670
1671 static void qed_mcp_update_stag(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1672 {
1673         struct public_func shmem_info;
1674         u32 resp = 0, param = 0;
1675
1676         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1677
1678         p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag &
1679                                                  FUNC_MF_CFG_OV_STAG_MASK;
1680         p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan;
1681         if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits)) {
1682                 if (p_hwfn->hw_info.ovlan != QED_MCP_VLAN_UNSET) {
1683                         qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE,
1684                                p_hwfn->hw_info.ovlan);
1685                         qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 1);
1686
1687                         /* Configure DB to add external vlan to EDPM packets */
1688                         qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 1);
1689                         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2,
1690                                p_hwfn->hw_info.ovlan);
1691                 } else {
1692                         qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 0);
1693                         qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, 0);
1694                         qed_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 0);
1695                         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 0);
1696                 }
1697
1698                 qed_sp_pf_update_stag(p_hwfn);
1699         }
1700
1701         DP_VERBOSE(p_hwfn, QED_MSG_SP, "ovlan = %d hw_mode = 0x%x\n",
1702                    p_hwfn->mcp_info->func_info.ovlan, p_hwfn->hw_info.hw_mode);
1703
1704         /* Acknowledge the MFW */
1705         qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0,
1706                     &resp, &param);
1707 }
1708
1709 static void qed_mcp_handle_fan_failure(struct qed_hwfn *p_hwfn,
1710                                        struct qed_ptt *p_ptt)
1711 {
1712         /* A single notification should be sent to upper driver in CMT mode */
1713         if (p_hwfn != QED_LEADING_HWFN(p_hwfn->cdev))
1714                 return;
1715
1716         qed_hw_err_notify(p_hwfn, p_ptt, QED_HW_ERR_FAN_FAIL,
1717                           "Fan failure was detected on the network interface card and it's going to be shut down.\n");
1718 }
1719
1720 struct qed_mdump_cmd_params {
1721         u32 cmd;
1722         void *p_data_src;
1723         u8 data_src_size;
1724         void *p_data_dst;
1725         u8 data_dst_size;
1726         u32 mcp_resp;
1727 };
1728
1729 static int
1730 qed_mcp_mdump_cmd(struct qed_hwfn *p_hwfn,
1731                   struct qed_ptt *p_ptt,
1732                   struct qed_mdump_cmd_params *p_mdump_cmd_params)
1733 {
1734         struct qed_mcp_mb_params mb_params;
1735         int rc;
1736
1737         memset(&mb_params, 0, sizeof(mb_params));
1738         mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD;
1739         mb_params.param = p_mdump_cmd_params->cmd;
1740         mb_params.p_data_src = p_mdump_cmd_params->p_data_src;
1741         mb_params.data_src_size = p_mdump_cmd_params->data_src_size;
1742         mb_params.p_data_dst = p_mdump_cmd_params->p_data_dst;
1743         mb_params.data_dst_size = p_mdump_cmd_params->data_dst_size;
1744         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1745         if (rc)
1746                 return rc;
1747
1748         p_mdump_cmd_params->mcp_resp = mb_params.mcp_resp;
1749
1750         if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) {
1751                 DP_INFO(p_hwfn,
1752                         "The mdump sub command is unsupported by the MFW [mdump_cmd 0x%x]\n",
1753                         p_mdump_cmd_params->cmd);
1754                 rc = -EOPNOTSUPP;
1755         } else if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
1756                 DP_INFO(p_hwfn,
1757                         "The mdump command is not supported by the MFW\n");
1758                 rc = -EOPNOTSUPP;
1759         }
1760
1761         return rc;
1762 }
1763
1764 static int qed_mcp_mdump_ack(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1765 {
1766         struct qed_mdump_cmd_params mdump_cmd_params;
1767
1768         memset(&mdump_cmd_params, 0, sizeof(mdump_cmd_params));
1769         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_ACK;
1770
1771         return qed_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1772 }
1773
1774 int
1775 qed_mcp_mdump_get_retain(struct qed_hwfn *p_hwfn,
1776                          struct qed_ptt *p_ptt,
1777                          struct mdump_retain_data_stc *p_mdump_retain)
1778 {
1779         struct qed_mdump_cmd_params mdump_cmd_params;
1780         int rc;
1781
1782         memset(&mdump_cmd_params, 0, sizeof(mdump_cmd_params));
1783         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_RETAIN;
1784         mdump_cmd_params.p_data_dst = p_mdump_retain;
1785         mdump_cmd_params.data_dst_size = sizeof(*p_mdump_retain);
1786
1787         rc = qed_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1788         if (rc)
1789                 return rc;
1790
1791         if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1792                 DP_INFO(p_hwfn,
1793                         "Failed to get the mdump retained data [mcp_resp 0x%x]\n",
1794                         mdump_cmd_params.mcp_resp);
1795                 return -EINVAL;
1796         }
1797
1798         return 0;
1799 }
1800
1801 static void qed_mcp_handle_critical_error(struct qed_hwfn *p_hwfn,
1802                                           struct qed_ptt *p_ptt)
1803 {
1804         struct mdump_retain_data_stc mdump_retain;
1805         int rc;
1806
1807         /* In CMT mode - no need for more than a single acknowledgment to the
1808          * MFW, and no more than a single notification to the upper driver.
1809          */
1810         if (p_hwfn != QED_LEADING_HWFN(p_hwfn->cdev))
1811                 return;
1812
1813         rc = qed_mcp_mdump_get_retain(p_hwfn, p_ptt, &mdump_retain);
1814         if (rc == 0 && mdump_retain.valid)
1815                 DP_NOTICE(p_hwfn,
1816                           "The MFW notified that a critical error occurred in the device [epoch 0x%08x, pf 0x%x, status 0x%08x]\n",
1817                           mdump_retain.epoch,
1818                           mdump_retain.pf, mdump_retain.status);
1819         else
1820                 DP_NOTICE(p_hwfn,
1821                           "The MFW notified that a critical error occurred in the device\n");
1822
1823         DP_NOTICE(p_hwfn,
1824                   "Acknowledging the notification to not allow the MFW crash dump [driver debug data collection is preferable]\n");
1825         qed_mcp_mdump_ack(p_hwfn, p_ptt);
1826
1827         qed_hw_err_notify(p_hwfn, p_ptt, QED_HW_ERR_HW_ATTN, NULL);
1828 }
1829
1830 void qed_mcp_read_ufp_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1831 {
1832         struct public_func shmem_info;
1833         u32 port_cfg, val;
1834
1835         if (!test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits))
1836                 return;
1837
1838         memset(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info));
1839         port_cfg = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1840                           offsetof(struct public_port, oem_cfg_port));
1841         val = (port_cfg & OEM_CFG_CHANNEL_TYPE_MASK) >>
1842                 OEM_CFG_CHANNEL_TYPE_OFFSET;
1843         if (val != OEM_CFG_CHANNEL_TYPE_STAGGED)
1844                 DP_NOTICE(p_hwfn,
1845                           "Incorrect UFP Channel type  %d port_id 0x%02x\n",
1846                           val, MFW_PORT(p_hwfn));
1847
1848         val = (port_cfg & OEM_CFG_SCHED_TYPE_MASK) >> OEM_CFG_SCHED_TYPE_OFFSET;
1849         if (val == OEM_CFG_SCHED_TYPE_ETS) {
1850                 p_hwfn->ufp_info.mode = QED_UFP_MODE_ETS;
1851         } else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW) {
1852                 p_hwfn->ufp_info.mode = QED_UFP_MODE_VNIC_BW;
1853         } else {
1854                 p_hwfn->ufp_info.mode = QED_UFP_MODE_UNKNOWN;
1855                 DP_NOTICE(p_hwfn,
1856                           "Unknown UFP scheduling mode %d port_id 0x%02x\n",
1857                           val, MFW_PORT(p_hwfn));
1858         }
1859
1860         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1861         val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_TC_MASK) >>
1862                 OEM_CFG_FUNC_TC_OFFSET;
1863         p_hwfn->ufp_info.tc = (u8)val;
1864         val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_HOST_PRI_CTRL_MASK) >>
1865                 OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET;
1866         if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC) {
1867                 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_VNIC;
1868         } else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS) {
1869                 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_OS;
1870         } else {
1871                 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_UNKNOWN;
1872                 DP_NOTICE(p_hwfn,
1873                           "Unknown Host priority control %d port_id 0x%02x\n",
1874                           val, MFW_PORT(p_hwfn));
1875         }
1876
1877         DP_NOTICE(p_hwfn,
1878                   "UFP shmem config: mode = %d tc = %d pri_type = %d port_id 0x%02x\n",
1879                   p_hwfn->ufp_info.mode, p_hwfn->ufp_info.tc,
1880                   p_hwfn->ufp_info.pri_type, MFW_PORT(p_hwfn));
1881 }
1882
1883 static int
1884 qed_mcp_handle_ufp_event(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1885 {
1886         qed_mcp_read_ufp_config(p_hwfn, p_ptt);
1887
1888         if (p_hwfn->ufp_info.mode == QED_UFP_MODE_VNIC_BW) {
1889                 p_hwfn->qm_info.ooo_tc = p_hwfn->ufp_info.tc;
1890                 qed_hw_info_set_offload_tc(&p_hwfn->hw_info,
1891                                            p_hwfn->ufp_info.tc);
1892
1893                 qed_qm_reconf(p_hwfn, p_ptt);
1894         } else if (p_hwfn->ufp_info.mode == QED_UFP_MODE_ETS) {
1895                 /* Merge UFP TC with the dcbx TC data */
1896                 qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1897                                           QED_DCBX_OPERATIONAL_MIB);
1898         } else {
1899                 DP_ERR(p_hwfn, "Invalid sched type, discard the UFP config\n");
1900                 return -EINVAL;
1901         }
1902
1903         /* update storm FW with negotiation results */
1904         qed_sp_pf_update_ufp(p_hwfn);
1905
1906         /* update stag pcp value */
1907         qed_sp_pf_update_stag(p_hwfn);
1908
1909         return 0;
1910 }
1911
1912 int qed_mcp_handle_events(struct qed_hwfn *p_hwfn,
1913                           struct qed_ptt *p_ptt)
1914 {
1915         struct qed_mcp_info *info = p_hwfn->mcp_info;
1916         int rc = 0;
1917         bool found = false;
1918         u16 i;
1919
1920         DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n");
1921
1922         /* Read Messages from MFW */
1923         qed_mcp_read_mb(p_hwfn, p_ptt);
1924
1925         /* Compare current messages to old ones */
1926         for (i = 0; i < info->mfw_mb_length; i++) {
1927                 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1928                         continue;
1929
1930                 found = true;
1931
1932                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1933                            "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1934                            i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1935
1936                 switch (i) {
1937                 case MFW_DRV_MSG_LINK_CHANGE:
1938                         qed_mcp_handle_link_change(p_hwfn, p_ptt, false);
1939                         break;
1940                 case MFW_DRV_MSG_VF_DISABLED:
1941                         qed_mcp_handle_vf_flr(p_hwfn, p_ptt);
1942                         break;
1943                 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1944                         qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1945                                                   QED_DCBX_REMOTE_LLDP_MIB);
1946                         break;
1947                 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1948                         qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1949                                                   QED_DCBX_REMOTE_MIB);
1950                         break;
1951                 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1952                         qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1953                                                   QED_DCBX_OPERATIONAL_MIB);
1954                         break;
1955                 case MFW_DRV_MSG_OEM_CFG_UPDATE:
1956                         qed_mcp_handle_ufp_event(p_hwfn, p_ptt);
1957                         break;
1958                 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1959                         qed_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1960                         break;
1961                 case MFW_DRV_MSG_ERROR_RECOVERY:
1962                         qed_mcp_handle_process_kill(p_hwfn, p_ptt);
1963                         break;
1964                 case MFW_DRV_MSG_GET_LAN_STATS:
1965                 case MFW_DRV_MSG_GET_FCOE_STATS:
1966                 case MFW_DRV_MSG_GET_ISCSI_STATS:
1967                 case MFW_DRV_MSG_GET_RDMA_STATS:
1968                         qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1969                         break;
1970                 case MFW_DRV_MSG_BW_UPDATE:
1971                         qed_mcp_update_bw(p_hwfn, p_ptt);
1972                         break;
1973                 case MFW_DRV_MSG_S_TAG_UPDATE:
1974                         qed_mcp_update_stag(p_hwfn, p_ptt);
1975                         break;
1976                 case MFW_DRV_MSG_FAILURE_DETECTED:
1977                         qed_mcp_handle_fan_failure(p_hwfn, p_ptt);
1978                         break;
1979                 case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED:
1980                         qed_mcp_handle_critical_error(p_hwfn, p_ptt);
1981                         break;
1982                 case MFW_DRV_MSG_GET_TLV_REQ:
1983                         qed_mfw_tlv_req(p_hwfn);
1984                         break;
1985                 default:
1986                         DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
1987                         rc = -EINVAL;
1988                 }
1989         }
1990
1991         /* ACK everything */
1992         for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1993                 __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]);
1994
1995                 /* MFW expect answer in BE, so we force write in that format */
1996                 qed_wr(p_hwfn, p_ptt,
1997                        info->mfw_mb_addr + sizeof(u32) +
1998                        MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1999                        sizeof(u32) + i * sizeof(u32),
2000                        (__force u32)val);
2001         }
2002
2003         if (!found) {
2004                 DP_NOTICE(p_hwfn,
2005                           "Received an MFW message indication but no new message!\n");
2006                 rc = -EINVAL;
2007         }
2008
2009         /* Copy the new mfw messages into the shadow */
2010         memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
2011
2012         return rc;
2013 }
2014
2015 int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn,
2016                         struct qed_ptt *p_ptt,
2017                         u32 *p_mfw_ver, u32 *p_running_bundle_id)
2018 {
2019         u32 global_offsize;
2020
2021         if (IS_VF(p_hwfn->cdev)) {
2022                 if (p_hwfn->vf_iov_info) {
2023                         struct pfvf_acquire_resp_tlv *p_resp;
2024
2025                         p_resp = &p_hwfn->vf_iov_info->acquire_resp;
2026                         *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
2027                         return 0;
2028                 } else {
2029                         DP_VERBOSE(p_hwfn,
2030                                    QED_MSG_IOV,
2031                                    "VF requested MFW version prior to ACQUIRE\n");
2032                         return -EINVAL;
2033                 }
2034         }
2035
2036         global_offsize = qed_rd(p_hwfn, p_ptt,
2037                                 SECTION_OFFSIZE_ADDR(p_hwfn->
2038                                                      mcp_info->public_base,
2039                                                      PUBLIC_GLOBAL));
2040         *p_mfw_ver =
2041             qed_rd(p_hwfn, p_ptt,
2042                    SECTION_ADDR(global_offsize,
2043                                 0) + offsetof(struct public_global, mfw_ver));
2044
2045         if (p_running_bundle_id != NULL) {
2046                 *p_running_bundle_id = qed_rd(p_hwfn, p_ptt,
2047                                               SECTION_ADDR(global_offsize, 0) +
2048                                               offsetof(struct public_global,
2049                                                        running_bundle_id));
2050         }
2051
2052         return 0;
2053 }
2054
2055 int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn,
2056                         struct qed_ptt *p_ptt, u32 *p_mbi_ver)
2057 {
2058         u32 nvm_cfg_addr, nvm_cfg1_offset, mbi_ver_addr;
2059
2060         if (IS_VF(p_hwfn->cdev))
2061                 return -EINVAL;
2062
2063         /* Read the address of the nvm_cfg */
2064         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2065         if (!nvm_cfg_addr) {
2066                 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
2067                 return -EINVAL;
2068         }
2069
2070         /* Read the offset of nvm_cfg1 */
2071         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2072
2073         mbi_ver_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2074                        offsetof(struct nvm_cfg1, glob) +
2075                        offsetof(struct nvm_cfg1_glob, mbi_version);
2076         *p_mbi_ver = qed_rd(p_hwfn, p_ptt,
2077                             mbi_ver_addr) &
2078                      (NVM_CFG1_GLOB_MBI_VERSION_0_MASK |
2079                       NVM_CFG1_GLOB_MBI_VERSION_1_MASK |
2080                       NVM_CFG1_GLOB_MBI_VERSION_2_MASK);
2081
2082         return 0;
2083 }
2084
2085 int qed_mcp_get_media_type(struct qed_hwfn *p_hwfn,
2086                            struct qed_ptt *p_ptt, u32 *p_media_type)
2087 {
2088         *p_media_type = MEDIA_UNSPECIFIED;
2089
2090         if (IS_VF(p_hwfn->cdev))
2091                 return -EINVAL;
2092
2093         if (!qed_mcp_is_init(p_hwfn)) {
2094                 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
2095                 return -EBUSY;
2096         }
2097
2098         if (!p_ptt) {
2099                 *p_media_type = MEDIA_UNSPECIFIED;
2100                 return -EINVAL;
2101         }
2102
2103         *p_media_type = qed_rd(p_hwfn, p_ptt,
2104                                p_hwfn->mcp_info->port_addr +
2105                                offsetof(struct public_port,
2106                                         media_type));
2107
2108         return 0;
2109 }
2110
2111 int qed_mcp_get_transceiver_data(struct qed_hwfn *p_hwfn,
2112                                  struct qed_ptt *p_ptt,
2113                                  u32 *p_transceiver_state,
2114                                  u32 *p_transceiver_type)
2115 {
2116         u32 transceiver_info;
2117
2118         *p_transceiver_type = ETH_TRANSCEIVER_TYPE_NONE;
2119         *p_transceiver_state = ETH_TRANSCEIVER_STATE_UPDATING;
2120
2121         if (IS_VF(p_hwfn->cdev))
2122                 return -EINVAL;
2123
2124         if (!qed_mcp_is_init(p_hwfn)) {
2125                 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
2126                 return -EBUSY;
2127         }
2128
2129         transceiver_info = qed_rd(p_hwfn, p_ptt,
2130                                   p_hwfn->mcp_info->port_addr +
2131                                   offsetof(struct public_port,
2132                                            transceiver_data));
2133
2134         *p_transceiver_state = (transceiver_info &
2135                                 ETH_TRANSCEIVER_STATE_MASK) >>
2136                                 ETH_TRANSCEIVER_STATE_OFFSET;
2137
2138         if (*p_transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
2139                 *p_transceiver_type = (transceiver_info &
2140                                        ETH_TRANSCEIVER_TYPE_MASK) >>
2141                                        ETH_TRANSCEIVER_TYPE_OFFSET;
2142         else
2143                 *p_transceiver_type = ETH_TRANSCEIVER_TYPE_UNKNOWN;
2144
2145         return 0;
2146 }
2147 static bool qed_is_transceiver_ready(u32 transceiver_state,
2148                                      u32 transceiver_type)
2149 {
2150         if ((transceiver_state & ETH_TRANSCEIVER_STATE_PRESENT) &&
2151             ((transceiver_state & ETH_TRANSCEIVER_STATE_UPDATING) == 0x0) &&
2152             (transceiver_type != ETH_TRANSCEIVER_TYPE_NONE))
2153                 return true;
2154
2155         return false;
2156 }
2157
2158 int qed_mcp_trans_speed_mask(struct qed_hwfn *p_hwfn,
2159                              struct qed_ptt *p_ptt, u32 *p_speed_mask)
2160 {
2161         u32 transceiver_type, transceiver_state;
2162         int ret;
2163
2164         ret = qed_mcp_get_transceiver_data(p_hwfn, p_ptt, &transceiver_state,
2165                                            &transceiver_type);
2166         if (ret)
2167                 return ret;
2168
2169         if (qed_is_transceiver_ready(transceiver_state, transceiver_type) ==
2170                                      false)
2171                 return -EINVAL;
2172
2173         switch (transceiver_type) {
2174         case ETH_TRANSCEIVER_TYPE_1G_LX:
2175         case ETH_TRANSCEIVER_TYPE_1G_SX:
2176         case ETH_TRANSCEIVER_TYPE_1G_PCC:
2177         case ETH_TRANSCEIVER_TYPE_1G_ACC:
2178         case ETH_TRANSCEIVER_TYPE_1000BASET:
2179                 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
2180                 break;
2181         case ETH_TRANSCEIVER_TYPE_10G_SR:
2182         case ETH_TRANSCEIVER_TYPE_10G_LR:
2183         case ETH_TRANSCEIVER_TYPE_10G_LRM:
2184         case ETH_TRANSCEIVER_TYPE_10G_ER:
2185         case ETH_TRANSCEIVER_TYPE_10G_PCC:
2186         case ETH_TRANSCEIVER_TYPE_10G_ACC:
2187         case ETH_TRANSCEIVER_TYPE_4x10G:
2188                 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
2189                 break;
2190         case ETH_TRANSCEIVER_TYPE_40G_LR4:
2191         case ETH_TRANSCEIVER_TYPE_40G_SR4:
2192         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR:
2193         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR:
2194                 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G |
2195                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
2196                 break;
2197         case ETH_TRANSCEIVER_TYPE_100G_AOC:
2198         case ETH_TRANSCEIVER_TYPE_100G_SR4:
2199         case ETH_TRANSCEIVER_TYPE_100G_LR4:
2200         case ETH_TRANSCEIVER_TYPE_100G_ER4:
2201         case ETH_TRANSCEIVER_TYPE_100G_ACC:
2202                 *p_speed_mask =
2203                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G |
2204                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G;
2205                 break;
2206         case ETH_TRANSCEIVER_TYPE_25G_SR:
2207         case ETH_TRANSCEIVER_TYPE_25G_LR:
2208         case ETH_TRANSCEIVER_TYPE_25G_AOC:
2209         case ETH_TRANSCEIVER_TYPE_25G_ACC_S:
2210         case ETH_TRANSCEIVER_TYPE_25G_ACC_M:
2211         case ETH_TRANSCEIVER_TYPE_25G_ACC_L:
2212                 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G;
2213                 break;
2214         case ETH_TRANSCEIVER_TYPE_25G_CA_N:
2215         case ETH_TRANSCEIVER_TYPE_25G_CA_S:
2216         case ETH_TRANSCEIVER_TYPE_25G_CA_L:
2217         case ETH_TRANSCEIVER_TYPE_4x25G_CR:
2218                 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G |
2219                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G |
2220                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
2221                 break;
2222         case ETH_TRANSCEIVER_TYPE_40G_CR4:
2223         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR:
2224                 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G |
2225                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G |
2226                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
2227                 break;
2228         case ETH_TRANSCEIVER_TYPE_100G_CR4:
2229         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR:
2230                 *p_speed_mask =
2231                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G |
2232                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G |
2233                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G |
2234                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G |
2235                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G |
2236                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G |
2237                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
2238                 break;
2239         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR:
2240         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR:
2241         case ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC:
2242                 *p_speed_mask =
2243                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G |
2244                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G |
2245                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G |
2246                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
2247                 break;
2248         case ETH_TRANSCEIVER_TYPE_XLPPI:
2249                 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G;
2250                 break;
2251         case ETH_TRANSCEIVER_TYPE_10G_BASET:
2252                 *p_speed_mask = NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G |
2253                     NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
2254                 break;
2255         default:
2256                 DP_INFO(p_hwfn, "Unknown transceiver type 0x%x\n",
2257                         transceiver_type);
2258                 *p_speed_mask = 0xff;
2259                 break;
2260         }
2261
2262         return 0;
2263 }
2264
2265 int qed_mcp_get_board_config(struct qed_hwfn *p_hwfn,
2266                              struct qed_ptt *p_ptt, u32 *p_board_config)
2267 {
2268         u32 nvm_cfg_addr, nvm_cfg1_offset, port_cfg_addr;
2269
2270         if (IS_VF(p_hwfn->cdev))
2271                 return -EINVAL;
2272
2273         if (!qed_mcp_is_init(p_hwfn)) {
2274                 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
2275                 return -EBUSY;
2276         }
2277         if (!p_ptt) {
2278                 *p_board_config = NVM_CFG1_PORT_PORT_TYPE_UNDEFINED;
2279                 return -EINVAL;
2280         }
2281
2282         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2283         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2284         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2285                         offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2286         *p_board_config = qed_rd(p_hwfn, p_ptt,
2287                                  port_cfg_addr +
2288                                  offsetof(struct nvm_cfg1_port,
2289                                           board_cfg));
2290
2291         return 0;
2292 }
2293
2294 /* Old MFW has a global configuration for all PFs regarding RDMA support */
2295 static void
2296 qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn,
2297                                enum qed_pci_personality *p_proto)
2298 {
2299         /* There wasn't ever a legacy MFW that published iwarp.
2300          * So at this point, this is either plain l2 or RoCE.
2301          */
2302         if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities))
2303                 *p_proto = QED_PCI_ETH_ROCE;
2304         else
2305                 *p_proto = QED_PCI_ETH;
2306
2307         DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
2308                    "According to Legacy capabilities, L2 personality is %08x\n",
2309                    (u32) *p_proto);
2310 }
2311
2312 static int
2313 qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn,
2314                             struct qed_ptt *p_ptt,
2315                             enum qed_pci_personality *p_proto)
2316 {
2317         u32 resp = 0, param = 0;
2318         int rc;
2319
2320         rc = qed_mcp_cmd(p_hwfn, p_ptt,
2321                          DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, &param);
2322         if (rc)
2323                 return rc;
2324         if (resp != FW_MSG_CODE_OK) {
2325                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
2326                            "MFW lacks support for command; Returns %08x\n",
2327                            resp);
2328                 return -EINVAL;
2329         }
2330
2331         switch (param) {
2332         case FW_MB_PARAM_GET_PF_RDMA_NONE:
2333                 *p_proto = QED_PCI_ETH;
2334                 break;
2335         case FW_MB_PARAM_GET_PF_RDMA_ROCE:
2336                 *p_proto = QED_PCI_ETH_ROCE;
2337                 break;
2338         case FW_MB_PARAM_GET_PF_RDMA_IWARP:
2339                 *p_proto = QED_PCI_ETH_IWARP;
2340                 break;
2341         case FW_MB_PARAM_GET_PF_RDMA_BOTH:
2342                 *p_proto = QED_PCI_ETH_RDMA;
2343                 break;
2344         default:
2345                 DP_NOTICE(p_hwfn,
2346                           "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n",
2347                           param);
2348                 return -EINVAL;
2349         }
2350
2351         DP_VERBOSE(p_hwfn,
2352                    NETIF_MSG_IFUP,
2353                    "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
2354                    (u32) *p_proto, resp, param);
2355         return 0;
2356 }
2357
2358 static int
2359 qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn,
2360                         struct public_func *p_info,
2361                         struct qed_ptt *p_ptt,
2362                         enum qed_pci_personality *p_proto)
2363 {
2364         int rc = 0;
2365
2366         switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
2367         case FUNC_MF_CFG_PROTOCOL_ETHERNET:
2368                 if (!IS_ENABLED(CONFIG_QED_RDMA))
2369                         *p_proto = QED_PCI_ETH;
2370                 else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto))
2371                         qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
2372                 break;
2373         case FUNC_MF_CFG_PROTOCOL_ISCSI:
2374                 *p_proto = QED_PCI_ISCSI;
2375                 break;
2376         case FUNC_MF_CFG_PROTOCOL_FCOE:
2377                 *p_proto = QED_PCI_FCOE;
2378                 break;
2379         case FUNC_MF_CFG_PROTOCOL_ROCE:
2380                 DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n");
2381         /* Fallthrough */
2382         default:
2383                 rc = -EINVAL;
2384         }
2385
2386         return rc;
2387 }
2388
2389 int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn,
2390                                  struct qed_ptt *p_ptt)
2391 {
2392         struct qed_mcp_function_info *info;
2393         struct public_func shmem_info;
2394
2395         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
2396         info = &p_hwfn->mcp_info->func_info;
2397
2398         info->pause_on_host = (shmem_info.config &
2399                                FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
2400
2401         if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2402                                     &info->protocol)) {
2403                 DP_ERR(p_hwfn, "Unknown personality %08x\n",
2404                        (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
2405                 return -EINVAL;
2406         }
2407
2408         qed_read_pf_bandwidth(p_hwfn, &shmem_info);
2409
2410         if (shmem_info.mac_upper || shmem_info.mac_lower) {
2411                 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
2412                 info->mac[1] = (u8)(shmem_info.mac_upper);
2413                 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
2414                 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
2415                 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
2416                 info->mac[5] = (u8)(shmem_info.mac_lower);
2417
2418                 /* Store primary MAC for later possible WoL */
2419                 memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN);
2420         } else {
2421                 DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n");
2422         }
2423
2424         info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_lower |
2425                          (((u64)shmem_info.fcoe_wwn_port_name_upper) << 32);
2426         info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_lower |
2427                          (((u64)shmem_info.fcoe_wwn_node_name_upper) << 32);
2428
2429         info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
2430
2431         info->mtu = (u16)shmem_info.mtu_size;
2432
2433         p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE;
2434         p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT;
2435         if (qed_mcp_is_init(p_hwfn)) {
2436                 u32 resp = 0, param = 0;
2437                 int rc;
2438
2439                 rc = qed_mcp_cmd(p_hwfn, p_ptt,
2440                                  DRV_MSG_CODE_OS_WOL, 0, &resp, &param);
2441                 if (rc)
2442                         return rc;
2443                 if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED)
2444                         p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME;
2445         }
2446
2447         DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP),
2448                    "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x wol %02x\n",
2449                 info->pause_on_host, info->protocol,
2450                 info->bandwidth_min, info->bandwidth_max,
2451                 info->mac[0], info->mac[1], info->mac[2],
2452                 info->mac[3], info->mac[4], info->mac[5],
2453                 info->wwn_port, info->wwn_node,
2454                 info->ovlan, (u8)p_hwfn->hw_info.b_wol_support);
2455
2456         return 0;
2457 }
2458
2459 struct qed_mcp_link_params
2460 *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn)
2461 {
2462         if (!p_hwfn || !p_hwfn->mcp_info)
2463                 return NULL;
2464         return &p_hwfn->mcp_info->link_input;
2465 }
2466
2467 struct qed_mcp_link_state
2468 *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn)
2469 {
2470         if (!p_hwfn || !p_hwfn->mcp_info)
2471                 return NULL;
2472         return &p_hwfn->mcp_info->link_output;
2473 }
2474
2475 struct qed_mcp_link_capabilities
2476 *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn)
2477 {
2478         if (!p_hwfn || !p_hwfn->mcp_info)
2479                 return NULL;
2480         return &p_hwfn->mcp_info->link_capabilities;
2481 }
2482
2483 int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2484 {
2485         u32 resp = 0, param = 0;
2486         int rc;
2487
2488         rc = qed_mcp_cmd(p_hwfn, p_ptt,
2489                          DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, &param);
2490
2491         /* Wait for the drain to complete before returning */
2492         msleep(1020);
2493
2494         return rc;
2495 }
2496
2497 int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn,
2498                            struct qed_ptt *p_ptt, u32 *p_flash_size)
2499 {
2500         u32 flash_size;
2501
2502         if (IS_VF(p_hwfn->cdev))
2503                 return -EINVAL;
2504
2505         flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
2506         flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
2507                       MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
2508         flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
2509
2510         *p_flash_size = flash_size;
2511
2512         return 0;
2513 }
2514
2515 int qed_start_recovery_process(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2516 {
2517         struct qed_dev *cdev = p_hwfn->cdev;
2518
2519         if (cdev->recov_in_prog) {
2520                 DP_NOTICE(p_hwfn,
2521                           "Avoid triggering a recovery since such a process is already in progress\n");
2522                 return -EAGAIN;
2523         }
2524
2525         DP_NOTICE(p_hwfn, "Triggering a recovery process\n");
2526         qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
2527
2528         return 0;
2529 }
2530
2531 #define QED_RECOVERY_PROLOG_SLEEP_MS    100
2532
2533 int qed_recovery_prolog(struct qed_dev *cdev)
2534 {
2535         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2536         struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
2537         int rc;
2538
2539         /* Allow ongoing PCIe transactions to complete */
2540         msleep(QED_RECOVERY_PROLOG_SLEEP_MS);
2541
2542         /* Clear the PF's internal FID_enable in the PXP */
2543         rc = qed_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
2544         if (rc)
2545                 DP_NOTICE(p_hwfn,
2546                           "qed_pglueb_set_pfid_enable() failed. rc = %d.\n",
2547                           rc);
2548
2549         return rc;
2550 }
2551
2552 static int
2553 qed_mcp_config_vf_msix_bb(struct qed_hwfn *p_hwfn,
2554                           struct qed_ptt *p_ptt, u8 vf_id, u8 num)
2555 {
2556         u32 resp = 0, param = 0, rc_param = 0;
2557         int rc;
2558
2559         /* Only Leader can configure MSIX, and need to take CMT into account */
2560         if (!IS_LEAD_HWFN(p_hwfn))
2561                 return 0;
2562         num *= p_hwfn->cdev->num_hwfns;
2563
2564         param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
2565                  DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
2566         param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
2567                  DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
2568
2569         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
2570                          &resp, &rc_param);
2571
2572         if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
2573                 DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id);
2574                 rc = -EINVAL;
2575         } else {
2576                 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2577                            "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
2578                            num, vf_id);
2579         }
2580
2581         return rc;
2582 }
2583
2584 static int
2585 qed_mcp_config_vf_msix_ah(struct qed_hwfn *p_hwfn,
2586                           struct qed_ptt *p_ptt, u8 num)
2587 {
2588         u32 resp = 0, param = num, rc_param = 0;
2589         int rc;
2590
2591         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX,
2592                          param, &resp, &rc_param);
2593
2594         if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) {
2595                 DP_NOTICE(p_hwfn, "MFW failed to set MSI-X for VFs\n");
2596                 rc = -EINVAL;
2597         } else {
2598                 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2599                            "Requested 0x%02x MSI-x interrupts for VFs\n", num);
2600         }
2601
2602         return rc;
2603 }
2604
2605 int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn,
2606                            struct qed_ptt *p_ptt, u8 vf_id, u8 num)
2607 {
2608         if (QED_IS_BB(p_hwfn->cdev))
2609                 return qed_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num);
2610         else
2611                 return qed_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num);
2612 }
2613
2614 int
2615 qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn,
2616                          struct qed_ptt *p_ptt,
2617                          struct qed_mcp_drv_version *p_ver)
2618 {
2619         struct qed_mcp_mb_params mb_params;
2620         struct drv_version_stc drv_version;
2621         __be32 val;
2622         u32 i;
2623         int rc;
2624
2625         memset(&drv_version, 0, sizeof(drv_version));
2626         drv_version.version = p_ver->version;
2627         for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) {
2628                 val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)]));
2629                 *(__be32 *)&drv_version.name[i * sizeof(u32)] = val;
2630         }
2631
2632         memset(&mb_params, 0, sizeof(mb_params));
2633         mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
2634         mb_params.p_data_src = &drv_version;
2635         mb_params.data_src_size = sizeof(drv_version);
2636         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2637         if (rc)
2638                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2639
2640         return rc;
2641 }
2642
2643 /* A maximal 100 msec waiting time for the MCP to halt */
2644 #define QED_MCP_HALT_SLEEP_MS           10
2645 #define QED_MCP_HALT_MAX_RETRIES        10
2646
2647 int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2648 {
2649         u32 resp = 0, param = 0, cpu_state, cnt = 0;
2650         int rc;
2651
2652         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
2653                          &param);
2654         if (rc) {
2655                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2656                 return rc;
2657         }
2658
2659         do {
2660                 msleep(QED_MCP_HALT_SLEEP_MS);
2661                 cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
2662                 if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED)
2663                         break;
2664         } while (++cnt < QED_MCP_HALT_MAX_RETRIES);
2665
2666         if (cnt == QED_MCP_HALT_MAX_RETRIES) {
2667                 DP_NOTICE(p_hwfn,
2668                           "Failed to halt the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
2669                           qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state);
2670                 return -EBUSY;
2671         }
2672
2673         qed_mcp_cmd_set_blocking(p_hwfn, true);
2674
2675         return 0;
2676 }
2677
2678 #define QED_MCP_RESUME_SLEEP_MS 10
2679
2680 int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2681 {
2682         u32 cpu_mode, cpu_state;
2683
2684         qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
2685
2686         cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2687         cpu_mode &= ~MCP_REG_CPU_MODE_SOFT_HALT;
2688         qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, cpu_mode);
2689         msleep(QED_MCP_RESUME_SLEEP_MS);
2690         cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
2691
2692         if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) {
2693                 DP_NOTICE(p_hwfn,
2694                           "Failed to resume the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
2695                           cpu_mode, cpu_state);
2696                 return -EBUSY;
2697         }
2698
2699         qed_mcp_cmd_set_blocking(p_hwfn, false);
2700
2701         return 0;
2702 }
2703
2704 int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn,
2705                                      struct qed_ptt *p_ptt,
2706                                      enum qed_ov_client client)
2707 {
2708         u32 resp = 0, param = 0;
2709         u32 drv_mb_param;
2710         int rc;
2711
2712         switch (client) {
2713         case QED_OV_CLIENT_DRV:
2714                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
2715                 break;
2716         case QED_OV_CLIENT_USER:
2717                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
2718                 break;
2719         case QED_OV_CLIENT_VENDOR_SPEC:
2720                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
2721                 break;
2722         default:
2723                 DP_NOTICE(p_hwfn, "Invalid client type %d\n", client);
2724                 return -EINVAL;
2725         }
2726
2727         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
2728                          drv_mb_param, &resp, &param);
2729         if (rc)
2730                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2731
2732         return rc;
2733 }
2734
2735 int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn,
2736                                    struct qed_ptt *p_ptt,
2737                                    enum qed_ov_driver_state drv_state)
2738 {
2739         u32 resp = 0, param = 0;
2740         u32 drv_mb_param;
2741         int rc;
2742
2743         switch (drv_state) {
2744         case QED_OV_DRIVER_STATE_NOT_LOADED:
2745                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
2746                 break;
2747         case QED_OV_DRIVER_STATE_DISABLED:
2748                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
2749                 break;
2750         case QED_OV_DRIVER_STATE_ACTIVE:
2751                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
2752                 break;
2753         default:
2754                 DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state);
2755                 return -EINVAL;
2756         }
2757
2758         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
2759                          drv_mb_param, &resp, &param);
2760         if (rc)
2761                 DP_ERR(p_hwfn, "Failed to send driver state\n");
2762
2763         return rc;
2764 }
2765
2766 int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn,
2767                           struct qed_ptt *p_ptt, u16 mtu)
2768 {
2769         u32 resp = 0, param = 0;
2770         u32 drv_mb_param;
2771         int rc;
2772
2773         drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT;
2774         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU,
2775                          drv_mb_param, &resp, &param);
2776         if (rc)
2777                 DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc);
2778
2779         return rc;
2780 }
2781
2782 int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn,
2783                           struct qed_ptt *p_ptt, u8 *mac)
2784 {
2785         struct qed_mcp_mb_params mb_params;
2786         u32 mfw_mac[2];
2787         int rc;
2788
2789         memset(&mb_params, 0, sizeof(mb_params));
2790         mb_params.cmd = DRV_MSG_CODE_SET_VMAC;
2791         mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC <<
2792                           DRV_MSG_CODE_VMAC_TYPE_SHIFT;
2793         mb_params.param |= MCP_PF_ID(p_hwfn);
2794
2795         /* MCP is BE, and on LE platforms PCI would swap access to SHMEM
2796          * in 32-bit granularity.
2797          * So the MAC has to be set in native order [and not byte order],
2798          * otherwise it would be read incorrectly by MFW after swap.
2799          */
2800         mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3];
2801         mfw_mac[1] = mac[4] << 24 | mac[5] << 16;
2802
2803         mb_params.p_data_src = (u8 *)mfw_mac;
2804         mb_params.data_src_size = 8;
2805         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2806         if (rc)
2807                 DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc);
2808
2809         /* Store primary MAC for later possible WoL */
2810         memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN);
2811
2812         return rc;
2813 }
2814
2815 int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn,
2816                           struct qed_ptt *p_ptt, enum qed_ov_wol wol)
2817 {
2818         u32 resp = 0, param = 0;
2819         u32 drv_mb_param;
2820         int rc;
2821
2822         if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) {
2823                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
2824                            "Can't change WoL configuration when WoL isn't supported\n");
2825                 return -EINVAL;
2826         }
2827
2828         switch (wol) {
2829         case QED_OV_WOL_DEFAULT:
2830                 drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT;
2831                 break;
2832         case QED_OV_WOL_DISABLED:
2833                 drv_mb_param = DRV_MB_PARAM_WOL_DISABLED;
2834                 break;
2835         case QED_OV_WOL_ENABLED:
2836                 drv_mb_param = DRV_MB_PARAM_WOL_ENABLED;
2837                 break;
2838         default:
2839                 DP_ERR(p_hwfn, "Invalid wol state %d\n", wol);
2840                 return -EINVAL;
2841         }
2842
2843         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL,
2844                          drv_mb_param, &resp, &param);
2845         if (rc)
2846                 DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc);
2847
2848         /* Store the WoL update for a future unload */
2849         p_hwfn->cdev->wol_config = (u8)wol;
2850
2851         return rc;
2852 }
2853
2854 int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn,
2855                               struct qed_ptt *p_ptt,
2856                               enum qed_ov_eswitch eswitch)
2857 {
2858         u32 resp = 0, param = 0;
2859         u32 drv_mb_param;
2860         int rc;
2861
2862         switch (eswitch) {
2863         case QED_OV_ESWITCH_NONE:
2864                 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE;
2865                 break;
2866         case QED_OV_ESWITCH_VEB:
2867                 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB;
2868                 break;
2869         case QED_OV_ESWITCH_VEPA:
2870                 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA;
2871                 break;
2872         default:
2873                 DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch);
2874                 return -EINVAL;
2875         }
2876
2877         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE,
2878                          drv_mb_param, &resp, &param);
2879         if (rc)
2880                 DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc);
2881
2882         return rc;
2883 }
2884
2885 int qed_mcp_set_led(struct qed_hwfn *p_hwfn,
2886                     struct qed_ptt *p_ptt, enum qed_led_mode mode)
2887 {
2888         u32 resp = 0, param = 0, drv_mb_param;
2889         int rc;
2890
2891         switch (mode) {
2892         case QED_LED_MODE_ON:
2893                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2894                 break;
2895         case QED_LED_MODE_OFF:
2896                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2897                 break;
2898         case QED_LED_MODE_RESTORE:
2899                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2900                 break;
2901         default:
2902                 DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode);
2903                 return -EINVAL;
2904         }
2905
2906         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2907                          drv_mb_param, &resp, &param);
2908
2909         return rc;
2910 }
2911
2912 int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn,
2913                           struct qed_ptt *p_ptt, u32 mask_parities)
2914 {
2915         u32 resp = 0, param = 0;
2916         int rc;
2917
2918         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2919                          mask_parities, &resp, &param);
2920
2921         if (rc) {
2922                 DP_ERR(p_hwfn,
2923                        "MCP response failure for mask parities, aborting\n");
2924         } else if (resp != FW_MSG_CODE_OK) {
2925                 DP_ERR(p_hwfn,
2926                        "MCP did not acknowledge mask parity request. Old MFW?\n");
2927                 rc = -EINVAL;
2928         }
2929
2930         return rc;
2931 }
2932
2933 int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len)
2934 {
2935         u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0;
2936         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2937         u32 resp = 0, resp_param = 0;
2938         struct qed_ptt *p_ptt;
2939         int rc = 0;
2940
2941         p_ptt = qed_ptt_acquire(p_hwfn);
2942         if (!p_ptt)
2943                 return -EBUSY;
2944
2945         while (bytes_left > 0) {
2946                 bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN);
2947
2948                 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2949                                         DRV_MSG_CODE_NVM_READ_NVRAM,
2950                                         addr + offset +
2951                                         (bytes_to_copy <<
2952                                          DRV_MB_PARAM_NVM_LEN_OFFSET),
2953                                         &resp, &resp_param,
2954                                         &read_len,
2955                                         (u32 *)(p_buf + offset));
2956
2957                 if (rc || (resp != FW_MSG_CODE_NVM_OK)) {
2958                         DP_NOTICE(cdev, "MCP command rc = %d\n", rc);
2959                         break;
2960                 }
2961
2962                 /* This can be a lengthy process, and it's possible scheduler
2963                  * isn't preemptable. Sleep a bit to prevent CPU hogging.
2964                  */
2965                 if (bytes_left % 0x1000 <
2966                     (bytes_left - read_len) % 0x1000)
2967                         usleep_range(1000, 2000);
2968
2969                 offset += read_len;
2970                 bytes_left -= read_len;
2971         }
2972
2973         cdev->mcp_nvm_resp = resp;
2974         qed_ptt_release(p_hwfn, p_ptt);
2975
2976         return rc;
2977 }
2978
2979 int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf)
2980 {
2981         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2982         struct qed_ptt *p_ptt;
2983
2984         p_ptt = qed_ptt_acquire(p_hwfn);
2985         if (!p_ptt)
2986                 return -EBUSY;
2987
2988         memcpy(p_buf, &cdev->mcp_nvm_resp, sizeof(cdev->mcp_nvm_resp));
2989         qed_ptt_release(p_hwfn, p_ptt);
2990
2991         return 0;
2992 }
2993
2994 int qed_mcp_nvm_write(struct qed_dev *cdev,
2995                       u32 cmd, u32 addr, u8 *p_buf, u32 len)
2996 {
2997         u32 buf_idx = 0, buf_size, nvm_cmd, nvm_offset, resp = 0, param;
2998         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2999         struct qed_ptt *p_ptt;
3000         int rc = -EINVAL;
3001
3002         p_ptt = qed_ptt_acquire(p_hwfn);
3003         if (!p_ptt)
3004                 return -EBUSY;
3005
3006         switch (cmd) {
3007         case QED_PUT_FILE_BEGIN:
3008                 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN;
3009                 break;
3010         case QED_PUT_FILE_DATA:
3011                 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
3012                 break;
3013         case QED_NVM_WRITE_NVRAM:
3014                 nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
3015                 break;
3016         default:
3017                 DP_NOTICE(p_hwfn, "Invalid nvm write command 0x%x\n", cmd);
3018                 rc = -EINVAL;
3019                 goto out;
3020         }
3021
3022         buf_size = min_t(u32, (len - buf_idx), MCP_DRV_NVM_BUF_LEN);
3023         while (buf_idx < len) {
3024                 if (cmd == QED_PUT_FILE_BEGIN)
3025                         nvm_offset = addr;
3026                 else
3027                         nvm_offset = ((buf_size <<
3028                                        DRV_MB_PARAM_NVM_LEN_OFFSET) | addr) +
3029                                        buf_idx;
3030                 rc = qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset,
3031                                         &resp, &param, buf_size,
3032                                         (u32 *)&p_buf[buf_idx]);
3033                 if (rc) {
3034                         DP_NOTICE(cdev, "nvm write failed, rc = %d\n", rc);
3035                         resp = FW_MSG_CODE_ERROR;
3036                         break;
3037                 }
3038
3039                 if (resp != FW_MSG_CODE_OK &&
3040                     resp != FW_MSG_CODE_NVM_OK &&
3041                     resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) {
3042                         DP_NOTICE(cdev,
3043                                   "nvm write failed, resp = 0x%08x\n", resp);
3044                         rc = -EINVAL;
3045                         break;
3046                 }
3047
3048                 /* This can be a lengthy process, and it's possible scheduler
3049                  * isn't pre-emptable. Sleep a bit to prevent CPU hogging.
3050                  */
3051                 if (buf_idx % 0x1000 > (buf_idx + buf_size) % 0x1000)
3052                         usleep_range(1000, 2000);
3053
3054                 /* For MBI upgrade, MFW response includes the next buffer offset
3055                  * to be delivered to MFW.
3056                  */
3057                 if (param && cmd == QED_PUT_FILE_DATA) {
3058                         buf_idx = QED_MFW_GET_FIELD(param,
3059                                         FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET);
3060                         buf_size = QED_MFW_GET_FIELD(param,
3061                                          FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE);
3062                 } else {
3063                         buf_idx += buf_size;
3064                         buf_size = min_t(u32, (len - buf_idx),
3065                                          MCP_DRV_NVM_BUF_LEN);
3066                 }
3067         }
3068
3069         cdev->mcp_nvm_resp = resp;
3070 out:
3071         qed_ptt_release(p_hwfn, p_ptt);
3072
3073         return rc;
3074 }
3075
3076 int qed_mcp_phy_sfp_read(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3077                          u32 port, u32 addr, u32 offset, u32 len, u8 *p_buf)
3078 {
3079         u32 bytes_left, bytes_to_copy, buf_size, nvm_offset = 0;
3080         u32 resp, param;
3081         int rc;
3082
3083         nvm_offset |= (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) &
3084                        DRV_MB_PARAM_TRANSCEIVER_PORT_MASK;
3085         nvm_offset |= (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET) &
3086                        DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK;
3087
3088         addr = offset;
3089         offset = 0;
3090         bytes_left = len;
3091         while (bytes_left > 0) {
3092                 bytes_to_copy = min_t(u32, bytes_left,
3093                                       MAX_I2C_TRANSACTION_SIZE);
3094                 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
3095                                DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
3096                 nvm_offset |= ((addr + offset) <<
3097                                DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET) &
3098                                DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK;
3099                 nvm_offset |= (bytes_to_copy <<
3100                                DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET) &
3101                                DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK;
3102                 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
3103                                         DRV_MSG_CODE_TRANSCEIVER_READ,
3104                                         nvm_offset, &resp, &param, &buf_size,
3105                                         (u32 *)(p_buf + offset));
3106                 if (rc) {
3107                         DP_NOTICE(p_hwfn,
3108                                   "Failed to send a transceiver read command to the MFW. rc = %d.\n",
3109                                   rc);
3110                         return rc;
3111                 }
3112
3113                 if (resp == FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT)
3114                         return -ENODEV;
3115                 else if (resp != FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
3116                         return -EINVAL;
3117
3118                 offset += buf_size;
3119                 bytes_left -= buf_size;
3120         }
3121
3122         return 0;
3123 }
3124
3125 int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3126 {
3127         u32 drv_mb_param = 0, rsp, param;
3128         int rc = 0;
3129
3130         drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
3131                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
3132
3133         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3134                          drv_mb_param, &rsp, &param);
3135
3136         if (rc)
3137                 return rc;
3138
3139         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3140             (param != DRV_MB_PARAM_BIST_RC_PASSED))
3141                 rc = -EAGAIN;
3142
3143         return rc;
3144 }
3145
3146 int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3147 {
3148         u32 drv_mb_param, rsp, param;
3149         int rc = 0;
3150
3151         drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
3152                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
3153
3154         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3155                          drv_mb_param, &rsp, &param);
3156
3157         if (rc)
3158                 return rc;
3159
3160         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3161             (param != DRV_MB_PARAM_BIST_RC_PASSED))
3162                 rc = -EAGAIN;
3163
3164         return rc;
3165 }
3166
3167 int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn,
3168                                     struct qed_ptt *p_ptt,
3169                                     u32 *num_images)
3170 {
3171         u32 drv_mb_param = 0, rsp;
3172         int rc = 0;
3173
3174         drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
3175                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
3176
3177         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3178                          drv_mb_param, &rsp, num_images);
3179         if (rc)
3180                 return rc;
3181
3182         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
3183                 rc = -EINVAL;
3184
3185         return rc;
3186 }
3187
3188 int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn,
3189                                    struct qed_ptt *p_ptt,
3190                                    struct bist_nvm_image_att *p_image_att,
3191                                    u32 image_index)
3192 {
3193         u32 buf_size = 0, param, resp = 0, resp_param = 0;
3194         int rc;
3195
3196         param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
3197                 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT;
3198         param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT;
3199
3200         rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
3201                                 DRV_MSG_CODE_BIST_TEST, param,
3202                                 &resp, &resp_param,
3203                                 &buf_size,
3204                                 (u32 *)p_image_att);
3205         if (rc)
3206                 return rc;
3207
3208         if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3209             (p_image_att->return_code != 1))
3210                 rc = -EINVAL;
3211
3212         return rc;
3213 }
3214
3215 int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn)
3216 {
3217         struct qed_nvm_image_info nvm_info;
3218         struct qed_ptt *p_ptt;
3219         int rc;
3220         u32 i;
3221
3222         if (p_hwfn->nvm_info.valid)
3223                 return 0;
3224
3225         p_ptt = qed_ptt_acquire(p_hwfn);
3226         if (!p_ptt) {
3227                 DP_ERR(p_hwfn, "failed to acquire ptt\n");
3228                 return -EBUSY;
3229         }
3230
3231         /* Acquire from MFW the amount of available images */
3232         nvm_info.num_images = 0;
3233         rc = qed_mcp_bist_nvm_get_num_images(p_hwfn,
3234                                              p_ptt, &nvm_info.num_images);
3235         if (rc == -EOPNOTSUPP) {
3236                 DP_INFO(p_hwfn, "DRV_MSG_CODE_BIST_TEST is not supported\n");
3237                 goto out;
3238         } else if (rc || !nvm_info.num_images) {
3239                 DP_ERR(p_hwfn, "Failed getting number of images\n");
3240                 goto err0;
3241         }
3242
3243         nvm_info.image_att = kmalloc_array(nvm_info.num_images,
3244                                            sizeof(struct bist_nvm_image_att),
3245                                            GFP_KERNEL);
3246         if (!nvm_info.image_att) {
3247                 rc = -ENOMEM;
3248                 goto err0;
3249         }
3250
3251         /* Iterate over images and get their attributes */
3252         for (i = 0; i < nvm_info.num_images; i++) {
3253                 rc = qed_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt,
3254                                                     &nvm_info.image_att[i], i);
3255                 if (rc) {
3256                         DP_ERR(p_hwfn,
3257                                "Failed getting image index %d attributes\n", i);
3258                         goto err1;
3259                 }
3260
3261                 DP_VERBOSE(p_hwfn, QED_MSG_SP, "image index %d, size %x\n", i,
3262                            nvm_info.image_att[i].len);
3263         }
3264 out:
3265         /* Update hwfn's nvm_info */
3266         if (nvm_info.num_images) {
3267                 p_hwfn->nvm_info.num_images = nvm_info.num_images;
3268                 kfree(p_hwfn->nvm_info.image_att);
3269                 p_hwfn->nvm_info.image_att = nvm_info.image_att;
3270                 p_hwfn->nvm_info.valid = true;
3271         }
3272
3273         qed_ptt_release(p_hwfn, p_ptt);
3274         return 0;
3275
3276 err1:
3277         kfree(nvm_info.image_att);
3278 err0:
3279         qed_ptt_release(p_hwfn, p_ptt);
3280         return rc;
3281 }
3282
3283 int
3284 qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn,
3285                           enum qed_nvm_images image_id,
3286                           struct qed_nvm_image_att *p_image_att)
3287 {
3288         enum nvm_image_type type;
3289         u32 i;
3290
3291         /* Translate image_id into MFW definitions */
3292         switch (image_id) {
3293         case QED_NVM_IMAGE_ISCSI_CFG:
3294                 type = NVM_TYPE_ISCSI_CFG;
3295                 break;
3296         case QED_NVM_IMAGE_FCOE_CFG:
3297                 type = NVM_TYPE_FCOE_CFG;
3298                 break;
3299         case QED_NVM_IMAGE_MDUMP:
3300                 type = NVM_TYPE_MDUMP;
3301                 break;
3302         case QED_NVM_IMAGE_NVM_CFG1:
3303                 type = NVM_TYPE_NVM_CFG1;
3304                 break;
3305         case QED_NVM_IMAGE_DEFAULT_CFG:
3306                 type = NVM_TYPE_DEFAULT_CFG;
3307                 break;
3308         case QED_NVM_IMAGE_NVM_META:
3309                 type = NVM_TYPE_META;
3310                 break;
3311         default:
3312                 DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n",
3313                           image_id);
3314                 return -EINVAL;
3315         }
3316
3317         qed_mcp_nvm_info_populate(p_hwfn);
3318         for (i = 0; i < p_hwfn->nvm_info.num_images; i++)
3319                 if (type == p_hwfn->nvm_info.image_att[i].image_type)
3320                         break;
3321         if (i == p_hwfn->nvm_info.num_images) {
3322                 DP_VERBOSE(p_hwfn, QED_MSG_STORAGE,
3323                            "Failed to find nvram image of type %08x\n",
3324                            image_id);
3325                 return -ENOENT;
3326         }
3327
3328         p_image_att->start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr;
3329         p_image_att->length = p_hwfn->nvm_info.image_att[i].len;
3330
3331         return 0;
3332 }
3333
3334 int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn,
3335                           enum qed_nvm_images image_id,
3336                           u8 *p_buffer, u32 buffer_len)
3337 {
3338         struct qed_nvm_image_att image_att;
3339         int rc;
3340
3341         memset(p_buffer, 0, buffer_len);
3342
3343         rc = qed_mcp_get_nvm_image_att(p_hwfn, image_id, &image_att);
3344         if (rc)
3345                 return rc;
3346
3347         /* Validate sizes - both the image's and the supplied buffer's */
3348         if (image_att.length <= 4) {
3349                 DP_VERBOSE(p_hwfn, QED_MSG_STORAGE,
3350                            "Image [%d] is too small - only %d bytes\n",
3351                            image_id, image_att.length);
3352                 return -EINVAL;
3353         }
3354
3355         if (image_att.length > buffer_len) {
3356                 DP_VERBOSE(p_hwfn,
3357                            QED_MSG_STORAGE,
3358                            "Image [%d] is too big - %08x bytes where only %08x are available\n",
3359                            image_id, image_att.length, buffer_len);
3360                 return -ENOMEM;
3361         }
3362
3363         return qed_mcp_nvm_read(p_hwfn->cdev, image_att.start_addr,
3364                                 p_buffer, image_att.length);
3365 }
3366
3367 static enum resource_id_enum qed_mcp_get_mfw_res_id(enum qed_resources res_id)
3368 {
3369         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
3370
3371         switch (res_id) {
3372         case QED_SB:
3373                 mfw_res_id = RESOURCE_NUM_SB_E;
3374                 break;
3375         case QED_L2_QUEUE:
3376                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
3377                 break;
3378         case QED_VPORT:
3379                 mfw_res_id = RESOURCE_NUM_VPORT_E;
3380                 break;
3381         case QED_RSS_ENG:
3382                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
3383                 break;
3384         case QED_PQ:
3385                 mfw_res_id = RESOURCE_NUM_PQ_E;
3386                 break;
3387         case QED_RL:
3388                 mfw_res_id = RESOURCE_NUM_RL_E;
3389                 break;
3390         case QED_MAC:
3391         case QED_VLAN:
3392                 /* Each VFC resource can accommodate both a MAC and a VLAN */
3393                 mfw_res_id = RESOURCE_VFC_FILTER_E;
3394                 break;
3395         case QED_ILT:
3396                 mfw_res_id = RESOURCE_ILT_E;
3397                 break;
3398         case QED_LL2_RAM_QUEUE:
3399                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
3400                 break;
3401         case QED_LL2_CTX_QUEUE:
3402                 mfw_res_id = RESOURCE_LL2_CQS_E;
3403                 break;
3404         case QED_RDMA_CNQ_RAM:
3405         case QED_CMDQS_CQS:
3406                 /* CNQ/CMDQS are the same resource */
3407                 mfw_res_id = RESOURCE_CQS_E;
3408                 break;
3409         case QED_RDMA_STATS_QUEUE:
3410                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
3411                 break;
3412         case QED_BDQ:
3413                 mfw_res_id = RESOURCE_BDQ_E;
3414                 break;
3415         default:
3416                 break;
3417         }
3418
3419         return mfw_res_id;
3420 }
3421
3422 #define QED_RESC_ALLOC_VERSION_MAJOR    2
3423 #define QED_RESC_ALLOC_VERSION_MINOR    0
3424 #define QED_RESC_ALLOC_VERSION                               \
3425         ((QED_RESC_ALLOC_VERSION_MAJOR <<                    \
3426           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \
3427          (QED_RESC_ALLOC_VERSION_MINOR <<                    \
3428           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT))
3429
3430 struct qed_resc_alloc_in_params {
3431         u32 cmd;
3432         enum qed_resources res_id;
3433         u32 resc_max_val;
3434 };
3435
3436 struct qed_resc_alloc_out_params {
3437         u32 mcp_resp;
3438         u32 mcp_param;
3439         u32 resc_num;
3440         u32 resc_start;
3441         u32 vf_resc_num;
3442         u32 vf_resc_start;
3443         u32 flags;
3444 };
3445
3446 static int
3447 qed_mcp_resc_allocation_msg(struct qed_hwfn *p_hwfn,
3448                             struct qed_ptt *p_ptt,
3449                             struct qed_resc_alloc_in_params *p_in_params,
3450                             struct qed_resc_alloc_out_params *p_out_params)
3451 {
3452         struct qed_mcp_mb_params mb_params;
3453         struct resource_info mfw_resc_info;
3454         int rc;
3455
3456         memset(&mfw_resc_info, 0, sizeof(mfw_resc_info));
3457
3458         mfw_resc_info.res_id = qed_mcp_get_mfw_res_id(p_in_params->res_id);
3459         if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
3460                 DP_ERR(p_hwfn,
3461                        "Failed to match resource %d [%s] with the MFW resources\n",
3462                        p_in_params->res_id,
3463                        qed_hw_get_resc_name(p_in_params->res_id));
3464                 return -EINVAL;
3465         }
3466
3467         switch (p_in_params->cmd) {
3468         case DRV_MSG_SET_RESOURCE_VALUE_MSG:
3469                 mfw_resc_info.size = p_in_params->resc_max_val;
3470                 /* Fallthrough */
3471         case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
3472                 break;
3473         default:
3474                 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
3475                        p_in_params->cmd);
3476                 return -EINVAL;
3477         }
3478
3479         memset(&mb_params, 0, sizeof(mb_params));
3480         mb_params.cmd = p_in_params->cmd;
3481         mb_params.param = QED_RESC_ALLOC_VERSION;
3482         mb_params.p_data_src = &mfw_resc_info;
3483         mb_params.data_src_size = sizeof(mfw_resc_info);
3484         mb_params.p_data_dst = mb_params.p_data_src;
3485         mb_params.data_dst_size = mb_params.data_src_size;
3486
3487         DP_VERBOSE(p_hwfn,
3488                    QED_MSG_SP,
3489                    "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
3490                    p_in_params->cmd,
3491                    p_in_params->res_id,
3492                    qed_hw_get_resc_name(p_in_params->res_id),
3493                    QED_MFW_GET_FIELD(mb_params.param,
3494                                      DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3495                    QED_MFW_GET_FIELD(mb_params.param,
3496                                      DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3497                    p_in_params->resc_max_val);
3498
3499         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3500         if (rc)
3501                 return rc;
3502
3503         p_out_params->mcp_resp = mb_params.mcp_resp;
3504         p_out_params->mcp_param = mb_params.mcp_param;
3505         p_out_params->resc_num = mfw_resc_info.size;
3506         p_out_params->resc_start = mfw_resc_info.offset;
3507         p_out_params->vf_resc_num = mfw_resc_info.vf_size;
3508         p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
3509         p_out_params->flags = mfw_resc_info.flags;
3510
3511         DP_VERBOSE(p_hwfn,
3512                    QED_MSG_SP,
3513                    "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
3514                    QED_MFW_GET_FIELD(p_out_params->mcp_param,
3515                                      FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3516                    QED_MFW_GET_FIELD(p_out_params->mcp_param,
3517                                      FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3518                    p_out_params->resc_num,
3519                    p_out_params->resc_start,
3520                    p_out_params->vf_resc_num,
3521                    p_out_params->vf_resc_start, p_out_params->flags);
3522
3523         return 0;
3524 }
3525
3526 int
3527 qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn,
3528                          struct qed_ptt *p_ptt,
3529                          enum qed_resources res_id,
3530                          u32 resc_max_val, u32 *p_mcp_resp)
3531 {
3532         struct qed_resc_alloc_out_params out_params;
3533         struct qed_resc_alloc_in_params in_params;
3534         int rc;
3535
3536         memset(&in_params, 0, sizeof(in_params));
3537         in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
3538         in_params.res_id = res_id;
3539         in_params.resc_max_val = resc_max_val;
3540         memset(&out_params, 0, sizeof(out_params));
3541         rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3542                                          &out_params);
3543         if (rc)
3544                 return rc;
3545
3546         *p_mcp_resp = out_params.mcp_resp;
3547
3548         return 0;
3549 }
3550
3551 int
3552 qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn,
3553                       struct qed_ptt *p_ptt,
3554                       enum qed_resources res_id,
3555                       u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start)
3556 {
3557         struct qed_resc_alloc_out_params out_params;
3558         struct qed_resc_alloc_in_params in_params;
3559         int rc;
3560
3561         memset(&in_params, 0, sizeof(in_params));
3562         in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
3563         in_params.res_id = res_id;
3564         memset(&out_params, 0, sizeof(out_params));
3565         rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3566                                          &out_params);
3567         if (rc)
3568                 return rc;
3569
3570         *p_mcp_resp = out_params.mcp_resp;
3571
3572         if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3573                 *p_resc_num = out_params.resc_num;
3574                 *p_resc_start = out_params.resc_start;
3575         }
3576
3577         return 0;
3578 }
3579
3580 int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3581 {
3582         u32 mcp_resp, mcp_param;
3583
3584         return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
3585                            &mcp_resp, &mcp_param);
3586 }
3587
3588 static int qed_mcp_resource_cmd(struct qed_hwfn *p_hwfn,
3589                                 struct qed_ptt *p_ptt,
3590                                 u32 param, u32 *p_mcp_resp, u32 *p_mcp_param)
3591 {
3592         int rc;
3593
3594         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
3595                          p_mcp_resp, p_mcp_param);
3596         if (rc)
3597                 return rc;
3598
3599         if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3600                 DP_INFO(p_hwfn,
3601                         "The resource command is unsupported by the MFW\n");
3602                 return -EINVAL;
3603         }
3604
3605         if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
3606                 u8 opcode = QED_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
3607
3608                 DP_NOTICE(p_hwfn,
3609                           "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
3610                           param, opcode);
3611                 return -EINVAL;
3612         }
3613
3614         return rc;
3615 }
3616
3617 static int
3618 __qed_mcp_resc_lock(struct qed_hwfn *p_hwfn,
3619                     struct qed_ptt *p_ptt,
3620                     struct qed_resc_lock_params *p_params)
3621 {
3622         u32 param = 0, mcp_resp, mcp_param;
3623         u8 opcode;
3624         int rc;
3625
3626         switch (p_params->timeout) {
3627         case QED_MCP_RESC_LOCK_TO_DEFAULT:
3628                 opcode = RESOURCE_OPCODE_REQ;
3629                 p_params->timeout = 0;
3630                 break;
3631         case QED_MCP_RESC_LOCK_TO_NONE:
3632                 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
3633                 p_params->timeout = 0;
3634                 break;
3635         default:
3636                 opcode = RESOURCE_OPCODE_REQ_W_AGING;
3637                 break;
3638         }
3639
3640         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3641         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3642         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
3643
3644         DP_VERBOSE(p_hwfn,
3645                    QED_MSG_SP,
3646                    "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
3647                    param, p_params->timeout, opcode, p_params->resource);
3648
3649         /* Attempt to acquire the resource */
3650         rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param);
3651         if (rc)
3652                 return rc;
3653
3654         /* Analyze the response */
3655         p_params->owner = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER);
3656         opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3657
3658         DP_VERBOSE(p_hwfn,
3659                    QED_MSG_SP,
3660                    "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
3661                    mcp_param, opcode, p_params->owner);
3662
3663         switch (opcode) {
3664         case RESOURCE_OPCODE_GNT:
3665                 p_params->b_granted = true;
3666                 break;
3667         case RESOURCE_OPCODE_BUSY:
3668                 p_params->b_granted = false;
3669                 break;
3670         default:
3671                 DP_NOTICE(p_hwfn,
3672                           "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
3673                           mcp_param, opcode);
3674                 return -EINVAL;
3675         }
3676
3677         return 0;
3678 }
3679
3680 int
3681 qed_mcp_resc_lock(struct qed_hwfn *p_hwfn,
3682                   struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params)
3683 {
3684         u32 retry_cnt = 0;
3685         int rc;
3686
3687         do {
3688                 /* No need for an interval before the first iteration */
3689                 if (retry_cnt) {
3690                         if (p_params->sleep_b4_retry) {
3691                                 u16 retry_interval_in_ms =
3692                                     DIV_ROUND_UP(p_params->retry_interval,
3693                                                  1000);
3694
3695                                 msleep(retry_interval_in_ms);
3696                         } else {
3697                                 udelay(p_params->retry_interval);
3698                         }
3699                 }
3700
3701                 rc = __qed_mcp_resc_lock(p_hwfn, p_ptt, p_params);
3702                 if (rc)
3703                         return rc;
3704
3705                 if (p_params->b_granted)
3706                         break;
3707         } while (retry_cnt++ < p_params->retry_num);
3708
3709         return 0;
3710 }
3711
3712 int
3713 qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn,
3714                     struct qed_ptt *p_ptt,
3715                     struct qed_resc_unlock_params *p_params)
3716 {
3717         u32 param = 0, mcp_resp, mcp_param;
3718         u8 opcode;
3719         int rc;
3720
3721         opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
3722                                    : RESOURCE_OPCODE_RELEASE;
3723         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3724         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3725
3726         DP_VERBOSE(p_hwfn, QED_MSG_SP,
3727                    "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
3728                    param, opcode, p_params->resource);
3729
3730         /* Attempt to release the resource */
3731         rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param);
3732         if (rc)
3733                 return rc;
3734
3735         /* Analyze the response */
3736         opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3737
3738         DP_VERBOSE(p_hwfn, QED_MSG_SP,
3739                    "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
3740                    mcp_param, opcode);
3741
3742         switch (opcode) {
3743         case RESOURCE_OPCODE_RELEASED_PREVIOUS:
3744                 DP_INFO(p_hwfn,
3745                         "Resource unlock request for an already released resource [%d]\n",
3746                         p_params->resource);
3747                 /* Fallthrough */
3748         case RESOURCE_OPCODE_RELEASED:
3749                 p_params->b_released = true;
3750                 break;
3751         case RESOURCE_OPCODE_WRONG_OWNER:
3752                 p_params->b_released = false;
3753                 break;
3754         default:
3755                 DP_NOTICE(p_hwfn,
3756                           "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
3757                           mcp_param, opcode);
3758                 return -EINVAL;
3759         }
3760
3761         return 0;
3762 }
3763
3764 void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock,
3765                                     struct qed_resc_unlock_params *p_unlock,
3766                                     enum qed_resc_lock
3767                                     resource, bool b_is_permanent)
3768 {
3769         if (p_lock) {
3770                 memset(p_lock, 0, sizeof(*p_lock));
3771
3772                 /* Permanent resources don't require aging, and there's no
3773                  * point in trying to acquire them more than once since it's
3774                  * unexpected another entity would release them.
3775                  */
3776                 if (b_is_permanent) {
3777                         p_lock->timeout = QED_MCP_RESC_LOCK_TO_NONE;
3778                 } else {
3779                         p_lock->retry_num = QED_MCP_RESC_LOCK_RETRY_CNT_DFLT;
3780                         p_lock->retry_interval =
3781                             QED_MCP_RESC_LOCK_RETRY_VAL_DFLT;
3782                         p_lock->sleep_b4_retry = true;
3783                 }
3784
3785                 p_lock->resource = resource;
3786         }
3787
3788         if (p_unlock) {
3789                 memset(p_unlock, 0, sizeof(*p_unlock));
3790                 p_unlock->resource = resource;
3791         }
3792 }
3793
3794 bool qed_mcp_is_smart_an_supported(struct qed_hwfn *p_hwfn)
3795 {
3796         return !!(p_hwfn->mcp_info->capabilities &
3797                   FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ);
3798 }
3799
3800 int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3801 {
3802         u32 mcp_resp;
3803         int rc;
3804
3805         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
3806                          0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
3807         if (!rc)
3808                 DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_PROBE),
3809                            "MFW supported features: %08x\n",
3810                            p_hwfn->mcp_info->capabilities);
3811
3812         return rc;
3813 }
3814
3815 int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3816 {
3817         u32 mcp_resp, mcp_param, features;
3818
3819         features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE |
3820                    DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK;
3821
3822         return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
3823                            features, &mcp_resp, &mcp_param);
3824 }
3825
3826 int qed_mcp_get_engine_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3827 {
3828         struct qed_mcp_mb_params mb_params = {0};
3829         struct qed_dev *cdev = p_hwfn->cdev;
3830         u8 fir_valid, l2_valid;
3831         int rc;
3832
3833         mb_params.cmd = DRV_MSG_CODE_GET_ENGINE_CONFIG;
3834         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3835         if (rc)
3836                 return rc;
3837
3838         if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3839                 DP_INFO(p_hwfn,
3840                         "The get_engine_config command is unsupported by the MFW\n");
3841                 return -EOPNOTSUPP;
3842         }
3843
3844         fir_valid = QED_MFW_GET_FIELD(mb_params.mcp_param,
3845                                       FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID);
3846         if (fir_valid)
3847                 cdev->fir_affin =
3848                     QED_MFW_GET_FIELD(mb_params.mcp_param,
3849                                       FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE);
3850
3851         l2_valid = QED_MFW_GET_FIELD(mb_params.mcp_param,
3852                                      FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID);
3853         if (l2_valid)
3854                 cdev->l2_affin_hint =
3855                     QED_MFW_GET_FIELD(mb_params.mcp_param,
3856                                       FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE);
3857
3858         DP_INFO(p_hwfn,
3859                 "Engine affinity config: FIR={valid %hhd, value %hhd}, L2_hint={valid %hhd, value %hhd}\n",
3860                 fir_valid, cdev->fir_affin, l2_valid, cdev->l2_affin_hint);
3861
3862         return 0;
3863 }
3864
3865 int qed_mcp_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3866 {
3867         struct qed_mcp_mb_params mb_params = {0};
3868         struct qed_dev *cdev = p_hwfn->cdev;
3869         int rc;
3870
3871         mb_params.cmd = DRV_MSG_CODE_GET_PPFID_BITMAP;
3872         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3873         if (rc)
3874                 return rc;
3875
3876         if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3877                 DP_INFO(p_hwfn,
3878                         "The get_ppfid_bitmap command is unsupported by the MFW\n");
3879                 return -EOPNOTSUPP;
3880         }
3881
3882         cdev->ppfid_bitmap = QED_MFW_GET_FIELD(mb_params.mcp_param,
3883                                                FW_MB_PARAM_PPFID_BITMAP);
3884
3885         DP_VERBOSE(p_hwfn, QED_MSG_SP, "PPFID bitmap 0x%hhx\n",
3886                    cdev->ppfid_bitmap);
3887
3888         return 0;
3889 }
3890
3891 int qed_mcp_nvm_get_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3892                         u16 option_id, u8 entity_id, u16 flags, u8 *p_buf,
3893                         u32 *p_len)
3894 {
3895         u32 mb_param = 0, resp, param;
3896         int rc;
3897
3898         QED_MFW_SET_FIELD(mb_param, DRV_MB_PARAM_NVM_CFG_OPTION_ID, option_id);
3899         if (flags & QED_NVM_CFG_OPTION_INIT)
3900                 QED_MFW_SET_FIELD(mb_param,
3901                                   DRV_MB_PARAM_NVM_CFG_OPTION_INIT, 1);
3902         if (flags & QED_NVM_CFG_OPTION_FREE)
3903                 QED_MFW_SET_FIELD(mb_param,
3904                                   DRV_MB_PARAM_NVM_CFG_OPTION_FREE, 1);
3905         if (flags & QED_NVM_CFG_OPTION_ENTITY_SEL) {
3906                 QED_MFW_SET_FIELD(mb_param,
3907                                   DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL, 1);
3908                 QED_MFW_SET_FIELD(mb_param,
3909                                   DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID,
3910                                   entity_id);
3911         }
3912
3913         rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
3914                                 DRV_MSG_CODE_GET_NVM_CFG_OPTION,
3915                                 mb_param, &resp, &param, p_len, (u32 *)p_buf);
3916
3917         return rc;
3918 }
3919
3920 int qed_mcp_nvm_set_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3921                         u16 option_id, u8 entity_id, u16 flags, u8 *p_buf,
3922                         u32 len)
3923 {
3924         u32 mb_param = 0, resp, param;
3925
3926         QED_MFW_SET_FIELD(mb_param, DRV_MB_PARAM_NVM_CFG_OPTION_ID, option_id);
3927         if (flags & QED_NVM_CFG_OPTION_ALL)
3928                 QED_MFW_SET_FIELD(mb_param,
3929                                   DRV_MB_PARAM_NVM_CFG_OPTION_ALL, 1);
3930         if (flags & QED_NVM_CFG_OPTION_INIT)
3931                 QED_MFW_SET_FIELD(mb_param,
3932                                   DRV_MB_PARAM_NVM_CFG_OPTION_INIT, 1);
3933         if (flags & QED_NVM_CFG_OPTION_COMMIT)
3934                 QED_MFW_SET_FIELD(mb_param,
3935                                   DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT, 1);
3936         if (flags & QED_NVM_CFG_OPTION_FREE)
3937                 QED_MFW_SET_FIELD(mb_param,
3938                                   DRV_MB_PARAM_NVM_CFG_OPTION_FREE, 1);
3939         if (flags & QED_NVM_CFG_OPTION_ENTITY_SEL) {
3940                 QED_MFW_SET_FIELD(mb_param,
3941                                   DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL, 1);
3942                 QED_MFW_SET_FIELD(mb_param,
3943                                   DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID,
3944                                   entity_id);
3945         }
3946
3947         return qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt,
3948                                   DRV_MSG_CODE_SET_NVM_CFG_OPTION,
3949                                   mb_param, &resp, &param, len, (u32 *)p_buf);
3950 }
3951
3952 #define QED_MCP_DBG_DATA_MAX_SIZE               MCP_DRV_NVM_BUF_LEN
3953 #define QED_MCP_DBG_DATA_MAX_HEADER_SIZE        sizeof(u32)
3954 #define QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE \
3955         (QED_MCP_DBG_DATA_MAX_SIZE - QED_MCP_DBG_DATA_MAX_HEADER_SIZE)
3956
3957 static int
3958 __qed_mcp_send_debug_data(struct qed_hwfn *p_hwfn,
3959                           struct qed_ptt *p_ptt, u8 *p_buf, u8 size)
3960 {
3961         struct qed_mcp_mb_params mb_params;
3962         int rc;
3963
3964         if (size > QED_MCP_DBG_DATA_MAX_SIZE) {
3965                 DP_ERR(p_hwfn,
3966                        "Debug data size is %d while it should not exceed %d\n",
3967                        size, QED_MCP_DBG_DATA_MAX_SIZE);
3968                 return -EINVAL;
3969         }
3970
3971         memset(&mb_params, 0, sizeof(mb_params));
3972         mb_params.cmd = DRV_MSG_CODE_DEBUG_DATA_SEND;
3973         SET_MFW_FIELD(mb_params.param, DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE, size);
3974         mb_params.p_data_src = p_buf;
3975         mb_params.data_src_size = size;
3976         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3977         if (rc)
3978                 return rc;
3979
3980         if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3981                 DP_INFO(p_hwfn,
3982                         "The DEBUG_DATA_SEND command is unsupported by the MFW\n");
3983                 return -EOPNOTSUPP;
3984         } else if (mb_params.mcp_resp == (u32)FW_MSG_CODE_DEBUG_NOT_ENABLED) {
3985                 DP_INFO(p_hwfn, "The DEBUG_DATA_SEND command is not enabled\n");
3986                 return -EBUSY;
3987         } else if (mb_params.mcp_resp != (u32)FW_MSG_CODE_DEBUG_DATA_SEND_OK) {
3988                 DP_NOTICE(p_hwfn,
3989                           "Failed to send debug data to the MFW [resp 0x%08x]\n",
3990                           mb_params.mcp_resp);
3991                 return -EINVAL;
3992         }
3993
3994         return 0;
3995 }
3996
3997 enum qed_mcp_dbg_data_type {
3998         QED_MCP_DBG_DATA_TYPE_RAW,
3999 };
4000
4001 /* Header format: [31:28] PFID, [27:20] flags, [19:12] type, [11:0] S/N */
4002 #define QED_MCP_DBG_DATA_HDR_SN_OFFSET  0
4003 #define QED_MCP_DBG_DATA_HDR_SN_MASK            0x00000fff
4004 #define QED_MCP_DBG_DATA_HDR_TYPE_OFFSET        12
4005 #define QED_MCP_DBG_DATA_HDR_TYPE_MASK  0x000ff000
4006 #define QED_MCP_DBG_DATA_HDR_FLAGS_OFFSET       20
4007 #define QED_MCP_DBG_DATA_HDR_FLAGS_MASK 0x0ff00000
4008 #define QED_MCP_DBG_DATA_HDR_PF_OFFSET  28
4009 #define QED_MCP_DBG_DATA_HDR_PF_MASK            0xf0000000
4010
4011 #define QED_MCP_DBG_DATA_HDR_FLAGS_FIRST        0x1
4012 #define QED_MCP_DBG_DATA_HDR_FLAGS_LAST 0x2
4013
4014 static int
4015 qed_mcp_send_debug_data(struct qed_hwfn *p_hwfn,
4016                         struct qed_ptt *p_ptt,
4017                         enum qed_mcp_dbg_data_type type, u8 *p_buf, u32 size)
4018 {
4019         u8 raw_data[QED_MCP_DBG_DATA_MAX_SIZE], *p_tmp_buf = p_buf;
4020         u32 tmp_size = size, *p_header, *p_payload;
4021         u8 flags = 0;
4022         u16 seq;
4023         int rc;
4024
4025         p_header = (u32 *)raw_data;
4026         p_payload = (u32 *)(raw_data + QED_MCP_DBG_DATA_MAX_HEADER_SIZE);
4027
4028         seq = (u16)atomic_inc_return(&p_hwfn->mcp_info->dbg_data_seq);
4029
4030         /* First chunk is marked as 'first' */
4031         flags |= QED_MCP_DBG_DATA_HDR_FLAGS_FIRST;
4032
4033         *p_header = 0;
4034         SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_SN, seq);
4035         SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_TYPE, type);
4036         SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_FLAGS, flags);
4037         SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_PF, p_hwfn->abs_pf_id);
4038
4039         while (tmp_size > QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE) {
4040                 memcpy(p_payload, p_tmp_buf, QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE);
4041                 rc = __qed_mcp_send_debug_data(p_hwfn, p_ptt, raw_data,
4042                                                QED_MCP_DBG_DATA_MAX_SIZE);
4043                 if (rc)
4044                         return rc;
4045
4046                 /* Clear the 'first' marking after sending the first chunk */
4047                 if (p_tmp_buf == p_buf) {
4048                         flags &= ~QED_MCP_DBG_DATA_HDR_FLAGS_FIRST;
4049                         SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_FLAGS,
4050                                       flags);
4051                 }
4052
4053                 p_tmp_buf += QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE;
4054                 tmp_size -= QED_MCP_DBG_DATA_MAX_PAYLOAD_SIZE;
4055         }
4056
4057         /* Last chunk is marked as 'last' */
4058         flags |= QED_MCP_DBG_DATA_HDR_FLAGS_LAST;
4059         SET_MFW_FIELD(*p_header, QED_MCP_DBG_DATA_HDR_FLAGS, flags);
4060         memcpy(p_payload, p_tmp_buf, tmp_size);
4061
4062         /* Casting the left size to u8 is ok since at this point it is <= 32 */
4063         return __qed_mcp_send_debug_data(p_hwfn, p_ptt, raw_data,
4064                                          (u8)(QED_MCP_DBG_DATA_MAX_HEADER_SIZE +
4065                                          tmp_size));
4066 }
4067
4068 int
4069 qed_mcp_send_raw_debug_data(struct qed_hwfn *p_hwfn,
4070                             struct qed_ptt *p_ptt, u8 *p_buf, u32 size)
4071 {
4072         return qed_mcp_send_debug_data(p_hwfn, p_ptt,
4073                                        QED_MCP_DBG_DATA_TYPE_RAW, p_buf, size);
4074 }