drivers/net/ethernet/qlogic/qed/qed_mcp.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/types.h>
  34 #include <asm/byteorder.h>
  35 #include <linux/delay.h>
  36 #include <linux/errno.h>
  37 #include <linux/kernel.h>
  38 #include <linux/slab.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/string.h>
  41 #include <linux/etherdevice.h>
  42 #include "qed.h"
  43 #include "qed_cxt.h"
  44 #include "qed_dcbx.h"
  45 #include "qed_hsi.h"
  46 #include "qed_hw.h"
  47 #include "qed_mcp.h"
  48 #include "qed_reg_addr.h"
  49 #include "qed_sriov.h"
  50
  51 #define CHIP_MCP_RESP_ITER_US 10
  52
  53 #define QED_DRV_MB_MAX_RETRIES  (500 * 1000)    /* Account for 5 sec */
  54 #define QED_MCP_RESET_RETRIES   (50 * 1000)     /* Account for 500 msec */
  55
  56 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val)           \
  57         qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
  58                _val)
  59
  60 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
  61         qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
  62
  63 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val)  \
  64         DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
  65                      offsetof(struct public_drv_mb, _field), _val)
  66
  67 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field)         \
  68         DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
  69                      offsetof(struct public_drv_mb, _field))
  70
  71 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
  72                   DRV_ID_PDA_COMP_VER_SHIFT)
  73
  74 #define MCP_BYTES_PER_MBIT_SHIFT 17
  75
  76 bool qed_mcp_is_init(struct qed_hwfn *p_hwfn)
  77 {
  78         if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
  79                 return false;
  80         return true;
  81 }
  82
  83 void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
  84 {
  85         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
  86                                         PUBLIC_PORT);
  87         u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr);
  88
  89         p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
  90                                                    MFW_PORT(p_hwfn));
  91         DP_VERBOSE(p_hwfn, QED_MSG_SP,
  92                    "port_addr = 0x%x, port_id 0x%02x\n",
  93                    p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
  94 }
  95
  96 void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
  97 {
  98         u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
  99         u32 tmp, i;
 100
 101         if (!p_hwfn->mcp_info->public_base)
 102                 return;
 103
 104         for (i = 0; i < length; i++) {
 105                 tmp = qed_rd(p_hwfn, p_ptt,
 106                              p_hwfn->mcp_info->mfw_mb_addr +
 107                              (i << 2) + sizeof(u32));
 108
 109                 /* The MB data is actually BE; Need to force it to cpu */
 110                 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
 111                         be32_to_cpu((__force __be32)tmp);
 112         }
 113 }
 114
 115 struct qed_mcp_cmd_elem {
 116         struct list_head list;
 117         struct qed_mcp_mb_params *p_mb_params;
 118         u16 expected_seq_num;
 119         bool b_is_completed;
 120 };
 121
 122 /* Must be called while cmd_lock is acquired */
 123 static struct qed_mcp_cmd_elem *
 124 qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn,
 125                      struct qed_mcp_mb_params *p_mb_params,
 126                      u16 expected_seq_num)
 127 {
 128         struct qed_mcp_cmd_elem *p_cmd_elem = NULL;
 129
 130         p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC);
 131         if (!p_cmd_elem)
 132                 goto out;
 133
 134         p_cmd_elem->p_mb_params = p_mb_params;
 135         p_cmd_elem->expected_seq_num = expected_seq_num;
 136         list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
 137 out:
 138         return p_cmd_elem;
 139 }
 140
 141 /* Must be called while cmd_lock is acquired */
 142 static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn,
 143                                  struct qed_mcp_cmd_elem *p_cmd_elem)
 144 {
 145         list_del(&p_cmd_elem->list);
 146         kfree(p_cmd_elem);
 147 }
 148
 149 /* Must be called while cmd_lock is acquired */
 150 static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn,
 151                                                      u16 seq_num)
 152 {
 153         struct qed_mcp_cmd_elem *p_cmd_elem = NULL;
 154
 155         list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) {
 156                 if (p_cmd_elem->expected_seq_num == seq_num)
 157                         return p_cmd_elem;
 158         }
 159
 160         return NULL;
 161 }
 162
 163 int qed_mcp_free(struct qed_hwfn *p_hwfn)
 164 {
 165         if (p_hwfn->mcp_info) {
 166                 struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp;
 167
 168                 kfree(p_hwfn->mcp_info->mfw_mb_cur);
 169                 kfree(p_hwfn->mcp_info->mfw_mb_shadow);
 170
 171                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 172                 list_for_each_entry_safe(p_cmd_elem,
 173                                          p_tmp,
 174                                          &p_hwfn->mcp_info->cmd_list, list) {
 175                         qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 176                 }
 177                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 178         }
 179
 180         kfree(p_hwfn->mcp_info);
 181         p_hwfn->mcp_info = NULL;
 182
 183         return 0;
 184 }
 185
 186 static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 187 {
 188         struct qed_mcp_info *p_info = p_hwfn->mcp_info;
 189         u32 drv_mb_offsize, mfw_mb_offsize;
 190         u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
 191
 192         p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
 193         if (!p_info->public_base)
 194                 return 0;
 195
 196         p_info->public_base |= GRCBASE_MCP;
 197
 198         /* Calculate the driver and MFW mailbox address */
 199         drv_mb_offsize = qed_rd(p_hwfn, p_ptt,
 200                                 SECTION_OFFSIZE_ADDR(p_info->public_base,
 201                                                      PUBLIC_DRV_MB));
 202         p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
 203         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 204                    "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n",
 205                    drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
 206
 207         /* Set the MFW MB address */
 208         mfw_mb_offsize = qed_rd(p_hwfn, p_ptt,
 209                                 SECTION_OFFSIZE_ADDR(p_info->public_base,
 210                                                      PUBLIC_MFW_MB));
 211         p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
 212         p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, p_info->mfw_mb_addr);
 213
 214         /* Get the current driver mailbox sequence before sending
 215          * the first command
 216          */
 217         p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 218                              DRV_MSG_SEQ_NUMBER_MASK;
 219
 220         /* Get current FW pulse sequence */
 221         p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
 222                                 DRV_PULSE_SEQ_MASK;
 223
 224         p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 225
 226         return 0;
 227 }
 228
 229 int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 230 {
 231         struct qed_mcp_info *p_info;
 232         u32 size;
 233
 234         /* Allocate mcp_info structure */
 235         p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL);
 236         if (!p_hwfn->mcp_info)
 237                 goto err;
 238         p_info = p_hwfn->mcp_info;
 239
 240         /* Initialize the MFW spinlock */
 241         spin_lock_init(&p_info->cmd_lock);
 242         spin_lock_init(&p_info->link_lock);
 243
 244         INIT_LIST_HEAD(&p_info->cmd_list);
 245
 246         if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) {
 247                 DP_NOTICE(p_hwfn, "MCP is not initialized\n");
 248                 /* Do not free mcp_info here, since public_base indicate that
 249                  * the MCP is not initialized
 250                  */
 251                 return 0;
 252         }
 253
 254         size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
 255         p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL);
 256         p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL);
 257         if (!p_info->mfw_mb_cur || !p_info->mfw_mb_shadow)
 258                 goto err;
 259
 260         return 0;
 261
 262 err:
 263         qed_mcp_free(p_hwfn);
 264         return -ENOMEM;
 265 }
 266
 267 static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn,
 268                                    struct qed_ptt *p_ptt)
 269 {
 270         u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 271
 272         /* Use MCP history register to check if MCP reset occurred between init
 273          * time and now.
 274          */
 275         if (p_hwfn->mcp_info->mcp_hist != generic_por_0) {
 276                 DP_VERBOSE(p_hwfn,
 277                            QED_MSG_SP,
 278                            "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n",
 279                            p_hwfn->mcp_info->mcp_hist, generic_por_0);
 280
 281                 qed_load_mcp_offsets(p_hwfn, p_ptt);
 282                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
 283         }
 284 }
 285
 286 int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 287 {
 288         u32 org_mcp_reset_seq, seq, delay = CHIP_MCP_RESP_ITER_US, cnt = 0;
 289         int rc = 0;
 290
 291         /* Ensure that only a single thread is accessing the mailbox */
 292         spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 293
 294         org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 295
 296         /* Set drv command along with the updated sequence */
 297         qed_mcp_reread_offsets(p_hwfn, p_ptt);
 298         seq = ++p_hwfn->mcp_info->drv_mb_seq;
 299         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
 300
 301         do {
 302                 /* Wait for MFW response */
 303                 udelay(delay);
 304                 /* Give the FW up to 500 second (50*1000*10usec) */
 305         } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt,
 306                                               MISCS_REG_GENERIC_POR_0)) &&
 307                  (cnt++ < QED_MCP_RESET_RETRIES));
 308
 309         if (org_mcp_reset_seq !=
 310             qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 311                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
 312                            "MCP was reset after %d usec\n", cnt * delay);
 313         } else {
 314                 DP_ERR(p_hwfn, "Failed to reset MCP\n");
 315                 rc = -EAGAIN;
 316         }
 317
 318         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 319
 320         return rc;
 321 }
 322
 323 /* Must be called while cmd_lock is acquired */
 324 static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn)
 325 {
 326         struct qed_mcp_cmd_elem *p_cmd_elem;
 327
 328         /* There is at most one pending command at a certain time, and if it
 329          * exists - it is placed at the HEAD of the list.
 330          */
 331         if (!list_empty(&p_hwfn->mcp_info->cmd_list)) {
 332                 p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list,
 333                                               struct qed_mcp_cmd_elem, list);
 334                 return !p_cmd_elem->b_is_completed;
 335         }
 336
 337         return false;
 338 }
 339
 340 /* Must be called while cmd_lock is acquired */
 341 static int
 342 qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 343 {
 344         struct qed_mcp_mb_params *p_mb_params;
 345         struct qed_mcp_cmd_elem *p_cmd_elem;
 346         u32 mcp_resp;
 347         u16 seq_num;
 348
 349         mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
 350         seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK);
 351
 352         /* Return if no new non-handled response has been received */
 353         if (seq_num != p_hwfn->mcp_info->drv_mb_seq)
 354                 return -EAGAIN;
 355
 356         p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num);
 357         if (!p_cmd_elem) {
 358                 DP_ERR(p_hwfn,
 359                        "Failed to find a pending mailbox cmd that expects sequence number %d\n",
 360                        seq_num);
 361                 return -EINVAL;
 362         }
 363
 364         p_mb_params = p_cmd_elem->p_mb_params;
 365
 366         /* Get the MFW response along with the sequence number */
 367         p_mb_params->mcp_resp = mcp_resp;
 368
 369         /* Get the MFW param */
 370         p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
 371
 372         /* Get the union data */
 373         if (p_mb_params->p_data_dst != NULL && p_mb_params->data_dst_size) {
 374                 u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 375                                       offsetof(struct public_drv_mb,
 376                                                union_data);
 377                 qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
 378                                 union_data_addr, p_mb_params->data_dst_size);
 379         }
 380
 381         p_cmd_elem->b_is_completed = true;
 382
 383         return 0;
 384 }
 385
 386 /* Must be called while cmd_lock is acquired */
 387 static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
 388                                     struct qed_ptt *p_ptt,
 389                                     struct qed_mcp_mb_params *p_mb_params,
 390                                     u16 seq_num)
 391 {
 392         union drv_union_data union_data;
 393         u32 union_data_addr;
 394
 395         /* Set the union data */
 396         union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 397                           offsetof(struct public_drv_mb, union_data);
 398         memset(&union_data, 0, sizeof(union_data));
 399         if (p_mb_params->p_data_src != NULL && p_mb_params->data_src_size)
 400                 memcpy(&union_data, p_mb_params->p_data_src,
 401                        p_mb_params->data_src_size);
 402         qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
 403                       sizeof(union_data));
 404
 405         /* Set the drv param */
 406         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param);
 407
 408         /* Set the drv command along with the sequence number */
 409         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num));
 410
 411         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 412                    "MFW mailbox: command 0x%08x param 0x%08x\n",
 413                    (p_mb_params->cmd | seq_num), p_mb_params->param);
 414 }
 415
 416 static int
 417 _qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
 418                        struct qed_ptt *p_ptt,
 419                        struct qed_mcp_mb_params *p_mb_params,
 420                        u32 max_retries, u32 delay)
 421 {
 422         struct qed_mcp_cmd_elem *p_cmd_elem;
 423         u32 cnt = 0;
 424         u16 seq_num;
 425         int rc = 0;
 426
 427         /* Wait until the mailbox is non-occupied */
 428         do {
 429                 /* Exit the loop if there is no pending command, or if the
 430                  * pending command is completed during this iteration.
 431                  * The spinlock stays locked until the command is sent.
 432                  */
 433
 434                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 435
 436                 if (!qed_mcp_has_pending_cmd(p_hwfn))
 437                         break;
 438
 439                 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt);
 440                 if (!rc)
 441                         break;
 442                 else if (rc != -EAGAIN)
 443                         goto err;
 444
 445                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 446                 udelay(delay);
 447         } while (++cnt < max_retries);
 448
 449         if (cnt >= max_retries) {
 450                 DP_NOTICE(p_hwfn,
 451                           "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n",
 452                           p_mb_params->cmd, p_mb_params->param);
 453                 return -EAGAIN;
 454         }
 455
 456         /* Send the mailbox command */
 457         qed_mcp_reread_offsets(p_hwfn, p_ptt);
 458         seq_num = ++p_hwfn->mcp_info->drv_mb_seq;
 459         p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num);
 460         if (!p_cmd_elem) {
 461                 rc = -ENOMEM;
 462                 goto err;
 463         }
 464
 465         __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num);
 466         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 467
 468         /* Wait for the MFW response */
 469         do {
 470                 /* Exit the loop if the command is already completed, or if the
 471                  * command is completed during this iteration.
 472                  * The spinlock stays locked until the list element is removed.
 473                  */
 474
 475                 udelay(delay);
 476                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 477
 478                 if (p_cmd_elem->b_is_completed)
 479                         break;
 480
 481                 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt);
 482                 if (!rc)
 483                         break;
 484                 else if (rc != -EAGAIN)
 485                         goto err;
 486
 487                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 488         } while (++cnt < max_retries);
 489
 490         if (cnt >= max_retries) {
 491                 DP_NOTICE(p_hwfn,
 492                           "The MFW failed to respond to command 0x%08x [param 0x%08x].\n",
 493                           p_mb_params->cmd, p_mb_params->param);
 494
 495                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 496                 qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 497                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 498
 499                 return -EAGAIN;
 500         }
 501
 502         qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 503         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 504
 505         DP_VERBOSE(p_hwfn,
 506                    QED_MSG_SP,
 507                    "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n",
 508                    p_mb_params->mcp_resp,
 509                    p_mb_params->mcp_param,
 510                    (cnt * delay) / 1000, (cnt * delay) % 1000);
 511
 512         /* Clear the sequence number from the MFW response */
 513         p_mb_params->mcp_resp &= FW_MSG_CODE_MASK;
 514
 515         return 0;
 516
 517 err:
 518         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 519         return rc;
 520 }
 521
 522 static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
 523                                  struct qed_ptt *p_ptt,
 524                                  struct qed_mcp_mb_params *p_mb_params)
 525 {
 526         size_t union_data_size = sizeof(union drv_union_data);
 527         u32 max_retries = QED_DRV_MB_MAX_RETRIES;
 528         u32 delay = CHIP_MCP_RESP_ITER_US;
 529
 530         /* MCP not initialized */
 531         if (!qed_mcp_is_init(p_hwfn)) {
 532                 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
 533                 return -EBUSY;
 534         }
 535
 536         if (p_mb_params->data_src_size > union_data_size ||
 537             p_mb_params->data_dst_size > union_data_size) {
 538                 DP_ERR(p_hwfn,
 539                        "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
 540                        p_mb_params->data_src_size,
 541                        p_mb_params->data_dst_size, union_data_size);
 542                 return -EINVAL;
 543         }
 544
 545         return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries,
 546                                       delay);
 547 }
 548
 549 int qed_mcp_cmd(struct qed_hwfn *p_hwfn,
 550                 struct qed_ptt *p_ptt,
 551                 u32 cmd,
 552                 u32 param,
 553                 u32 *o_mcp_resp,
 554                 u32 *o_mcp_param)
 555 {
 556         struct qed_mcp_mb_params mb_params;
 557         int rc;
 558
 559         memset(&mb_params, 0, sizeof(mb_params));
 560         mb_params.cmd = cmd;
 561         mb_params.param = param;
 562
 563         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 564         if (rc)
 565                 return rc;
 566
 567         *o_mcp_resp = mb_params.mcp_resp;
 568         *o_mcp_param = mb_params.mcp_param;
 569
 570         return 0;
 571 }
 572
 573 int qed_mcp_nvm_wr_cmd(struct qed_hwfn *p_hwfn,
 574                        struct qed_ptt *p_ptt,
 575                        u32 cmd,
 576                        u32 param,
 577                        u32 *o_mcp_resp,
 578                        u32 *o_mcp_param, u32 i_txn_size, u32 *i_buf)
 579 {
 580         struct qed_mcp_mb_params mb_params;
 581         int rc;
 582
 583         memset(&mb_params, 0, sizeof(mb_params));
 584         mb_params.cmd = cmd;
 585         mb_params.param = param;
 586         mb_params.p_data_src = i_buf;
 587         mb_params.data_src_size = (u8)i_txn_size;
 588         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 589         if (rc)
 590                 return rc;
 591
 592         *o_mcp_resp = mb_params.mcp_resp;
 593         *o_mcp_param = mb_params.mcp_param;
 594
 595         /* nvm_info needs to be updated */
 596         p_hwfn->nvm_info.valid = false;
 597
 598         return 0;
 599 }
 600
 601 int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn,
 602                        struct qed_ptt *p_ptt,
 603                        u32 cmd,
 604                        u32 param,
 605                        u32 *o_mcp_resp,
 606                        u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf)
 607 {
 608         struct qed_mcp_mb_params mb_params;
 609         u8 raw_data[MCP_DRV_NVM_BUF_LEN];
 610         int rc;
 611
 612         memset(&mb_params, 0, sizeof(mb_params));
 613         mb_params.cmd = cmd;
 614         mb_params.param = param;
 615         mb_params.p_data_dst = raw_data;
 616
 617         /* Use the maximal value since the actual one is part of the response */
 618         mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
 619
 620         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 621         if (rc)
 622                 return rc;
 623
 624         *o_mcp_resp = mb_params.mcp_resp;
 625         *o_mcp_param = mb_params.mcp_param;
 626
 627         *o_txn_size = *o_mcp_param;
 628         memcpy(o_buf, raw_data, *o_txn_size);
 629
 630         return 0;
 631 }
 632
 633 static bool
 634 qed_mcp_can_force_load(u8 drv_role,
 635                        u8 exist_drv_role,
 636                        enum qed_override_force_load override_force_load)
 637 {
 638         bool can_force_load = false;
 639
 640         switch (override_force_load) {
 641         case QED_OVERRIDE_FORCE_LOAD_ALWAYS:
 642                 can_force_load = true;
 643                 break;
 644         case QED_OVERRIDE_FORCE_LOAD_NEVER:
 645                 can_force_load = false;
 646                 break;
 647         default:
 648                 can_force_load = (drv_role == DRV_ROLE_OS &&
 649                                   exist_drv_role == DRV_ROLE_PREBOOT) ||
 650                                  (drv_role == DRV_ROLE_KDUMP &&
 651                                   exist_drv_role == DRV_ROLE_OS);
 652                 break;
 653         }
 654
 655         return can_force_load;
 656 }
 657
 658 static int qed_mcp_cancel_load_req(struct qed_hwfn *p_hwfn,
 659                                    struct qed_ptt *p_ptt)
 660 {
 661         u32 resp = 0, param = 0;
 662         int rc;
 663
 664         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
 665                          &resp, &param);
 666         if (rc)
 667                 DP_NOTICE(p_hwfn,
 668                           "Failed to send cancel load request, rc = %d\n", rc);
 669
 670         return rc;
 671 }
 672
 673 #define CONFIG_QEDE_BITMAP_IDX          BIT(0)
 674 #define CONFIG_QED_SRIOV_BITMAP_IDX     BIT(1)
 675 #define CONFIG_QEDR_BITMAP_IDX          BIT(2)
 676 #define CONFIG_QEDF_BITMAP_IDX          BIT(4)
 677 #define CONFIG_QEDI_BITMAP_IDX          BIT(5)
 678 #define CONFIG_QED_LL2_BITMAP_IDX       BIT(6)
 679
 680 static u32 qed_get_config_bitmap(void)
 681 {
 682         u32 config_bitmap = 0x0;
 683
 684         if (IS_ENABLED(CONFIG_QEDE))
 685                 config_bitmap |= CONFIG_QEDE_BITMAP_IDX;
 686
 687         if (IS_ENABLED(CONFIG_QED_SRIOV))
 688                 config_bitmap |= CONFIG_QED_SRIOV_BITMAP_IDX;
 689
 690         if (IS_ENABLED(CONFIG_QED_RDMA))
 691                 config_bitmap |= CONFIG_QEDR_BITMAP_IDX;
 692
 693         if (IS_ENABLED(CONFIG_QED_FCOE))
 694                 config_bitmap |= CONFIG_QEDF_BITMAP_IDX;
 695
 696         if (IS_ENABLED(CONFIG_QED_ISCSI))
 697                 config_bitmap |= CONFIG_QEDI_BITMAP_IDX;
 698
 699         if (IS_ENABLED(CONFIG_QED_LL2))
 700                 config_bitmap |= CONFIG_QED_LL2_BITMAP_IDX;
 701
 702         return config_bitmap;
 703 }
 704
 705 struct qed_load_req_in_params {
 706         u8 hsi_ver;
 707 #define QED_LOAD_REQ_HSI_VER_DEFAULT    0
 708 #define QED_LOAD_REQ_HSI_VER_1          1
 709         u32 drv_ver_0;
 710         u32 drv_ver_1;
 711         u32 fw_ver;
 712         u8 drv_role;
 713         u8 timeout_val;
 714         u8 force_cmd;
 715         bool avoid_eng_reset;
 716 };
 717
 718 struct qed_load_req_out_params {
 719         u32 load_code;
 720         u32 exist_drv_ver_0;
 721         u32 exist_drv_ver_1;
 722         u32 exist_fw_ver;
 723         u8 exist_drv_role;
 724         u8 mfw_hsi_ver;
 725         bool drv_exists;
 726 };
 727
 728 static int
 729 __qed_mcp_load_req(struct qed_hwfn *p_hwfn,
 730                    struct qed_ptt *p_ptt,
 731                    struct qed_load_req_in_params *p_in_params,
 732                    struct qed_load_req_out_params *p_out_params)
 733 {
 734         struct qed_mcp_mb_params mb_params;
 735         struct load_req_stc load_req;
 736         struct load_rsp_stc load_rsp;
 737         u32 hsi_ver;
 738         int rc;
 739
 740         memset(&load_req, 0, sizeof(load_req));
 741         load_req.drv_ver_0 = p_in_params->drv_ver_0;
 742         load_req.drv_ver_1 = p_in_params->drv_ver_1;
 743         load_req.fw_ver = p_in_params->fw_ver;
 744         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role);
 745         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
 746                           p_in_params->timeout_val);
 747         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE,
 748                           p_in_params->force_cmd);
 749         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
 750                           p_in_params->avoid_eng_reset);
 751
 752         hsi_ver = (p_in_params->hsi_ver == QED_LOAD_REQ_HSI_VER_DEFAULT) ?
 753                   DRV_ID_MCP_HSI_VER_CURRENT :
 754                   (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT);
 755
 756         memset(&mb_params, 0, sizeof(mb_params));
 757         mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
 758         mb_params.param = PDA_COMP | hsi_ver | p_hwfn->cdev->drv_type;
 759         mb_params.p_data_src = &load_req;
 760         mb_params.data_src_size = sizeof(load_req);
 761         mb_params.p_data_dst = &load_rsp;
 762         mb_params.data_dst_size = sizeof(load_rsp);
 763
 764         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 765                    "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
 766                    mb_params.param,
 767                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
 768                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
 769                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
 770                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
 771
 772         if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1) {
 773                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
 774                            "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
 775                            load_req.drv_ver_0,
 776                            load_req.drv_ver_1,
 777                            load_req.fw_ver,
 778                            load_req.misc0,
 779                            QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE),
 780                            QED_MFW_GET_FIELD(load_req.misc0,
 781                                              LOAD_REQ_LOCK_TO),
 782                            QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE),
 783                            QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0));
 784         }
 785
 786         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 787         if (rc) {
 788                 DP_NOTICE(p_hwfn, "Failed to send load request, rc = %d\n", rc);
 789                 return rc;
 790         }
 791
 792         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 793                    "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
 794         p_out_params->load_code = mb_params.mcp_resp;
 795
 796         if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1 &&
 797             p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 798                 DP_VERBOSE(p_hwfn,
 799                            QED_MSG_SP,
 800                            "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
 801                            load_rsp.drv_ver_0,
 802                            load_rsp.drv_ver_1,
 803                            load_rsp.fw_ver,
 804                            load_rsp.misc0,
 805                            QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
 806                            QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
 807                            QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0));
 808
 809                 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
 810                 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
 811                 p_out_params->exist_fw_ver = load_rsp.fw_ver;
 812                 p_out_params->exist_drv_role =
 813                     QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
 814                 p_out_params->mfw_hsi_ver =
 815                     QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
 816                 p_out_params->drv_exists =
 817                     QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
 818                     LOAD_RSP_FLAGS0_DRV_EXISTS;
 819         }
 820
 821         return 0;
 822 }
 823
 824 static int eocre_get_mfw_drv_role(struct qed_hwfn *p_hwfn,
 825                                   enum qed_drv_role drv_role,
 826                                   u8 *p_mfw_drv_role)
 827 {
 828         switch (drv_role) {
 829         case QED_DRV_ROLE_OS:
 830                 *p_mfw_drv_role = DRV_ROLE_OS;
 831                 break;
 832         case QED_DRV_ROLE_KDUMP:
 833                 *p_mfw_drv_role = DRV_ROLE_KDUMP;
 834                 break;
 835         default:
 836                 DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role);
 837                 return -EINVAL;
 838         }
 839
 840         return 0;
 841 }
 842
 843 enum qed_load_req_force {
 844         QED_LOAD_REQ_FORCE_NONE,
 845         QED_LOAD_REQ_FORCE_PF,
 846         QED_LOAD_REQ_FORCE_ALL,
 847 };
 848
 849 static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn,
 850
 851                                   enum qed_load_req_force force_cmd,
 852                                   u8 *p_mfw_force_cmd)
 853 {
 854         switch (force_cmd) {
 855         case QED_LOAD_REQ_FORCE_NONE:
 856                 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
 857                 break;
 858         case QED_LOAD_REQ_FORCE_PF:
 859                 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
 860                 break;
 861         case QED_LOAD_REQ_FORCE_ALL:
 862                 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
 863                 break;
 864         }
 865 }
 866
 867 int qed_mcp_load_req(struct qed_hwfn *p_hwfn,
 868                      struct qed_ptt *p_ptt,
 869                      struct qed_load_req_params *p_params)
 870 {
 871         struct qed_load_req_out_params out_params;
 872         struct qed_load_req_in_params in_params;
 873         u8 mfw_drv_role, mfw_force_cmd;
 874         int rc;
 875
 876         memset(&in_params, 0, sizeof(in_params));
 877         in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_DEFAULT;
 878         in_params.drv_ver_0 = QED_VERSION;
 879         in_params.drv_ver_1 = qed_get_config_bitmap();
 880         in_params.fw_ver = STORM_FW_VERSION;
 881         rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role);
 882         if (rc)
 883                 return rc;
 884
 885         in_params.drv_role = mfw_drv_role;
 886         in_params.timeout_val = p_params->timeout_val;
 887         qed_get_mfw_force_cmd(p_hwfn,
 888                               QED_LOAD_REQ_FORCE_NONE, &mfw_force_cmd);
 889
 890         in_params.force_cmd = mfw_force_cmd;
 891         in_params.avoid_eng_reset = p_params->avoid_eng_reset;
 892
 893         memset(&out_params, 0, sizeof(out_params));
 894         rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
 895         if (rc)
 896                 return rc;
 897
 898         /* First handle cases where another load request should/might be sent:
 899          * - MFW expects the old interface [HSI version = 1]
 900          * - MFW responds that a force load request is required
 901          */
 902         if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 903                 DP_INFO(p_hwfn,
 904                         "MFW refused a load request due to HSI > 1. Resending with HSI = 1\n");
 905
 906                 in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_1;
 907                 memset(&out_params, 0, sizeof(out_params));
 908                 rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
 909                 if (rc)
 910                         return rc;
 911         } else if (out_params.load_code ==
 912                    FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
 913                 if (qed_mcp_can_force_load(in_params.drv_role,
 914                                            out_params.exist_drv_role,
 915                                            p_params->override_force_load)) {
 916                         DP_INFO(p_hwfn,
 917                                 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}]\n",
 918                                 in_params.drv_role, in_params.fw_ver,
 919                                 in_params.drv_ver_0, in_params.drv_ver_1,
 920                                 out_params.exist_drv_role,
 921                                 out_params.exist_fw_ver,
 922                                 out_params.exist_drv_ver_0,
 923                                 out_params.exist_drv_ver_1);
 924
 925                         qed_get_mfw_force_cmd(p_hwfn,
 926                                               QED_LOAD_REQ_FORCE_ALL,
 927                                               &mfw_force_cmd);
 928
 929                         in_params.force_cmd = mfw_force_cmd;
 930                         memset(&out_params, 0, sizeof(out_params));
 931                         rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params,
 932                                                 &out_params);
 933                         if (rc)
 934                                 return rc;
 935                 } else {
 936                         DP_NOTICE(p_hwfn,
 937                                   "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n",
 938                                   in_params.drv_role, in_params.fw_ver,
 939                                   in_params.drv_ver_0, in_params.drv_ver_1,
 940                                   out_params.exist_drv_role,
 941                                   out_params.exist_fw_ver,
 942                                   out_params.exist_drv_ver_0,
 943                                   out_params.exist_drv_ver_1);
 944                         DP_NOTICE(p_hwfn,
 945                                   "Avoid sending a force load request to prevent disruption of active PFs\n");
 946
 947                         qed_mcp_cancel_load_req(p_hwfn, p_ptt);
 948                         return -EBUSY;
 949                 }
 950         }
 951
 952         /* Now handle the other types of responses.
 953          * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not
 954          * expected here after the additional revised load requests were sent.
 955          */
 956         switch (out_params.load_code) {
 957         case FW_MSG_CODE_DRV_LOAD_ENGINE:
 958         case FW_MSG_CODE_DRV_LOAD_PORT:
 959         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
 960                 if (out_params.mfw_hsi_ver != QED_LOAD_REQ_HSI_VER_1 &&
 961                     out_params.drv_exists) {
 962                         /* The role and fw/driver version match, but the PF is
 963                          * already loaded and has not been unloaded gracefully.
 964                          */
 965                         DP_NOTICE(p_hwfn,
 966                                   "PF is already loaded\n");
 967                         return -EINVAL;
 968                 }
 969                 break;
 970         default:
 971                 DP_NOTICE(p_hwfn,
 972                           "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n",
 973                           out_params.load_code);
 974                 return -EBUSY;
 975         }
 976
 977         p_params->load_code = out_params.load_code;
 978
 979         return 0;
 980 }
 981
 982 int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 983 {
 984         u32 wol_param, mcp_resp, mcp_param;
 985
 986         switch (p_hwfn->cdev->wol_config) {
 987         case QED_OV_WOL_DISABLED:
 988                 wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED;
 989                 break;
 990         case QED_OV_WOL_ENABLED:
 991                 wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED;
 992                 break;
 993         default:
 994                 DP_NOTICE(p_hwfn,
 995                           "Unknown WoL configuration %02x\n",
 996                           p_hwfn->cdev->wol_config);
 997                 /* Fallthrough */
 998         case QED_OV_WOL_DEFAULT:
 999                 wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
1000         }
1001
1002         return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param,
1003                            &mcp_resp, &mcp_param);
1004 }
1005
1006 int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1007 {
1008         struct qed_mcp_mb_params mb_params;
1009         struct mcp_mac wol_mac;
1010
1011         memset(&mb_params, 0, sizeof(mb_params));
1012         mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
1013
1014         /* Set the primary MAC if WoL is enabled */
1015         if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) {
1016                 u8 *p_mac = p_hwfn->cdev->wol_mac;
1017
1018                 memset(&wol_mac, 0, sizeof(wol_mac));
1019                 wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1];
1020                 wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 |
1021                                     p_mac[4] << 8 | p_mac[5];
1022
1023                 DP_VERBOSE(p_hwfn,
1024                            (QED_MSG_SP | NETIF_MSG_IFDOWN),
1025                            "Setting WoL MAC: %pM --> [%08x,%08x]\n",
1026                            p_mac, wol_mac.mac_upper, wol_mac.mac_lower);
1027
1028                 mb_params.p_data_src = &wol_mac;
1029                 mb_params.data_src_size = sizeof(wol_mac);
1030         }
1031
1032         return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1033 }
1034
1035 static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn,
1036                                   struct qed_ptt *p_ptt)
1037 {
1038         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1039                                         PUBLIC_PATH);
1040         u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
1041         u32 path_addr = SECTION_ADDR(mfw_path_offsize,
1042                                      QED_PATH_ID(p_hwfn));
1043         u32 disabled_vfs[VF_MAX_STATIC / 32];
1044         int i;
1045
1046         DP_VERBOSE(p_hwfn,
1047                    QED_MSG_SP,
1048                    "Reading Disabled VF information from [offset %08x], path_addr %08x\n",
1049                    mfw_path_offsize, path_addr);
1050
1051         for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
1052                 disabled_vfs[i] = qed_rd(p_hwfn, p_ptt,
1053                                          path_addr +
1054                                          offsetof(struct public_path,
1055                                                   mcp_vf_disabled) +
1056                                          sizeof(u32) * i);
1057                 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV),
1058                            "FLR-ed VFs [%08x,...,%08x] - %08x\n",
1059                            i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
1060         }
1061
1062         if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs))
1063                 qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG);
1064 }
1065
1066 int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn,
1067                        struct qed_ptt *p_ptt, u32 *vfs_to_ack)
1068 {
1069         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1070                                         PUBLIC_FUNC);
1071         u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr);
1072         u32 func_addr = SECTION_ADDR(mfw_func_offsize,
1073                                      MCP_PF_ID(p_hwfn));
1074         struct qed_mcp_mb_params mb_params;
1075         int rc;
1076         int i;
1077
1078         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1079                 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV),
1080                            "Acking VFs [%08x,...,%08x] - %08x\n",
1081                            i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
1082
1083         memset(&mb_params, 0, sizeof(mb_params));
1084         mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
1085         mb_params.p_data_src = vfs_to_ack;
1086         mb_params.data_src_size = VF_MAX_STATIC / 8;
1087         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1088         if (rc) {
1089                 DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n");
1090                 return -EBUSY;
1091         }
1092
1093         /* Clear the ACK bits */
1094         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1095                 qed_wr(p_hwfn, p_ptt,
1096                        func_addr +
1097                        offsetof(struct public_func, drv_ack_vf_disabled) +
1098                        i * sizeof(u32), 0);
1099
1100         return rc;
1101 }
1102
1103 static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn,
1104                                               struct qed_ptt *p_ptt)
1105 {
1106         u32 transceiver_state;
1107
1108         transceiver_state = qed_rd(p_hwfn, p_ptt,
1109                                    p_hwfn->mcp_info->port_addr +
1110                                    offsetof(struct public_port,
1111                                             transceiver_data));
1112
1113         DP_VERBOSE(p_hwfn,
1114                    (NETIF_MSG_HW | QED_MSG_SP),
1115                    "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n",
1116                    transceiver_state,
1117                    (u32)(p_hwfn->mcp_info->port_addr +
1118                           offsetof(struct public_port, transceiver_data)));
1119
1120         transceiver_state = GET_FIELD(transceiver_state,
1121                                       ETH_TRANSCEIVER_STATE);
1122
1123         if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1124                 DP_NOTICE(p_hwfn, "Transceiver is present.\n");
1125         else
1126                 DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n");
1127 }
1128
1129 static void qed_mcp_read_eee_config(struct qed_hwfn *p_hwfn,
1130                                     struct qed_ptt *p_ptt,
1131                                     struct qed_mcp_link_state *p_link)
1132 {
1133         u32 eee_status, val;
1134
1135         p_link->eee_adv_caps = 0;
1136         p_link->eee_lp_adv_caps = 0;
1137         eee_status = qed_rd(p_hwfn,
1138                             p_ptt,
1139                             p_hwfn->mcp_info->port_addr +
1140                             offsetof(struct public_port, eee_status));
1141         p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT);
1142         val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET;
1143         if (val & EEE_1G_ADV)
1144                 p_link->eee_adv_caps |= QED_EEE_1G_ADV;
1145         if (val & EEE_10G_ADV)
1146                 p_link->eee_adv_caps |= QED_EEE_10G_ADV;
1147         val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET;
1148         if (val & EEE_1G_ADV)
1149                 p_link->eee_lp_adv_caps |= QED_EEE_1G_ADV;
1150         if (val & EEE_10G_ADV)
1151                 p_link->eee_lp_adv_caps |= QED_EEE_10G_ADV;
1152 }
1153
1154 static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn,
1155                                        struct qed_ptt *p_ptt, bool b_reset)
1156 {
1157         struct qed_mcp_link_state *p_link;
1158         u8 max_bw, min_bw;
1159         u32 status = 0;
1160
1161         /* Prevent SW/attentions from doing this at the same time */
1162         spin_lock_bh(&p_hwfn->mcp_info->link_lock);
1163
1164         p_link = &p_hwfn->mcp_info->link_output;
1165         memset(p_link, 0, sizeof(*p_link));
1166         if (!b_reset) {
1167                 status = qed_rd(p_hwfn, p_ptt,
1168                                 p_hwfn->mcp_info->port_addr +
1169                                 offsetof(struct public_port, link_status));
1170                 DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP),
1171                            "Received link update [0x%08x] from mfw [Addr 0x%x]\n",
1172                            status,
1173                            (u32)(p_hwfn->mcp_info->port_addr +
1174                                  offsetof(struct public_port, link_status)));
1175         } else {
1176                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1177                            "Resetting link indications\n");
1178                 goto out;
1179         }
1180
1181         if (p_hwfn->b_drv_link_init)
1182                 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1183         else
1184                 p_link->link_up = false;
1185
1186         p_link->full_duplex = true;
1187         switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1188         case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1189                 p_link->speed = 100000;
1190                 break;
1191         case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1192                 p_link->speed = 50000;
1193                 break;
1194         case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1195                 p_link->speed = 40000;
1196                 break;
1197         case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1198                 p_link->speed = 25000;
1199                 break;
1200         case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1201                 p_link->speed = 20000;
1202                 break;
1203         case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1204                 p_link->speed = 10000;
1205                 break;
1206         case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1207                 p_link->full_duplex = false;
1208         /* Fall-through */
1209         case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1210                 p_link->speed = 1000;
1211                 break;
1212         default:
1213                 p_link->speed = 0;
1214         }
1215
1216         if (p_link->link_up && p_link->speed)
1217                 p_link->line_speed = p_link->speed;
1218         else
1219                 p_link->line_speed = 0;
1220
1221         max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1222         min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1223
1224         /* Max bandwidth configuration */
1225         __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw);
1226
1227         /* Min bandwidth configuration */
1228         __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw);
1229         qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt,
1230                                             p_link->min_pf_rate);
1231
1232         p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1233         p_link->an_complete = !!(status &
1234                                  LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1235         p_link->parallel_detection = !!(status &
1236                                         LINK_STATUS_PARALLEL_DETECTION_USED);
1237         p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1238
1239         p_link->partner_adv_speed |=
1240                 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1241                 QED_LINK_PARTNER_SPEED_1G_FD : 0;
1242         p_link->partner_adv_speed |=
1243                 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1244                 QED_LINK_PARTNER_SPEED_1G_HD : 0;
1245         p_link->partner_adv_speed |=
1246                 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1247                 QED_LINK_PARTNER_SPEED_10G : 0;
1248         p_link->partner_adv_speed |=
1249                 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1250                 QED_LINK_PARTNER_SPEED_20G : 0;
1251         p_link->partner_adv_speed |=
1252                 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1253                 QED_LINK_PARTNER_SPEED_25G : 0;
1254         p_link->partner_adv_speed |=
1255                 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1256                 QED_LINK_PARTNER_SPEED_40G : 0;
1257         p_link->partner_adv_speed |=
1258                 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1259                 QED_LINK_PARTNER_SPEED_50G : 0;
1260         p_link->partner_adv_speed |=
1261                 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1262                 QED_LINK_PARTNER_SPEED_100G : 0;
1263
1264         p_link->partner_tx_flow_ctrl_en =
1265                 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1266         p_link->partner_rx_flow_ctrl_en =
1267                 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1268
1269         switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1270         case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1271                 p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE;
1272                 break;
1273         case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1274                 p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE;
1275                 break;
1276         case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1277                 p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE;
1278                 break;
1279         default:
1280                 p_link->partner_adv_pause = 0;
1281         }
1282
1283         p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1284
1285         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE)
1286                 qed_mcp_read_eee_config(p_hwfn, p_ptt, p_link);
1287
1288         qed_link_update(p_hwfn);
1289 out:
1290         spin_unlock_bh(&p_hwfn->mcp_info->link_lock);
1291 }
1292
1293 int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up)
1294 {
1295         struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1296         struct qed_mcp_mb_params mb_params;
1297         struct eth_phy_cfg phy_cfg;
1298         int rc = 0;
1299         u32 cmd;
1300
1301         /* Set the shmem configuration according to params */
1302         memset(&phy_cfg, 0, sizeof(phy_cfg));
1303         cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1304         if (!params->speed.autoneg)
1305                 phy_cfg.speed = params->speed.forced_speed;
1306         phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1307         phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1308         phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1309         phy_cfg.adv_speed = params->speed.advertised_speeds;
1310         phy_cfg.loopback_mode = params->loopback_mode;
1311         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
1312                 if (params->eee.enable)
1313                         phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED;
1314                 if (params->eee.tx_lpi_enable)
1315                         phy_cfg.eee_cfg |= EEE_CFG_TX_LPI;
1316                 if (params->eee.adv_caps & QED_EEE_1G_ADV)
1317                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G;
1318                 if (params->eee.adv_caps & QED_EEE_10G_ADV)
1319                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G;
1320                 phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer <<
1321                                     EEE_TX_TIMER_USEC_OFFSET) &
1322                                    EEE_TX_TIMER_USEC_MASK;
1323         }
1324
1325         p_hwfn->b_drv_link_init = b_up;
1326
1327         if (b_up) {
1328                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1329                            "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n",
1330                            phy_cfg.speed,
1331                            phy_cfg.pause,
1332                            phy_cfg.adv_speed,
1333                            phy_cfg.loopback_mode,
1334                            phy_cfg.feature_config_flags);
1335         } else {
1336                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1337                            "Resetting link\n");
1338         }
1339
1340         memset(&mb_params, 0, sizeof(mb_params));
1341         mb_params.cmd = cmd;
1342         mb_params.p_data_src = &phy_cfg;
1343         mb_params.data_src_size = sizeof(phy_cfg);
1344         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1345
1346         /* if mcp fails to respond we must abort */
1347         if (rc) {
1348                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1349                 return rc;
1350         }
1351
1352         /* Mimic link-change attention, done for several reasons:
1353          *  - On reset, there's no guarantee MFW would trigger
1354          *    an attention.
1355          *  - On initialization, older MFWs might not indicate link change
1356          *    during LFA, so we'll never get an UP indication.
1357          */
1358         qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up);
1359
1360         return 0;
1361 }
1362
1363 static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn,
1364                                         struct qed_ptt *p_ptt,
1365                                         enum MFW_DRV_MSG_TYPE type)
1366 {
1367         enum qed_mcp_protocol_type stats_type;
1368         union qed_mcp_protocol_stats stats;
1369         struct qed_mcp_mb_params mb_params;
1370         u32 hsi_param;
1371
1372         switch (type) {
1373         case MFW_DRV_MSG_GET_LAN_STATS:
1374                 stats_type = QED_MCP_LAN_STATS;
1375                 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1376                 break;
1377         case MFW_DRV_MSG_GET_FCOE_STATS:
1378                 stats_type = QED_MCP_FCOE_STATS;
1379                 hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE;
1380                 break;
1381         case MFW_DRV_MSG_GET_ISCSI_STATS:
1382                 stats_type = QED_MCP_ISCSI_STATS;
1383                 hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI;
1384                 break;
1385         case MFW_DRV_MSG_GET_RDMA_STATS:
1386                 stats_type = QED_MCP_RDMA_STATS;
1387                 hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA;
1388                 break;
1389         default:
1390                 DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type);
1391                 return;
1392         }
1393
1394         qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats);
1395
1396         memset(&mb_params, 0, sizeof(mb_params));
1397         mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1398         mb_params.param = hsi_param;
1399         mb_params.p_data_src = &stats;
1400         mb_params.data_src_size = sizeof(stats);
1401         qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1402 }
1403
1404 static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn,
1405                                   struct public_func *p_shmem_info)
1406 {
1407         struct qed_mcp_function_info *p_info;
1408
1409         p_info = &p_hwfn->mcp_info->func_info;
1410
1411         p_info->bandwidth_min = (p_shmem_info->config &
1412                                  FUNC_MF_CFG_MIN_BW_MASK) >>
1413                                         FUNC_MF_CFG_MIN_BW_SHIFT;
1414         if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1415                 DP_INFO(p_hwfn,
1416                         "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1417                         p_info->bandwidth_min);
1418                 p_info->bandwidth_min = 1;
1419         }
1420
1421         p_info->bandwidth_max = (p_shmem_info->config &
1422                                  FUNC_MF_CFG_MAX_BW_MASK) >>
1423                                         FUNC_MF_CFG_MAX_BW_SHIFT;
1424         if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1425                 DP_INFO(p_hwfn,
1426                         "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1427                         p_info->bandwidth_max);
1428                 p_info->bandwidth_max = 100;
1429         }
1430 }
1431
1432 static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn,
1433                                   struct qed_ptt *p_ptt,
1434                                   struct public_func *p_data, int pfid)
1435 {
1436         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1437                                         PUBLIC_FUNC);
1438         u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
1439         u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1440         u32 i, size;
1441
1442         memset(p_data, 0, sizeof(*p_data));
1443
1444         size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize));
1445         for (i = 0; i < size / sizeof(u32); i++)
1446                 ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt,
1447                                             func_addr + (i << 2));
1448         return size;
1449 }
1450
1451 static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1452 {
1453         struct qed_mcp_function_info *p_info;
1454         struct public_func shmem_info;
1455         u32 resp = 0, param = 0;
1456
1457         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1458
1459         qed_read_pf_bandwidth(p_hwfn, &shmem_info);
1460
1461         p_info = &p_hwfn->mcp_info->func_info;
1462
1463         qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min);
1464         qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max);
1465
1466         /* Acknowledge the MFW */
1467         qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1468                     &param);
1469 }
1470
1471 static void qed_mcp_update_stag(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1472 {
1473         struct public_func shmem_info;
1474         u32 resp = 0, param = 0;
1475
1476         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1477
1478         p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag &
1479                                                  FUNC_MF_CFG_OV_STAG_MASK;
1480         p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan;
1481         if ((p_hwfn->hw_info.hw_mode & BIT(MODE_MF_SD)) &&
1482             (p_hwfn->hw_info.ovlan != QED_MCP_VLAN_UNSET)) {
1483                 qed_wr(p_hwfn, p_ptt,
1484                        NIG_REG_LLH_FUNC_TAG_VALUE, p_hwfn->hw_info.ovlan);
1485                 qed_sp_pf_update_stag(p_hwfn);
1486         }
1487
1488         /* Acknowledge the MFW */
1489         qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0,
1490                     &resp, &param);
1491 }
1492
1493 void qed_mcp_read_ufp_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1494 {
1495         struct public_func shmem_info;
1496         u32 port_cfg, val;
1497
1498         if (!test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits))
1499                 return;
1500
1501         memset(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info));
1502         port_cfg = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1503                           offsetof(struct public_port, oem_cfg_port));
1504         val = (port_cfg & OEM_CFG_CHANNEL_TYPE_MASK) >>
1505                 OEM_CFG_CHANNEL_TYPE_OFFSET;
1506         if (val != OEM_CFG_CHANNEL_TYPE_STAGGED)
1507                 DP_NOTICE(p_hwfn, "Incorrect UFP Channel type  %d\n", val);
1508
1509         val = (port_cfg & OEM_CFG_SCHED_TYPE_MASK) >> OEM_CFG_SCHED_TYPE_OFFSET;
1510         if (val == OEM_CFG_SCHED_TYPE_ETS) {
1511                 p_hwfn->ufp_info.mode = QED_UFP_MODE_ETS;
1512         } else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW) {
1513                 p_hwfn->ufp_info.mode = QED_UFP_MODE_VNIC_BW;
1514         } else {
1515                 p_hwfn->ufp_info.mode = QED_UFP_MODE_UNKNOWN;
1516                 DP_NOTICE(p_hwfn, "Unknown UFP scheduling mode %d\n", val);
1517         }
1518
1519         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1520         val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_TC_MASK) >>
1521                 OEM_CFG_FUNC_TC_OFFSET;
1522         p_hwfn->ufp_info.tc = (u8)val;
1523         val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_HOST_PRI_CTRL_MASK) >>
1524                 OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET;
1525         if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC) {
1526                 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_VNIC;
1527         } else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS) {
1528                 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_OS;
1529         } else {
1530                 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_UNKNOWN;
1531                 DP_NOTICE(p_hwfn, "Unknown Host priority control %d\n", val);
1532         }
1533
1534         DP_NOTICE(p_hwfn,
1535                   "UFP shmem config: mode = %d tc = %d pri_type = %d\n",
1536                   p_hwfn->ufp_info.mode,
1537                   p_hwfn->ufp_info.tc, p_hwfn->ufp_info.pri_type);
1538 }
1539
1540 static int
1541 qed_mcp_handle_ufp_event(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1542 {
1543         qed_mcp_read_ufp_config(p_hwfn, p_ptt);
1544
1545         if (p_hwfn->ufp_info.mode == QED_UFP_MODE_VNIC_BW) {
1546                 p_hwfn->qm_info.ooo_tc = p_hwfn->ufp_info.tc;
1547                 p_hwfn->hw_info.offload_tc = p_hwfn->ufp_info.tc;
1548
1549                 qed_qm_reconf(p_hwfn, p_ptt);
1550         } else if (p_hwfn->ufp_info.mode == QED_UFP_MODE_ETS) {
1551                 /* Merge UFP TC with the dcbx TC data */
1552                 qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1553                                           QED_DCBX_OPERATIONAL_MIB);
1554         } else {
1555                 DP_ERR(p_hwfn, "Invalid sched type, discard the UFP config\n");
1556                 return -EINVAL;
1557         }
1558
1559         /* update storm FW with negotiation results */
1560         qed_sp_pf_update_ufp(p_hwfn);
1561
1562         /* update stag pcp value */
1563         qed_sp_pf_update_stag(p_hwfn);
1564
1565         return 0;
1566 }
1567
1568 int qed_mcp_handle_events(struct qed_hwfn *p_hwfn,
1569                           struct qed_ptt *p_ptt)
1570 {
1571         struct qed_mcp_info *info = p_hwfn->mcp_info;
1572         int rc = 0;
1573         bool found = false;
1574         u16 i;
1575
1576         DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n");
1577
1578         /* Read Messages from MFW */
1579         qed_mcp_read_mb(p_hwfn, p_ptt);
1580
1581         /* Compare current messages to old ones */
1582         for (i = 0; i < info->mfw_mb_length; i++) {
1583                 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1584                         continue;
1585
1586                 found = true;
1587
1588                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1589                            "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1590                            i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1591
1592                 switch (i) {
1593                 case MFW_DRV_MSG_LINK_CHANGE:
1594                         qed_mcp_handle_link_change(p_hwfn, p_ptt, false);
1595                         break;
1596                 case MFW_DRV_MSG_VF_DISABLED:
1597                         qed_mcp_handle_vf_flr(p_hwfn, p_ptt);
1598                         break;
1599                 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1600                         qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1601                                                   QED_DCBX_REMOTE_LLDP_MIB);
1602                         break;
1603                 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1604                         qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1605                                                   QED_DCBX_REMOTE_MIB);
1606                         break;
1607                 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1608                         qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1609                                                   QED_DCBX_OPERATIONAL_MIB);
1610                         break;
1611                 case MFW_DRV_MSG_OEM_CFG_UPDATE:
1612                         qed_mcp_handle_ufp_event(p_hwfn, p_ptt);
1613                         break;
1614                 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1615                         qed_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1616                         break;
1617                 case MFW_DRV_MSG_GET_LAN_STATS:
1618                 case MFW_DRV_MSG_GET_FCOE_STATS:
1619                 case MFW_DRV_MSG_GET_ISCSI_STATS:
1620                 case MFW_DRV_MSG_GET_RDMA_STATS:
1621                         qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1622                         break;
1623                 case MFW_DRV_MSG_BW_UPDATE:
1624                         qed_mcp_update_bw(p_hwfn, p_ptt);
1625                         break;
1626                 case MFW_DRV_MSG_S_TAG_UPDATE:
1627                         qed_mcp_update_stag(p_hwfn, p_ptt);
1628                         break;
1629                 case MFW_DRV_MSG_GET_TLV_REQ:
1630                         qed_mfw_tlv_req(p_hwfn);
1631                         break;
1632                 default:
1633                         DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
1634                         rc = -EINVAL;
1635                 }
1636         }
1637
1638         /* ACK everything */
1639         for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1640                 __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]);
1641
1642                 /* MFW expect answer in BE, so we force write in that format */
1643                 qed_wr(p_hwfn, p_ptt,
1644                        info->mfw_mb_addr + sizeof(u32) +
1645                        MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1646                        sizeof(u32) + i * sizeof(u32),
1647                        (__force u32)val);
1648         }
1649
1650         if (!found) {
1651                 DP_NOTICE(p_hwfn,
1652                           "Received an MFW message indication but no new message!\n");
1653                 rc = -EINVAL;
1654         }
1655
1656         /* Copy the new mfw messages into the shadow */
1657         memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1658
1659         return rc;
1660 }
1661
1662 int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn,
1663                         struct qed_ptt *p_ptt,
1664                         u32 *p_mfw_ver, u32 *p_running_bundle_id)
1665 {
1666         u32 global_offsize;
1667
1668         if (IS_VF(p_hwfn->cdev)) {
1669                 if (p_hwfn->vf_iov_info) {
1670                         struct pfvf_acquire_resp_tlv *p_resp;
1671
1672                         p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1673                         *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1674                         return 0;
1675                 } else {
1676                         DP_VERBOSE(p_hwfn,
1677                                    QED_MSG_IOV,
1678                                    "VF requested MFW version prior to ACQUIRE\n");
1679                         return -EINVAL;
1680                 }
1681         }
1682
1683         global_offsize = qed_rd(p_hwfn, p_ptt,
1684                                 SECTION_OFFSIZE_ADDR(p_hwfn->
1685                                                      mcp_info->public_base,
1686                                                      PUBLIC_GLOBAL));
1687         *p_mfw_ver =
1688             qed_rd(p_hwfn, p_ptt,
1689                    SECTION_ADDR(global_offsize,
1690                                 0) + offsetof(struct public_global, mfw_ver));
1691
1692         if (p_running_bundle_id != NULL) {
1693                 *p_running_bundle_id = qed_rd(p_hwfn, p_ptt,
1694                                               SECTION_ADDR(global_offsize, 0) +
1695                                               offsetof(struct public_global,
1696                                                        running_bundle_id));
1697         }
1698
1699         return 0;
1700 }
1701
1702 int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn,
1703                         struct qed_ptt *p_ptt, u32 *p_mbi_ver)
1704 {
1705         u32 nvm_cfg_addr, nvm_cfg1_offset, mbi_ver_addr;
1706
1707         if (IS_VF(p_hwfn->cdev))
1708                 return -EINVAL;
1709
1710         /* Read the address of the nvm_cfg */
1711         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
1712         if (!nvm_cfg_addr) {
1713                 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
1714                 return -EINVAL;
1715         }
1716
1717         /* Read the offset of nvm_cfg1 */
1718         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
1719
1720         mbi_ver_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1721                        offsetof(struct nvm_cfg1, glob) +
1722                        offsetof(struct nvm_cfg1_glob, mbi_version);
1723         *p_mbi_ver = qed_rd(p_hwfn, p_ptt,
1724                             mbi_ver_addr) &
1725                      (NVM_CFG1_GLOB_MBI_VERSION_0_MASK |
1726                       NVM_CFG1_GLOB_MBI_VERSION_1_MASK |
1727                       NVM_CFG1_GLOB_MBI_VERSION_2_MASK);
1728
1729         return 0;
1730 }
1731
1732 int qed_mcp_get_media_type(struct qed_dev *cdev, u32 *p_media_type)
1733 {
1734         struct qed_hwfn *p_hwfn = &cdev->hwfns[0];
1735         struct qed_ptt  *p_ptt;
1736
1737         if (IS_VF(cdev))
1738                 return -EINVAL;
1739
1740         if (!qed_mcp_is_init(p_hwfn)) {
1741                 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
1742                 return -EBUSY;
1743         }
1744
1745         *p_media_type = MEDIA_UNSPECIFIED;
1746
1747         p_ptt = qed_ptt_acquire(p_hwfn);
1748         if (!p_ptt)
1749                 return -EBUSY;
1750
1751         *p_media_type = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1752                                offsetof(struct public_port, media_type));
1753
1754         qed_ptt_release(p_hwfn, p_ptt);
1755
1756         return 0;
1757 }
1758
1759 /* Old MFW has a global configuration for all PFs regarding RDMA support */
1760 static void
1761 qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn,
1762                                enum qed_pci_personality *p_proto)
1763 {
1764         /* There wasn't ever a legacy MFW that published iwarp.
1765          * So at this point, this is either plain l2 or RoCE.
1766          */
1767         if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities))
1768                 *p_proto = QED_PCI_ETH_ROCE;
1769         else
1770                 *p_proto = QED_PCI_ETH;
1771
1772         DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
1773                    "According to Legacy capabilities, L2 personality is %08x\n",
1774                    (u32) *p_proto);
1775 }
1776
1777 static int
1778 qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn,
1779                             struct qed_ptt *p_ptt,
1780                             enum qed_pci_personality *p_proto)
1781 {
1782         u32 resp = 0, param = 0;
1783         int rc;
1784
1785         rc = qed_mcp_cmd(p_hwfn, p_ptt,
1786                          DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, &param);
1787         if (rc)
1788                 return rc;
1789         if (resp != FW_MSG_CODE_OK) {
1790                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
1791                            "MFW lacks support for command; Returns %08x\n",
1792                            resp);
1793                 return -EINVAL;
1794         }
1795
1796         switch (param) {
1797         case FW_MB_PARAM_GET_PF_RDMA_NONE:
1798                 *p_proto = QED_PCI_ETH;
1799                 break;
1800         case FW_MB_PARAM_GET_PF_RDMA_ROCE:
1801                 *p_proto = QED_PCI_ETH_ROCE;
1802                 break;
1803         case FW_MB_PARAM_GET_PF_RDMA_IWARP:
1804                 *p_proto = QED_PCI_ETH_IWARP;
1805                 break;
1806         case FW_MB_PARAM_GET_PF_RDMA_BOTH:
1807                 *p_proto = QED_PCI_ETH_RDMA;
1808                 break;
1809         default:
1810                 DP_NOTICE(p_hwfn,
1811                           "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n",
1812                           param);
1813                 return -EINVAL;
1814         }
1815
1816         DP_VERBOSE(p_hwfn,
1817                    NETIF_MSG_IFUP,
1818                    "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
1819                    (u32) *p_proto, resp, param);
1820         return 0;
1821 }
1822
1823 static int
1824 qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn,
1825                         struct public_func *p_info,
1826                         struct qed_ptt *p_ptt,
1827                         enum qed_pci_personality *p_proto)
1828 {
1829         int rc = 0;
1830
1831         switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
1832         case FUNC_MF_CFG_PROTOCOL_ETHERNET:
1833                 if (!IS_ENABLED(CONFIG_QED_RDMA))
1834                         *p_proto = QED_PCI_ETH;
1835                 else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto))
1836                         qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
1837                 break;
1838         case FUNC_MF_CFG_PROTOCOL_ISCSI:
1839                 *p_proto = QED_PCI_ISCSI;
1840                 break;
1841         case FUNC_MF_CFG_PROTOCOL_FCOE:
1842                 *p_proto = QED_PCI_FCOE;
1843                 break;
1844         case FUNC_MF_CFG_PROTOCOL_ROCE:
1845                 DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n");
1846         /* Fallthrough */
1847         default:
1848                 rc = -EINVAL;
1849         }
1850
1851         return rc;
1852 }
1853
1854 int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn,
1855                                  struct qed_ptt *p_ptt)
1856 {
1857         struct qed_mcp_function_info *info;
1858         struct public_func shmem_info;
1859
1860         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1861         info = &p_hwfn->mcp_info->func_info;
1862
1863         info->pause_on_host = (shmem_info.config &
1864                                FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
1865
1866         if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
1867                                     &info->protocol)) {
1868                 DP_ERR(p_hwfn, "Unknown personality %08x\n",
1869                        (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
1870                 return -EINVAL;
1871         }
1872
1873         qed_read_pf_bandwidth(p_hwfn, &shmem_info);
1874
1875         if (shmem_info.mac_upper || shmem_info.mac_lower) {
1876                 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
1877                 info->mac[1] = (u8)(shmem_info.mac_upper);
1878                 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
1879                 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
1880                 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
1881                 info->mac[5] = (u8)(shmem_info.mac_lower);
1882
1883                 /* Store primary MAC for later possible WoL */
1884                 memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN);
1885         } else {
1886                 DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n");
1887         }
1888
1889         info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_lower |
1890                          (((u64)shmem_info.fcoe_wwn_port_name_upper) << 32);
1891         info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_lower |
1892                          (((u64)shmem_info.fcoe_wwn_node_name_upper) << 32);
1893
1894         info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
1895
1896         info->mtu = (u16)shmem_info.mtu_size;
1897
1898         p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE;
1899         p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT;
1900         if (qed_mcp_is_init(p_hwfn)) {
1901                 u32 resp = 0, param = 0;
1902                 int rc;
1903
1904                 rc = qed_mcp_cmd(p_hwfn, p_ptt,
1905                                  DRV_MSG_CODE_OS_WOL, 0, &resp, &param);
1906                 if (rc)
1907                         return rc;
1908                 if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED)
1909                         p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME;
1910         }
1911
1912         DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP),
1913                    "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x wol %02x\n",
1914                 info->pause_on_host, info->protocol,
1915                 info->bandwidth_min, info->bandwidth_max,
1916                 info->mac[0], info->mac[1], info->mac[2],
1917                 info->mac[3], info->mac[4], info->mac[5],
1918                 info->wwn_port, info->wwn_node,
1919                 info->ovlan, (u8)p_hwfn->hw_info.b_wol_support);
1920
1921         return 0;
1922 }
1923
1924 struct qed_mcp_link_params
1925 *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn)
1926 {
1927         if (!p_hwfn || !p_hwfn->mcp_info)
1928                 return NULL;
1929         return &p_hwfn->mcp_info->link_input;
1930 }
1931
1932 struct qed_mcp_link_state
1933 *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn)
1934 {
1935         if (!p_hwfn || !p_hwfn->mcp_info)
1936                 return NULL;
1937         return &p_hwfn->mcp_info->link_output;
1938 }
1939
1940 struct qed_mcp_link_capabilities
1941 *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn)
1942 {
1943         if (!p_hwfn || !p_hwfn->mcp_info)
1944                 return NULL;
1945         return &p_hwfn->mcp_info->link_capabilities;
1946 }
1947
1948 int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1949 {
1950         u32 resp = 0, param = 0;
1951         int rc;
1952
1953         rc = qed_mcp_cmd(p_hwfn, p_ptt,
1954                          DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, &param);
1955
1956         /* Wait for the drain to complete before returning */
1957         msleep(1020);
1958
1959         return rc;
1960 }
1961
1962 int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn,
1963                            struct qed_ptt *p_ptt, u32 *p_flash_size)
1964 {
1965         u32 flash_size;
1966
1967         if (IS_VF(p_hwfn->cdev))
1968                 return -EINVAL;
1969
1970         flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
1971         flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
1972                       MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
1973         flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
1974
1975         *p_flash_size = flash_size;
1976
1977         return 0;
1978 }
1979
1980 static int
1981 qed_mcp_config_vf_msix_bb(struct qed_hwfn *p_hwfn,
1982                           struct qed_ptt *p_ptt, u8 vf_id, u8 num)
1983 {
1984         u32 resp = 0, param = 0, rc_param = 0;
1985         int rc;
1986
1987         /* Only Leader can configure MSIX, and need to take CMT into account */
1988         if (!IS_LEAD_HWFN(p_hwfn))
1989                 return 0;
1990         num *= p_hwfn->cdev->num_hwfns;
1991
1992         param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
1993                  DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
1994         param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
1995                  DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
1996
1997         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
1998                          &resp, &rc_param);
1999
2000         if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
2001                 DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id);
2002                 rc = -EINVAL;
2003         } else {
2004                 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2005                            "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
2006                            num, vf_id);
2007         }
2008
2009         return rc;
2010 }
2011
2012 static int
2013 qed_mcp_config_vf_msix_ah(struct qed_hwfn *p_hwfn,
2014                           struct qed_ptt *p_ptt, u8 num)
2015 {
2016         u32 resp = 0, param = num, rc_param = 0;
2017         int rc;
2018
2019         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX,
2020                          param, &resp, &rc_param);
2021
2022         if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) {
2023                 DP_NOTICE(p_hwfn, "MFW failed to set MSI-X for VFs\n");
2024                 rc = -EINVAL;
2025         } else {
2026                 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2027                            "Requested 0x%02x MSI-x interrupts for VFs\n", num);
2028         }
2029
2030         return rc;
2031 }
2032
2033 int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn,
2034                            struct qed_ptt *p_ptt, u8 vf_id, u8 num)
2035 {
2036         if (QED_IS_BB(p_hwfn->cdev))
2037                 return qed_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num);
2038         else
2039                 return qed_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num);
2040 }
2041
2042 int
2043 qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn,
2044                          struct qed_ptt *p_ptt,
2045                          struct qed_mcp_drv_version *p_ver)
2046 {
2047         struct qed_mcp_mb_params mb_params;
2048         struct drv_version_stc drv_version;
2049         __be32 val;
2050         u32 i;
2051         int rc;
2052
2053         memset(&drv_version, 0, sizeof(drv_version));
2054         drv_version.version = p_ver->version;
2055         for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) {
2056                 val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)]));
2057                 *(__be32 *)&drv_version.name[i * sizeof(u32)] = val;
2058         }
2059
2060         memset(&mb_params, 0, sizeof(mb_params));
2061         mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
2062         mb_params.p_data_src = &drv_version;
2063         mb_params.data_src_size = sizeof(drv_version);
2064         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2065         if (rc)
2066                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2067
2068         return rc;
2069 }
2070
2071 int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2072 {
2073         u32 resp = 0, param = 0;
2074         int rc;
2075
2076         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
2077                          &param);
2078         if (rc)
2079                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2080
2081         return rc;
2082 }
2083
2084 int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2085 {
2086         u32 value, cpu_mode;
2087
2088         qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
2089
2090         value = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2091         value &= ~MCP_REG_CPU_MODE_SOFT_HALT;
2092         qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value);
2093         cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2094
2095         return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -EAGAIN : 0;
2096 }
2097
2098 int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn,
2099                                      struct qed_ptt *p_ptt,
2100                                      enum qed_ov_client client)
2101 {
2102         u32 resp = 0, param = 0;
2103         u32 drv_mb_param;
2104         int rc;
2105
2106         switch (client) {
2107         case QED_OV_CLIENT_DRV:
2108                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
2109                 break;
2110         case QED_OV_CLIENT_USER:
2111                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
2112                 break;
2113         case QED_OV_CLIENT_VENDOR_SPEC:
2114                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
2115                 break;
2116         default:
2117                 DP_NOTICE(p_hwfn, "Invalid client type %d\n", client);
2118                 return -EINVAL;
2119         }
2120
2121         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
2122                          drv_mb_param, &resp, &param);
2123         if (rc)
2124                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2125
2126         return rc;
2127 }
2128
2129 int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn,
2130                                    struct qed_ptt *p_ptt,
2131                                    enum qed_ov_driver_state drv_state)
2132 {
2133         u32 resp = 0, param = 0;
2134         u32 drv_mb_param;
2135         int rc;
2136
2137         switch (drv_state) {
2138         case QED_OV_DRIVER_STATE_NOT_LOADED:
2139                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
2140                 break;
2141         case QED_OV_DRIVER_STATE_DISABLED:
2142                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
2143                 break;
2144         case QED_OV_DRIVER_STATE_ACTIVE:
2145                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
2146                 break;
2147         default:
2148                 DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state);
2149                 return -EINVAL;
2150         }
2151
2152         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
2153                          drv_mb_param, &resp, &param);
2154         if (rc)
2155                 DP_ERR(p_hwfn, "Failed to send driver state\n");
2156
2157         return rc;
2158 }
2159
2160 int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn,
2161                           struct qed_ptt *p_ptt, u16 mtu)
2162 {
2163         u32 resp = 0, param = 0;
2164         u32 drv_mb_param;
2165         int rc;
2166
2167         drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT;
2168         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU,
2169                          drv_mb_param, &resp, &param);
2170         if (rc)
2171                 DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc);
2172
2173         return rc;
2174 }
2175
2176 int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn,
2177                           struct qed_ptt *p_ptt, u8 *mac)
2178 {
2179         struct qed_mcp_mb_params mb_params;
2180         u32 mfw_mac[2];
2181         int rc;
2182
2183         memset(&mb_params, 0, sizeof(mb_params));
2184         mb_params.cmd = DRV_MSG_CODE_SET_VMAC;
2185         mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC <<
2186                           DRV_MSG_CODE_VMAC_TYPE_SHIFT;
2187         mb_params.param |= MCP_PF_ID(p_hwfn);
2188
2189         /* MCP is BE, and on LE platforms PCI would swap access to SHMEM
2190          * in 32-bit granularity.
2191          * So the MAC has to be set in native order [and not byte order],
2192          * otherwise it would be read incorrectly by MFW after swap.
2193          */
2194         mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3];
2195         mfw_mac[1] = mac[4] << 24 | mac[5] << 16;
2196
2197         mb_params.p_data_src = (u8 *)mfw_mac;
2198         mb_params.data_src_size = 8;
2199         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2200         if (rc)
2201                 DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc);
2202
2203         /* Store primary MAC for later possible WoL */
2204         memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN);
2205
2206         return rc;
2207 }
2208
2209 int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn,
2210                           struct qed_ptt *p_ptt, enum qed_ov_wol wol)
2211 {
2212         u32 resp = 0, param = 0;
2213         u32 drv_mb_param;
2214         int rc;
2215
2216         if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) {
2217                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
2218                            "Can't change WoL configuration when WoL isn't supported\n");
2219                 return -EINVAL;
2220         }
2221
2222         switch (wol) {
2223         case QED_OV_WOL_DEFAULT:
2224                 drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT;
2225                 break;
2226         case QED_OV_WOL_DISABLED:
2227                 drv_mb_param = DRV_MB_PARAM_WOL_DISABLED;
2228                 break;
2229         case QED_OV_WOL_ENABLED:
2230                 drv_mb_param = DRV_MB_PARAM_WOL_ENABLED;
2231                 break;
2232         default:
2233                 DP_ERR(p_hwfn, "Invalid wol state %d\n", wol);
2234                 return -EINVAL;
2235         }
2236
2237         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL,
2238                          drv_mb_param, &resp, &param);
2239         if (rc)
2240                 DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc);
2241
2242         /* Store the WoL update for a future unload */
2243         p_hwfn->cdev->wol_config = (u8)wol;
2244
2245         return rc;
2246 }
2247
2248 int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn,
2249                               struct qed_ptt *p_ptt,
2250                               enum qed_ov_eswitch eswitch)
2251 {
2252         u32 resp = 0, param = 0;
2253         u32 drv_mb_param;
2254         int rc;
2255
2256         switch (eswitch) {
2257         case QED_OV_ESWITCH_NONE:
2258                 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE;
2259                 break;
2260         case QED_OV_ESWITCH_VEB:
2261                 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB;
2262                 break;
2263         case QED_OV_ESWITCH_VEPA:
2264                 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA;
2265                 break;
2266         default:
2267                 DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch);
2268                 return -EINVAL;
2269         }
2270
2271         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE,
2272                          drv_mb_param, &resp, &param);
2273         if (rc)
2274                 DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc);
2275
2276         return rc;
2277 }
2278
2279 int qed_mcp_set_led(struct qed_hwfn *p_hwfn,
2280                     struct qed_ptt *p_ptt, enum qed_led_mode mode)
2281 {
2282         u32 resp = 0, param = 0, drv_mb_param;
2283         int rc;
2284
2285         switch (mode) {
2286         case QED_LED_MODE_ON:
2287                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2288                 break;
2289         case QED_LED_MODE_OFF:
2290                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2291                 break;
2292         case QED_LED_MODE_RESTORE:
2293                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2294                 break;
2295         default:
2296                 DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode);
2297                 return -EINVAL;
2298         }
2299
2300         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2301                          drv_mb_param, &resp, &param);
2302
2303         return rc;
2304 }
2305
2306 int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn,
2307                           struct qed_ptt *p_ptt, u32 mask_parities)
2308 {
2309         u32 resp = 0, param = 0;
2310         int rc;
2311
2312         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2313                          mask_parities, &resp, &param);
2314
2315         if (rc) {
2316                 DP_ERR(p_hwfn,
2317                        "MCP response failure for mask parities, aborting\n");
2318         } else if (resp != FW_MSG_CODE_OK) {
2319                 DP_ERR(p_hwfn,
2320                        "MCP did not acknowledge mask parity request. Old MFW?\n");
2321                 rc = -EINVAL;
2322         }
2323
2324         return rc;
2325 }
2326
2327 int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len)
2328 {
2329         u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0;
2330         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2331         u32 resp = 0, resp_param = 0;
2332         struct qed_ptt *p_ptt;
2333         int rc = 0;
2334
2335         p_ptt = qed_ptt_acquire(p_hwfn);
2336         if (!p_ptt)
2337                 return -EBUSY;
2338
2339         while (bytes_left > 0) {
2340                 bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN);
2341
2342                 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2343                                         DRV_MSG_CODE_NVM_READ_NVRAM,
2344                                         addr + offset +
2345                                         (bytes_to_copy <<
2346                                          DRV_MB_PARAM_NVM_LEN_OFFSET),
2347                                         &resp, &resp_param,
2348                                         &read_len,
2349                                         (u32 *)(p_buf + offset));
2350
2351                 if (rc || (resp != FW_MSG_CODE_NVM_OK)) {
2352                         DP_NOTICE(cdev, "MCP command rc = %d\n", rc);
2353                         break;
2354                 }
2355
2356                 /* This can be a lengthy process, and it's possible scheduler
2357                  * isn't preemptable. Sleep a bit to prevent CPU hogging.
2358                  */
2359                 if (bytes_left % 0x1000 <
2360                     (bytes_left - read_len) % 0x1000)
2361                         usleep_range(1000, 2000);
2362
2363                 offset += read_len;
2364                 bytes_left -= read_len;
2365         }
2366
2367         cdev->mcp_nvm_resp = resp;
2368         qed_ptt_release(p_hwfn, p_ptt);
2369
2370         return rc;
2371 }
2372
2373 int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf)
2374 {
2375         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2376         struct qed_ptt *p_ptt;
2377
2378         p_ptt = qed_ptt_acquire(p_hwfn);
2379         if (!p_ptt)
2380                 return -EBUSY;
2381
2382         memcpy(p_buf, &cdev->mcp_nvm_resp, sizeof(cdev->mcp_nvm_resp));
2383         qed_ptt_release(p_hwfn, p_ptt);
2384
2385         return 0;
2386 }
2387
2388 int qed_mcp_nvm_put_file_begin(struct qed_dev *cdev, u32 addr)
2389 {
2390         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2391         struct qed_ptt *p_ptt;
2392         u32 resp, param;
2393         int rc;
2394
2395         p_ptt = qed_ptt_acquire(p_hwfn);
2396         if (!p_ptt)
2397                 return -EBUSY;
2398         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, addr,
2399                          &resp, &param);
2400         cdev->mcp_nvm_resp = resp;
2401         qed_ptt_release(p_hwfn, p_ptt);
2402
2403         return rc;
2404 }
2405
2406 int qed_mcp_nvm_write(struct qed_dev *cdev,
2407                       u32 cmd, u32 addr, u8 *p_buf, u32 len)
2408 {
2409         u32 buf_idx = 0, buf_size, nvm_cmd, nvm_offset, resp = 0, param;
2410         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2411         struct qed_ptt *p_ptt;
2412         int rc = -EINVAL;
2413
2414         p_ptt = qed_ptt_acquire(p_hwfn);
2415         if (!p_ptt)
2416                 return -EBUSY;
2417
2418         switch (cmd) {
2419         case QED_PUT_FILE_DATA:
2420                 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
2421                 break;
2422         case QED_NVM_WRITE_NVRAM:
2423                 nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2424                 break;
2425         default:
2426                 DP_NOTICE(p_hwfn, "Invalid nvm write command 0x%x\n", cmd);
2427                 rc = -EINVAL;
2428                 goto out;
2429         }
2430
2431         while (buf_idx < len) {
2432                 buf_size = min_t(u32, (len - buf_idx), MCP_DRV_NVM_BUF_LEN);
2433                 nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_OFFSET) |
2434                               addr) + buf_idx;
2435                 rc = qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset,
2436                                         &resp, &param, buf_size,
2437                                         (u32 *)&p_buf[buf_idx]);
2438                 if (rc) {
2439                         DP_NOTICE(cdev, "nvm write failed, rc = %d\n", rc);
2440                         resp = FW_MSG_CODE_ERROR;
2441                         break;
2442                 }
2443
2444                 if (resp != FW_MSG_CODE_OK &&
2445                     resp != FW_MSG_CODE_NVM_OK &&
2446                     resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) {
2447                         DP_NOTICE(cdev,
2448                                   "nvm write failed, resp = 0x%08x\n", resp);
2449                         rc = -EINVAL;
2450                         break;
2451                 }
2452
2453                 /* This can be a lengthy process, and it's possible scheduler
2454                  * isn't pre-emptable. Sleep a bit to prevent CPU hogging.
2455                  */
2456                 if (buf_idx % 0x1000 > (buf_idx + buf_size) % 0x1000)
2457                         usleep_range(1000, 2000);
2458
2459                 buf_idx += buf_size;
2460         }
2461
2462         cdev->mcp_nvm_resp = resp;
2463 out:
2464         qed_ptt_release(p_hwfn, p_ptt);
2465
2466         return rc;
2467 }
2468
2469 int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2470 {
2471         u32 drv_mb_param = 0, rsp, param;
2472         int rc = 0;
2473
2474         drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
2475                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2476
2477         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2478                          drv_mb_param, &rsp, &param);
2479
2480         if (rc)
2481                 return rc;
2482
2483         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2484             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2485                 rc = -EAGAIN;
2486
2487         return rc;
2488 }
2489
2490 int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2491 {
2492         u32 drv_mb_param, rsp, param;
2493         int rc = 0;
2494
2495         drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
2496                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2497
2498         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2499                          drv_mb_param, &rsp, &param);
2500
2501         if (rc)
2502                 return rc;
2503
2504         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2505             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2506                 rc = -EAGAIN;
2507
2508         return rc;
2509 }
2510
2511 int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn,
2512                                     struct qed_ptt *p_ptt,
2513                                     u32 *num_images)
2514 {
2515         u32 drv_mb_param = 0, rsp;
2516         int rc = 0;
2517
2518         drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
2519                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2520
2521         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2522                          drv_mb_param, &rsp, num_images);
2523         if (rc)
2524                 return rc;
2525
2526         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
2527                 rc = -EINVAL;
2528
2529         return rc;
2530 }
2531
2532 int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn,
2533                                    struct qed_ptt *p_ptt,
2534                                    struct bist_nvm_image_att *p_image_att,
2535                                    u32 image_index)
2536 {
2537         u32 buf_size = 0, param, resp = 0, resp_param = 0;
2538         int rc;
2539
2540         param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
2541                 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT;
2542         param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT;
2543
2544         rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2545                                 DRV_MSG_CODE_BIST_TEST, param,
2546                                 &resp, &resp_param,
2547                                 &buf_size,
2548                                 (u32 *)p_image_att);
2549         if (rc)
2550                 return rc;
2551
2552         if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2553             (p_image_att->return_code != 1))
2554                 rc = -EINVAL;
2555
2556         return rc;
2557 }
2558
2559 int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn)
2560 {
2561         struct qed_nvm_image_info nvm_info;
2562         struct qed_ptt *p_ptt;
2563         int rc;
2564         u32 i;
2565
2566         if (p_hwfn->nvm_info.valid)
2567                 return 0;
2568
2569         p_ptt = qed_ptt_acquire(p_hwfn);
2570         if (!p_ptt) {
2571                 DP_ERR(p_hwfn, "failed to acquire ptt\n");
2572                 return -EBUSY;
2573         }
2574
2575         /* Acquire from MFW the amount of available images */
2576         nvm_info.num_images = 0;
2577         rc = qed_mcp_bist_nvm_get_num_images(p_hwfn,
2578                                              p_ptt, &nvm_info.num_images);
2579         if (rc == -EOPNOTSUPP) {
2580                 DP_INFO(p_hwfn, "DRV_MSG_CODE_BIST_TEST is not supported\n");
2581                 goto out;
2582         } else if (rc || !nvm_info.num_images) {
2583                 DP_ERR(p_hwfn, "Failed getting number of images\n");
2584                 goto err0;
2585         }
2586
2587         nvm_info.image_att = kmalloc_array(nvm_info.num_images,
2588                                            sizeof(struct bist_nvm_image_att),
2589                                            GFP_KERNEL);
2590         if (!nvm_info.image_att) {
2591                 rc = -ENOMEM;
2592                 goto err0;
2593         }
2594
2595         /* Iterate over images and get their attributes */
2596         for (i = 0; i < nvm_info.num_images; i++) {
2597                 rc = qed_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt,
2598                                                     &nvm_info.image_att[i], i);
2599                 if (rc) {
2600                         DP_ERR(p_hwfn,
2601                                "Failed getting image index %d attributes\n", i);
2602                         goto err1;
2603                 }
2604
2605                 DP_VERBOSE(p_hwfn, QED_MSG_SP, "image index %d, size %x\n", i,
2606                            nvm_info.image_att[i].len);
2607         }
2608 out:
2609         /* Update hwfn's nvm_info */
2610         if (nvm_info.num_images) {
2611                 p_hwfn->nvm_info.num_images = nvm_info.num_images;
2612                 kfree(p_hwfn->nvm_info.image_att);
2613                 p_hwfn->nvm_info.image_att = nvm_info.image_att;
2614                 p_hwfn->nvm_info.valid = true;
2615         }
2616
2617         qed_ptt_release(p_hwfn, p_ptt);
2618         return 0;
2619
2620 err1:
2621         kfree(nvm_info.image_att);
2622 err0:
2623         qed_ptt_release(p_hwfn, p_ptt);
2624         return rc;
2625 }
2626
2627 int
2628 qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn,
2629                           enum qed_nvm_images image_id,
2630                           struct qed_nvm_image_att *p_image_att)
2631 {
2632         enum nvm_image_type type;
2633         u32 i;
2634
2635         /* Translate image_id into MFW definitions */
2636         switch (image_id) {
2637         case QED_NVM_IMAGE_ISCSI_CFG:
2638                 type = NVM_TYPE_ISCSI_CFG;
2639                 break;
2640         case QED_NVM_IMAGE_FCOE_CFG:
2641                 type = NVM_TYPE_FCOE_CFG;
2642                 break;
2643         case QED_NVM_IMAGE_NVM_CFG1:
2644                 type = NVM_TYPE_NVM_CFG1;
2645                 break;
2646         case QED_NVM_IMAGE_DEFAULT_CFG:
2647                 type = NVM_TYPE_DEFAULT_CFG;
2648                 break;
2649         case QED_NVM_IMAGE_NVM_META:
2650                 type = NVM_TYPE_META;
2651                 break;
2652         default:
2653                 DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n",
2654                           image_id);
2655                 return -EINVAL;
2656         }
2657
2658         qed_mcp_nvm_info_populate(p_hwfn);
2659         for (i = 0; i < p_hwfn->nvm_info.num_images; i++)
2660                 if (type == p_hwfn->nvm_info.image_att[i].image_type)
2661                         break;
2662         if (i == p_hwfn->nvm_info.num_images) {
2663                 DP_VERBOSE(p_hwfn, QED_MSG_STORAGE,
2664                            "Failed to find nvram image of type %08x\n",
2665                            image_id);
2666                 return -ENOENT;
2667         }
2668
2669         p_image_att->start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr;
2670         p_image_att->length = p_hwfn->nvm_info.image_att[i].len;
2671
2672         return 0;
2673 }
2674
2675 int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn,
2676                           enum qed_nvm_images image_id,
2677                           u8 *p_buffer, u32 buffer_len)
2678 {
2679         struct qed_nvm_image_att image_att;
2680         int rc;
2681
2682         memset(p_buffer, 0, buffer_len);
2683
2684         rc = qed_mcp_get_nvm_image_att(p_hwfn, image_id, &image_att);
2685         if (rc)
2686                 return rc;
2687
2688         /* Validate sizes - both the image's and the supplied buffer's */
2689         if (image_att.length <= 4) {
2690                 DP_VERBOSE(p_hwfn, QED_MSG_STORAGE,
2691                            "Image [%d] is too small - only %d bytes\n",
2692                            image_id, image_att.length);
2693                 return -EINVAL;
2694         }
2695
2696         if (image_att.length > buffer_len) {
2697                 DP_VERBOSE(p_hwfn,
2698                            QED_MSG_STORAGE,
2699                            "Image [%d] is too big - %08x bytes where only %08x are available\n",
2700                            image_id, image_att.length, buffer_len);
2701                 return -ENOMEM;
2702         }
2703
2704         return qed_mcp_nvm_read(p_hwfn->cdev, image_att.start_addr,
2705                                 p_buffer, image_att.length);
2706 }
2707
2708 static enum resource_id_enum qed_mcp_get_mfw_res_id(enum qed_resources res_id)
2709 {
2710         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2711
2712         switch (res_id) {
2713         case QED_SB:
2714                 mfw_res_id = RESOURCE_NUM_SB_E;
2715                 break;
2716         case QED_L2_QUEUE:
2717                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2718                 break;
2719         case QED_VPORT:
2720                 mfw_res_id = RESOURCE_NUM_VPORT_E;
2721                 break;
2722         case QED_RSS_ENG:
2723                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2724                 break;
2725         case QED_PQ:
2726                 mfw_res_id = RESOURCE_NUM_PQ_E;
2727                 break;
2728         case QED_RL:
2729                 mfw_res_id = RESOURCE_NUM_RL_E;
2730                 break;
2731         case QED_MAC:
2732         case QED_VLAN:
2733                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2734                 mfw_res_id = RESOURCE_VFC_FILTER_E;
2735                 break;
2736         case QED_ILT:
2737                 mfw_res_id = RESOURCE_ILT_E;
2738                 break;
2739         case QED_LL2_QUEUE:
2740                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2741                 break;
2742         case QED_RDMA_CNQ_RAM:
2743         case QED_CMDQS_CQS:
2744                 /* CNQ/CMDQS are the same resource */
2745                 mfw_res_id = RESOURCE_CQS_E;
2746                 break;
2747         case QED_RDMA_STATS_QUEUE:
2748                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2749                 break;
2750         case QED_BDQ:
2751                 mfw_res_id = RESOURCE_BDQ_E;
2752                 break;
2753         default:
2754                 break;
2755         }
2756
2757         return mfw_res_id;
2758 }
2759
2760 #define QED_RESC_ALLOC_VERSION_MAJOR    2
2761 #define QED_RESC_ALLOC_VERSION_MINOR    0
2762 #define QED_RESC_ALLOC_VERSION                               \
2763         ((QED_RESC_ALLOC_VERSION_MAJOR <<                    \
2764           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \
2765          (QED_RESC_ALLOC_VERSION_MINOR <<                    \
2766           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT))
2767
2768 struct qed_resc_alloc_in_params {
2769         u32 cmd;
2770         enum qed_resources res_id;
2771         u32 resc_max_val;
2772 };
2773
2774 struct qed_resc_alloc_out_params {
2775         u32 mcp_resp;
2776         u32 mcp_param;
2777         u32 resc_num;
2778         u32 resc_start;
2779         u32 vf_resc_num;
2780         u32 vf_resc_start;
2781         u32 flags;
2782 };
2783
2784 static int
2785 qed_mcp_resc_allocation_msg(struct qed_hwfn *p_hwfn,
2786                             struct qed_ptt *p_ptt,
2787                             struct qed_resc_alloc_in_params *p_in_params,
2788                             struct qed_resc_alloc_out_params *p_out_params)
2789 {
2790         struct qed_mcp_mb_params mb_params;
2791         struct resource_info mfw_resc_info;
2792         int rc;
2793
2794         memset(&mfw_resc_info, 0, sizeof(mfw_resc_info));
2795
2796         mfw_resc_info.res_id = qed_mcp_get_mfw_res_id(p_in_params->res_id);
2797         if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
2798                 DP_ERR(p_hwfn,
2799                        "Failed to match resource %d [%s] with the MFW resources\n",
2800                        p_in_params->res_id,
2801                        qed_hw_get_resc_name(p_in_params->res_id));
2802                 return -EINVAL;
2803         }
2804
2805         switch (p_in_params->cmd) {
2806         case DRV_MSG_SET_RESOURCE_VALUE_MSG:
2807                 mfw_resc_info.size = p_in_params->resc_max_val;
2808                 /* Fallthrough */
2809         case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
2810                 break;
2811         default:
2812                 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
2813                        p_in_params->cmd);
2814                 return -EINVAL;
2815         }
2816
2817         memset(&mb_params, 0, sizeof(mb_params));
2818         mb_params.cmd = p_in_params->cmd;
2819         mb_params.param = QED_RESC_ALLOC_VERSION;
2820         mb_params.p_data_src = &mfw_resc_info;
2821         mb_params.data_src_size = sizeof(mfw_resc_info);
2822         mb_params.p_data_dst = mb_params.p_data_src;
2823         mb_params.data_dst_size = mb_params.data_src_size;
2824
2825         DP_VERBOSE(p_hwfn,
2826                    QED_MSG_SP,
2827                    "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
2828                    p_in_params->cmd,
2829                    p_in_params->res_id,
2830                    qed_hw_get_resc_name(p_in_params->res_id),
2831                    QED_MFW_GET_FIELD(mb_params.param,
2832                                      DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
2833                    QED_MFW_GET_FIELD(mb_params.param,
2834                                      DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
2835                    p_in_params->resc_max_val);
2836
2837         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2838         if (rc)
2839                 return rc;
2840
2841         p_out_params->mcp_resp = mb_params.mcp_resp;
2842         p_out_params->mcp_param = mb_params.mcp_param;
2843         p_out_params->resc_num = mfw_resc_info.size;
2844         p_out_params->resc_start = mfw_resc_info.offset;
2845         p_out_params->vf_resc_num = mfw_resc_info.vf_size;
2846         p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
2847         p_out_params->flags = mfw_resc_info.flags;
2848
2849         DP_VERBOSE(p_hwfn,
2850                    QED_MSG_SP,
2851                    "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
2852                    QED_MFW_GET_FIELD(p_out_params->mcp_param,
2853                                      FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
2854                    QED_MFW_GET_FIELD(p_out_params->mcp_param,
2855                                      FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
2856                    p_out_params->resc_num,
2857                    p_out_params->resc_start,
2858                    p_out_params->vf_resc_num,
2859                    p_out_params->vf_resc_start, p_out_params->flags);
2860
2861         return 0;
2862 }
2863
2864 int
2865 qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn,
2866                          struct qed_ptt *p_ptt,
2867                          enum qed_resources res_id,
2868                          u32 resc_max_val, u32 *p_mcp_resp)
2869 {
2870         struct qed_resc_alloc_out_params out_params;
2871         struct qed_resc_alloc_in_params in_params;
2872         int rc;
2873
2874         memset(&in_params, 0, sizeof(in_params));
2875         in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
2876         in_params.res_id = res_id;
2877         in_params.resc_max_val = resc_max_val;
2878         memset(&out_params, 0, sizeof(out_params));
2879         rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
2880                                          &out_params);
2881         if (rc)
2882                 return rc;
2883
2884         *p_mcp_resp = out_params.mcp_resp;
2885
2886         return 0;
2887 }
2888
2889 int
2890 qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn,
2891                       struct qed_ptt *p_ptt,
2892                       enum qed_resources res_id,
2893                       u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start)
2894 {
2895         struct qed_resc_alloc_out_params out_params;
2896         struct qed_resc_alloc_in_params in_params;
2897         int rc;
2898
2899         memset(&in_params, 0, sizeof(in_params));
2900         in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
2901         in_params.res_id = res_id;
2902         memset(&out_params, 0, sizeof(out_params));
2903         rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
2904                                          &out_params);
2905         if (rc)
2906                 return rc;
2907
2908         *p_mcp_resp = out_params.mcp_resp;
2909
2910         if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2911                 *p_resc_num = out_params.resc_num;
2912                 *p_resc_start = out_params.resc_start;
2913         }
2914
2915         return 0;
2916 }
2917
2918 int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2919 {
2920         u32 mcp_resp, mcp_param;
2921
2922         return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
2923                            &mcp_resp, &mcp_param);
2924 }
2925
2926 static int qed_mcp_resource_cmd(struct qed_hwfn *p_hwfn,
2927                                 struct qed_ptt *p_ptt,
2928                                 u32 param, u32 *p_mcp_resp, u32 *p_mcp_param)
2929 {
2930         int rc;
2931
2932         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
2933                          p_mcp_resp, p_mcp_param);
2934         if (rc)
2935                 return rc;
2936
2937         if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
2938                 DP_INFO(p_hwfn,
2939                         "The resource command is unsupported by the MFW\n");
2940                 return -EINVAL;
2941         }
2942
2943         if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
2944                 u8 opcode = QED_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
2945
2946                 DP_NOTICE(p_hwfn,
2947                           "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
2948                           param, opcode);
2949                 return -EINVAL;
2950         }
2951
2952         return rc;
2953 }
2954
2955 int
2956 __qed_mcp_resc_lock(struct qed_hwfn *p_hwfn,
2957                     struct qed_ptt *p_ptt,
2958                     struct qed_resc_lock_params *p_params)
2959 {
2960         u32 param = 0, mcp_resp, mcp_param;
2961         u8 opcode;
2962         int rc;
2963
2964         switch (p_params->timeout) {
2965         case QED_MCP_RESC_LOCK_TO_DEFAULT:
2966                 opcode = RESOURCE_OPCODE_REQ;
2967                 p_params->timeout = 0;
2968                 break;
2969         case QED_MCP_RESC_LOCK_TO_NONE:
2970                 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
2971                 p_params->timeout = 0;
2972                 break;
2973         default:
2974                 opcode = RESOURCE_OPCODE_REQ_W_AGING;
2975                 break;
2976         }
2977
2978         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
2979         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
2980         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
2981
2982         DP_VERBOSE(p_hwfn,
2983                    QED_MSG_SP,
2984                    "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
2985                    param, p_params->timeout, opcode, p_params->resource);
2986
2987         /* Attempt to acquire the resource */
2988         rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param);
2989         if (rc)
2990                 return rc;
2991
2992         /* Analyze the response */
2993         p_params->owner = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER);
2994         opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
2995
2996         DP_VERBOSE(p_hwfn,
2997                    QED_MSG_SP,
2998                    "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
2999                    mcp_param, opcode, p_params->owner);
3000
3001         switch (opcode) {
3002         case RESOURCE_OPCODE_GNT:
3003                 p_params->b_granted = true;
3004                 break;
3005         case RESOURCE_OPCODE_BUSY:
3006                 p_params->b_granted = false;
3007                 break;
3008         default:
3009                 DP_NOTICE(p_hwfn,
3010                           "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
3011                           mcp_param, opcode);
3012                 return -EINVAL;
3013         }
3014
3015         return 0;
3016 }
3017
3018 int
3019 qed_mcp_resc_lock(struct qed_hwfn *p_hwfn,
3020                   struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params)
3021 {
3022         u32 retry_cnt = 0;
3023         int rc;
3024
3025         do {
3026                 /* No need for an interval before the first iteration */
3027                 if (retry_cnt) {
3028                         if (p_params->sleep_b4_retry) {
3029                                 u16 retry_interval_in_ms =
3030                                     DIV_ROUND_UP(p_params->retry_interval,
3031                                                  1000);
3032
3033                                 msleep(retry_interval_in_ms);
3034                         } else {
3035                                 udelay(p_params->retry_interval);
3036                         }
3037                 }
3038
3039                 rc = __qed_mcp_resc_lock(p_hwfn, p_ptt, p_params);
3040                 if (rc)
3041                         return rc;
3042
3043                 if (p_params->b_granted)
3044                         break;
3045         } while (retry_cnt++ < p_params->retry_num);
3046
3047         return 0;
3048 }
3049
3050 int
3051 qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn,
3052                     struct qed_ptt *p_ptt,
3053                     struct qed_resc_unlock_params *p_params)
3054 {
3055         u32 param = 0, mcp_resp, mcp_param;
3056         u8 opcode;
3057         int rc;
3058
3059         opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
3060                                    : RESOURCE_OPCODE_RELEASE;
3061         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3062         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3063
3064         DP_VERBOSE(p_hwfn, QED_MSG_SP,
3065                    "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
3066                    param, opcode, p_params->resource);
3067
3068         /* Attempt to release the resource */
3069         rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param);
3070         if (rc)
3071                 return rc;
3072
3073         /* Analyze the response */
3074         opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3075
3076         DP_VERBOSE(p_hwfn, QED_MSG_SP,
3077                    "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
3078                    mcp_param, opcode);
3079
3080         switch (opcode) {
3081         case RESOURCE_OPCODE_RELEASED_PREVIOUS:
3082                 DP_INFO(p_hwfn,
3083                         "Resource unlock request for an already released resource [%d]\n",
3084                         p_params->resource);
3085                 /* Fallthrough */
3086         case RESOURCE_OPCODE_RELEASED:
3087                 p_params->b_released = true;
3088                 break;
3089         case RESOURCE_OPCODE_WRONG_OWNER:
3090                 p_params->b_released = false;
3091                 break;
3092         default:
3093                 DP_NOTICE(p_hwfn,
3094                           "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
3095                           mcp_param, opcode);
3096                 return -EINVAL;
3097         }
3098
3099         return 0;
3100 }
3101
3102 void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock,
3103                                     struct qed_resc_unlock_params *p_unlock,
3104                                     enum qed_resc_lock
3105                                     resource, bool b_is_permanent)
3106 {
3107         if (p_lock) {
3108                 memset(p_lock, 0, sizeof(*p_lock));
3109
3110                 /* Permanent resources don't require aging, and there's no
3111                  * point in trying to acquire them more than once since it's
3112                  * unexpected another entity would release them.
3113                  */
3114                 if (b_is_permanent) {
3115                         p_lock->timeout = QED_MCP_RESC_LOCK_TO_NONE;
3116                 } else {
3117                         p_lock->retry_num = QED_MCP_RESC_LOCK_RETRY_CNT_DFLT;
3118                         p_lock->retry_interval =
3119                             QED_MCP_RESC_LOCK_RETRY_VAL_DFLT;
3120                         p_lock->sleep_b4_retry = true;
3121                 }
3122
3123                 p_lock->resource = resource;
3124         }
3125
3126         if (p_unlock) {
3127                 memset(p_unlock, 0, sizeof(*p_unlock));
3128                 p_unlock->resource = resource;
3129         }
3130 }
3131
3132 int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3133 {
3134         u32 mcp_resp;
3135         int rc;
3136
3137         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
3138                          0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
3139         if (!rc)
3140                 DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_PROBE),
3141                            "MFW supported features: %08x\n",
3142                            p_hwfn->mcp_info->capabilities);
3143
3144         return rc;
3145 }
3146
3147 int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3148 {
3149         u32 mcp_resp, mcp_param, features;
3150
3151         features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE;
3152
3153         return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
3154                            features, &mcp_resp, &mcp_param);
3155 }