drivers/net/ethernet/qlogic/qed/qed_mcp.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/types.h>
  34 #include <asm/byteorder.h>
  35 #include <linux/delay.h>
  36 #include <linux/errno.h>
  37 #include <linux/kernel.h>
  38 #include <linux/slab.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/string.h>
  41 #include <linux/etherdevice.h>
  42 #include "qed.h"
  43 #include "qed_cxt.h"
  44 #include "qed_dcbx.h"
  45 #include "qed_hsi.h"
  46 #include "qed_hw.h"
  47 #include "qed_mcp.h"
  48 #include "qed_reg_addr.h"
  49 #include "qed_sriov.h"
  50
  51 #define CHIP_MCP_RESP_ITER_US 10
  52
  53 #define QED_DRV_MB_MAX_RETRIES  (500 * 1000)    /* Account for 5 sec */
  54 #define QED_MCP_RESET_RETRIES   (50 * 1000)     /* Account for 500 msec */
  55
  56 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val)           \
  57         qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
  58                _val)
  59
  60 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
  61         qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
  62
  63 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val)  \
  64         DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
  65                      offsetof(struct public_drv_mb, _field), _val)
  66
  67 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field)         \
  68         DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
  69                      offsetof(struct public_drv_mb, _field))
  70
  71 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
  72                   DRV_ID_PDA_COMP_VER_SHIFT)
  73
  74 #define MCP_BYTES_PER_MBIT_SHIFT 17
  75
  76 bool qed_mcp_is_init(struct qed_hwfn *p_hwfn)
  77 {
  78         if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
  79                 return false;
  80         return true;
  81 }
  82
  83 void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
  84 {
  85         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
  86                                         PUBLIC_PORT);
  87         u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr);
  88
  89         p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
  90                                                    MFW_PORT(p_hwfn));
  91         DP_VERBOSE(p_hwfn, QED_MSG_SP,
  92                    "port_addr = 0x%x, port_id 0x%02x\n",
  93                    p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
  94 }
  95
  96 void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
  97 {
  98         u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
  99         u32 tmp, i;
 100
 101         if (!p_hwfn->mcp_info->public_base)
 102                 return;
 103
 104         for (i = 0; i < length; i++) {
 105                 tmp = qed_rd(p_hwfn, p_ptt,
 106                              p_hwfn->mcp_info->mfw_mb_addr +
 107                              (i << 2) + sizeof(u32));
 108
 109                 /* The MB data is actually BE; Need to force it to cpu */
 110                 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
 111                         be32_to_cpu((__force __be32)tmp);
 112         }
 113 }
 114
 115 struct qed_mcp_cmd_elem {
 116         struct list_head list;
 117         struct qed_mcp_mb_params *p_mb_params;
 118         u16 expected_seq_num;
 119         bool b_is_completed;
 120 };
 121
 122 /* Must be called while cmd_lock is acquired */
 123 static struct qed_mcp_cmd_elem *
 124 qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn,
 125                      struct qed_mcp_mb_params *p_mb_params,
 126                      u16 expected_seq_num)
 127 {
 128         struct qed_mcp_cmd_elem *p_cmd_elem = NULL;
 129
 130         p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC);
 131         if (!p_cmd_elem)
 132                 goto out;
 133
 134         p_cmd_elem->p_mb_params = p_mb_params;
 135         p_cmd_elem->expected_seq_num = expected_seq_num;
 136         list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
 137 out:
 138         return p_cmd_elem;
 139 }
 140
 141 /* Must be called while cmd_lock is acquired */
 142 static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn,
 143                                  struct qed_mcp_cmd_elem *p_cmd_elem)
 144 {
 145         list_del(&p_cmd_elem->list);
 146         kfree(p_cmd_elem);
 147 }
 148
 149 /* Must be called while cmd_lock is acquired */
 150 static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn,
 151                                                      u16 seq_num)
 152 {
 153         struct qed_mcp_cmd_elem *p_cmd_elem = NULL;
 154
 155         list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) {
 156                 if (p_cmd_elem->expected_seq_num == seq_num)
 157                         return p_cmd_elem;
 158         }
 159
 160         return NULL;
 161 }
 162
 163 int qed_mcp_free(struct qed_hwfn *p_hwfn)
 164 {
 165         if (p_hwfn->mcp_info) {
 166                 struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp;
 167
 168                 kfree(p_hwfn->mcp_info->mfw_mb_cur);
 169                 kfree(p_hwfn->mcp_info->mfw_mb_shadow);
 170
 171                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 172                 list_for_each_entry_safe(p_cmd_elem,
 173                                          p_tmp,
 174                                          &p_hwfn->mcp_info->cmd_list, list) {
 175                         qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 176                 }
 177                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 178         }
 179
 180         kfree(p_hwfn->mcp_info);
 181         p_hwfn->mcp_info = NULL;
 182
 183         return 0;
 184 }
 185
 186 static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 187 {
 188         struct qed_mcp_info *p_info = p_hwfn->mcp_info;
 189         u32 drv_mb_offsize, mfw_mb_offsize;
 190         u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
 191
 192         p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
 193         if (!p_info->public_base)
 194                 return 0;
 195
 196         p_info->public_base |= GRCBASE_MCP;
 197
 198         /* Calculate the driver and MFW mailbox address */
 199         drv_mb_offsize = qed_rd(p_hwfn, p_ptt,
 200                                 SECTION_OFFSIZE_ADDR(p_info->public_base,
 201                                                      PUBLIC_DRV_MB));
 202         p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
 203         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 204                    "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n",
 205                    drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
 206
 207         /* Set the MFW MB address */
 208         mfw_mb_offsize = qed_rd(p_hwfn, p_ptt,
 209                                 SECTION_OFFSIZE_ADDR(p_info->public_base,
 210                                                      PUBLIC_MFW_MB));
 211         p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
 212         p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, p_info->mfw_mb_addr);
 213
 214         /* Get the current driver mailbox sequence before sending
 215          * the first command
 216          */
 217         p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 218                              DRV_MSG_SEQ_NUMBER_MASK;
 219
 220         /* Get current FW pulse sequence */
 221         p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
 222                                 DRV_PULSE_SEQ_MASK;
 223
 224         p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 225
 226         return 0;
 227 }
 228
 229 int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 230 {
 231         struct qed_mcp_info *p_info;
 232         u32 size;
 233
 234         /* Allocate mcp_info structure */
 235         p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL);
 236         if (!p_hwfn->mcp_info)
 237                 goto err;
 238         p_info = p_hwfn->mcp_info;
 239
 240         /* Initialize the MFW spinlock */
 241         spin_lock_init(&p_info->cmd_lock);
 242         spin_lock_init(&p_info->link_lock);
 243
 244         INIT_LIST_HEAD(&p_info->cmd_list);
 245
 246         if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) {
 247                 DP_NOTICE(p_hwfn, "MCP is not initialized\n");
 248                 /* Do not free mcp_info here, since public_base indicate that
 249                  * the MCP is not initialized
 250                  */
 251                 return 0;
 252         }
 253
 254         size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
 255         p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL);
 256         p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL);
 257         if (!p_info->mfw_mb_cur || !p_info->mfw_mb_shadow)
 258                 goto err;
 259
 260         return 0;
 261
 262 err:
 263         qed_mcp_free(p_hwfn);
 264         return -ENOMEM;
 265 }
 266
 267 static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn,
 268                                    struct qed_ptt *p_ptt)
 269 {
 270         u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 271
 272         /* Use MCP history register to check if MCP reset occurred between init
 273          * time and now.
 274          */
 275         if (p_hwfn->mcp_info->mcp_hist != generic_por_0) {
 276                 DP_VERBOSE(p_hwfn,
 277                            QED_MSG_SP,
 278                            "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n",
 279                            p_hwfn->mcp_info->mcp_hist, generic_por_0);
 280
 281                 qed_load_mcp_offsets(p_hwfn, p_ptt);
 282                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
 283         }
 284 }
 285
 286 int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 287 {
 288         u32 org_mcp_reset_seq, seq, delay = CHIP_MCP_RESP_ITER_US, cnt = 0;
 289         int rc = 0;
 290
 291         /* Ensure that only a single thread is accessing the mailbox */
 292         spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 293
 294         org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 295
 296         /* Set drv command along with the updated sequence */
 297         qed_mcp_reread_offsets(p_hwfn, p_ptt);
 298         seq = ++p_hwfn->mcp_info->drv_mb_seq;
 299         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
 300
 301         do {
 302                 /* Wait for MFW response */
 303                 udelay(delay);
 304                 /* Give the FW up to 500 second (50*1000*10usec) */
 305         } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt,
 306                                               MISCS_REG_GENERIC_POR_0)) &&
 307                  (cnt++ < QED_MCP_RESET_RETRIES));
 308
 309         if (org_mcp_reset_seq !=
 310             qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 311                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
 312                            "MCP was reset after %d usec\n", cnt * delay);
 313         } else {
 314                 DP_ERR(p_hwfn, "Failed to reset MCP\n");
 315                 rc = -EAGAIN;
 316         }
 317
 318         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 319
 320         return rc;
 321 }
 322
 323 /* Must be called while cmd_lock is acquired */
 324 static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn)
 325 {
 326         struct qed_mcp_cmd_elem *p_cmd_elem;
 327
 328         /* There is at most one pending command at a certain time, and if it
 329          * exists - it is placed at the HEAD of the list.
 330          */
 331         if (!list_empty(&p_hwfn->mcp_info->cmd_list)) {
 332                 p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list,
 333                                               struct qed_mcp_cmd_elem, list);
 334                 return !p_cmd_elem->b_is_completed;
 335         }
 336
 337         return false;
 338 }
 339
 340 /* Must be called while cmd_lock is acquired */
 341 static int
 342 qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 343 {
 344         struct qed_mcp_mb_params *p_mb_params;
 345         struct qed_mcp_cmd_elem *p_cmd_elem;
 346         u32 mcp_resp;
 347         u16 seq_num;
 348
 349         mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
 350         seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK);
 351
 352         /* Return if no new non-handled response has been received */
 353         if (seq_num != p_hwfn->mcp_info->drv_mb_seq)
 354                 return -EAGAIN;
 355
 356         p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num);
 357         if (!p_cmd_elem) {
 358                 DP_ERR(p_hwfn,
 359                        "Failed to find a pending mailbox cmd that expects sequence number %d\n",
 360                        seq_num);
 361                 return -EINVAL;
 362         }
 363
 364         p_mb_params = p_cmd_elem->p_mb_params;
 365
 366         /* Get the MFW response along with the sequence number */
 367         p_mb_params->mcp_resp = mcp_resp;
 368
 369         /* Get the MFW param */
 370         p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
 371
 372         /* Get the union data */
 373         if (p_mb_params->p_data_dst != NULL && p_mb_params->data_dst_size) {
 374                 u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 375                                       offsetof(struct public_drv_mb,
 376                                                union_data);
 377                 qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
 378                                 union_data_addr, p_mb_params->data_dst_size);
 379         }
 380
 381         p_cmd_elem->b_is_completed = true;
 382
 383         return 0;
 384 }
 385
 386 /* Must be called while cmd_lock is acquired */
 387 static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
 388                                     struct qed_ptt *p_ptt,
 389                                     struct qed_mcp_mb_params *p_mb_params,
 390                                     u16 seq_num)
 391 {
 392         union drv_union_data union_data;
 393         u32 union_data_addr;
 394
 395         /* Set the union data */
 396         union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 397                           offsetof(struct public_drv_mb, union_data);
 398         memset(&union_data, 0, sizeof(union_data));
 399         if (p_mb_params->p_data_src != NULL && p_mb_params->data_src_size)
 400                 memcpy(&union_data, p_mb_params->p_data_src,
 401                        p_mb_params->data_src_size);
 402         qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
 403                       sizeof(union_data));
 404
 405         /* Set the drv param */
 406         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param);
 407
 408         /* Set the drv command along with the sequence number */
 409         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num));
 410
 411         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 412                    "MFW mailbox: command 0x%08x param 0x%08x\n",
 413                    (p_mb_params->cmd | seq_num), p_mb_params->param);
 414 }
 415
 416 static int
 417 _qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
 418                        struct qed_ptt *p_ptt,
 419                        struct qed_mcp_mb_params *p_mb_params,
 420                        u32 max_retries, u32 delay)
 421 {
 422         struct qed_mcp_cmd_elem *p_cmd_elem;
 423         u32 cnt = 0;
 424         u16 seq_num;
 425         int rc = 0;
 426
 427         /* Wait until the mailbox is non-occupied */
 428         do {
 429                 /* Exit the loop if there is no pending command, or if the
 430                  * pending command is completed during this iteration.
 431                  * The spinlock stays locked until the command is sent.
 432                  */
 433
 434                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 435
 436                 if (!qed_mcp_has_pending_cmd(p_hwfn))
 437                         break;
 438
 439                 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt);
 440                 if (!rc)
 441                         break;
 442                 else if (rc != -EAGAIN)
 443                         goto err;
 444
 445                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 446                 udelay(delay);
 447         } while (++cnt < max_retries);
 448
 449         if (cnt >= max_retries) {
 450                 DP_NOTICE(p_hwfn,
 451                           "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n",
 452                           p_mb_params->cmd, p_mb_params->param);
 453                 return -EAGAIN;
 454         }
 455
 456         /* Send the mailbox command */
 457         qed_mcp_reread_offsets(p_hwfn, p_ptt);
 458         seq_num = ++p_hwfn->mcp_info->drv_mb_seq;
 459         p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num);
 460         if (!p_cmd_elem) {
 461                 rc = -ENOMEM;
 462                 goto err;
 463         }
 464
 465         __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num);
 466         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 467
 468         /* Wait for the MFW response */
 469         do {
 470                 /* Exit the loop if the command is already completed, or if the
 471                  * command is completed during this iteration.
 472                  * The spinlock stays locked until the list element is removed.
 473                  */
 474
 475                 udelay(delay);
 476                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 477
 478                 if (p_cmd_elem->b_is_completed)
 479                         break;
 480
 481                 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt);
 482                 if (!rc)
 483                         break;
 484                 else if (rc != -EAGAIN)
 485                         goto err;
 486
 487                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 488         } while (++cnt < max_retries);
 489
 490         if (cnt >= max_retries) {
 491                 DP_NOTICE(p_hwfn,
 492                           "The MFW failed to respond to command 0x%08x [param 0x%08x].\n",
 493                           p_mb_params->cmd, p_mb_params->param);
 494
 495                 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
 496                 qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 497                 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 498
 499                 return -EAGAIN;
 500         }
 501
 502         qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 503         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 504
 505         DP_VERBOSE(p_hwfn,
 506                    QED_MSG_SP,
 507                    "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n",
 508                    p_mb_params->mcp_resp,
 509                    p_mb_params->mcp_param,
 510                    (cnt * delay) / 1000, (cnt * delay) % 1000);
 511
 512         /* Clear the sequence number from the MFW response */
 513         p_mb_params->mcp_resp &= FW_MSG_CODE_MASK;
 514
 515         return 0;
 516
 517 err:
 518         spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
 519         return rc;
 520 }
 521
 522 static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
 523                                  struct qed_ptt *p_ptt,
 524                                  struct qed_mcp_mb_params *p_mb_params)
 525 {
 526         size_t union_data_size = sizeof(union drv_union_data);
 527         u32 max_retries = QED_DRV_MB_MAX_RETRIES;
 528         u32 delay = CHIP_MCP_RESP_ITER_US;
 529
 530         /* MCP not initialized */
 531         if (!qed_mcp_is_init(p_hwfn)) {
 532                 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
 533                 return -EBUSY;
 534         }
 535
 536         if (p_mb_params->data_src_size > union_data_size ||
 537             p_mb_params->data_dst_size > union_data_size) {
 538                 DP_ERR(p_hwfn,
 539                        "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
 540                        p_mb_params->data_src_size,
 541                        p_mb_params->data_dst_size, union_data_size);
 542                 return -EINVAL;
 543         }
 544
 545         return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries,
 546                                       delay);
 547 }
 548
 549 int qed_mcp_cmd(struct qed_hwfn *p_hwfn,
 550                 struct qed_ptt *p_ptt,
 551                 u32 cmd,
 552                 u32 param,
 553                 u32 *o_mcp_resp,
 554                 u32 *o_mcp_param)
 555 {
 556         struct qed_mcp_mb_params mb_params;
 557         int rc;
 558
 559         memset(&mb_params, 0, sizeof(mb_params));
 560         mb_params.cmd = cmd;
 561         mb_params.param = param;
 562
 563         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 564         if (rc)
 565                 return rc;
 566
 567         *o_mcp_resp = mb_params.mcp_resp;
 568         *o_mcp_param = mb_params.mcp_param;
 569
 570         return 0;
 571 }
 572
 573 int qed_mcp_nvm_wr_cmd(struct qed_hwfn *p_hwfn,
 574                        struct qed_ptt *p_ptt,
 575                        u32 cmd,
 576                        u32 param,
 577                        u32 *o_mcp_resp,
 578                        u32 *o_mcp_param, u32 i_txn_size, u32 *i_buf)
 579 {
 580         struct qed_mcp_mb_params mb_params;
 581         int rc;
 582
 583         memset(&mb_params, 0, sizeof(mb_params));
 584         mb_params.cmd = cmd;
 585         mb_params.param = param;
 586         mb_params.p_data_src = i_buf;
 587         mb_params.data_src_size = (u8)i_txn_size;
 588         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 589         if (rc)
 590                 return rc;
 591
 592         *o_mcp_resp = mb_params.mcp_resp;
 593         *o_mcp_param = mb_params.mcp_param;
 594
 595         return 0;
 596 }
 597
 598 int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn,
 599                        struct qed_ptt *p_ptt,
 600                        u32 cmd,
 601                        u32 param,
 602                        u32 *o_mcp_resp,
 603                        u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf)
 604 {
 605         struct qed_mcp_mb_params mb_params;
 606         u8 raw_data[MCP_DRV_NVM_BUF_LEN];
 607         int rc;
 608
 609         memset(&mb_params, 0, sizeof(mb_params));
 610         mb_params.cmd = cmd;
 611         mb_params.param = param;
 612         mb_params.p_data_dst = raw_data;
 613
 614         /* Use the maximal value since the actual one is part of the response */
 615         mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
 616
 617         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 618         if (rc)
 619                 return rc;
 620
 621         *o_mcp_resp = mb_params.mcp_resp;
 622         *o_mcp_param = mb_params.mcp_param;
 623
 624         *o_txn_size = *o_mcp_param;
 625         memcpy(o_buf, raw_data, *o_txn_size);
 626
 627         return 0;
 628 }
 629
 630 static bool
 631 qed_mcp_can_force_load(u8 drv_role,
 632                        u8 exist_drv_role,
 633                        enum qed_override_force_load override_force_load)
 634 {
 635         bool can_force_load = false;
 636
 637         switch (override_force_load) {
 638         case QED_OVERRIDE_FORCE_LOAD_ALWAYS:
 639                 can_force_load = true;
 640                 break;
 641         case QED_OVERRIDE_FORCE_LOAD_NEVER:
 642                 can_force_load = false;
 643                 break;
 644         default:
 645                 can_force_load = (drv_role == DRV_ROLE_OS &&
 646                                   exist_drv_role == DRV_ROLE_PREBOOT) ||
 647                                  (drv_role == DRV_ROLE_KDUMP &&
 648                                   exist_drv_role == DRV_ROLE_OS);
 649                 break;
 650         }
 651
 652         return can_force_load;
 653 }
 654
 655 static int qed_mcp_cancel_load_req(struct qed_hwfn *p_hwfn,
 656                                    struct qed_ptt *p_ptt)
 657 {
 658         u32 resp = 0, param = 0;
 659         int rc;
 660
 661         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
 662                          &resp, &param);
 663         if (rc)
 664                 DP_NOTICE(p_hwfn,
 665                           "Failed to send cancel load request, rc = %d\n", rc);
 666
 667         return rc;
 668 }
 669
 670 #define CONFIG_QEDE_BITMAP_IDX          BIT(0)
 671 #define CONFIG_QED_SRIOV_BITMAP_IDX     BIT(1)
 672 #define CONFIG_QEDR_BITMAP_IDX          BIT(2)
 673 #define CONFIG_QEDF_BITMAP_IDX          BIT(4)
 674 #define CONFIG_QEDI_BITMAP_IDX          BIT(5)
 675 #define CONFIG_QED_LL2_BITMAP_IDX       BIT(6)
 676
 677 static u32 qed_get_config_bitmap(void)
 678 {
 679         u32 config_bitmap = 0x0;
 680
 681         if (IS_ENABLED(CONFIG_QEDE))
 682                 config_bitmap |= CONFIG_QEDE_BITMAP_IDX;
 683
 684         if (IS_ENABLED(CONFIG_QED_SRIOV))
 685                 config_bitmap |= CONFIG_QED_SRIOV_BITMAP_IDX;
 686
 687         if (IS_ENABLED(CONFIG_QED_RDMA))
 688                 config_bitmap |= CONFIG_QEDR_BITMAP_IDX;
 689
 690         if (IS_ENABLED(CONFIG_QED_FCOE))
 691                 config_bitmap |= CONFIG_QEDF_BITMAP_IDX;
 692
 693         if (IS_ENABLED(CONFIG_QED_ISCSI))
 694                 config_bitmap |= CONFIG_QEDI_BITMAP_IDX;
 695
 696         if (IS_ENABLED(CONFIG_QED_LL2))
 697                 config_bitmap |= CONFIG_QED_LL2_BITMAP_IDX;
 698
 699         return config_bitmap;
 700 }
 701
 702 struct qed_load_req_in_params {
 703         u8 hsi_ver;
 704 #define QED_LOAD_REQ_HSI_VER_DEFAULT    0
 705 #define QED_LOAD_REQ_HSI_VER_1          1
 706         u32 drv_ver_0;
 707         u32 drv_ver_1;
 708         u32 fw_ver;
 709         u8 drv_role;
 710         u8 timeout_val;
 711         u8 force_cmd;
 712         bool avoid_eng_reset;
 713 };
 714
 715 struct qed_load_req_out_params {
 716         u32 load_code;
 717         u32 exist_drv_ver_0;
 718         u32 exist_drv_ver_1;
 719         u32 exist_fw_ver;
 720         u8 exist_drv_role;
 721         u8 mfw_hsi_ver;
 722         bool drv_exists;
 723 };
 724
 725 static int
 726 __qed_mcp_load_req(struct qed_hwfn *p_hwfn,
 727                    struct qed_ptt *p_ptt,
 728                    struct qed_load_req_in_params *p_in_params,
 729                    struct qed_load_req_out_params *p_out_params)
 730 {
 731         struct qed_mcp_mb_params mb_params;
 732         struct load_req_stc load_req;
 733         struct load_rsp_stc load_rsp;
 734         u32 hsi_ver;
 735         int rc;
 736
 737         memset(&load_req, 0, sizeof(load_req));
 738         load_req.drv_ver_0 = p_in_params->drv_ver_0;
 739         load_req.drv_ver_1 = p_in_params->drv_ver_1;
 740         load_req.fw_ver = p_in_params->fw_ver;
 741         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role);
 742         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
 743                           p_in_params->timeout_val);
 744         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE,
 745                           p_in_params->force_cmd);
 746         QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
 747                           p_in_params->avoid_eng_reset);
 748
 749         hsi_ver = (p_in_params->hsi_ver == QED_LOAD_REQ_HSI_VER_DEFAULT) ?
 750                   DRV_ID_MCP_HSI_VER_CURRENT :
 751                   (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT);
 752
 753         memset(&mb_params, 0, sizeof(mb_params));
 754         mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
 755         mb_params.param = PDA_COMP | hsi_ver | p_hwfn->cdev->drv_type;
 756         mb_params.p_data_src = &load_req;
 757         mb_params.data_src_size = sizeof(load_req);
 758         mb_params.p_data_dst = &load_rsp;
 759         mb_params.data_dst_size = sizeof(load_rsp);
 760
 761         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 762                    "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
 763                    mb_params.param,
 764                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
 765                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
 766                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
 767                    QED_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
 768
 769         if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1) {
 770                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
 771                            "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
 772                            load_req.drv_ver_0,
 773                            load_req.drv_ver_1,
 774                            load_req.fw_ver,
 775                            load_req.misc0,
 776                            QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE),
 777                            QED_MFW_GET_FIELD(load_req.misc0,
 778                                              LOAD_REQ_LOCK_TO),
 779                            QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE),
 780                            QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0));
 781         }
 782
 783         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 784         if (rc) {
 785                 DP_NOTICE(p_hwfn, "Failed to send load request, rc = %d\n", rc);
 786                 return rc;
 787         }
 788
 789         DP_VERBOSE(p_hwfn, QED_MSG_SP,
 790                    "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
 791         p_out_params->load_code = mb_params.mcp_resp;
 792
 793         if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1 &&
 794             p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 795                 DP_VERBOSE(p_hwfn,
 796                            QED_MSG_SP,
 797                            "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
 798                            load_rsp.drv_ver_0,
 799                            load_rsp.drv_ver_1,
 800                            load_rsp.fw_ver,
 801                            load_rsp.misc0,
 802                            QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
 803                            QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
 804                            QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0));
 805
 806                 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
 807                 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
 808                 p_out_params->exist_fw_ver = load_rsp.fw_ver;
 809                 p_out_params->exist_drv_role =
 810                     QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
 811                 p_out_params->mfw_hsi_ver =
 812                     QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
 813                 p_out_params->drv_exists =
 814                     QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
 815                     LOAD_RSP_FLAGS0_DRV_EXISTS;
 816         }
 817
 818         return 0;
 819 }
 820
 821 static int eocre_get_mfw_drv_role(struct qed_hwfn *p_hwfn,
 822                                   enum qed_drv_role drv_role,
 823                                   u8 *p_mfw_drv_role)
 824 {
 825         switch (drv_role) {
 826         case QED_DRV_ROLE_OS:
 827                 *p_mfw_drv_role = DRV_ROLE_OS;
 828                 break;
 829         case QED_DRV_ROLE_KDUMP:
 830                 *p_mfw_drv_role = DRV_ROLE_KDUMP;
 831                 break;
 832         default:
 833                 DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role);
 834                 return -EINVAL;
 835         }
 836
 837         return 0;
 838 }
 839
 840 enum qed_load_req_force {
 841         QED_LOAD_REQ_FORCE_NONE,
 842         QED_LOAD_REQ_FORCE_PF,
 843         QED_LOAD_REQ_FORCE_ALL,
 844 };
 845
 846 static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn,
 847
 848                                   enum qed_load_req_force force_cmd,
 849                                   u8 *p_mfw_force_cmd)
 850 {
 851         switch (force_cmd) {
 852         case QED_LOAD_REQ_FORCE_NONE:
 853                 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
 854                 break;
 855         case QED_LOAD_REQ_FORCE_PF:
 856                 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
 857                 break;
 858         case QED_LOAD_REQ_FORCE_ALL:
 859                 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
 860                 break;
 861         }
 862 }
 863
 864 int qed_mcp_load_req(struct qed_hwfn *p_hwfn,
 865                      struct qed_ptt *p_ptt,
 866                      struct qed_load_req_params *p_params)
 867 {
 868         struct qed_load_req_out_params out_params;
 869         struct qed_load_req_in_params in_params;
 870         u8 mfw_drv_role, mfw_force_cmd;
 871         int rc;
 872
 873         memset(&in_params, 0, sizeof(in_params));
 874         in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_DEFAULT;
 875         in_params.drv_ver_0 = QED_VERSION;
 876         in_params.drv_ver_1 = qed_get_config_bitmap();
 877         in_params.fw_ver = STORM_FW_VERSION;
 878         rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role);
 879         if (rc)
 880                 return rc;
 881
 882         in_params.drv_role = mfw_drv_role;
 883         in_params.timeout_val = p_params->timeout_val;
 884         qed_get_mfw_force_cmd(p_hwfn,
 885                               QED_LOAD_REQ_FORCE_NONE, &mfw_force_cmd);
 886
 887         in_params.force_cmd = mfw_force_cmd;
 888         in_params.avoid_eng_reset = p_params->avoid_eng_reset;
 889
 890         memset(&out_params, 0, sizeof(out_params));
 891         rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
 892         if (rc)
 893                 return rc;
 894
 895         /* First handle cases where another load request should/might be sent:
 896          * - MFW expects the old interface [HSI version = 1]
 897          * - MFW responds that a force load request is required
 898          */
 899         if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 900                 DP_INFO(p_hwfn,
 901                         "MFW refused a load request due to HSI > 1. Resending with HSI = 1\n");
 902
 903                 in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_1;
 904                 memset(&out_params, 0, sizeof(out_params));
 905                 rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
 906                 if (rc)
 907                         return rc;
 908         } else if (out_params.load_code ==
 909                    FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
 910                 if (qed_mcp_can_force_load(in_params.drv_role,
 911                                            out_params.exist_drv_role,
 912                                            p_params->override_force_load)) {
 913                         DP_INFO(p_hwfn,
 914                                 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}]\n",
 915                                 in_params.drv_role, in_params.fw_ver,
 916                                 in_params.drv_ver_0, in_params.drv_ver_1,
 917                                 out_params.exist_drv_role,
 918                                 out_params.exist_fw_ver,
 919                                 out_params.exist_drv_ver_0,
 920                                 out_params.exist_drv_ver_1);
 921
 922                         qed_get_mfw_force_cmd(p_hwfn,
 923                                               QED_LOAD_REQ_FORCE_ALL,
 924                                               &mfw_force_cmd);
 925
 926                         in_params.force_cmd = mfw_force_cmd;
 927                         memset(&out_params, 0, sizeof(out_params));
 928                         rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params,
 929                                                 &out_params);
 930                         if (rc)
 931                                 return rc;
 932                 } else {
 933                         DP_NOTICE(p_hwfn,
 934                                   "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n",
 935                                   in_params.drv_role, in_params.fw_ver,
 936                                   in_params.drv_ver_0, in_params.drv_ver_1,
 937                                   out_params.exist_drv_role,
 938                                   out_params.exist_fw_ver,
 939                                   out_params.exist_drv_ver_0,
 940                                   out_params.exist_drv_ver_1);
 941                         DP_NOTICE(p_hwfn,
 942                                   "Avoid sending a force load request to prevent disruption of active PFs\n");
 943
 944                         qed_mcp_cancel_load_req(p_hwfn, p_ptt);
 945                         return -EBUSY;
 946                 }
 947         }
 948
 949         /* Now handle the other types of responses.
 950          * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not
 951          * expected here after the additional revised load requests were sent.
 952          */
 953         switch (out_params.load_code) {
 954         case FW_MSG_CODE_DRV_LOAD_ENGINE:
 955         case FW_MSG_CODE_DRV_LOAD_PORT:
 956         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
 957                 if (out_params.mfw_hsi_ver != QED_LOAD_REQ_HSI_VER_1 &&
 958                     out_params.drv_exists) {
 959                         /* The role and fw/driver version match, but the PF is
 960                          * already loaded and has not been unloaded gracefully.
 961                          */
 962                         DP_NOTICE(p_hwfn,
 963                                   "PF is already loaded\n");
 964                         return -EINVAL;
 965                 }
 966                 break;
 967         default:
 968                 DP_NOTICE(p_hwfn,
 969                           "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n",
 970                           out_params.load_code);
 971                 return -EBUSY;
 972         }
 973
 974         p_params->load_code = out_params.load_code;
 975
 976         return 0;
 977 }
 978
 979 int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 980 {
 981         u32 wol_param, mcp_resp, mcp_param;
 982
 983         switch (p_hwfn->cdev->wol_config) {
 984         case QED_OV_WOL_DISABLED:
 985                 wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED;
 986                 break;
 987         case QED_OV_WOL_ENABLED:
 988                 wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED;
 989                 break;
 990         default:
 991                 DP_NOTICE(p_hwfn,
 992                           "Unknown WoL configuration %02x\n",
 993                           p_hwfn->cdev->wol_config);
 994                 /* Fallthrough */
 995         case QED_OV_WOL_DEFAULT:
 996                 wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
 997         }
 998
 999         return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param,
1000                            &mcp_resp, &mcp_param);
1001 }
1002
1003 int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1004 {
1005         struct qed_mcp_mb_params mb_params;
1006         struct mcp_mac wol_mac;
1007
1008         memset(&mb_params, 0, sizeof(mb_params));
1009         mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
1010
1011         /* Set the primary MAC if WoL is enabled */
1012         if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) {
1013                 u8 *p_mac = p_hwfn->cdev->wol_mac;
1014
1015                 memset(&wol_mac, 0, sizeof(wol_mac));
1016                 wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1];
1017                 wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 |
1018                                     p_mac[4] << 8 | p_mac[5];
1019
1020                 DP_VERBOSE(p_hwfn,
1021                            (QED_MSG_SP | NETIF_MSG_IFDOWN),
1022                            "Setting WoL MAC: %pM --> [%08x,%08x]\n",
1023                            p_mac, wol_mac.mac_upper, wol_mac.mac_lower);
1024
1025                 mb_params.p_data_src = &wol_mac;
1026                 mb_params.data_src_size = sizeof(wol_mac);
1027         }
1028
1029         return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1030 }
1031
1032 static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn,
1033                                   struct qed_ptt *p_ptt)
1034 {
1035         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1036                                         PUBLIC_PATH);
1037         u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
1038         u32 path_addr = SECTION_ADDR(mfw_path_offsize,
1039                                      QED_PATH_ID(p_hwfn));
1040         u32 disabled_vfs[VF_MAX_STATIC / 32];
1041         int i;
1042
1043         DP_VERBOSE(p_hwfn,
1044                    QED_MSG_SP,
1045                    "Reading Disabled VF information from [offset %08x], path_addr %08x\n",
1046                    mfw_path_offsize, path_addr);
1047
1048         for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
1049                 disabled_vfs[i] = qed_rd(p_hwfn, p_ptt,
1050                                          path_addr +
1051                                          offsetof(struct public_path,
1052                                                   mcp_vf_disabled) +
1053                                          sizeof(u32) * i);
1054                 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV),
1055                            "FLR-ed VFs [%08x,...,%08x] - %08x\n",
1056                            i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
1057         }
1058
1059         if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs))
1060                 qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG);
1061 }
1062
1063 int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn,
1064                        struct qed_ptt *p_ptt, u32 *vfs_to_ack)
1065 {
1066         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1067                                         PUBLIC_FUNC);
1068         u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr);
1069         u32 func_addr = SECTION_ADDR(mfw_func_offsize,
1070                                      MCP_PF_ID(p_hwfn));
1071         struct qed_mcp_mb_params mb_params;
1072         int rc;
1073         int i;
1074
1075         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1076                 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV),
1077                            "Acking VFs [%08x,...,%08x] - %08x\n",
1078                            i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
1079
1080         memset(&mb_params, 0, sizeof(mb_params));
1081         mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
1082         mb_params.p_data_src = vfs_to_ack;
1083         mb_params.data_src_size = VF_MAX_STATIC / 8;
1084         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1085         if (rc) {
1086                 DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n");
1087                 return -EBUSY;
1088         }
1089
1090         /* Clear the ACK bits */
1091         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1092                 qed_wr(p_hwfn, p_ptt,
1093                        func_addr +
1094                        offsetof(struct public_func, drv_ack_vf_disabled) +
1095                        i * sizeof(u32), 0);
1096
1097         return rc;
1098 }
1099
1100 static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn,
1101                                               struct qed_ptt *p_ptt)
1102 {
1103         u32 transceiver_state;
1104
1105         transceiver_state = qed_rd(p_hwfn, p_ptt,
1106                                    p_hwfn->mcp_info->port_addr +
1107                                    offsetof(struct public_port,
1108                                             transceiver_data));
1109
1110         DP_VERBOSE(p_hwfn,
1111                    (NETIF_MSG_HW | QED_MSG_SP),
1112                    "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n",
1113                    transceiver_state,
1114                    (u32)(p_hwfn->mcp_info->port_addr +
1115                           offsetof(struct public_port, transceiver_data)));
1116
1117         transceiver_state = GET_FIELD(transceiver_state,
1118                                       ETH_TRANSCEIVER_STATE);
1119
1120         if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1121                 DP_NOTICE(p_hwfn, "Transceiver is present.\n");
1122         else
1123                 DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n");
1124 }
1125
1126 static void qed_mcp_read_eee_config(struct qed_hwfn *p_hwfn,
1127                                     struct qed_ptt *p_ptt,
1128                                     struct qed_mcp_link_state *p_link)
1129 {
1130         u32 eee_status, val;
1131
1132         p_link->eee_adv_caps = 0;
1133         p_link->eee_lp_adv_caps = 0;
1134         eee_status = qed_rd(p_hwfn,
1135                             p_ptt,
1136                             p_hwfn->mcp_info->port_addr +
1137                             offsetof(struct public_port, eee_status));
1138         p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT);
1139         val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET;
1140         if (val & EEE_1G_ADV)
1141                 p_link->eee_adv_caps |= QED_EEE_1G_ADV;
1142         if (val & EEE_10G_ADV)
1143                 p_link->eee_adv_caps |= QED_EEE_10G_ADV;
1144         val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET;
1145         if (val & EEE_1G_ADV)
1146                 p_link->eee_lp_adv_caps |= QED_EEE_1G_ADV;
1147         if (val & EEE_10G_ADV)
1148                 p_link->eee_lp_adv_caps |= QED_EEE_10G_ADV;
1149 }
1150
1151 static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn,
1152                                        struct qed_ptt *p_ptt, bool b_reset)
1153 {
1154         struct qed_mcp_link_state *p_link;
1155         u8 max_bw, min_bw;
1156         u32 status = 0;
1157
1158         /* Prevent SW/attentions from doing this at the same time */
1159         spin_lock_bh(&p_hwfn->mcp_info->link_lock);
1160
1161         p_link = &p_hwfn->mcp_info->link_output;
1162         memset(p_link, 0, sizeof(*p_link));
1163         if (!b_reset) {
1164                 status = qed_rd(p_hwfn, p_ptt,
1165                                 p_hwfn->mcp_info->port_addr +
1166                                 offsetof(struct public_port, link_status));
1167                 DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP),
1168                            "Received link update [0x%08x] from mfw [Addr 0x%x]\n",
1169                            status,
1170                            (u32)(p_hwfn->mcp_info->port_addr +
1171                                  offsetof(struct public_port, link_status)));
1172         } else {
1173                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1174                            "Resetting link indications\n");
1175                 goto out;
1176         }
1177
1178         if (p_hwfn->b_drv_link_init)
1179                 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1180         else
1181                 p_link->link_up = false;
1182
1183         p_link->full_duplex = true;
1184         switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1185         case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1186                 p_link->speed = 100000;
1187                 break;
1188         case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1189                 p_link->speed = 50000;
1190                 break;
1191         case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1192                 p_link->speed = 40000;
1193                 break;
1194         case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1195                 p_link->speed = 25000;
1196                 break;
1197         case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1198                 p_link->speed = 20000;
1199                 break;
1200         case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1201                 p_link->speed = 10000;
1202                 break;
1203         case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1204                 p_link->full_duplex = false;
1205         /* Fall-through */
1206         case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1207                 p_link->speed = 1000;
1208                 break;
1209         default:
1210                 p_link->speed = 0;
1211         }
1212
1213         if (p_link->link_up && p_link->speed)
1214                 p_link->line_speed = p_link->speed;
1215         else
1216                 p_link->line_speed = 0;
1217
1218         max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1219         min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1220
1221         /* Max bandwidth configuration */
1222         __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw);
1223
1224         /* Min bandwidth configuration */
1225         __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw);
1226         qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt,
1227                                             p_link->min_pf_rate);
1228
1229         p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1230         p_link->an_complete = !!(status &
1231                                  LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1232         p_link->parallel_detection = !!(status &
1233                                         LINK_STATUS_PARALLEL_DETECTION_USED);
1234         p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1235
1236         p_link->partner_adv_speed |=
1237                 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1238                 QED_LINK_PARTNER_SPEED_1G_FD : 0;
1239         p_link->partner_adv_speed |=
1240                 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1241                 QED_LINK_PARTNER_SPEED_1G_HD : 0;
1242         p_link->partner_adv_speed |=
1243                 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1244                 QED_LINK_PARTNER_SPEED_10G : 0;
1245         p_link->partner_adv_speed |=
1246                 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1247                 QED_LINK_PARTNER_SPEED_20G : 0;
1248         p_link->partner_adv_speed |=
1249                 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1250                 QED_LINK_PARTNER_SPEED_25G : 0;
1251         p_link->partner_adv_speed |=
1252                 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1253                 QED_LINK_PARTNER_SPEED_40G : 0;
1254         p_link->partner_adv_speed |=
1255                 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1256                 QED_LINK_PARTNER_SPEED_50G : 0;
1257         p_link->partner_adv_speed |=
1258                 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1259                 QED_LINK_PARTNER_SPEED_100G : 0;
1260
1261         p_link->partner_tx_flow_ctrl_en =
1262                 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1263         p_link->partner_rx_flow_ctrl_en =
1264                 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1265
1266         switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1267         case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1268                 p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE;
1269                 break;
1270         case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1271                 p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE;
1272                 break;
1273         case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1274                 p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE;
1275                 break;
1276         default:
1277                 p_link->partner_adv_pause = 0;
1278         }
1279
1280         p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1281
1282         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE)
1283                 qed_mcp_read_eee_config(p_hwfn, p_ptt, p_link);
1284
1285         qed_link_update(p_hwfn);
1286 out:
1287         spin_unlock_bh(&p_hwfn->mcp_info->link_lock);
1288 }
1289
1290 int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up)
1291 {
1292         struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1293         struct qed_mcp_mb_params mb_params;
1294         struct eth_phy_cfg phy_cfg;
1295         int rc = 0;
1296         u32 cmd;
1297
1298         /* Set the shmem configuration according to params */
1299         memset(&phy_cfg, 0, sizeof(phy_cfg));
1300         cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1301         if (!params->speed.autoneg)
1302                 phy_cfg.speed = params->speed.forced_speed;
1303         phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1304         phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1305         phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1306         phy_cfg.adv_speed = params->speed.advertised_speeds;
1307         phy_cfg.loopback_mode = params->loopback_mode;
1308         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
1309                 if (params->eee.enable)
1310                         phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED;
1311                 if (params->eee.tx_lpi_enable)
1312                         phy_cfg.eee_cfg |= EEE_CFG_TX_LPI;
1313                 if (params->eee.adv_caps & QED_EEE_1G_ADV)
1314                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G;
1315                 if (params->eee.adv_caps & QED_EEE_10G_ADV)
1316                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G;
1317                 phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer <<
1318                                     EEE_TX_TIMER_USEC_OFFSET) &
1319                                    EEE_TX_TIMER_USEC_MASK;
1320         }
1321
1322         p_hwfn->b_drv_link_init = b_up;
1323
1324         if (b_up) {
1325                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1326                            "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n",
1327                            phy_cfg.speed,
1328                            phy_cfg.pause,
1329                            phy_cfg.adv_speed,
1330                            phy_cfg.loopback_mode,
1331                            phy_cfg.feature_config_flags);
1332         } else {
1333                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1334                            "Resetting link\n");
1335         }
1336
1337         memset(&mb_params, 0, sizeof(mb_params));
1338         mb_params.cmd = cmd;
1339         mb_params.p_data_src = &phy_cfg;
1340         mb_params.data_src_size = sizeof(phy_cfg);
1341         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1342
1343         /* if mcp fails to respond we must abort */
1344         if (rc) {
1345                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1346                 return rc;
1347         }
1348
1349         /* Mimic link-change attention, done for several reasons:
1350          *  - On reset, there's no guarantee MFW would trigger
1351          *    an attention.
1352          *  - On initialization, older MFWs might not indicate link change
1353          *    during LFA, so we'll never get an UP indication.
1354          */
1355         qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up);
1356
1357         return 0;
1358 }
1359
1360 static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn,
1361                                         struct qed_ptt *p_ptt,
1362                                         enum MFW_DRV_MSG_TYPE type)
1363 {
1364         enum qed_mcp_protocol_type stats_type;
1365         union qed_mcp_protocol_stats stats;
1366         struct qed_mcp_mb_params mb_params;
1367         u32 hsi_param;
1368
1369         switch (type) {
1370         case MFW_DRV_MSG_GET_LAN_STATS:
1371                 stats_type = QED_MCP_LAN_STATS;
1372                 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1373                 break;
1374         case MFW_DRV_MSG_GET_FCOE_STATS:
1375                 stats_type = QED_MCP_FCOE_STATS;
1376                 hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE;
1377                 break;
1378         case MFW_DRV_MSG_GET_ISCSI_STATS:
1379                 stats_type = QED_MCP_ISCSI_STATS;
1380                 hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI;
1381                 break;
1382         case MFW_DRV_MSG_GET_RDMA_STATS:
1383                 stats_type = QED_MCP_RDMA_STATS;
1384                 hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA;
1385                 break;
1386         default:
1387                 DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type);
1388                 return;
1389         }
1390
1391         qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats);
1392
1393         memset(&mb_params, 0, sizeof(mb_params));
1394         mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1395         mb_params.param = hsi_param;
1396         mb_params.p_data_src = &stats;
1397         mb_params.data_src_size = sizeof(stats);
1398         qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1399 }
1400
1401 static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn,
1402                                   struct public_func *p_shmem_info)
1403 {
1404         struct qed_mcp_function_info *p_info;
1405
1406         p_info = &p_hwfn->mcp_info->func_info;
1407
1408         p_info->bandwidth_min = (p_shmem_info->config &
1409                                  FUNC_MF_CFG_MIN_BW_MASK) >>
1410                                         FUNC_MF_CFG_MIN_BW_SHIFT;
1411         if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1412                 DP_INFO(p_hwfn,
1413                         "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1414                         p_info->bandwidth_min);
1415                 p_info->bandwidth_min = 1;
1416         }
1417
1418         p_info->bandwidth_max = (p_shmem_info->config &
1419                                  FUNC_MF_CFG_MAX_BW_MASK) >>
1420                                         FUNC_MF_CFG_MAX_BW_SHIFT;
1421         if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1422                 DP_INFO(p_hwfn,
1423                         "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1424                         p_info->bandwidth_max);
1425                 p_info->bandwidth_max = 100;
1426         }
1427 }
1428
1429 static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn,
1430                                   struct qed_ptt *p_ptt,
1431                                   struct public_func *p_data, int pfid)
1432 {
1433         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1434                                         PUBLIC_FUNC);
1435         u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
1436         u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1437         u32 i, size;
1438
1439         memset(p_data, 0, sizeof(*p_data));
1440
1441         size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize));
1442         for (i = 0; i < size / sizeof(u32); i++)
1443                 ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt,
1444                                             func_addr + (i << 2));
1445         return size;
1446 }
1447
1448 static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1449 {
1450         struct qed_mcp_function_info *p_info;
1451         struct public_func shmem_info;
1452         u32 resp = 0, param = 0;
1453
1454         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1455
1456         qed_read_pf_bandwidth(p_hwfn, &shmem_info);
1457
1458         p_info = &p_hwfn->mcp_info->func_info;
1459
1460         qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min);
1461         qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max);
1462
1463         /* Acknowledge the MFW */
1464         qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1465                     &param);
1466 }
1467
1468 static void qed_mcp_update_stag(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1469 {
1470         struct public_func shmem_info;
1471         u32 resp = 0, param = 0;
1472
1473         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1474
1475         p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag &
1476                                                  FUNC_MF_CFG_OV_STAG_MASK;
1477         p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan;
1478         if ((p_hwfn->hw_info.hw_mode & BIT(MODE_MF_SD)) &&
1479             (p_hwfn->hw_info.ovlan != QED_MCP_VLAN_UNSET)) {
1480                 qed_wr(p_hwfn, p_ptt,
1481                        NIG_REG_LLH_FUNC_TAG_VALUE, p_hwfn->hw_info.ovlan);
1482                 qed_sp_pf_update_stag(p_hwfn);
1483         }
1484
1485         /* Acknowledge the MFW */
1486         qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0,
1487                     &resp, &param);
1488 }
1489
1490 void qed_mcp_read_ufp_config(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1491 {
1492         struct public_func shmem_info;
1493         u32 port_cfg, val;
1494
1495         if (!test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits))
1496                 return;
1497
1498         memset(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info));
1499         port_cfg = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1500                           offsetof(struct public_port, oem_cfg_port));
1501         val = (port_cfg & OEM_CFG_CHANNEL_TYPE_MASK) >>
1502                 OEM_CFG_CHANNEL_TYPE_OFFSET;
1503         if (val != OEM_CFG_CHANNEL_TYPE_STAGGED)
1504                 DP_NOTICE(p_hwfn, "Incorrect UFP Channel type  %d\n", val);
1505
1506         val = (port_cfg & OEM_CFG_SCHED_TYPE_MASK) >> OEM_CFG_SCHED_TYPE_OFFSET;
1507         if (val == OEM_CFG_SCHED_TYPE_ETS) {
1508                 p_hwfn->ufp_info.mode = QED_UFP_MODE_ETS;
1509         } else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW) {
1510                 p_hwfn->ufp_info.mode = QED_UFP_MODE_VNIC_BW;
1511         } else {
1512                 p_hwfn->ufp_info.mode = QED_UFP_MODE_UNKNOWN;
1513                 DP_NOTICE(p_hwfn, "Unknown UFP scheduling mode %d\n", val);
1514         }
1515
1516         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1517         val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_TC_MASK) >>
1518                 OEM_CFG_FUNC_TC_OFFSET;
1519         p_hwfn->ufp_info.tc = (u8)val;
1520         val = (shmem_info.oem_cfg_func & OEM_CFG_FUNC_HOST_PRI_CTRL_MASK) >>
1521                 OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET;
1522         if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC) {
1523                 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_VNIC;
1524         } else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS) {
1525                 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_OS;
1526         } else {
1527                 p_hwfn->ufp_info.pri_type = QED_UFP_PRI_UNKNOWN;
1528                 DP_NOTICE(p_hwfn, "Unknown Host priority control %d\n", val);
1529         }
1530
1531         DP_NOTICE(p_hwfn,
1532                   "UFP shmem config: mode = %d tc = %d pri_type = %d\n",
1533                   p_hwfn->ufp_info.mode,
1534                   p_hwfn->ufp_info.tc, p_hwfn->ufp_info.pri_type);
1535 }
1536
1537 static int
1538 qed_mcp_handle_ufp_event(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1539 {
1540         qed_mcp_read_ufp_config(p_hwfn, p_ptt);
1541
1542         if (p_hwfn->ufp_info.mode == QED_UFP_MODE_VNIC_BW) {
1543                 p_hwfn->qm_info.ooo_tc = p_hwfn->ufp_info.tc;
1544                 p_hwfn->hw_info.offload_tc = p_hwfn->ufp_info.tc;
1545
1546                 qed_qm_reconf(p_hwfn, p_ptt);
1547         } else if (p_hwfn->ufp_info.mode == QED_UFP_MODE_ETS) {
1548                 /* Merge UFP TC with the dcbx TC data */
1549                 qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1550                                           QED_DCBX_OPERATIONAL_MIB);
1551         } else {
1552                 DP_ERR(p_hwfn, "Invalid sched type, discard the UFP config\n");
1553                 return -EINVAL;
1554         }
1555
1556         /* update storm FW with negotiation results */
1557         qed_sp_pf_update_ufp(p_hwfn);
1558
1559         /* update stag pcp value */
1560         qed_sp_pf_update_stag(p_hwfn);
1561
1562         return 0;
1563 }
1564
1565 int qed_mcp_handle_events(struct qed_hwfn *p_hwfn,
1566                           struct qed_ptt *p_ptt)
1567 {
1568         struct qed_mcp_info *info = p_hwfn->mcp_info;
1569         int rc = 0;
1570         bool found = false;
1571         u16 i;
1572
1573         DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n");
1574
1575         /* Read Messages from MFW */
1576         qed_mcp_read_mb(p_hwfn, p_ptt);
1577
1578         /* Compare current messages to old ones */
1579         for (i = 0; i < info->mfw_mb_length; i++) {
1580                 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1581                         continue;
1582
1583                 found = true;
1584
1585                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1586                            "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1587                            i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1588
1589                 switch (i) {
1590                 case MFW_DRV_MSG_LINK_CHANGE:
1591                         qed_mcp_handle_link_change(p_hwfn, p_ptt, false);
1592                         break;
1593                 case MFW_DRV_MSG_VF_DISABLED:
1594                         qed_mcp_handle_vf_flr(p_hwfn, p_ptt);
1595                         break;
1596                 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1597                         qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1598                                                   QED_DCBX_REMOTE_LLDP_MIB);
1599                         break;
1600                 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1601                         qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1602                                                   QED_DCBX_REMOTE_MIB);
1603                         break;
1604                 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1605                         qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1606                                                   QED_DCBX_OPERATIONAL_MIB);
1607                         break;
1608                 case MFW_DRV_MSG_OEM_CFG_UPDATE:
1609                         qed_mcp_handle_ufp_event(p_hwfn, p_ptt);
1610                         break;
1611                 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1612                         qed_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1613                         break;
1614                 case MFW_DRV_MSG_GET_LAN_STATS:
1615                 case MFW_DRV_MSG_GET_FCOE_STATS:
1616                 case MFW_DRV_MSG_GET_ISCSI_STATS:
1617                 case MFW_DRV_MSG_GET_RDMA_STATS:
1618                         qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1619                         break;
1620                 case MFW_DRV_MSG_BW_UPDATE:
1621                         qed_mcp_update_bw(p_hwfn, p_ptt);
1622                         break;
1623                 case MFW_DRV_MSG_S_TAG_UPDATE:
1624                         qed_mcp_update_stag(p_hwfn, p_ptt);
1625                         break;
1626                 case MFW_DRV_MSG_GET_TLV_REQ:
1627                         qed_mfw_tlv_req(p_hwfn);
1628                         break;
1629                 default:
1630                         DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
1631                         rc = -EINVAL;
1632                 }
1633         }
1634
1635         /* ACK everything */
1636         for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1637                 __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]);
1638
1639                 /* MFW expect answer in BE, so we force write in that format */
1640                 qed_wr(p_hwfn, p_ptt,
1641                        info->mfw_mb_addr + sizeof(u32) +
1642                        MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1643                        sizeof(u32) + i * sizeof(u32),
1644                        (__force u32)val);
1645         }
1646
1647         if (!found) {
1648                 DP_NOTICE(p_hwfn,
1649                           "Received an MFW message indication but no new message!\n");
1650                 rc = -EINVAL;
1651         }
1652
1653         /* Copy the new mfw messages into the shadow */
1654         memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1655
1656         return rc;
1657 }
1658
1659 int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn,
1660                         struct qed_ptt *p_ptt,
1661                         u32 *p_mfw_ver, u32 *p_running_bundle_id)
1662 {
1663         u32 global_offsize;
1664
1665         if (IS_VF(p_hwfn->cdev)) {
1666                 if (p_hwfn->vf_iov_info) {
1667                         struct pfvf_acquire_resp_tlv *p_resp;
1668
1669                         p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1670                         *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1671                         return 0;
1672                 } else {
1673                         DP_VERBOSE(p_hwfn,
1674                                    QED_MSG_IOV,
1675                                    "VF requested MFW version prior to ACQUIRE\n");
1676                         return -EINVAL;
1677                 }
1678         }
1679
1680         global_offsize = qed_rd(p_hwfn, p_ptt,
1681                                 SECTION_OFFSIZE_ADDR(p_hwfn->
1682                                                      mcp_info->public_base,
1683                                                      PUBLIC_GLOBAL));
1684         *p_mfw_ver =
1685             qed_rd(p_hwfn, p_ptt,
1686                    SECTION_ADDR(global_offsize,
1687                                 0) + offsetof(struct public_global, mfw_ver));
1688
1689         if (p_running_bundle_id != NULL) {
1690                 *p_running_bundle_id = qed_rd(p_hwfn, p_ptt,
1691                                               SECTION_ADDR(global_offsize, 0) +
1692                                               offsetof(struct public_global,
1693                                                        running_bundle_id));
1694         }
1695
1696         return 0;
1697 }
1698
1699 int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn,
1700                         struct qed_ptt *p_ptt, u32 *p_mbi_ver)
1701 {
1702         u32 nvm_cfg_addr, nvm_cfg1_offset, mbi_ver_addr;
1703
1704         if (IS_VF(p_hwfn->cdev))
1705                 return -EINVAL;
1706
1707         /* Read the address of the nvm_cfg */
1708         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
1709         if (!nvm_cfg_addr) {
1710                 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
1711                 return -EINVAL;
1712         }
1713
1714         /* Read the offset of nvm_cfg1 */
1715         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
1716
1717         mbi_ver_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1718                        offsetof(struct nvm_cfg1, glob) +
1719                        offsetof(struct nvm_cfg1_glob, mbi_version);
1720         *p_mbi_ver = qed_rd(p_hwfn, p_ptt,
1721                             mbi_ver_addr) &
1722                      (NVM_CFG1_GLOB_MBI_VERSION_0_MASK |
1723                       NVM_CFG1_GLOB_MBI_VERSION_1_MASK |
1724                       NVM_CFG1_GLOB_MBI_VERSION_2_MASK);
1725
1726         return 0;
1727 }
1728
1729 int qed_mcp_get_media_type(struct qed_dev *cdev, u32 *p_media_type)
1730 {
1731         struct qed_hwfn *p_hwfn = &cdev->hwfns[0];
1732         struct qed_ptt  *p_ptt;
1733
1734         if (IS_VF(cdev))
1735                 return -EINVAL;
1736
1737         if (!qed_mcp_is_init(p_hwfn)) {
1738                 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
1739                 return -EBUSY;
1740         }
1741
1742         *p_media_type = MEDIA_UNSPECIFIED;
1743
1744         p_ptt = qed_ptt_acquire(p_hwfn);
1745         if (!p_ptt)
1746                 return -EBUSY;
1747
1748         *p_media_type = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1749                                offsetof(struct public_port, media_type));
1750
1751         qed_ptt_release(p_hwfn, p_ptt);
1752
1753         return 0;
1754 }
1755
1756 /* Old MFW has a global configuration for all PFs regarding RDMA support */
1757 static void
1758 qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn,
1759                                enum qed_pci_personality *p_proto)
1760 {
1761         /* There wasn't ever a legacy MFW that published iwarp.
1762          * So at this point, this is either plain l2 or RoCE.
1763          */
1764         if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities))
1765                 *p_proto = QED_PCI_ETH_ROCE;
1766         else
1767                 *p_proto = QED_PCI_ETH;
1768
1769         DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
1770                    "According to Legacy capabilities, L2 personality is %08x\n",
1771                    (u32) *p_proto);
1772 }
1773
1774 static int
1775 qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn,
1776                             struct qed_ptt *p_ptt,
1777                             enum qed_pci_personality *p_proto)
1778 {
1779         u32 resp = 0, param = 0;
1780         int rc;
1781
1782         rc = qed_mcp_cmd(p_hwfn, p_ptt,
1783                          DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, &param);
1784         if (rc)
1785                 return rc;
1786         if (resp != FW_MSG_CODE_OK) {
1787                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
1788                            "MFW lacks support for command; Returns %08x\n",
1789                            resp);
1790                 return -EINVAL;
1791         }
1792
1793         switch (param) {
1794         case FW_MB_PARAM_GET_PF_RDMA_NONE:
1795                 *p_proto = QED_PCI_ETH;
1796                 break;
1797         case FW_MB_PARAM_GET_PF_RDMA_ROCE:
1798                 *p_proto = QED_PCI_ETH_ROCE;
1799                 break;
1800         case FW_MB_PARAM_GET_PF_RDMA_IWARP:
1801                 *p_proto = QED_PCI_ETH_IWARP;
1802                 break;
1803         case FW_MB_PARAM_GET_PF_RDMA_BOTH:
1804                 *p_proto = QED_PCI_ETH_RDMA;
1805                 break;
1806         default:
1807                 DP_NOTICE(p_hwfn,
1808                           "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n",
1809                           param);
1810                 return -EINVAL;
1811         }
1812
1813         DP_VERBOSE(p_hwfn,
1814                    NETIF_MSG_IFUP,
1815                    "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
1816                    (u32) *p_proto, resp, param);
1817         return 0;
1818 }
1819
1820 static int
1821 qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn,
1822                         struct public_func *p_info,
1823                         struct qed_ptt *p_ptt,
1824                         enum qed_pci_personality *p_proto)
1825 {
1826         int rc = 0;
1827
1828         switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
1829         case FUNC_MF_CFG_PROTOCOL_ETHERNET:
1830                 if (!IS_ENABLED(CONFIG_QED_RDMA))
1831                         *p_proto = QED_PCI_ETH;
1832                 else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto))
1833                         qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
1834                 break;
1835         case FUNC_MF_CFG_PROTOCOL_ISCSI:
1836                 *p_proto = QED_PCI_ISCSI;
1837                 break;
1838         case FUNC_MF_CFG_PROTOCOL_FCOE:
1839                 *p_proto = QED_PCI_FCOE;
1840                 break;
1841         case FUNC_MF_CFG_PROTOCOL_ROCE:
1842                 DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n");
1843         /* Fallthrough */
1844         default:
1845                 rc = -EINVAL;
1846         }
1847
1848         return rc;
1849 }
1850
1851 int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn,
1852                                  struct qed_ptt *p_ptt)
1853 {
1854         struct qed_mcp_function_info *info;
1855         struct public_func shmem_info;
1856
1857         qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1858         info = &p_hwfn->mcp_info->func_info;
1859
1860         info->pause_on_host = (shmem_info.config &
1861                                FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
1862
1863         if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
1864                                     &info->protocol)) {
1865                 DP_ERR(p_hwfn, "Unknown personality %08x\n",
1866                        (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
1867                 return -EINVAL;
1868         }
1869
1870         qed_read_pf_bandwidth(p_hwfn, &shmem_info);
1871
1872         if (shmem_info.mac_upper || shmem_info.mac_lower) {
1873                 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
1874                 info->mac[1] = (u8)(shmem_info.mac_upper);
1875                 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
1876                 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
1877                 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
1878                 info->mac[5] = (u8)(shmem_info.mac_lower);
1879
1880                 /* Store primary MAC for later possible WoL */
1881                 memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN);
1882         } else {
1883                 DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n");
1884         }
1885
1886         info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_lower |
1887                          (((u64)shmem_info.fcoe_wwn_port_name_upper) << 32);
1888         info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_lower |
1889                          (((u64)shmem_info.fcoe_wwn_node_name_upper) << 32);
1890
1891         info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
1892
1893         info->mtu = (u16)shmem_info.mtu_size;
1894
1895         p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE;
1896         p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT;
1897         if (qed_mcp_is_init(p_hwfn)) {
1898                 u32 resp = 0, param = 0;
1899                 int rc;
1900
1901                 rc = qed_mcp_cmd(p_hwfn, p_ptt,
1902                                  DRV_MSG_CODE_OS_WOL, 0, &resp, &param);
1903                 if (rc)
1904                         return rc;
1905                 if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED)
1906                         p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME;
1907         }
1908
1909         DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP),
1910                    "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x wol %02x\n",
1911                 info->pause_on_host, info->protocol,
1912                 info->bandwidth_min, info->bandwidth_max,
1913                 info->mac[0], info->mac[1], info->mac[2],
1914                 info->mac[3], info->mac[4], info->mac[5],
1915                 info->wwn_port, info->wwn_node,
1916                 info->ovlan, (u8)p_hwfn->hw_info.b_wol_support);
1917
1918         return 0;
1919 }
1920
1921 struct qed_mcp_link_params
1922 *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn)
1923 {
1924         if (!p_hwfn || !p_hwfn->mcp_info)
1925                 return NULL;
1926         return &p_hwfn->mcp_info->link_input;
1927 }
1928
1929 struct qed_mcp_link_state
1930 *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn)
1931 {
1932         if (!p_hwfn || !p_hwfn->mcp_info)
1933                 return NULL;
1934         return &p_hwfn->mcp_info->link_output;
1935 }
1936
1937 struct qed_mcp_link_capabilities
1938 *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn)
1939 {
1940         if (!p_hwfn || !p_hwfn->mcp_info)
1941                 return NULL;
1942         return &p_hwfn->mcp_info->link_capabilities;
1943 }
1944
1945 int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1946 {
1947         u32 resp = 0, param = 0;
1948         int rc;
1949
1950         rc = qed_mcp_cmd(p_hwfn, p_ptt,
1951                          DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, &param);
1952
1953         /* Wait for the drain to complete before returning */
1954         msleep(1020);
1955
1956         return rc;
1957 }
1958
1959 int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn,
1960                            struct qed_ptt *p_ptt, u32 *p_flash_size)
1961 {
1962         u32 flash_size;
1963
1964         if (IS_VF(p_hwfn->cdev))
1965                 return -EINVAL;
1966
1967         flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
1968         flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
1969                       MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
1970         flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
1971
1972         *p_flash_size = flash_size;
1973
1974         return 0;
1975 }
1976
1977 static int
1978 qed_mcp_config_vf_msix_bb(struct qed_hwfn *p_hwfn,
1979                           struct qed_ptt *p_ptt, u8 vf_id, u8 num)
1980 {
1981         u32 resp = 0, param = 0, rc_param = 0;
1982         int rc;
1983
1984         /* Only Leader can configure MSIX, and need to take CMT into account */
1985         if (!IS_LEAD_HWFN(p_hwfn))
1986                 return 0;
1987         num *= p_hwfn->cdev->num_hwfns;
1988
1989         param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
1990                  DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
1991         param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
1992                  DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
1993
1994         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
1995                          &resp, &rc_param);
1996
1997         if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
1998                 DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id);
1999                 rc = -EINVAL;
2000         } else {
2001                 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2002                            "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
2003                            num, vf_id);
2004         }
2005
2006         return rc;
2007 }
2008
2009 static int
2010 qed_mcp_config_vf_msix_ah(struct qed_hwfn *p_hwfn,
2011                           struct qed_ptt *p_ptt, u8 num)
2012 {
2013         u32 resp = 0, param = num, rc_param = 0;
2014         int rc;
2015
2016         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX,
2017                          param, &resp, &rc_param);
2018
2019         if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) {
2020                 DP_NOTICE(p_hwfn, "MFW failed to set MSI-X for VFs\n");
2021                 rc = -EINVAL;
2022         } else {
2023                 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2024                            "Requested 0x%02x MSI-x interrupts for VFs\n", num);
2025         }
2026
2027         return rc;
2028 }
2029
2030 int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn,
2031                            struct qed_ptt *p_ptt, u8 vf_id, u8 num)
2032 {
2033         if (QED_IS_BB(p_hwfn->cdev))
2034                 return qed_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num);
2035         else
2036                 return qed_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num);
2037 }
2038
2039 int
2040 qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn,
2041                          struct qed_ptt *p_ptt,
2042                          struct qed_mcp_drv_version *p_ver)
2043 {
2044         struct qed_mcp_mb_params mb_params;
2045         struct drv_version_stc drv_version;
2046         __be32 val;
2047         u32 i;
2048         int rc;
2049
2050         memset(&drv_version, 0, sizeof(drv_version));
2051         drv_version.version = p_ver->version;
2052         for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) {
2053                 val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)]));
2054                 *(__be32 *)&drv_version.name[i * sizeof(u32)] = val;
2055         }
2056
2057         memset(&mb_params, 0, sizeof(mb_params));
2058         mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
2059         mb_params.p_data_src = &drv_version;
2060         mb_params.data_src_size = sizeof(drv_version);
2061         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2062         if (rc)
2063                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2064
2065         return rc;
2066 }
2067
2068 int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2069 {
2070         u32 resp = 0, param = 0;
2071         int rc;
2072
2073         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
2074                          &param);
2075         if (rc)
2076                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2077
2078         return rc;
2079 }
2080
2081 int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2082 {
2083         u32 value, cpu_mode;
2084
2085         qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
2086
2087         value = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2088         value &= ~MCP_REG_CPU_MODE_SOFT_HALT;
2089         qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value);
2090         cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2091
2092         return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -EAGAIN : 0;
2093 }
2094
2095 int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn,
2096                                      struct qed_ptt *p_ptt,
2097                                      enum qed_ov_client client)
2098 {
2099         u32 resp = 0, param = 0;
2100         u32 drv_mb_param;
2101         int rc;
2102
2103         switch (client) {
2104         case QED_OV_CLIENT_DRV:
2105                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
2106                 break;
2107         case QED_OV_CLIENT_USER:
2108                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
2109                 break;
2110         case QED_OV_CLIENT_VENDOR_SPEC:
2111                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
2112                 break;
2113         default:
2114                 DP_NOTICE(p_hwfn, "Invalid client type %d\n", client);
2115                 return -EINVAL;
2116         }
2117
2118         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
2119                          drv_mb_param, &resp, &param);
2120         if (rc)
2121                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2122
2123         return rc;
2124 }
2125
2126 int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn,
2127                                    struct qed_ptt *p_ptt,
2128                                    enum qed_ov_driver_state drv_state)
2129 {
2130         u32 resp = 0, param = 0;
2131         u32 drv_mb_param;
2132         int rc;
2133
2134         switch (drv_state) {
2135         case QED_OV_DRIVER_STATE_NOT_LOADED:
2136                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
2137                 break;
2138         case QED_OV_DRIVER_STATE_DISABLED:
2139                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
2140                 break;
2141         case QED_OV_DRIVER_STATE_ACTIVE:
2142                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
2143                 break;
2144         default:
2145                 DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state);
2146                 return -EINVAL;
2147         }
2148
2149         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
2150                          drv_mb_param, &resp, &param);
2151         if (rc)
2152                 DP_ERR(p_hwfn, "Failed to send driver state\n");
2153
2154         return rc;
2155 }
2156
2157 int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn,
2158                           struct qed_ptt *p_ptt, u16 mtu)
2159 {
2160         u32 resp = 0, param = 0;
2161         u32 drv_mb_param;
2162         int rc;
2163
2164         drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT;
2165         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU,
2166                          drv_mb_param, &resp, &param);
2167         if (rc)
2168                 DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc);
2169
2170         return rc;
2171 }
2172
2173 int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn,
2174                           struct qed_ptt *p_ptt, u8 *mac)
2175 {
2176         struct qed_mcp_mb_params mb_params;
2177         u32 mfw_mac[2];
2178         int rc;
2179
2180         memset(&mb_params, 0, sizeof(mb_params));
2181         mb_params.cmd = DRV_MSG_CODE_SET_VMAC;
2182         mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC <<
2183                           DRV_MSG_CODE_VMAC_TYPE_SHIFT;
2184         mb_params.param |= MCP_PF_ID(p_hwfn);
2185
2186         /* MCP is BE, and on LE platforms PCI would swap access to SHMEM
2187          * in 32-bit granularity.
2188          * So the MAC has to be set in native order [and not byte order],
2189          * otherwise it would be read incorrectly by MFW after swap.
2190          */
2191         mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3];
2192         mfw_mac[1] = mac[4] << 24 | mac[5] << 16;
2193
2194         mb_params.p_data_src = (u8 *)mfw_mac;
2195         mb_params.data_src_size = 8;
2196         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2197         if (rc)
2198                 DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc);
2199
2200         /* Store primary MAC for later possible WoL */
2201         memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN);
2202
2203         return rc;
2204 }
2205
2206 int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn,
2207                           struct qed_ptt *p_ptt, enum qed_ov_wol wol)
2208 {
2209         u32 resp = 0, param = 0;
2210         u32 drv_mb_param;
2211         int rc;
2212
2213         if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) {
2214                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
2215                            "Can't change WoL configuration when WoL isn't supported\n");
2216                 return -EINVAL;
2217         }
2218
2219         switch (wol) {
2220         case QED_OV_WOL_DEFAULT:
2221                 drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT;
2222                 break;
2223         case QED_OV_WOL_DISABLED:
2224                 drv_mb_param = DRV_MB_PARAM_WOL_DISABLED;
2225                 break;
2226         case QED_OV_WOL_ENABLED:
2227                 drv_mb_param = DRV_MB_PARAM_WOL_ENABLED;
2228                 break;
2229         default:
2230                 DP_ERR(p_hwfn, "Invalid wol state %d\n", wol);
2231                 return -EINVAL;
2232         }
2233
2234         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL,
2235                          drv_mb_param, &resp, &param);
2236         if (rc)
2237                 DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc);
2238
2239         /* Store the WoL update for a future unload */
2240         p_hwfn->cdev->wol_config = (u8)wol;
2241
2242         return rc;
2243 }
2244
2245 int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn,
2246                               struct qed_ptt *p_ptt,
2247                               enum qed_ov_eswitch eswitch)
2248 {
2249         u32 resp = 0, param = 0;
2250         u32 drv_mb_param;
2251         int rc;
2252
2253         switch (eswitch) {
2254         case QED_OV_ESWITCH_NONE:
2255                 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE;
2256                 break;
2257         case QED_OV_ESWITCH_VEB:
2258                 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB;
2259                 break;
2260         case QED_OV_ESWITCH_VEPA:
2261                 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA;
2262                 break;
2263         default:
2264                 DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch);
2265                 return -EINVAL;
2266         }
2267
2268         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE,
2269                          drv_mb_param, &resp, &param);
2270         if (rc)
2271                 DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc);
2272
2273         return rc;
2274 }
2275
2276 int qed_mcp_set_led(struct qed_hwfn *p_hwfn,
2277                     struct qed_ptt *p_ptt, enum qed_led_mode mode)
2278 {
2279         u32 resp = 0, param = 0, drv_mb_param;
2280         int rc;
2281
2282         switch (mode) {
2283         case QED_LED_MODE_ON:
2284                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2285                 break;
2286         case QED_LED_MODE_OFF:
2287                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2288                 break;
2289         case QED_LED_MODE_RESTORE:
2290                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2291                 break;
2292         default:
2293                 DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode);
2294                 return -EINVAL;
2295         }
2296
2297         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2298                          drv_mb_param, &resp, &param);
2299
2300         return rc;
2301 }
2302
2303 int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn,
2304                           struct qed_ptt *p_ptt, u32 mask_parities)
2305 {
2306         u32 resp = 0, param = 0;
2307         int rc;
2308
2309         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2310                          mask_parities, &resp, &param);
2311
2312         if (rc) {
2313                 DP_ERR(p_hwfn,
2314                        "MCP response failure for mask parities, aborting\n");
2315         } else if (resp != FW_MSG_CODE_OK) {
2316                 DP_ERR(p_hwfn,
2317                        "MCP did not acknowledge mask parity request. Old MFW?\n");
2318                 rc = -EINVAL;
2319         }
2320
2321         return rc;
2322 }
2323
2324 int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len)
2325 {
2326         u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0;
2327         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2328         u32 resp = 0, resp_param = 0;
2329         struct qed_ptt *p_ptt;
2330         int rc = 0;
2331
2332         p_ptt = qed_ptt_acquire(p_hwfn);
2333         if (!p_ptt)
2334                 return -EBUSY;
2335
2336         while (bytes_left > 0) {
2337                 bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN);
2338
2339                 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2340                                         DRV_MSG_CODE_NVM_READ_NVRAM,
2341                                         addr + offset +
2342                                         (bytes_to_copy <<
2343                                          DRV_MB_PARAM_NVM_LEN_OFFSET),
2344                                         &resp, &resp_param,
2345                                         &read_len,
2346                                         (u32 *)(p_buf + offset));
2347
2348                 if (rc || (resp != FW_MSG_CODE_NVM_OK)) {
2349                         DP_NOTICE(cdev, "MCP command rc = %d\n", rc);
2350                         break;
2351                 }
2352
2353                 /* This can be a lengthy process, and it's possible scheduler
2354                  * isn't preemptable. Sleep a bit to prevent CPU hogging.
2355                  */
2356                 if (bytes_left % 0x1000 <
2357                     (bytes_left - read_len) % 0x1000)
2358                         usleep_range(1000, 2000);
2359
2360                 offset += read_len;
2361                 bytes_left -= read_len;
2362         }
2363
2364         cdev->mcp_nvm_resp = resp;
2365         qed_ptt_release(p_hwfn, p_ptt);
2366
2367         return rc;
2368 }
2369
2370 int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf)
2371 {
2372         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2373         struct qed_ptt *p_ptt;
2374
2375         p_ptt = qed_ptt_acquire(p_hwfn);
2376         if (!p_ptt)
2377                 return -EBUSY;
2378
2379         memcpy(p_buf, &cdev->mcp_nvm_resp, sizeof(cdev->mcp_nvm_resp));
2380         qed_ptt_release(p_hwfn, p_ptt);
2381
2382         return 0;
2383 }
2384
2385 int qed_mcp_nvm_put_file_begin(struct qed_dev *cdev, u32 addr)
2386 {
2387         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2388         struct qed_ptt *p_ptt;
2389         u32 resp, param;
2390         int rc;
2391
2392         p_ptt = qed_ptt_acquire(p_hwfn);
2393         if (!p_ptt)
2394                 return -EBUSY;
2395         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, addr,
2396                          &resp, &param);
2397         cdev->mcp_nvm_resp = resp;
2398         qed_ptt_release(p_hwfn, p_ptt);
2399
2400         return rc;
2401 }
2402
2403 int qed_mcp_nvm_write(struct qed_dev *cdev,
2404                       u32 cmd, u32 addr, u8 *p_buf, u32 len)
2405 {
2406         u32 buf_idx = 0, buf_size, nvm_cmd, nvm_offset, resp = 0, param;
2407         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2408         struct qed_ptt *p_ptt;
2409         int rc = -EINVAL;
2410
2411         p_ptt = qed_ptt_acquire(p_hwfn);
2412         if (!p_ptt)
2413                 return -EBUSY;
2414
2415         switch (cmd) {
2416         case QED_PUT_FILE_DATA:
2417                 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
2418                 break;
2419         case QED_NVM_WRITE_NVRAM:
2420                 nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2421                 break;
2422         default:
2423                 DP_NOTICE(p_hwfn, "Invalid nvm write command 0x%x\n", cmd);
2424                 rc = -EINVAL;
2425                 goto out;
2426         }
2427
2428         while (buf_idx < len) {
2429                 buf_size = min_t(u32, (len - buf_idx), MCP_DRV_NVM_BUF_LEN);
2430                 nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_OFFSET) |
2431                               addr) + buf_idx;
2432                 rc = qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset,
2433                                         &resp, &param, buf_size,
2434                                         (u32 *)&p_buf[buf_idx]);
2435                 if (rc) {
2436                         DP_NOTICE(cdev, "nvm write failed, rc = %d\n", rc);
2437                         resp = FW_MSG_CODE_ERROR;
2438                         break;
2439                 }
2440
2441                 if (resp != FW_MSG_CODE_OK &&
2442                     resp != FW_MSG_CODE_NVM_OK &&
2443                     resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) {
2444                         DP_NOTICE(cdev,
2445                                   "nvm write failed, resp = 0x%08x\n", resp);
2446                         rc = -EINVAL;
2447                         break;
2448                 }
2449
2450                 /* This can be a lengthy process, and it's possible scheduler
2451                  * isn't pre-emptable. Sleep a bit to prevent CPU hogging.
2452                  */
2453                 if (buf_idx % 0x1000 > (buf_idx + buf_size) % 0x1000)
2454                         usleep_range(1000, 2000);
2455
2456                 buf_idx += buf_size;
2457         }
2458
2459         cdev->mcp_nvm_resp = resp;
2460 out:
2461         qed_ptt_release(p_hwfn, p_ptt);
2462
2463         return rc;
2464 }
2465
2466 int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2467 {
2468         u32 drv_mb_param = 0, rsp, param;
2469         int rc = 0;
2470
2471         drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
2472                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2473
2474         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2475                          drv_mb_param, &rsp, &param);
2476
2477         if (rc)
2478                 return rc;
2479
2480         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2481             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2482                 rc = -EAGAIN;
2483
2484         return rc;
2485 }
2486
2487 int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2488 {
2489         u32 drv_mb_param, rsp, param;
2490         int rc = 0;
2491
2492         drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
2493                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2494
2495         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2496                          drv_mb_param, &rsp, &param);
2497
2498         if (rc)
2499                 return rc;
2500
2501         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2502             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2503                 rc = -EAGAIN;
2504
2505         return rc;
2506 }
2507
2508 int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn,
2509                                     struct qed_ptt *p_ptt,
2510                                     u32 *num_images)
2511 {
2512         u32 drv_mb_param = 0, rsp;
2513         int rc = 0;
2514
2515         drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
2516                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2517
2518         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2519                          drv_mb_param, &rsp, num_images);
2520         if (rc)
2521                 return rc;
2522
2523         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
2524                 rc = -EINVAL;
2525
2526         return rc;
2527 }
2528
2529 int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn,
2530                                    struct qed_ptt *p_ptt,
2531                                    struct bist_nvm_image_att *p_image_att,
2532                                    u32 image_index)
2533 {
2534         u32 buf_size = 0, param, resp = 0, resp_param = 0;
2535         int rc;
2536
2537         param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
2538                 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT;
2539         param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT;
2540
2541         rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2542                                 DRV_MSG_CODE_BIST_TEST, param,
2543                                 &resp, &resp_param,
2544                                 &buf_size,
2545                                 (u32 *)p_image_att);
2546         if (rc)
2547                 return rc;
2548
2549         if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2550             (p_image_att->return_code != 1))
2551                 rc = -EINVAL;
2552
2553         return rc;
2554 }
2555
2556 int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn)
2557 {
2558         struct qed_nvm_image_info *nvm_info = &p_hwfn->nvm_info;
2559         struct qed_ptt *p_ptt;
2560         int rc;
2561         u32 i;
2562
2563         p_ptt = qed_ptt_acquire(p_hwfn);
2564         if (!p_ptt) {
2565                 DP_ERR(p_hwfn, "failed to acquire ptt\n");
2566                 return -EBUSY;
2567         }
2568
2569         /* Acquire from MFW the amount of available images */
2570         nvm_info->num_images = 0;
2571         rc = qed_mcp_bist_nvm_get_num_images(p_hwfn,
2572                                              p_ptt, &nvm_info->num_images);
2573         if (rc == -EOPNOTSUPP) {
2574                 DP_INFO(p_hwfn, "DRV_MSG_CODE_BIST_TEST is not supported\n");
2575                 goto out;
2576         } else if (rc || !nvm_info->num_images) {
2577                 DP_ERR(p_hwfn, "Failed getting number of images\n");
2578                 goto err0;
2579         }
2580
2581         nvm_info->image_att = kmalloc_array(nvm_info->num_images,
2582                                             sizeof(struct bist_nvm_image_att),
2583                                             GFP_KERNEL);
2584         if (!nvm_info->image_att) {
2585                 rc = -ENOMEM;
2586                 goto err0;
2587         }
2588
2589         /* Iterate over images and get their attributes */
2590         for (i = 0; i < nvm_info->num_images; i++) {
2591                 rc = qed_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt,
2592                                                     &nvm_info->image_att[i], i);
2593                 if (rc) {
2594                         DP_ERR(p_hwfn,
2595                                "Failed getting image index %d attributes\n", i);
2596                         goto err1;
2597                 }
2598
2599                 DP_VERBOSE(p_hwfn, QED_MSG_SP, "image index %d, size %x\n", i,
2600                            nvm_info->image_att[i].len);
2601         }
2602 out:
2603         qed_ptt_release(p_hwfn, p_ptt);
2604         return 0;
2605
2606 err1:
2607         kfree(nvm_info->image_att);
2608 err0:
2609         qed_ptt_release(p_hwfn, p_ptt);
2610         return rc;
2611 }
2612
2613 int
2614 qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn,
2615                           enum qed_nvm_images image_id,
2616                           struct qed_nvm_image_att *p_image_att)
2617 {
2618         enum nvm_image_type type;
2619         u32 i;
2620
2621         /* Translate image_id into MFW definitions */
2622         switch (image_id) {
2623         case QED_NVM_IMAGE_ISCSI_CFG:
2624                 type = NVM_TYPE_ISCSI_CFG;
2625                 break;
2626         case QED_NVM_IMAGE_FCOE_CFG:
2627                 type = NVM_TYPE_FCOE_CFG;
2628                 break;
2629         case QED_NVM_IMAGE_NVM_CFG1:
2630                 type = NVM_TYPE_NVM_CFG1;
2631                 break;
2632         case QED_NVM_IMAGE_DEFAULT_CFG:
2633                 type = NVM_TYPE_DEFAULT_CFG;
2634                 break;
2635         case QED_NVM_IMAGE_NVM_META:
2636                 type = NVM_TYPE_META;
2637                 break;
2638         default:
2639                 DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n",
2640                           image_id);
2641                 return -EINVAL;
2642         }
2643
2644         for (i = 0; i < p_hwfn->nvm_info.num_images; i++)
2645                 if (type == p_hwfn->nvm_info.image_att[i].image_type)
2646                         break;
2647         if (i == p_hwfn->nvm_info.num_images) {
2648                 DP_VERBOSE(p_hwfn, QED_MSG_STORAGE,
2649                            "Failed to find nvram image of type %08x\n",
2650                            image_id);
2651                 return -ENOENT;
2652         }
2653
2654         p_image_att->start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr;
2655         p_image_att->length = p_hwfn->nvm_info.image_att[i].len;
2656
2657         return 0;
2658 }
2659
2660 int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn,
2661                           enum qed_nvm_images image_id,
2662                           u8 *p_buffer, u32 buffer_len)
2663 {
2664         struct qed_nvm_image_att image_att;
2665         int rc;
2666
2667         memset(p_buffer, 0, buffer_len);
2668
2669         rc = qed_mcp_get_nvm_image_att(p_hwfn, image_id, &image_att);
2670         if (rc)
2671                 return rc;
2672
2673         /* Validate sizes - both the image's and the supplied buffer's */
2674         if (image_att.length <= 4) {
2675                 DP_VERBOSE(p_hwfn, QED_MSG_STORAGE,
2676                            "Image [%d] is too small - only %d bytes\n",
2677                            image_id, image_att.length);
2678                 return -EINVAL;
2679         }
2680
2681         if (image_att.length > buffer_len) {
2682                 DP_VERBOSE(p_hwfn,
2683                            QED_MSG_STORAGE,
2684                            "Image [%d] is too big - %08x bytes where only %08x are available\n",
2685                            image_id, image_att.length, buffer_len);
2686                 return -ENOMEM;
2687         }
2688
2689         return qed_mcp_nvm_read(p_hwfn->cdev, image_att.start_addr,
2690                                 p_buffer, image_att.length);
2691 }
2692
2693 static enum resource_id_enum qed_mcp_get_mfw_res_id(enum qed_resources res_id)
2694 {
2695         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2696
2697         switch (res_id) {
2698         case QED_SB:
2699                 mfw_res_id = RESOURCE_NUM_SB_E;
2700                 break;
2701         case QED_L2_QUEUE:
2702                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2703                 break;
2704         case QED_VPORT:
2705                 mfw_res_id = RESOURCE_NUM_VPORT_E;
2706                 break;
2707         case QED_RSS_ENG:
2708                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2709                 break;
2710         case QED_PQ:
2711                 mfw_res_id = RESOURCE_NUM_PQ_E;
2712                 break;
2713         case QED_RL:
2714                 mfw_res_id = RESOURCE_NUM_RL_E;
2715                 break;
2716         case QED_MAC:
2717         case QED_VLAN:
2718                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2719                 mfw_res_id = RESOURCE_VFC_FILTER_E;
2720                 break;
2721         case QED_ILT:
2722                 mfw_res_id = RESOURCE_ILT_E;
2723                 break;
2724         case QED_LL2_QUEUE:
2725                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2726                 break;
2727         case QED_RDMA_CNQ_RAM:
2728         case QED_CMDQS_CQS:
2729                 /* CNQ/CMDQS are the same resource */
2730                 mfw_res_id = RESOURCE_CQS_E;
2731                 break;
2732         case QED_RDMA_STATS_QUEUE:
2733                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2734                 break;
2735         case QED_BDQ:
2736                 mfw_res_id = RESOURCE_BDQ_E;
2737                 break;
2738         default:
2739                 break;
2740         }
2741
2742         return mfw_res_id;
2743 }
2744
2745 #define QED_RESC_ALLOC_VERSION_MAJOR    2
2746 #define QED_RESC_ALLOC_VERSION_MINOR    0
2747 #define QED_RESC_ALLOC_VERSION                               \
2748         ((QED_RESC_ALLOC_VERSION_MAJOR <<                    \
2749           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \
2750          (QED_RESC_ALLOC_VERSION_MINOR <<                    \
2751           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT))
2752
2753 struct qed_resc_alloc_in_params {
2754         u32 cmd;
2755         enum qed_resources res_id;
2756         u32 resc_max_val;
2757 };
2758
2759 struct qed_resc_alloc_out_params {
2760         u32 mcp_resp;
2761         u32 mcp_param;
2762         u32 resc_num;
2763         u32 resc_start;
2764         u32 vf_resc_num;
2765         u32 vf_resc_start;
2766         u32 flags;
2767 };
2768
2769 static int
2770 qed_mcp_resc_allocation_msg(struct qed_hwfn *p_hwfn,
2771                             struct qed_ptt *p_ptt,
2772                             struct qed_resc_alloc_in_params *p_in_params,
2773                             struct qed_resc_alloc_out_params *p_out_params)
2774 {
2775         struct qed_mcp_mb_params mb_params;
2776         struct resource_info mfw_resc_info;
2777         int rc;
2778
2779         memset(&mfw_resc_info, 0, sizeof(mfw_resc_info));
2780
2781         mfw_resc_info.res_id = qed_mcp_get_mfw_res_id(p_in_params->res_id);
2782         if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
2783                 DP_ERR(p_hwfn,
2784                        "Failed to match resource %d [%s] with the MFW resources\n",
2785                        p_in_params->res_id,
2786                        qed_hw_get_resc_name(p_in_params->res_id));
2787                 return -EINVAL;
2788         }
2789
2790         switch (p_in_params->cmd) {
2791         case DRV_MSG_SET_RESOURCE_VALUE_MSG:
2792                 mfw_resc_info.size = p_in_params->resc_max_val;
2793                 /* Fallthrough */
2794         case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
2795                 break;
2796         default:
2797                 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
2798                        p_in_params->cmd);
2799                 return -EINVAL;
2800         }
2801
2802         memset(&mb_params, 0, sizeof(mb_params));
2803         mb_params.cmd = p_in_params->cmd;
2804         mb_params.param = QED_RESC_ALLOC_VERSION;
2805         mb_params.p_data_src = &mfw_resc_info;
2806         mb_params.data_src_size = sizeof(mfw_resc_info);
2807         mb_params.p_data_dst = mb_params.p_data_src;
2808         mb_params.data_dst_size = mb_params.data_src_size;
2809
2810         DP_VERBOSE(p_hwfn,
2811                    QED_MSG_SP,
2812                    "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
2813                    p_in_params->cmd,
2814                    p_in_params->res_id,
2815                    qed_hw_get_resc_name(p_in_params->res_id),
2816                    QED_MFW_GET_FIELD(mb_params.param,
2817                                      DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
2818                    QED_MFW_GET_FIELD(mb_params.param,
2819                                      DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
2820                    p_in_params->resc_max_val);
2821
2822         rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2823         if (rc)
2824                 return rc;
2825
2826         p_out_params->mcp_resp = mb_params.mcp_resp;
2827         p_out_params->mcp_param = mb_params.mcp_param;
2828         p_out_params->resc_num = mfw_resc_info.size;
2829         p_out_params->resc_start = mfw_resc_info.offset;
2830         p_out_params->vf_resc_num = mfw_resc_info.vf_size;
2831         p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
2832         p_out_params->flags = mfw_resc_info.flags;
2833
2834         DP_VERBOSE(p_hwfn,
2835                    QED_MSG_SP,
2836                    "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
2837                    QED_MFW_GET_FIELD(p_out_params->mcp_param,
2838                                      FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
2839                    QED_MFW_GET_FIELD(p_out_params->mcp_param,
2840                                      FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
2841                    p_out_params->resc_num,
2842                    p_out_params->resc_start,
2843                    p_out_params->vf_resc_num,
2844                    p_out_params->vf_resc_start, p_out_params->flags);
2845
2846         return 0;
2847 }
2848
2849 int
2850 qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn,
2851                          struct qed_ptt *p_ptt,
2852                          enum qed_resources res_id,
2853                          u32 resc_max_val, u32 *p_mcp_resp)
2854 {
2855         struct qed_resc_alloc_out_params out_params;
2856         struct qed_resc_alloc_in_params in_params;
2857         int rc;
2858
2859         memset(&in_params, 0, sizeof(in_params));
2860         in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
2861         in_params.res_id = res_id;
2862         in_params.resc_max_val = resc_max_val;
2863         memset(&out_params, 0, sizeof(out_params));
2864         rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
2865                                          &out_params);
2866         if (rc)
2867                 return rc;
2868
2869         *p_mcp_resp = out_params.mcp_resp;
2870
2871         return 0;
2872 }
2873
2874 int
2875 qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn,
2876                       struct qed_ptt *p_ptt,
2877                       enum qed_resources res_id,
2878                       u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start)
2879 {
2880         struct qed_resc_alloc_out_params out_params;
2881         struct qed_resc_alloc_in_params in_params;
2882         int rc;
2883
2884         memset(&in_params, 0, sizeof(in_params));
2885         in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
2886         in_params.res_id = res_id;
2887         memset(&out_params, 0, sizeof(out_params));
2888         rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
2889                                          &out_params);
2890         if (rc)
2891                 return rc;
2892
2893         *p_mcp_resp = out_params.mcp_resp;
2894
2895         if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2896                 *p_resc_num = out_params.resc_num;
2897                 *p_resc_start = out_params.resc_start;
2898         }
2899
2900         return 0;
2901 }
2902
2903 int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2904 {
2905         u32 mcp_resp, mcp_param;
2906
2907         return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
2908                            &mcp_resp, &mcp_param);
2909 }
2910
2911 static int qed_mcp_resource_cmd(struct qed_hwfn *p_hwfn,
2912                                 struct qed_ptt *p_ptt,
2913                                 u32 param, u32 *p_mcp_resp, u32 *p_mcp_param)
2914 {
2915         int rc;
2916
2917         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
2918                          p_mcp_resp, p_mcp_param);
2919         if (rc)
2920                 return rc;
2921
2922         if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
2923                 DP_INFO(p_hwfn,
2924                         "The resource command is unsupported by the MFW\n");
2925                 return -EINVAL;
2926         }
2927
2928         if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
2929                 u8 opcode = QED_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
2930
2931                 DP_NOTICE(p_hwfn,
2932                           "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
2933                           param, opcode);
2934                 return -EINVAL;
2935         }
2936
2937         return rc;
2938 }
2939
2940 int
2941 __qed_mcp_resc_lock(struct qed_hwfn *p_hwfn,
2942                     struct qed_ptt *p_ptt,
2943                     struct qed_resc_lock_params *p_params)
2944 {
2945         u32 param = 0, mcp_resp, mcp_param;
2946         u8 opcode;
2947         int rc;
2948
2949         switch (p_params->timeout) {
2950         case QED_MCP_RESC_LOCK_TO_DEFAULT:
2951                 opcode = RESOURCE_OPCODE_REQ;
2952                 p_params->timeout = 0;
2953                 break;
2954         case QED_MCP_RESC_LOCK_TO_NONE:
2955                 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
2956                 p_params->timeout = 0;
2957                 break;
2958         default:
2959                 opcode = RESOURCE_OPCODE_REQ_W_AGING;
2960                 break;
2961         }
2962
2963         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
2964         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
2965         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
2966
2967         DP_VERBOSE(p_hwfn,
2968                    QED_MSG_SP,
2969                    "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
2970                    param, p_params->timeout, opcode, p_params->resource);
2971
2972         /* Attempt to acquire the resource */
2973         rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param);
2974         if (rc)
2975                 return rc;
2976
2977         /* Analyze the response */
2978         p_params->owner = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER);
2979         opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
2980
2981         DP_VERBOSE(p_hwfn,
2982                    QED_MSG_SP,
2983                    "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
2984                    mcp_param, opcode, p_params->owner);
2985
2986         switch (opcode) {
2987         case RESOURCE_OPCODE_GNT:
2988                 p_params->b_granted = true;
2989                 break;
2990         case RESOURCE_OPCODE_BUSY:
2991                 p_params->b_granted = false;
2992                 break;
2993         default:
2994                 DP_NOTICE(p_hwfn,
2995                           "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
2996                           mcp_param, opcode);
2997                 return -EINVAL;
2998         }
2999
3000         return 0;
3001 }
3002
3003 int
3004 qed_mcp_resc_lock(struct qed_hwfn *p_hwfn,
3005                   struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params)
3006 {
3007         u32 retry_cnt = 0;
3008         int rc;
3009
3010         do {
3011                 /* No need for an interval before the first iteration */
3012                 if (retry_cnt) {
3013                         if (p_params->sleep_b4_retry) {
3014                                 u16 retry_interval_in_ms =
3015                                     DIV_ROUND_UP(p_params->retry_interval,
3016                                                  1000);
3017
3018                                 msleep(retry_interval_in_ms);
3019                         } else {
3020                                 udelay(p_params->retry_interval);
3021                         }
3022                 }
3023
3024                 rc = __qed_mcp_resc_lock(p_hwfn, p_ptt, p_params);
3025                 if (rc)
3026                         return rc;
3027
3028                 if (p_params->b_granted)
3029                         break;
3030         } while (retry_cnt++ < p_params->retry_num);
3031
3032         return 0;
3033 }
3034
3035 int
3036 qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn,
3037                     struct qed_ptt *p_ptt,
3038                     struct qed_resc_unlock_params *p_params)
3039 {
3040         u32 param = 0, mcp_resp, mcp_param;
3041         u8 opcode;
3042         int rc;
3043
3044         opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
3045                                    : RESOURCE_OPCODE_RELEASE;
3046         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3047         QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3048
3049         DP_VERBOSE(p_hwfn, QED_MSG_SP,
3050                    "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
3051                    param, opcode, p_params->resource);
3052
3053         /* Attempt to release the resource */
3054         rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param);
3055         if (rc)
3056                 return rc;
3057
3058         /* Analyze the response */
3059         opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3060
3061         DP_VERBOSE(p_hwfn, QED_MSG_SP,
3062                    "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
3063                    mcp_param, opcode);
3064
3065         switch (opcode) {
3066         case RESOURCE_OPCODE_RELEASED_PREVIOUS:
3067                 DP_INFO(p_hwfn,
3068                         "Resource unlock request for an already released resource [%d]\n",
3069                         p_params->resource);
3070                 /* Fallthrough */
3071         case RESOURCE_OPCODE_RELEASED:
3072                 p_params->b_released = true;
3073                 break;
3074         case RESOURCE_OPCODE_WRONG_OWNER:
3075                 p_params->b_released = false;
3076                 break;
3077         default:
3078                 DP_NOTICE(p_hwfn,
3079                           "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
3080                           mcp_param, opcode);
3081                 return -EINVAL;
3082         }
3083
3084         return 0;
3085 }
3086
3087 void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock,
3088                                     struct qed_resc_unlock_params *p_unlock,
3089                                     enum qed_resc_lock
3090                                     resource, bool b_is_permanent)
3091 {
3092         if (p_lock) {
3093                 memset(p_lock, 0, sizeof(*p_lock));
3094
3095                 /* Permanent resources don't require aging, and there's no
3096                  * point in trying to acquire them more than once since it's
3097                  * unexpected another entity would release them.
3098                  */
3099                 if (b_is_permanent) {
3100                         p_lock->timeout = QED_MCP_RESC_LOCK_TO_NONE;
3101                 } else {
3102                         p_lock->retry_num = QED_MCP_RESC_LOCK_RETRY_CNT_DFLT;
3103                         p_lock->retry_interval =
3104                             QED_MCP_RESC_LOCK_RETRY_VAL_DFLT;
3105                         p_lock->sleep_b4_retry = true;
3106                 }
3107
3108                 p_lock->resource = resource;
3109         }
3110
3111         if (p_unlock) {
3112                 memset(p_unlock, 0, sizeof(*p_unlock));
3113                 p_unlock->resource = resource;
3114         }
3115 }
3116
3117 int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3118 {
3119         u32 mcp_resp;
3120         int rc;
3121
3122         rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
3123                          0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
3124         if (!rc)
3125                 DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_PROBE),
3126                            "MFW supported features: %08x\n",
3127                            p_hwfn->mcp_info->capabilities);
3128
3129         return rc;
3130 }
3131
3132 int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3133 {
3134         u32 mcp_resp, mcp_param, features;
3135
3136         features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE;
3137
3138         return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
3139                            features, &mcp_resp, &mcp_param);
3140 }