drivers/net/ethernet/qlogic/qed/qed_dev.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/types.h>
  34 #include <asm/byteorder.h>
  35 #include <linux/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/errno.h>
  39 #include <linux/kernel.h>
  40 #include <linux/mutex.h>
  41 #include <linux/pci.h>
  42 #include <linux/slab.h>
  43 #include <linux/string.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/qed/qed_chain.h>
  47 #include <linux/qed/qed_if.h>
  48 #include "qed.h"
  49 #include "qed_cxt.h"
  50 #include "qed_dcbx.h"
  51 #include "qed_dev_api.h"
  52 #include "qed_fcoe.h"
  53 #include "qed_hsi.h"
  54 #include "qed_hw.h"
  55 #include "qed_init_ops.h"
  56 #include "qed_int.h"
  57 #include "qed_iscsi.h"
  58 #include "qed_ll2.h"
  59 #include "qed_mcp.h"
  60 #include "qed_ooo.h"
  61 #include "qed_reg_addr.h"
  62 #include "qed_sp.h"
  63 #include "qed_sriov.h"
  64 #include "qed_vf.h"
  65 #include "qed_rdma.h"
  66
  67 static DEFINE_SPINLOCK(qm_lock);
  68
  69 /******************** Doorbell Recovery *******************/
  70 /* The doorbell recovery mechanism consists of a list of entries which represent
  71  * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
  72  * entity needs to register with the mechanism and provide the parameters
  73  * describing it's doorbell, including a location where last used doorbell data
  74  * can be found. The doorbell execute function will traverse the list and
  75  * doorbell all of the registered entries.
  76  */
  77 struct qed_db_recovery_entry {
  78         struct list_head list_entry;
  79         void __iomem *db_addr;
  80         void *db_data;
  81         enum qed_db_rec_width db_width;
  82         enum qed_db_rec_space db_space;
  83         u8 hwfn_idx;
  84 };
  85
  86 /* Display a single doorbell recovery entry */
  87 static void qed_db_recovery_dp_entry(struct qed_hwfn *p_hwfn,
  88                                      struct qed_db_recovery_entry *db_entry,
  89                                      char *action)
  90 {
  91         DP_VERBOSE(p_hwfn,
  92                    QED_MSG_SPQ,
  93                    "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
  94                    action,
  95                    db_entry,
  96                    db_entry->db_addr,
  97                    db_entry->db_data,
  98                    db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
  99                    db_entry->db_space == DB_REC_USER ? "user" : "kernel",
 100                    db_entry->hwfn_idx);
 101 }
 102
 103 /* Doorbell address sanity (address within doorbell bar range) */
 104 static bool qed_db_rec_sanity(struct qed_dev *cdev,
 105                               void __iomem *db_addr,
 106                               enum qed_db_rec_width db_width,
 107                               void *db_data)
 108 {
 109         u32 width = (db_width == DB_REC_WIDTH_32B) ? 32 : 64;
 110
 111         /* Make sure doorbell address is within the doorbell bar */
 112         if (db_addr < cdev->doorbells ||
 113             (u8 __iomem *)db_addr + width >
 114             (u8 __iomem *)cdev->doorbells + cdev->db_size) {
 115                 WARN(true,
 116                      "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
 117                      db_addr,
 118                      cdev->doorbells,
 119                      (u8 __iomem *)cdev->doorbells + cdev->db_size);
 120                 return false;
 121         }
 122
 123         /* ake sure doorbell data pointer is not null */
 124         if (!db_data) {
 125                 WARN(true, "Illegal doorbell data pointer: %p", db_data);
 126                 return false;
 127         }
 128
 129         return true;
 130 }
 131
 132 /* Find hwfn according to the doorbell address */
 133 static struct qed_hwfn *qed_db_rec_find_hwfn(struct qed_dev *cdev,
 134                                              void __iomem *db_addr)
 135 {
 136         struct qed_hwfn *p_hwfn;
 137
 138         /* In CMT doorbell bar is split down the middle between engine 0 and enigne 1 */
 139         if (cdev->num_hwfns > 1)
 140                 p_hwfn = db_addr < cdev->hwfns[1].doorbells ?
 141                     &cdev->hwfns[0] : &cdev->hwfns[1];
 142         else
 143                 p_hwfn = QED_LEADING_HWFN(cdev);
 144
 145         return p_hwfn;
 146 }
 147
 148 /* Add a new entry to the doorbell recovery mechanism */
 149 int qed_db_recovery_add(struct qed_dev *cdev,
 150                         void __iomem *db_addr,
 151                         void *db_data,
 152                         enum qed_db_rec_width db_width,
 153                         enum qed_db_rec_space db_space)
 154 {
 155         struct qed_db_recovery_entry *db_entry;
 156         struct qed_hwfn *p_hwfn;
 157
 158         /* Shortcircuit VFs, for now */
 159         if (IS_VF(cdev)) {
 160                 DP_VERBOSE(cdev,
 161                            QED_MSG_IOV, "db recovery - skipping VF doorbell\n");
 162                 return 0;
 163         }
 164
 165         /* Sanitize doorbell address */
 166         if (!qed_db_rec_sanity(cdev, db_addr, db_width, db_data))
 167                 return -EINVAL;
 168
 169         /* Obtain hwfn from doorbell address */
 170         p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr);
 171
 172         /* Create entry */
 173         db_entry = kzalloc(sizeof(*db_entry), GFP_KERNEL);
 174         if (!db_entry) {
 175                 DP_NOTICE(cdev, "Failed to allocate a db recovery entry\n");
 176                 return -ENOMEM;
 177         }
 178
 179         /* Populate entry */
 180         db_entry->db_addr = db_addr;
 181         db_entry->db_data = db_data;
 182         db_entry->db_width = db_width;
 183         db_entry->db_space = db_space;
 184         db_entry->hwfn_idx = p_hwfn->my_id;
 185
 186         /* Display */
 187         qed_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
 188
 189         /* Protect the list */
 190         spin_lock_bh(&p_hwfn->db_recovery_info.lock);
 191         list_add_tail(&db_entry->list_entry, &p_hwfn->db_recovery_info.list);
 192         spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
 193
 194         return 0;
 195 }
 196
 197 /* Remove an entry from the doorbell recovery mechanism */
 198 int qed_db_recovery_del(struct qed_dev *cdev,
 199                         void __iomem *db_addr, void *db_data)
 200 {
 201         struct qed_db_recovery_entry *db_entry = NULL;
 202         struct qed_hwfn *p_hwfn;
 203         int rc = -EINVAL;
 204
 205         /* Shortcircuit VFs, for now */
 206         if (IS_VF(cdev)) {
 207                 DP_VERBOSE(cdev,
 208                            QED_MSG_IOV, "db recovery - skipping VF doorbell\n");
 209                 return 0;
 210         }
 211
 212         /* Obtain hwfn from doorbell address */
 213         p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr);
 214
 215         /* Protect the list */
 216         spin_lock_bh(&p_hwfn->db_recovery_info.lock);
 217         list_for_each_entry(db_entry,
 218                             &p_hwfn->db_recovery_info.list, list_entry) {
 219                 /* search according to db_data addr since db_addr is not unique (roce) */
 220                 if (db_entry->db_data == db_data) {
 221                         qed_db_recovery_dp_entry(p_hwfn, db_entry, "Deleting");
 222                         list_del(&db_entry->list_entry);
 223                         rc = 0;
 224                         break;
 225                 }
 226         }
 227
 228         spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
 229
 230         if (rc == -EINVAL)
 231
 232                 DP_NOTICE(p_hwfn,
 233                           "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
 234                           db_data, db_addr);
 235         else
 236                 kfree(db_entry);
 237
 238         return rc;
 239 }
 240
 241 /* Initialize the doorbell recovery mechanism */
 242 static int qed_db_recovery_setup(struct qed_hwfn *p_hwfn)
 243 {
 244         DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Setting up db recovery\n");
 245
 246         /* Make sure db_size was set in cdev */
 247         if (!p_hwfn->cdev->db_size) {
 248                 DP_ERR(p_hwfn->cdev, "db_size not set\n");
 249                 return -EINVAL;
 250         }
 251
 252         INIT_LIST_HEAD(&p_hwfn->db_recovery_info.list);
 253         spin_lock_init(&p_hwfn->db_recovery_info.lock);
 254         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 255
 256         return 0;
 257 }
 258
 259 /* Destroy the doorbell recovery mechanism */
 260 static void qed_db_recovery_teardown(struct qed_hwfn *p_hwfn)
 261 {
 262         struct qed_db_recovery_entry *db_entry = NULL;
 263
 264         DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Tearing down db recovery\n");
 265         if (!list_empty(&p_hwfn->db_recovery_info.list)) {
 266                 DP_VERBOSE(p_hwfn,
 267                            QED_MSG_SPQ,
 268                            "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
 269                 while (!list_empty(&p_hwfn->db_recovery_info.list)) {
 270                         db_entry =
 271                             list_first_entry(&p_hwfn->db_recovery_info.list,
 272                                              struct qed_db_recovery_entry,
 273                                              list_entry);
 274                         qed_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
 275                         list_del(&db_entry->list_entry);
 276                         kfree(db_entry);
 277                 }
 278         }
 279         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 280 }
 281
 282 /* Print the content of the doorbell recovery mechanism */
 283 void qed_db_recovery_dp(struct qed_hwfn *p_hwfn)
 284 {
 285         struct qed_db_recovery_entry *db_entry = NULL;
 286
 287         DP_NOTICE(p_hwfn,
 288                   "Displaying doorbell recovery database. Counter was %d\n",
 289                   p_hwfn->db_recovery_info.db_recovery_counter);
 290
 291         /* Protect the list */
 292         spin_lock_bh(&p_hwfn->db_recovery_info.lock);
 293         list_for_each_entry(db_entry,
 294                             &p_hwfn->db_recovery_info.list, list_entry) {
 295                 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
 296         }
 297
 298         spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
 299 }
 300
 301 /* Ring the doorbell of a single doorbell recovery entry */
 302 static void qed_db_recovery_ring(struct qed_hwfn *p_hwfn,
 303                                  struct qed_db_recovery_entry *db_entry)
 304 {
 305         /* Print according to width */
 306         if (db_entry->db_width == DB_REC_WIDTH_32B) {
 307                 DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
 308                            "ringing doorbell address %p data %x\n",
 309                            db_entry->db_addr,
 310                            *(u32 *)db_entry->db_data);
 311         } else {
 312                 DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
 313                            "ringing doorbell address %p data %llx\n",
 314                            db_entry->db_addr,
 315                            *(u64 *)(db_entry->db_data));
 316         }
 317
 318         /* Sanity */
 319         if (!qed_db_rec_sanity(p_hwfn->cdev, db_entry->db_addr,
 320                                db_entry->db_width, db_entry->db_data))
 321                 return;
 322
 323         /* Flush the write combined buffer. Since there are multiple doorbelling
 324          * entities using the same address, if we don't flush, a transaction
 325          * could be lost.
 326          */
 327         wmb();
 328
 329         /* Ring the doorbell */
 330         if (db_entry->db_width == DB_REC_WIDTH_32B)
 331                 DIRECT_REG_WR(db_entry->db_addr,
 332                               *(u32 *)(db_entry->db_data));
 333         else
 334                 DIRECT_REG_WR64(db_entry->db_addr,
 335                                 *(u64 *)(db_entry->db_data));
 336
 337         /* Flush the write combined buffer. Next doorbell may come from a
 338          * different entity to the same address...
 339          */
 340         wmb();
 341 }
 342
 343 /* Traverse the doorbell recovery entry list and ring all the doorbells */
 344 void qed_db_recovery_execute(struct qed_hwfn *p_hwfn)
 345 {
 346         struct qed_db_recovery_entry *db_entry = NULL;
 347
 348         DP_NOTICE(p_hwfn, "Executing doorbell recovery. Counter was %d\n",
 349                   p_hwfn->db_recovery_info.db_recovery_counter);
 350
 351         /* Track amount of times recovery was executed */
 352         p_hwfn->db_recovery_info.db_recovery_counter++;
 353
 354         /* Protect the list */
 355         spin_lock_bh(&p_hwfn->db_recovery_info.lock);
 356         list_for_each_entry(db_entry,
 357                             &p_hwfn->db_recovery_info.list, list_entry)
 358                 qed_db_recovery_ring(p_hwfn, db_entry);
 359         spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
 360 }
 361
 362 /******************** Doorbell Recovery end ****************/
 363
 364 /********************************** NIG LLH ***********************************/
 365
 366 enum qed_llh_filter_type {
 367         QED_LLH_FILTER_TYPE_MAC,
 368         QED_LLH_FILTER_TYPE_PROTOCOL,
 369 };
 370
 371 struct qed_llh_mac_filter {
 372         u8 addr[ETH_ALEN];
 373 };
 374
 375 struct qed_llh_protocol_filter {
 376         enum qed_llh_prot_filter_type_t type;
 377         u16 source_port_or_eth_type;
 378         u16 dest_port;
 379 };
 380
 381 union qed_llh_filter {
 382         struct qed_llh_mac_filter mac;
 383         struct qed_llh_protocol_filter protocol;
 384 };
 385
 386 struct qed_llh_filter_info {
 387         bool b_enabled;
 388         u32 ref_cnt;
 389         enum qed_llh_filter_type type;
 390         union qed_llh_filter filter;
 391 };
 392
 393 struct qed_llh_info {
 394         /* Number of LLH filters banks */
 395         u8 num_ppfid;
 396
 397 #define MAX_NUM_PPFID   8
 398         u8 ppfid_array[MAX_NUM_PPFID];
 399
 400         /* Array of filters arrays:
 401          * "num_ppfid" elements of filters banks, where each is an array of
 402          * "NIG_REG_LLH_FUNC_FILTER_EN_SIZE" filters.
 403          */
 404         struct qed_llh_filter_info **pp_filters;
 405 };
 406
 407 static void qed_llh_free(struct qed_dev *cdev)
 408 {
 409         struct qed_llh_info *p_llh_info = cdev->p_llh_info;
 410         u32 i;
 411
 412         if (p_llh_info) {
 413                 if (p_llh_info->pp_filters)
 414                         for (i = 0; i < p_llh_info->num_ppfid; i++)
 415                                 kfree(p_llh_info->pp_filters[i]);
 416
 417                 kfree(p_llh_info->pp_filters);
 418         }
 419
 420         kfree(p_llh_info);
 421         cdev->p_llh_info = NULL;
 422 }
 423
 424 static int qed_llh_alloc(struct qed_dev *cdev)
 425 {
 426         struct qed_llh_info *p_llh_info;
 427         u32 size, i;
 428
 429         p_llh_info = kzalloc(sizeof(*p_llh_info), GFP_KERNEL);
 430         if (!p_llh_info)
 431                 return -ENOMEM;
 432         cdev->p_llh_info = p_llh_info;
 433
 434         for (i = 0; i < MAX_NUM_PPFID; i++) {
 435                 if (!(cdev->ppfid_bitmap & (0x1 << i)))
 436                         continue;
 437
 438                 p_llh_info->ppfid_array[p_llh_info->num_ppfid] = i;
 439                 DP_VERBOSE(cdev, QED_MSG_SP, "ppfid_array[%d] = %hhd\n",
 440                            p_llh_info->num_ppfid, i);
 441                 p_llh_info->num_ppfid++;
 442         }
 443
 444         size = p_llh_info->num_ppfid * sizeof(*p_llh_info->pp_filters);
 445         p_llh_info->pp_filters = kzalloc(size, GFP_KERNEL);
 446         if (!p_llh_info->pp_filters)
 447                 return -ENOMEM;
 448
 449         size = NIG_REG_LLH_FUNC_FILTER_EN_SIZE *
 450             sizeof(**p_llh_info->pp_filters);
 451         for (i = 0; i < p_llh_info->num_ppfid; i++) {
 452                 p_llh_info->pp_filters[i] = kzalloc(size, GFP_KERNEL);
 453                 if (!p_llh_info->pp_filters[i])
 454                         return -ENOMEM;
 455         }
 456
 457         return 0;
 458 }
 459
 460 static int qed_llh_shadow_sanity(struct qed_dev *cdev,
 461                                  u8 ppfid, u8 filter_idx, const char *action)
 462 {
 463         struct qed_llh_info *p_llh_info = cdev->p_llh_info;
 464
 465         if (ppfid >= p_llh_info->num_ppfid) {
 466                 DP_NOTICE(cdev,
 467                           "LLH shadow [%s]: using ppfid %d while only %d ppfids are available\n",
 468                           action, ppfid, p_llh_info->num_ppfid);
 469                 return -EINVAL;
 470         }
 471
 472         if (filter_idx >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
 473                 DP_NOTICE(cdev,
 474                           "LLH shadow [%s]: using filter_idx %d while only %d filters are available\n",
 475                           action, filter_idx, NIG_REG_LLH_FUNC_FILTER_EN_SIZE);
 476                 return -EINVAL;
 477         }
 478
 479         return 0;
 480 }
 481
 482 #define QED_LLH_INVALID_FILTER_IDX      0xff
 483
 484 static int
 485 qed_llh_shadow_search_filter(struct qed_dev *cdev,
 486                              u8 ppfid,
 487                              union qed_llh_filter *p_filter, u8 *p_filter_idx)
 488 {
 489         struct qed_llh_info *p_llh_info = cdev->p_llh_info;
 490         struct qed_llh_filter_info *p_filters;
 491         int rc;
 492         u8 i;
 493
 494         rc = qed_llh_shadow_sanity(cdev, ppfid, 0, "search");
 495         if (rc)
 496                 return rc;
 497
 498         *p_filter_idx = QED_LLH_INVALID_FILTER_IDX;
 499
 500         p_filters = p_llh_info->pp_filters[ppfid];
 501         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
 502                 if (!memcmp(p_filter, &p_filters[i].filter,
 503                             sizeof(*p_filter))) {
 504                         *p_filter_idx = i;
 505                         break;
 506                 }
 507         }
 508
 509         return 0;
 510 }
 511
 512 static int
 513 qed_llh_shadow_get_free_idx(struct qed_dev *cdev, u8 ppfid, u8 *p_filter_idx)
 514 {
 515         struct qed_llh_info *p_llh_info = cdev->p_llh_info;
 516         struct qed_llh_filter_info *p_filters;
 517         int rc;
 518         u8 i;
 519
 520         rc = qed_llh_shadow_sanity(cdev, ppfid, 0, "get_free_idx");
 521         if (rc)
 522                 return rc;
 523
 524         *p_filter_idx = QED_LLH_INVALID_FILTER_IDX;
 525
 526         p_filters = p_llh_info->pp_filters[ppfid];
 527         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
 528                 if (!p_filters[i].b_enabled) {
 529                         *p_filter_idx = i;
 530                         break;
 531                 }
 532         }
 533
 534         return 0;
 535 }
 536
 537 static int
 538 __qed_llh_shadow_add_filter(struct qed_dev *cdev,
 539                             u8 ppfid,
 540                             u8 filter_idx,
 541                             enum qed_llh_filter_type type,
 542                             union qed_llh_filter *p_filter, u32 *p_ref_cnt)
 543 {
 544         struct qed_llh_info *p_llh_info = cdev->p_llh_info;
 545         struct qed_llh_filter_info *p_filters;
 546         int rc;
 547
 548         rc = qed_llh_shadow_sanity(cdev, ppfid, filter_idx, "add");
 549         if (rc)
 550                 return rc;
 551
 552         p_filters = p_llh_info->pp_filters[ppfid];
 553         if (!p_filters[filter_idx].ref_cnt) {
 554                 p_filters[filter_idx].b_enabled = true;
 555                 p_filters[filter_idx].type = type;
 556                 memcpy(&p_filters[filter_idx].filter, p_filter,
 557                        sizeof(p_filters[filter_idx].filter));
 558         }
 559
 560         *p_ref_cnt = ++p_filters[filter_idx].ref_cnt;
 561
 562         return 0;
 563 }
 564
 565 static int
 566 qed_llh_shadow_add_filter(struct qed_dev *cdev,
 567                           u8 ppfid,
 568                           enum qed_llh_filter_type type,
 569                           union qed_llh_filter *p_filter,
 570                           u8 *p_filter_idx, u32 *p_ref_cnt)
 571 {
 572         int rc;
 573
 574         /* Check if the same filter already exist */
 575         rc = qed_llh_shadow_search_filter(cdev, ppfid, p_filter, p_filter_idx);
 576         if (rc)
 577                 return rc;
 578
 579         /* Find a new entry in case of a new filter */
 580         if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) {
 581                 rc = qed_llh_shadow_get_free_idx(cdev, ppfid, p_filter_idx);
 582                 if (rc)
 583                         return rc;
 584         }
 585
 586         /* No free entry was found */
 587         if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) {
 588                 DP_NOTICE(cdev,
 589                           "Failed to find an empty LLH filter to utilize [ppfid %d]\n",
 590                           ppfid);
 591                 return -EINVAL;
 592         }
 593
 594         return __qed_llh_shadow_add_filter(cdev, ppfid, *p_filter_idx, type,
 595                                            p_filter, p_ref_cnt);
 596 }
 597
 598 static int
 599 __qed_llh_shadow_remove_filter(struct qed_dev *cdev,
 600                                u8 ppfid, u8 filter_idx, u32 *p_ref_cnt)
 601 {
 602         struct qed_llh_info *p_llh_info = cdev->p_llh_info;
 603         struct qed_llh_filter_info *p_filters;
 604         int rc;
 605
 606         rc = qed_llh_shadow_sanity(cdev, ppfid, filter_idx, "remove");
 607         if (rc)
 608                 return rc;
 609
 610         p_filters = p_llh_info->pp_filters[ppfid];
 611         if (!p_filters[filter_idx].ref_cnt) {
 612                 DP_NOTICE(cdev,
 613                           "LLH shadow: trying to remove a filter with ref_cnt=0\n");
 614                 return -EINVAL;
 615         }
 616
 617         *p_ref_cnt = --p_filters[filter_idx].ref_cnt;
 618         if (!p_filters[filter_idx].ref_cnt)
 619                 memset(&p_filters[filter_idx],
 620                        0, sizeof(p_filters[filter_idx]));
 621
 622         return 0;
 623 }
 624
 625 static int
 626 qed_llh_shadow_remove_filter(struct qed_dev *cdev,
 627                              u8 ppfid,
 628                              union qed_llh_filter *p_filter,
 629                              u8 *p_filter_idx, u32 *p_ref_cnt)
 630 {
 631         int rc;
 632
 633         rc = qed_llh_shadow_search_filter(cdev, ppfid, p_filter, p_filter_idx);
 634         if (rc)
 635                 return rc;
 636
 637         /* No matching filter was found */
 638         if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) {
 639                 DP_NOTICE(cdev, "Failed to find a filter in the LLH shadow\n");
 640                 return -EINVAL;
 641         }
 642
 643         return __qed_llh_shadow_remove_filter(cdev, ppfid, *p_filter_idx,
 644                                               p_ref_cnt);
 645 }
 646
 647 static int qed_llh_abs_ppfid(struct qed_dev *cdev, u8 ppfid, u8 *p_abs_ppfid)
 648 {
 649         struct qed_llh_info *p_llh_info = cdev->p_llh_info;
 650
 651         if (ppfid >= p_llh_info->num_ppfid) {
 652                 DP_NOTICE(cdev,
 653                           "ppfid %d is not valid, available indices are 0..%hhd\n",
 654                           ppfid, p_llh_info->num_ppfid - 1);
 655                 *p_abs_ppfid = 0;
 656                 return -EINVAL;
 657         }
 658
 659         *p_abs_ppfid = p_llh_info->ppfid_array[ppfid];
 660
 661         return 0;
 662 }
 663
 664 static int
 665 qed_llh_set_engine_affin(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 666 {
 667         struct qed_dev *cdev = p_hwfn->cdev;
 668         enum qed_eng eng;
 669         u8 ppfid;
 670         int rc;
 671
 672         rc = qed_mcp_get_engine_config(p_hwfn, p_ptt);
 673         if (rc != 0 && rc != -EOPNOTSUPP) {
 674                 DP_NOTICE(p_hwfn,
 675                           "Failed to get the engine affinity configuration\n");
 676                 return rc;
 677         }
 678
 679         /* RoCE PF is bound to a single engine */
 680         if (QED_IS_ROCE_PERSONALITY(p_hwfn)) {
 681                 eng = cdev->fir_affin ? QED_ENG1 : QED_ENG0;
 682                 rc = qed_llh_set_roce_affinity(cdev, eng);
 683                 if (rc) {
 684                         DP_NOTICE(cdev,
 685                                   "Failed to set the RoCE engine affinity\n");
 686                         return rc;
 687                 }
 688
 689                 DP_VERBOSE(cdev,
 690                            QED_MSG_SP,
 691                            "LLH: Set the engine affinity of RoCE packets as %d\n",
 692                            eng);
 693         }
 694
 695         /* Storage PF is bound to a single engine while L2 PF uses both */
 696         if (QED_IS_FCOE_PERSONALITY(p_hwfn) || QED_IS_ISCSI_PERSONALITY(p_hwfn))
 697                 eng = cdev->fir_affin ? QED_ENG1 : QED_ENG0;
 698         else                    /* L2_PERSONALITY */
 699                 eng = QED_BOTH_ENG;
 700
 701         for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) {
 702                 rc = qed_llh_set_ppfid_affinity(cdev, ppfid, eng);
 703                 if (rc) {
 704                         DP_NOTICE(cdev,
 705                                   "Failed to set the engine affinity of ppfid %d\n",
 706                                   ppfid);
 707                         return rc;
 708                 }
 709         }
 710
 711         DP_VERBOSE(cdev, QED_MSG_SP,
 712                    "LLH: Set the engine affinity of non-RoCE packets as %d\n",
 713                    eng);
 714
 715         return 0;
 716 }
 717
 718 static int qed_llh_hw_init_pf(struct qed_hwfn *p_hwfn,
 719                               struct qed_ptt *p_ptt)
 720 {
 721         struct qed_dev *cdev = p_hwfn->cdev;
 722         u8 ppfid, abs_ppfid;
 723         int rc;
 724
 725         for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) {
 726                 u32 addr;
 727
 728                 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
 729                 if (rc)
 730                         return rc;
 731
 732                 addr = NIG_REG_LLH_PPFID2PFID_TBL_0 + abs_ppfid * 0x4;
 733                 qed_wr(p_hwfn, p_ptt, addr, p_hwfn->rel_pf_id);
 734         }
 735
 736         if (test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits) &&
 737             !QED_IS_FCOE_PERSONALITY(p_hwfn)) {
 738                 rc = qed_llh_add_mac_filter(cdev, 0,
 739                                             p_hwfn->hw_info.hw_mac_addr);
 740                 if (rc)
 741                         DP_NOTICE(cdev,
 742                                   "Failed to add an LLH filter with the primary MAC\n");
 743         }
 744
 745         if (QED_IS_CMT(cdev)) {
 746                 rc = qed_llh_set_engine_affin(p_hwfn, p_ptt);
 747                 if (rc)
 748                         return rc;
 749         }
 750
 751         return 0;
 752 }
 753
 754 u8 qed_llh_get_num_ppfid(struct qed_dev *cdev)
 755 {
 756         return cdev->p_llh_info->num_ppfid;
 757 }
 758
 759 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_MASK             0x3
 760 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_SHIFT            0
 761 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_MASK         0x3
 762 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_SHIFT        2
 763
 764 int qed_llh_set_ppfid_affinity(struct qed_dev *cdev, u8 ppfid, enum qed_eng eng)
 765 {
 766         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
 767         struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
 768         u32 addr, val, eng_sel;
 769         u8 abs_ppfid;
 770         int rc = 0;
 771
 772         if (!p_ptt)
 773                 return -EAGAIN;
 774
 775         if (!QED_IS_CMT(cdev))
 776                 goto out;
 777
 778         rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
 779         if (rc)
 780                 goto out;
 781
 782         switch (eng) {
 783         case QED_ENG0:
 784                 eng_sel = 0;
 785                 break;
 786         case QED_ENG1:
 787                 eng_sel = 1;
 788                 break;
 789         case QED_BOTH_ENG:
 790                 eng_sel = 2;
 791                 break;
 792         default:
 793                 DP_NOTICE(cdev, "Invalid affinity value for ppfid [%d]\n", eng);
 794                 rc = -EINVAL;
 795                 goto out;
 796         }
 797
 798         addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
 799         val = qed_rd(p_hwfn, p_ptt, addr);
 800         SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE, eng_sel);
 801         qed_wr(p_hwfn, p_ptt, addr, val);
 802
 803         /* The iWARP affinity is set as the affinity of ppfid 0 */
 804         if (!ppfid && QED_IS_IWARP_PERSONALITY(p_hwfn))
 805                 cdev->iwarp_affin = (eng == QED_ENG1) ? 1 : 0;
 806 out:
 807         qed_ptt_release(p_hwfn, p_ptt);
 808
 809         return rc;
 810 }
 811
 812 int qed_llh_set_roce_affinity(struct qed_dev *cdev, enum qed_eng eng)
 813 {
 814         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
 815         struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
 816         u32 addr, val, eng_sel;
 817         u8 ppfid, abs_ppfid;
 818         int rc = 0;
 819
 820         if (!p_ptt)
 821                 return -EAGAIN;
 822
 823         if (!QED_IS_CMT(cdev))
 824                 goto out;
 825
 826         switch (eng) {
 827         case QED_ENG0:
 828                 eng_sel = 0;
 829                 break;
 830         case QED_ENG1:
 831                 eng_sel = 1;
 832                 break;
 833         case QED_BOTH_ENG:
 834                 eng_sel = 2;
 835                 qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL,
 836                        0xf);  /* QP bit 15 */
 837                 break;
 838         default:
 839                 DP_NOTICE(cdev, "Invalid affinity value for RoCE [%d]\n", eng);
 840                 rc = -EINVAL;
 841                 goto out;
 842         }
 843
 844         for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) {
 845                 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
 846                 if (rc)
 847                         goto out;
 848
 849                 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
 850                 val = qed_rd(p_hwfn, p_ptt, addr);
 851                 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_ROCE, eng_sel);
 852                 qed_wr(p_hwfn, p_ptt, addr, val);
 853         }
 854 out:
 855         qed_ptt_release(p_hwfn, p_ptt);
 856
 857         return rc;
 858 }
 859
 860 struct qed_llh_filter_details {
 861         u64 value;
 862         u32 mode;
 863         u32 protocol_type;
 864         u32 hdr_sel;
 865         u32 enable;
 866 };
 867
 868 static int
 869 qed_llh_access_filter(struct qed_hwfn *p_hwfn,
 870                       struct qed_ptt *p_ptt,
 871                       u8 abs_ppfid,
 872                       u8 filter_idx,
 873                       struct qed_llh_filter_details *p_details)
 874 {
 875         struct qed_dmae_params params = {0};
 876         u32 addr;
 877         u8 pfid;
 878         int rc;
 879
 880         /* The NIG/LLH registers that are accessed in this function have only 16
 881          * rows which are exposed to a PF. I.e. only the 16 filters of its
 882          * default ppfid. Accessing filters of other ppfids requires pretending
 883          * to another PFs.
 884          * The calculation of PPFID->PFID in AH is based on the relative index
 885          * of a PF on its port.
 886          * For BB the pfid is actually the abs_ppfid.
 887          */
 888         if (QED_IS_BB(p_hwfn->cdev))
 889                 pfid = abs_ppfid;
 890         else
 891                 pfid = abs_ppfid * p_hwfn->cdev->num_ports_in_engine +
 892                     MFW_PORT(p_hwfn);
 893
 894         /* Filter enable - should be done first when removing a filter */
 895         if (!p_details->enable) {
 896                 qed_fid_pretend(p_hwfn, p_ptt,
 897                                 pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
 898
 899                 addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4;
 900                 qed_wr(p_hwfn, p_ptt, addr, p_details->enable);
 901
 902                 qed_fid_pretend(p_hwfn, p_ptt,
 903                                 p_hwfn->rel_pf_id <<
 904                                 PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
 905         }
 906
 907         /* Filter value */
 908         addr = NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * filter_idx * 0x4;
 909
 910         SET_FIELD(params.flags, QED_DMAE_PARAMS_DST_PF_VALID, 0x1);
 911         params.dst_pfid = pfid;
 912         rc = qed_dmae_host2grc(p_hwfn,
 913                                p_ptt,
 914                                (u64)(uintptr_t)&p_details->value,
 915                                addr, 2 /* size_in_dwords */,
 916                                &params);
 917         if (rc)
 918                 return rc;
 919
 920         qed_fid_pretend(p_hwfn, p_ptt,
 921                         pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
 922
 923         /* Filter mode */
 924         addr = NIG_REG_LLH_FUNC_FILTER_MODE + filter_idx * 0x4;
 925         qed_wr(p_hwfn, p_ptt, addr, p_details->mode);
 926
 927         /* Filter protocol type */
 928         addr = NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + filter_idx * 0x4;
 929         qed_wr(p_hwfn, p_ptt, addr, p_details->protocol_type);
 930
 931         /* Filter header select */
 932         addr = NIG_REG_LLH_FUNC_FILTER_HDR_SEL + filter_idx * 0x4;
 933         qed_wr(p_hwfn, p_ptt, addr, p_details->hdr_sel);
 934
 935         /* Filter enable - should be done last when adding a filter */
 936         if (p_details->enable) {
 937                 addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4;
 938                 qed_wr(p_hwfn, p_ptt, addr, p_details->enable);
 939         }
 940
 941         qed_fid_pretend(p_hwfn, p_ptt,
 942                         p_hwfn->rel_pf_id <<
 943                         PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
 944
 945         return 0;
 946 }
 947
 948 static int
 949 qed_llh_add_filter(struct qed_hwfn *p_hwfn,
 950                    struct qed_ptt *p_ptt,
 951                    u8 abs_ppfid,
 952                    u8 filter_idx, u8 filter_prot_type, u32 high, u32 low)
 953 {
 954         struct qed_llh_filter_details filter_details;
 955
 956         filter_details.enable = 1;
 957         filter_details.value = ((u64)high << 32) | low;
 958         filter_details.hdr_sel = 0;
 959         filter_details.protocol_type = filter_prot_type;
 960         /* Mode: 0: MAC-address classification 1: protocol classification */
 961         filter_details.mode = filter_prot_type ? 1 : 0;
 962
 963         return qed_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
 964                                      &filter_details);
 965 }
 966
 967 static int
 968 qed_llh_remove_filter(struct qed_hwfn *p_hwfn,
 969                       struct qed_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx)
 970 {
 971         struct qed_llh_filter_details filter_details = {0};
 972
 973         return qed_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
 974                                      &filter_details);
 975 }
 976
 977 int qed_llh_add_mac_filter(struct qed_dev *cdev,
 978                            u8 ppfid, u8 mac_addr[ETH_ALEN])
 979 {
 980         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
 981         struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
 982         union qed_llh_filter filter = {};
 983         u8 filter_idx, abs_ppfid = 0;
 984         u32 high, low, ref_cnt;
 985         int rc = 0;
 986
 987         if (!p_ptt)
 988                 return -EAGAIN;
 989
 990         if (!test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits))
 991                 goto out;
 992
 993         memcpy(filter.mac.addr, mac_addr, ETH_ALEN);
 994         rc = qed_llh_shadow_add_filter(cdev, ppfid,
 995                                        QED_LLH_FILTER_TYPE_MAC,
 996                                        &filter, &filter_idx, &ref_cnt);
 997         if (rc)
 998                 goto err;
 999
1000         /* Configure the LLH only in case of a new the filter */
1001         if (ref_cnt == 1) {
1002                 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1003                 if (rc)
1004                         goto err;
1005
1006                 high = mac_addr[1] | (mac_addr[0] << 8);
1007                 low = mac_addr[5] | (mac_addr[4] << 8) | (mac_addr[3] << 16) |
1008                       (mac_addr[2] << 24);
1009                 rc = qed_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1010                                         0, high, low);
1011                 if (rc)
1012                         goto err;
1013         }
1014
1015         DP_VERBOSE(cdev,
1016                    QED_MSG_SP,
1017                    "LLH: Added MAC filter [%pM] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1018                    mac_addr, ppfid, abs_ppfid, filter_idx, ref_cnt);
1019
1020         goto out;
1021
1022 err:    DP_NOTICE(cdev,
1023                   "LLH: Failed to add MAC filter [%pM] to ppfid %hhd\n",
1024                   mac_addr, ppfid);
1025 out:
1026         qed_ptt_release(p_hwfn, p_ptt);
1027
1028         return rc;
1029 }
1030
1031 static int
1032 qed_llh_protocol_filter_stringify(struct qed_dev *cdev,
1033                                   enum qed_llh_prot_filter_type_t type,
1034                                   u16 source_port_or_eth_type,
1035                                   u16 dest_port, u8 *str, size_t str_len)
1036 {
1037         switch (type) {
1038         case QED_LLH_FILTER_ETHERTYPE:
1039                 snprintf(str, str_len, "Ethertype 0x%04x",
1040                          source_port_or_eth_type);
1041                 break;
1042         case QED_LLH_FILTER_TCP_SRC_PORT:
1043                 snprintf(str, str_len, "TCP src port 0x%04x",
1044                          source_port_or_eth_type);
1045                 break;
1046         case QED_LLH_FILTER_UDP_SRC_PORT:
1047                 snprintf(str, str_len, "UDP src port 0x%04x",
1048                          source_port_or_eth_type);
1049                 break;
1050         case QED_LLH_FILTER_TCP_DEST_PORT:
1051                 snprintf(str, str_len, "TCP dst port 0x%04x", dest_port);
1052                 break;
1053         case QED_LLH_FILTER_UDP_DEST_PORT:
1054                 snprintf(str, str_len, "UDP dst port 0x%04x", dest_port);
1055                 break;
1056         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1057                 snprintf(str, str_len, "TCP src/dst ports 0x%04x/0x%04x",
1058                          source_port_or_eth_type, dest_port);
1059                 break;
1060         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1061                 snprintf(str, str_len, "UDP src/dst ports 0x%04x/0x%04x",
1062                          source_port_or_eth_type, dest_port);
1063                 break;
1064         default:
1065                 DP_NOTICE(cdev,
1066                           "Non valid LLH protocol filter type %d\n", type);
1067                 return -EINVAL;
1068         }
1069
1070         return 0;
1071 }
1072
1073 static int
1074 qed_llh_protocol_filter_to_hilo(struct qed_dev *cdev,
1075                                 enum qed_llh_prot_filter_type_t type,
1076                                 u16 source_port_or_eth_type,
1077                                 u16 dest_port, u32 *p_high, u32 *p_low)
1078 {
1079         *p_high = 0;
1080         *p_low = 0;
1081
1082         switch (type) {
1083         case QED_LLH_FILTER_ETHERTYPE:
1084                 *p_high = source_port_or_eth_type;
1085                 break;
1086         case QED_LLH_FILTER_TCP_SRC_PORT:
1087         case QED_LLH_FILTER_UDP_SRC_PORT:
1088                 *p_low = source_port_or_eth_type << 16;
1089                 break;
1090         case QED_LLH_FILTER_TCP_DEST_PORT:
1091         case QED_LLH_FILTER_UDP_DEST_PORT:
1092                 *p_low = dest_port;
1093                 break;
1094         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1095         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1096                 *p_low = (source_port_or_eth_type << 16) | dest_port;
1097                 break;
1098         default:
1099                 DP_NOTICE(cdev,
1100                           "Non valid LLH protocol filter type %d\n", type);
1101                 return -EINVAL;
1102         }
1103
1104         return 0;
1105 }
1106
1107 int
1108 qed_llh_add_protocol_filter(struct qed_dev *cdev,
1109                             u8 ppfid,
1110                             enum qed_llh_prot_filter_type_t type,
1111                             u16 source_port_or_eth_type, u16 dest_port)
1112 {
1113         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1114         struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
1115         u8 filter_idx, abs_ppfid, str[32], type_bitmap;
1116         union qed_llh_filter filter = {};
1117         u32 high, low, ref_cnt;
1118         int rc = 0;
1119
1120         if (!p_ptt)
1121                 return -EAGAIN;
1122
1123         if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits))
1124                 goto out;
1125
1126         rc = qed_llh_protocol_filter_stringify(cdev, type,
1127                                                source_port_or_eth_type,
1128                                                dest_port, str, sizeof(str));
1129         if (rc)
1130                 goto err;
1131
1132         filter.protocol.type = type;
1133         filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1134         filter.protocol.dest_port = dest_port;
1135         rc = qed_llh_shadow_add_filter(cdev,
1136                                        ppfid,
1137                                        QED_LLH_FILTER_TYPE_PROTOCOL,
1138                                        &filter, &filter_idx, &ref_cnt);
1139         if (rc)
1140                 goto err;
1141
1142         rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1143         if (rc)
1144                 goto err;
1145
1146         /* Configure the LLH only in case of a new the filter */
1147         if (ref_cnt == 1) {
1148                 rc = qed_llh_protocol_filter_to_hilo(cdev, type,
1149                                                      source_port_or_eth_type,
1150                                                      dest_port, &high, &low);
1151                 if (rc)
1152                         goto err;
1153
1154                 type_bitmap = 0x1 << type;
1155                 rc = qed_llh_add_filter(p_hwfn, p_ptt, abs_ppfid,
1156                                         filter_idx, type_bitmap, high, low);
1157                 if (rc)
1158                         goto err;
1159         }
1160
1161         DP_VERBOSE(cdev,
1162                    QED_MSG_SP,
1163                    "LLH: Added protocol filter [%s] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1164                    str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1165
1166         goto out;
1167
1168 err:    DP_NOTICE(p_hwfn,
1169                   "LLH: Failed to add protocol filter [%s] to ppfid %hhd\n",
1170                   str, ppfid);
1171 out:
1172         qed_ptt_release(p_hwfn, p_ptt);
1173
1174         return rc;
1175 }
1176
1177 void qed_llh_remove_mac_filter(struct qed_dev *cdev,
1178                                u8 ppfid, u8 mac_addr[ETH_ALEN])
1179 {
1180         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1181         struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
1182         union qed_llh_filter filter = {};
1183         u8 filter_idx, abs_ppfid;
1184         int rc = 0;
1185         u32 ref_cnt;
1186
1187         if (!p_ptt)
1188                 return;
1189
1190         if (!test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits))
1191                 goto out;
1192
1193         ether_addr_copy(filter.mac.addr, mac_addr);
1194         rc = qed_llh_shadow_remove_filter(cdev, ppfid, &filter, &filter_idx,
1195                                           &ref_cnt);
1196         if (rc)
1197                 goto err;
1198
1199         rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1200         if (rc)
1201                 goto err;
1202
1203         /* Remove from the LLH in case the filter is not in use */
1204         if (!ref_cnt) {
1205                 rc = qed_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1206                                            filter_idx);
1207                 if (rc)
1208                         goto err;
1209         }
1210
1211         DP_VERBOSE(cdev,
1212                    QED_MSG_SP,
1213                    "LLH: Removed MAC filter [%pM] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1214                    mac_addr, ppfid, abs_ppfid, filter_idx, ref_cnt);
1215
1216         goto out;
1217
1218 err:    DP_NOTICE(cdev,
1219                   "LLH: Failed to remove MAC filter [%pM] from ppfid %hhd\n",
1220                   mac_addr, ppfid);
1221 out:
1222         qed_ptt_release(p_hwfn, p_ptt);
1223 }
1224
1225 void qed_llh_remove_protocol_filter(struct qed_dev *cdev,
1226                                     u8 ppfid,
1227                                     enum qed_llh_prot_filter_type_t type,
1228                                     u16 source_port_or_eth_type, u16 dest_port)
1229 {
1230         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1231         struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
1232         u8 filter_idx, abs_ppfid, str[32];
1233         union qed_llh_filter filter = {};
1234         int rc = 0;
1235         u32 ref_cnt;
1236
1237         if (!p_ptt)
1238                 return;
1239
1240         if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits))
1241                 goto out;
1242
1243         rc = qed_llh_protocol_filter_stringify(cdev, type,
1244                                                source_port_or_eth_type,
1245                                                dest_port, str, sizeof(str));
1246         if (rc)
1247                 goto err;
1248
1249         filter.protocol.type = type;
1250         filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1251         filter.protocol.dest_port = dest_port;
1252         rc = qed_llh_shadow_remove_filter(cdev, ppfid, &filter, &filter_idx,
1253                                           &ref_cnt);
1254         if (rc)
1255                 goto err;
1256
1257         rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1258         if (rc)
1259                 goto err;
1260
1261         /* Remove from the LLH in case the filter is not in use */
1262         if (!ref_cnt) {
1263                 rc = qed_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1264                                            filter_idx);
1265                 if (rc)
1266                         goto err;
1267         }
1268
1269         DP_VERBOSE(cdev,
1270                    QED_MSG_SP,
1271                    "LLH: Removed protocol filter [%s] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1272                    str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1273
1274         goto out;
1275
1276 err:    DP_NOTICE(cdev,
1277                   "LLH: Failed to remove protocol filter [%s] from ppfid %hhd\n",
1278                   str, ppfid);
1279 out:
1280         qed_ptt_release(p_hwfn, p_ptt);
1281 }
1282
1283 /******************************* NIG LLH - End ********************************/
1284
1285 #define QED_MIN_DPIS            (4)
1286 #define QED_MIN_PWM_REGION      (QED_WID_SIZE * QED_MIN_DPIS)
1287
1288 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
1289                            struct qed_ptt *p_ptt, enum BAR_ID bar_id)
1290 {
1291         u32 bar_reg = (bar_id == BAR_ID_0 ?
1292                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
1293         u32 val;
1294
1295         if (IS_VF(p_hwfn->cdev))
1296                 return qed_vf_hw_bar_size(p_hwfn, bar_id);
1297
1298         val = qed_rd(p_hwfn, p_ptt, bar_reg);
1299         if (val)
1300                 return 1 << (val + 15);
1301
1302         /* Old MFW initialized above registered only conditionally */
1303         if (p_hwfn->cdev->num_hwfns > 1) {
1304                 DP_INFO(p_hwfn,
1305                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
1306                         return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
1307         } else {
1308                 DP_INFO(p_hwfn,
1309                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
1310                         return 512 * 1024;
1311         }
1312 }
1313
1314 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
1315 {
1316         u32 i;
1317
1318         cdev->dp_level = dp_level;
1319         cdev->dp_module = dp_module;
1320         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1321                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1322
1323                 p_hwfn->dp_level = dp_level;
1324                 p_hwfn->dp_module = dp_module;
1325         }
1326 }
1327
1328 void qed_init_struct(struct qed_dev *cdev)
1329 {
1330         u8 i;
1331
1332         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1333                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1334
1335                 p_hwfn->cdev = cdev;
1336                 p_hwfn->my_id = i;
1337                 p_hwfn->b_active = false;
1338
1339                 mutex_init(&p_hwfn->dmae_info.mutex);
1340         }
1341
1342         /* hwfn 0 is always active */
1343         cdev->hwfns[0].b_active = true;
1344
1345         /* set the default cache alignment to 128 */
1346         cdev->cache_shift = 7;
1347 }
1348
1349 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
1350 {
1351         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1352
1353         kfree(qm_info->qm_pq_params);
1354         qm_info->qm_pq_params = NULL;
1355         kfree(qm_info->qm_vport_params);
1356         qm_info->qm_vport_params = NULL;
1357         kfree(qm_info->qm_port_params);
1358         qm_info->qm_port_params = NULL;
1359         kfree(qm_info->wfq_data);
1360         qm_info->wfq_data = NULL;
1361 }
1362
1363 static void qed_dbg_user_data_free(struct qed_hwfn *p_hwfn)
1364 {
1365         kfree(p_hwfn->dbg_user_info);
1366         p_hwfn->dbg_user_info = NULL;
1367 }
1368
1369 void qed_resc_free(struct qed_dev *cdev)
1370 {
1371         struct qed_rdma_info *rdma_info;
1372         struct qed_hwfn *p_hwfn;
1373         int i;
1374
1375         if (IS_VF(cdev)) {
1376                 for_each_hwfn(cdev, i)
1377                         qed_l2_free(&cdev->hwfns[i]);
1378                 return;
1379         }
1380
1381         kfree(cdev->fw_data);
1382         cdev->fw_data = NULL;
1383
1384         kfree(cdev->reset_stats);
1385         cdev->reset_stats = NULL;
1386
1387         qed_llh_free(cdev);
1388
1389         for_each_hwfn(cdev, i) {
1390                 p_hwfn = cdev->hwfns + i;
1391                 rdma_info = p_hwfn->p_rdma_info;
1392
1393                 qed_cxt_mngr_free(p_hwfn);
1394                 qed_qm_info_free(p_hwfn);
1395                 qed_spq_free(p_hwfn);
1396                 qed_eq_free(p_hwfn);
1397                 qed_consq_free(p_hwfn);
1398                 qed_int_free(p_hwfn);
1399 #ifdef CONFIG_QED_LL2
1400                 qed_ll2_free(p_hwfn);
1401 #endif
1402                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
1403                         qed_fcoe_free(p_hwfn);
1404
1405                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1406                         qed_iscsi_free(p_hwfn);
1407                         qed_ooo_free(p_hwfn);
1408                 }
1409
1410                 if (QED_IS_RDMA_PERSONALITY(p_hwfn) && rdma_info) {
1411                         qed_spq_unregister_async_cb(p_hwfn, rdma_info->proto);
1412                         qed_rdma_info_free(p_hwfn);
1413                 }
1414
1415                 qed_iov_free(p_hwfn);
1416                 qed_l2_free(p_hwfn);
1417                 qed_dmae_info_free(p_hwfn);
1418                 qed_dcbx_info_free(p_hwfn);
1419                 qed_dbg_user_data_free(p_hwfn);
1420                 qed_fw_overlay_mem_free(p_hwfn, p_hwfn->fw_overlay_mem);
1421
1422                 /* Destroy doorbell recovery mechanism */
1423                 qed_db_recovery_teardown(p_hwfn);
1424         }
1425 }
1426
1427 /******************** QM initialization *******************/
1428 #define ACTIVE_TCS_BMAP 0x9f
1429 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
1430
1431 /* determines the physical queue flags for a given PF. */
1432 static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn)
1433 {
1434         u32 flags;
1435
1436         /* common flags */
1437         flags = PQ_FLAGS_LB;
1438
1439         /* feature flags */
1440         if (IS_QED_SRIOV(p_hwfn->cdev))
1441                 flags |= PQ_FLAGS_VFS;
1442
1443         /* protocol flags */
1444         switch (p_hwfn->hw_info.personality) {
1445         case QED_PCI_ETH:
1446                 flags |= PQ_FLAGS_MCOS;
1447                 break;
1448         case QED_PCI_FCOE:
1449                 flags |= PQ_FLAGS_OFLD;
1450                 break;
1451         case QED_PCI_ISCSI:
1452                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
1453                 break;
1454         case QED_PCI_ETH_ROCE:
1455                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
1456                 if (IS_QED_MULTI_TC_ROCE(p_hwfn))
1457                         flags |= PQ_FLAGS_MTC;
1458                 break;
1459         case QED_PCI_ETH_IWARP:
1460                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
1461                     PQ_FLAGS_OFLD;
1462                 break;
1463         default:
1464                 DP_ERR(p_hwfn,
1465                        "unknown personality %d\n", p_hwfn->hw_info.personality);
1466                 return 0;
1467         }
1468
1469         return flags;
1470 }
1471
1472 /* Getters for resource amounts necessary for qm initialization */
1473 static u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn)
1474 {
1475         return p_hwfn->hw_info.num_hw_tc;
1476 }
1477
1478 static u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn)
1479 {
1480         return IS_QED_SRIOV(p_hwfn->cdev) ?
1481                p_hwfn->cdev->p_iov_info->total_vfs : 0;
1482 }
1483
1484 static u8 qed_init_qm_get_num_mtc_tcs(struct qed_hwfn *p_hwfn)
1485 {
1486         u32 pq_flags = qed_get_pq_flags(p_hwfn);
1487
1488         if (!(PQ_FLAGS_MTC & pq_flags))
1489                 return 1;
1490
1491         return qed_init_qm_get_num_tcs(p_hwfn);
1492 }
1493
1494 #define NUM_DEFAULT_RLS 1
1495
1496 static u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
1497 {
1498         u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
1499
1500         /* num RLs can't exceed resource amount of rls or vports */
1501         num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
1502                                  RESC_NUM(p_hwfn, QED_VPORT));
1503
1504         /* Make sure after we reserve there's something left */
1505         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
1506                 return 0;
1507
1508         /* subtract rls necessary for VFs and one default one for the PF */
1509         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
1510
1511         return num_pf_rls;
1512 }
1513
1514 static u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn)
1515 {
1516         u32 pq_flags = qed_get_pq_flags(p_hwfn);
1517
1518         /* all pqs share the same vport, except for vfs and pf_rl pqs */
1519         return (!!(PQ_FLAGS_RLS & pq_flags)) *
1520                qed_init_qm_get_num_pf_rls(p_hwfn) +
1521                (!!(PQ_FLAGS_VFS & pq_flags)) *
1522                qed_init_qm_get_num_vfs(p_hwfn) + 1;
1523 }
1524
1525 /* calc amount of PQs according to the requested flags */
1526 static u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn)
1527 {
1528         u32 pq_flags = qed_get_pq_flags(p_hwfn);
1529
1530         return (!!(PQ_FLAGS_RLS & pq_flags)) *
1531                qed_init_qm_get_num_pf_rls(p_hwfn) +
1532                (!!(PQ_FLAGS_MCOS & pq_flags)) *
1533                qed_init_qm_get_num_tcs(p_hwfn) +
1534                (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) +
1535                (!!(PQ_FLAGS_ACK & pq_flags)) +
1536                (!!(PQ_FLAGS_OFLD & pq_flags)) *
1537                qed_init_qm_get_num_mtc_tcs(p_hwfn) +
1538                (!!(PQ_FLAGS_LLT & pq_flags)) *
1539                qed_init_qm_get_num_mtc_tcs(p_hwfn) +
1540                (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn);
1541 }
1542
1543 /* initialize the top level QM params */
1544 static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
1545 {
1546         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1547         bool four_port;
1548
1549         /* pq and vport bases for this PF */
1550         qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
1551         qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
1552
1553         /* rate limiting and weighted fair queueing are always enabled */
1554         qm_info->vport_rl_en = true;
1555         qm_info->vport_wfq_en = true;
1556
1557         /* TC config is different for AH 4 port */
1558         four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2;
1559
1560         /* in AH 4 port we have fewer TCs per port */
1561         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
1562                                                      NUM_OF_PHYS_TCS;
1563
1564         /* unless MFW indicated otherwise, ooo_tc == 3 for
1565          * AH 4-port and 4 otherwise.
1566          */
1567         if (!qm_info->ooo_tc)
1568                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
1569                                               DCBX_TCP_OOO_TC;
1570 }
1571
1572 /* initialize qm vport params */
1573 static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn)
1574 {
1575         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1576         u8 i;
1577
1578         /* all vports participate in weighted fair queueing */
1579         for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++)
1580                 qm_info->qm_vport_params[i].wfq = 1;
1581 }
1582
1583 /* initialize qm port params */
1584 static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
1585 {
1586         /* Initialize qm port parameters */
1587         u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine;
1588         struct qed_dev *cdev = p_hwfn->cdev;
1589
1590         /* indicate how ooo and high pri traffic is dealt with */
1591         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
1592                           ACTIVE_TCS_BMAP_4PORT_K2 :
1593                           ACTIVE_TCS_BMAP;
1594
1595         for (i = 0; i < num_ports; i++) {
1596                 struct init_qm_port_params *p_qm_port =
1597                     &p_hwfn->qm_info.qm_port_params[i];
1598                 u16 pbf_max_cmd_lines;
1599
1600                 p_qm_port->active = 1;
1601                 p_qm_port->active_phys_tcs = active_phys_tcs;
1602                 pbf_max_cmd_lines = (u16)NUM_OF_PBF_CMD_LINES(cdev);
1603                 p_qm_port->num_pbf_cmd_lines = pbf_max_cmd_lines / num_ports;
1604                 p_qm_port->num_btb_blocks = NUM_OF_BTB_BLOCKS(cdev) / num_ports;
1605         }
1606 }
1607
1608 /* Reset the params which must be reset for qm init. QM init may be called as
1609  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
1610  * params may be affected by the init but would simply recalculate to the same
1611  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
1612  * affected as these amounts stay the same.
1613  */
1614 static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn)
1615 {
1616         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1617
1618         qm_info->num_pqs = 0;
1619         qm_info->num_vports = 0;
1620         qm_info->num_pf_rls = 0;
1621         qm_info->num_vf_pqs = 0;
1622         qm_info->first_vf_pq = 0;
1623         qm_info->first_mcos_pq = 0;
1624         qm_info->first_rl_pq = 0;
1625 }
1626
1627 static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
1628 {
1629         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1630
1631         qm_info->num_vports++;
1632
1633         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
1634                 DP_ERR(p_hwfn,
1635                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
1636                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
1637 }
1638
1639 /* initialize a single pq and manage qm_info resources accounting.
1640  * The pq_init_flags param determines whether the PQ is rate limited
1641  * (for VF or PF) and whether a new vport is allocated to the pq or not
1642  * (i.e. vport will be shared).
1643  */
1644
1645 /* flags for pq init */
1646 #define PQ_INIT_SHARE_VPORT     (1 << 0)
1647 #define PQ_INIT_PF_RL           (1 << 1)
1648 #define PQ_INIT_VF_RL           (1 << 2)
1649
1650 /* defines for pq init */
1651 #define PQ_INIT_DEFAULT_WRR_GROUP       1
1652 #define PQ_INIT_DEFAULT_TC              0
1653
1654 void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc)
1655 {
1656         p_info->offload_tc = tc;
1657         p_info->offload_tc_set = true;
1658 }
1659
1660 static bool qed_is_offload_tc_set(struct qed_hwfn *p_hwfn)
1661 {
1662         return p_hwfn->hw_info.offload_tc_set;
1663 }
1664
1665 static u32 qed_get_offload_tc(struct qed_hwfn *p_hwfn)
1666 {
1667         if (qed_is_offload_tc_set(p_hwfn))
1668                 return p_hwfn->hw_info.offload_tc;
1669
1670         return PQ_INIT_DEFAULT_TC;
1671 }
1672
1673 static void qed_init_qm_pq(struct qed_hwfn *p_hwfn,
1674                            struct qed_qm_info *qm_info,
1675                            u8 tc, u32 pq_init_flags)
1676 {
1677         u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn);
1678
1679         if (pq_idx > max_pq)
1680                 DP_ERR(p_hwfn,
1681                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
1682
1683         /* init pq params */
1684         qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
1685         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
1686             qm_info->num_vports;
1687         qm_info->qm_pq_params[pq_idx].tc_id = tc;
1688         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
1689         qm_info->qm_pq_params[pq_idx].rl_valid =
1690             (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
1691
1692         /* qm params accounting */
1693         qm_info->num_pqs++;
1694         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
1695                 qm_info->num_vports++;
1696
1697         if (pq_init_flags & PQ_INIT_PF_RL)
1698                 qm_info->num_pf_rls++;
1699
1700         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
1701                 DP_ERR(p_hwfn,
1702                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
1703                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
1704
1705         if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn))
1706                 DP_ERR(p_hwfn,
1707                        "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n",
1708                        qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn));
1709 }
1710
1711 /* get pq index according to PQ_FLAGS */
1712 static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn,
1713                                            unsigned long pq_flags)
1714 {
1715         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1716
1717         /* Can't have multiple flags set here */
1718         if (bitmap_weight(&pq_flags,
1719                           sizeof(pq_flags) * BITS_PER_BYTE) > 1) {
1720                 DP_ERR(p_hwfn, "requested multiple pq flags 0x%lx\n", pq_flags);
1721                 goto err;
1722         }
1723
1724         if (!(qed_get_pq_flags(p_hwfn) & pq_flags)) {
1725                 DP_ERR(p_hwfn, "pq flag 0x%lx is not set\n", pq_flags);
1726                 goto err;
1727         }
1728
1729         switch (pq_flags) {
1730         case PQ_FLAGS_RLS:
1731                 return &qm_info->first_rl_pq;
1732         case PQ_FLAGS_MCOS:
1733                 return &qm_info->first_mcos_pq;
1734         case PQ_FLAGS_LB:
1735                 return &qm_info->pure_lb_pq;
1736         case PQ_FLAGS_OOO:
1737                 return &qm_info->ooo_pq;
1738         case PQ_FLAGS_ACK:
1739                 return &qm_info->pure_ack_pq;
1740         case PQ_FLAGS_OFLD:
1741                 return &qm_info->first_ofld_pq;
1742         case PQ_FLAGS_LLT:
1743                 return &qm_info->first_llt_pq;
1744         case PQ_FLAGS_VFS:
1745                 return &qm_info->first_vf_pq;
1746         default:
1747                 goto err;
1748         }
1749
1750 err:
1751         return &qm_info->start_pq;
1752 }
1753
1754 /* save pq index in qm info */
1755 static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn,
1756                                 u32 pq_flags, u16 pq_val)
1757 {
1758         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
1759
1760         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
1761 }
1762
1763 /* get tx pq index, with the PQ TX base already set (ready for context init) */
1764 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags)
1765 {
1766         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
1767
1768         return *base_pq_idx + CM_TX_PQ_BASE;
1769 }
1770
1771 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc)
1772 {
1773         u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn);
1774
1775         if (max_tc == 0) {
1776                 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
1777                        PQ_FLAGS_MCOS);
1778                 return p_hwfn->qm_info.start_pq;
1779         }
1780
1781         if (tc > max_tc)
1782                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
1783
1784         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc);
1785 }
1786
1787 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf)
1788 {
1789         u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn);
1790
1791         if (max_vf == 0) {
1792                 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
1793                        PQ_FLAGS_VFS);
1794                 return p_hwfn->qm_info.start_pq;
1795         }
1796
1797         if (vf > max_vf)
1798                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
1799
1800         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf);
1801 }
1802
1803 u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc)
1804 {
1805         u16 first_ofld_pq, pq_offset;
1806
1807         first_ofld_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD);
1808         pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
1809                     tc : PQ_INIT_DEFAULT_TC;
1810
1811         return first_ofld_pq + pq_offset;
1812 }
1813
1814 u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc)
1815 {
1816         u16 first_llt_pq, pq_offset;
1817
1818         first_llt_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LLT);
1819         pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
1820                     tc : PQ_INIT_DEFAULT_TC;
1821
1822         return first_llt_pq + pq_offset;
1823 }
1824
1825 /* Functions for creating specific types of pqs */
1826 static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn)
1827 {
1828         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1829
1830         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
1831                 return;
1832
1833         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
1834         qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
1835 }
1836
1837 static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn)
1838 {
1839         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1840
1841         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
1842                 return;
1843
1844         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
1845         qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
1846 }
1847
1848 static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn)
1849 {
1850         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1851
1852         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
1853                 return;
1854
1855         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
1856         qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
1857                        PQ_INIT_SHARE_VPORT);
1858 }
1859
1860 static void qed_init_qm_mtc_pqs(struct qed_hwfn *p_hwfn)
1861 {
1862         u8 num_tcs = qed_init_qm_get_num_mtc_tcs(p_hwfn);
1863         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1864         u8 tc;
1865
1866         /* override pq's TC if offload TC is set */
1867         for (tc = 0; tc < num_tcs; tc++)
1868                 qed_init_qm_pq(p_hwfn, qm_info,
1869                                qed_is_offload_tc_set(p_hwfn) ?
1870                                p_hwfn->hw_info.offload_tc : tc,
1871                                PQ_INIT_SHARE_VPORT);
1872 }
1873
1874 static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn)
1875 {
1876         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1877
1878         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
1879                 return;
1880
1881         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
1882         qed_init_qm_mtc_pqs(p_hwfn);
1883 }
1884
1885 static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn)
1886 {
1887         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1888
1889         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
1890                 return;
1891
1892         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
1893         qed_init_qm_mtc_pqs(p_hwfn);
1894 }
1895
1896 static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn)
1897 {
1898         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1899         u8 tc_idx;
1900
1901         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
1902                 return;
1903
1904         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
1905         for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++)
1906                 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
1907 }
1908
1909 static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn)
1910 {
1911         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1912         u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
1913
1914         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
1915                 return;
1916
1917         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
1918         qm_info->num_vf_pqs = num_vfs;
1919         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
1920                 qed_init_qm_pq(p_hwfn,
1921                                qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
1922 }
1923
1924 static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn)
1925 {
1926         u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn);
1927         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1928
1929         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
1930                 return;
1931
1932         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
1933         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
1934                 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
1935                                PQ_INIT_PF_RL);
1936 }
1937
1938 static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn)
1939 {
1940         /* rate limited pqs, must come first (FW assumption) */
1941         qed_init_qm_rl_pqs(p_hwfn);
1942
1943         /* pqs for multi cos */
1944         qed_init_qm_mcos_pqs(p_hwfn);
1945
1946         /* pure loopback pq */
1947         qed_init_qm_lb_pq(p_hwfn);
1948
1949         /* out of order pq */
1950         qed_init_qm_ooo_pq(p_hwfn);
1951
1952         /* pure ack pq */
1953         qed_init_qm_pure_ack_pq(p_hwfn);
1954
1955         /* pq for offloaded protocol */
1956         qed_init_qm_offload_pq(p_hwfn);
1957
1958         /* low latency pq */
1959         qed_init_qm_low_latency_pq(p_hwfn);
1960
1961         /* done sharing vports */
1962         qed_init_qm_advance_vport(p_hwfn);
1963
1964         /* pqs for vfs */
1965         qed_init_qm_vf_pqs(p_hwfn);
1966 }
1967
1968 /* compare values of getters against resources amounts */
1969 static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn)
1970 {
1971         if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) {
1972                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
1973                 return -EINVAL;
1974         }
1975
1976         if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
1977                 return 0;
1978
1979         if (QED_IS_ROCE_PERSONALITY(p_hwfn)) {
1980                 p_hwfn->hw_info.multi_tc_roce_en = false;
1981                 DP_NOTICE(p_hwfn,
1982                           "multi-tc roce was disabled to reduce requested amount of pqs\n");
1983                 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
1984                         return 0;
1985         }
1986
1987         DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
1988         return -EINVAL;
1989 }
1990
1991 static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn)
1992 {
1993         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1994         struct init_qm_vport_params *vport;
1995         struct init_qm_port_params *port;
1996         struct init_qm_pq_params *pq;
1997         int i, tc;
1998
1999         /* top level params */
2000         DP_VERBOSE(p_hwfn,
2001                    NETIF_MSG_HW,
2002                    "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, llt_pq %d, pure_ack_pq %d\n",
2003                    qm_info->start_pq,
2004                    qm_info->start_vport,
2005                    qm_info->pure_lb_pq,
2006                    qm_info->first_ofld_pq,
2007                    qm_info->first_llt_pq,
2008                    qm_info->pure_ack_pq);
2009         DP_VERBOSE(p_hwfn,
2010                    NETIF_MSG_HW,
2011                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
2012                    qm_info->ooo_pq,
2013                    qm_info->first_vf_pq,
2014                    qm_info->num_pqs,
2015                    qm_info->num_vf_pqs,
2016                    qm_info->num_vports, qm_info->max_phys_tcs_per_port);
2017         DP_VERBOSE(p_hwfn,
2018                    NETIF_MSG_HW,
2019                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
2020                    qm_info->pf_rl_en,
2021                    qm_info->pf_wfq_en,
2022                    qm_info->vport_rl_en,
2023                    qm_info->vport_wfq_en,
2024                    qm_info->pf_wfq,
2025                    qm_info->pf_rl,
2026                    qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn));
2027
2028         /* port table */
2029         for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) {
2030                 port = &(qm_info->qm_port_params[i]);
2031                 DP_VERBOSE(p_hwfn,
2032                            NETIF_MSG_HW,
2033                            "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
2034                            i,
2035                            port->active,
2036                            port->active_phys_tcs,
2037                            port->num_pbf_cmd_lines,
2038                            port->num_btb_blocks, port->reserved);
2039         }
2040
2041         /* vport table */
2042         for (i = 0; i < qm_info->num_vports; i++) {
2043                 vport = &(qm_info->qm_vport_params[i]);
2044                 DP_VERBOSE(p_hwfn,
2045                            NETIF_MSG_HW,
2046                            "vport idx %d, wfq %d, first_tx_pq_id [ ",
2047                            qm_info->start_vport + i, vport->wfq);
2048                 for (tc = 0; tc < NUM_OF_TCS; tc++)
2049                         DP_VERBOSE(p_hwfn,
2050                                    NETIF_MSG_HW,
2051                                    "%d ", vport->first_tx_pq_id[tc]);
2052                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n");
2053         }
2054
2055         /* pq table */
2056         for (i = 0; i < qm_info->num_pqs; i++) {
2057                 pq = &(qm_info->qm_pq_params[i]);
2058                 DP_VERBOSE(p_hwfn,
2059                            NETIF_MSG_HW,
2060                            "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d rl_id %d\n",
2061                            qm_info->start_pq + i,
2062                            pq->port_id,
2063                            pq->vport_id,
2064                            pq->tc_id, pq->wrr_group, pq->rl_valid, pq->rl_id);
2065         }
2066 }
2067
2068 static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
2069 {
2070         /* reset params required for init run */
2071         qed_init_qm_reset_params(p_hwfn);
2072
2073         /* init QM top level params */
2074         qed_init_qm_params(p_hwfn);
2075
2076         /* init QM port params */
2077         qed_init_qm_port_params(p_hwfn);
2078
2079         /* init QM vport params */
2080         qed_init_qm_vport_params(p_hwfn);
2081
2082         /* init QM physical queue params */
2083         qed_init_qm_pq_params(p_hwfn);
2084
2085         /* display all that init */
2086         qed_dp_init_qm_params(p_hwfn);
2087 }
2088
2089 /* This function reconfigures the QM pf on the fly.
2090  * For this purpose we:
2091  * 1. reconfigure the QM database
2092  * 2. set new values to runtime array
2093  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
2094  * 4. activate init tool in QM_PF stage
2095  * 5. send an sdm_qm_cmd through rbc interface to release the QM
2096  */
2097 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2098 {
2099         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
2100         bool b_rc;
2101         int rc;
2102
2103         /* initialize qed's qm data structure */
2104         qed_init_qm_info(p_hwfn);
2105
2106         /* stop PF's qm queues */
2107         spin_lock_bh(&qm_lock);
2108         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
2109                                     qm_info->start_pq, qm_info->num_pqs);
2110         spin_unlock_bh(&qm_lock);
2111         if (!b_rc)
2112                 return -EINVAL;
2113
2114         /* prepare QM portion of runtime array */
2115         qed_qm_init_pf(p_hwfn, p_ptt, false);
2116
2117         /* activate init tool on runtime array */
2118         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
2119                           p_hwfn->hw_info.hw_mode);
2120         if (rc)
2121                 return rc;
2122
2123         /* start PF's qm queues */
2124         spin_lock_bh(&qm_lock);
2125         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
2126                                     qm_info->start_pq, qm_info->num_pqs);
2127         spin_unlock_bh(&qm_lock);
2128         if (!b_rc)
2129                 return -EINVAL;
2130
2131         return 0;
2132 }
2133
2134 static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn)
2135 {
2136         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
2137         int rc;
2138
2139         rc = qed_init_qm_sanity(p_hwfn);
2140         if (rc)
2141                 goto alloc_err;
2142
2143         qm_info->qm_pq_params = kcalloc(qed_init_qm_get_num_pqs(p_hwfn),
2144                                         sizeof(*qm_info->qm_pq_params),
2145                                         GFP_KERNEL);
2146         if (!qm_info->qm_pq_params)
2147                 goto alloc_err;
2148
2149         qm_info->qm_vport_params = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
2150                                            sizeof(*qm_info->qm_vport_params),
2151                                            GFP_KERNEL);
2152         if (!qm_info->qm_vport_params)
2153                 goto alloc_err;
2154
2155         qm_info->qm_port_params = kcalloc(p_hwfn->cdev->num_ports_in_engine,
2156                                           sizeof(*qm_info->qm_port_params),
2157                                           GFP_KERNEL);
2158         if (!qm_info->qm_port_params)
2159                 goto alloc_err;
2160
2161         qm_info->wfq_data = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
2162                                     sizeof(*qm_info->wfq_data),
2163                                     GFP_KERNEL);
2164         if (!qm_info->wfq_data)
2165                 goto alloc_err;
2166
2167         return 0;
2168
2169 alloc_err:
2170         DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
2171         qed_qm_info_free(p_hwfn);
2172         return -ENOMEM;
2173 }
2174
2175 int qed_resc_alloc(struct qed_dev *cdev)
2176 {
2177         u32 rdma_tasks, excess_tasks;
2178         u32 line_count;
2179         int i, rc = 0;
2180
2181         if (IS_VF(cdev)) {
2182                 for_each_hwfn(cdev, i) {
2183                         rc = qed_l2_alloc(&cdev->hwfns[i]);
2184                         if (rc)
2185                                 return rc;
2186                 }
2187                 return rc;
2188         }
2189
2190         cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
2191         if (!cdev->fw_data)
2192                 return -ENOMEM;
2193
2194         for_each_hwfn(cdev, i) {
2195                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2196                 u32 n_eqes, num_cons;
2197
2198                 /* Initialize the doorbell recovery mechanism */
2199                 rc = qed_db_recovery_setup(p_hwfn);
2200                 if (rc)
2201                         goto alloc_err;
2202
2203                 /* First allocate the context manager structure */
2204                 rc = qed_cxt_mngr_alloc(p_hwfn);
2205                 if (rc)
2206                         goto alloc_err;
2207
2208                 /* Set the HW cid/tid numbers (in the contest manager)
2209                  * Must be done prior to any further computations.
2210                  */
2211                 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
2212                 if (rc)
2213                         goto alloc_err;
2214
2215                 rc = qed_alloc_qm_data(p_hwfn);
2216                 if (rc)
2217                         goto alloc_err;
2218
2219                 /* init qm info */
2220                 qed_init_qm_info(p_hwfn);
2221
2222                 /* Compute the ILT client partition */
2223                 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
2224                 if (rc) {
2225                         DP_NOTICE(p_hwfn,
2226                                   "too many ILT lines; re-computing with less lines\n");
2227                         /* In case there are not enough ILT lines we reduce the
2228                          * number of RDMA tasks and re-compute.
2229                          */
2230                         excess_tasks =
2231                             qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count);
2232                         if (!excess_tasks)
2233                                 goto alloc_err;
2234
2235                         rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
2236                         rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks);
2237                         if (rc)
2238                                 goto alloc_err;
2239
2240                         rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
2241                         if (rc) {
2242                                 DP_ERR(p_hwfn,
2243                                        "failed ILT compute. Requested too many lines: %u\n",
2244                                        line_count);
2245
2246                                 goto alloc_err;
2247                         }
2248                 }
2249
2250                 /* CID map / ILT shadow table / T2
2251                  * The talbes sizes are determined by the computations above
2252                  */
2253                 rc = qed_cxt_tables_alloc(p_hwfn);
2254                 if (rc)
2255                         goto alloc_err;
2256
2257                 /* SPQ, must follow ILT because initializes SPQ context */
2258                 rc = qed_spq_alloc(p_hwfn);
2259                 if (rc)
2260                         goto alloc_err;
2261
2262                 /* SP status block allocation */
2263                 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
2264                                                          RESERVED_PTT_DPC);
2265
2266                 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
2267                 if (rc)
2268                         goto alloc_err;
2269
2270                 rc = qed_iov_alloc(p_hwfn);
2271                 if (rc)
2272                         goto alloc_err;
2273
2274                 /* EQ */
2275                 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
2276                 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2277                         u32 n_srq = qed_cxt_get_total_srq_count(p_hwfn);
2278                         enum protocol_type rdma_proto;
2279
2280                         if (QED_IS_ROCE_PERSONALITY(p_hwfn))
2281                                 rdma_proto = PROTOCOLID_ROCE;
2282                         else
2283                                 rdma_proto = PROTOCOLID_IWARP;
2284
2285                         num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
2286                                                                rdma_proto,
2287                                                                NULL) * 2;
2288                         /* EQ should be able to get events from all SRQ's
2289                          * at the same time
2290                          */
2291                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB + n_srq;
2292                 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
2293                         num_cons =
2294                             qed_cxt_get_proto_cid_count(p_hwfn,
2295                                                         PROTOCOLID_ISCSI,
2296                                                         NULL);
2297                         n_eqes += 2 * num_cons;
2298                 }
2299
2300                 if (n_eqes > 0xFFFF) {
2301                         DP_ERR(p_hwfn,
2302                                "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
2303                                n_eqes, 0xFFFF);
2304                         goto alloc_no_mem;
2305                 }
2306
2307                 rc = qed_eq_alloc(p_hwfn, (u16) n_eqes);
2308                 if (rc)
2309                         goto alloc_err;
2310
2311                 rc = qed_consq_alloc(p_hwfn);
2312                 if (rc)
2313                         goto alloc_err;
2314
2315                 rc = qed_l2_alloc(p_hwfn);
2316                 if (rc)
2317                         goto alloc_err;
2318
2319 #ifdef CONFIG_QED_LL2
2320                 if (p_hwfn->using_ll2) {
2321                         rc = qed_ll2_alloc(p_hwfn);
2322                         if (rc)
2323                                 goto alloc_err;
2324                 }
2325 #endif
2326
2327                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
2328                         rc = qed_fcoe_alloc(p_hwfn);
2329                         if (rc)
2330                                 goto alloc_err;
2331                 }
2332
2333                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
2334                         rc = qed_iscsi_alloc(p_hwfn);
2335                         if (rc)
2336                                 goto alloc_err;
2337                         rc = qed_ooo_alloc(p_hwfn);
2338                         if (rc)
2339                                 goto alloc_err;
2340                 }
2341
2342                 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2343                         rc = qed_rdma_info_alloc(p_hwfn);
2344                         if (rc)
2345                                 goto alloc_err;
2346                 }
2347
2348                 /* DMA info initialization */
2349                 rc = qed_dmae_info_alloc(p_hwfn);
2350                 if (rc)
2351                         goto alloc_err;
2352
2353                 /* DCBX initialization */
2354                 rc = qed_dcbx_info_alloc(p_hwfn);
2355                 if (rc)
2356                         goto alloc_err;
2357
2358                 rc = qed_dbg_alloc_user_data(p_hwfn, &p_hwfn->dbg_user_info);
2359                 if (rc)
2360                         goto alloc_err;
2361         }
2362
2363         rc = qed_llh_alloc(cdev);
2364         if (rc) {
2365                 DP_NOTICE(cdev,
2366                           "Failed to allocate memory for the llh_info structure\n");
2367                 goto alloc_err;
2368         }
2369
2370         cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
2371         if (!cdev->reset_stats)
2372                 goto alloc_no_mem;
2373
2374         return 0;
2375
2376 alloc_no_mem:
2377         rc = -ENOMEM;
2378 alloc_err:
2379         qed_resc_free(cdev);
2380         return rc;
2381 }
2382
2383 void qed_resc_setup(struct qed_dev *cdev)
2384 {
2385         int i;
2386
2387         if (IS_VF(cdev)) {
2388                 for_each_hwfn(cdev, i)
2389                         qed_l2_setup(&cdev->hwfns[i]);
2390                 return;
2391         }
2392
2393         for_each_hwfn(cdev, i) {
2394                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2395
2396                 qed_cxt_mngr_setup(p_hwfn);
2397                 qed_spq_setup(p_hwfn);
2398                 qed_eq_setup(p_hwfn);
2399                 qed_consq_setup(p_hwfn);
2400
2401                 /* Read shadow of current MFW mailbox */
2402                 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
2403                 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
2404                        p_hwfn->mcp_info->mfw_mb_cur,
2405                        p_hwfn->mcp_info->mfw_mb_length);
2406
2407                 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
2408
2409                 qed_l2_setup(p_hwfn);
2410                 qed_iov_setup(p_hwfn);
2411 #ifdef CONFIG_QED_LL2
2412                 if (p_hwfn->using_ll2)
2413                         qed_ll2_setup(p_hwfn);
2414 #endif
2415                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
2416                         qed_fcoe_setup(p_hwfn);
2417
2418                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
2419                         qed_iscsi_setup(p_hwfn);
2420                         qed_ooo_setup(p_hwfn);
2421                 }
2422         }
2423 }
2424
2425 #define FINAL_CLEANUP_POLL_CNT          (100)
2426 #define FINAL_CLEANUP_POLL_TIME         (10)
2427 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
2428                       struct qed_ptt *p_ptt, u16 id, bool is_vf)
2429 {
2430         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
2431         int rc = -EBUSY;
2432
2433         addr = GTT_BAR0_MAP_REG_USDM_RAM +
2434                 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
2435
2436         if (is_vf)
2437                 id += 0x10;
2438
2439         command |= X_FINAL_CLEANUP_AGG_INT <<
2440                 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
2441         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
2442         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
2443         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
2444
2445         /* Make sure notification is not set before initiating final cleanup */
2446         if (REG_RD(p_hwfn, addr)) {
2447                 DP_NOTICE(p_hwfn,
2448                           "Unexpected; Found final cleanup notification before initiating final cleanup\n");
2449                 REG_WR(p_hwfn, addr, 0);
2450         }
2451
2452         DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2453                    "Sending final cleanup for PFVF[%d] [Command %08x]\n",
2454                    id, command);
2455
2456         qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
2457
2458         /* Poll until completion */
2459         while (!REG_RD(p_hwfn, addr) && count--)
2460                 msleep(FINAL_CLEANUP_POLL_TIME);
2461
2462         if (REG_RD(p_hwfn, addr))
2463                 rc = 0;
2464         else
2465                 DP_NOTICE(p_hwfn,
2466                           "Failed to receive FW final cleanup notification\n");
2467
2468         /* Cleanup afterwards */
2469         REG_WR(p_hwfn, addr, 0);
2470
2471         return rc;
2472 }
2473
2474 static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
2475 {
2476         int hw_mode = 0;
2477
2478         if (QED_IS_BB_B0(p_hwfn->cdev)) {
2479                 hw_mode |= 1 << MODE_BB;
2480         } else if (QED_IS_AH(p_hwfn->cdev)) {
2481                 hw_mode |= 1 << MODE_K2;
2482         } else {
2483                 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
2484                           p_hwfn->cdev->type);
2485                 return -EINVAL;
2486         }
2487
2488         switch (p_hwfn->cdev->num_ports_in_engine) {
2489         case 1:
2490                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
2491                 break;
2492         case 2:
2493                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
2494                 break;
2495         case 4:
2496                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
2497                 break;
2498         default:
2499                 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
2500                           p_hwfn->cdev->num_ports_in_engine);
2501                 return -EINVAL;
2502         }
2503
2504         if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits))
2505                 hw_mode |= 1 << MODE_MF_SD;
2506         else
2507                 hw_mode |= 1 << MODE_MF_SI;
2508
2509         hw_mode |= 1 << MODE_ASIC;
2510
2511         if (p_hwfn->cdev->num_hwfns > 1)
2512                 hw_mode |= 1 << MODE_100G;
2513
2514         p_hwfn->hw_info.hw_mode = hw_mode;
2515
2516         DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
2517                    "Configuring function for hw_mode: 0x%08x\n",
2518                    p_hwfn->hw_info.hw_mode);
2519
2520         return 0;
2521 }
2522
2523 /* Init run time data for all PFs on an engine. */
2524 static void qed_init_cau_rt_data(struct qed_dev *cdev)
2525 {
2526         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
2527         int i, igu_sb_id;
2528
2529         for_each_hwfn(cdev, i) {
2530                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2531                 struct qed_igu_info *p_igu_info;
2532                 struct qed_igu_block *p_block;
2533                 struct cau_sb_entry sb_entry;
2534
2535                 p_igu_info = p_hwfn->hw_info.p_igu_info;
2536
2537                 for (igu_sb_id = 0;
2538                      igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) {
2539                         p_block = &p_igu_info->entry[igu_sb_id];
2540
2541                         if (!p_block->is_pf)
2542                                 continue;
2543
2544                         qed_init_cau_sb_entry(p_hwfn, &sb_entry,
2545                                               p_block->function_id, 0, 0);
2546                         STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
2547                                          sb_entry);
2548                 }
2549         }
2550 }
2551
2552 static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
2553                                      struct qed_ptt *p_ptt)
2554 {
2555         u32 val, wr_mbs, cache_line_size;
2556
2557         val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
2558         switch (val) {
2559         case 0:
2560                 wr_mbs = 128;
2561                 break;
2562         case 1:
2563                 wr_mbs = 256;
2564                 break;
2565         case 2:
2566                 wr_mbs = 512;
2567                 break;
2568         default:
2569                 DP_INFO(p_hwfn,
2570                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2571                         val);
2572                 return;
2573         }
2574
2575         cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
2576         switch (cache_line_size) {
2577         case 32:
2578                 val = 0;
2579                 break;
2580         case 64:
2581                 val = 1;
2582                 break;
2583         case 128:
2584                 val = 2;
2585                 break;
2586         case 256:
2587                 val = 3;
2588                 break;
2589         default:
2590                 DP_INFO(p_hwfn,
2591                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2592                         cache_line_size);
2593         }
2594
2595         if (L1_CACHE_BYTES > wr_mbs)
2596                 DP_INFO(p_hwfn,
2597                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
2598                         L1_CACHE_BYTES, wr_mbs);
2599
2600         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
2601         if (val > 0) {
2602                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
2603                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
2604         }
2605 }
2606
2607 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
2608                               struct qed_ptt *p_ptt, int hw_mode)
2609 {
2610         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
2611         struct qed_qm_common_rt_init_params params;
2612         struct qed_dev *cdev = p_hwfn->cdev;
2613         u8 vf_id, max_num_vfs;
2614         u16 num_pfs, pf_id;
2615         u32 concrete_fid;
2616         int rc = 0;
2617
2618         qed_init_cau_rt_data(cdev);
2619
2620         /* Program GTT windows */
2621         qed_gtt_init(p_hwfn);
2622
2623         if (p_hwfn->mcp_info) {
2624                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
2625                         qm_info->pf_rl_en = true;
2626                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
2627                         qm_info->pf_wfq_en = true;
2628         }
2629
2630         memset(&params, 0, sizeof(params));
2631         params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine;
2632         params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
2633         params.pf_rl_en = qm_info->pf_rl_en;
2634         params.pf_wfq_en = qm_info->pf_wfq_en;
2635         params.global_rl_en = qm_info->vport_rl_en;
2636         params.vport_wfq_en = qm_info->vport_wfq_en;
2637         params.port_params = qm_info->qm_port_params;
2638
2639         qed_qm_common_rt_init(p_hwfn, &params);
2640
2641         qed_cxt_hw_init_common(p_hwfn);
2642
2643         qed_init_cache_line_size(p_hwfn, p_ptt);
2644
2645         rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
2646         if (rc)
2647                 return rc;
2648
2649         qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
2650         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
2651
2652         if (QED_IS_BB(p_hwfn->cdev)) {
2653                 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
2654                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
2655                         qed_fid_pretend(p_hwfn, p_ptt, pf_id);
2656                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2657                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2658                 }
2659                 /* pretend to original PF */
2660                 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2661         }
2662
2663         max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
2664         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
2665                 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
2666                 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
2667                 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
2668                 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
2669                 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
2670                 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
2671         }
2672         /* pretend to original PF */
2673         qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2674
2675         return rc;
2676 }
2677
2678 static int
2679 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
2680                      struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
2681 {
2682         u32 dpi_bit_shift, dpi_count, dpi_page_size;
2683         u32 min_dpis;
2684         u32 n_wids;
2685
2686         /* Calculate DPI size */
2687         n_wids = max_t(u32, QED_MIN_WIDS, n_cpus);
2688         dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids);
2689         dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
2690         dpi_bit_shift = ilog2(dpi_page_size / 4096);
2691         dpi_count = pwm_region_size / dpi_page_size;
2692
2693         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
2694         min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
2695
2696         p_hwfn->dpi_size = dpi_page_size;
2697         p_hwfn->dpi_count = dpi_count;
2698
2699         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
2700
2701         if (dpi_count < min_dpis)
2702                 return -EINVAL;
2703
2704         return 0;
2705 }
2706
2707 enum QED_ROCE_EDPM_MODE {
2708         QED_ROCE_EDPM_MODE_ENABLE = 0,
2709         QED_ROCE_EDPM_MODE_FORCE_ON = 1,
2710         QED_ROCE_EDPM_MODE_DISABLE = 2,
2711 };
2712
2713 bool qed_edpm_enabled(struct qed_hwfn *p_hwfn)
2714 {
2715         if (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm)
2716                 return false;
2717
2718         return true;
2719 }
2720
2721 static int
2722 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2723 {
2724         u32 pwm_regsize, norm_regsize;
2725         u32 non_pwm_conn, min_addr_reg1;
2726         u32 db_bar_size, n_cpus = 1;
2727         u32 roce_edpm_mode;
2728         u32 pf_dems_shift;
2729         int rc = 0;
2730         u8 cond;
2731
2732         db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
2733         if (p_hwfn->cdev->num_hwfns > 1)
2734                 db_bar_size /= 2;
2735
2736         /* Calculate doorbell regions */
2737         non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
2738                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
2739                                                    NULL) +
2740                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
2741                                                    NULL);
2742         norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE);
2743         min_addr_reg1 = norm_regsize / 4096;
2744         pwm_regsize = db_bar_size - norm_regsize;
2745
2746         /* Check that the normal and PWM sizes are valid */
2747         if (db_bar_size < norm_regsize) {
2748                 DP_ERR(p_hwfn->cdev,
2749                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
2750                        db_bar_size, norm_regsize);
2751                 return -EINVAL;
2752         }
2753
2754         if (pwm_regsize < QED_MIN_PWM_REGION) {
2755                 DP_ERR(p_hwfn->cdev,
2756                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
2757                        pwm_regsize,
2758                        QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
2759                 return -EINVAL;
2760         }
2761
2762         /* Calculate number of DPIs */
2763         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
2764         if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
2765             ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
2766                 /* Either EDPM is mandatory, or we are attempting to allocate a
2767                  * WID per CPU.
2768                  */
2769                 n_cpus = num_present_cpus();
2770                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2771         }
2772
2773         cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
2774                (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
2775         if (cond || p_hwfn->dcbx_no_edpm) {
2776                 /* Either EDPM is disabled from user configuration, or it is
2777                  * disabled via DCBx, or it is not mandatory and we failed to
2778                  * allocated a WID per CPU.
2779                  */
2780                 n_cpus = 1;
2781                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2782
2783                 if (cond)
2784                         qed_rdma_dpm_bar(p_hwfn, p_ptt);
2785         }
2786
2787         p_hwfn->wid_count = (u16) n_cpus;
2788
2789         DP_INFO(p_hwfn,
2790                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s, page_size=%lu\n",
2791                 norm_regsize,
2792                 pwm_regsize,
2793                 p_hwfn->dpi_size,
2794                 p_hwfn->dpi_count,
2795                 (!qed_edpm_enabled(p_hwfn)) ?
2796                 "disabled" : "enabled", PAGE_SIZE);
2797
2798         if (rc) {
2799                 DP_ERR(p_hwfn,
2800                        "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
2801                        p_hwfn->dpi_count,
2802                        p_hwfn->pf_params.rdma_pf_params.min_dpis);
2803                 return -EINVAL;
2804         }
2805
2806         p_hwfn->dpi_start_offset = norm_regsize;
2807
2808         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
2809         pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
2810         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
2811         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
2812
2813         return 0;
2814 }
2815
2816 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
2817                             struct qed_ptt *p_ptt, int hw_mode)
2818 {
2819         int rc = 0;
2820
2821         /* In CMT the gate should be cleared by the 2nd hwfn */
2822         if (!QED_IS_CMT(p_hwfn->cdev) || !IS_LEAD_HWFN(p_hwfn))
2823                 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
2824
2825         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
2826         if (rc)
2827                 return rc;
2828
2829         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
2830
2831         return 0;
2832 }
2833
2834 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
2835                           struct qed_ptt *p_ptt,
2836                           struct qed_tunnel_info *p_tunn,
2837                           int hw_mode,
2838                           bool b_hw_start,
2839                           enum qed_int_mode int_mode,
2840                           bool allow_npar_tx_switch)
2841 {
2842         u8 rel_pf_id = p_hwfn->rel_pf_id;
2843         int rc = 0;
2844
2845         if (p_hwfn->mcp_info) {
2846                 struct qed_mcp_function_info *p_info;
2847
2848                 p_info = &p_hwfn->mcp_info->func_info;
2849                 if (p_info->bandwidth_min)
2850                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
2851
2852                 /* Update rate limit once we'll actually have a link */
2853                 p_hwfn->qm_info.pf_rl = 100000;
2854         }
2855
2856         qed_cxt_hw_init_pf(p_hwfn, p_ptt);
2857
2858         qed_int_igu_init_rt(p_hwfn);
2859
2860         /* Set VLAN in NIG if needed */
2861         if (hw_mode & BIT(MODE_MF_SD)) {
2862                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
2863                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
2864                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
2865                              p_hwfn->hw_info.ovlan);
2866
2867                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2868                            "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
2869                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
2870                              1);
2871         }
2872
2873         /* Enable classification by MAC if needed */
2874         if (hw_mode & BIT(MODE_MF_SI)) {
2875                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2876                            "Configuring TAGMAC_CLS_TYPE\n");
2877                 STORE_RT_REG(p_hwfn,
2878                              NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
2879         }
2880
2881         /* Protocol Configuration */
2882         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
2883                      (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
2884         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
2885                      (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
2886         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
2887
2888         /* Sanity check before the PF init sequence that uses DMAE */
2889         rc = qed_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
2890         if (rc)
2891                 return rc;
2892
2893         /* PF Init sequence */
2894         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
2895         if (rc)
2896                 return rc;
2897
2898         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
2899         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
2900         if (rc)
2901                 return rc;
2902
2903         qed_fw_overlay_init_ram(p_hwfn, p_ptt, p_hwfn->fw_overlay_mem);
2904
2905         /* Pure runtime initializations - directly to the HW  */
2906         qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
2907
2908         rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
2909         if (rc)
2910                 return rc;
2911
2912         /* Use the leading hwfn since in CMT only NIG #0 is operational */
2913         if (IS_LEAD_HWFN(p_hwfn)) {
2914                 rc = qed_llh_hw_init_pf(p_hwfn, p_ptt);
2915                 if (rc)
2916                         return rc;
2917         }
2918
2919         if (b_hw_start) {
2920                 /* enable interrupts */
2921                 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
2922
2923                 /* send function start command */
2924                 rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,
2925                                      allow_npar_tx_switch);
2926                 if (rc) {
2927                         DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
2928                         return rc;
2929                 }
2930                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
2931                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
2932                         qed_wr(p_hwfn, p_ptt,
2933                                PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
2934                                0x100);
2935                 }
2936         }
2937         return rc;
2938 }
2939
2940 int qed_pglueb_set_pfid_enable(struct qed_hwfn *p_hwfn,
2941                                struct qed_ptt *p_ptt, bool b_enable)
2942 {
2943         u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
2944
2945         /* Configure the PF's internal FID_enable for master transactions */
2946         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
2947
2948         /* Wait until value is set - try for 1 second every 50us */
2949         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
2950                 val = qed_rd(p_hwfn, p_ptt,
2951                              PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2952                 if (val == set_val)
2953                         break;
2954
2955                 usleep_range(50, 60);
2956         }
2957
2958         if (val != set_val) {
2959                 DP_NOTICE(p_hwfn,
2960                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
2961                 return -EAGAIN;
2962         }
2963
2964         return 0;
2965 }
2966
2967 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
2968                                 struct qed_ptt *p_main_ptt)
2969 {
2970         /* Read shadow of current MFW mailbox */
2971         qed_mcp_read_mb(p_hwfn, p_main_ptt);
2972         memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
2973                p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
2974 }
2975
2976 static void
2977 qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
2978                          struct qed_drv_load_params *p_drv_load)
2979 {
2980         memset(p_load_req, 0, sizeof(*p_load_req));
2981
2982         p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2983                                QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
2984         p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2985         p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2986         p_load_req->override_force_load = p_drv_load->override_force_load;
2987 }
2988
2989 static int qed_vf_start(struct qed_hwfn *p_hwfn,
2990                         struct qed_hw_init_params *p_params)
2991 {
2992         if (p_params->p_tunn) {
2993                 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2994                 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2995         }
2996
2997         p_hwfn->b_int_enabled = true;
2998
2999         return 0;
3000 }
3001
3002 static void qed_pglueb_clear_err(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3003 {
3004         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
3005                BIT(p_hwfn->abs_pf_id));
3006 }
3007
3008 int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
3009 {
3010         struct qed_load_req_params load_req_params;
3011         u32 load_code, resp, param, drv_mb_param;
3012         bool b_default_mtu = true;
3013         struct qed_hwfn *p_hwfn;
3014         const u32 *fw_overlays;
3015         u32 fw_overlays_len;
3016         u16 ether_type;
3017         int rc = 0, i;
3018
3019         if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
3020                 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
3021                 return -EINVAL;
3022         }
3023
3024         if (IS_PF(cdev)) {
3025                 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
3026                 if (rc)
3027                         return rc;
3028         }
3029
3030         for_each_hwfn(cdev, i) {
3031                 p_hwfn = &cdev->hwfns[i];
3032
3033                 /* If management didn't provide a default, set one of our own */
3034                 if (!p_hwfn->hw_info.mtu) {
3035                         p_hwfn->hw_info.mtu = 1500;
3036                         b_default_mtu = false;
3037                 }
3038
3039                 if (IS_VF(cdev)) {
3040                         qed_vf_start(p_hwfn, p_params);
3041                         continue;
3042                 }
3043
3044                 rc = qed_calc_hw_mode(p_hwfn);
3045                 if (rc)
3046                         return rc;
3047
3048                 if (IS_PF(cdev) && (test_bit(QED_MF_8021Q_TAGGING,
3049                                              &cdev->mf_bits) ||
3050                                     test_bit(QED_MF_8021AD_TAGGING,
3051                                              &cdev->mf_bits))) {
3052                         if (test_bit(QED_MF_8021Q_TAGGING, &cdev->mf_bits))
3053                                 ether_type = ETH_P_8021Q;
3054                         else
3055                                 ether_type = ETH_P_8021AD;
3056                         STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3057                                      ether_type);
3058                         STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3059                                      ether_type);
3060                         STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3061                                      ether_type);
3062                         STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
3063                                      ether_type);
3064                 }
3065
3066                 qed_fill_load_req_params(&load_req_params,
3067                                          p_params->p_drv_load_params);
3068                 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
3069                                       &load_req_params);
3070                 if (rc) {
3071                         DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
3072                         return rc;
3073                 }
3074
3075                 load_code = load_req_params.load_code;
3076                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
3077                            "Load request was sent. Load code: 0x%x\n",
3078                            load_code);
3079
3080                 /* Only relevant for recovery:
3081                  * Clear the indication after LOAD_REQ is responded by the MFW.
3082                  */
3083                 cdev->recov_in_prog = false;
3084
3085                 qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
3086
3087                 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
3088
3089                 /* Clean up chip from previous driver if such remains exist.
3090                  * This is not needed when the PF is the first one on the
3091                  * engine, since afterwards we are going to init the FW.
3092                  */
3093                 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
3094                         rc = qed_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
3095                                                p_hwfn->rel_pf_id, false);
3096                         if (rc) {
3097                                 qed_hw_err_notify(p_hwfn, p_hwfn->p_main_ptt,
3098                                                   QED_HW_ERR_RAMROD_FAIL,
3099                                                   "Final cleanup failed\n");
3100                                 goto load_err;
3101                         }
3102                 }
3103
3104                 /* Log and clear previous pglue_b errors if such exist */
3105                 qed_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt, true);
3106
3107                 /* Enable the PF's internal FID_enable in the PXP */
3108                 rc = qed_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
3109                                                 true);
3110                 if (rc)
3111                         goto load_err;
3112
3113                 /* Clear the pglue_b was_error indication.
3114                  * In E4 it must be done after the BME and the internal
3115                  * FID_enable for the PF are set, since VDMs may cause the
3116                  * indication to be set again.
3117                  */
3118                 qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
3119
3120                 fw_overlays = cdev->fw_data->fw_overlays;
3121                 fw_overlays_len = cdev->fw_data->fw_overlays_len;
3122                 p_hwfn->fw_overlay_mem =
3123                     qed_fw_overlay_mem_alloc(p_hwfn, fw_overlays,
3124                                              fw_overlays_len);
3125                 if (!p_hwfn->fw_overlay_mem) {
3126                         DP_NOTICE(p_hwfn,
3127                                   "Failed to allocate fw overlay memory\n");
3128                         rc = -ENOMEM;
3129                         goto load_err;
3130                 }
3131
3132                 switch (load_code) {
3133                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
3134                         rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
3135                                                 p_hwfn->hw_info.hw_mode);
3136                         if (rc)
3137                                 break;
3138                 /* Fall through */
3139                 case FW_MSG_CODE_DRV_LOAD_PORT:
3140                         rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
3141                                               p_hwfn->hw_info.hw_mode);
3142                         if (rc)
3143                                 break;
3144
3145                 /* Fall through */
3146                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
3147                         rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
3148                                             p_params->p_tunn,
3149                                             p_hwfn->hw_info.hw_mode,
3150                                             p_params->b_hw_start,
3151                                             p_params->int_mode,
3152                                             p_params->allow_npar_tx_switch);
3153                         break;
3154                 default:
3155                         DP_NOTICE(p_hwfn,
3156                                   "Unexpected load code [0x%08x]", load_code);
3157                         rc = -EINVAL;
3158                         break;
3159                 }
3160
3161                 if (rc) {
3162                         DP_NOTICE(p_hwfn,
3163                                   "init phase failed for loadcode 0x%x (rc %d)\n",
3164                                   load_code, rc);
3165                         goto load_err;
3166                 }
3167
3168                 rc = qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
3169                 if (rc)
3170                         return rc;
3171
3172                 /* send DCBX attention request command */
3173                 DP_VERBOSE(p_hwfn,
3174                            QED_MSG_DCB,
3175                            "sending phony dcbx set command to trigger DCBx attention handling\n");
3176                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3177                                  DRV_MSG_CODE_SET_DCBX,
3178                                  1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
3179                                  &resp, &param);
3180                 if (rc) {
3181                         DP_NOTICE(p_hwfn,
3182                                   "Failed to send DCBX attention request\n");
3183                         return rc;
3184                 }
3185
3186                 p_hwfn->hw_init_done = true;
3187         }
3188
3189         if (IS_PF(cdev)) {
3190                 p_hwfn = QED_LEADING_HWFN(cdev);
3191
3192                 /* Get pre-negotiated values for stag, bandwidth etc. */
3193                 DP_VERBOSE(p_hwfn,
3194                            QED_MSG_SPQ,
3195                            "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
3196                 drv_mb_param = 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET;
3197                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3198                                  DRV_MSG_CODE_GET_OEM_UPDATES,
3199                                  drv_mb_param, &resp, &param);
3200                 if (rc)
3201                         DP_NOTICE(p_hwfn,
3202                                   "Failed to send GET_OEM_UPDATES attention request\n");
3203
3204                 drv_mb_param = STORM_FW_VERSION;
3205                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3206                                  DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
3207                                  drv_mb_param, &load_code, &param);
3208                 if (rc)
3209                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
3210
3211                 if (!b_default_mtu) {
3212                         rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
3213                                                    p_hwfn->hw_info.mtu);
3214                         if (rc)
3215                                 DP_INFO(p_hwfn,
3216                                         "Failed to update default mtu\n");
3217                 }
3218
3219                 rc = qed_mcp_ov_update_driver_state(p_hwfn,
3220                                                     p_hwfn->p_main_ptt,
3221                                                   QED_OV_DRIVER_STATE_DISABLED);
3222                 if (rc)
3223                         DP_INFO(p_hwfn, "Failed to update driver state\n");
3224
3225                 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
3226                                                QED_OV_ESWITCH_NONE);
3227                 if (rc)
3228                         DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
3229         }
3230
3231         return 0;
3232
3233 load_err:
3234         /* The MFW load lock should be released also when initialization fails.
3235          */
3236         qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
3237         return rc;
3238 }
3239
3240 #define QED_HW_STOP_RETRY_LIMIT (10)
3241 static void qed_hw_timers_stop(struct qed_dev *cdev,
3242                                struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3243 {
3244         int i;
3245
3246         /* close timers */
3247         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
3248         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
3249
3250         if (cdev->recov_in_prog)
3251                 return;
3252
3253         for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
3254                 if ((!qed_rd(p_hwfn, p_ptt,
3255                              TM_REG_PF_SCAN_ACTIVE_CONN)) &&
3256                     (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
3257                         break;
3258
3259                 /* Dependent on number of connection/tasks, possibly
3260                  * 1ms sleep is required between polls
3261                  */
3262                 usleep_range(1000, 2000);
3263         }
3264
3265         if (i < QED_HW_STOP_RETRY_LIMIT)
3266                 return;
3267
3268         DP_NOTICE(p_hwfn,
3269                   "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
3270                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
3271                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
3272 }
3273
3274 void qed_hw_timers_stop_all(struct qed_dev *cdev)
3275 {
3276         int j;
3277
3278         for_each_hwfn(cdev, j) {
3279                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
3280                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
3281
3282                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
3283         }
3284 }
3285
3286 int qed_hw_stop(struct qed_dev *cdev)
3287 {
3288         struct qed_hwfn *p_hwfn;
3289         struct qed_ptt *p_ptt;
3290         int rc, rc2 = 0;
3291         int j;
3292
3293         for_each_hwfn(cdev, j) {
3294                 p_hwfn = &cdev->hwfns[j];
3295                 p_ptt = p_hwfn->p_main_ptt;
3296
3297                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
3298
3299                 if (IS_VF(cdev)) {
3300                         qed_vf_pf_int_cleanup(p_hwfn);
3301                         rc = qed_vf_pf_reset(p_hwfn);
3302                         if (rc) {
3303                                 DP_NOTICE(p_hwfn,
3304                                           "qed_vf_pf_reset failed. rc = %d.\n",
3305                                           rc);
3306                                 rc2 = -EINVAL;
3307                         }
3308                         continue;
3309                 }
3310
3311                 /* mark the hw as uninitialized... */
3312                 p_hwfn->hw_init_done = false;
3313
3314                 /* Send unload command to MCP */
3315                 if (!cdev->recov_in_prog) {
3316                         rc = qed_mcp_unload_req(p_hwfn, p_ptt);
3317                         if (rc) {
3318                                 DP_NOTICE(p_hwfn,
3319                                           "Failed sending a UNLOAD_REQ command. rc = %d.\n",
3320                                           rc);
3321                                 rc2 = -EINVAL;
3322                         }
3323                 }
3324
3325                 qed_slowpath_irq_sync(p_hwfn);
3326
3327                 /* After this point no MFW attentions are expected, e.g. prevent
3328                  * race between pf stop and dcbx pf update.
3329                  */
3330                 rc = qed_sp_pf_stop(p_hwfn);
3331                 if (rc) {
3332                         DP_NOTICE(p_hwfn,
3333                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
3334                                   rc);
3335                         rc2 = -EINVAL;
3336                 }
3337
3338                 qed_wr(p_hwfn, p_ptt,
3339                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
3340
3341                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
3342                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
3343                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
3344                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
3345                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
3346
3347                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
3348
3349                 /* Disable Attention Generation */
3350                 qed_int_igu_disable_int(p_hwfn, p_ptt);
3351
3352                 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
3353                 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
3354
3355                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
3356
3357                 /* Need to wait 1ms to guarantee SBs are cleared */
3358                 usleep_range(1000, 2000);
3359
3360                 /* Disable PF in HW blocks */
3361                 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
3362                 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
3363
3364                 if (IS_LEAD_HWFN(p_hwfn) &&
3365                     test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits) &&
3366                     !QED_IS_FCOE_PERSONALITY(p_hwfn))
3367                         qed_llh_remove_mac_filter(cdev, 0,
3368                                                   p_hwfn->hw_info.hw_mac_addr);
3369
3370                 if (!cdev->recov_in_prog) {
3371                         rc = qed_mcp_unload_done(p_hwfn, p_ptt);
3372                         if (rc) {
3373                                 DP_NOTICE(p_hwfn,
3374                                           "Failed sending a UNLOAD_DONE command. rc = %d.\n",
3375                                           rc);
3376                                 rc2 = -EINVAL;
3377                         }
3378                 }
3379         }
3380
3381         if (IS_PF(cdev) && !cdev->recov_in_prog) {
3382                 p_hwfn = QED_LEADING_HWFN(cdev);
3383                 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
3384
3385                 /* Clear the PF's internal FID_enable in the PXP.
3386                  * In CMT this should only be done for first hw-function, and
3387                  * only after all transactions have stopped for all active
3388                  * hw-functions.
3389                  */
3390                 rc = qed_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
3391                 if (rc) {
3392                         DP_NOTICE(p_hwfn,
3393                                   "qed_pglueb_set_pfid_enable() failed. rc = %d.\n",
3394                                   rc);
3395                         rc2 = -EINVAL;
3396                 }
3397         }
3398
3399         return rc2;
3400 }
3401
3402 int qed_hw_stop_fastpath(struct qed_dev *cdev)
3403 {
3404         int j;
3405
3406         for_each_hwfn(cdev, j) {
3407                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
3408                 struct qed_ptt *p_ptt;
3409
3410                 if (IS_VF(cdev)) {
3411                         qed_vf_pf_int_cleanup(p_hwfn);
3412                         continue;
3413                 }
3414                 p_ptt = qed_ptt_acquire(p_hwfn);
3415                 if (!p_ptt)
3416                         return -EAGAIN;
3417
3418                 DP_VERBOSE(p_hwfn,
3419                            NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
3420
3421                 qed_wr(p_hwfn, p_ptt,
3422                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
3423
3424                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
3425                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
3426                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
3427                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
3428                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
3429
3430                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
3431
3432                 /* Need to wait 1ms to guarantee SBs are cleared */
3433                 usleep_range(1000, 2000);
3434                 qed_ptt_release(p_hwfn, p_ptt);
3435         }
3436
3437         return 0;
3438 }
3439
3440 int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
3441 {
3442         struct qed_ptt *p_ptt;
3443
3444         if (IS_VF(p_hwfn->cdev))
3445                 return 0;
3446
3447         p_ptt = qed_ptt_acquire(p_hwfn);
3448         if (!p_ptt)
3449                 return -EAGAIN;
3450
3451         if (p_hwfn->p_rdma_info &&
3452             p_hwfn->p_rdma_info->active && p_hwfn->b_rdma_enabled_in_prs)
3453                 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1);
3454
3455         /* Re-open incoming traffic */
3456         qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
3457         qed_ptt_release(p_hwfn, p_ptt);
3458
3459         return 0;
3460 }
3461
3462 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
3463 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
3464 {
3465         qed_ptt_pool_free(p_hwfn);
3466         kfree(p_hwfn->hw_info.p_igu_info);
3467         p_hwfn->hw_info.p_igu_info = NULL;
3468 }
3469
3470 /* Setup bar access */
3471 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
3472 {
3473         /* clear indirect access */
3474         if (QED_IS_AH(p_hwfn->cdev)) {
3475                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3476                        PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
3477                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3478                        PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
3479                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3480                        PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
3481                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3482                        PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
3483         } else {
3484                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3485                        PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
3486                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3487                        PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
3488                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3489                        PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
3490                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3491                        PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
3492         }
3493
3494         /* Clean previous pglue_b errors if such exist */
3495         qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
3496
3497         /* enable internal target-read */
3498         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3499                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
3500 }
3501
3502 static void get_function_id(struct qed_hwfn *p_hwfn)
3503 {
3504         /* ME Register */
3505         p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
3506                                                   PXP_PF_ME_OPAQUE_ADDR);
3507
3508         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
3509
3510         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
3511         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
3512                                       PXP_CONCRETE_FID_PFID);
3513         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
3514                                     PXP_CONCRETE_FID_PORT);
3515
3516         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
3517                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
3518                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
3519 }
3520
3521 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
3522 {
3523         u32 *feat_num = p_hwfn->hw_info.feat_num;
3524         struct qed_sb_cnt_info sb_cnt;
3525         u32 non_l2_sbs = 0;
3526
3527         memset(&sb_cnt, 0, sizeof(sb_cnt));
3528         qed_int_get_num_sbs(p_hwfn, &sb_cnt);
3529
3530         if (IS_ENABLED(CONFIG_QED_RDMA) &&
3531             QED_IS_RDMA_PERSONALITY(p_hwfn)) {
3532                 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
3533                  * the status blocks equally between L2 / RoCE but with
3534                  * consideration as to how many l2 queues / cnqs we have.
3535                  */
3536                 feat_num[QED_RDMA_CNQ] =
3537                         min_t(u32, sb_cnt.cnt / 2,
3538                               RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
3539
3540                 non_l2_sbs = feat_num[QED_RDMA_CNQ];
3541         }
3542         if (QED_IS_L2_PERSONALITY(p_hwfn)) {
3543                 /* Start by allocating VF queues, then PF's */
3544                 feat_num[QED_VF_L2_QUE] = min_t(u32,
3545                                                 RESC_NUM(p_hwfn, QED_L2_QUEUE),
3546                                                 sb_cnt.iov_cnt);
3547                 feat_num[QED_PF_L2_QUE] = min_t(u32,
3548                                                 sb_cnt.cnt - non_l2_sbs,
3549                                                 RESC_NUM(p_hwfn,
3550                                                          QED_L2_QUEUE) -
3551                                                 FEAT_NUM(p_hwfn,
3552                                                          QED_VF_L2_QUE));
3553         }
3554
3555         if (QED_IS_FCOE_PERSONALITY(p_hwfn))
3556                 feat_num[QED_FCOE_CQ] =  min_t(u32, sb_cnt.cnt,
3557                                                RESC_NUM(p_hwfn,
3558                                                         QED_CMDQS_CQS));
3559
3560         if (QED_IS_ISCSI_PERSONALITY(p_hwfn))
3561                 feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt,
3562                                                RESC_NUM(p_hwfn,
3563                                                         QED_CMDQS_CQS));
3564         DP_VERBOSE(p_hwfn,
3565                    NETIF_MSG_PROBE,
3566                    "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d #SBS=%d\n",
3567                    (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
3568                    (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
3569                    (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
3570                    (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ),
3571                    (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ),
3572                    (int)sb_cnt.cnt);
3573 }
3574
3575 const char *qed_hw_get_resc_name(enum qed_resources res_id)
3576 {
3577         switch (res_id) {
3578         case QED_L2_QUEUE:
3579                 return "L2_QUEUE";
3580         case QED_VPORT:
3581                 return "VPORT";
3582         case QED_RSS_ENG:
3583                 return "RSS_ENG";
3584         case QED_PQ:
3585                 return "PQ";
3586         case QED_RL:
3587                 return "RL";
3588         case QED_MAC:
3589                 return "MAC";
3590         case QED_VLAN:
3591                 return "VLAN";
3592         case QED_RDMA_CNQ_RAM:
3593                 return "RDMA_CNQ_RAM";
3594         case QED_ILT:
3595                 return "ILT";
3596         case QED_LL2_RAM_QUEUE:
3597                 return "LL2_RAM_QUEUE";
3598         case QED_LL2_CTX_QUEUE:
3599                 return "LL2_CTX_QUEUE";
3600         case QED_CMDQS_CQS:
3601                 return "CMDQS_CQS";
3602         case QED_RDMA_STATS_QUEUE:
3603                 return "RDMA_STATS_QUEUE";
3604         case QED_BDQ:
3605                 return "BDQ";
3606         case QED_SB:
3607                 return "SB";
3608         default:
3609                 return "UNKNOWN_RESOURCE";
3610         }
3611 }
3612
3613 static int
3614 __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
3615                             struct qed_ptt *p_ptt,
3616                             enum qed_resources res_id,
3617                             u32 resc_max_val, u32 *p_mcp_resp)
3618 {
3619         int rc;
3620
3621         rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
3622                                       resc_max_val, p_mcp_resp);
3623         if (rc) {
3624                 DP_NOTICE(p_hwfn,
3625                           "MFW response failure for a max value setting of resource %d [%s]\n",
3626                           res_id, qed_hw_get_resc_name(res_id));
3627                 return rc;
3628         }
3629
3630         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
3631                 DP_INFO(p_hwfn,
3632                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
3633                         res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp);
3634
3635         return 0;
3636 }
3637
3638 static u32 qed_hsi_def_val[][MAX_CHIP_IDS] = {
3639         {MAX_NUM_VFS_BB, MAX_NUM_VFS_K2},
3640         {MAX_NUM_L2_QUEUES_BB, MAX_NUM_L2_QUEUES_K2},
3641         {MAX_NUM_PORTS_BB, MAX_NUM_PORTS_K2},
3642         {MAX_SB_PER_PATH_BB, MAX_SB_PER_PATH_K2,},
3643         {MAX_NUM_PFS_BB, MAX_NUM_PFS_K2},
3644         {MAX_NUM_VPORTS_BB, MAX_NUM_VPORTS_K2},
3645         {ETH_RSS_ENGINE_NUM_BB, ETH_RSS_ENGINE_NUM_K2},
3646         {MAX_QM_TX_QUEUES_BB, MAX_QM_TX_QUEUES_K2},
3647         {PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2},
3648         {RDMA_NUM_STATISTIC_COUNTERS_BB, RDMA_NUM_STATISTIC_COUNTERS_K2},
3649         {MAX_QM_GLOBAL_RLS, MAX_QM_GLOBAL_RLS},
3650         {PBF_MAX_CMD_LINES, PBF_MAX_CMD_LINES},
3651         {BTB_MAX_BLOCKS_BB, BTB_MAX_BLOCKS_K2},
3652 };
3653
3654 u32 qed_get_hsi_def_val(struct qed_dev *cdev, enum qed_hsi_def_type type)
3655 {
3656         enum chip_ids chip_id = QED_IS_BB(cdev) ? CHIP_BB : CHIP_K2;
3657
3658         if (type >= QED_NUM_HSI_DEFS) {
3659                 DP_ERR(cdev, "Unexpected HSI definition type [%d]\n", type);
3660                 return 0;
3661         }
3662
3663         return qed_hsi_def_val[type][chip_id];
3664 }
3665 static int
3666 qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3667 {
3668         u32 resc_max_val, mcp_resp;
3669         u8 res_id;
3670         int rc;
3671         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
3672                 switch (res_id) {
3673                 case QED_LL2_RAM_QUEUE:
3674                         resc_max_val = MAX_NUM_LL2_RX_RAM_QUEUES;
3675                         break;
3676                 case QED_LL2_CTX_QUEUE:
3677                         resc_max_val = MAX_NUM_LL2_RX_CTX_QUEUES;
3678                         break;
3679                 case QED_RDMA_CNQ_RAM:
3680                         /* No need for a case for QED_CMDQS_CQS since
3681                          * CNQ/CMDQS are the same resource.
3682                          */
3683                         resc_max_val = NUM_OF_GLOBAL_QUEUES;
3684                         break;
3685                 case QED_RDMA_STATS_QUEUE:
3686                         resc_max_val =
3687                             NUM_OF_RDMA_STATISTIC_COUNTERS(p_hwfn->cdev);
3688                         break;
3689                 case QED_BDQ:
3690                         resc_max_val = BDQ_NUM_RESOURCES;
3691                         break;
3692                 default:
3693                         continue;
3694                 }
3695
3696                 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
3697                                                  resc_max_val, &mcp_resp);
3698                 if (rc)
3699                         return rc;
3700
3701                 /* There's no point to continue to the next resource if the
3702                  * command is not supported by the MFW.
3703                  * We do continue if the command is supported but the resource
3704                  * is unknown to the MFW. Such a resource will be later
3705                  * configured with the default allocation values.
3706                  */
3707                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
3708                         return -EINVAL;
3709         }
3710
3711         return 0;
3712 }
3713
3714 static
3715 int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
3716                          enum qed_resources res_id,
3717                          u32 *p_resc_num, u32 *p_resc_start)
3718 {
3719         u8 num_funcs = p_hwfn->num_funcs_on_engine;
3720         struct qed_dev *cdev = p_hwfn->cdev;
3721
3722         switch (res_id) {
3723         case QED_L2_QUEUE:
3724                 *p_resc_num = NUM_OF_L2_QUEUES(cdev) / num_funcs;
3725                 break;
3726         case QED_VPORT:
3727                 *p_resc_num = NUM_OF_VPORTS(cdev) / num_funcs;
3728                 break;
3729         case QED_RSS_ENG:
3730                 *p_resc_num = NUM_OF_RSS_ENGINES(cdev) / num_funcs;
3731                 break;
3732         case QED_PQ:
3733                 *p_resc_num = NUM_OF_QM_TX_QUEUES(cdev) / num_funcs;
3734                 *p_resc_num &= ~0x7;    /* The granularity of the PQs is 8 */
3735                 break;
3736         case QED_RL:
3737                 *p_resc_num = NUM_OF_QM_GLOBAL_RLS(cdev) / num_funcs;
3738                 break;
3739         case QED_MAC:
3740         case QED_VLAN:
3741                 /* Each VFC resource can accommodate both a MAC and a VLAN */
3742                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
3743                 break;
3744         case QED_ILT:
3745                 *p_resc_num = NUM_OF_PXP_ILT_RECORDS(cdev) / num_funcs;
3746                 break;
3747         case QED_LL2_RAM_QUEUE:
3748                 *p_resc_num = MAX_NUM_LL2_RX_RAM_QUEUES / num_funcs;
3749                 break;
3750         case QED_LL2_CTX_QUEUE:
3751                 *p_resc_num = MAX_NUM_LL2_RX_CTX_QUEUES / num_funcs;
3752                 break;
3753         case QED_RDMA_CNQ_RAM:
3754         case QED_CMDQS_CQS:
3755                 /* CNQ/CMDQS are the same resource */
3756                 *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs;
3757                 break;
3758         case QED_RDMA_STATS_QUEUE:
3759                 *p_resc_num = NUM_OF_RDMA_STATISTIC_COUNTERS(cdev) / num_funcs;
3760                 break;
3761         case QED_BDQ:
3762                 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
3763                     p_hwfn->hw_info.personality != QED_PCI_FCOE)
3764                         *p_resc_num = 0;
3765                 else
3766                         *p_resc_num = 1;
3767                 break;
3768         case QED_SB:
3769                 /* Since we want its value to reflect whether MFW supports
3770                  * the new scheme, have a default of 0.
3771                  */
3772                 *p_resc_num = 0;
3773                 break;
3774         default:
3775                 return -EINVAL;
3776         }
3777
3778         switch (res_id) {
3779         case QED_BDQ:
3780                 if (!*p_resc_num)
3781                         *p_resc_start = 0;
3782                 else if (p_hwfn->cdev->num_ports_in_engine == 4)
3783                         *p_resc_start = p_hwfn->port_id;
3784                 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
3785                         *p_resc_start = p_hwfn->port_id;
3786                 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
3787                         *p_resc_start = p_hwfn->port_id + 2;
3788                 break;
3789         default:
3790                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
3791                 break;
3792         }
3793
3794         return 0;
3795 }
3796
3797 static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
3798                                   enum qed_resources res_id)
3799 {
3800         u32 dflt_resc_num = 0, dflt_resc_start = 0;
3801         u32 mcp_resp, *p_resc_num, *p_resc_start;
3802         int rc;
3803
3804         p_resc_num = &RESC_NUM(p_hwfn, res_id);
3805         p_resc_start = &RESC_START(p_hwfn, res_id);
3806
3807         rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
3808                                   &dflt_resc_start);
3809         if (rc) {
3810                 DP_ERR(p_hwfn,
3811                        "Failed to get default amount for resource %d [%s]\n",
3812                        res_id, qed_hw_get_resc_name(res_id));
3813                 return rc;
3814         }
3815
3816         rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
3817                                    &mcp_resp, p_resc_num, p_resc_start);
3818         if (rc) {
3819                 DP_NOTICE(p_hwfn,
3820                           "MFW response failure for an allocation request for resource %d [%s]\n",
3821                           res_id, qed_hw_get_resc_name(res_id));
3822                 return rc;
3823         }
3824
3825         /* Default driver values are applied in the following cases:
3826          * - The resource allocation MB command is not supported by the MFW
3827          * - There is an internal error in the MFW while processing the request
3828          * - The resource ID is unknown to the MFW
3829          */
3830         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3831                 DP_INFO(p_hwfn,
3832                         "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
3833                         res_id,
3834                         qed_hw_get_resc_name(res_id),
3835                         mcp_resp, dflt_resc_num, dflt_resc_start);
3836                 *p_resc_num = dflt_resc_num;
3837                 *p_resc_start = dflt_resc_start;
3838                 goto out;
3839         }
3840
3841 out:
3842         /* PQs have to divide by 8 [that's the HW granularity].
3843          * Reduce number so it would fit.
3844          */
3845         if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
3846                 DP_INFO(p_hwfn,
3847                         "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
3848                         *p_resc_num,
3849                         (*p_resc_num) & ~0x7,
3850                         *p_resc_start, (*p_resc_start) & ~0x7);
3851                 *p_resc_num &= ~0x7;
3852                 *p_resc_start &= ~0x7;
3853         }
3854
3855         return 0;
3856 }
3857
3858 static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn)
3859 {
3860         int rc;
3861         u8 res_id;
3862
3863         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
3864                 rc = __qed_hw_set_resc_info(p_hwfn, res_id);
3865                 if (rc)
3866                         return rc;
3867         }
3868
3869         return 0;
3870 }
3871
3872 static int qed_hw_get_ppfid_bitmap(struct qed_hwfn *p_hwfn,
3873                                    struct qed_ptt *p_ptt)
3874 {
3875         struct qed_dev *cdev = p_hwfn->cdev;
3876         u8 native_ppfid_idx;
3877         int rc;
3878
3879         /* Calculation of BB/AH is different for native_ppfid_idx */
3880         if (QED_IS_BB(cdev))
3881                 native_ppfid_idx = p_hwfn->rel_pf_id;
3882         else
3883                 native_ppfid_idx = p_hwfn->rel_pf_id /
3884                     cdev->num_ports_in_engine;
3885
3886         rc = qed_mcp_get_ppfid_bitmap(p_hwfn, p_ptt);
3887         if (rc != 0 && rc != -EOPNOTSUPP)
3888                 return rc;
3889         else if (rc == -EOPNOTSUPP)
3890                 cdev->ppfid_bitmap = 0x1 << native_ppfid_idx;
3891
3892         if (!(cdev->ppfid_bitmap & (0x1 << native_ppfid_idx))) {
3893                 DP_INFO(p_hwfn,
3894                         "Fix the PPFID bitmap to include the native PPFID [native_ppfid_idx %hhd, orig_bitmap 0x%hhx]\n",
3895                         native_ppfid_idx, cdev->ppfid_bitmap);
3896                 cdev->ppfid_bitmap = 0x1 << native_ppfid_idx;
3897         }
3898
3899         return 0;
3900 }
3901
3902 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3903 {
3904         struct qed_resc_unlock_params resc_unlock_params;
3905         struct qed_resc_lock_params resc_lock_params;
3906         bool b_ah = QED_IS_AH(p_hwfn->cdev);
3907         u8 res_id;
3908         int rc;
3909
3910         /* Setting the max values of the soft resources and the following
3911          * resources allocation queries should be atomic. Since several PFs can
3912          * run in parallel - a resource lock is needed.
3913          * If either the resource lock or resource set value commands are not
3914          * supported - skip the the max values setting, release the lock if
3915          * needed, and proceed to the queries. Other failures, including a
3916          * failure to acquire the lock, will cause this function to fail.
3917          */
3918         qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
3919                                        QED_RESC_LOCK_RESC_ALLOC, false);
3920
3921         rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
3922         if (rc && rc != -EINVAL) {
3923                 return rc;
3924         } else if (rc == -EINVAL) {
3925                 DP_INFO(p_hwfn,
3926                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
3927         } else if (!rc && !resc_lock_params.b_granted) {
3928                 DP_NOTICE(p_hwfn,
3929                           "Failed to acquire the resource lock for the resource allocation commands\n");
3930                 return -EBUSY;
3931         } else {
3932                 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt);
3933                 if (rc && rc != -EINVAL) {
3934                         DP_NOTICE(p_hwfn,
3935                                   "Failed to set the max values of the soft resources\n");
3936                         goto unlock_and_exit;
3937                 } else if (rc == -EINVAL) {
3938                         DP_INFO(p_hwfn,
3939                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
3940                         rc = qed_mcp_resc_unlock(p_hwfn, p_ptt,
3941                                                  &resc_unlock_params);
3942                         if (rc)
3943                                 DP_INFO(p_hwfn,
3944                                         "Failed to release the resource lock for the resource allocation commands\n");
3945                 }
3946         }
3947
3948         rc = qed_hw_set_resc_info(p_hwfn);
3949         if (rc)
3950                 goto unlock_and_exit;
3951
3952         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
3953                 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
3954                 if (rc)
3955                         DP_INFO(p_hwfn,
3956                                 "Failed to release the resource lock for the resource allocation commands\n");
3957         }
3958
3959         /* PPFID bitmap */
3960         if (IS_LEAD_HWFN(p_hwfn)) {
3961                 rc = qed_hw_get_ppfid_bitmap(p_hwfn, p_ptt);
3962                 if (rc)
3963                         return rc;
3964         }
3965
3966         /* Sanity for ILT */
3967         if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
3968             (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
3969                 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
3970                           RESC_START(p_hwfn, QED_ILT),
3971                           RESC_END(p_hwfn, QED_ILT) - 1);
3972                 return -EINVAL;
3973         }
3974
3975         /* This will also learn the number of SBs from MFW */
3976         if (qed_int_igu_reset_cam(p_hwfn, p_ptt))
3977                 return -EINVAL;
3978
3979         qed_hw_set_feat(p_hwfn);
3980
3981         for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
3982                 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
3983                            qed_hw_get_resc_name(res_id),
3984                            RESC_NUM(p_hwfn, res_id),
3985                            RESC_START(p_hwfn, res_id));
3986
3987         return 0;
3988
3989 unlock_and_exit:
3990         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
3991                 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
3992         return rc;
3993 }
3994
3995 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3996 {
3997         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
3998         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
3999         struct qed_mcp_link_capabilities *p_caps;
4000         struct qed_mcp_link_params *link;
4001
4002         /* Read global nvm_cfg address */
4003         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
4004
4005         /* Verify MCP has initialized it */
4006         if (!nvm_cfg_addr) {
4007                 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
4008                 return -EINVAL;
4009         }
4010
4011         /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
4012         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
4013
4014         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4015                offsetof(struct nvm_cfg1, glob) +
4016                offsetof(struct nvm_cfg1_glob, core_cfg);
4017
4018         core_cfg = qed_rd(p_hwfn, p_ptt, addr);
4019
4020         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
4021                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
4022         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
4023                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
4024                 break;
4025         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
4026                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
4027                 break;
4028         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
4029                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
4030                 break;
4031         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
4032                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
4033                 break;
4034         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
4035                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
4036                 break;
4037         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
4038                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
4039                 break;
4040         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
4041                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
4042                 break;
4043         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
4044                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
4045                 break;
4046         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
4047                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
4048                 break;
4049         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
4050                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
4051                 break;
4052         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
4053                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
4054                 break;
4055         default:
4056                 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
4057                 break;
4058         }
4059
4060         /* Read default link configuration */
4061         link = &p_hwfn->mcp_info->link_input;
4062         p_caps = &p_hwfn->mcp_info->link_capabilities;
4063         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4064                         offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
4065         link_temp = qed_rd(p_hwfn, p_ptt,
4066                            port_cfg_addr +
4067                            offsetof(struct nvm_cfg1_port, speed_cap_mask));
4068         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
4069         link->speed.advertised_speeds = link_temp;
4070
4071         link_temp = link->speed.advertised_speeds;
4072         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
4073
4074         link_temp = qed_rd(p_hwfn, p_ptt,
4075                            port_cfg_addr +
4076                            offsetof(struct nvm_cfg1_port, link_settings));
4077         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
4078                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
4079         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
4080                 link->speed.autoneg = true;
4081                 break;
4082         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
4083                 link->speed.forced_speed = 1000;
4084                 break;
4085         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
4086                 link->speed.forced_speed = 10000;
4087                 break;
4088         case NVM_CFG1_PORT_DRV_LINK_SPEED_20G:
4089                 link->speed.forced_speed = 20000;
4090                 break;
4091         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
4092                 link->speed.forced_speed = 25000;
4093                 break;
4094         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
4095                 link->speed.forced_speed = 40000;
4096                 break;
4097         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
4098                 link->speed.forced_speed = 50000;
4099                 break;
4100         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
4101                 link->speed.forced_speed = 100000;
4102                 break;
4103         default:
4104                 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
4105         }
4106
4107         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
4108                 link->speed.autoneg;
4109
4110         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
4111         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
4112         link->pause.autoneg = !!(link_temp &
4113                                  NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
4114         link->pause.forced_rx = !!(link_temp &
4115                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
4116         link->pause.forced_tx = !!(link_temp &
4117                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
4118         link->loopback_mode = 0;
4119
4120         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
4121                 link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr +
4122                                    offsetof(struct nvm_cfg1_port, ext_phy));
4123                 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
4124                 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
4125                 p_caps->default_eee = QED_MCP_EEE_ENABLED;
4126                 link->eee.enable = true;
4127                 switch (link_temp) {
4128                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
4129                         p_caps->default_eee = QED_MCP_EEE_DISABLED;
4130                         link->eee.enable = false;
4131                         break;
4132                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
4133                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
4134                         break;
4135                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
4136                         p_caps->eee_lpi_timer =
4137                             EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
4138                         break;
4139                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
4140                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
4141                         break;
4142                 }
4143
4144                 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
4145                 link->eee.tx_lpi_enable = link->eee.enable;
4146                 link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV;
4147         } else {
4148                 p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED;
4149         }
4150
4151         DP_VERBOSE(p_hwfn,
4152                    NETIF_MSG_LINK,
4153                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x EEE: %02x [%08x usec]\n",
4154                    link->speed.forced_speed,
4155                    link->speed.advertised_speeds,
4156                    link->speed.autoneg,
4157                    link->pause.autoneg,
4158                    p_caps->default_eee, p_caps->eee_lpi_timer);
4159
4160         if (IS_LEAD_HWFN(p_hwfn)) {
4161                 struct qed_dev *cdev = p_hwfn->cdev;
4162
4163                 /* Read Multi-function information from shmem */
4164                 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4165                        offsetof(struct nvm_cfg1, glob) +
4166                        offsetof(struct nvm_cfg1_glob, generic_cont0);
4167
4168                 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
4169
4170                 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
4171                           NVM_CFG1_GLOB_MF_MODE_OFFSET;
4172
4173                 switch (mf_mode) {
4174                 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
4175                         cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS);
4176                         break;
4177                 case NVM_CFG1_GLOB_MF_MODE_UFP:
4178                         cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
4179                                         BIT(QED_MF_LLH_PROTO_CLSS) |
4180                                         BIT(QED_MF_UFP_SPECIFIC) |
4181                                         BIT(QED_MF_8021Q_TAGGING) |
4182                                         BIT(QED_MF_DONT_ADD_VLAN0_TAG);
4183                         break;
4184                 case NVM_CFG1_GLOB_MF_MODE_BD:
4185                         cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
4186                                         BIT(QED_MF_LLH_PROTO_CLSS) |
4187                                         BIT(QED_MF_8021AD_TAGGING) |
4188                                         BIT(QED_MF_DONT_ADD_VLAN0_TAG);
4189                         break;
4190                 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
4191                         cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
4192                                         BIT(QED_MF_LLH_PROTO_CLSS) |
4193                                         BIT(QED_MF_LL2_NON_UNICAST) |
4194                                         BIT(QED_MF_INTER_PF_SWITCH);
4195                         break;
4196                 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
4197                         cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
4198                                         BIT(QED_MF_LLH_PROTO_CLSS) |
4199                                         BIT(QED_MF_LL2_NON_UNICAST);
4200                         if (QED_IS_BB(p_hwfn->cdev))
4201                                 cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF);
4202                         break;
4203                 }
4204
4205                 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
4206                         cdev->mf_bits);
4207         }
4208
4209         DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
4210                 p_hwfn->cdev->mf_bits);
4211
4212         /* Read device capabilities information from shmem */
4213         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4214                 offsetof(struct nvm_cfg1, glob) +
4215                 offsetof(struct nvm_cfg1_glob, device_capabilities);
4216
4217         device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
4218         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
4219                 __set_bit(QED_DEV_CAP_ETH,
4220                           &p_hwfn->hw_info.device_capabilities);
4221         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
4222                 __set_bit(QED_DEV_CAP_FCOE,
4223                           &p_hwfn->hw_info.device_capabilities);
4224         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
4225                 __set_bit(QED_DEV_CAP_ISCSI,
4226                           &p_hwfn->hw_info.device_capabilities);
4227         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
4228                 __set_bit(QED_DEV_CAP_ROCE,
4229                           &p_hwfn->hw_info.device_capabilities);
4230
4231         return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
4232 }
4233
4234 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4235 {
4236         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
4237         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
4238         struct qed_dev *cdev = p_hwfn->cdev;
4239
4240         num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
4241
4242         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
4243          * in the other bits are selected.
4244          * Bits 1-15 are for functions 1-15, respectively, and their value is
4245          * '0' only for enabled functions (function 0 always exists and
4246          * enabled).
4247          * In case of CMT, only the "even" functions are enabled, and thus the
4248          * number of functions for both hwfns is learnt from the same bits.
4249          */
4250         reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
4251
4252         if (reg_function_hide & 0x1) {
4253                 if (QED_IS_BB(cdev)) {
4254                         if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
4255                                 num_funcs = 0;
4256                                 eng_mask = 0xaaaa;
4257                         } else {
4258                                 num_funcs = 1;
4259                                 eng_mask = 0x5554;
4260                         }
4261                 } else {
4262                         num_funcs = 1;
4263                         eng_mask = 0xfffe;
4264                 }
4265
4266                 /* Get the number of the enabled functions on the engine */
4267                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
4268                 while (tmp) {
4269                         if (tmp & 0x1)
4270                                 num_funcs++;
4271                         tmp >>= 0x1;
4272                 }
4273
4274                 /* Get the PF index within the enabled functions */
4275                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
4276                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
4277                 while (tmp) {
4278                         if (tmp & 0x1)
4279                                 enabled_func_idx--;
4280                         tmp >>= 0x1;
4281                 }
4282         }
4283
4284         p_hwfn->num_funcs_on_engine = num_funcs;
4285         p_hwfn->enabled_func_idx = enabled_func_idx;
4286
4287         DP_VERBOSE(p_hwfn,
4288                    NETIF_MSG_PROBE,
4289                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
4290                    p_hwfn->rel_pf_id,
4291                    p_hwfn->abs_pf_id,
4292                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
4293 }
4294
4295 static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4296 {
4297         u32 addr, global_offsize, global_addr, port_mode;
4298         struct qed_dev *cdev = p_hwfn->cdev;
4299
4300         /* In CMT there is always only one port */
4301         if (cdev->num_hwfns > 1) {
4302                 cdev->num_ports_in_engine = 1;
4303                 cdev->num_ports = 1;
4304                 return;
4305         }
4306
4307         /* Determine the number of ports per engine */
4308         port_mode = qed_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE);
4309         switch (port_mode) {
4310         case 0x0:
4311                 cdev->num_ports_in_engine = 1;
4312                 break;
4313         case 0x1:
4314                 cdev->num_ports_in_engine = 2;
4315                 break;
4316         case 0x2:
4317                 cdev->num_ports_in_engine = 4;
4318                 break;
4319         default:
4320                 DP_NOTICE(p_hwfn, "Unknown port mode 0x%08x\n", port_mode);
4321                 cdev->num_ports_in_engine = 1;  /* Default to something */
4322                 break;
4323         }
4324
4325         /* Get the total number of ports of the device */
4326         addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
4327                                     PUBLIC_GLOBAL);
4328         global_offsize = qed_rd(p_hwfn, p_ptt, addr);
4329         global_addr = SECTION_ADDR(global_offsize, 0);
4330         addr = global_addr + offsetof(struct public_global, max_ports);
4331         cdev->num_ports = (u8)qed_rd(p_hwfn, p_ptt, addr);
4332 }
4333
4334 static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4335 {
4336         struct qed_mcp_link_capabilities *p_caps;
4337         u32 eee_status;
4338
4339         p_caps = &p_hwfn->mcp_info->link_capabilities;
4340         if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED)
4341                 return;
4342
4343         p_caps->eee_speed_caps = 0;
4344         eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
4345                             offsetof(struct public_port, eee_status));
4346         eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
4347                         EEE_SUPPORTED_SPEED_OFFSET;
4348
4349         if (eee_status & EEE_1G_SUPPORTED)
4350                 p_caps->eee_speed_caps |= QED_EEE_1G_ADV;
4351         if (eee_status & EEE_10G_ADV)
4352                 p_caps->eee_speed_caps |= QED_EEE_10G_ADV;
4353 }
4354
4355 static int
4356 qed_get_hw_info(struct qed_hwfn *p_hwfn,
4357                 struct qed_ptt *p_ptt,
4358                 enum qed_pci_personality personality)
4359 {
4360         int rc;
4361
4362         /* Since all information is common, only first hwfns should do this */
4363         if (IS_LEAD_HWFN(p_hwfn)) {
4364                 rc = qed_iov_hw_info(p_hwfn);
4365                 if (rc)
4366                         return rc;
4367         }
4368
4369         if (IS_LEAD_HWFN(p_hwfn))
4370                 qed_hw_info_port_num(p_hwfn, p_ptt);
4371
4372         qed_mcp_get_capabilities(p_hwfn, p_ptt);
4373
4374         qed_hw_get_nvm_info(p_hwfn, p_ptt);
4375
4376         rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
4377         if (rc)
4378                 return rc;
4379
4380         if (qed_mcp_is_init(p_hwfn))
4381                 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
4382                                 p_hwfn->mcp_info->func_info.mac);
4383         else
4384                 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
4385
4386         if (qed_mcp_is_init(p_hwfn)) {
4387                 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
4388                         p_hwfn->hw_info.ovlan =
4389                                 p_hwfn->mcp_info->func_info.ovlan;
4390
4391                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
4392
4393                 qed_get_eee_caps(p_hwfn, p_ptt);
4394
4395                 qed_mcp_read_ufp_config(p_hwfn, p_ptt);
4396         }
4397
4398         if (qed_mcp_is_init(p_hwfn)) {
4399                 enum qed_pci_personality protocol;
4400
4401                 protocol = p_hwfn->mcp_info->func_info.protocol;
4402                 p_hwfn->hw_info.personality = protocol;
4403         }
4404
4405         if (QED_IS_ROCE_PERSONALITY(p_hwfn))
4406                 p_hwfn->hw_info.multi_tc_roce_en = true;
4407
4408         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
4409         p_hwfn->hw_info.num_active_tc = 1;
4410
4411         qed_get_num_funcs(p_hwfn, p_ptt);
4412
4413         if (qed_mcp_is_init(p_hwfn))
4414                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
4415
4416         return qed_hw_get_resc(p_hwfn, p_ptt);
4417 }
4418
4419 static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4420 {
4421         struct qed_dev *cdev = p_hwfn->cdev;
4422         u16 device_id_mask;
4423         u32 tmp;
4424
4425         /* Read Vendor Id / Device Id */
4426         pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
4427         pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
4428
4429         /* Determine type */
4430         device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
4431         switch (device_id_mask) {
4432         case QED_DEV_ID_MASK_BB:
4433                 cdev->type = QED_DEV_TYPE_BB;
4434                 break;
4435         case QED_DEV_ID_MASK_AH:
4436                 cdev->type = QED_DEV_TYPE_AH;
4437                 break;
4438         default:
4439                 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
4440                 return -EBUSY;
4441         }
4442
4443         cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
4444         cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
4445
4446         MASK_FIELD(CHIP_REV, cdev->chip_rev);
4447
4448         /* Learn number of HW-functions */
4449         tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
4450
4451         if (tmp & (1 << p_hwfn->rel_pf_id)) {
4452                 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
4453                 cdev->num_hwfns = 2;
4454         } else {
4455                 cdev->num_hwfns = 1;
4456         }
4457
4458         cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
4459                                     MISCS_REG_CHIP_TEST_REG) >> 4;
4460         MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
4461         cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
4462         MASK_FIELD(CHIP_METAL, cdev->chip_metal);
4463
4464         DP_INFO(cdev->hwfns,
4465                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
4466                 QED_IS_BB(cdev) ? "BB" : "AH",
4467                 'A' + cdev->chip_rev,
4468                 (int)cdev->chip_metal,
4469                 cdev->chip_num, cdev->chip_rev,
4470                 cdev->chip_bond_id, cdev->chip_metal);
4471
4472         return 0;
4473 }
4474
4475 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
4476                                  void __iomem *p_regview,
4477                                  void __iomem *p_doorbells,
4478                                  u64 db_phys_addr,
4479                                  enum qed_pci_personality personality)
4480 {
4481         struct qed_dev *cdev = p_hwfn->cdev;
4482         int rc = 0;
4483
4484         /* Split PCI bars evenly between hwfns */
4485         p_hwfn->regview = p_regview;
4486         p_hwfn->doorbells = p_doorbells;
4487         p_hwfn->db_phys_addr = db_phys_addr;
4488
4489         if (IS_VF(p_hwfn->cdev))
4490                 return qed_vf_hw_prepare(p_hwfn);
4491
4492         /* Validate that chip access is feasible */
4493         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
4494                 DP_ERR(p_hwfn,
4495                        "Reading the ME register returns all Fs; Preventing further chip access\n");
4496                 return -EINVAL;
4497         }
4498
4499         get_function_id(p_hwfn);
4500
4501         /* Allocate PTT pool */
4502         rc = qed_ptt_pool_alloc(p_hwfn);
4503         if (rc)
4504                 goto err0;
4505
4506         /* Allocate the main PTT */
4507         p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
4508
4509         /* First hwfn learns basic information, e.g., number of hwfns */
4510         if (!p_hwfn->my_id) {
4511                 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
4512                 if (rc)
4513                         goto err1;
4514         }
4515
4516         qed_hw_hwfn_prepare(p_hwfn);
4517
4518         /* Initialize MCP structure */
4519         rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
4520         if (rc) {
4521                 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
4522                 goto err1;
4523         }
4524
4525         /* Read the device configuration information from the HW and SHMEM */
4526         rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
4527         if (rc) {
4528                 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
4529                 goto err2;
4530         }
4531
4532         /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
4533          * is called as it sets the ports number in an engine.
4534          */
4535         if (IS_LEAD_HWFN(p_hwfn) && !cdev->recov_in_prog) {
4536                 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
4537                 if (rc)
4538                         DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
4539         }
4540
4541         /* NVRAM info initialization and population */
4542         if (IS_LEAD_HWFN(p_hwfn)) {
4543                 rc = qed_mcp_nvm_info_populate(p_hwfn);
4544                 if (rc) {
4545                         DP_NOTICE(p_hwfn,
4546                                   "Failed to populate nvm info shadow\n");
4547                         goto err2;
4548                 }
4549         }
4550
4551         /* Allocate the init RT array and initialize the init-ops engine */
4552         rc = qed_init_alloc(p_hwfn);
4553         if (rc)
4554                 goto err3;
4555
4556         return rc;
4557 err3:
4558         if (IS_LEAD_HWFN(p_hwfn))
4559                 qed_mcp_nvm_info_free(p_hwfn);
4560 err2:
4561         if (IS_LEAD_HWFN(p_hwfn))
4562                 qed_iov_free_hw_info(p_hwfn->cdev);
4563         qed_mcp_free(p_hwfn);
4564 err1:
4565         qed_hw_hwfn_free(p_hwfn);
4566 err0:
4567         return rc;
4568 }
4569
4570 int qed_hw_prepare(struct qed_dev *cdev,
4571                    int personality)
4572 {
4573         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
4574         int rc;
4575
4576         /* Store the precompiled init data ptrs */
4577         if (IS_PF(cdev))
4578                 qed_init_iro_array(cdev);
4579
4580         /* Initialize the first hwfn - will learn number of hwfns */
4581         rc = qed_hw_prepare_single(p_hwfn,
4582                                    cdev->regview,
4583                                    cdev->doorbells,
4584                                    cdev->db_phys_addr,
4585                                    personality);
4586         if (rc)
4587                 return rc;
4588
4589         personality = p_hwfn->hw_info.personality;
4590
4591         /* Initialize the rest of the hwfns */
4592         if (cdev->num_hwfns > 1) {
4593                 void __iomem *p_regview, *p_doorbell;
4594                 u64 db_phys_addr;
4595                 u32 offset;
4596
4597                 /* adjust bar offset for second engine */
4598                 offset = qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
4599                                          BAR_ID_0) / 2;
4600                 p_regview = cdev->regview + offset;
4601
4602                 offset = qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
4603                                          BAR_ID_1) / 2;
4604
4605                 p_doorbell = cdev->doorbells + offset;
4606
4607                 db_phys_addr = cdev->db_phys_addr + offset;
4608
4609                 /* prepare second hw function */
4610                 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
4611                                            p_doorbell, db_phys_addr,
4612                                            personality);
4613
4614                 /* in case of error, need to free the previously
4615                  * initiliazed hwfn 0.
4616                  */
4617                 if (rc) {
4618                         if (IS_PF(cdev)) {
4619                                 qed_init_free(p_hwfn);
4620                                 qed_mcp_nvm_info_free(p_hwfn);
4621                                 qed_mcp_free(p_hwfn);
4622                                 qed_hw_hwfn_free(p_hwfn);
4623                         }
4624                 }
4625         }
4626
4627         return rc;
4628 }
4629
4630 void qed_hw_remove(struct qed_dev *cdev)
4631 {
4632         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
4633         int i;
4634
4635         if (IS_PF(cdev))
4636                 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
4637                                                QED_OV_DRIVER_STATE_NOT_LOADED);
4638
4639         for_each_hwfn(cdev, i) {
4640                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4641
4642                 if (IS_VF(cdev)) {
4643                         qed_vf_pf_release(p_hwfn);
4644                         continue;
4645                 }
4646
4647                 qed_init_free(p_hwfn);
4648                 qed_hw_hwfn_free(p_hwfn);
4649                 qed_mcp_free(p_hwfn);
4650         }
4651
4652         qed_iov_free_hw_info(cdev);
4653
4654         qed_mcp_nvm_info_free(p_hwfn);
4655 }
4656
4657 static void qed_chain_free_next_ptr(struct qed_dev *cdev,
4658                                     struct qed_chain *p_chain)
4659 {
4660         void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
4661         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
4662         struct qed_chain_next *p_next;
4663         u32 size, i;
4664
4665         if (!p_virt)
4666                 return;
4667
4668         size = p_chain->elem_size * p_chain->usable_per_page;
4669
4670         for (i = 0; i < p_chain->page_cnt; i++) {
4671                 if (!p_virt)
4672                         break;
4673
4674                 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
4675                 p_virt_next = p_next->next_virt;
4676                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
4677
4678                 dma_free_coherent(&cdev->pdev->dev,
4679                                   QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
4680
4681                 p_virt = p_virt_next;
4682                 p_phys = p_phys_next;
4683         }
4684 }
4685
4686 static void qed_chain_free_single(struct qed_dev *cdev,
4687                                   struct qed_chain *p_chain)
4688 {
4689         if (!p_chain->p_virt_addr)
4690                 return;
4691
4692         dma_free_coherent(&cdev->pdev->dev,
4693                           QED_CHAIN_PAGE_SIZE,
4694                           p_chain->p_virt_addr, p_chain->p_phys_addr);
4695 }
4696
4697 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
4698 {
4699         struct addr_tbl_entry *pp_addr_tbl = p_chain->pbl.pp_addr_tbl;
4700         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
4701
4702         if (!pp_addr_tbl)
4703                 return;
4704
4705         for (i = 0; i < page_cnt; i++) {
4706                 if (!pp_addr_tbl[i].virt_addr || !pp_addr_tbl[i].dma_map)
4707                         break;
4708
4709                 dma_free_coherent(&cdev->pdev->dev,
4710                                   QED_CHAIN_PAGE_SIZE,
4711                                   pp_addr_tbl[i].virt_addr,
4712                                   pp_addr_tbl[i].dma_map);
4713         }
4714
4715         pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
4716
4717         if (!p_chain->b_external_pbl)
4718                 dma_free_coherent(&cdev->pdev->dev,
4719                                   pbl_size,
4720                                   p_chain->pbl_sp.p_virt_table,
4721                                   p_chain->pbl_sp.p_phys_table);
4722
4723         vfree(p_chain->pbl.pp_addr_tbl);
4724         p_chain->pbl.pp_addr_tbl = NULL;
4725 }
4726
4727 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
4728 {
4729         switch (p_chain->mode) {
4730         case QED_CHAIN_MODE_NEXT_PTR:
4731                 qed_chain_free_next_ptr(cdev, p_chain);
4732                 break;
4733         case QED_CHAIN_MODE_SINGLE:
4734                 qed_chain_free_single(cdev, p_chain);
4735                 break;
4736         case QED_CHAIN_MODE_PBL:
4737                 qed_chain_free_pbl(cdev, p_chain);
4738                 break;
4739         }
4740 }
4741
4742 static int
4743 qed_chain_alloc_sanity_check(struct qed_dev *cdev,
4744                              enum qed_chain_cnt_type cnt_type,
4745                              size_t elem_size, u32 page_cnt)
4746 {
4747         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
4748
4749         /* The actual chain size can be larger than the maximal possible value
4750          * after rounding up the requested elements number to pages, and after
4751          * taking into acount the unusuable elements (next-ptr elements).
4752          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
4753          * size/capacity fields are of a u32 type.
4754          */
4755         if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
4756              chain_size > ((u32)U16_MAX + 1)) ||
4757             (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
4758                 DP_NOTICE(cdev,
4759                           "The actual chain size (0x%llx) is larger than the maximal possible value\n",
4760                           chain_size);
4761                 return -EINVAL;
4762         }
4763
4764         return 0;
4765 }
4766
4767 static int
4768 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
4769 {
4770         void *p_virt = NULL, *p_virt_prev = NULL;
4771         dma_addr_t p_phys = 0;
4772         u32 i;
4773
4774         for (i = 0; i < p_chain->page_cnt; i++) {
4775                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
4776                                             QED_CHAIN_PAGE_SIZE,
4777                                             &p_phys, GFP_KERNEL);
4778                 if (!p_virt)
4779                         return -ENOMEM;
4780
4781                 if (i == 0) {
4782                         qed_chain_init_mem(p_chain, p_virt, p_phys);
4783                         qed_chain_reset(p_chain);
4784                 } else {
4785                         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4786                                                      p_virt, p_phys);
4787                 }
4788
4789                 p_virt_prev = p_virt;
4790         }
4791         /* Last page's next element should point to the beginning of the
4792          * chain.
4793          */
4794         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4795                                      p_chain->p_virt_addr,
4796                                      p_chain->p_phys_addr);
4797
4798         return 0;
4799 }
4800
4801 static int
4802 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
4803 {
4804         dma_addr_t p_phys = 0;
4805         void *p_virt = NULL;
4806
4807         p_virt = dma_alloc_coherent(&cdev->pdev->dev,
4808                                     QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
4809         if (!p_virt)
4810                 return -ENOMEM;
4811
4812         qed_chain_init_mem(p_chain, p_virt, p_phys);
4813         qed_chain_reset(p_chain);
4814
4815         return 0;
4816 }
4817
4818 static int
4819 qed_chain_alloc_pbl(struct qed_dev *cdev,
4820                     struct qed_chain *p_chain,
4821                     struct qed_chain_ext_pbl *ext_pbl)
4822 {
4823         u32 page_cnt = p_chain->page_cnt, size, i;
4824         dma_addr_t p_phys = 0, p_pbl_phys = 0;
4825         struct addr_tbl_entry *pp_addr_tbl;
4826         u8 *p_pbl_virt = NULL;
4827         void *p_virt = NULL;
4828
4829         size = page_cnt * sizeof(*pp_addr_tbl);
4830         pp_addr_tbl =  vzalloc(size);
4831         if (!pp_addr_tbl)
4832                 return -ENOMEM;
4833
4834         /* The allocation of the PBL table is done with its full size, since it
4835          * is expected to be successive.
4836          * qed_chain_init_pbl_mem() is called even in a case of an allocation
4837          * failure, since tbl was previously allocated, and it
4838          * should be saved to allow its freeing during the error flow.
4839          */
4840         size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
4841
4842         if (!ext_pbl) {
4843                 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
4844                                                 size, &p_pbl_phys, GFP_KERNEL);
4845         } else {
4846                 p_pbl_virt = ext_pbl->p_pbl_virt;
4847                 p_pbl_phys = ext_pbl->p_pbl_phys;
4848                 p_chain->b_external_pbl = true;
4849         }
4850
4851         qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys, pp_addr_tbl);
4852         if (!p_pbl_virt)
4853                 return -ENOMEM;
4854
4855         for (i = 0; i < page_cnt; i++) {
4856                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
4857                                             QED_CHAIN_PAGE_SIZE,
4858                                             &p_phys, GFP_KERNEL);
4859                 if (!p_virt)
4860                         return -ENOMEM;
4861
4862                 if (i == 0) {
4863                         qed_chain_init_mem(p_chain, p_virt, p_phys);
4864                         qed_chain_reset(p_chain);
4865                 }
4866
4867                 /* Fill the PBL table with the physical address of the page */
4868                 *(dma_addr_t *)p_pbl_virt = p_phys;
4869                 /* Keep the virtual address of the page */
4870                 p_chain->pbl.pp_addr_tbl[i].virt_addr = p_virt;
4871                 p_chain->pbl.pp_addr_tbl[i].dma_map = p_phys;
4872
4873                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
4874         }
4875
4876         return 0;
4877 }
4878
4879 int qed_chain_alloc(struct qed_dev *cdev,
4880                     enum qed_chain_use_mode intended_use,
4881                     enum qed_chain_mode mode,
4882                     enum qed_chain_cnt_type cnt_type,
4883                     u32 num_elems,
4884                     size_t elem_size,
4885                     struct qed_chain *p_chain,
4886                     struct qed_chain_ext_pbl *ext_pbl)
4887 {
4888         u32 page_cnt;
4889         int rc = 0;
4890
4891         if (mode == QED_CHAIN_MODE_SINGLE)
4892                 page_cnt = 1;
4893         else
4894                 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
4895
4896         rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
4897         if (rc) {
4898                 DP_NOTICE(cdev,
4899                           "Cannot allocate a chain with the given arguments:\n");
4900                 DP_NOTICE(cdev,
4901                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
4902                           intended_use, mode, cnt_type, num_elems, elem_size);
4903                 return rc;
4904         }
4905
4906         qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
4907                               mode, cnt_type);
4908
4909         switch (mode) {
4910         case QED_CHAIN_MODE_NEXT_PTR:
4911                 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
4912                 break;
4913         case QED_CHAIN_MODE_SINGLE:
4914                 rc = qed_chain_alloc_single(cdev, p_chain);
4915                 break;
4916         case QED_CHAIN_MODE_PBL:
4917                 rc = qed_chain_alloc_pbl(cdev, p_chain, ext_pbl);
4918                 break;
4919         }
4920         if (rc)
4921                 goto nomem;
4922
4923         return 0;
4924
4925 nomem:
4926         qed_chain_free(cdev, p_chain);
4927         return rc;
4928 }
4929
4930 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
4931 {
4932         if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
4933                 u16 min, max;
4934
4935                 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
4936                 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
4937                 DP_NOTICE(p_hwfn,
4938                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4939                           src_id, min, max);
4940
4941                 return -EINVAL;
4942         }
4943
4944         *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
4945
4946         return 0;
4947 }
4948
4949 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
4950 {
4951         if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
4952                 u8 min, max;
4953
4954                 min = (u8)RESC_START(p_hwfn, QED_VPORT);
4955                 max = min + RESC_NUM(p_hwfn, QED_VPORT);
4956                 DP_NOTICE(p_hwfn,
4957                           "vport id [%d] is not valid, available indices [%d - %d]\n",
4958                           src_id, min, max);
4959
4960                 return -EINVAL;
4961         }
4962
4963         *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
4964
4965         return 0;
4966 }
4967
4968 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
4969 {
4970         if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
4971                 u8 min, max;
4972
4973                 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
4974                 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
4975                 DP_NOTICE(p_hwfn,
4976                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4977                           src_id, min, max);
4978
4979                 return -EINVAL;
4980         }
4981
4982         *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
4983
4984         return 0;
4985 }
4986
4987 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
4988                             u32 hw_addr, void *p_eth_qzone,
4989                             size_t eth_qzone_size, u8 timeset)
4990 {
4991         struct coalescing_timeset *p_coal_timeset;
4992
4993         if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
4994                 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
4995                 return -EINVAL;
4996         }
4997
4998         p_coal_timeset = p_eth_qzone;
4999         memset(p_eth_qzone, 0, eth_qzone_size);
5000         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
5001         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
5002         qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
5003
5004         return 0;
5005 }
5006
5007 int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle)
5008 {
5009         struct qed_queue_cid *p_cid = p_handle;
5010         struct qed_hwfn *p_hwfn;
5011         struct qed_ptt *p_ptt;
5012         int rc = 0;
5013
5014         p_hwfn = p_cid->p_owner;
5015
5016         if (IS_VF(p_hwfn->cdev))
5017                 return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid);
5018
5019         p_ptt = qed_ptt_acquire(p_hwfn);
5020         if (!p_ptt)
5021                 return -EAGAIN;
5022
5023         if (rx_coal) {
5024                 rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
5025                 if (rc)
5026                         goto out;
5027                 p_hwfn->cdev->rx_coalesce_usecs = rx_coal;
5028         }
5029
5030         if (tx_coal) {
5031                 rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
5032                 if (rc)
5033                         goto out;
5034                 p_hwfn->cdev->tx_coalesce_usecs = tx_coal;
5035         }
5036 out:
5037         qed_ptt_release(p_hwfn, p_ptt);
5038         return rc;
5039 }
5040
5041 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn,
5042                          struct qed_ptt *p_ptt,
5043                          u16 coalesce, struct qed_queue_cid *p_cid)
5044 {
5045         struct ustorm_eth_queue_zone eth_qzone;
5046         u8 timeset, timer_res;
5047         u32 address;
5048         int rc;
5049
5050         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5051         if (coalesce <= 0x7F) {
5052                 timer_res = 0;
5053         } else if (coalesce <= 0xFF) {
5054                 timer_res = 1;
5055         } else if (coalesce <= 0x1FF) {
5056                 timer_res = 2;
5057         } else {
5058                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5059                 return -EINVAL;
5060         }
5061         timeset = (u8)(coalesce >> timer_res);
5062
5063         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5064                                    p_cid->sb_igu_id, false);
5065         if (rc)
5066                 goto out;
5067
5068         address = BAR0_MAP_REG_USDM_RAM +
5069                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5070
5071         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
5072                               sizeof(struct ustorm_eth_queue_zone), timeset);
5073         if (rc)
5074                 goto out;
5075
5076 out:
5077         return rc;
5078 }
5079
5080 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn,
5081                          struct qed_ptt *p_ptt,
5082                          u16 coalesce, struct qed_queue_cid *p_cid)
5083 {
5084         struct xstorm_eth_queue_zone eth_qzone;
5085         u8 timeset, timer_res;
5086         u32 address;
5087         int rc;
5088
5089         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5090         if (coalesce <= 0x7F) {
5091                 timer_res = 0;
5092         } else if (coalesce <= 0xFF) {
5093                 timer_res = 1;
5094         } else if (coalesce <= 0x1FF) {
5095                 timer_res = 2;
5096         } else {
5097                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5098                 return -EINVAL;
5099         }
5100         timeset = (u8)(coalesce >> timer_res);
5101
5102         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5103                                    p_cid->sb_igu_id, true);
5104         if (rc)
5105                 goto out;
5106
5107         address = BAR0_MAP_REG_XSDM_RAM +
5108                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5109
5110         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
5111                               sizeof(struct xstorm_eth_queue_zone), timeset);
5112 out:
5113         return rc;
5114 }
5115
5116 /* Calculate final WFQ values for all vports and configure them.
5117  * After this configuration each vport will have
5118  * approx min rate =  min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
5119  */
5120 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
5121                                              struct qed_ptt *p_ptt,
5122                                              u32 min_pf_rate)
5123 {
5124         struct init_qm_vport_params *vport_params;
5125         int i;
5126
5127         vport_params = p_hwfn->qm_info.qm_vport_params;
5128
5129         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5130                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5131
5132                 vport_params[i].wfq = (wfq_speed * QED_WFQ_UNIT) /
5133                                                 min_pf_rate;
5134                 qed_init_vport_wfq(p_hwfn, p_ptt,
5135                                    vport_params[i].first_tx_pq_id,
5136                                    vport_params[i].wfq);
5137         }
5138 }
5139
5140 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
5141                                        u32 min_pf_rate)
5142
5143 {
5144         int i;
5145
5146         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
5147                 p_hwfn->qm_info.qm_vport_params[i].wfq = 1;
5148 }
5149
5150 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
5151                                            struct qed_ptt *p_ptt,
5152                                            u32 min_pf_rate)
5153 {
5154         struct init_qm_vport_params *vport_params;
5155         int i;
5156
5157         vport_params = p_hwfn->qm_info.qm_vport_params;
5158
5159         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5160                 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
5161                 qed_init_vport_wfq(p_hwfn, p_ptt,
5162                                    vport_params[i].first_tx_pq_id,
5163                                    vport_params[i].wfq);
5164         }
5165 }
5166
5167 /* This function performs several validations for WFQ
5168  * configuration and required min rate for a given vport
5169  * 1. req_rate must be greater than one percent of min_pf_rate.
5170  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
5171  *    rates to get less than one percent of min_pf_rate.
5172  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
5173  */
5174 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
5175                               u16 vport_id, u32 req_rate, u32 min_pf_rate)
5176 {
5177         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
5178         int non_requested_count = 0, req_count = 0, i, num_vports;
5179
5180         num_vports = p_hwfn->qm_info.num_vports;
5181
5182         /* Accounting for the vports which are configured for WFQ explicitly */
5183         for (i = 0; i < num_vports; i++) {
5184                 u32 tmp_speed;
5185
5186                 if ((i != vport_id) &&
5187                     p_hwfn->qm_info.wfq_data[i].configured) {
5188                         req_count++;
5189                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5190                         total_req_min_rate += tmp_speed;
5191                 }
5192         }
5193
5194         /* Include current vport data as well */
5195         req_count++;
5196         total_req_min_rate += req_rate;
5197         non_requested_count = num_vports - req_count;
5198
5199         if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
5200                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5201                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5202                            vport_id, req_rate, min_pf_rate);
5203                 return -EINVAL;
5204         }
5205
5206         if (num_vports > QED_WFQ_UNIT) {
5207                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5208                            "Number of vports is greater than %d\n",
5209                            QED_WFQ_UNIT);
5210                 return -EINVAL;
5211         }
5212
5213         if (total_req_min_rate > min_pf_rate) {
5214                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5215                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5216                            total_req_min_rate, min_pf_rate);
5217                 return -EINVAL;
5218         }
5219
5220         total_left_rate = min_pf_rate - total_req_min_rate;
5221
5222         left_rate_per_vp = total_left_rate / non_requested_count;
5223         if (left_rate_per_vp <  min_pf_rate / QED_WFQ_UNIT) {
5224                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5225                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5226                            left_rate_per_vp, min_pf_rate);
5227                 return -EINVAL;
5228         }
5229
5230         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
5231         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
5232
5233         for (i = 0; i < num_vports; i++) {
5234                 if (p_hwfn->qm_info.wfq_data[i].configured)
5235                         continue;
5236
5237                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
5238         }
5239
5240         return 0;
5241 }
5242
5243 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
5244                                      struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
5245 {
5246         struct qed_mcp_link_state *p_link;
5247         int rc = 0;
5248
5249         p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
5250
5251         if (!p_link->min_pf_rate) {
5252                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
5253                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
5254                 return rc;
5255         }
5256
5257         rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
5258
5259         if (!rc)
5260                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
5261                                                  p_link->min_pf_rate);
5262         else
5263                 DP_NOTICE(p_hwfn,
5264                           "Validation failed while configuring min rate\n");
5265
5266         return rc;
5267 }
5268
5269 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
5270                                                  struct qed_ptt *p_ptt,
5271                                                  u32 min_pf_rate)
5272 {
5273         bool use_wfq = false;
5274         int rc = 0;
5275         u16 i;
5276
5277         /* Validate all pre configured vports for wfq */
5278         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5279                 u32 rate;
5280
5281                 if (!p_hwfn->qm_info.wfq_data[i].configured)
5282                         continue;
5283
5284                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
5285                 use_wfq = true;
5286
5287                 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
5288                 if (rc) {
5289                         DP_NOTICE(p_hwfn,
5290                                   "WFQ validation failed while configuring min rate\n");
5291                         break;
5292                 }
5293         }
5294
5295         if (!rc && use_wfq)
5296                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5297         else
5298                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5299
5300         return rc;
5301 }
5302
5303 /* Main API for qed clients to configure vport min rate.
5304  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
5305  * rate - Speed in Mbps needs to be assigned to a given vport.
5306  */
5307 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
5308 {
5309         int i, rc = -EINVAL;
5310
5311         /* Currently not supported; Might change in future */
5312         if (cdev->num_hwfns > 1) {
5313                 DP_NOTICE(cdev,
5314                           "WFQ configuration is not supported for this device\n");
5315                 return rc;
5316         }
5317
5318         for_each_hwfn(cdev, i) {
5319                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5320                 struct qed_ptt *p_ptt;
5321
5322                 p_ptt = qed_ptt_acquire(p_hwfn);
5323                 if (!p_ptt)
5324                         return -EBUSY;
5325
5326                 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
5327
5328                 if (rc) {
5329                         qed_ptt_release(p_hwfn, p_ptt);
5330                         return rc;
5331                 }
5332
5333                 qed_ptt_release(p_hwfn, p_ptt);
5334         }
5335
5336         return rc;
5337 }
5338
5339 /* API to configure WFQ from mcp link change */
5340 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
5341                                          struct qed_ptt *p_ptt, u32 min_pf_rate)
5342 {
5343         int i;
5344
5345         if (cdev->num_hwfns > 1) {
5346                 DP_VERBOSE(cdev,
5347                            NETIF_MSG_LINK,
5348                            "WFQ configuration is not supported for this device\n");
5349                 return;
5350         }
5351
5352         for_each_hwfn(cdev, i) {
5353                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5354
5355                 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
5356                                                       min_pf_rate);
5357         }
5358 }
5359
5360 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
5361                                      struct qed_ptt *p_ptt,
5362                                      struct qed_mcp_link_state *p_link,
5363                                      u8 max_bw)
5364 {
5365         int rc = 0;
5366
5367         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
5368
5369         if (!p_link->line_speed && (max_bw != 100))
5370                 return rc;
5371
5372         p_link->speed = (p_link->line_speed * max_bw) / 100;
5373         p_hwfn->qm_info.pf_rl = p_link->speed;
5374
5375         /* Since the limiter also affects Tx-switched traffic, we don't want it
5376          * to limit such traffic in case there's no actual limit.
5377          * In that case, set limit to imaginary high boundary.
5378          */
5379         if (max_bw == 100)
5380                 p_hwfn->qm_info.pf_rl = 100000;
5381
5382         rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
5383                             p_hwfn->qm_info.pf_rl);
5384
5385         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5386                    "Configured MAX bandwidth to be %08x Mb/sec\n",
5387                    p_link->speed);
5388
5389         return rc;
5390 }
5391
5392 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
5393 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
5394 {
5395         int i, rc = -EINVAL;
5396
5397         if (max_bw < 1 || max_bw > 100) {
5398                 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
5399                 return rc;
5400         }
5401
5402         for_each_hwfn(cdev, i) {
5403                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5404                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
5405                 struct qed_mcp_link_state *p_link;
5406                 struct qed_ptt *p_ptt;
5407
5408                 p_link = &p_lead->mcp_info->link_output;
5409
5410                 p_ptt = qed_ptt_acquire(p_hwfn);
5411                 if (!p_ptt)
5412                         return -EBUSY;
5413
5414                 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5415                                                       p_link, max_bw);
5416
5417                 qed_ptt_release(p_hwfn, p_ptt);
5418
5419                 if (rc)
5420                         break;
5421         }
5422
5423         return rc;
5424 }
5425
5426 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
5427                                      struct qed_ptt *p_ptt,
5428                                      struct qed_mcp_link_state *p_link,
5429                                      u8 min_bw)
5430 {
5431         int rc = 0;
5432
5433         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5434         p_hwfn->qm_info.pf_wfq = min_bw;
5435
5436         if (!p_link->line_speed)
5437                 return rc;
5438
5439         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5440
5441         rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5442
5443         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5444                    "Configured MIN bandwidth to be %d Mb/sec\n",
5445                    p_link->min_pf_rate);
5446
5447         return rc;
5448 }
5449
5450 /* Main API to configure PF min bandwidth where bw range is [1-100] */
5451 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
5452 {
5453         int i, rc = -EINVAL;
5454
5455         if (min_bw < 1 || min_bw > 100) {
5456                 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
5457                 return rc;
5458         }
5459
5460         for_each_hwfn(cdev, i) {
5461                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5462                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
5463                 struct qed_mcp_link_state *p_link;
5464                 struct qed_ptt *p_ptt;
5465
5466                 p_link = &p_lead->mcp_info->link_output;
5467
5468                 p_ptt = qed_ptt_acquire(p_hwfn);
5469                 if (!p_ptt)
5470                         return -EBUSY;
5471
5472                 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5473                                                       p_link, min_bw);
5474                 if (rc) {
5475                         qed_ptt_release(p_hwfn, p_ptt);
5476                         return rc;
5477                 }
5478
5479                 if (p_link->min_pf_rate) {
5480                         u32 min_rate = p_link->min_pf_rate;
5481
5482                         rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
5483                                                                    p_ptt,
5484                                                                    min_rate);
5485                 }
5486
5487                 qed_ptt_release(p_hwfn, p_ptt);
5488         }
5489
5490         return rc;
5491 }
5492
5493 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
5494 {
5495         struct qed_mcp_link_state *p_link;
5496
5497         p_link = &p_hwfn->mcp_info->link_output;
5498
5499         if (p_link->min_pf_rate)
5500                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
5501                                                p_link->min_pf_rate);
5502
5503         memset(p_hwfn->qm_info.wfq_data, 0,
5504                sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
5505 }
5506
5507 int qed_device_num_ports(struct qed_dev *cdev)
5508 {
5509         return cdev->num_ports;
5510 }
5511
5512 void qed_set_fw_mac_addr(__le16 *fw_msb,
5513                          __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
5514 {
5515         ((u8 *)fw_msb)[0] = mac[1];
5516         ((u8 *)fw_msb)[1] = mac[0];
5517         ((u8 *)fw_mid)[0] = mac[3];
5518         ((u8 *)fw_mid)[1] = mac[2];
5519         ((u8 *)fw_lsb)[0] = mac[5];
5520         ((u8 *)fw_lsb)[1] = mac[4];
5521 }