1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/types.h>
34 #include <asm/byteorder.h>
36 #include <linux/delay.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/errno.h>
39 #include <linux/kernel.h>
40 #include <linux/mutex.h>
41 #include <linux/pci.h>
42 #include <linux/slab.h>
43 #include <linux/string.h>
44 #include <linux/vmalloc.h>
45 #include <linux/etherdevice.h>
46 #include <linux/qed/qed_chain.h>
47 #include <linux/qed/qed_if.h>
51 #include "qed_dev_api.h"
55 #include "qed_init_ops.h"
57 #include "qed_iscsi.h"
61 #include "qed_reg_addr.h"
63 #include "qed_sriov.h"
67 static DEFINE_SPINLOCK(qm_lock);
69 /******************** Doorbell Recovery *******************/
70 /* The doorbell recovery mechanism consists of a list of entries which represent
71 * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
72 * entity needs to register with the mechanism and provide the parameters
73 * describing it's doorbell, including a location where last used doorbell data
74 * can be found. The doorbell execute function will traverse the list and
75 * doorbell all of the registered entries.
77 struct qed_db_recovery_entry {
78 struct list_head list_entry;
79 void __iomem *db_addr;
81 enum qed_db_rec_width db_width;
82 enum qed_db_rec_space db_space;
86 /* Display a single doorbell recovery entry */
87 static void qed_db_recovery_dp_entry(struct qed_hwfn *p_hwfn,
88 struct qed_db_recovery_entry *db_entry,
93 "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
98 db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
99 db_entry->db_space == DB_REC_USER ? "user" : "kernel",
103 /* Doorbell address sanity (address within doorbell bar range) */
104 static bool qed_db_rec_sanity(struct qed_dev *cdev,
105 void __iomem *db_addr,
106 enum qed_db_rec_width db_width,
109 u32 width = (db_width == DB_REC_WIDTH_32B) ? 32 : 64;
111 /* Make sure doorbell address is within the doorbell bar */
112 if (db_addr < cdev->doorbells ||
113 (u8 __iomem *)db_addr + width >
114 (u8 __iomem *)cdev->doorbells + cdev->db_size) {
116 "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
119 (u8 __iomem *)cdev->doorbells + cdev->db_size);
123 /* ake sure doorbell data pointer is not null */
125 WARN(true, "Illegal doorbell data pointer: %p", db_data);
132 /* Find hwfn according to the doorbell address */
133 static struct qed_hwfn *qed_db_rec_find_hwfn(struct qed_dev *cdev,
134 void __iomem *db_addr)
136 struct qed_hwfn *p_hwfn;
138 /* In CMT doorbell bar is split down the middle between engine 0 and enigne 1 */
139 if (cdev->num_hwfns > 1)
140 p_hwfn = db_addr < cdev->hwfns[1].doorbells ?
141 &cdev->hwfns[0] : &cdev->hwfns[1];
143 p_hwfn = QED_LEADING_HWFN(cdev);
148 /* Add a new entry to the doorbell recovery mechanism */
149 int qed_db_recovery_add(struct qed_dev *cdev,
150 void __iomem *db_addr,
152 enum qed_db_rec_width db_width,
153 enum qed_db_rec_space db_space)
155 struct qed_db_recovery_entry *db_entry;
156 struct qed_hwfn *p_hwfn;
158 /* Shortcircuit VFs, for now */
161 QED_MSG_IOV, "db recovery - skipping VF doorbell\n");
165 /* Sanitize doorbell address */
166 if (!qed_db_rec_sanity(cdev, db_addr, db_width, db_data))
169 /* Obtain hwfn from doorbell address */
170 p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr);
173 db_entry = kzalloc(sizeof(*db_entry), GFP_KERNEL);
175 DP_NOTICE(cdev, "Failed to allocate a db recovery entry\n");
180 db_entry->db_addr = db_addr;
181 db_entry->db_data = db_data;
182 db_entry->db_width = db_width;
183 db_entry->db_space = db_space;
184 db_entry->hwfn_idx = p_hwfn->my_id;
187 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
189 /* Protect the list */
190 spin_lock_bh(&p_hwfn->db_recovery_info.lock);
191 list_add_tail(&db_entry->list_entry, &p_hwfn->db_recovery_info.list);
192 spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
197 /* Remove an entry from the doorbell recovery mechanism */
198 int qed_db_recovery_del(struct qed_dev *cdev,
199 void __iomem *db_addr, void *db_data)
201 struct qed_db_recovery_entry *db_entry = NULL;
202 struct qed_hwfn *p_hwfn;
205 /* Shortcircuit VFs, for now */
208 QED_MSG_IOV, "db recovery - skipping VF doorbell\n");
212 /* Obtain hwfn from doorbell address */
213 p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr);
215 /* Protect the list */
216 spin_lock_bh(&p_hwfn->db_recovery_info.lock);
217 list_for_each_entry(db_entry,
218 &p_hwfn->db_recovery_info.list, list_entry) {
219 /* search according to db_data addr since db_addr is not unique (roce) */
220 if (db_entry->db_data == db_data) {
221 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Deleting");
222 list_del(&db_entry->list_entry);
228 spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
233 "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
241 /* Initialize the doorbell recovery mechanism */
242 static int qed_db_recovery_setup(struct qed_hwfn *p_hwfn)
244 DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Setting up db recovery\n");
246 /* Make sure db_size was set in cdev */
247 if (!p_hwfn->cdev->db_size) {
248 DP_ERR(p_hwfn->cdev, "db_size not set\n");
252 INIT_LIST_HEAD(&p_hwfn->db_recovery_info.list);
253 spin_lock_init(&p_hwfn->db_recovery_info.lock);
254 p_hwfn->db_recovery_info.db_recovery_counter = 0;
259 /* Destroy the doorbell recovery mechanism */
260 static void qed_db_recovery_teardown(struct qed_hwfn *p_hwfn)
262 struct qed_db_recovery_entry *db_entry = NULL;
264 DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Tearing down db recovery\n");
265 if (!list_empty(&p_hwfn->db_recovery_info.list)) {
268 "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
269 while (!list_empty(&p_hwfn->db_recovery_info.list)) {
271 list_first_entry(&p_hwfn->db_recovery_info.list,
272 struct qed_db_recovery_entry,
274 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
275 list_del(&db_entry->list_entry);
279 p_hwfn->db_recovery_info.db_recovery_counter = 0;
282 /* Print the content of the doorbell recovery mechanism */
283 void qed_db_recovery_dp(struct qed_hwfn *p_hwfn)
285 struct qed_db_recovery_entry *db_entry = NULL;
288 "Displaying doorbell recovery database. Counter was %d\n",
289 p_hwfn->db_recovery_info.db_recovery_counter);
291 /* Protect the list */
292 spin_lock_bh(&p_hwfn->db_recovery_info.lock);
293 list_for_each_entry(db_entry,
294 &p_hwfn->db_recovery_info.list, list_entry) {
295 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
298 spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
301 /* Ring the doorbell of a single doorbell recovery entry */
302 static void qed_db_recovery_ring(struct qed_hwfn *p_hwfn,
303 struct qed_db_recovery_entry *db_entry)
305 /* Print according to width */
306 if (db_entry->db_width == DB_REC_WIDTH_32B) {
307 DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
308 "ringing doorbell address %p data %x\n",
310 *(u32 *)db_entry->db_data);
312 DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
313 "ringing doorbell address %p data %llx\n",
315 *(u64 *)(db_entry->db_data));
319 if (!qed_db_rec_sanity(p_hwfn->cdev, db_entry->db_addr,
320 db_entry->db_width, db_entry->db_data))
323 /* Flush the write combined buffer. Since there are multiple doorbelling
324 * entities using the same address, if we don't flush, a transaction
329 /* Ring the doorbell */
330 if (db_entry->db_width == DB_REC_WIDTH_32B)
331 DIRECT_REG_WR(db_entry->db_addr,
332 *(u32 *)(db_entry->db_data));
334 DIRECT_REG_WR64(db_entry->db_addr,
335 *(u64 *)(db_entry->db_data));
337 /* Flush the write combined buffer. Next doorbell may come from a
338 * different entity to the same address...
343 /* Traverse the doorbell recovery entry list and ring all the doorbells */
344 void qed_db_recovery_execute(struct qed_hwfn *p_hwfn)
346 struct qed_db_recovery_entry *db_entry = NULL;
348 DP_NOTICE(p_hwfn, "Executing doorbell recovery. Counter was %d\n",
349 p_hwfn->db_recovery_info.db_recovery_counter);
351 /* Track amount of times recovery was executed */
352 p_hwfn->db_recovery_info.db_recovery_counter++;
354 /* Protect the list */
355 spin_lock_bh(&p_hwfn->db_recovery_info.lock);
356 list_for_each_entry(db_entry,
357 &p_hwfn->db_recovery_info.list, list_entry)
358 qed_db_recovery_ring(p_hwfn, db_entry);
359 spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
362 /******************** Doorbell Recovery end ****************/
364 /********************************** NIG LLH ***********************************/
366 enum qed_llh_filter_type {
367 QED_LLH_FILTER_TYPE_MAC,
368 QED_LLH_FILTER_TYPE_PROTOCOL,
371 struct qed_llh_mac_filter {
375 struct qed_llh_protocol_filter {
376 enum qed_llh_prot_filter_type_t type;
377 u16 source_port_or_eth_type;
381 union qed_llh_filter {
382 struct qed_llh_mac_filter mac;
383 struct qed_llh_protocol_filter protocol;
386 struct qed_llh_filter_info {
389 enum qed_llh_filter_type type;
390 union qed_llh_filter filter;
393 struct qed_llh_info {
394 /* Number of LLH filters banks */
397 #define MAX_NUM_PPFID 8
398 u8 ppfid_array[MAX_NUM_PPFID];
400 /* Array of filters arrays:
401 * "num_ppfid" elements of filters banks, where each is an array of
402 * "NIG_REG_LLH_FUNC_FILTER_EN_SIZE" filters.
404 struct qed_llh_filter_info **pp_filters;
407 static void qed_llh_free(struct qed_dev *cdev)
409 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
413 if (p_llh_info->pp_filters)
414 for (i = 0; i < p_llh_info->num_ppfid; i++)
415 kfree(p_llh_info->pp_filters[i]);
417 kfree(p_llh_info->pp_filters);
421 cdev->p_llh_info = NULL;
424 static int qed_llh_alloc(struct qed_dev *cdev)
426 struct qed_llh_info *p_llh_info;
429 p_llh_info = kzalloc(sizeof(*p_llh_info), GFP_KERNEL);
432 cdev->p_llh_info = p_llh_info;
434 for (i = 0; i < MAX_NUM_PPFID; i++) {
435 if (!(cdev->ppfid_bitmap & (0x1 << i)))
438 p_llh_info->ppfid_array[p_llh_info->num_ppfid] = i;
439 DP_VERBOSE(cdev, QED_MSG_SP, "ppfid_array[%d] = %hhd\n",
440 p_llh_info->num_ppfid, i);
441 p_llh_info->num_ppfid++;
444 size = p_llh_info->num_ppfid * sizeof(*p_llh_info->pp_filters);
445 p_llh_info->pp_filters = kzalloc(size, GFP_KERNEL);
446 if (!p_llh_info->pp_filters)
449 size = NIG_REG_LLH_FUNC_FILTER_EN_SIZE *
450 sizeof(**p_llh_info->pp_filters);
451 for (i = 0; i < p_llh_info->num_ppfid; i++) {
452 p_llh_info->pp_filters[i] = kzalloc(size, GFP_KERNEL);
453 if (!p_llh_info->pp_filters[i])
460 static int qed_llh_shadow_sanity(struct qed_dev *cdev,
461 u8 ppfid, u8 filter_idx, const char *action)
463 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
465 if (ppfid >= p_llh_info->num_ppfid) {
467 "LLH shadow [%s]: using ppfid %d while only %d ppfids are available\n",
468 action, ppfid, p_llh_info->num_ppfid);
472 if (filter_idx >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
474 "LLH shadow [%s]: using filter_idx %d while only %d filters are available\n",
475 action, filter_idx, NIG_REG_LLH_FUNC_FILTER_EN_SIZE);
482 #define QED_LLH_INVALID_FILTER_IDX 0xff
485 qed_llh_shadow_search_filter(struct qed_dev *cdev,
487 union qed_llh_filter *p_filter, u8 *p_filter_idx)
489 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
490 struct qed_llh_filter_info *p_filters;
494 rc = qed_llh_shadow_sanity(cdev, ppfid, 0, "search");
498 *p_filter_idx = QED_LLH_INVALID_FILTER_IDX;
500 p_filters = p_llh_info->pp_filters[ppfid];
501 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
502 if (!memcmp(p_filter, &p_filters[i].filter,
503 sizeof(*p_filter))) {
513 qed_llh_shadow_get_free_idx(struct qed_dev *cdev, u8 ppfid, u8 *p_filter_idx)
515 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
516 struct qed_llh_filter_info *p_filters;
520 rc = qed_llh_shadow_sanity(cdev, ppfid, 0, "get_free_idx");
524 *p_filter_idx = QED_LLH_INVALID_FILTER_IDX;
526 p_filters = p_llh_info->pp_filters[ppfid];
527 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
528 if (!p_filters[i].b_enabled) {
538 __qed_llh_shadow_add_filter(struct qed_dev *cdev,
541 enum qed_llh_filter_type type,
542 union qed_llh_filter *p_filter, u32 *p_ref_cnt)
544 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
545 struct qed_llh_filter_info *p_filters;
548 rc = qed_llh_shadow_sanity(cdev, ppfid, filter_idx, "add");
552 p_filters = p_llh_info->pp_filters[ppfid];
553 if (!p_filters[filter_idx].ref_cnt) {
554 p_filters[filter_idx].b_enabled = true;
555 p_filters[filter_idx].type = type;
556 memcpy(&p_filters[filter_idx].filter, p_filter,
557 sizeof(p_filters[filter_idx].filter));
560 *p_ref_cnt = ++p_filters[filter_idx].ref_cnt;
566 qed_llh_shadow_add_filter(struct qed_dev *cdev,
568 enum qed_llh_filter_type type,
569 union qed_llh_filter *p_filter,
570 u8 *p_filter_idx, u32 *p_ref_cnt)
574 /* Check if the same filter already exist */
575 rc = qed_llh_shadow_search_filter(cdev, ppfid, p_filter, p_filter_idx);
579 /* Find a new entry in case of a new filter */
580 if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) {
581 rc = qed_llh_shadow_get_free_idx(cdev, ppfid, p_filter_idx);
586 /* No free entry was found */
587 if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) {
589 "Failed to find an empty LLH filter to utilize [ppfid %d]\n",
594 return __qed_llh_shadow_add_filter(cdev, ppfid, *p_filter_idx, type,
595 p_filter, p_ref_cnt);
599 __qed_llh_shadow_remove_filter(struct qed_dev *cdev,
600 u8 ppfid, u8 filter_idx, u32 *p_ref_cnt)
602 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
603 struct qed_llh_filter_info *p_filters;
606 rc = qed_llh_shadow_sanity(cdev, ppfid, filter_idx, "remove");
610 p_filters = p_llh_info->pp_filters[ppfid];
611 if (!p_filters[filter_idx].ref_cnt) {
613 "LLH shadow: trying to remove a filter with ref_cnt=0\n");
617 *p_ref_cnt = --p_filters[filter_idx].ref_cnt;
618 if (!p_filters[filter_idx].ref_cnt)
619 memset(&p_filters[filter_idx],
620 0, sizeof(p_filters[filter_idx]));
626 qed_llh_shadow_remove_filter(struct qed_dev *cdev,
628 union qed_llh_filter *p_filter,
629 u8 *p_filter_idx, u32 *p_ref_cnt)
633 rc = qed_llh_shadow_search_filter(cdev, ppfid, p_filter, p_filter_idx);
637 /* No matching filter was found */
638 if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) {
639 DP_NOTICE(cdev, "Failed to find a filter in the LLH shadow\n");
643 return __qed_llh_shadow_remove_filter(cdev, ppfid, *p_filter_idx,
647 static int qed_llh_abs_ppfid(struct qed_dev *cdev, u8 ppfid, u8 *p_abs_ppfid)
649 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
651 if (ppfid >= p_llh_info->num_ppfid) {
653 "ppfid %d is not valid, available indices are 0..%hhd\n",
654 ppfid, p_llh_info->num_ppfid - 1);
659 *p_abs_ppfid = p_llh_info->ppfid_array[ppfid];
665 qed_llh_set_engine_affin(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
667 struct qed_dev *cdev = p_hwfn->cdev;
672 rc = qed_mcp_get_engine_config(p_hwfn, p_ptt);
673 if (rc != 0 && rc != -EOPNOTSUPP) {
675 "Failed to get the engine affinity configuration\n");
679 /* RoCE PF is bound to a single engine */
680 if (QED_IS_ROCE_PERSONALITY(p_hwfn)) {
681 eng = cdev->fir_affin ? QED_ENG1 : QED_ENG0;
682 rc = qed_llh_set_roce_affinity(cdev, eng);
685 "Failed to set the RoCE engine affinity\n");
691 "LLH: Set the engine affinity of RoCE packets as %d\n",
695 /* Storage PF is bound to a single engine while L2 PF uses both */
696 if (QED_IS_FCOE_PERSONALITY(p_hwfn) || QED_IS_ISCSI_PERSONALITY(p_hwfn))
697 eng = cdev->fir_affin ? QED_ENG1 : QED_ENG0;
698 else /* L2_PERSONALITY */
701 for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) {
702 rc = qed_llh_set_ppfid_affinity(cdev, ppfid, eng);
705 "Failed to set the engine affinity of ppfid %d\n",
711 DP_VERBOSE(cdev, QED_MSG_SP,
712 "LLH: Set the engine affinity of non-RoCE packets as %d\n",
718 static int qed_llh_hw_init_pf(struct qed_hwfn *p_hwfn,
719 struct qed_ptt *p_ptt)
721 struct qed_dev *cdev = p_hwfn->cdev;
725 for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) {
728 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
732 addr = NIG_REG_LLH_PPFID2PFID_TBL_0 + abs_ppfid * 0x4;
733 qed_wr(p_hwfn, p_ptt, addr, p_hwfn->rel_pf_id);
736 if (test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits) &&
737 !QED_IS_FCOE_PERSONALITY(p_hwfn)) {
738 rc = qed_llh_add_mac_filter(cdev, 0,
739 p_hwfn->hw_info.hw_mac_addr);
742 "Failed to add an LLH filter with the primary MAC\n");
745 if (QED_IS_CMT(cdev)) {
746 rc = qed_llh_set_engine_affin(p_hwfn, p_ptt);
754 u8 qed_llh_get_num_ppfid(struct qed_dev *cdev)
756 return cdev->p_llh_info->num_ppfid;
759 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_MASK 0x3
760 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_SHIFT 0
761 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_MASK 0x3
762 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_SHIFT 2
764 int qed_llh_set_ppfid_affinity(struct qed_dev *cdev, u8 ppfid, enum qed_eng eng)
766 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
767 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
768 u32 addr, val, eng_sel;
775 if (!QED_IS_CMT(cdev))
778 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
793 DP_NOTICE(cdev, "Invalid affinity value for ppfid [%d]\n", eng);
798 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
799 val = qed_rd(p_hwfn, p_ptt, addr);
800 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE, eng_sel);
801 qed_wr(p_hwfn, p_ptt, addr, val);
803 /* The iWARP affinity is set as the affinity of ppfid 0 */
804 if (!ppfid && QED_IS_IWARP_PERSONALITY(p_hwfn))
805 cdev->iwarp_affin = (eng == QED_ENG1) ? 1 : 0;
807 qed_ptt_release(p_hwfn, p_ptt);
812 int qed_llh_set_roce_affinity(struct qed_dev *cdev, enum qed_eng eng)
814 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
815 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
816 u32 addr, val, eng_sel;
823 if (!QED_IS_CMT(cdev))
835 qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL,
836 0xf); /* QP bit 15 */
839 DP_NOTICE(cdev, "Invalid affinity value for RoCE [%d]\n", eng);
844 for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) {
845 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
849 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
850 val = qed_rd(p_hwfn, p_ptt, addr);
851 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_ROCE, eng_sel);
852 qed_wr(p_hwfn, p_ptt, addr, val);
855 qed_ptt_release(p_hwfn, p_ptt);
860 struct qed_llh_filter_details {
869 qed_llh_access_filter(struct qed_hwfn *p_hwfn,
870 struct qed_ptt *p_ptt,
873 struct qed_llh_filter_details *p_details)
875 struct qed_dmae_params params = {0};
880 /* The NIG/LLH registers that are accessed in this function have only 16
881 * rows which are exposed to a PF. I.e. only the 16 filters of its
882 * default ppfid. Accessing filters of other ppfids requires pretending
884 * The calculation of PPFID->PFID in AH is based on the relative index
885 * of a PF on its port.
886 * For BB the pfid is actually the abs_ppfid.
888 if (QED_IS_BB(p_hwfn->cdev))
891 pfid = abs_ppfid * p_hwfn->cdev->num_ports_in_engine +
894 /* Filter enable - should be done first when removing a filter */
895 if (!p_details->enable) {
896 qed_fid_pretend(p_hwfn, p_ptt,
897 pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
899 addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4;
900 qed_wr(p_hwfn, p_ptt, addr, p_details->enable);
902 qed_fid_pretend(p_hwfn, p_ptt,
904 PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
908 addr = NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * filter_idx * 0x4;
910 SET_FIELD(params.flags, QED_DMAE_PARAMS_DST_PF_VALID, 0x1);
911 params.dst_pfid = pfid;
912 rc = qed_dmae_host2grc(p_hwfn,
914 (u64)(uintptr_t)&p_details->value,
915 addr, 2 /* size_in_dwords */,
920 qed_fid_pretend(p_hwfn, p_ptt,
921 pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
924 addr = NIG_REG_LLH_FUNC_FILTER_MODE + filter_idx * 0x4;
925 qed_wr(p_hwfn, p_ptt, addr, p_details->mode);
927 /* Filter protocol type */
928 addr = NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + filter_idx * 0x4;
929 qed_wr(p_hwfn, p_ptt, addr, p_details->protocol_type);
931 /* Filter header select */
932 addr = NIG_REG_LLH_FUNC_FILTER_HDR_SEL + filter_idx * 0x4;
933 qed_wr(p_hwfn, p_ptt, addr, p_details->hdr_sel);
935 /* Filter enable - should be done last when adding a filter */
936 if (p_details->enable) {
937 addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4;
938 qed_wr(p_hwfn, p_ptt, addr, p_details->enable);
941 qed_fid_pretend(p_hwfn, p_ptt,
943 PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
949 qed_llh_add_filter(struct qed_hwfn *p_hwfn,
950 struct qed_ptt *p_ptt,
952 u8 filter_idx, u8 filter_prot_type, u32 high, u32 low)
954 struct qed_llh_filter_details filter_details;
956 filter_details.enable = 1;
957 filter_details.value = ((u64)high << 32) | low;
958 filter_details.hdr_sel = 0;
959 filter_details.protocol_type = filter_prot_type;
960 /* Mode: 0: MAC-address classification 1: protocol classification */
961 filter_details.mode = filter_prot_type ? 1 : 0;
963 return qed_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
968 qed_llh_remove_filter(struct qed_hwfn *p_hwfn,
969 struct qed_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx)
971 struct qed_llh_filter_details filter_details = {0};
973 return qed_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
977 int qed_llh_add_mac_filter(struct qed_dev *cdev,
978 u8 ppfid, u8 mac_addr[ETH_ALEN])
980 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
981 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
982 union qed_llh_filter filter = {};
983 u8 filter_idx, abs_ppfid;
984 u32 high, low, ref_cnt;
990 if (!test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits))
993 memcpy(filter.mac.addr, mac_addr, ETH_ALEN);
994 rc = qed_llh_shadow_add_filter(cdev, ppfid,
995 QED_LLH_FILTER_TYPE_MAC,
996 &filter, &filter_idx, &ref_cnt);
1000 /* Configure the LLH only in case of a new the filter */
1002 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1006 high = mac_addr[1] | (mac_addr[0] << 8);
1007 low = mac_addr[5] | (mac_addr[4] << 8) | (mac_addr[3] << 16) |
1008 (mac_addr[2] << 24);
1009 rc = qed_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1017 "LLH: Added MAC filter [%pM] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1018 mac_addr, ppfid, abs_ppfid, filter_idx, ref_cnt);
1022 err: DP_NOTICE(cdev,
1023 "LLH: Failed to add MAC filter [%pM] to ppfid %hhd\n",
1026 qed_ptt_release(p_hwfn, p_ptt);
1032 qed_llh_protocol_filter_stringify(struct qed_dev *cdev,
1033 enum qed_llh_prot_filter_type_t type,
1034 u16 source_port_or_eth_type,
1035 u16 dest_port, u8 *str, size_t str_len)
1038 case QED_LLH_FILTER_ETHERTYPE:
1039 snprintf(str, str_len, "Ethertype 0x%04x",
1040 source_port_or_eth_type);
1042 case QED_LLH_FILTER_TCP_SRC_PORT:
1043 snprintf(str, str_len, "TCP src port 0x%04x",
1044 source_port_or_eth_type);
1046 case QED_LLH_FILTER_UDP_SRC_PORT:
1047 snprintf(str, str_len, "UDP src port 0x%04x",
1048 source_port_or_eth_type);
1050 case QED_LLH_FILTER_TCP_DEST_PORT:
1051 snprintf(str, str_len, "TCP dst port 0x%04x", dest_port);
1053 case QED_LLH_FILTER_UDP_DEST_PORT:
1054 snprintf(str, str_len, "UDP dst port 0x%04x", dest_port);
1056 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1057 snprintf(str, str_len, "TCP src/dst ports 0x%04x/0x%04x",
1058 source_port_or_eth_type, dest_port);
1060 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1061 snprintf(str, str_len, "UDP src/dst ports 0x%04x/0x%04x",
1062 source_port_or_eth_type, dest_port);
1066 "Non valid LLH protocol filter type %d\n", type);
1074 qed_llh_protocol_filter_to_hilo(struct qed_dev *cdev,
1075 enum qed_llh_prot_filter_type_t type,
1076 u16 source_port_or_eth_type,
1077 u16 dest_port, u32 *p_high, u32 *p_low)
1083 case QED_LLH_FILTER_ETHERTYPE:
1084 *p_high = source_port_or_eth_type;
1086 case QED_LLH_FILTER_TCP_SRC_PORT:
1087 case QED_LLH_FILTER_UDP_SRC_PORT:
1088 *p_low = source_port_or_eth_type << 16;
1090 case QED_LLH_FILTER_TCP_DEST_PORT:
1091 case QED_LLH_FILTER_UDP_DEST_PORT:
1094 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1095 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1096 *p_low = (source_port_or_eth_type << 16) | dest_port;
1100 "Non valid LLH protocol filter type %d\n", type);
1108 qed_llh_add_protocol_filter(struct qed_dev *cdev,
1110 enum qed_llh_prot_filter_type_t type,
1111 u16 source_port_or_eth_type, u16 dest_port)
1113 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1114 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
1115 u8 filter_idx, abs_ppfid, str[32], type_bitmap;
1116 union qed_llh_filter filter = {};
1117 u32 high, low, ref_cnt;
1123 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits))
1126 rc = qed_llh_protocol_filter_stringify(cdev, type,
1127 source_port_or_eth_type,
1128 dest_port, str, sizeof(str));
1132 filter.protocol.type = type;
1133 filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1134 filter.protocol.dest_port = dest_port;
1135 rc = qed_llh_shadow_add_filter(cdev,
1137 QED_LLH_FILTER_TYPE_PROTOCOL,
1138 &filter, &filter_idx, &ref_cnt);
1142 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1146 /* Configure the LLH only in case of a new the filter */
1148 rc = qed_llh_protocol_filter_to_hilo(cdev, type,
1149 source_port_or_eth_type,
1150 dest_port, &high, &low);
1154 type_bitmap = 0x1 << type;
1155 rc = qed_llh_add_filter(p_hwfn, p_ptt, abs_ppfid,
1156 filter_idx, type_bitmap, high, low);
1163 "LLH: Added protocol filter [%s] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1164 str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1168 err: DP_NOTICE(p_hwfn,
1169 "LLH: Failed to add protocol filter [%s] to ppfid %hhd\n",
1172 qed_ptt_release(p_hwfn, p_ptt);
1177 void qed_llh_remove_mac_filter(struct qed_dev *cdev,
1178 u8 ppfid, u8 mac_addr[ETH_ALEN])
1180 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1181 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
1182 union qed_llh_filter filter = {};
1183 u8 filter_idx, abs_ppfid;
1190 if (!test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits))
1193 ether_addr_copy(filter.mac.addr, mac_addr);
1194 rc = qed_llh_shadow_remove_filter(cdev, ppfid, &filter, &filter_idx,
1199 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1203 /* Remove from the LLH in case the filter is not in use */
1205 rc = qed_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1213 "LLH: Removed MAC filter [%pM] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1214 mac_addr, ppfid, abs_ppfid, filter_idx, ref_cnt);
1218 err: DP_NOTICE(cdev,
1219 "LLH: Failed to remove MAC filter [%pM] from ppfid %hhd\n",
1222 qed_ptt_release(p_hwfn, p_ptt);
1225 void qed_llh_remove_protocol_filter(struct qed_dev *cdev,
1227 enum qed_llh_prot_filter_type_t type,
1228 u16 source_port_or_eth_type, u16 dest_port)
1230 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1231 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
1232 u8 filter_idx, abs_ppfid, str[32];
1233 union qed_llh_filter filter = {};
1240 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits))
1243 rc = qed_llh_protocol_filter_stringify(cdev, type,
1244 source_port_or_eth_type,
1245 dest_port, str, sizeof(str));
1249 filter.protocol.type = type;
1250 filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1251 filter.protocol.dest_port = dest_port;
1252 rc = qed_llh_shadow_remove_filter(cdev, ppfid, &filter, &filter_idx,
1257 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1261 /* Remove from the LLH in case the filter is not in use */
1263 rc = qed_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1271 "LLH: Removed protocol filter [%s] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1272 str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1276 err: DP_NOTICE(cdev,
1277 "LLH: Failed to remove protocol filter [%s] from ppfid %hhd\n",
1280 qed_ptt_release(p_hwfn, p_ptt);
1283 /******************************* NIG LLH - End ********************************/
1285 #define QED_MIN_DPIS (4)
1286 #define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS)
1288 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
1289 struct qed_ptt *p_ptt, enum BAR_ID bar_id)
1291 u32 bar_reg = (bar_id == BAR_ID_0 ?
1292 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
1295 if (IS_VF(p_hwfn->cdev))
1296 return qed_vf_hw_bar_size(p_hwfn, bar_id);
1298 val = qed_rd(p_hwfn, p_ptt, bar_reg);
1300 return 1 << (val + 15);
1302 /* Old MFW initialized above registered only conditionally */
1303 if (p_hwfn->cdev->num_hwfns > 1) {
1305 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
1306 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
1309 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
1314 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
1318 cdev->dp_level = dp_level;
1319 cdev->dp_module = dp_module;
1320 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1321 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1323 p_hwfn->dp_level = dp_level;
1324 p_hwfn->dp_module = dp_module;
1328 void qed_init_struct(struct qed_dev *cdev)
1332 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1333 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1335 p_hwfn->cdev = cdev;
1337 p_hwfn->b_active = false;
1339 mutex_init(&p_hwfn->dmae_info.mutex);
1342 /* hwfn 0 is always active */
1343 cdev->hwfns[0].b_active = true;
1345 /* set the default cache alignment to 128 */
1346 cdev->cache_shift = 7;
1349 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
1351 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1353 kfree(qm_info->qm_pq_params);
1354 qm_info->qm_pq_params = NULL;
1355 kfree(qm_info->qm_vport_params);
1356 qm_info->qm_vport_params = NULL;
1357 kfree(qm_info->qm_port_params);
1358 qm_info->qm_port_params = NULL;
1359 kfree(qm_info->wfq_data);
1360 qm_info->wfq_data = NULL;
1363 static void qed_dbg_user_data_free(struct qed_hwfn *p_hwfn)
1365 kfree(p_hwfn->dbg_user_info);
1366 p_hwfn->dbg_user_info = NULL;
1369 void qed_resc_free(struct qed_dev *cdev)
1371 struct qed_rdma_info *rdma_info;
1372 struct qed_hwfn *p_hwfn;
1376 for_each_hwfn(cdev, i)
1377 qed_l2_free(&cdev->hwfns[i]);
1381 kfree(cdev->fw_data);
1382 cdev->fw_data = NULL;
1384 kfree(cdev->reset_stats);
1385 cdev->reset_stats = NULL;
1389 for_each_hwfn(cdev, i) {
1390 p_hwfn = cdev->hwfns + i;
1391 rdma_info = p_hwfn->p_rdma_info;
1393 qed_cxt_mngr_free(p_hwfn);
1394 qed_qm_info_free(p_hwfn);
1395 qed_spq_free(p_hwfn);
1396 qed_eq_free(p_hwfn);
1397 qed_consq_free(p_hwfn);
1398 qed_int_free(p_hwfn);
1399 #ifdef CONFIG_QED_LL2
1400 qed_ll2_free(p_hwfn);
1402 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
1403 qed_fcoe_free(p_hwfn);
1405 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1406 qed_iscsi_free(p_hwfn);
1407 qed_ooo_free(p_hwfn);
1410 if (QED_IS_RDMA_PERSONALITY(p_hwfn) && rdma_info) {
1411 qed_spq_unregister_async_cb(p_hwfn, rdma_info->proto);
1412 qed_rdma_info_free(p_hwfn);
1415 qed_iov_free(p_hwfn);
1416 qed_l2_free(p_hwfn);
1417 qed_dmae_info_free(p_hwfn);
1418 qed_dcbx_info_free(p_hwfn);
1419 qed_dbg_user_data_free(p_hwfn);
1420 qed_fw_overlay_mem_free(p_hwfn, p_hwfn->fw_overlay_mem);
1422 /* Destroy doorbell recovery mechanism */
1423 qed_db_recovery_teardown(p_hwfn);
1427 /******************** QM initialization *******************/
1428 #define ACTIVE_TCS_BMAP 0x9f
1429 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
1431 /* determines the physical queue flags for a given PF. */
1432 static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn)
1437 flags = PQ_FLAGS_LB;
1440 if (IS_QED_SRIOV(p_hwfn->cdev))
1441 flags |= PQ_FLAGS_VFS;
1443 /* protocol flags */
1444 switch (p_hwfn->hw_info.personality) {
1446 flags |= PQ_FLAGS_MCOS;
1449 flags |= PQ_FLAGS_OFLD;
1452 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
1454 case QED_PCI_ETH_ROCE:
1455 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
1456 if (IS_QED_MULTI_TC_ROCE(p_hwfn))
1457 flags |= PQ_FLAGS_MTC;
1459 case QED_PCI_ETH_IWARP:
1460 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
1465 "unknown personality %d\n", p_hwfn->hw_info.personality);
1472 /* Getters for resource amounts necessary for qm initialization */
1473 static u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn)
1475 return p_hwfn->hw_info.num_hw_tc;
1478 static u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn)
1480 return IS_QED_SRIOV(p_hwfn->cdev) ?
1481 p_hwfn->cdev->p_iov_info->total_vfs : 0;
1484 static u8 qed_init_qm_get_num_mtc_tcs(struct qed_hwfn *p_hwfn)
1486 u32 pq_flags = qed_get_pq_flags(p_hwfn);
1488 if (!(PQ_FLAGS_MTC & pq_flags))
1491 return qed_init_qm_get_num_tcs(p_hwfn);
1494 #define NUM_DEFAULT_RLS 1
1496 static u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
1498 u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
1500 /* num RLs can't exceed resource amount of rls or vports */
1501 num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
1502 RESC_NUM(p_hwfn, QED_VPORT));
1504 /* Make sure after we reserve there's something left */
1505 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
1508 /* subtract rls necessary for VFs and one default one for the PF */
1509 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
1514 static u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn)
1516 u32 pq_flags = qed_get_pq_flags(p_hwfn);
1518 /* all pqs share the same vport, except for vfs and pf_rl pqs */
1519 return (!!(PQ_FLAGS_RLS & pq_flags)) *
1520 qed_init_qm_get_num_pf_rls(p_hwfn) +
1521 (!!(PQ_FLAGS_VFS & pq_flags)) *
1522 qed_init_qm_get_num_vfs(p_hwfn) + 1;
1525 /* calc amount of PQs according to the requested flags */
1526 static u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn)
1528 u32 pq_flags = qed_get_pq_flags(p_hwfn);
1530 return (!!(PQ_FLAGS_RLS & pq_flags)) *
1531 qed_init_qm_get_num_pf_rls(p_hwfn) +
1532 (!!(PQ_FLAGS_MCOS & pq_flags)) *
1533 qed_init_qm_get_num_tcs(p_hwfn) +
1534 (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) +
1535 (!!(PQ_FLAGS_ACK & pq_flags)) +
1536 (!!(PQ_FLAGS_OFLD & pq_flags)) *
1537 qed_init_qm_get_num_mtc_tcs(p_hwfn) +
1538 (!!(PQ_FLAGS_LLT & pq_flags)) *
1539 qed_init_qm_get_num_mtc_tcs(p_hwfn) +
1540 (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn);
1543 /* initialize the top level QM params */
1544 static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
1546 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1549 /* pq and vport bases for this PF */
1550 qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
1551 qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
1553 /* rate limiting and weighted fair queueing are always enabled */
1554 qm_info->vport_rl_en = true;
1555 qm_info->vport_wfq_en = true;
1557 /* TC config is different for AH 4 port */
1558 four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2;
1560 /* in AH 4 port we have fewer TCs per port */
1561 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
1564 /* unless MFW indicated otherwise, ooo_tc == 3 for
1565 * AH 4-port and 4 otherwise.
1567 if (!qm_info->ooo_tc)
1568 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
1572 /* initialize qm vport params */
1573 static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn)
1575 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1578 /* all vports participate in weighted fair queueing */
1579 for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++)
1580 qm_info->qm_vport_params[i].wfq = 1;
1583 /* initialize qm port params */
1584 static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
1586 /* Initialize qm port parameters */
1587 u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine;
1588 struct qed_dev *cdev = p_hwfn->cdev;
1590 /* indicate how ooo and high pri traffic is dealt with */
1591 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
1592 ACTIVE_TCS_BMAP_4PORT_K2 :
1595 for (i = 0; i < num_ports; i++) {
1596 struct init_qm_port_params *p_qm_port =
1597 &p_hwfn->qm_info.qm_port_params[i];
1598 u16 pbf_max_cmd_lines;
1600 p_qm_port->active = 1;
1601 p_qm_port->active_phys_tcs = active_phys_tcs;
1602 pbf_max_cmd_lines = (u16)NUM_OF_PBF_CMD_LINES(cdev);
1603 p_qm_port->num_pbf_cmd_lines = pbf_max_cmd_lines / num_ports;
1604 p_qm_port->num_btb_blocks = NUM_OF_BTB_BLOCKS(cdev) / num_ports;
1608 /* Reset the params which must be reset for qm init. QM init may be called as
1609 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
1610 * params may be affected by the init but would simply recalculate to the same
1611 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
1612 * affected as these amounts stay the same.
1614 static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn)
1616 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1618 qm_info->num_pqs = 0;
1619 qm_info->num_vports = 0;
1620 qm_info->num_pf_rls = 0;
1621 qm_info->num_vf_pqs = 0;
1622 qm_info->first_vf_pq = 0;
1623 qm_info->first_mcos_pq = 0;
1624 qm_info->first_rl_pq = 0;
1627 static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
1629 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1631 qm_info->num_vports++;
1633 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
1635 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
1636 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
1639 /* initialize a single pq and manage qm_info resources accounting.
1640 * The pq_init_flags param determines whether the PQ is rate limited
1641 * (for VF or PF) and whether a new vport is allocated to the pq or not
1642 * (i.e. vport will be shared).
1645 /* flags for pq init */
1646 #define PQ_INIT_SHARE_VPORT (1 << 0)
1647 #define PQ_INIT_PF_RL (1 << 1)
1648 #define PQ_INIT_VF_RL (1 << 2)
1650 /* defines for pq init */
1651 #define PQ_INIT_DEFAULT_WRR_GROUP 1
1652 #define PQ_INIT_DEFAULT_TC 0
1654 void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc)
1656 p_info->offload_tc = tc;
1657 p_info->offload_tc_set = true;
1660 static bool qed_is_offload_tc_set(struct qed_hwfn *p_hwfn)
1662 return p_hwfn->hw_info.offload_tc_set;
1665 static u32 qed_get_offload_tc(struct qed_hwfn *p_hwfn)
1667 if (qed_is_offload_tc_set(p_hwfn))
1668 return p_hwfn->hw_info.offload_tc;
1670 return PQ_INIT_DEFAULT_TC;
1673 static void qed_init_qm_pq(struct qed_hwfn *p_hwfn,
1674 struct qed_qm_info *qm_info,
1675 u8 tc, u32 pq_init_flags)
1677 u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn);
1679 if (pq_idx > max_pq)
1681 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
1683 /* init pq params */
1684 qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
1685 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
1686 qm_info->num_vports;
1687 qm_info->qm_pq_params[pq_idx].tc_id = tc;
1688 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
1689 qm_info->qm_pq_params[pq_idx].rl_valid =
1690 (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
1692 /* qm params accounting */
1694 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
1695 qm_info->num_vports++;
1697 if (pq_init_flags & PQ_INIT_PF_RL)
1698 qm_info->num_pf_rls++;
1700 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
1702 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
1703 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
1705 if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn))
1707 "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n",
1708 qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn));
1711 /* get pq index according to PQ_FLAGS */
1712 static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn,
1713 unsigned long pq_flags)
1715 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1717 /* Can't have multiple flags set here */
1718 if (bitmap_weight(&pq_flags,
1719 sizeof(pq_flags) * BITS_PER_BYTE) > 1) {
1720 DP_ERR(p_hwfn, "requested multiple pq flags 0x%lx\n", pq_flags);
1724 if (!(qed_get_pq_flags(p_hwfn) & pq_flags)) {
1725 DP_ERR(p_hwfn, "pq flag 0x%lx is not set\n", pq_flags);
1731 return &qm_info->first_rl_pq;
1733 return &qm_info->first_mcos_pq;
1735 return &qm_info->pure_lb_pq;
1737 return &qm_info->ooo_pq;
1739 return &qm_info->pure_ack_pq;
1741 return &qm_info->first_ofld_pq;
1743 return &qm_info->first_llt_pq;
1745 return &qm_info->first_vf_pq;
1751 return &qm_info->start_pq;
1754 /* save pq index in qm info */
1755 static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn,
1756 u32 pq_flags, u16 pq_val)
1758 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
1760 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
1763 /* get tx pq index, with the PQ TX base already set (ready for context init) */
1764 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags)
1766 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
1768 return *base_pq_idx + CM_TX_PQ_BASE;
1771 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc)
1773 u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn);
1776 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
1778 return p_hwfn->qm_info.start_pq;
1782 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
1784 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc);
1787 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf)
1789 u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn);
1792 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
1794 return p_hwfn->qm_info.start_pq;
1798 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
1800 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf);
1803 u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc)
1805 u16 first_ofld_pq, pq_offset;
1807 first_ofld_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD);
1808 pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
1809 tc : PQ_INIT_DEFAULT_TC;
1811 return first_ofld_pq + pq_offset;
1814 u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc)
1816 u16 first_llt_pq, pq_offset;
1818 first_llt_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LLT);
1819 pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
1820 tc : PQ_INIT_DEFAULT_TC;
1822 return first_llt_pq + pq_offset;
1825 /* Functions for creating specific types of pqs */
1826 static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn)
1828 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1830 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
1833 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
1834 qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
1837 static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn)
1839 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1841 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
1844 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
1845 qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
1848 static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn)
1850 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1852 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
1855 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
1856 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
1857 PQ_INIT_SHARE_VPORT);
1860 static void qed_init_qm_mtc_pqs(struct qed_hwfn *p_hwfn)
1862 u8 num_tcs = qed_init_qm_get_num_mtc_tcs(p_hwfn);
1863 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1866 /* override pq's TC if offload TC is set */
1867 for (tc = 0; tc < num_tcs; tc++)
1868 qed_init_qm_pq(p_hwfn, qm_info,
1869 qed_is_offload_tc_set(p_hwfn) ?
1870 p_hwfn->hw_info.offload_tc : tc,
1871 PQ_INIT_SHARE_VPORT);
1874 static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn)
1876 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1878 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
1881 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
1882 qed_init_qm_mtc_pqs(p_hwfn);
1885 static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn)
1887 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1889 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
1892 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
1893 qed_init_qm_mtc_pqs(p_hwfn);
1896 static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn)
1898 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1901 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
1904 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
1905 for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++)
1906 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
1909 static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn)
1911 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1912 u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
1914 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
1917 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
1918 qm_info->num_vf_pqs = num_vfs;
1919 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
1920 qed_init_qm_pq(p_hwfn,
1921 qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
1924 static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn)
1926 u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn);
1927 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1929 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
1932 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
1933 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
1934 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
1938 static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn)
1940 /* rate limited pqs, must come first (FW assumption) */
1941 qed_init_qm_rl_pqs(p_hwfn);
1943 /* pqs for multi cos */
1944 qed_init_qm_mcos_pqs(p_hwfn);
1946 /* pure loopback pq */
1947 qed_init_qm_lb_pq(p_hwfn);
1949 /* out of order pq */
1950 qed_init_qm_ooo_pq(p_hwfn);
1953 qed_init_qm_pure_ack_pq(p_hwfn);
1955 /* pq for offloaded protocol */
1956 qed_init_qm_offload_pq(p_hwfn);
1958 /* low latency pq */
1959 qed_init_qm_low_latency_pq(p_hwfn);
1961 /* done sharing vports */
1962 qed_init_qm_advance_vport(p_hwfn);
1965 qed_init_qm_vf_pqs(p_hwfn);
1968 /* compare values of getters against resources amounts */
1969 static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn)
1971 if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) {
1972 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
1976 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
1979 if (QED_IS_ROCE_PERSONALITY(p_hwfn)) {
1980 p_hwfn->hw_info.multi_tc_roce_en = false;
1982 "multi-tc roce was disabled to reduce requested amount of pqs\n");
1983 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
1987 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
1991 static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn)
1993 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1994 struct init_qm_vport_params *vport;
1995 struct init_qm_port_params *port;
1996 struct init_qm_pq_params *pq;
1999 /* top level params */
2002 "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, llt_pq %d, pure_ack_pq %d\n",
2004 qm_info->start_vport,
2005 qm_info->pure_lb_pq,
2006 qm_info->first_ofld_pq,
2007 qm_info->first_llt_pq,
2008 qm_info->pure_ack_pq);
2011 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
2013 qm_info->first_vf_pq,
2015 qm_info->num_vf_pqs,
2016 qm_info->num_vports, qm_info->max_phys_tcs_per_port);
2019 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
2022 qm_info->vport_rl_en,
2023 qm_info->vport_wfq_en,
2026 qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn));
2029 for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) {
2030 port = &(qm_info->qm_port_params[i]);
2033 "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
2036 port->active_phys_tcs,
2037 port->num_pbf_cmd_lines,
2038 port->num_btb_blocks, port->reserved);
2042 for (i = 0; i < qm_info->num_vports; i++) {
2043 vport = &(qm_info->qm_vport_params[i]);
2046 "vport idx %d, wfq %d, first_tx_pq_id [ ",
2047 qm_info->start_vport + i, vport->wfq);
2048 for (tc = 0; tc < NUM_OF_TCS; tc++)
2051 "%d ", vport->first_tx_pq_id[tc]);
2052 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n");
2056 for (i = 0; i < qm_info->num_pqs; i++) {
2057 pq = &(qm_info->qm_pq_params[i]);
2060 "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d rl_id %d\n",
2061 qm_info->start_pq + i,
2064 pq->tc_id, pq->wrr_group, pq->rl_valid, pq->rl_id);
2068 static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
2070 /* reset params required for init run */
2071 qed_init_qm_reset_params(p_hwfn);
2073 /* init QM top level params */
2074 qed_init_qm_params(p_hwfn);
2076 /* init QM port params */
2077 qed_init_qm_port_params(p_hwfn);
2079 /* init QM vport params */
2080 qed_init_qm_vport_params(p_hwfn);
2082 /* init QM physical queue params */
2083 qed_init_qm_pq_params(p_hwfn);
2085 /* display all that init */
2086 qed_dp_init_qm_params(p_hwfn);
2089 /* This function reconfigures the QM pf on the fly.
2090 * For this purpose we:
2091 * 1. reconfigure the QM database
2092 * 2. set new values to runtime array
2093 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
2094 * 4. activate init tool in QM_PF stage
2095 * 5. send an sdm_qm_cmd through rbc interface to release the QM
2097 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2099 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
2103 /* initialize qed's qm data structure */
2104 qed_init_qm_info(p_hwfn);
2106 /* stop PF's qm queues */
2107 spin_lock_bh(&qm_lock);
2108 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
2109 qm_info->start_pq, qm_info->num_pqs);
2110 spin_unlock_bh(&qm_lock);
2114 /* prepare QM portion of runtime array */
2115 qed_qm_init_pf(p_hwfn, p_ptt, false);
2117 /* activate init tool on runtime array */
2118 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
2119 p_hwfn->hw_info.hw_mode);
2123 /* start PF's qm queues */
2124 spin_lock_bh(&qm_lock);
2125 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
2126 qm_info->start_pq, qm_info->num_pqs);
2127 spin_unlock_bh(&qm_lock);
2134 static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn)
2136 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
2139 rc = qed_init_qm_sanity(p_hwfn);
2143 qm_info->qm_pq_params = kcalloc(qed_init_qm_get_num_pqs(p_hwfn),
2144 sizeof(*qm_info->qm_pq_params),
2146 if (!qm_info->qm_pq_params)
2149 qm_info->qm_vport_params = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
2150 sizeof(*qm_info->qm_vport_params),
2152 if (!qm_info->qm_vport_params)
2155 qm_info->qm_port_params = kcalloc(p_hwfn->cdev->num_ports_in_engine,
2156 sizeof(*qm_info->qm_port_params),
2158 if (!qm_info->qm_port_params)
2161 qm_info->wfq_data = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
2162 sizeof(*qm_info->wfq_data),
2164 if (!qm_info->wfq_data)
2170 DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
2171 qed_qm_info_free(p_hwfn);
2175 int qed_resc_alloc(struct qed_dev *cdev)
2177 u32 rdma_tasks, excess_tasks;
2182 for_each_hwfn(cdev, i) {
2183 rc = qed_l2_alloc(&cdev->hwfns[i]);
2190 cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
2194 for_each_hwfn(cdev, i) {
2195 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2196 u32 n_eqes, num_cons;
2198 /* Initialize the doorbell recovery mechanism */
2199 rc = qed_db_recovery_setup(p_hwfn);
2203 /* First allocate the context manager structure */
2204 rc = qed_cxt_mngr_alloc(p_hwfn);
2208 /* Set the HW cid/tid numbers (in the contest manager)
2209 * Must be done prior to any further computations.
2211 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
2215 rc = qed_alloc_qm_data(p_hwfn);
2220 qed_init_qm_info(p_hwfn);
2222 /* Compute the ILT client partition */
2223 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
2226 "too many ILT lines; re-computing with less lines\n");
2227 /* In case there are not enough ILT lines we reduce the
2228 * number of RDMA tasks and re-compute.
2231 qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count);
2235 rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
2236 rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks);
2240 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
2243 "failed ILT compute. Requested too many lines: %u\n",
2250 /* CID map / ILT shadow table / T2
2251 * The talbes sizes are determined by the computations above
2253 rc = qed_cxt_tables_alloc(p_hwfn);
2257 /* SPQ, must follow ILT because initializes SPQ context */
2258 rc = qed_spq_alloc(p_hwfn);
2262 /* SP status block allocation */
2263 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
2266 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
2270 rc = qed_iov_alloc(p_hwfn);
2275 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
2276 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2277 u32 n_srq = qed_cxt_get_total_srq_count(p_hwfn);
2278 enum protocol_type rdma_proto;
2280 if (QED_IS_ROCE_PERSONALITY(p_hwfn))
2281 rdma_proto = PROTOCOLID_ROCE;
2283 rdma_proto = PROTOCOLID_IWARP;
2285 num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
2288 /* EQ should be able to get events from all SRQ's
2291 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB + n_srq;
2292 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
2294 qed_cxt_get_proto_cid_count(p_hwfn,
2297 n_eqes += 2 * num_cons;
2300 if (n_eqes > 0xFFFF) {
2302 "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
2307 rc = qed_eq_alloc(p_hwfn, (u16) n_eqes);
2311 rc = qed_consq_alloc(p_hwfn);
2315 rc = qed_l2_alloc(p_hwfn);
2319 #ifdef CONFIG_QED_LL2
2320 if (p_hwfn->using_ll2) {
2321 rc = qed_ll2_alloc(p_hwfn);
2327 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
2328 rc = qed_fcoe_alloc(p_hwfn);
2333 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
2334 rc = qed_iscsi_alloc(p_hwfn);
2337 rc = qed_ooo_alloc(p_hwfn);
2342 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2343 rc = qed_rdma_info_alloc(p_hwfn);
2348 /* DMA info initialization */
2349 rc = qed_dmae_info_alloc(p_hwfn);
2353 /* DCBX initialization */
2354 rc = qed_dcbx_info_alloc(p_hwfn);
2358 rc = qed_dbg_alloc_user_data(p_hwfn, &p_hwfn->dbg_user_info);
2363 rc = qed_llh_alloc(cdev);
2366 "Failed to allocate memory for the llh_info structure\n");
2370 cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
2371 if (!cdev->reset_stats)
2379 qed_resc_free(cdev);
2383 void qed_resc_setup(struct qed_dev *cdev)
2388 for_each_hwfn(cdev, i)
2389 qed_l2_setup(&cdev->hwfns[i]);
2393 for_each_hwfn(cdev, i) {
2394 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2396 qed_cxt_mngr_setup(p_hwfn);
2397 qed_spq_setup(p_hwfn);
2398 qed_eq_setup(p_hwfn);
2399 qed_consq_setup(p_hwfn);
2401 /* Read shadow of current MFW mailbox */
2402 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
2403 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
2404 p_hwfn->mcp_info->mfw_mb_cur,
2405 p_hwfn->mcp_info->mfw_mb_length);
2407 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
2409 qed_l2_setup(p_hwfn);
2410 qed_iov_setup(p_hwfn);
2411 #ifdef CONFIG_QED_LL2
2412 if (p_hwfn->using_ll2)
2413 qed_ll2_setup(p_hwfn);
2415 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
2416 qed_fcoe_setup(p_hwfn);
2418 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
2419 qed_iscsi_setup(p_hwfn);
2420 qed_ooo_setup(p_hwfn);
2425 #define FINAL_CLEANUP_POLL_CNT (100)
2426 #define FINAL_CLEANUP_POLL_TIME (10)
2427 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
2428 struct qed_ptt *p_ptt, u16 id, bool is_vf)
2430 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
2433 addr = GTT_BAR0_MAP_REG_USDM_RAM +
2434 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
2439 command |= X_FINAL_CLEANUP_AGG_INT <<
2440 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
2441 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
2442 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
2443 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
2445 /* Make sure notification is not set before initiating final cleanup */
2446 if (REG_RD(p_hwfn, addr)) {
2448 "Unexpected; Found final cleanup notification before initiating final cleanup\n");
2449 REG_WR(p_hwfn, addr, 0);
2452 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2453 "Sending final cleanup for PFVF[%d] [Command %08x]\n",
2456 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
2458 /* Poll until completion */
2459 while (!REG_RD(p_hwfn, addr) && count--)
2460 msleep(FINAL_CLEANUP_POLL_TIME);
2462 if (REG_RD(p_hwfn, addr))
2466 "Failed to receive FW final cleanup notification\n");
2468 /* Cleanup afterwards */
2469 REG_WR(p_hwfn, addr, 0);
2474 static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
2478 if (QED_IS_BB_B0(p_hwfn->cdev)) {
2479 hw_mode |= 1 << MODE_BB;
2480 } else if (QED_IS_AH(p_hwfn->cdev)) {
2481 hw_mode |= 1 << MODE_K2;
2483 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
2484 p_hwfn->cdev->type);
2488 switch (p_hwfn->cdev->num_ports_in_engine) {
2490 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
2493 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
2496 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
2499 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
2500 p_hwfn->cdev->num_ports_in_engine);
2504 if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits))
2505 hw_mode |= 1 << MODE_MF_SD;
2507 hw_mode |= 1 << MODE_MF_SI;
2509 hw_mode |= 1 << MODE_ASIC;
2511 if (p_hwfn->cdev->num_hwfns > 1)
2512 hw_mode |= 1 << MODE_100G;
2514 p_hwfn->hw_info.hw_mode = hw_mode;
2516 DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
2517 "Configuring function for hw_mode: 0x%08x\n",
2518 p_hwfn->hw_info.hw_mode);
2523 /* Init run time data for all PFs on an engine. */
2524 static void qed_init_cau_rt_data(struct qed_dev *cdev)
2526 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
2529 for_each_hwfn(cdev, i) {
2530 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2531 struct qed_igu_info *p_igu_info;
2532 struct qed_igu_block *p_block;
2533 struct cau_sb_entry sb_entry;
2535 p_igu_info = p_hwfn->hw_info.p_igu_info;
2538 igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) {
2539 p_block = &p_igu_info->entry[igu_sb_id];
2541 if (!p_block->is_pf)
2544 qed_init_cau_sb_entry(p_hwfn, &sb_entry,
2545 p_block->function_id, 0, 0);
2546 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
2552 static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
2553 struct qed_ptt *p_ptt)
2555 u32 val, wr_mbs, cache_line_size;
2557 val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
2570 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2575 cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
2576 switch (cache_line_size) {
2591 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2595 if (L1_CACHE_BYTES > wr_mbs)
2597 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
2598 L1_CACHE_BYTES, wr_mbs);
2600 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
2602 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
2603 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
2607 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
2608 struct qed_ptt *p_ptt, int hw_mode)
2610 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
2611 struct qed_qm_common_rt_init_params params;
2612 struct qed_dev *cdev = p_hwfn->cdev;
2613 u8 vf_id, max_num_vfs;
2618 qed_init_cau_rt_data(cdev);
2620 /* Program GTT windows */
2621 qed_gtt_init(p_hwfn);
2623 if (p_hwfn->mcp_info) {
2624 if (p_hwfn->mcp_info->func_info.bandwidth_max)
2625 qm_info->pf_rl_en = true;
2626 if (p_hwfn->mcp_info->func_info.bandwidth_min)
2627 qm_info->pf_wfq_en = true;
2630 memset(¶ms, 0, sizeof(params));
2631 params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine;
2632 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
2633 params.pf_rl_en = qm_info->pf_rl_en;
2634 params.pf_wfq_en = qm_info->pf_wfq_en;
2635 params.global_rl_en = qm_info->vport_rl_en;
2636 params.vport_wfq_en = qm_info->vport_wfq_en;
2637 params.port_params = qm_info->qm_port_params;
2639 qed_qm_common_rt_init(p_hwfn, ¶ms);
2641 qed_cxt_hw_init_common(p_hwfn);
2643 qed_init_cache_line_size(p_hwfn, p_ptt);
2645 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
2649 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
2650 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
2652 if (QED_IS_BB(p_hwfn->cdev)) {
2653 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
2654 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
2655 qed_fid_pretend(p_hwfn, p_ptt, pf_id);
2656 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2657 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2659 /* pretend to original PF */
2660 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2663 max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
2664 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
2665 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
2666 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
2667 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
2668 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
2669 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
2670 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
2672 /* pretend to original PF */
2673 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2679 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
2680 struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
2682 u32 dpi_bit_shift, dpi_count, dpi_page_size;
2686 /* Calculate DPI size */
2687 n_wids = max_t(u32, QED_MIN_WIDS, n_cpus);
2688 dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids);
2689 dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
2690 dpi_bit_shift = ilog2(dpi_page_size / 4096);
2691 dpi_count = pwm_region_size / dpi_page_size;
2693 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
2694 min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
2696 p_hwfn->dpi_size = dpi_page_size;
2697 p_hwfn->dpi_count = dpi_count;
2699 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
2701 if (dpi_count < min_dpis)
2707 enum QED_ROCE_EDPM_MODE {
2708 QED_ROCE_EDPM_MODE_ENABLE = 0,
2709 QED_ROCE_EDPM_MODE_FORCE_ON = 1,
2710 QED_ROCE_EDPM_MODE_DISABLE = 2,
2713 bool qed_edpm_enabled(struct qed_hwfn *p_hwfn)
2715 if (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm)
2722 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2724 u32 pwm_regsize, norm_regsize;
2725 u32 non_pwm_conn, min_addr_reg1;
2726 u32 db_bar_size, n_cpus = 1;
2732 db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
2733 if (p_hwfn->cdev->num_hwfns > 1)
2736 /* Calculate doorbell regions */
2737 non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
2738 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
2740 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
2742 norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE);
2743 min_addr_reg1 = norm_regsize / 4096;
2744 pwm_regsize = db_bar_size - norm_regsize;
2746 /* Check that the normal and PWM sizes are valid */
2747 if (db_bar_size < norm_regsize) {
2748 DP_ERR(p_hwfn->cdev,
2749 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
2750 db_bar_size, norm_regsize);
2754 if (pwm_regsize < QED_MIN_PWM_REGION) {
2755 DP_ERR(p_hwfn->cdev,
2756 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
2758 QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
2762 /* Calculate number of DPIs */
2763 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
2764 if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
2765 ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
2766 /* Either EDPM is mandatory, or we are attempting to allocate a
2769 n_cpus = num_present_cpus();
2770 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2773 cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
2774 (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
2775 if (cond || p_hwfn->dcbx_no_edpm) {
2776 /* Either EDPM is disabled from user configuration, or it is
2777 * disabled via DCBx, or it is not mandatory and we failed to
2778 * allocated a WID per CPU.
2781 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2784 qed_rdma_dpm_bar(p_hwfn, p_ptt);
2787 p_hwfn->wid_count = (u16) n_cpus;
2790 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s, page_size=%lu\n",
2795 (!qed_edpm_enabled(p_hwfn)) ?
2796 "disabled" : "enabled", PAGE_SIZE);
2800 "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
2802 p_hwfn->pf_params.rdma_pf_params.min_dpis);
2806 p_hwfn->dpi_start_offset = norm_regsize;
2808 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
2809 pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
2810 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
2811 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
2816 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
2817 struct qed_ptt *p_ptt, int hw_mode)
2821 /* In CMT the gate should be cleared by the 2nd hwfn */
2822 if (!QED_IS_CMT(p_hwfn->cdev) || !IS_LEAD_HWFN(p_hwfn))
2823 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
2825 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
2829 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
2834 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
2835 struct qed_ptt *p_ptt,
2836 struct qed_tunnel_info *p_tunn,
2839 enum qed_int_mode int_mode,
2840 bool allow_npar_tx_switch)
2842 u8 rel_pf_id = p_hwfn->rel_pf_id;
2845 if (p_hwfn->mcp_info) {
2846 struct qed_mcp_function_info *p_info;
2848 p_info = &p_hwfn->mcp_info->func_info;
2849 if (p_info->bandwidth_min)
2850 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
2852 /* Update rate limit once we'll actually have a link */
2853 p_hwfn->qm_info.pf_rl = 100000;
2856 qed_cxt_hw_init_pf(p_hwfn, p_ptt);
2858 qed_int_igu_init_rt(p_hwfn);
2860 /* Set VLAN in NIG if needed */
2861 if (hw_mode & BIT(MODE_MF_SD)) {
2862 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
2863 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
2864 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
2865 p_hwfn->hw_info.ovlan);
2867 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2868 "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
2869 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
2873 /* Enable classification by MAC if needed */
2874 if (hw_mode & BIT(MODE_MF_SI)) {
2875 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2876 "Configuring TAGMAC_CLS_TYPE\n");
2877 STORE_RT_REG(p_hwfn,
2878 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
2881 /* Protocol Configuration */
2882 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
2883 (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
2884 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
2885 (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
2886 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
2888 /* Sanity check before the PF init sequence that uses DMAE */
2889 rc = qed_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
2893 /* PF Init sequence */
2894 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
2898 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
2899 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
2903 qed_fw_overlay_init_ram(p_hwfn, p_ptt, p_hwfn->fw_overlay_mem);
2905 /* Pure runtime initializations - directly to the HW */
2906 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
2908 rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
2912 /* Use the leading hwfn since in CMT only NIG #0 is operational */
2913 if (IS_LEAD_HWFN(p_hwfn)) {
2914 rc = qed_llh_hw_init_pf(p_hwfn, p_ptt);
2920 /* enable interrupts */
2921 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
2923 /* send function start command */
2924 rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,
2925 allow_npar_tx_switch);
2927 DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
2930 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
2931 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
2932 qed_wr(p_hwfn, p_ptt,
2933 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
2940 int qed_pglueb_set_pfid_enable(struct qed_hwfn *p_hwfn,
2941 struct qed_ptt *p_ptt, bool b_enable)
2943 u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
2945 /* Configure the PF's internal FID_enable for master transactions */
2946 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
2948 /* Wait until value is set - try for 1 second every 50us */
2949 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
2950 val = qed_rd(p_hwfn, p_ptt,
2951 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2955 usleep_range(50, 60);
2958 if (val != set_val) {
2960 "PFID_ENABLE_MASTER wasn't changed after a second\n");
2967 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
2968 struct qed_ptt *p_main_ptt)
2970 /* Read shadow of current MFW mailbox */
2971 qed_mcp_read_mb(p_hwfn, p_main_ptt);
2972 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
2973 p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
2977 qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
2978 struct qed_drv_load_params *p_drv_load)
2980 memset(p_load_req, 0, sizeof(*p_load_req));
2982 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2983 QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
2984 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2985 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2986 p_load_req->override_force_load = p_drv_load->override_force_load;
2989 static int qed_vf_start(struct qed_hwfn *p_hwfn,
2990 struct qed_hw_init_params *p_params)
2992 if (p_params->p_tunn) {
2993 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2994 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2997 p_hwfn->b_int_enabled = true;
3002 static void qed_pglueb_clear_err(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3004 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
3005 BIT(p_hwfn->abs_pf_id));
3008 int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
3010 struct qed_load_req_params load_req_params;
3011 u32 load_code, resp, param, drv_mb_param;
3012 bool b_default_mtu = true;
3013 struct qed_hwfn *p_hwfn;
3014 const u32 *fw_overlays;
3015 u32 fw_overlays_len;
3019 if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
3020 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
3025 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
3030 for_each_hwfn(cdev, i) {
3031 p_hwfn = &cdev->hwfns[i];
3033 /* If management didn't provide a default, set one of our own */
3034 if (!p_hwfn->hw_info.mtu) {
3035 p_hwfn->hw_info.mtu = 1500;
3036 b_default_mtu = false;
3040 qed_vf_start(p_hwfn, p_params);
3044 rc = qed_calc_hw_mode(p_hwfn);
3048 if (IS_PF(cdev) && (test_bit(QED_MF_8021Q_TAGGING,
3050 test_bit(QED_MF_8021AD_TAGGING,
3052 if (test_bit(QED_MF_8021Q_TAGGING, &cdev->mf_bits))
3053 ether_type = ETH_P_8021Q;
3055 ether_type = ETH_P_8021AD;
3056 STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3058 STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3060 STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3062 STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
3066 qed_fill_load_req_params(&load_req_params,
3067 p_params->p_drv_load_params);
3068 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
3071 DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
3075 load_code = load_req_params.load_code;
3076 DP_VERBOSE(p_hwfn, QED_MSG_SP,
3077 "Load request was sent. Load code: 0x%x\n",
3080 /* Only relevant for recovery:
3081 * Clear the indication after LOAD_REQ is responded by the MFW.
3083 cdev->recov_in_prog = false;
3085 qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
3087 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
3089 /* Clean up chip from previous driver if such remains exist.
3090 * This is not needed when the PF is the first one on the
3091 * engine, since afterwards we are going to init the FW.
3093 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
3094 rc = qed_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
3095 p_hwfn->rel_pf_id, false);
3097 qed_hw_err_notify(p_hwfn, p_hwfn->p_main_ptt,
3098 QED_HW_ERR_RAMROD_FAIL,
3099 "Final cleanup failed\n");
3104 /* Log and clear previous pglue_b errors if such exist */
3105 qed_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt);
3107 /* Enable the PF's internal FID_enable in the PXP */
3108 rc = qed_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
3113 /* Clear the pglue_b was_error indication.
3114 * In E4 it must be done after the BME and the internal
3115 * FID_enable for the PF are set, since VDMs may cause the
3116 * indication to be set again.
3118 qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
3120 fw_overlays = cdev->fw_data->fw_overlays;
3121 fw_overlays_len = cdev->fw_data->fw_overlays_len;
3122 p_hwfn->fw_overlay_mem =
3123 qed_fw_overlay_mem_alloc(p_hwfn, fw_overlays,
3125 if (!p_hwfn->fw_overlay_mem) {
3127 "Failed to allocate fw overlay memory\n");
3132 switch (load_code) {
3133 case FW_MSG_CODE_DRV_LOAD_ENGINE:
3134 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
3135 p_hwfn->hw_info.hw_mode);
3139 case FW_MSG_CODE_DRV_LOAD_PORT:
3140 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
3141 p_hwfn->hw_info.hw_mode);
3146 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
3147 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
3149 p_hwfn->hw_info.hw_mode,
3150 p_params->b_hw_start,
3152 p_params->allow_npar_tx_switch);
3156 "Unexpected load code [0x%08x]", load_code);
3163 "init phase failed for loadcode 0x%x (rc %d)\n",
3168 rc = qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
3172 /* send DCBX attention request command */
3175 "sending phony dcbx set command to trigger DCBx attention handling\n");
3176 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3177 DRV_MSG_CODE_SET_DCBX,
3178 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
3182 "Failed to send DCBX attention request\n");
3186 p_hwfn->hw_init_done = true;
3190 p_hwfn = QED_LEADING_HWFN(cdev);
3192 /* Get pre-negotiated values for stag, bandwidth etc. */
3195 "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
3196 drv_mb_param = 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET;
3197 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3198 DRV_MSG_CODE_GET_OEM_UPDATES,
3199 drv_mb_param, &resp, ¶m);
3202 "Failed to send GET_OEM_UPDATES attention request\n");
3204 drv_mb_param = STORM_FW_VERSION;
3205 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3206 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
3207 drv_mb_param, &load_code, ¶m);
3209 DP_INFO(p_hwfn, "Failed to update firmware version\n");
3211 if (!b_default_mtu) {
3212 rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
3213 p_hwfn->hw_info.mtu);
3216 "Failed to update default mtu\n");
3219 rc = qed_mcp_ov_update_driver_state(p_hwfn,
3221 QED_OV_DRIVER_STATE_DISABLED);
3223 DP_INFO(p_hwfn, "Failed to update driver state\n");
3225 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
3226 QED_OV_ESWITCH_NONE);
3228 DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
3234 /* The MFW load lock should be released also when initialization fails.
3236 qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
3240 #define QED_HW_STOP_RETRY_LIMIT (10)
3241 static void qed_hw_timers_stop(struct qed_dev *cdev,
3242 struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3247 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
3248 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
3250 if (cdev->recov_in_prog)
3253 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
3254 if ((!qed_rd(p_hwfn, p_ptt,
3255 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
3256 (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
3259 /* Dependent on number of connection/tasks, possibly
3260 * 1ms sleep is required between polls
3262 usleep_range(1000, 2000);
3265 if (i < QED_HW_STOP_RETRY_LIMIT)
3269 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
3270 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
3271 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
3274 void qed_hw_timers_stop_all(struct qed_dev *cdev)
3278 for_each_hwfn(cdev, j) {
3279 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
3280 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
3282 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
3286 int qed_hw_stop(struct qed_dev *cdev)
3288 struct qed_hwfn *p_hwfn;
3289 struct qed_ptt *p_ptt;
3293 for_each_hwfn(cdev, j) {
3294 p_hwfn = &cdev->hwfns[j];
3295 p_ptt = p_hwfn->p_main_ptt;
3297 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
3300 qed_vf_pf_int_cleanup(p_hwfn);
3301 rc = qed_vf_pf_reset(p_hwfn);
3304 "qed_vf_pf_reset failed. rc = %d.\n",
3311 /* mark the hw as uninitialized... */
3312 p_hwfn->hw_init_done = false;
3314 /* Send unload command to MCP */
3315 if (!cdev->recov_in_prog) {
3316 rc = qed_mcp_unload_req(p_hwfn, p_ptt);
3319 "Failed sending a UNLOAD_REQ command. rc = %d.\n",
3325 qed_slowpath_irq_sync(p_hwfn);
3327 /* After this point no MFW attentions are expected, e.g. prevent
3328 * race between pf stop and dcbx pf update.
3330 rc = qed_sp_pf_stop(p_hwfn);
3333 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
3338 qed_wr(p_hwfn, p_ptt,
3339 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
3341 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
3342 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
3343 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
3344 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
3345 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
3347 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
3349 /* Disable Attention Generation */
3350 qed_int_igu_disable_int(p_hwfn, p_ptt);
3352 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
3353 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
3355 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
3357 /* Need to wait 1ms to guarantee SBs are cleared */
3358 usleep_range(1000, 2000);
3360 /* Disable PF in HW blocks */
3361 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
3362 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
3364 if (IS_LEAD_HWFN(p_hwfn) &&
3365 test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits) &&
3366 !QED_IS_FCOE_PERSONALITY(p_hwfn))
3367 qed_llh_remove_mac_filter(cdev, 0,
3368 p_hwfn->hw_info.hw_mac_addr);
3370 if (!cdev->recov_in_prog) {
3371 rc = qed_mcp_unload_done(p_hwfn, p_ptt);
3374 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
3381 if (IS_PF(cdev) && !cdev->recov_in_prog) {
3382 p_hwfn = QED_LEADING_HWFN(cdev);
3383 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
3385 /* Clear the PF's internal FID_enable in the PXP.
3386 * In CMT this should only be done for first hw-function, and
3387 * only after all transactions have stopped for all active
3390 rc = qed_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
3393 "qed_pglueb_set_pfid_enable() failed. rc = %d.\n",
3402 int qed_hw_stop_fastpath(struct qed_dev *cdev)
3406 for_each_hwfn(cdev, j) {
3407 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
3408 struct qed_ptt *p_ptt;
3411 qed_vf_pf_int_cleanup(p_hwfn);
3414 p_ptt = qed_ptt_acquire(p_hwfn);
3419 NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
3421 qed_wr(p_hwfn, p_ptt,
3422 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
3424 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
3425 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
3426 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
3427 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
3428 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
3430 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
3432 /* Need to wait 1ms to guarantee SBs are cleared */
3433 usleep_range(1000, 2000);
3434 qed_ptt_release(p_hwfn, p_ptt);
3440 int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
3442 struct qed_ptt *p_ptt;
3444 if (IS_VF(p_hwfn->cdev))
3447 p_ptt = qed_ptt_acquire(p_hwfn);
3451 if (p_hwfn->p_rdma_info &&
3452 p_hwfn->p_rdma_info->active && p_hwfn->b_rdma_enabled_in_prs)
3453 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1);
3455 /* Re-open incoming traffic */
3456 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
3457 qed_ptt_release(p_hwfn, p_ptt);
3462 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
3463 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
3465 qed_ptt_pool_free(p_hwfn);
3466 kfree(p_hwfn->hw_info.p_igu_info);
3467 p_hwfn->hw_info.p_igu_info = NULL;
3470 /* Setup bar access */
3471 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
3473 /* clear indirect access */
3474 if (QED_IS_AH(p_hwfn->cdev)) {
3475 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3476 PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
3477 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3478 PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
3479 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3480 PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
3481 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3482 PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
3484 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3485 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
3486 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3487 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
3488 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3489 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
3490 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3491 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
3494 /* Clean previous pglue_b errors if such exist */
3495 qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
3497 /* enable internal target-read */
3498 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3499 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
3502 static void get_function_id(struct qed_hwfn *p_hwfn)
3505 p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
3506 PXP_PF_ME_OPAQUE_ADDR);
3508 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
3510 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
3511 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
3512 PXP_CONCRETE_FID_PFID);
3513 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
3514 PXP_CONCRETE_FID_PORT);
3516 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
3517 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
3518 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
3521 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
3523 u32 *feat_num = p_hwfn->hw_info.feat_num;
3524 struct qed_sb_cnt_info sb_cnt;
3527 memset(&sb_cnt, 0, sizeof(sb_cnt));
3528 qed_int_get_num_sbs(p_hwfn, &sb_cnt);
3530 if (IS_ENABLED(CONFIG_QED_RDMA) &&
3531 QED_IS_RDMA_PERSONALITY(p_hwfn)) {
3532 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
3533 * the status blocks equally between L2 / RoCE but with
3534 * consideration as to how many l2 queues / cnqs we have.
3536 feat_num[QED_RDMA_CNQ] =
3537 min_t(u32, sb_cnt.cnt / 2,
3538 RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
3540 non_l2_sbs = feat_num[QED_RDMA_CNQ];
3542 if (QED_IS_L2_PERSONALITY(p_hwfn)) {
3543 /* Start by allocating VF queues, then PF's */
3544 feat_num[QED_VF_L2_QUE] = min_t(u32,
3545 RESC_NUM(p_hwfn, QED_L2_QUEUE),
3547 feat_num[QED_PF_L2_QUE] = min_t(u32,
3548 sb_cnt.cnt - non_l2_sbs,
3555 if (QED_IS_FCOE_PERSONALITY(p_hwfn))
3556 feat_num[QED_FCOE_CQ] = min_t(u32, sb_cnt.cnt,
3560 if (QED_IS_ISCSI_PERSONALITY(p_hwfn))
3561 feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt,
3566 "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d #SBS=%d\n",
3567 (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
3568 (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
3569 (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
3570 (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ),
3571 (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ),
3575 const char *qed_hw_get_resc_name(enum qed_resources res_id)
3592 case QED_RDMA_CNQ_RAM:
3593 return "RDMA_CNQ_RAM";
3596 case QED_LL2_RAM_QUEUE:
3597 return "LL2_RAM_QUEUE";
3598 case QED_LL2_CTX_QUEUE:
3599 return "LL2_CTX_QUEUE";
3602 case QED_RDMA_STATS_QUEUE:
3603 return "RDMA_STATS_QUEUE";
3609 return "UNKNOWN_RESOURCE";
3614 __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
3615 struct qed_ptt *p_ptt,
3616 enum qed_resources res_id,
3617 u32 resc_max_val, u32 *p_mcp_resp)
3621 rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
3622 resc_max_val, p_mcp_resp);
3625 "MFW response failure for a max value setting of resource %d [%s]\n",
3626 res_id, qed_hw_get_resc_name(res_id));
3630 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
3632 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
3633 res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp);
3638 static u32 qed_hsi_def_val[][MAX_CHIP_IDS] = {
3639 {MAX_NUM_VFS_BB, MAX_NUM_VFS_K2},
3640 {MAX_NUM_L2_QUEUES_BB, MAX_NUM_L2_QUEUES_K2},
3641 {MAX_NUM_PORTS_BB, MAX_NUM_PORTS_K2},
3642 {MAX_SB_PER_PATH_BB, MAX_SB_PER_PATH_K2,},
3643 {MAX_NUM_PFS_BB, MAX_NUM_PFS_K2},
3644 {MAX_NUM_VPORTS_BB, MAX_NUM_VPORTS_K2},
3645 {ETH_RSS_ENGINE_NUM_BB, ETH_RSS_ENGINE_NUM_K2},
3646 {MAX_QM_TX_QUEUES_BB, MAX_QM_TX_QUEUES_K2},
3647 {PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2},
3648 {RDMA_NUM_STATISTIC_COUNTERS_BB, RDMA_NUM_STATISTIC_COUNTERS_K2},
3649 {MAX_QM_GLOBAL_RLS, MAX_QM_GLOBAL_RLS},
3650 {PBF_MAX_CMD_LINES, PBF_MAX_CMD_LINES},
3651 {BTB_MAX_BLOCKS_BB, BTB_MAX_BLOCKS_K2},
3654 u32 qed_get_hsi_def_val(struct qed_dev *cdev, enum qed_hsi_def_type type)
3656 enum chip_ids chip_id = QED_IS_BB(cdev) ? CHIP_BB : CHIP_K2;
3658 if (type >= QED_NUM_HSI_DEFS) {
3659 DP_ERR(cdev, "Unexpected HSI definition type [%d]\n", type);
3663 return qed_hsi_def_val[type][chip_id];
3666 qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3668 u32 resc_max_val, mcp_resp;
3671 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
3673 case QED_LL2_RAM_QUEUE:
3674 resc_max_val = MAX_NUM_LL2_RX_RAM_QUEUES;
3676 case QED_LL2_CTX_QUEUE:
3677 resc_max_val = MAX_NUM_LL2_RX_CTX_QUEUES;
3679 case QED_RDMA_CNQ_RAM:
3680 /* No need for a case for QED_CMDQS_CQS since
3681 * CNQ/CMDQS are the same resource.
3683 resc_max_val = NUM_OF_GLOBAL_QUEUES;
3685 case QED_RDMA_STATS_QUEUE:
3687 NUM_OF_RDMA_STATISTIC_COUNTERS(p_hwfn->cdev);
3690 resc_max_val = BDQ_NUM_RESOURCES;
3696 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
3697 resc_max_val, &mcp_resp);
3701 /* There's no point to continue to the next resource if the
3702 * command is not supported by the MFW.
3703 * We do continue if the command is supported but the resource
3704 * is unknown to the MFW. Such a resource will be later
3705 * configured with the default allocation values.
3707 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
3715 int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
3716 enum qed_resources res_id,
3717 u32 *p_resc_num, u32 *p_resc_start)
3719 u8 num_funcs = p_hwfn->num_funcs_on_engine;
3720 struct qed_dev *cdev = p_hwfn->cdev;
3724 *p_resc_num = NUM_OF_L2_QUEUES(cdev) / num_funcs;
3727 *p_resc_num = NUM_OF_VPORTS(cdev) / num_funcs;
3730 *p_resc_num = NUM_OF_RSS_ENGINES(cdev) / num_funcs;
3733 *p_resc_num = NUM_OF_QM_TX_QUEUES(cdev) / num_funcs;
3734 *p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */
3737 *p_resc_num = NUM_OF_QM_GLOBAL_RLS(cdev) / num_funcs;
3741 /* Each VFC resource can accommodate both a MAC and a VLAN */
3742 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
3745 *p_resc_num = NUM_OF_PXP_ILT_RECORDS(cdev) / num_funcs;
3747 case QED_LL2_RAM_QUEUE:
3748 *p_resc_num = MAX_NUM_LL2_RX_RAM_QUEUES / num_funcs;
3750 case QED_LL2_CTX_QUEUE:
3751 *p_resc_num = MAX_NUM_LL2_RX_CTX_QUEUES / num_funcs;
3753 case QED_RDMA_CNQ_RAM:
3755 /* CNQ/CMDQS are the same resource */
3756 *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs;
3758 case QED_RDMA_STATS_QUEUE:
3759 *p_resc_num = NUM_OF_RDMA_STATISTIC_COUNTERS(cdev) / num_funcs;
3762 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
3763 p_hwfn->hw_info.personality != QED_PCI_FCOE)
3769 /* Since we want its value to reflect whether MFW supports
3770 * the new scheme, have a default of 0.
3782 else if (p_hwfn->cdev->num_ports_in_engine == 4)
3783 *p_resc_start = p_hwfn->port_id;
3784 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
3785 *p_resc_start = p_hwfn->port_id;
3786 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
3787 *p_resc_start = p_hwfn->port_id + 2;
3790 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
3797 static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
3798 enum qed_resources res_id)
3800 u32 dflt_resc_num = 0, dflt_resc_start = 0;
3801 u32 mcp_resp, *p_resc_num, *p_resc_start;
3804 p_resc_num = &RESC_NUM(p_hwfn, res_id);
3805 p_resc_start = &RESC_START(p_hwfn, res_id);
3807 rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
3811 "Failed to get default amount for resource %d [%s]\n",
3812 res_id, qed_hw_get_resc_name(res_id));
3816 rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
3817 &mcp_resp, p_resc_num, p_resc_start);
3820 "MFW response failure for an allocation request for resource %d [%s]\n",
3821 res_id, qed_hw_get_resc_name(res_id));
3825 /* Default driver values are applied in the following cases:
3826 * - The resource allocation MB command is not supported by the MFW
3827 * - There is an internal error in the MFW while processing the request
3828 * - The resource ID is unknown to the MFW
3830 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3832 "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
3834 qed_hw_get_resc_name(res_id),
3835 mcp_resp, dflt_resc_num, dflt_resc_start);
3836 *p_resc_num = dflt_resc_num;
3837 *p_resc_start = dflt_resc_start;
3842 /* PQs have to divide by 8 [that's the HW granularity].
3843 * Reduce number so it would fit.
3845 if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
3847 "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
3849 (*p_resc_num) & ~0x7,
3850 *p_resc_start, (*p_resc_start) & ~0x7);
3851 *p_resc_num &= ~0x7;
3852 *p_resc_start &= ~0x7;
3858 static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn)
3863 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
3864 rc = __qed_hw_set_resc_info(p_hwfn, res_id);
3872 static int qed_hw_get_ppfid_bitmap(struct qed_hwfn *p_hwfn,
3873 struct qed_ptt *p_ptt)
3875 struct qed_dev *cdev = p_hwfn->cdev;
3876 u8 native_ppfid_idx;
3879 /* Calculation of BB/AH is different for native_ppfid_idx */
3880 if (QED_IS_BB(cdev))
3881 native_ppfid_idx = p_hwfn->rel_pf_id;
3883 native_ppfid_idx = p_hwfn->rel_pf_id /
3884 cdev->num_ports_in_engine;
3886 rc = qed_mcp_get_ppfid_bitmap(p_hwfn, p_ptt);
3887 if (rc != 0 && rc != -EOPNOTSUPP)
3889 else if (rc == -EOPNOTSUPP)
3890 cdev->ppfid_bitmap = 0x1 << native_ppfid_idx;
3892 if (!(cdev->ppfid_bitmap & (0x1 << native_ppfid_idx))) {
3894 "Fix the PPFID bitmap to include the native PPFID [native_ppfid_idx %hhd, orig_bitmap 0x%hhx]\n",
3895 native_ppfid_idx, cdev->ppfid_bitmap);
3896 cdev->ppfid_bitmap = 0x1 << native_ppfid_idx;
3902 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3904 struct qed_resc_unlock_params resc_unlock_params;
3905 struct qed_resc_lock_params resc_lock_params;
3906 bool b_ah = QED_IS_AH(p_hwfn->cdev);
3910 /* Setting the max values of the soft resources and the following
3911 * resources allocation queries should be atomic. Since several PFs can
3912 * run in parallel - a resource lock is needed.
3913 * If either the resource lock or resource set value commands are not
3914 * supported - skip the the max values setting, release the lock if
3915 * needed, and proceed to the queries. Other failures, including a
3916 * failure to acquire the lock, will cause this function to fail.
3918 qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
3919 QED_RESC_LOCK_RESC_ALLOC, false);
3921 rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
3922 if (rc && rc != -EINVAL) {
3924 } else if (rc == -EINVAL) {
3926 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
3927 } else if (!rc && !resc_lock_params.b_granted) {
3929 "Failed to acquire the resource lock for the resource allocation commands\n");
3932 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt);
3933 if (rc && rc != -EINVAL) {
3935 "Failed to set the max values of the soft resources\n");
3936 goto unlock_and_exit;
3937 } else if (rc == -EINVAL) {
3939 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
3940 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt,
3941 &resc_unlock_params);
3944 "Failed to release the resource lock for the resource allocation commands\n");
3948 rc = qed_hw_set_resc_info(p_hwfn);
3950 goto unlock_and_exit;
3952 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
3953 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
3956 "Failed to release the resource lock for the resource allocation commands\n");
3960 if (IS_LEAD_HWFN(p_hwfn)) {
3961 rc = qed_hw_get_ppfid_bitmap(p_hwfn, p_ptt);
3966 /* Sanity for ILT */
3967 if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
3968 (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
3969 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
3970 RESC_START(p_hwfn, QED_ILT),
3971 RESC_END(p_hwfn, QED_ILT) - 1);
3975 /* This will also learn the number of SBs from MFW */
3976 if (qed_int_igu_reset_cam(p_hwfn, p_ptt))
3979 qed_hw_set_feat(p_hwfn);
3981 for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
3982 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
3983 qed_hw_get_resc_name(res_id),
3984 RESC_NUM(p_hwfn, res_id),
3985 RESC_START(p_hwfn, res_id));
3990 if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
3991 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
3995 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3997 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
3998 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
3999 struct qed_mcp_link_capabilities *p_caps;
4000 struct qed_mcp_link_params *link;
4002 /* Read global nvm_cfg address */
4003 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
4005 /* Verify MCP has initialized it */
4006 if (!nvm_cfg_addr) {
4007 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
4011 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
4012 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
4014 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4015 offsetof(struct nvm_cfg1, glob) +
4016 offsetof(struct nvm_cfg1_glob, core_cfg);
4018 core_cfg = qed_rd(p_hwfn, p_ptt, addr);
4020 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
4021 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
4022 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
4023 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
4025 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
4026 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
4028 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
4029 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
4031 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
4032 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
4034 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
4035 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
4037 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
4038 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
4040 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
4041 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
4043 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
4044 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
4046 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
4047 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
4049 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
4050 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
4052 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
4053 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
4056 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
4060 /* Read default link configuration */
4061 link = &p_hwfn->mcp_info->link_input;
4062 p_caps = &p_hwfn->mcp_info->link_capabilities;
4063 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4064 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
4065 link_temp = qed_rd(p_hwfn, p_ptt,
4067 offsetof(struct nvm_cfg1_port, speed_cap_mask));
4068 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
4069 link->speed.advertised_speeds = link_temp;
4071 link_temp = link->speed.advertised_speeds;
4072 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
4074 link_temp = qed_rd(p_hwfn, p_ptt,
4076 offsetof(struct nvm_cfg1_port, link_settings));
4077 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
4078 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
4079 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
4080 link->speed.autoneg = true;
4082 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
4083 link->speed.forced_speed = 1000;
4085 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
4086 link->speed.forced_speed = 10000;
4088 case NVM_CFG1_PORT_DRV_LINK_SPEED_20G:
4089 link->speed.forced_speed = 20000;
4091 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
4092 link->speed.forced_speed = 25000;
4094 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
4095 link->speed.forced_speed = 40000;
4097 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
4098 link->speed.forced_speed = 50000;
4100 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
4101 link->speed.forced_speed = 100000;
4104 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
4107 p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
4108 link->speed.autoneg;
4110 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
4111 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
4112 link->pause.autoneg = !!(link_temp &
4113 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
4114 link->pause.forced_rx = !!(link_temp &
4115 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
4116 link->pause.forced_tx = !!(link_temp &
4117 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
4118 link->loopback_mode = 0;
4120 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
4121 link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr +
4122 offsetof(struct nvm_cfg1_port, ext_phy));
4123 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
4124 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
4125 p_caps->default_eee = QED_MCP_EEE_ENABLED;
4126 link->eee.enable = true;
4127 switch (link_temp) {
4128 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
4129 p_caps->default_eee = QED_MCP_EEE_DISABLED;
4130 link->eee.enable = false;
4132 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
4133 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
4135 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
4136 p_caps->eee_lpi_timer =
4137 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
4139 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
4140 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
4144 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
4145 link->eee.tx_lpi_enable = link->eee.enable;
4146 link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV;
4148 p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED;
4153 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x EEE: %02x [%08x usec]\n",
4154 link->speed.forced_speed,
4155 link->speed.advertised_speeds,
4156 link->speed.autoneg,
4157 link->pause.autoneg,
4158 p_caps->default_eee, p_caps->eee_lpi_timer);
4160 if (IS_LEAD_HWFN(p_hwfn)) {
4161 struct qed_dev *cdev = p_hwfn->cdev;
4163 /* Read Multi-function information from shmem */
4164 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4165 offsetof(struct nvm_cfg1, glob) +
4166 offsetof(struct nvm_cfg1_glob, generic_cont0);
4168 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
4170 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
4171 NVM_CFG1_GLOB_MF_MODE_OFFSET;
4174 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
4175 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS);
4177 case NVM_CFG1_GLOB_MF_MODE_UFP:
4178 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
4179 BIT(QED_MF_LLH_PROTO_CLSS) |
4180 BIT(QED_MF_UFP_SPECIFIC) |
4181 BIT(QED_MF_8021Q_TAGGING) |
4182 BIT(QED_MF_DONT_ADD_VLAN0_TAG);
4184 case NVM_CFG1_GLOB_MF_MODE_BD:
4185 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
4186 BIT(QED_MF_LLH_PROTO_CLSS) |
4187 BIT(QED_MF_8021AD_TAGGING) |
4188 BIT(QED_MF_DONT_ADD_VLAN0_TAG);
4190 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
4191 cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
4192 BIT(QED_MF_LLH_PROTO_CLSS) |
4193 BIT(QED_MF_LL2_NON_UNICAST) |
4194 BIT(QED_MF_INTER_PF_SWITCH);
4196 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
4197 cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
4198 BIT(QED_MF_LLH_PROTO_CLSS) |
4199 BIT(QED_MF_LL2_NON_UNICAST);
4200 if (QED_IS_BB(p_hwfn->cdev))
4201 cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF);
4205 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
4209 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
4210 p_hwfn->cdev->mf_bits);
4212 /* Read device capabilities information from shmem */
4213 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4214 offsetof(struct nvm_cfg1, glob) +
4215 offsetof(struct nvm_cfg1_glob, device_capabilities);
4217 device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
4218 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
4219 __set_bit(QED_DEV_CAP_ETH,
4220 &p_hwfn->hw_info.device_capabilities);
4221 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
4222 __set_bit(QED_DEV_CAP_FCOE,
4223 &p_hwfn->hw_info.device_capabilities);
4224 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
4225 __set_bit(QED_DEV_CAP_ISCSI,
4226 &p_hwfn->hw_info.device_capabilities);
4227 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
4228 __set_bit(QED_DEV_CAP_ROCE,
4229 &p_hwfn->hw_info.device_capabilities);
4231 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
4234 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4236 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
4237 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
4238 struct qed_dev *cdev = p_hwfn->cdev;
4240 num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
4242 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
4243 * in the other bits are selected.
4244 * Bits 1-15 are for functions 1-15, respectively, and their value is
4245 * '0' only for enabled functions (function 0 always exists and
4247 * In case of CMT, only the "even" functions are enabled, and thus the
4248 * number of functions for both hwfns is learnt from the same bits.
4250 reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
4252 if (reg_function_hide & 0x1) {
4253 if (QED_IS_BB(cdev)) {
4254 if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
4266 /* Get the number of the enabled functions on the engine */
4267 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
4274 /* Get the PF index within the enabled functions */
4275 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
4276 tmp = reg_function_hide & eng_mask & low_pfs_mask;
4284 p_hwfn->num_funcs_on_engine = num_funcs;
4285 p_hwfn->enabled_func_idx = enabled_func_idx;
4289 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
4292 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
4295 static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4297 u32 addr, global_offsize, global_addr, port_mode;
4298 struct qed_dev *cdev = p_hwfn->cdev;
4300 /* In CMT there is always only one port */
4301 if (cdev->num_hwfns > 1) {
4302 cdev->num_ports_in_engine = 1;
4303 cdev->num_ports = 1;
4307 /* Determine the number of ports per engine */
4308 port_mode = qed_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE);
4309 switch (port_mode) {
4311 cdev->num_ports_in_engine = 1;
4314 cdev->num_ports_in_engine = 2;
4317 cdev->num_ports_in_engine = 4;
4320 DP_NOTICE(p_hwfn, "Unknown port mode 0x%08x\n", port_mode);
4321 cdev->num_ports_in_engine = 1; /* Default to something */
4325 /* Get the total number of ports of the device */
4326 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
4328 global_offsize = qed_rd(p_hwfn, p_ptt, addr);
4329 global_addr = SECTION_ADDR(global_offsize, 0);
4330 addr = global_addr + offsetof(struct public_global, max_ports);
4331 cdev->num_ports = (u8)qed_rd(p_hwfn, p_ptt, addr);
4334 static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4336 struct qed_mcp_link_capabilities *p_caps;
4339 p_caps = &p_hwfn->mcp_info->link_capabilities;
4340 if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED)
4343 p_caps->eee_speed_caps = 0;
4344 eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
4345 offsetof(struct public_port, eee_status));
4346 eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
4347 EEE_SUPPORTED_SPEED_OFFSET;
4349 if (eee_status & EEE_1G_SUPPORTED)
4350 p_caps->eee_speed_caps |= QED_EEE_1G_ADV;
4351 if (eee_status & EEE_10G_ADV)
4352 p_caps->eee_speed_caps |= QED_EEE_10G_ADV;
4356 qed_get_hw_info(struct qed_hwfn *p_hwfn,
4357 struct qed_ptt *p_ptt,
4358 enum qed_pci_personality personality)
4362 /* Since all information is common, only first hwfns should do this */
4363 if (IS_LEAD_HWFN(p_hwfn)) {
4364 rc = qed_iov_hw_info(p_hwfn);
4369 if (IS_LEAD_HWFN(p_hwfn))
4370 qed_hw_info_port_num(p_hwfn, p_ptt);
4372 qed_mcp_get_capabilities(p_hwfn, p_ptt);
4374 qed_hw_get_nvm_info(p_hwfn, p_ptt);
4376 rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
4380 if (qed_mcp_is_init(p_hwfn))
4381 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
4382 p_hwfn->mcp_info->func_info.mac);
4384 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
4386 if (qed_mcp_is_init(p_hwfn)) {
4387 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
4388 p_hwfn->hw_info.ovlan =
4389 p_hwfn->mcp_info->func_info.ovlan;
4391 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
4393 qed_get_eee_caps(p_hwfn, p_ptt);
4395 qed_mcp_read_ufp_config(p_hwfn, p_ptt);
4398 if (qed_mcp_is_init(p_hwfn)) {
4399 enum qed_pci_personality protocol;
4401 protocol = p_hwfn->mcp_info->func_info.protocol;
4402 p_hwfn->hw_info.personality = protocol;
4405 if (QED_IS_ROCE_PERSONALITY(p_hwfn))
4406 p_hwfn->hw_info.multi_tc_roce_en = true;
4408 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
4409 p_hwfn->hw_info.num_active_tc = 1;
4411 qed_get_num_funcs(p_hwfn, p_ptt);
4413 if (qed_mcp_is_init(p_hwfn))
4414 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
4416 return qed_hw_get_resc(p_hwfn, p_ptt);
4419 static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4421 struct qed_dev *cdev = p_hwfn->cdev;
4425 /* Read Vendor Id / Device Id */
4426 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
4427 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
4429 /* Determine type */
4430 device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
4431 switch (device_id_mask) {
4432 case QED_DEV_ID_MASK_BB:
4433 cdev->type = QED_DEV_TYPE_BB;
4435 case QED_DEV_ID_MASK_AH:
4436 cdev->type = QED_DEV_TYPE_AH;
4439 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
4443 cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
4444 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
4446 MASK_FIELD(CHIP_REV, cdev->chip_rev);
4448 /* Learn number of HW-functions */
4449 tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
4451 if (tmp & (1 << p_hwfn->rel_pf_id)) {
4452 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
4453 cdev->num_hwfns = 2;
4455 cdev->num_hwfns = 1;
4458 cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
4459 MISCS_REG_CHIP_TEST_REG) >> 4;
4460 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
4461 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
4462 MASK_FIELD(CHIP_METAL, cdev->chip_metal);
4464 DP_INFO(cdev->hwfns,
4465 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
4466 QED_IS_BB(cdev) ? "BB" : "AH",
4467 'A' + cdev->chip_rev,
4468 (int)cdev->chip_metal,
4469 cdev->chip_num, cdev->chip_rev,
4470 cdev->chip_bond_id, cdev->chip_metal);
4475 static void qed_nvm_info_free(struct qed_hwfn *p_hwfn)
4477 kfree(p_hwfn->nvm_info.image_att);
4478 p_hwfn->nvm_info.image_att = NULL;
4481 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
4482 void __iomem *p_regview,
4483 void __iomem *p_doorbells,
4485 enum qed_pci_personality personality)
4487 struct qed_dev *cdev = p_hwfn->cdev;
4490 /* Split PCI bars evenly between hwfns */
4491 p_hwfn->regview = p_regview;
4492 p_hwfn->doorbells = p_doorbells;
4493 p_hwfn->db_phys_addr = db_phys_addr;
4495 if (IS_VF(p_hwfn->cdev))
4496 return qed_vf_hw_prepare(p_hwfn);
4498 /* Validate that chip access is feasible */
4499 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
4501 "Reading the ME register returns all Fs; Preventing further chip access\n");
4505 get_function_id(p_hwfn);
4507 /* Allocate PTT pool */
4508 rc = qed_ptt_pool_alloc(p_hwfn);
4512 /* Allocate the main PTT */
4513 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
4515 /* First hwfn learns basic information, e.g., number of hwfns */
4516 if (!p_hwfn->my_id) {
4517 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
4522 qed_hw_hwfn_prepare(p_hwfn);
4524 /* Initialize MCP structure */
4525 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
4527 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
4531 /* Read the device configuration information from the HW and SHMEM */
4532 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
4534 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
4538 /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
4539 * is called as it sets the ports number in an engine.
4541 if (IS_LEAD_HWFN(p_hwfn) && !cdev->recov_in_prog) {
4542 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
4544 DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
4547 /* NVRAM info initialization and population */
4548 if (IS_LEAD_HWFN(p_hwfn)) {
4549 rc = qed_mcp_nvm_info_populate(p_hwfn);
4552 "Failed to populate nvm info shadow\n");
4557 /* Allocate the init RT array and initialize the init-ops engine */
4558 rc = qed_init_alloc(p_hwfn);
4564 if (IS_LEAD_HWFN(p_hwfn))
4565 qed_nvm_info_free(p_hwfn);
4567 if (IS_LEAD_HWFN(p_hwfn))
4568 qed_iov_free_hw_info(p_hwfn->cdev);
4569 qed_mcp_free(p_hwfn);
4571 qed_hw_hwfn_free(p_hwfn);
4576 int qed_hw_prepare(struct qed_dev *cdev,
4579 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
4582 /* Store the precompiled init data ptrs */
4584 qed_init_iro_array(cdev);
4586 /* Initialize the first hwfn - will learn number of hwfns */
4587 rc = qed_hw_prepare_single(p_hwfn,
4595 personality = p_hwfn->hw_info.personality;
4597 /* Initialize the rest of the hwfns */
4598 if (cdev->num_hwfns > 1) {
4599 void __iomem *p_regview, *p_doorbell;
4603 /* adjust bar offset for second engine */
4604 offset = qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
4606 p_regview = cdev->regview + offset;
4608 offset = qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
4611 p_doorbell = cdev->doorbells + offset;
4613 db_phys_addr = cdev->db_phys_addr + offset;
4615 /* prepare second hw function */
4616 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
4617 p_doorbell, db_phys_addr,
4620 /* in case of error, need to free the previously
4621 * initiliazed hwfn 0.
4625 qed_init_free(p_hwfn);
4626 qed_nvm_info_free(p_hwfn);
4627 qed_mcp_free(p_hwfn);
4628 qed_hw_hwfn_free(p_hwfn);
4636 void qed_hw_remove(struct qed_dev *cdev)
4638 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
4642 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
4643 QED_OV_DRIVER_STATE_NOT_LOADED);
4645 for_each_hwfn(cdev, i) {
4646 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4649 qed_vf_pf_release(p_hwfn);
4653 qed_init_free(p_hwfn);
4654 qed_hw_hwfn_free(p_hwfn);
4655 qed_mcp_free(p_hwfn);
4658 qed_iov_free_hw_info(cdev);
4660 qed_nvm_info_free(p_hwfn);
4663 static void qed_chain_free_next_ptr(struct qed_dev *cdev,
4664 struct qed_chain *p_chain)
4666 void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
4667 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
4668 struct qed_chain_next *p_next;
4674 size = p_chain->elem_size * p_chain->usable_per_page;
4676 for (i = 0; i < p_chain->page_cnt; i++) {
4680 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
4681 p_virt_next = p_next->next_virt;
4682 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
4684 dma_free_coherent(&cdev->pdev->dev,
4685 QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
4687 p_virt = p_virt_next;
4688 p_phys = p_phys_next;
4692 static void qed_chain_free_single(struct qed_dev *cdev,
4693 struct qed_chain *p_chain)
4695 if (!p_chain->p_virt_addr)
4698 dma_free_coherent(&cdev->pdev->dev,
4699 QED_CHAIN_PAGE_SIZE,
4700 p_chain->p_virt_addr, p_chain->p_phys_addr);
4703 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
4705 struct addr_tbl_entry *pp_addr_tbl = p_chain->pbl.pp_addr_tbl;
4706 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
4711 for (i = 0; i < page_cnt; i++) {
4712 if (!pp_addr_tbl[i].virt_addr || !pp_addr_tbl[i].dma_map)
4715 dma_free_coherent(&cdev->pdev->dev,
4716 QED_CHAIN_PAGE_SIZE,
4717 pp_addr_tbl[i].virt_addr,
4718 pp_addr_tbl[i].dma_map);
4721 pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
4723 if (!p_chain->b_external_pbl)
4724 dma_free_coherent(&cdev->pdev->dev,
4726 p_chain->pbl_sp.p_virt_table,
4727 p_chain->pbl_sp.p_phys_table);
4729 vfree(p_chain->pbl.pp_addr_tbl);
4730 p_chain->pbl.pp_addr_tbl = NULL;
4733 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
4735 switch (p_chain->mode) {
4736 case QED_CHAIN_MODE_NEXT_PTR:
4737 qed_chain_free_next_ptr(cdev, p_chain);
4739 case QED_CHAIN_MODE_SINGLE:
4740 qed_chain_free_single(cdev, p_chain);
4742 case QED_CHAIN_MODE_PBL:
4743 qed_chain_free_pbl(cdev, p_chain);
4749 qed_chain_alloc_sanity_check(struct qed_dev *cdev,
4750 enum qed_chain_cnt_type cnt_type,
4751 size_t elem_size, u32 page_cnt)
4753 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
4755 /* The actual chain size can be larger than the maximal possible value
4756 * after rounding up the requested elements number to pages, and after
4757 * taking into acount the unusuable elements (next-ptr elements).
4758 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
4759 * size/capacity fields are of a u32 type.
4761 if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
4762 chain_size > ((u32)U16_MAX + 1)) ||
4763 (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
4765 "The actual chain size (0x%llx) is larger than the maximal possible value\n",
4774 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
4776 void *p_virt = NULL, *p_virt_prev = NULL;
4777 dma_addr_t p_phys = 0;
4780 for (i = 0; i < p_chain->page_cnt; i++) {
4781 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
4782 QED_CHAIN_PAGE_SIZE,
4783 &p_phys, GFP_KERNEL);
4788 qed_chain_init_mem(p_chain, p_virt, p_phys);
4789 qed_chain_reset(p_chain);
4791 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4795 p_virt_prev = p_virt;
4797 /* Last page's next element should point to the beginning of the
4800 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4801 p_chain->p_virt_addr,
4802 p_chain->p_phys_addr);
4808 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
4810 dma_addr_t p_phys = 0;
4811 void *p_virt = NULL;
4813 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
4814 QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
4818 qed_chain_init_mem(p_chain, p_virt, p_phys);
4819 qed_chain_reset(p_chain);
4825 qed_chain_alloc_pbl(struct qed_dev *cdev,
4826 struct qed_chain *p_chain,
4827 struct qed_chain_ext_pbl *ext_pbl)
4829 u32 page_cnt = p_chain->page_cnt, size, i;
4830 dma_addr_t p_phys = 0, p_pbl_phys = 0;
4831 struct addr_tbl_entry *pp_addr_tbl;
4832 u8 *p_pbl_virt = NULL;
4833 void *p_virt = NULL;
4835 size = page_cnt * sizeof(*pp_addr_tbl);
4836 pp_addr_tbl = vzalloc(size);
4840 /* The allocation of the PBL table is done with its full size, since it
4841 * is expected to be successive.
4842 * qed_chain_init_pbl_mem() is called even in a case of an allocation
4843 * failure, since tbl was previously allocated, and it
4844 * should be saved to allow its freeing during the error flow.
4846 size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
4849 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
4850 size, &p_pbl_phys, GFP_KERNEL);
4852 p_pbl_virt = ext_pbl->p_pbl_virt;
4853 p_pbl_phys = ext_pbl->p_pbl_phys;
4854 p_chain->b_external_pbl = true;
4857 qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys, pp_addr_tbl);
4861 for (i = 0; i < page_cnt; i++) {
4862 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
4863 QED_CHAIN_PAGE_SIZE,
4864 &p_phys, GFP_KERNEL);
4869 qed_chain_init_mem(p_chain, p_virt, p_phys);
4870 qed_chain_reset(p_chain);
4873 /* Fill the PBL table with the physical address of the page */
4874 *(dma_addr_t *)p_pbl_virt = p_phys;
4875 /* Keep the virtual address of the page */
4876 p_chain->pbl.pp_addr_tbl[i].virt_addr = p_virt;
4877 p_chain->pbl.pp_addr_tbl[i].dma_map = p_phys;
4879 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
4885 int qed_chain_alloc(struct qed_dev *cdev,
4886 enum qed_chain_use_mode intended_use,
4887 enum qed_chain_mode mode,
4888 enum qed_chain_cnt_type cnt_type,
4891 struct qed_chain *p_chain,
4892 struct qed_chain_ext_pbl *ext_pbl)
4897 if (mode == QED_CHAIN_MODE_SINGLE)
4900 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
4902 rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
4905 "Cannot allocate a chain with the given arguments:\n");
4907 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
4908 intended_use, mode, cnt_type, num_elems, elem_size);
4912 qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
4916 case QED_CHAIN_MODE_NEXT_PTR:
4917 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
4919 case QED_CHAIN_MODE_SINGLE:
4920 rc = qed_chain_alloc_single(cdev, p_chain);
4922 case QED_CHAIN_MODE_PBL:
4923 rc = qed_chain_alloc_pbl(cdev, p_chain, ext_pbl);
4932 qed_chain_free(cdev, p_chain);
4936 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
4938 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
4941 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
4942 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
4944 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4950 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
4955 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
4957 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
4960 min = (u8)RESC_START(p_hwfn, QED_VPORT);
4961 max = min + RESC_NUM(p_hwfn, QED_VPORT);
4963 "vport id [%d] is not valid, available indices [%d - %d]\n",
4969 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
4974 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
4976 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
4979 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
4980 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
4982 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4988 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
4993 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
4994 u32 hw_addr, void *p_eth_qzone,
4995 size_t eth_qzone_size, u8 timeset)
4997 struct coalescing_timeset *p_coal_timeset;
4999 if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
5000 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
5004 p_coal_timeset = p_eth_qzone;
5005 memset(p_eth_qzone, 0, eth_qzone_size);
5006 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
5007 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
5008 qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
5013 int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle)
5015 struct qed_queue_cid *p_cid = p_handle;
5016 struct qed_hwfn *p_hwfn;
5017 struct qed_ptt *p_ptt;
5020 p_hwfn = p_cid->p_owner;
5022 if (IS_VF(p_hwfn->cdev))
5023 return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid);
5025 p_ptt = qed_ptt_acquire(p_hwfn);
5030 rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
5033 p_hwfn->cdev->rx_coalesce_usecs = rx_coal;
5037 rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
5040 p_hwfn->cdev->tx_coalesce_usecs = tx_coal;
5043 qed_ptt_release(p_hwfn, p_ptt);
5047 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn,
5048 struct qed_ptt *p_ptt,
5049 u16 coalesce, struct qed_queue_cid *p_cid)
5051 struct ustorm_eth_queue_zone eth_qzone;
5052 u8 timeset, timer_res;
5056 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5057 if (coalesce <= 0x7F) {
5059 } else if (coalesce <= 0xFF) {
5061 } else if (coalesce <= 0x1FF) {
5064 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5067 timeset = (u8)(coalesce >> timer_res);
5069 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5070 p_cid->sb_igu_id, false);
5074 address = BAR0_MAP_REG_USDM_RAM +
5075 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5077 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
5078 sizeof(struct ustorm_eth_queue_zone), timeset);
5086 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn,
5087 struct qed_ptt *p_ptt,
5088 u16 coalesce, struct qed_queue_cid *p_cid)
5090 struct xstorm_eth_queue_zone eth_qzone;
5091 u8 timeset, timer_res;
5095 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5096 if (coalesce <= 0x7F) {
5098 } else if (coalesce <= 0xFF) {
5100 } else if (coalesce <= 0x1FF) {
5103 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5106 timeset = (u8)(coalesce >> timer_res);
5108 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5109 p_cid->sb_igu_id, true);
5113 address = BAR0_MAP_REG_XSDM_RAM +
5114 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5116 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
5117 sizeof(struct xstorm_eth_queue_zone), timeset);
5122 /* Calculate final WFQ values for all vports and configure them.
5123 * After this configuration each vport will have
5124 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
5126 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
5127 struct qed_ptt *p_ptt,
5130 struct init_qm_vport_params *vport_params;
5133 vport_params = p_hwfn->qm_info.qm_vport_params;
5135 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5136 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5138 vport_params[i].wfq = (wfq_speed * QED_WFQ_UNIT) /
5140 qed_init_vport_wfq(p_hwfn, p_ptt,
5141 vport_params[i].first_tx_pq_id,
5142 vport_params[i].wfq);
5146 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
5152 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
5153 p_hwfn->qm_info.qm_vport_params[i].wfq = 1;
5156 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
5157 struct qed_ptt *p_ptt,
5160 struct init_qm_vport_params *vport_params;
5163 vport_params = p_hwfn->qm_info.qm_vport_params;
5165 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5166 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
5167 qed_init_vport_wfq(p_hwfn, p_ptt,
5168 vport_params[i].first_tx_pq_id,
5169 vport_params[i].wfq);
5173 /* This function performs several validations for WFQ
5174 * configuration and required min rate for a given vport
5175 * 1. req_rate must be greater than one percent of min_pf_rate.
5176 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
5177 * rates to get less than one percent of min_pf_rate.
5178 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
5180 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
5181 u16 vport_id, u32 req_rate, u32 min_pf_rate)
5183 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
5184 int non_requested_count = 0, req_count = 0, i, num_vports;
5186 num_vports = p_hwfn->qm_info.num_vports;
5188 /* Accounting for the vports which are configured for WFQ explicitly */
5189 for (i = 0; i < num_vports; i++) {
5192 if ((i != vport_id) &&
5193 p_hwfn->qm_info.wfq_data[i].configured) {
5195 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5196 total_req_min_rate += tmp_speed;
5200 /* Include current vport data as well */
5202 total_req_min_rate += req_rate;
5203 non_requested_count = num_vports - req_count;
5205 if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
5206 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5207 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5208 vport_id, req_rate, min_pf_rate);
5212 if (num_vports > QED_WFQ_UNIT) {
5213 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5214 "Number of vports is greater than %d\n",
5219 if (total_req_min_rate > min_pf_rate) {
5220 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5221 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5222 total_req_min_rate, min_pf_rate);
5226 total_left_rate = min_pf_rate - total_req_min_rate;
5228 left_rate_per_vp = total_left_rate / non_requested_count;
5229 if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) {
5230 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5231 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5232 left_rate_per_vp, min_pf_rate);
5236 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
5237 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
5239 for (i = 0; i < num_vports; i++) {
5240 if (p_hwfn->qm_info.wfq_data[i].configured)
5243 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
5249 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
5250 struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
5252 struct qed_mcp_link_state *p_link;
5255 p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
5257 if (!p_link->min_pf_rate) {
5258 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
5259 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
5263 rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
5266 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
5267 p_link->min_pf_rate);
5270 "Validation failed while configuring min rate\n");
5275 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
5276 struct qed_ptt *p_ptt,
5279 bool use_wfq = false;
5283 /* Validate all pre configured vports for wfq */
5284 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5287 if (!p_hwfn->qm_info.wfq_data[i].configured)
5290 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
5293 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
5296 "WFQ validation failed while configuring min rate\n");
5302 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5304 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5309 /* Main API for qed clients to configure vport min rate.
5310 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
5311 * rate - Speed in Mbps needs to be assigned to a given vport.
5313 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
5315 int i, rc = -EINVAL;
5317 /* Currently not supported; Might change in future */
5318 if (cdev->num_hwfns > 1) {
5320 "WFQ configuration is not supported for this device\n");
5324 for_each_hwfn(cdev, i) {
5325 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5326 struct qed_ptt *p_ptt;
5328 p_ptt = qed_ptt_acquire(p_hwfn);
5332 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
5335 qed_ptt_release(p_hwfn, p_ptt);
5339 qed_ptt_release(p_hwfn, p_ptt);
5345 /* API to configure WFQ from mcp link change */
5346 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
5347 struct qed_ptt *p_ptt, u32 min_pf_rate)
5351 if (cdev->num_hwfns > 1) {
5354 "WFQ configuration is not supported for this device\n");
5358 for_each_hwfn(cdev, i) {
5359 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5361 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
5366 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
5367 struct qed_ptt *p_ptt,
5368 struct qed_mcp_link_state *p_link,
5373 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
5375 if (!p_link->line_speed && (max_bw != 100))
5378 p_link->speed = (p_link->line_speed * max_bw) / 100;
5379 p_hwfn->qm_info.pf_rl = p_link->speed;
5381 /* Since the limiter also affects Tx-switched traffic, we don't want it
5382 * to limit such traffic in case there's no actual limit.
5383 * In that case, set limit to imaginary high boundary.
5386 p_hwfn->qm_info.pf_rl = 100000;
5388 rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
5389 p_hwfn->qm_info.pf_rl);
5391 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5392 "Configured MAX bandwidth to be %08x Mb/sec\n",
5398 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
5399 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
5401 int i, rc = -EINVAL;
5403 if (max_bw < 1 || max_bw > 100) {
5404 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
5408 for_each_hwfn(cdev, i) {
5409 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5410 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
5411 struct qed_mcp_link_state *p_link;
5412 struct qed_ptt *p_ptt;
5414 p_link = &p_lead->mcp_info->link_output;
5416 p_ptt = qed_ptt_acquire(p_hwfn);
5420 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5423 qed_ptt_release(p_hwfn, p_ptt);
5432 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
5433 struct qed_ptt *p_ptt,
5434 struct qed_mcp_link_state *p_link,
5439 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5440 p_hwfn->qm_info.pf_wfq = min_bw;
5442 if (!p_link->line_speed)
5445 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5447 rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5449 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5450 "Configured MIN bandwidth to be %d Mb/sec\n",
5451 p_link->min_pf_rate);
5456 /* Main API to configure PF min bandwidth where bw range is [1-100] */
5457 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
5459 int i, rc = -EINVAL;
5461 if (min_bw < 1 || min_bw > 100) {
5462 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
5466 for_each_hwfn(cdev, i) {
5467 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5468 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
5469 struct qed_mcp_link_state *p_link;
5470 struct qed_ptt *p_ptt;
5472 p_link = &p_lead->mcp_info->link_output;
5474 p_ptt = qed_ptt_acquire(p_hwfn);
5478 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5481 qed_ptt_release(p_hwfn, p_ptt);
5485 if (p_link->min_pf_rate) {
5486 u32 min_rate = p_link->min_pf_rate;
5488 rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
5493 qed_ptt_release(p_hwfn, p_ptt);
5499 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
5501 struct qed_mcp_link_state *p_link;
5503 p_link = &p_hwfn->mcp_info->link_output;
5505 if (p_link->min_pf_rate)
5506 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
5507 p_link->min_pf_rate);
5509 memset(p_hwfn->qm_info.wfq_data, 0,
5510 sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
5513 int qed_device_num_ports(struct qed_dev *cdev)
5515 return cdev->num_ports;
5518 void qed_set_fw_mac_addr(__le16 *fw_msb,
5519 __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
5521 ((u8 *)fw_msb)[0] = mac[1];
5522 ((u8 *)fw_msb)[1] = mac[0];
5523 ((u8 *)fw_mid)[0] = mac[3];
5524 ((u8 *)fw_mid)[1] = mac[2];
5525 ((u8 *)fw_lsb)[0] = mac[5];
5526 ((u8 *)fw_lsb)[1] = mac[4];