drivers/net/ethernet/qlogic/qed/qed_dev.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/types.h>
  34 #include <asm/byteorder.h>
  35 #include <linux/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/errno.h>
  39 #include <linux/kernel.h>
  40 #include <linux/mutex.h>
  41 #include <linux/pci.h>
  42 #include <linux/slab.h>
  43 #include <linux/string.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/qed/qed_chain.h>
  47 #include <linux/qed/qed_if.h>
  48 #include "qed.h"
  49 #include "qed_cxt.h"
  50 #include "qed_dcbx.h"
  51 #include "qed_dev_api.h"
  52 #include "qed_fcoe.h"
  53 #include "qed_hsi.h"
  54 #include "qed_hw.h"
  55 #include "qed_init_ops.h"
  56 #include "qed_int.h"
  57 #include "qed_iscsi.h"
  58 #include "qed_ll2.h"
  59 #include "qed_mcp.h"
  60 #include "qed_ooo.h"
  61 #include "qed_reg_addr.h"
  62 #include "qed_sp.h"
  63 #include "qed_sriov.h"
  64 #include "qed_vf.h"
  65 #include "qed_rdma.h"
  66
  67 static DEFINE_SPINLOCK(qm_lock);
  68
  69 /******************** Doorbell Recovery *******************/
  70 /* The doorbell recovery mechanism consists of a list of entries which represent
  71  * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
  72  * entity needs to register with the mechanism and provide the parameters
  73  * describing it's doorbell, including a location where last used doorbell data
  74  * can be found. The doorbell execute function will traverse the list and
  75  * doorbell all of the registered entries.
  76  */
  77 struct qed_db_recovery_entry {
  78         struct list_head list_entry;
  79         void __iomem *db_addr;
  80         void *db_data;
  81         enum qed_db_rec_width db_width;
  82         enum qed_db_rec_space db_space;
  83         u8 hwfn_idx;
  84 };
  85
  86 /* Display a single doorbell recovery entry */
  87 static void qed_db_recovery_dp_entry(struct qed_hwfn *p_hwfn,
  88                                      struct qed_db_recovery_entry *db_entry,
  89                                      char *action)
  90 {
  91         DP_VERBOSE(p_hwfn,
  92                    QED_MSG_SPQ,
  93                    "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
  94                    action,
  95                    db_entry,
  96                    db_entry->db_addr,
  97                    db_entry->db_data,
  98                    db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
  99                    db_entry->db_space == DB_REC_USER ? "user" : "kernel",
 100                    db_entry->hwfn_idx);
 101 }
 102
 103 /* Doorbell address sanity (address within doorbell bar range) */
 104 static bool qed_db_rec_sanity(struct qed_dev *cdev,
 105                               void __iomem *db_addr, void *db_data)
 106 {
 107         /* Make sure doorbell address is within the doorbell bar */
 108         if (db_addr < cdev->doorbells ||
 109             (u8 __iomem *)db_addr >
 110             (u8 __iomem *)cdev->doorbells + cdev->db_size) {
 111                 WARN(true,
 112                      "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
 113                      db_addr,
 114                      cdev->doorbells,
 115                      (u8 __iomem *)cdev->doorbells + cdev->db_size);
 116                 return false;
 117         }
 118
 119         /* ake sure doorbell data pointer is not null */
 120         if (!db_data) {
 121                 WARN(true, "Illegal doorbell data pointer: %p", db_data);
 122                 return false;
 123         }
 124
 125         return true;
 126 }
 127
 128 /* Find hwfn according to the doorbell address */
 129 static struct qed_hwfn *qed_db_rec_find_hwfn(struct qed_dev *cdev,
 130                                              void __iomem *db_addr)
 131 {
 132         struct qed_hwfn *p_hwfn;
 133
 134         /* In CMT doorbell bar is split down the middle between engine 0 and enigne 1 */
 135         if (cdev->num_hwfns > 1)
 136                 p_hwfn = db_addr < cdev->hwfns[1].doorbells ?
 137                     &cdev->hwfns[0] : &cdev->hwfns[1];
 138         else
 139                 p_hwfn = QED_LEADING_HWFN(cdev);
 140
 141         return p_hwfn;
 142 }
 143
 144 /* Add a new entry to the doorbell recovery mechanism */
 145 int qed_db_recovery_add(struct qed_dev *cdev,
 146                         void __iomem *db_addr,
 147                         void *db_data,
 148                         enum qed_db_rec_width db_width,
 149                         enum qed_db_rec_space db_space)
 150 {
 151         struct qed_db_recovery_entry *db_entry;
 152         struct qed_hwfn *p_hwfn;
 153
 154         /* Shortcircuit VFs, for now */
 155         if (IS_VF(cdev)) {
 156                 DP_VERBOSE(cdev,
 157                            QED_MSG_IOV, "db recovery - skipping VF doorbell\n");
 158                 return 0;
 159         }
 160
 161         /* Sanitize doorbell address */
 162         if (!qed_db_rec_sanity(cdev, db_addr, db_data))
 163                 return -EINVAL;
 164
 165         /* Obtain hwfn from doorbell address */
 166         p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr);
 167
 168         /* Create entry */
 169         db_entry = kzalloc(sizeof(*db_entry), GFP_KERNEL);
 170         if (!db_entry) {
 171                 DP_NOTICE(cdev, "Failed to allocate a db recovery entry\n");
 172                 return -ENOMEM;
 173         }
 174
 175         /* Populate entry */
 176         db_entry->db_addr = db_addr;
 177         db_entry->db_data = db_data;
 178         db_entry->db_width = db_width;
 179         db_entry->db_space = db_space;
 180         db_entry->hwfn_idx = p_hwfn->my_id;
 181
 182         /* Display */
 183         qed_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
 184
 185         /* Protect the list */
 186         spin_lock_bh(&p_hwfn->db_recovery_info.lock);
 187         list_add_tail(&db_entry->list_entry, &p_hwfn->db_recovery_info.list);
 188         spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
 189
 190         return 0;
 191 }
 192
 193 /* Remove an entry from the doorbell recovery mechanism */
 194 int qed_db_recovery_del(struct qed_dev *cdev,
 195                         void __iomem *db_addr, void *db_data)
 196 {
 197         struct qed_db_recovery_entry *db_entry = NULL;
 198         struct qed_hwfn *p_hwfn;
 199         int rc = -EINVAL;
 200
 201         /* Shortcircuit VFs, for now */
 202         if (IS_VF(cdev)) {
 203                 DP_VERBOSE(cdev,
 204                            QED_MSG_IOV, "db recovery - skipping VF doorbell\n");
 205                 return 0;
 206         }
 207
 208         /* Sanitize doorbell address */
 209         if (!qed_db_rec_sanity(cdev, db_addr, db_data))
 210                 return -EINVAL;
 211
 212         /* Obtain hwfn from doorbell address */
 213         p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr);
 214
 215         /* Protect the list */
 216         spin_lock_bh(&p_hwfn->db_recovery_info.lock);
 217         list_for_each_entry(db_entry,
 218                             &p_hwfn->db_recovery_info.list, list_entry) {
 219                 /* search according to db_data addr since db_addr is not unique (roce) */
 220                 if (db_entry->db_data == db_data) {
 221                         qed_db_recovery_dp_entry(p_hwfn, db_entry, "Deleting");
 222                         list_del(&db_entry->list_entry);
 223                         rc = 0;
 224                         break;
 225                 }
 226         }
 227
 228         spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
 229
 230         if (rc == -EINVAL)
 231
 232                 DP_NOTICE(p_hwfn,
 233                           "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
 234                           db_data, db_addr);
 235         else
 236                 kfree(db_entry);
 237
 238         return rc;
 239 }
 240
 241 /* Initialize the doorbell recovery mechanism */
 242 static int qed_db_recovery_setup(struct qed_hwfn *p_hwfn)
 243 {
 244         DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Setting up db recovery\n");
 245
 246         /* Make sure db_size was set in cdev */
 247         if (!p_hwfn->cdev->db_size) {
 248                 DP_ERR(p_hwfn->cdev, "db_size not set\n");
 249                 return -EINVAL;
 250         }
 251
 252         INIT_LIST_HEAD(&p_hwfn->db_recovery_info.list);
 253         spin_lock_init(&p_hwfn->db_recovery_info.lock);
 254         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 255
 256         return 0;
 257 }
 258
 259 /* Destroy the doorbell recovery mechanism */
 260 static void qed_db_recovery_teardown(struct qed_hwfn *p_hwfn)
 261 {
 262         struct qed_db_recovery_entry *db_entry = NULL;
 263
 264         DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Tearing down db recovery\n");
 265         if (!list_empty(&p_hwfn->db_recovery_info.list)) {
 266                 DP_VERBOSE(p_hwfn,
 267                            QED_MSG_SPQ,
 268                            "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
 269                 while (!list_empty(&p_hwfn->db_recovery_info.list)) {
 270                         db_entry =
 271                             list_first_entry(&p_hwfn->db_recovery_info.list,
 272                                              struct qed_db_recovery_entry,
 273                                              list_entry);
 274                         qed_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
 275                         list_del(&db_entry->list_entry);
 276                         kfree(db_entry);
 277                 }
 278         }
 279         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 280 }
 281
 282 /* Print the content of the doorbell recovery mechanism */
 283 void qed_db_recovery_dp(struct qed_hwfn *p_hwfn)
 284 {
 285         struct qed_db_recovery_entry *db_entry = NULL;
 286
 287         DP_NOTICE(p_hwfn,
 288                   "Displaying doorbell recovery database. Counter was %d\n",
 289                   p_hwfn->db_recovery_info.db_recovery_counter);
 290
 291         /* Protect the list */
 292         spin_lock_bh(&p_hwfn->db_recovery_info.lock);
 293         list_for_each_entry(db_entry,
 294                             &p_hwfn->db_recovery_info.list, list_entry) {
 295                 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
 296         }
 297
 298         spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
 299 }
 300
 301 /* Ring the doorbell of a single doorbell recovery entry */
 302 static void qed_db_recovery_ring(struct qed_hwfn *p_hwfn,
 303                                  struct qed_db_recovery_entry *db_entry,
 304                                  enum qed_db_rec_exec db_exec)
 305 {
 306         if (db_exec != DB_REC_ONCE) {
 307                 /* Print according to width */
 308                 if (db_entry->db_width == DB_REC_WIDTH_32B) {
 309                         DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
 310                                    "%s doorbell address %p data %x\n",
 311                                    db_exec == DB_REC_DRY_RUN ?
 312                                    "would have rung" : "ringing",
 313                                    db_entry->db_addr,
 314                                    *(u32 *)db_entry->db_data);
 315                 } else {
 316                         DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
 317                                    "%s doorbell address %p data %llx\n",
 318                                    db_exec == DB_REC_DRY_RUN ?
 319                                    "would have rung" : "ringing",
 320                                    db_entry->db_addr,
 321                                    *(u64 *)(db_entry->db_data));
 322                 }
 323         }
 324
 325         /* Sanity */
 326         if (!qed_db_rec_sanity(p_hwfn->cdev, db_entry->db_addr,
 327                                db_entry->db_data))
 328                 return;
 329
 330         /* Flush the write combined buffer. Since there are multiple doorbelling
 331          * entities using the same address, if we don't flush, a transaction
 332          * could be lost.
 333          */
 334         wmb();
 335
 336         /* Ring the doorbell */
 337         if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) {
 338                 if (db_entry->db_width == DB_REC_WIDTH_32B)
 339                         DIRECT_REG_WR(db_entry->db_addr,
 340                                       *(u32 *)(db_entry->db_data));
 341                 else
 342                         DIRECT_REG_WR64(db_entry->db_addr,
 343                                         *(u64 *)(db_entry->db_data));
 344         }
 345
 346         /* Flush the write combined buffer. Next doorbell may come from a
 347          * different entity to the same address...
 348          */
 349         wmb();
 350 }
 351
 352 /* Traverse the doorbell recovery entry list and ring all the doorbells */
 353 void qed_db_recovery_execute(struct qed_hwfn *p_hwfn,
 354                              enum qed_db_rec_exec db_exec)
 355 {
 356         struct qed_db_recovery_entry *db_entry = NULL;
 357
 358         if (db_exec != DB_REC_ONCE) {
 359                 DP_NOTICE(p_hwfn,
 360                           "Executing doorbell recovery. Counter was %d\n",
 361                           p_hwfn->db_recovery_info.db_recovery_counter);
 362
 363                 /* Track amount of times recovery was executed */
 364                 p_hwfn->db_recovery_info.db_recovery_counter++;
 365         }
 366
 367         /* Protect the list */
 368         spin_lock_bh(&p_hwfn->db_recovery_info.lock);
 369         list_for_each_entry(db_entry,
 370                             &p_hwfn->db_recovery_info.list, list_entry) {
 371                 qed_db_recovery_ring(p_hwfn, db_entry, db_exec);
 372                 if (db_exec == DB_REC_ONCE)
 373                         break;
 374         }
 375
 376         spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
 377 }
 378
 379 /******************** Doorbell Recovery end ****************/
 380
 381 #define QED_MIN_DPIS            (4)
 382 #define QED_MIN_PWM_REGION      (QED_WID_SIZE * QED_MIN_DPIS)
 383
 384 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
 385                            struct qed_ptt *p_ptt, enum BAR_ID bar_id)
 386 {
 387         u32 bar_reg = (bar_id == BAR_ID_0 ?
 388                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
 389         u32 val;
 390
 391         if (IS_VF(p_hwfn->cdev))
 392                 return qed_vf_hw_bar_size(p_hwfn, bar_id);
 393
 394         val = qed_rd(p_hwfn, p_ptt, bar_reg);
 395         if (val)
 396                 return 1 << (val + 15);
 397
 398         /* Old MFW initialized above registered only conditionally */
 399         if (p_hwfn->cdev->num_hwfns > 1) {
 400                 DP_INFO(p_hwfn,
 401                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
 402                         return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
 403         } else {
 404                 DP_INFO(p_hwfn,
 405                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
 406                         return 512 * 1024;
 407         }
 408 }
 409
 410 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
 411 {
 412         u32 i;
 413
 414         cdev->dp_level = dp_level;
 415         cdev->dp_module = dp_module;
 416         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 417                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 418
 419                 p_hwfn->dp_level = dp_level;
 420                 p_hwfn->dp_module = dp_module;
 421         }
 422 }
 423
 424 void qed_init_struct(struct qed_dev *cdev)
 425 {
 426         u8 i;
 427
 428         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 429                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 430
 431                 p_hwfn->cdev = cdev;
 432                 p_hwfn->my_id = i;
 433                 p_hwfn->b_active = false;
 434
 435                 mutex_init(&p_hwfn->dmae_info.mutex);
 436         }
 437
 438         /* hwfn 0 is always active */
 439         cdev->hwfns[0].b_active = true;
 440
 441         /* set the default cache alignment to 128 */
 442         cdev->cache_shift = 7;
 443 }
 444
 445 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
 446 {
 447         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 448
 449         kfree(qm_info->qm_pq_params);
 450         qm_info->qm_pq_params = NULL;
 451         kfree(qm_info->qm_vport_params);
 452         qm_info->qm_vport_params = NULL;
 453         kfree(qm_info->qm_port_params);
 454         qm_info->qm_port_params = NULL;
 455         kfree(qm_info->wfq_data);
 456         qm_info->wfq_data = NULL;
 457 }
 458
 459 static void qed_dbg_user_data_free(struct qed_hwfn *p_hwfn)
 460 {
 461         kfree(p_hwfn->dbg_user_info);
 462         p_hwfn->dbg_user_info = NULL;
 463 }
 464
 465 void qed_resc_free(struct qed_dev *cdev)
 466 {
 467         int i;
 468
 469         if (IS_VF(cdev)) {
 470                 for_each_hwfn(cdev, i)
 471                         qed_l2_free(&cdev->hwfns[i]);
 472                 return;
 473         }
 474
 475         kfree(cdev->fw_data);
 476         cdev->fw_data = NULL;
 477
 478         kfree(cdev->reset_stats);
 479         cdev->reset_stats = NULL;
 480
 481         for_each_hwfn(cdev, i) {
 482                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 483
 484                 qed_cxt_mngr_free(p_hwfn);
 485                 qed_qm_info_free(p_hwfn);
 486                 qed_spq_free(p_hwfn);
 487                 qed_eq_free(p_hwfn);
 488                 qed_consq_free(p_hwfn);
 489                 qed_int_free(p_hwfn);
 490 #ifdef CONFIG_QED_LL2
 491                 qed_ll2_free(p_hwfn);
 492 #endif
 493                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
 494                         qed_fcoe_free(p_hwfn);
 495
 496                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 497                         qed_iscsi_free(p_hwfn);
 498                         qed_ooo_free(p_hwfn);
 499                 }
 500
 501                 if (QED_IS_RDMA_PERSONALITY(p_hwfn))
 502                         qed_rdma_info_free(p_hwfn);
 503
 504                 qed_iov_free(p_hwfn);
 505                 qed_l2_free(p_hwfn);
 506                 qed_dmae_info_free(p_hwfn);
 507                 qed_dcbx_info_free(p_hwfn);
 508                 qed_dbg_user_data_free(p_hwfn);
 509
 510                 /* Destroy doorbell recovery mechanism */
 511                 qed_db_recovery_teardown(p_hwfn);
 512         }
 513 }
 514
 515 /******************** QM initialization *******************/
 516 #define ACTIVE_TCS_BMAP 0x9f
 517 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 518
 519 /* determines the physical queue flags for a given PF. */
 520 static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn)
 521 {
 522         u32 flags;
 523
 524         /* common flags */
 525         flags = PQ_FLAGS_LB;
 526
 527         /* feature flags */
 528         if (IS_QED_SRIOV(p_hwfn->cdev))
 529                 flags |= PQ_FLAGS_VFS;
 530
 531         /* protocol flags */
 532         switch (p_hwfn->hw_info.personality) {
 533         case QED_PCI_ETH:
 534                 flags |= PQ_FLAGS_MCOS;
 535                 break;
 536         case QED_PCI_FCOE:
 537                 flags |= PQ_FLAGS_OFLD;
 538                 break;
 539         case QED_PCI_ISCSI:
 540                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 541                 break;
 542         case QED_PCI_ETH_ROCE:
 543                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
 544                 if (IS_QED_MULTI_TC_ROCE(p_hwfn))
 545                         flags |= PQ_FLAGS_MTC;
 546                 break;
 547         case QED_PCI_ETH_IWARP:
 548                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
 549                     PQ_FLAGS_OFLD;
 550                 break;
 551         default:
 552                 DP_ERR(p_hwfn,
 553                        "unknown personality %d\n", p_hwfn->hw_info.personality);
 554                 return 0;
 555         }
 556
 557         return flags;
 558 }
 559
 560 /* Getters for resource amounts necessary for qm initialization */
 561 static u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn)
 562 {
 563         return p_hwfn->hw_info.num_hw_tc;
 564 }
 565
 566 static u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn)
 567 {
 568         return IS_QED_SRIOV(p_hwfn->cdev) ?
 569                p_hwfn->cdev->p_iov_info->total_vfs : 0;
 570 }
 571
 572 static u8 qed_init_qm_get_num_mtc_tcs(struct qed_hwfn *p_hwfn)
 573 {
 574         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 575
 576         if (!(PQ_FLAGS_MTC & pq_flags))
 577                 return 1;
 578
 579         return qed_init_qm_get_num_tcs(p_hwfn);
 580 }
 581
 582 #define NUM_DEFAULT_RLS 1
 583
 584 static u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
 585 {
 586         u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
 587
 588         /* num RLs can't exceed resource amount of rls or vports */
 589         num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
 590                                  RESC_NUM(p_hwfn, QED_VPORT));
 591
 592         /* Make sure after we reserve there's something left */
 593         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
 594                 return 0;
 595
 596         /* subtract rls necessary for VFs and one default one for the PF */
 597         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 598
 599         return num_pf_rls;
 600 }
 601
 602 static u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn)
 603 {
 604         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 605
 606         /* all pqs share the same vport, except for vfs and pf_rl pqs */
 607         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 608                qed_init_qm_get_num_pf_rls(p_hwfn) +
 609                (!!(PQ_FLAGS_VFS & pq_flags)) *
 610                qed_init_qm_get_num_vfs(p_hwfn) + 1;
 611 }
 612
 613 /* calc amount of PQs according to the requested flags */
 614 static u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn)
 615 {
 616         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 617
 618         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 619                qed_init_qm_get_num_pf_rls(p_hwfn) +
 620                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 621                qed_init_qm_get_num_tcs(p_hwfn) +
 622                (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) +
 623                (!!(PQ_FLAGS_ACK & pq_flags)) +
 624                (!!(PQ_FLAGS_OFLD & pq_flags)) *
 625                qed_init_qm_get_num_mtc_tcs(p_hwfn) +
 626                (!!(PQ_FLAGS_LLT & pq_flags)) *
 627                qed_init_qm_get_num_mtc_tcs(p_hwfn) +
 628                (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn);
 629 }
 630
 631 /* initialize the top level QM params */
 632 static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
 633 {
 634         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 635         bool four_port;
 636
 637         /* pq and vport bases for this PF */
 638         qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
 639         qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
 640
 641         /* rate limiting and weighted fair queueing are always enabled */
 642         qm_info->vport_rl_en = true;
 643         qm_info->vport_wfq_en = true;
 644
 645         /* TC config is different for AH 4 port */
 646         four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2;
 647
 648         /* in AH 4 port we have fewer TCs per port */
 649         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 650                                                      NUM_OF_PHYS_TCS;
 651
 652         /* unless MFW indicated otherwise, ooo_tc == 3 for
 653          * AH 4-port and 4 otherwise.
 654          */
 655         if (!qm_info->ooo_tc)
 656                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 657                                               DCBX_TCP_OOO_TC;
 658 }
 659
 660 /* initialize qm vport params */
 661 static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn)
 662 {
 663         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 664         u8 i;
 665
 666         /* all vports participate in weighted fair queueing */
 667         for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++)
 668                 qm_info->qm_vport_params[i].vport_wfq = 1;
 669 }
 670
 671 /* initialize qm port params */
 672 static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
 673 {
 674         /* Initialize qm port parameters */
 675         u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine;
 676
 677         /* indicate how ooo and high pri traffic is dealt with */
 678         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 679                           ACTIVE_TCS_BMAP_4PORT_K2 :
 680                           ACTIVE_TCS_BMAP;
 681
 682         for (i = 0; i < num_ports; i++) {
 683                 struct init_qm_port_params *p_qm_port =
 684                     &p_hwfn->qm_info.qm_port_params[i];
 685
 686                 p_qm_port->active = 1;
 687                 p_qm_port->active_phys_tcs = active_phys_tcs;
 688                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 689                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 690         }
 691 }
 692
 693 /* Reset the params which must be reset for qm init. QM init may be called as
 694  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 695  * params may be affected by the init but would simply recalculate to the same
 696  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 697  * affected as these amounts stay the same.
 698  */
 699 static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn)
 700 {
 701         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 702
 703         qm_info->num_pqs = 0;
 704         qm_info->num_vports = 0;
 705         qm_info->num_pf_rls = 0;
 706         qm_info->num_vf_pqs = 0;
 707         qm_info->first_vf_pq = 0;
 708         qm_info->first_mcos_pq = 0;
 709         qm_info->first_rl_pq = 0;
 710 }
 711
 712 static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
 713 {
 714         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 715
 716         qm_info->num_vports++;
 717
 718         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
 719                 DP_ERR(p_hwfn,
 720                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
 721                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
 722 }
 723
 724 /* initialize a single pq and manage qm_info resources accounting.
 725  * The pq_init_flags param determines whether the PQ is rate limited
 726  * (for VF or PF) and whether a new vport is allocated to the pq or not
 727  * (i.e. vport will be shared).
 728  */
 729
 730 /* flags for pq init */
 731 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 732 #define PQ_INIT_PF_RL           (1 << 1)
 733 #define PQ_INIT_VF_RL           (1 << 2)
 734
 735 /* defines for pq init */
 736 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 737 #define PQ_INIT_DEFAULT_TC              0
 738
 739 void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc)
 740 {
 741         p_info->offload_tc = tc;
 742         p_info->offload_tc_set = true;
 743 }
 744
 745 static bool qed_is_offload_tc_set(struct qed_hwfn *p_hwfn)
 746 {
 747         return p_hwfn->hw_info.offload_tc_set;
 748 }
 749
 750 static u32 qed_get_offload_tc(struct qed_hwfn *p_hwfn)
 751 {
 752         if (qed_is_offload_tc_set(p_hwfn))
 753                 return p_hwfn->hw_info.offload_tc;
 754
 755         return PQ_INIT_DEFAULT_TC;
 756 }
 757
 758 static void qed_init_qm_pq(struct qed_hwfn *p_hwfn,
 759                            struct qed_qm_info *qm_info,
 760                            u8 tc, u32 pq_init_flags)
 761 {
 762         u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn);
 763
 764         if (pq_idx > max_pq)
 765                 DP_ERR(p_hwfn,
 766                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 767
 768         /* init pq params */
 769         qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
 770         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 771             qm_info->num_vports;
 772         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 773         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 774         qm_info->qm_pq_params[pq_idx].rl_valid =
 775             (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
 776
 777         /* qm params accounting */
 778         qm_info->num_pqs++;
 779         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 780                 qm_info->num_vports++;
 781
 782         if (pq_init_flags & PQ_INIT_PF_RL)
 783                 qm_info->num_pf_rls++;
 784
 785         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
 786                 DP_ERR(p_hwfn,
 787                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
 788                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
 789
 790         if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn))
 791                 DP_ERR(p_hwfn,
 792                        "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n",
 793                        qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn));
 794 }
 795
 796 /* get pq index according to PQ_FLAGS */
 797 static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn,
 798                                            unsigned long pq_flags)
 799 {
 800         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 801
 802         /* Can't have multiple flags set here */
 803         if (bitmap_weight(&pq_flags,
 804                           sizeof(pq_flags) * BITS_PER_BYTE) > 1) {
 805                 DP_ERR(p_hwfn, "requested multiple pq flags 0x%lx\n", pq_flags);
 806                 goto err;
 807         }
 808
 809         if (!(qed_get_pq_flags(p_hwfn) & pq_flags)) {
 810                 DP_ERR(p_hwfn, "pq flag 0x%lx is not set\n", pq_flags);
 811                 goto err;
 812         }
 813
 814         switch (pq_flags) {
 815         case PQ_FLAGS_RLS:
 816                 return &qm_info->first_rl_pq;
 817         case PQ_FLAGS_MCOS:
 818                 return &qm_info->first_mcos_pq;
 819         case PQ_FLAGS_LB:
 820                 return &qm_info->pure_lb_pq;
 821         case PQ_FLAGS_OOO:
 822                 return &qm_info->ooo_pq;
 823         case PQ_FLAGS_ACK:
 824                 return &qm_info->pure_ack_pq;
 825         case PQ_FLAGS_OFLD:
 826                 return &qm_info->first_ofld_pq;
 827         case PQ_FLAGS_LLT:
 828                 return &qm_info->first_llt_pq;
 829         case PQ_FLAGS_VFS:
 830                 return &qm_info->first_vf_pq;
 831         default:
 832                 goto err;
 833         }
 834
 835 err:
 836         return &qm_info->start_pq;
 837 }
 838
 839 /* save pq index in qm info */
 840 static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn,
 841                                 u32 pq_flags, u16 pq_val)
 842 {
 843         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 844
 845         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 846 }
 847
 848 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 849 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags)
 850 {
 851         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 852
 853         return *base_pq_idx + CM_TX_PQ_BASE;
 854 }
 855
 856 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc)
 857 {
 858         u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn);
 859
 860         if (max_tc == 0) {
 861                 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
 862                        PQ_FLAGS_MCOS);
 863                 return p_hwfn->qm_info.start_pq;
 864         }
 865
 866         if (tc > max_tc)
 867                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 868
 869         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc);
 870 }
 871
 872 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf)
 873 {
 874         u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn);
 875
 876         if (max_vf == 0) {
 877                 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
 878                        PQ_FLAGS_VFS);
 879                 return p_hwfn->qm_info.start_pq;
 880         }
 881
 882         if (vf > max_vf)
 883                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 884
 885         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf);
 886 }
 887
 888 u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc)
 889 {
 890         u16 first_ofld_pq, pq_offset;
 891
 892         first_ofld_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD);
 893         pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
 894                     tc : PQ_INIT_DEFAULT_TC;
 895
 896         return first_ofld_pq + pq_offset;
 897 }
 898
 899 u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc)
 900 {
 901         u16 first_llt_pq, pq_offset;
 902
 903         first_llt_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LLT);
 904         pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
 905                     tc : PQ_INIT_DEFAULT_TC;
 906
 907         return first_llt_pq + pq_offset;
 908 }
 909
 910 /* Functions for creating specific types of pqs */
 911 static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn)
 912 {
 913         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 914
 915         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 916                 return;
 917
 918         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 919         qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 920 }
 921
 922 static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn)
 923 {
 924         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 925
 926         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 927                 return;
 928
 929         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 930         qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 931 }
 932
 933 static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn)
 934 {
 935         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 936
 937         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 938                 return;
 939
 940         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 941         qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
 942                        PQ_INIT_SHARE_VPORT);
 943 }
 944
 945 static void qed_init_qm_mtc_pqs(struct qed_hwfn *p_hwfn)
 946 {
 947         u8 num_tcs = qed_init_qm_get_num_mtc_tcs(p_hwfn);
 948         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 949         u8 tc;
 950
 951         /* override pq's TC if offload TC is set */
 952         for (tc = 0; tc < num_tcs; tc++)
 953                 qed_init_qm_pq(p_hwfn, qm_info,
 954                                qed_is_offload_tc_set(p_hwfn) ?
 955                                p_hwfn->hw_info.offload_tc : tc,
 956                                PQ_INIT_SHARE_VPORT);
 957 }
 958
 959 static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn)
 960 {
 961         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 962
 963         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 964                 return;
 965
 966         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 967         qed_init_qm_mtc_pqs(p_hwfn);
 968 }
 969
 970 static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn)
 971 {
 972         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 973
 974         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
 975                 return;
 976
 977         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
 978         qed_init_qm_mtc_pqs(p_hwfn);
 979 }
 980
 981 static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn)
 982 {
 983         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 984         u8 tc_idx;
 985
 986         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 987                 return;
 988
 989         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 990         for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 991                 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 992 }
 993
 994 static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn)
 995 {
 996         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 997         u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
 998
 999         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
1000                 return;
1001
1002         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
1003         qm_info->num_vf_pqs = num_vfs;
1004         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
1005                 qed_init_qm_pq(p_hwfn,
1006                                qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
1007 }
1008
1009 static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn)
1010 {
1011         u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn);
1012         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1013
1014         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
1015                 return;
1016
1017         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
1018         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
1019                 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
1020                                PQ_INIT_PF_RL);
1021 }
1022
1023 static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn)
1024 {
1025         /* rate limited pqs, must come first (FW assumption) */
1026         qed_init_qm_rl_pqs(p_hwfn);
1027
1028         /* pqs for multi cos */
1029         qed_init_qm_mcos_pqs(p_hwfn);
1030
1031         /* pure loopback pq */
1032         qed_init_qm_lb_pq(p_hwfn);
1033
1034         /* out of order pq */
1035         qed_init_qm_ooo_pq(p_hwfn);
1036
1037         /* pure ack pq */
1038         qed_init_qm_pure_ack_pq(p_hwfn);
1039
1040         /* pq for offloaded protocol */
1041         qed_init_qm_offload_pq(p_hwfn);
1042
1043         /* low latency pq */
1044         qed_init_qm_low_latency_pq(p_hwfn);
1045
1046         /* done sharing vports */
1047         qed_init_qm_advance_vport(p_hwfn);
1048
1049         /* pqs for vfs */
1050         qed_init_qm_vf_pqs(p_hwfn);
1051 }
1052
1053 /* compare values of getters against resources amounts */
1054 static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn)
1055 {
1056         if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) {
1057                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
1058                 return -EINVAL;
1059         }
1060
1061         if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
1062                 return 0;
1063
1064         if (QED_IS_ROCE_PERSONALITY(p_hwfn)) {
1065                 p_hwfn->hw_info.multi_tc_roce_en = 0;
1066                 DP_NOTICE(p_hwfn,
1067                           "multi-tc roce was disabled to reduce requested amount of pqs\n");
1068                 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
1069                         return 0;
1070         }
1071
1072         DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
1073         return -EINVAL;
1074 }
1075
1076 static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn)
1077 {
1078         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1079         struct init_qm_vport_params *vport;
1080         struct init_qm_port_params *port;
1081         struct init_qm_pq_params *pq;
1082         int i, tc;
1083
1084         /* top level params */
1085         DP_VERBOSE(p_hwfn,
1086                    NETIF_MSG_HW,
1087                    "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, llt_pq %d, pure_ack_pq %d\n",
1088                    qm_info->start_pq,
1089                    qm_info->start_vport,
1090                    qm_info->pure_lb_pq,
1091                    qm_info->first_ofld_pq,
1092                    qm_info->first_llt_pq,
1093                    qm_info->pure_ack_pq);
1094         DP_VERBOSE(p_hwfn,
1095                    NETIF_MSG_HW,
1096                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
1097                    qm_info->ooo_pq,
1098                    qm_info->first_vf_pq,
1099                    qm_info->num_pqs,
1100                    qm_info->num_vf_pqs,
1101                    qm_info->num_vports, qm_info->max_phys_tcs_per_port);
1102         DP_VERBOSE(p_hwfn,
1103                    NETIF_MSG_HW,
1104                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
1105                    qm_info->pf_rl_en,
1106                    qm_info->pf_wfq_en,
1107                    qm_info->vport_rl_en,
1108                    qm_info->vport_wfq_en,
1109                    qm_info->pf_wfq,
1110                    qm_info->pf_rl,
1111                    qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn));
1112
1113         /* port table */
1114         for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) {
1115                 port = &(qm_info->qm_port_params[i]);
1116                 DP_VERBOSE(p_hwfn,
1117                            NETIF_MSG_HW,
1118                            "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
1119                            i,
1120                            port->active,
1121                            port->active_phys_tcs,
1122                            port->num_pbf_cmd_lines,
1123                            port->num_btb_blocks, port->reserved);
1124         }
1125
1126         /* vport table */
1127         for (i = 0; i < qm_info->num_vports; i++) {
1128                 vport = &(qm_info->qm_vport_params[i]);
1129                 DP_VERBOSE(p_hwfn,
1130                            NETIF_MSG_HW,
1131                            "vport idx %d, vport_rl %d, wfq %d, first_tx_pq_id [ ",
1132                            qm_info->start_vport + i,
1133                            vport->vport_rl, vport->vport_wfq);
1134                 for (tc = 0; tc < NUM_OF_TCS; tc++)
1135                         DP_VERBOSE(p_hwfn,
1136                                    NETIF_MSG_HW,
1137                                    "%d ", vport->first_tx_pq_id[tc]);
1138                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n");
1139         }
1140
1141         /* pq table */
1142         for (i = 0; i < qm_info->num_pqs; i++) {
1143                 pq = &(qm_info->qm_pq_params[i]);
1144                 DP_VERBOSE(p_hwfn,
1145                            NETIF_MSG_HW,
1146                            "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
1147                            qm_info->start_pq + i,
1148                            pq->port_id,
1149                            pq->vport_id,
1150                            pq->tc_id, pq->wrr_group, pq->rl_valid);
1151         }
1152 }
1153
1154 static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
1155 {
1156         /* reset params required for init run */
1157         qed_init_qm_reset_params(p_hwfn);
1158
1159         /* init QM top level params */
1160         qed_init_qm_params(p_hwfn);
1161
1162         /* init QM port params */
1163         qed_init_qm_port_params(p_hwfn);
1164
1165         /* init QM vport params */
1166         qed_init_qm_vport_params(p_hwfn);
1167
1168         /* init QM physical queue params */
1169         qed_init_qm_pq_params(p_hwfn);
1170
1171         /* display all that init */
1172         qed_dp_init_qm_params(p_hwfn);
1173 }
1174
1175 /* This function reconfigures the QM pf on the fly.
1176  * For this purpose we:
1177  * 1. reconfigure the QM database
1178  * 2. set new values to runtime array
1179  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
1180  * 4. activate init tool in QM_PF stage
1181  * 5. send an sdm_qm_cmd through rbc interface to release the QM
1182  */
1183 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1184 {
1185         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1186         bool b_rc;
1187         int rc;
1188
1189         /* initialize qed's qm data structure */
1190         qed_init_qm_info(p_hwfn);
1191
1192         /* stop PF's qm queues */
1193         spin_lock_bh(&qm_lock);
1194         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
1195                                     qm_info->start_pq, qm_info->num_pqs);
1196         spin_unlock_bh(&qm_lock);
1197         if (!b_rc)
1198                 return -EINVAL;
1199
1200         /* clear the QM_PF runtime phase leftovers from previous init */
1201         qed_init_clear_rt_data(p_hwfn);
1202
1203         /* prepare QM portion of runtime array */
1204         qed_qm_init_pf(p_hwfn, p_ptt, false);
1205
1206         /* activate init tool on runtime array */
1207         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
1208                           p_hwfn->hw_info.hw_mode);
1209         if (rc)
1210                 return rc;
1211
1212         /* start PF's qm queues */
1213         spin_lock_bh(&qm_lock);
1214         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
1215                                     qm_info->start_pq, qm_info->num_pqs);
1216         spin_unlock_bh(&qm_lock);
1217         if (!b_rc)
1218                 return -EINVAL;
1219
1220         return 0;
1221 }
1222
1223 static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn)
1224 {
1225         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1226         int rc;
1227
1228         rc = qed_init_qm_sanity(p_hwfn);
1229         if (rc)
1230                 goto alloc_err;
1231
1232         qm_info->qm_pq_params = kcalloc(qed_init_qm_get_num_pqs(p_hwfn),
1233                                         sizeof(*qm_info->qm_pq_params),
1234                                         GFP_KERNEL);
1235         if (!qm_info->qm_pq_params)
1236                 goto alloc_err;
1237
1238         qm_info->qm_vport_params = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
1239                                            sizeof(*qm_info->qm_vport_params),
1240                                            GFP_KERNEL);
1241         if (!qm_info->qm_vport_params)
1242                 goto alloc_err;
1243
1244         qm_info->qm_port_params = kcalloc(p_hwfn->cdev->num_ports_in_engine,
1245                                           sizeof(*qm_info->qm_port_params),
1246                                           GFP_KERNEL);
1247         if (!qm_info->qm_port_params)
1248                 goto alloc_err;
1249
1250         qm_info->wfq_data = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
1251                                     sizeof(*qm_info->wfq_data),
1252                                     GFP_KERNEL);
1253         if (!qm_info->wfq_data)
1254                 goto alloc_err;
1255
1256         return 0;
1257
1258 alloc_err:
1259         DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
1260         qed_qm_info_free(p_hwfn);
1261         return -ENOMEM;
1262 }
1263
1264 int qed_resc_alloc(struct qed_dev *cdev)
1265 {
1266         u32 rdma_tasks, excess_tasks;
1267         u32 line_count;
1268         int i, rc = 0;
1269
1270         if (IS_VF(cdev)) {
1271                 for_each_hwfn(cdev, i) {
1272                         rc = qed_l2_alloc(&cdev->hwfns[i]);
1273                         if (rc)
1274                                 return rc;
1275                 }
1276                 return rc;
1277         }
1278
1279         cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
1280         if (!cdev->fw_data)
1281                 return -ENOMEM;
1282
1283         for_each_hwfn(cdev, i) {
1284                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1285                 u32 n_eqes, num_cons;
1286
1287                 /* Initialize the doorbell recovery mechanism */
1288                 rc = qed_db_recovery_setup(p_hwfn);
1289                 if (rc)
1290                         goto alloc_err;
1291
1292                 /* First allocate the context manager structure */
1293                 rc = qed_cxt_mngr_alloc(p_hwfn);
1294                 if (rc)
1295                         goto alloc_err;
1296
1297                 /* Set the HW cid/tid numbers (in the contest manager)
1298                  * Must be done prior to any further computations.
1299                  */
1300                 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
1301                 if (rc)
1302                         goto alloc_err;
1303
1304                 rc = qed_alloc_qm_data(p_hwfn);
1305                 if (rc)
1306                         goto alloc_err;
1307
1308                 /* init qm info */
1309                 qed_init_qm_info(p_hwfn);
1310
1311                 /* Compute the ILT client partition */
1312                 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
1313                 if (rc) {
1314                         DP_NOTICE(p_hwfn,
1315                                   "too many ILT lines; re-computing with less lines\n");
1316                         /* In case there are not enough ILT lines we reduce the
1317                          * number of RDMA tasks and re-compute.
1318                          */
1319                         excess_tasks =
1320                             qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count);
1321                         if (!excess_tasks)
1322                                 goto alloc_err;
1323
1324                         rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
1325                         rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks);
1326                         if (rc)
1327                                 goto alloc_err;
1328
1329                         rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
1330                         if (rc) {
1331                                 DP_ERR(p_hwfn,
1332                                        "failed ILT compute. Requested too many lines: %u\n",
1333                                        line_count);
1334
1335                                 goto alloc_err;
1336                         }
1337                 }
1338
1339                 /* CID map / ILT shadow table / T2
1340                  * The talbes sizes are determined by the computations above
1341                  */
1342                 rc = qed_cxt_tables_alloc(p_hwfn);
1343                 if (rc)
1344                         goto alloc_err;
1345
1346                 /* SPQ, must follow ILT because initializes SPQ context */
1347                 rc = qed_spq_alloc(p_hwfn);
1348                 if (rc)
1349                         goto alloc_err;
1350
1351                 /* SP status block allocation */
1352                 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
1353                                                          RESERVED_PTT_DPC);
1354
1355                 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
1356                 if (rc)
1357                         goto alloc_err;
1358
1359                 rc = qed_iov_alloc(p_hwfn);
1360                 if (rc)
1361                         goto alloc_err;
1362
1363                 /* EQ */
1364                 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
1365                 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
1366                         enum protocol_type rdma_proto;
1367
1368                         if (QED_IS_ROCE_PERSONALITY(p_hwfn))
1369                                 rdma_proto = PROTOCOLID_ROCE;
1370                         else
1371                                 rdma_proto = PROTOCOLID_IWARP;
1372
1373                         num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
1374                                                                rdma_proto,
1375                                                                NULL) * 2;
1376                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
1377                 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1378                         num_cons =
1379                             qed_cxt_get_proto_cid_count(p_hwfn,
1380                                                         PROTOCOLID_ISCSI,
1381                                                         NULL);
1382                         n_eqes += 2 * num_cons;
1383                 }
1384
1385                 if (n_eqes > 0xFFFF) {
1386                         DP_ERR(p_hwfn,
1387                                "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
1388                                n_eqes, 0xFFFF);
1389                         goto alloc_no_mem;
1390                 }
1391
1392                 rc = qed_eq_alloc(p_hwfn, (u16) n_eqes);
1393                 if (rc)
1394                         goto alloc_err;
1395
1396                 rc = qed_consq_alloc(p_hwfn);
1397                 if (rc)
1398                         goto alloc_err;
1399
1400                 rc = qed_l2_alloc(p_hwfn);
1401                 if (rc)
1402                         goto alloc_err;
1403
1404 #ifdef CONFIG_QED_LL2
1405                 if (p_hwfn->using_ll2) {
1406                         rc = qed_ll2_alloc(p_hwfn);
1407                         if (rc)
1408                                 goto alloc_err;
1409                 }
1410 #endif
1411
1412                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1413                         rc = qed_fcoe_alloc(p_hwfn);
1414                         if (rc)
1415                                 goto alloc_err;
1416                 }
1417
1418                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1419                         rc = qed_iscsi_alloc(p_hwfn);
1420                         if (rc)
1421                                 goto alloc_err;
1422                         rc = qed_ooo_alloc(p_hwfn);
1423                         if (rc)
1424                                 goto alloc_err;
1425                 }
1426
1427                 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
1428                         rc = qed_rdma_info_alloc(p_hwfn);
1429                         if (rc)
1430                                 goto alloc_err;
1431                 }
1432
1433                 /* DMA info initialization */
1434                 rc = qed_dmae_info_alloc(p_hwfn);
1435                 if (rc)
1436                         goto alloc_err;
1437
1438                 /* DCBX initialization */
1439                 rc = qed_dcbx_info_alloc(p_hwfn);
1440                 if (rc)
1441                         goto alloc_err;
1442
1443                 rc = qed_dbg_alloc_user_data(p_hwfn);
1444                 if (rc)
1445                         goto alloc_err;
1446         }
1447
1448         cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
1449         if (!cdev->reset_stats)
1450                 goto alloc_no_mem;
1451
1452         return 0;
1453
1454 alloc_no_mem:
1455         rc = -ENOMEM;
1456 alloc_err:
1457         qed_resc_free(cdev);
1458         return rc;
1459 }
1460
1461 void qed_resc_setup(struct qed_dev *cdev)
1462 {
1463         int i;
1464
1465         if (IS_VF(cdev)) {
1466                 for_each_hwfn(cdev, i)
1467                         qed_l2_setup(&cdev->hwfns[i]);
1468                 return;
1469         }
1470
1471         for_each_hwfn(cdev, i) {
1472                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1473
1474                 qed_cxt_mngr_setup(p_hwfn);
1475                 qed_spq_setup(p_hwfn);
1476                 qed_eq_setup(p_hwfn);
1477                 qed_consq_setup(p_hwfn);
1478
1479                 /* Read shadow of current MFW mailbox */
1480                 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1481                 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1482                        p_hwfn->mcp_info->mfw_mb_cur,
1483                        p_hwfn->mcp_info->mfw_mb_length);
1484
1485                 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1486
1487                 qed_l2_setup(p_hwfn);
1488                 qed_iov_setup(p_hwfn);
1489 #ifdef CONFIG_QED_LL2
1490                 if (p_hwfn->using_ll2)
1491                         qed_ll2_setup(p_hwfn);
1492 #endif
1493                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
1494                         qed_fcoe_setup(p_hwfn);
1495
1496                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1497                         qed_iscsi_setup(p_hwfn);
1498                         qed_ooo_setup(p_hwfn);
1499                 }
1500         }
1501 }
1502
1503 #define FINAL_CLEANUP_POLL_CNT          (100)
1504 #define FINAL_CLEANUP_POLL_TIME         (10)
1505 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
1506                       struct qed_ptt *p_ptt, u16 id, bool is_vf)
1507 {
1508         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1509         int rc = -EBUSY;
1510
1511         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1512                 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1513
1514         if (is_vf)
1515                 id += 0x10;
1516
1517         command |= X_FINAL_CLEANUP_AGG_INT <<
1518                 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1519         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1520         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1521         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1522
1523         /* Make sure notification is not set before initiating final cleanup */
1524         if (REG_RD(p_hwfn, addr)) {
1525                 DP_NOTICE(p_hwfn,
1526                           "Unexpected; Found final cleanup notification before initiating final cleanup\n");
1527                 REG_WR(p_hwfn, addr, 0);
1528         }
1529
1530         DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1531                    "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1532                    id, command);
1533
1534         qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1535
1536         /* Poll until completion */
1537         while (!REG_RD(p_hwfn, addr) && count--)
1538                 msleep(FINAL_CLEANUP_POLL_TIME);
1539
1540         if (REG_RD(p_hwfn, addr))
1541                 rc = 0;
1542         else
1543                 DP_NOTICE(p_hwfn,
1544                           "Failed to receive FW final cleanup notification\n");
1545
1546         /* Cleanup afterwards */
1547         REG_WR(p_hwfn, addr, 0);
1548
1549         return rc;
1550 }
1551
1552 static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
1553 {
1554         int hw_mode = 0;
1555
1556         if (QED_IS_BB_B0(p_hwfn->cdev)) {
1557                 hw_mode |= 1 << MODE_BB;
1558         } else if (QED_IS_AH(p_hwfn->cdev)) {
1559                 hw_mode |= 1 << MODE_K2;
1560         } else {
1561                 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
1562                           p_hwfn->cdev->type);
1563                 return -EINVAL;
1564         }
1565
1566         switch (p_hwfn->cdev->num_ports_in_engine) {
1567         case 1:
1568                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1569                 break;
1570         case 2:
1571                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1572                 break;
1573         case 4:
1574                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1575                 break;
1576         default:
1577                 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
1578                           p_hwfn->cdev->num_ports_in_engine);
1579                 return -EINVAL;
1580         }
1581
1582         if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits))
1583                 hw_mode |= 1 << MODE_MF_SD;
1584         else
1585                 hw_mode |= 1 << MODE_MF_SI;
1586
1587         hw_mode |= 1 << MODE_ASIC;
1588
1589         if (p_hwfn->cdev->num_hwfns > 1)
1590                 hw_mode |= 1 << MODE_100G;
1591
1592         p_hwfn->hw_info.hw_mode = hw_mode;
1593
1594         DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
1595                    "Configuring function for hw_mode: 0x%08x\n",
1596                    p_hwfn->hw_info.hw_mode);
1597
1598         return 0;
1599 }
1600
1601 /* Init run time data for all PFs on an engine. */
1602 static void qed_init_cau_rt_data(struct qed_dev *cdev)
1603 {
1604         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1605         int i, igu_sb_id;
1606
1607         for_each_hwfn(cdev, i) {
1608                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1609                 struct qed_igu_info *p_igu_info;
1610                 struct qed_igu_block *p_block;
1611                 struct cau_sb_entry sb_entry;
1612
1613                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1614
1615                 for (igu_sb_id = 0;
1616                      igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) {
1617                         p_block = &p_igu_info->entry[igu_sb_id];
1618
1619                         if (!p_block->is_pf)
1620                                 continue;
1621
1622                         qed_init_cau_sb_entry(p_hwfn, &sb_entry,
1623                                               p_block->function_id, 0, 0);
1624                         STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1625                                          sb_entry);
1626                 }
1627         }
1628 }
1629
1630 static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
1631                                      struct qed_ptt *p_ptt)
1632 {
1633         u32 val, wr_mbs, cache_line_size;
1634
1635         val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1636         switch (val) {
1637         case 0:
1638                 wr_mbs = 128;
1639                 break;
1640         case 1:
1641                 wr_mbs = 256;
1642                 break;
1643         case 2:
1644                 wr_mbs = 512;
1645                 break;
1646         default:
1647                 DP_INFO(p_hwfn,
1648                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1649                         val);
1650                 return;
1651         }
1652
1653         cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
1654         switch (cache_line_size) {
1655         case 32:
1656                 val = 0;
1657                 break;
1658         case 64:
1659                 val = 1;
1660                 break;
1661         case 128:
1662                 val = 2;
1663                 break;
1664         case 256:
1665                 val = 3;
1666                 break;
1667         default:
1668                 DP_INFO(p_hwfn,
1669                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1670                         cache_line_size);
1671         }
1672
1673         if (L1_CACHE_BYTES > wr_mbs)
1674                 DP_INFO(p_hwfn,
1675                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1676                         L1_CACHE_BYTES, wr_mbs);
1677
1678         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1679         if (val > 0) {
1680                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1681                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1682         }
1683 }
1684
1685 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
1686                               struct qed_ptt *p_ptt, int hw_mode)
1687 {
1688         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1689         struct qed_qm_common_rt_init_params params;
1690         struct qed_dev *cdev = p_hwfn->cdev;
1691         u8 vf_id, max_num_vfs;
1692         u16 num_pfs, pf_id;
1693         u32 concrete_fid;
1694         int rc = 0;
1695
1696         qed_init_cau_rt_data(cdev);
1697
1698         /* Program GTT windows */
1699         qed_gtt_init(p_hwfn);
1700
1701         if (p_hwfn->mcp_info) {
1702                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1703                         qm_info->pf_rl_en = true;
1704                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1705                         qm_info->pf_wfq_en = true;
1706         }
1707
1708         memset(&params, 0, sizeof(params));
1709         params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine;
1710         params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
1711         params.pf_rl_en = qm_info->pf_rl_en;
1712         params.pf_wfq_en = qm_info->pf_wfq_en;
1713         params.vport_rl_en = qm_info->vport_rl_en;
1714         params.vport_wfq_en = qm_info->vport_wfq_en;
1715         params.port_params = qm_info->qm_port_params;
1716
1717         qed_qm_common_rt_init(p_hwfn, &params);
1718
1719         qed_cxt_hw_init_common(p_hwfn);
1720
1721         qed_init_cache_line_size(p_hwfn, p_ptt);
1722
1723         rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1724         if (rc)
1725                 return rc;
1726
1727         qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1728         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1729
1730         if (QED_IS_BB(p_hwfn->cdev)) {
1731                 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
1732                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1733                         qed_fid_pretend(p_hwfn, p_ptt, pf_id);
1734                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1735                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1736                 }
1737                 /* pretend to original PF */
1738                 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1739         }
1740
1741         max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1742         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1743                 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
1744                 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
1745                 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1746                 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1747                 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1748                 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1749         }
1750         /* pretend to original PF */
1751         qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1752
1753         return rc;
1754 }
1755
1756 static int
1757 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
1758                      struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1759 {
1760         u32 dpi_bit_shift, dpi_count, dpi_page_size;
1761         u32 min_dpis;
1762         u32 n_wids;
1763
1764         /* Calculate DPI size */
1765         n_wids = max_t(u32, QED_MIN_WIDS, n_cpus);
1766         dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids);
1767         dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
1768         dpi_bit_shift = ilog2(dpi_page_size / 4096);
1769         dpi_count = pwm_region_size / dpi_page_size;
1770
1771         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1772         min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
1773
1774         p_hwfn->dpi_size = dpi_page_size;
1775         p_hwfn->dpi_count = dpi_count;
1776
1777         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1778
1779         if (dpi_count < min_dpis)
1780                 return -EINVAL;
1781
1782         return 0;
1783 }
1784
1785 enum QED_ROCE_EDPM_MODE {
1786         QED_ROCE_EDPM_MODE_ENABLE = 0,
1787         QED_ROCE_EDPM_MODE_FORCE_ON = 1,
1788         QED_ROCE_EDPM_MODE_DISABLE = 2,
1789 };
1790
1791 bool qed_edpm_enabled(struct qed_hwfn *p_hwfn)
1792 {
1793         if (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm)
1794                 return false;
1795
1796         return true;
1797 }
1798
1799 static int
1800 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1801 {
1802         u32 pwm_regsize, norm_regsize;
1803         u32 non_pwm_conn, min_addr_reg1;
1804         u32 db_bar_size, n_cpus = 1;
1805         u32 roce_edpm_mode;
1806         u32 pf_dems_shift;
1807         int rc = 0;
1808         u8 cond;
1809
1810         db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1811         if (p_hwfn->cdev->num_hwfns > 1)
1812                 db_bar_size /= 2;
1813
1814         /* Calculate doorbell regions */
1815         non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1816                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1817                                                    NULL) +
1818                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
1819                                                    NULL);
1820         norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE);
1821         min_addr_reg1 = norm_regsize / 4096;
1822         pwm_regsize = db_bar_size - norm_regsize;
1823
1824         /* Check that the normal and PWM sizes are valid */
1825         if (db_bar_size < norm_regsize) {
1826                 DP_ERR(p_hwfn->cdev,
1827                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1828                        db_bar_size, norm_regsize);
1829                 return -EINVAL;
1830         }
1831
1832         if (pwm_regsize < QED_MIN_PWM_REGION) {
1833                 DP_ERR(p_hwfn->cdev,
1834                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1835                        pwm_regsize,
1836                        QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
1837                 return -EINVAL;
1838         }
1839
1840         /* Calculate number of DPIs */
1841         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1842         if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
1843             ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
1844                 /* Either EDPM is mandatory, or we are attempting to allocate a
1845                  * WID per CPU.
1846                  */
1847                 n_cpus = num_present_cpus();
1848                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1849         }
1850
1851         cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
1852                (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
1853         if (cond || p_hwfn->dcbx_no_edpm) {
1854                 /* Either EDPM is disabled from user configuration, or it is
1855                  * disabled via DCBx, or it is not mandatory and we failed to
1856                  * allocated a WID per CPU.
1857                  */
1858                 n_cpus = 1;
1859                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1860
1861                 if (cond)
1862                         qed_rdma_dpm_bar(p_hwfn, p_ptt);
1863         }
1864
1865         p_hwfn->wid_count = (u16) n_cpus;
1866
1867         DP_INFO(p_hwfn,
1868                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s, page_size=%lu\n",
1869                 norm_regsize,
1870                 pwm_regsize,
1871                 p_hwfn->dpi_size,
1872                 p_hwfn->dpi_count,
1873                 (!qed_edpm_enabled(p_hwfn)) ?
1874                 "disabled" : "enabled", PAGE_SIZE);
1875
1876         if (rc) {
1877                 DP_ERR(p_hwfn,
1878                        "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
1879                        p_hwfn->dpi_count,
1880                        p_hwfn->pf_params.rdma_pf_params.min_dpis);
1881                 return -EINVAL;
1882         }
1883
1884         p_hwfn->dpi_start_offset = norm_regsize;
1885
1886         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1887         pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
1888         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1889         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1890
1891         return 0;
1892 }
1893
1894 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
1895                             struct qed_ptt *p_ptt, int hw_mode)
1896 {
1897         int rc = 0;
1898
1899         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
1900         if (rc)
1901                 return rc;
1902
1903         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
1904
1905         return 0;
1906 }
1907
1908 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
1909                           struct qed_ptt *p_ptt,
1910                           struct qed_tunnel_info *p_tunn,
1911                           int hw_mode,
1912                           bool b_hw_start,
1913                           enum qed_int_mode int_mode,
1914                           bool allow_npar_tx_switch)
1915 {
1916         u8 rel_pf_id = p_hwfn->rel_pf_id;
1917         int rc = 0;
1918
1919         if (p_hwfn->mcp_info) {
1920                 struct qed_mcp_function_info *p_info;
1921
1922                 p_info = &p_hwfn->mcp_info->func_info;
1923                 if (p_info->bandwidth_min)
1924                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1925
1926                 /* Update rate limit once we'll actually have a link */
1927                 p_hwfn->qm_info.pf_rl = 100000;
1928         }
1929
1930         qed_cxt_hw_init_pf(p_hwfn, p_ptt);
1931
1932         qed_int_igu_init_rt(p_hwfn);
1933
1934         /* Set VLAN in NIG if needed */
1935         if (hw_mode & BIT(MODE_MF_SD)) {
1936                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1937                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1938                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1939                              p_hwfn->hw_info.ovlan);
1940
1941                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1942                            "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
1943                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
1944                              1);
1945         }
1946
1947         /* Enable classification by MAC if needed */
1948         if (hw_mode & BIT(MODE_MF_SI)) {
1949                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1950                            "Configuring TAGMAC_CLS_TYPE\n");
1951                 STORE_RT_REG(p_hwfn,
1952                              NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
1953         }
1954
1955         /* Protocol Configuration */
1956         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1957                      (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
1958         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1959                      (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
1960         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1961
1962         /* Cleanup chip from previous driver if such remains exist */
1963         rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1964         if (rc)
1965                 return rc;
1966
1967         /* Sanity check before the PF init sequence that uses DMAE */
1968         rc = qed_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
1969         if (rc)
1970                 return rc;
1971
1972         /* PF Init sequence */
1973         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1974         if (rc)
1975                 return rc;
1976
1977         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1978         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1979         if (rc)
1980                 return rc;
1981
1982         /* Pure runtime initializations - directly to the HW  */
1983         qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1984
1985         rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1986         if (rc)
1987                 return rc;
1988
1989         if (b_hw_start) {
1990                 /* enable interrupts */
1991                 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
1992
1993                 /* send function start command */
1994                 rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,
1995                                      allow_npar_tx_switch);
1996                 if (rc) {
1997                         DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
1998                         return rc;
1999                 }
2000                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
2001                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
2002                         qed_wr(p_hwfn, p_ptt,
2003                                PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
2004                                0x100);
2005                 }
2006         }
2007         return rc;
2008 }
2009
2010 static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
2011                                struct qed_ptt *p_ptt,
2012                                u8 enable)
2013 {
2014         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
2015
2016         /* Change PF in PXP */
2017         qed_wr(p_hwfn, p_ptt,
2018                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
2019
2020         /* wait until value is set - try for 1 second every 50us */
2021         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
2022                 val = qed_rd(p_hwfn, p_ptt,
2023                              PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2024                 if (val == set_val)
2025                         break;
2026
2027                 usleep_range(50, 60);
2028         }
2029
2030         if (val != set_val) {
2031                 DP_NOTICE(p_hwfn,
2032                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
2033                 return -EAGAIN;
2034         }
2035
2036         return 0;
2037 }
2038
2039 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
2040                                 struct qed_ptt *p_main_ptt)
2041 {
2042         /* Read shadow of current MFW mailbox */
2043         qed_mcp_read_mb(p_hwfn, p_main_ptt);
2044         memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
2045                p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
2046 }
2047
2048 static void
2049 qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
2050                          struct qed_drv_load_params *p_drv_load)
2051 {
2052         memset(p_load_req, 0, sizeof(*p_load_req));
2053
2054         p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2055                                QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
2056         p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2057         p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2058         p_load_req->override_force_load = p_drv_load->override_force_load;
2059 }
2060
2061 static int qed_vf_start(struct qed_hwfn *p_hwfn,
2062                         struct qed_hw_init_params *p_params)
2063 {
2064         if (p_params->p_tunn) {
2065                 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2066                 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2067         }
2068
2069         p_hwfn->b_int_enabled = true;
2070
2071         return 0;
2072 }
2073
2074 int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
2075 {
2076         struct qed_load_req_params load_req_params;
2077         u32 load_code, resp, param, drv_mb_param;
2078         bool b_default_mtu = true;
2079         struct qed_hwfn *p_hwfn;
2080         int rc = 0, mfw_rc, i;
2081         u16 ether_type;
2082
2083         if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
2084                 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
2085                 return -EINVAL;
2086         }
2087
2088         if (IS_PF(cdev)) {
2089                 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
2090                 if (rc)
2091                         return rc;
2092         }
2093
2094         for_each_hwfn(cdev, i) {
2095                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2096
2097                 /* If management didn't provide a default, set one of our own */
2098                 if (!p_hwfn->hw_info.mtu) {
2099                         p_hwfn->hw_info.mtu = 1500;
2100                         b_default_mtu = false;
2101                 }
2102
2103                 if (IS_VF(cdev)) {
2104                         qed_vf_start(p_hwfn, p_params);
2105                         continue;
2106                 }
2107
2108                 /* Enable DMAE in PXP */
2109                 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
2110
2111                 rc = qed_calc_hw_mode(p_hwfn);
2112                 if (rc)
2113                         return rc;
2114
2115                 if (IS_PF(cdev) && (test_bit(QED_MF_8021Q_TAGGING,
2116                                              &cdev->mf_bits) ||
2117                                     test_bit(QED_MF_8021AD_TAGGING,
2118                                              &cdev->mf_bits))) {
2119                         if (test_bit(QED_MF_8021Q_TAGGING, &cdev->mf_bits))
2120                                 ether_type = ETH_P_8021Q;
2121                         else
2122                                 ether_type = ETH_P_8021AD;
2123                         STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
2124                                      ether_type);
2125                         STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
2126                                      ether_type);
2127                         STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
2128                                      ether_type);
2129                         STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
2130                                      ether_type);
2131                 }
2132
2133                 qed_fill_load_req_params(&load_req_params,
2134                                          p_params->p_drv_load_params);
2135                 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
2136                                       &load_req_params);
2137                 if (rc) {
2138                         DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
2139                         return rc;
2140                 }
2141
2142                 load_code = load_req_params.load_code;
2143                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
2144                            "Load request was sent. Load code: 0x%x\n",
2145                            load_code);
2146
2147                 qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
2148
2149                 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
2150
2151                 p_hwfn->first_on_engine = (load_code ==
2152                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
2153
2154                 switch (load_code) {
2155                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2156                         rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2157                                                 p_hwfn->hw_info.hw_mode);
2158                         if (rc)
2159                                 break;
2160                 /* Fall through */
2161                 case FW_MSG_CODE_DRV_LOAD_PORT:
2162                         rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2163                                               p_hwfn->hw_info.hw_mode);
2164                         if (rc)
2165                                 break;
2166
2167                 /* Fall through */
2168                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2169                         rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2170                                             p_params->p_tunn,
2171                                             p_hwfn->hw_info.hw_mode,
2172                                             p_params->b_hw_start,
2173                                             p_params->int_mode,
2174                                             p_params->allow_npar_tx_switch);
2175                         break;
2176                 default:
2177                         DP_NOTICE(p_hwfn,
2178                                   "Unexpected load code [0x%08x]", load_code);
2179                         rc = -EINVAL;
2180                         break;
2181                 }
2182
2183                 if (rc)
2184                         DP_NOTICE(p_hwfn,
2185                                   "init phase failed for loadcode 0x%x (rc %d)\n",
2186                                    load_code, rc);
2187
2188                 /* ACK mfw regardless of success or failure of initialization */
2189                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2190                                      DRV_MSG_CODE_LOAD_DONE,
2191                                      0, &load_code, &param);
2192                 if (rc)
2193                         return rc;
2194                 if (mfw_rc) {
2195                         DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
2196                         return mfw_rc;
2197                 }
2198
2199                 /* Check if there is a DID mismatch between nvm-cfg/efuse */
2200                 if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
2201                         DP_NOTICE(p_hwfn,
2202                                   "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
2203
2204                 /* send DCBX attention request command */
2205                 DP_VERBOSE(p_hwfn,
2206                            QED_MSG_DCB,
2207                            "sending phony dcbx set command to trigger DCBx attention handling\n");
2208                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2209                                      DRV_MSG_CODE_SET_DCBX,
2210                                      1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
2211                                      &load_code, &param);
2212                 if (mfw_rc) {
2213                         DP_NOTICE(p_hwfn,
2214                                   "Failed to send DCBX attention request\n");
2215                         return mfw_rc;
2216                 }
2217
2218                 p_hwfn->hw_init_done = true;
2219         }
2220
2221         if (IS_PF(cdev)) {
2222                 p_hwfn = QED_LEADING_HWFN(cdev);
2223
2224                 /* Get pre-negotiated values for stag, bandwidth etc. */
2225                 DP_VERBOSE(p_hwfn,
2226                            QED_MSG_SPQ,
2227                            "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
2228                 drv_mb_param = 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET;
2229                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2230                                  DRV_MSG_CODE_GET_OEM_UPDATES,
2231                                  drv_mb_param, &resp, &param);
2232                 if (rc)
2233                         DP_NOTICE(p_hwfn,
2234                                   "Failed to send GET_OEM_UPDATES attention request\n");
2235
2236                 drv_mb_param = STORM_FW_VERSION;
2237                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2238                                  DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2239                                  drv_mb_param, &load_code, &param);
2240                 if (rc)
2241                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
2242
2243                 if (!b_default_mtu) {
2244                         rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2245                                                    p_hwfn->hw_info.mtu);
2246                         if (rc)
2247                                 DP_INFO(p_hwfn,
2248                                         "Failed to update default mtu\n");
2249                 }
2250
2251                 rc = qed_mcp_ov_update_driver_state(p_hwfn,
2252                                                     p_hwfn->p_main_ptt,
2253                                                   QED_OV_DRIVER_STATE_DISABLED);
2254                 if (rc)
2255                         DP_INFO(p_hwfn, "Failed to update driver state\n");
2256
2257                 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
2258                                                QED_OV_ESWITCH_NONE);
2259                 if (rc)
2260                         DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
2261         }
2262
2263         return 0;
2264 }
2265
2266 #define QED_HW_STOP_RETRY_LIMIT (10)
2267 static void qed_hw_timers_stop(struct qed_dev *cdev,
2268                                struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2269 {
2270         int i;
2271
2272         /* close timers */
2273         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2274         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2275
2276         for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
2277                 if ((!qed_rd(p_hwfn, p_ptt,
2278                              TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2279                     (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2280                         break;
2281
2282                 /* Dependent on number of connection/tasks, possibly
2283                  * 1ms sleep is required between polls
2284                  */
2285                 usleep_range(1000, 2000);
2286         }
2287
2288         if (i < QED_HW_STOP_RETRY_LIMIT)
2289                 return;
2290
2291         DP_NOTICE(p_hwfn,
2292                   "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
2293                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2294                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2295 }
2296
2297 void qed_hw_timers_stop_all(struct qed_dev *cdev)
2298 {
2299         int j;
2300
2301         for_each_hwfn(cdev, j) {
2302                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
2303                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
2304
2305                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
2306         }
2307 }
2308
2309 int qed_hw_stop(struct qed_dev *cdev)
2310 {
2311         struct qed_hwfn *p_hwfn;
2312         struct qed_ptt *p_ptt;
2313         int rc, rc2 = 0;
2314         int j;
2315
2316         for_each_hwfn(cdev, j) {
2317                 p_hwfn = &cdev->hwfns[j];
2318                 p_ptt = p_hwfn->p_main_ptt;
2319
2320                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
2321
2322                 if (IS_VF(cdev)) {
2323                         qed_vf_pf_int_cleanup(p_hwfn);
2324                         rc = qed_vf_pf_reset(p_hwfn);
2325                         if (rc) {
2326                                 DP_NOTICE(p_hwfn,
2327                                           "qed_vf_pf_reset failed. rc = %d.\n",
2328                                           rc);
2329                                 rc2 = -EINVAL;
2330                         }
2331                         continue;
2332                 }
2333
2334                 /* mark the hw as uninitialized... */
2335                 p_hwfn->hw_init_done = false;
2336
2337                 /* Send unload command to MCP */
2338                 rc = qed_mcp_unload_req(p_hwfn, p_ptt);
2339                 if (rc) {
2340                         DP_NOTICE(p_hwfn,
2341                                   "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2342                                   rc);
2343                         rc2 = -EINVAL;
2344                 }
2345
2346                 qed_slowpath_irq_sync(p_hwfn);
2347
2348                 /* After this point no MFW attentions are expected, e.g. prevent
2349                  * race between pf stop and dcbx pf update.
2350                  */
2351                 rc = qed_sp_pf_stop(p_hwfn);
2352                 if (rc) {
2353                         DP_NOTICE(p_hwfn,
2354                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2355                                   rc);
2356                         rc2 = -EINVAL;
2357                 }
2358
2359                 qed_wr(p_hwfn, p_ptt,
2360                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2361
2362                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2363                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2364                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2365                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2366                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2367
2368                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
2369
2370                 /* Disable Attention Generation */
2371                 qed_int_igu_disable_int(p_hwfn, p_ptt);
2372
2373                 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2374                 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2375
2376                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2377
2378                 /* Need to wait 1ms to guarantee SBs are cleared */
2379                 usleep_range(1000, 2000);
2380
2381                 /* Disable PF in HW blocks */
2382                 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2383                 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2384
2385                 qed_mcp_unload_done(p_hwfn, p_ptt);
2386                 if (rc) {
2387                         DP_NOTICE(p_hwfn,
2388                                   "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2389                                   rc);
2390                         rc2 = -EINVAL;
2391                 }
2392         }
2393
2394         if (IS_PF(cdev)) {
2395                 p_hwfn = QED_LEADING_HWFN(cdev);
2396                 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
2397
2398                 /* Disable DMAE in PXP - in CMT, this should only be done for
2399                  * first hw-function, and only after all transactions have
2400                  * stopped for all active hw-functions.
2401                  */
2402                 rc = qed_change_pci_hwfn(p_hwfn, p_ptt, false);
2403                 if (rc) {
2404                         DP_NOTICE(p_hwfn,
2405                                   "qed_change_pci_hwfn failed. rc = %d.\n", rc);
2406                         rc2 = -EINVAL;
2407                 }
2408         }
2409
2410         return rc2;
2411 }
2412
2413 int qed_hw_stop_fastpath(struct qed_dev *cdev)
2414 {
2415         int j;
2416
2417         for_each_hwfn(cdev, j) {
2418                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
2419                 struct qed_ptt *p_ptt;
2420
2421                 if (IS_VF(cdev)) {
2422                         qed_vf_pf_int_cleanup(p_hwfn);
2423                         continue;
2424                 }
2425                 p_ptt = qed_ptt_acquire(p_hwfn);
2426                 if (!p_ptt)
2427                         return -EAGAIN;
2428
2429                 DP_VERBOSE(p_hwfn,
2430                            NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
2431
2432                 qed_wr(p_hwfn, p_ptt,
2433                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2434
2435                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2436                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2437                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2438                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2439                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2440
2441                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2442
2443                 /* Need to wait 1ms to guarantee SBs are cleared */
2444                 usleep_range(1000, 2000);
2445                 qed_ptt_release(p_hwfn, p_ptt);
2446         }
2447
2448         return 0;
2449 }
2450
2451 int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
2452 {
2453         struct qed_ptt *p_ptt;
2454
2455         if (IS_VF(p_hwfn->cdev))
2456                 return 0;
2457
2458         p_ptt = qed_ptt_acquire(p_hwfn);
2459         if (!p_ptt)
2460                 return -EAGAIN;
2461
2462         if (p_hwfn->p_rdma_info &&
2463             p_hwfn->p_rdma_info->active && p_hwfn->b_rdma_enabled_in_prs)
2464                 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1);
2465
2466         /* Re-open incoming traffic */
2467         qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2468         qed_ptt_release(p_hwfn, p_ptt);
2469
2470         return 0;
2471 }
2472
2473 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2474 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
2475 {
2476         qed_ptt_pool_free(p_hwfn);
2477         kfree(p_hwfn->hw_info.p_igu_info);
2478         p_hwfn->hw_info.p_igu_info = NULL;
2479 }
2480
2481 /* Setup bar access */
2482 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
2483 {
2484         /* clear indirect access */
2485         if (QED_IS_AH(p_hwfn->cdev)) {
2486                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2487                        PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
2488                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2489                        PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
2490                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2491                        PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
2492                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2493                        PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
2494         } else {
2495                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2496                        PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2497                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2498                        PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2499                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2500                        PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2501                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2502                        PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2503         }
2504
2505         /* Clean Previous errors if such exist */
2506         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2507                PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2508
2509         /* enable internal target-read */
2510         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2511                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2512 }
2513
2514 static void get_function_id(struct qed_hwfn *p_hwfn)
2515 {
2516         /* ME Register */
2517         p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
2518                                                   PXP_PF_ME_OPAQUE_ADDR);
2519
2520         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2521
2522         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2523         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2524                                       PXP_CONCRETE_FID_PFID);
2525         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2526                                     PXP_CONCRETE_FID_PORT);
2527
2528         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
2529                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2530                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2531 }
2532
2533 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
2534 {
2535         u32 *feat_num = p_hwfn->hw_info.feat_num;
2536         struct qed_sb_cnt_info sb_cnt;
2537         u32 non_l2_sbs = 0;
2538
2539         memset(&sb_cnt, 0, sizeof(sb_cnt));
2540         qed_int_get_num_sbs(p_hwfn, &sb_cnt);
2541
2542         if (IS_ENABLED(CONFIG_QED_RDMA) &&
2543             QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2544                 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
2545                  * the status blocks equally between L2 / RoCE but with
2546                  * consideration as to how many l2 queues / cnqs we have.
2547                  */
2548                 feat_num[QED_RDMA_CNQ] =
2549                         min_t(u32, sb_cnt.cnt / 2,
2550                               RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
2551
2552                 non_l2_sbs = feat_num[QED_RDMA_CNQ];
2553         }
2554         if (QED_IS_L2_PERSONALITY(p_hwfn)) {
2555                 /* Start by allocating VF queues, then PF's */
2556                 feat_num[QED_VF_L2_QUE] = min_t(u32,
2557                                                 RESC_NUM(p_hwfn, QED_L2_QUEUE),
2558                                                 sb_cnt.iov_cnt);
2559                 feat_num[QED_PF_L2_QUE] = min_t(u32,
2560                                                 sb_cnt.cnt - non_l2_sbs,
2561                                                 RESC_NUM(p_hwfn,
2562                                                          QED_L2_QUEUE) -
2563                                                 FEAT_NUM(p_hwfn,
2564                                                          QED_VF_L2_QUE));
2565         }
2566
2567         if (QED_IS_FCOE_PERSONALITY(p_hwfn))
2568                 feat_num[QED_FCOE_CQ] =  min_t(u32, sb_cnt.cnt,
2569                                                RESC_NUM(p_hwfn,
2570                                                         QED_CMDQS_CQS));
2571
2572         if (QED_IS_ISCSI_PERSONALITY(p_hwfn))
2573                 feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt,
2574                                                RESC_NUM(p_hwfn,
2575                                                         QED_CMDQS_CQS));
2576         DP_VERBOSE(p_hwfn,
2577                    NETIF_MSG_PROBE,
2578                    "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d #SBS=%d\n",
2579                    (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
2580                    (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
2581                    (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
2582                    (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ),
2583                    (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ),
2584                    (int)sb_cnt.cnt);
2585 }
2586
2587 const char *qed_hw_get_resc_name(enum qed_resources res_id)
2588 {
2589         switch (res_id) {
2590         case QED_L2_QUEUE:
2591                 return "L2_QUEUE";
2592         case QED_VPORT:
2593                 return "VPORT";
2594         case QED_RSS_ENG:
2595                 return "RSS_ENG";
2596         case QED_PQ:
2597                 return "PQ";
2598         case QED_RL:
2599                 return "RL";
2600         case QED_MAC:
2601                 return "MAC";
2602         case QED_VLAN:
2603                 return "VLAN";
2604         case QED_RDMA_CNQ_RAM:
2605                 return "RDMA_CNQ_RAM";
2606         case QED_ILT:
2607                 return "ILT";
2608         case QED_LL2_QUEUE:
2609                 return "LL2_QUEUE";
2610         case QED_CMDQS_CQS:
2611                 return "CMDQS_CQS";
2612         case QED_RDMA_STATS_QUEUE:
2613                 return "RDMA_STATS_QUEUE";
2614         case QED_BDQ:
2615                 return "BDQ";
2616         case QED_SB:
2617                 return "SB";
2618         default:
2619                 return "UNKNOWN_RESOURCE";
2620         }
2621 }
2622
2623 static int
2624 __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
2625                             struct qed_ptt *p_ptt,
2626                             enum qed_resources res_id,
2627                             u32 resc_max_val, u32 *p_mcp_resp)
2628 {
2629         int rc;
2630
2631         rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2632                                       resc_max_val, p_mcp_resp);
2633         if (rc) {
2634                 DP_NOTICE(p_hwfn,
2635                           "MFW response failure for a max value setting of resource %d [%s]\n",
2636                           res_id, qed_hw_get_resc_name(res_id));
2637                 return rc;
2638         }
2639
2640         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2641                 DP_INFO(p_hwfn,
2642                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2643                         res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp);
2644
2645         return 0;
2646 }
2647
2648 static int
2649 qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2650 {
2651         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2652         u32 resc_max_val, mcp_resp;
2653         u8 res_id;
2654         int rc;
2655
2656         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2657                 switch (res_id) {
2658                 case QED_LL2_QUEUE:
2659                         resc_max_val = MAX_NUM_LL2_RX_QUEUES;
2660                         break;
2661                 case QED_RDMA_CNQ_RAM:
2662                         /* No need for a case for QED_CMDQS_CQS since
2663                          * CNQ/CMDQS are the same resource.
2664                          */
2665                         resc_max_val = NUM_OF_GLOBAL_QUEUES;
2666                         break;
2667                 case QED_RDMA_STATS_QUEUE:
2668                         resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
2669                             : RDMA_NUM_STATISTIC_COUNTERS_BB;
2670                         break;
2671                 case QED_BDQ:
2672                         resc_max_val = BDQ_NUM_RESOURCES;
2673                         break;
2674                 default:
2675                         continue;
2676                 }
2677
2678                 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2679                                                  resc_max_val, &mcp_resp);
2680                 if (rc)
2681                         return rc;
2682
2683                 /* There's no point to continue to the next resource if the
2684                  * command is not supported by the MFW.
2685                  * We do continue if the command is supported but the resource
2686                  * is unknown to the MFW. Such a resource will be later
2687                  * configured with the default allocation values.
2688                  */
2689                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2690                         return -EINVAL;
2691         }
2692
2693         return 0;
2694 }
2695
2696 static
2697 int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
2698                          enum qed_resources res_id,
2699                          u32 *p_resc_num, u32 *p_resc_start)
2700 {
2701         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2702         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2703
2704         switch (res_id) {
2705         case QED_L2_QUEUE:
2706                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2707                                MAX_NUM_L2_QUEUES_BB) / num_funcs;
2708                 break;
2709         case QED_VPORT:
2710                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2711                                MAX_NUM_VPORTS_BB) / num_funcs;
2712                 break;
2713         case QED_RSS_ENG:
2714                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2715                                ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2716                 break;
2717         case QED_PQ:
2718                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2719                                MAX_QM_TX_QUEUES_BB) / num_funcs;
2720                 *p_resc_num &= ~0x7;    /* The granularity of the PQs is 8 */
2721                 break;
2722         case QED_RL:
2723                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2724                 break;
2725         case QED_MAC:
2726         case QED_VLAN:
2727                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2728                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2729                 break;
2730         case QED_ILT:
2731                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2732                                PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2733                 break;
2734         case QED_LL2_QUEUE:
2735                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2736                 break;
2737         case QED_RDMA_CNQ_RAM:
2738         case QED_CMDQS_CQS:
2739                 /* CNQ/CMDQS are the same resource */
2740                 *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs;
2741                 break;
2742         case QED_RDMA_STATS_QUEUE:
2743                 *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 :
2744                                RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs;
2745                 break;
2746         case QED_BDQ:
2747                 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
2748                     p_hwfn->hw_info.personality != QED_PCI_FCOE)
2749                         *p_resc_num = 0;
2750                 else
2751                         *p_resc_num = 1;
2752                 break;
2753         case QED_SB:
2754                 /* Since we want its value to reflect whether MFW supports
2755                  * the new scheme, have a default of 0.
2756                  */
2757                 *p_resc_num = 0;
2758                 break;
2759         default:
2760                 return -EINVAL;
2761         }
2762
2763         switch (res_id) {
2764         case QED_BDQ:
2765                 if (!*p_resc_num)
2766                         *p_resc_start = 0;
2767                 else if (p_hwfn->cdev->num_ports_in_engine == 4)
2768                         *p_resc_start = p_hwfn->port_id;
2769                 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
2770                         *p_resc_start = p_hwfn->port_id;
2771                 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
2772                         *p_resc_start = p_hwfn->port_id + 2;
2773                 break;
2774         default:
2775                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2776                 break;
2777         }
2778
2779         return 0;
2780 }
2781
2782 static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
2783                                   enum qed_resources res_id)
2784 {
2785         u32 dflt_resc_num = 0, dflt_resc_start = 0;
2786         u32 mcp_resp, *p_resc_num, *p_resc_start;
2787         int rc;
2788
2789         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2790         p_resc_start = &RESC_START(p_hwfn, res_id);
2791
2792         rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2793                                   &dflt_resc_start);
2794         if (rc) {
2795                 DP_ERR(p_hwfn,
2796                        "Failed to get default amount for resource %d [%s]\n",
2797                        res_id, qed_hw_get_resc_name(res_id));
2798                 return rc;
2799         }
2800
2801         rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2802                                    &mcp_resp, p_resc_num, p_resc_start);
2803         if (rc) {
2804                 DP_NOTICE(p_hwfn,
2805                           "MFW response failure for an allocation request for resource %d [%s]\n",
2806                           res_id, qed_hw_get_resc_name(res_id));
2807                 return rc;
2808         }
2809
2810         /* Default driver values are applied in the following cases:
2811          * - The resource allocation MB command is not supported by the MFW
2812          * - There is an internal error in the MFW while processing the request
2813          * - The resource ID is unknown to the MFW
2814          */
2815         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2816                 DP_INFO(p_hwfn,
2817                         "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
2818                         res_id,
2819                         qed_hw_get_resc_name(res_id),
2820                         mcp_resp, dflt_resc_num, dflt_resc_start);
2821                 *p_resc_num = dflt_resc_num;
2822                 *p_resc_start = dflt_resc_start;
2823                 goto out;
2824         }
2825
2826 out:
2827         /* PQs have to divide by 8 [that's the HW granularity].
2828          * Reduce number so it would fit.
2829          */
2830         if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
2831                 DP_INFO(p_hwfn,
2832                         "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
2833                         *p_resc_num,
2834                         (*p_resc_num) & ~0x7,
2835                         *p_resc_start, (*p_resc_start) & ~0x7);
2836                 *p_resc_num &= ~0x7;
2837                 *p_resc_start &= ~0x7;
2838         }
2839
2840         return 0;
2841 }
2842
2843 static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn)
2844 {
2845         int rc;
2846         u8 res_id;
2847
2848         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2849                 rc = __qed_hw_set_resc_info(p_hwfn, res_id);
2850                 if (rc)
2851                         return rc;
2852         }
2853
2854         return 0;
2855 }
2856
2857 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2858 {
2859         struct qed_resc_unlock_params resc_unlock_params;
2860         struct qed_resc_lock_params resc_lock_params;
2861         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2862         u8 res_id;
2863         int rc;
2864
2865         /* Setting the max values of the soft resources and the following
2866          * resources allocation queries should be atomic. Since several PFs can
2867          * run in parallel - a resource lock is needed.
2868          * If either the resource lock or resource set value commands are not
2869          * supported - skip the the max values setting, release the lock if
2870          * needed, and proceed to the queries. Other failures, including a
2871          * failure to acquire the lock, will cause this function to fail.
2872          */
2873         qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
2874                                        QED_RESC_LOCK_RESC_ALLOC, false);
2875
2876         rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
2877         if (rc && rc != -EINVAL) {
2878                 return rc;
2879         } else if (rc == -EINVAL) {
2880                 DP_INFO(p_hwfn,
2881                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2882         } else if (!rc && !resc_lock_params.b_granted) {
2883                 DP_NOTICE(p_hwfn,
2884                           "Failed to acquire the resource lock for the resource allocation commands\n");
2885                 return -EBUSY;
2886         } else {
2887                 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt);
2888                 if (rc && rc != -EINVAL) {
2889                         DP_NOTICE(p_hwfn,
2890                                   "Failed to set the max values of the soft resources\n");
2891                         goto unlock_and_exit;
2892                 } else if (rc == -EINVAL) {
2893                         DP_INFO(p_hwfn,
2894                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2895                         rc = qed_mcp_resc_unlock(p_hwfn, p_ptt,
2896                                                  &resc_unlock_params);
2897                         if (rc)
2898                                 DP_INFO(p_hwfn,
2899                                         "Failed to release the resource lock for the resource allocation commands\n");
2900                 }
2901         }
2902
2903         rc = qed_hw_set_resc_info(p_hwfn);
2904         if (rc)
2905                 goto unlock_and_exit;
2906
2907         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2908                 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2909                 if (rc)
2910                         DP_INFO(p_hwfn,
2911                                 "Failed to release the resource lock for the resource allocation commands\n");
2912         }
2913
2914         /* Sanity for ILT */
2915         if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2916             (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2917                 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
2918                           RESC_START(p_hwfn, QED_ILT),
2919                           RESC_END(p_hwfn, QED_ILT) - 1);
2920                 return -EINVAL;
2921         }
2922
2923         /* This will also learn the number of SBs from MFW */
2924         if (qed_int_igu_reset_cam(p_hwfn, p_ptt))
2925                 return -EINVAL;
2926
2927         qed_hw_set_feat(p_hwfn);
2928
2929         for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
2930                 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
2931                            qed_hw_get_resc_name(res_id),
2932                            RESC_NUM(p_hwfn, res_id),
2933                            RESC_START(p_hwfn, res_id));
2934
2935         return 0;
2936
2937 unlock_and_exit:
2938         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
2939                 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2940         return rc;
2941 }
2942
2943 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2944 {
2945         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2946         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
2947         struct qed_mcp_link_capabilities *p_caps;
2948         struct qed_mcp_link_params *link;
2949
2950         /* Read global nvm_cfg address */
2951         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2952
2953         /* Verify MCP has initialized it */
2954         if (!nvm_cfg_addr) {
2955                 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
2956                 return -EINVAL;
2957         }
2958
2959         /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
2960         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2961
2962         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2963                offsetof(struct nvm_cfg1, glob) +
2964                offsetof(struct nvm_cfg1_glob, core_cfg);
2965
2966         core_cfg = qed_rd(p_hwfn, p_ptt, addr);
2967
2968         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2969                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2970         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2971                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
2972                 break;
2973         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2974                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
2975                 break;
2976         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2977                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
2978                 break;
2979         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2980                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
2981                 break;
2982         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2983                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
2984                 break;
2985         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2986                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
2987                 break;
2988         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2989                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
2990                 break;
2991         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2992                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
2993                 break;
2994         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2995                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
2996                 break;
2997         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2998                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
2999                 break;
3000         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
3001                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
3002                 break;
3003         default:
3004                 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
3005                 break;
3006         }
3007
3008         /* Read default link configuration */
3009         link = &p_hwfn->mcp_info->link_input;
3010         p_caps = &p_hwfn->mcp_info->link_capabilities;
3011         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3012                         offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3013         link_temp = qed_rd(p_hwfn, p_ptt,
3014                            port_cfg_addr +
3015                            offsetof(struct nvm_cfg1_port, speed_cap_mask));
3016         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
3017         link->speed.advertised_speeds = link_temp;
3018
3019         link_temp = link->speed.advertised_speeds;
3020         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
3021
3022         link_temp = qed_rd(p_hwfn, p_ptt,
3023                            port_cfg_addr +
3024                            offsetof(struct nvm_cfg1_port, link_settings));
3025         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
3026                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
3027         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
3028                 link->speed.autoneg = true;
3029                 break;
3030         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
3031                 link->speed.forced_speed = 1000;
3032                 break;
3033         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
3034                 link->speed.forced_speed = 10000;
3035                 break;
3036         case NVM_CFG1_PORT_DRV_LINK_SPEED_20G:
3037                 link->speed.forced_speed = 20000;
3038                 break;
3039         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
3040                 link->speed.forced_speed = 25000;
3041                 break;
3042         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
3043                 link->speed.forced_speed = 40000;
3044                 break;
3045         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
3046                 link->speed.forced_speed = 50000;
3047                 break;
3048         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
3049                 link->speed.forced_speed = 100000;
3050                 break;
3051         default:
3052                 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
3053         }
3054
3055         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
3056                 link->speed.autoneg;
3057
3058         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
3059         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
3060         link->pause.autoneg = !!(link_temp &
3061                                  NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
3062         link->pause.forced_rx = !!(link_temp &
3063                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
3064         link->pause.forced_tx = !!(link_temp &
3065                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
3066         link->loopback_mode = 0;
3067
3068         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
3069                 link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr +
3070                                    offsetof(struct nvm_cfg1_port, ext_phy));
3071                 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
3072                 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
3073                 p_caps->default_eee = QED_MCP_EEE_ENABLED;
3074                 link->eee.enable = true;
3075                 switch (link_temp) {
3076                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
3077                         p_caps->default_eee = QED_MCP_EEE_DISABLED;
3078                         link->eee.enable = false;
3079                         break;
3080                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
3081                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
3082                         break;
3083                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
3084                         p_caps->eee_lpi_timer =
3085                             EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
3086                         break;
3087                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
3088                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
3089                         break;
3090                 }
3091
3092                 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
3093                 link->eee.tx_lpi_enable = link->eee.enable;
3094                 link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV;
3095         } else {
3096                 p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED;
3097         }
3098
3099         DP_VERBOSE(p_hwfn,
3100                    NETIF_MSG_LINK,
3101                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x EEE: %02x [%08x usec]\n",
3102                    link->speed.forced_speed,
3103                    link->speed.advertised_speeds,
3104                    link->speed.autoneg,
3105                    link->pause.autoneg,
3106                    p_caps->default_eee, p_caps->eee_lpi_timer);
3107
3108         if (IS_LEAD_HWFN(p_hwfn)) {
3109                 struct qed_dev *cdev = p_hwfn->cdev;
3110
3111                 /* Read Multi-function information from shmem */
3112                 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3113                        offsetof(struct nvm_cfg1, glob) +
3114                        offsetof(struct nvm_cfg1_glob, generic_cont0);
3115
3116                 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
3117
3118                 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3119                           NVM_CFG1_GLOB_MF_MODE_OFFSET;
3120
3121                 switch (mf_mode) {
3122                 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3123                         cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS);
3124                         break;
3125                 case NVM_CFG1_GLOB_MF_MODE_UFP:
3126                         cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
3127                                         BIT(QED_MF_LLH_PROTO_CLSS) |
3128                                         BIT(QED_MF_UFP_SPECIFIC) |
3129                                         BIT(QED_MF_8021Q_TAGGING);
3130                         break;
3131                 case NVM_CFG1_GLOB_MF_MODE_BD:
3132                         cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
3133                                         BIT(QED_MF_LLH_PROTO_CLSS) |
3134                                         BIT(QED_MF_8021AD_TAGGING);
3135                         break;
3136                 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3137                         cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
3138                                         BIT(QED_MF_LLH_PROTO_CLSS) |
3139                                         BIT(QED_MF_LL2_NON_UNICAST) |
3140                                         BIT(QED_MF_INTER_PF_SWITCH);
3141                         break;
3142                 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3143                         cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
3144                                         BIT(QED_MF_LLH_PROTO_CLSS) |
3145                                         BIT(QED_MF_LL2_NON_UNICAST);
3146                         if (QED_IS_BB(p_hwfn->cdev))
3147                                 cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF);
3148                         break;
3149                 }
3150
3151                 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
3152                         cdev->mf_bits);
3153         }
3154
3155         DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
3156                 p_hwfn->cdev->mf_bits);
3157
3158         /* Read device capabilities information from shmem */
3159         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3160                 offsetof(struct nvm_cfg1, glob) +
3161                 offsetof(struct nvm_cfg1_glob, device_capabilities);
3162
3163         device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
3164         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3165                 __set_bit(QED_DEV_CAP_ETH,
3166                           &p_hwfn->hw_info.device_capabilities);
3167         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3168                 __set_bit(QED_DEV_CAP_FCOE,
3169                           &p_hwfn->hw_info.device_capabilities);
3170         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3171                 __set_bit(QED_DEV_CAP_ISCSI,
3172                           &p_hwfn->hw_info.device_capabilities);
3173         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3174                 __set_bit(QED_DEV_CAP_ROCE,
3175                           &p_hwfn->hw_info.device_capabilities);
3176
3177         return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3178 }
3179
3180 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3181 {
3182         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3183         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3184         struct qed_dev *cdev = p_hwfn->cdev;
3185
3186         num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3187
3188         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3189          * in the other bits are selected.
3190          * Bits 1-15 are for functions 1-15, respectively, and their value is
3191          * '0' only for enabled functions (function 0 always exists and
3192          * enabled).
3193          * In case of CMT, only the "even" functions are enabled, and thus the
3194          * number of functions for both hwfns is learnt from the same bits.
3195          */
3196         reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
3197
3198         if (reg_function_hide & 0x1) {
3199                 if (QED_IS_BB(cdev)) {
3200                         if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
3201                                 num_funcs = 0;
3202                                 eng_mask = 0xaaaa;
3203                         } else {
3204                                 num_funcs = 1;
3205                                 eng_mask = 0x5554;
3206                         }
3207                 } else {
3208                         num_funcs = 1;
3209                         eng_mask = 0xfffe;
3210                 }
3211
3212                 /* Get the number of the enabled functions on the engine */
3213                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3214                 while (tmp) {
3215                         if (tmp & 0x1)
3216                                 num_funcs++;
3217                         tmp >>= 0x1;
3218                 }
3219
3220                 /* Get the PF index within the enabled functions */
3221                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3222                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3223                 while (tmp) {
3224                         if (tmp & 0x1)
3225                                 enabled_func_idx--;
3226                         tmp >>= 0x1;
3227                 }
3228         }
3229
3230         p_hwfn->num_funcs_on_engine = num_funcs;
3231         p_hwfn->enabled_func_idx = enabled_func_idx;
3232
3233         DP_VERBOSE(p_hwfn,
3234                    NETIF_MSG_PROBE,
3235                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3236                    p_hwfn->rel_pf_id,
3237                    p_hwfn->abs_pf_id,
3238                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3239 }
3240
3241 static void qed_hw_info_port_num_bb(struct qed_hwfn *p_hwfn,
3242                                     struct qed_ptt *p_ptt)
3243 {
3244         u32 port_mode;
3245
3246         port_mode = qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3247
3248         if (port_mode < 3) {
3249                 p_hwfn->cdev->num_ports_in_engine = 1;
3250         } else if (port_mode <= 5) {
3251                 p_hwfn->cdev->num_ports_in_engine = 2;
3252         } else {
3253                 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
3254                           p_hwfn->cdev->num_ports_in_engine);
3255
3256                 /* Default num_ports_in_engine to something */
3257                 p_hwfn->cdev->num_ports_in_engine = 1;
3258         }
3259 }
3260
3261 static void qed_hw_info_port_num_ah(struct qed_hwfn *p_hwfn,
3262                                     struct qed_ptt *p_ptt)
3263 {
3264         u32 port;
3265         int i;
3266
3267         p_hwfn->cdev->num_ports_in_engine = 0;
3268
3269         for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3270                 port = qed_rd(p_hwfn, p_ptt,
3271                               CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
3272                 if (port & 1)
3273                         p_hwfn->cdev->num_ports_in_engine++;
3274         }
3275
3276         if (!p_hwfn->cdev->num_ports_in_engine) {
3277                 DP_NOTICE(p_hwfn, "All NIG ports are inactive\n");
3278
3279                 /* Default num_ports_in_engine to something */
3280                 p_hwfn->cdev->num_ports_in_engine = 1;
3281         }
3282 }
3283
3284 static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3285 {
3286         if (QED_IS_BB(p_hwfn->cdev))
3287                 qed_hw_info_port_num_bb(p_hwfn, p_ptt);
3288         else
3289                 qed_hw_info_port_num_ah(p_hwfn, p_ptt);
3290 }
3291
3292 static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3293 {
3294         struct qed_mcp_link_capabilities *p_caps;
3295         u32 eee_status;
3296
3297         p_caps = &p_hwfn->mcp_info->link_capabilities;
3298         if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED)
3299                 return;
3300
3301         p_caps->eee_speed_caps = 0;
3302         eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
3303                             offsetof(struct public_port, eee_status));
3304         eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
3305                         EEE_SUPPORTED_SPEED_OFFSET;
3306
3307         if (eee_status & EEE_1G_SUPPORTED)
3308                 p_caps->eee_speed_caps |= QED_EEE_1G_ADV;
3309         if (eee_status & EEE_10G_ADV)
3310                 p_caps->eee_speed_caps |= QED_EEE_10G_ADV;
3311 }
3312
3313 static int
3314 qed_get_hw_info(struct qed_hwfn *p_hwfn,
3315                 struct qed_ptt *p_ptt,
3316                 enum qed_pci_personality personality)
3317 {
3318         int rc;
3319
3320         /* Since all information is common, only first hwfns should do this */
3321         if (IS_LEAD_HWFN(p_hwfn)) {
3322                 rc = qed_iov_hw_info(p_hwfn);
3323                 if (rc)
3324                         return rc;
3325         }
3326
3327         qed_hw_info_port_num(p_hwfn, p_ptt);
3328
3329         qed_mcp_get_capabilities(p_hwfn, p_ptt);
3330
3331         qed_hw_get_nvm_info(p_hwfn, p_ptt);
3332
3333         rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
3334         if (rc)
3335                 return rc;
3336
3337         if (qed_mcp_is_init(p_hwfn))
3338                 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
3339                                 p_hwfn->mcp_info->func_info.mac);
3340         else
3341                 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
3342
3343         if (qed_mcp_is_init(p_hwfn)) {
3344                 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
3345                         p_hwfn->hw_info.ovlan =
3346                                 p_hwfn->mcp_info->func_info.ovlan;
3347
3348                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
3349
3350                 qed_get_eee_caps(p_hwfn, p_ptt);
3351
3352                 qed_mcp_read_ufp_config(p_hwfn, p_ptt);
3353         }
3354
3355         if (qed_mcp_is_init(p_hwfn)) {
3356                 enum qed_pci_personality protocol;
3357
3358                 protocol = p_hwfn->mcp_info->func_info.protocol;
3359                 p_hwfn->hw_info.personality = protocol;
3360         }
3361
3362         if (QED_IS_ROCE_PERSONALITY(p_hwfn))
3363                 p_hwfn->hw_info.multi_tc_roce_en = 1;
3364
3365         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3366         p_hwfn->hw_info.num_active_tc = 1;
3367
3368         qed_get_num_funcs(p_hwfn, p_ptt);
3369
3370         if (qed_mcp_is_init(p_hwfn))
3371                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3372
3373         return qed_hw_get_resc(p_hwfn, p_ptt);
3374 }
3375
3376 static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3377 {
3378         struct qed_dev *cdev = p_hwfn->cdev;
3379         u16 device_id_mask;
3380         u32 tmp;
3381
3382         /* Read Vendor Id / Device Id */
3383         pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
3384         pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
3385
3386         /* Determine type */
3387         device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
3388         switch (device_id_mask) {
3389         case QED_DEV_ID_MASK_BB:
3390                 cdev->type = QED_DEV_TYPE_BB;
3391                 break;
3392         case QED_DEV_ID_MASK_AH:
3393                 cdev->type = QED_DEV_TYPE_AH;
3394                 break;
3395         default:
3396                 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
3397                 return -EBUSY;
3398         }
3399
3400         cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
3401         cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
3402
3403         MASK_FIELD(CHIP_REV, cdev->chip_rev);
3404
3405         /* Learn number of HW-functions */
3406         tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
3407
3408         if (tmp & (1 << p_hwfn->rel_pf_id)) {
3409                 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
3410                 cdev->num_hwfns = 2;
3411         } else {
3412                 cdev->num_hwfns = 1;
3413         }
3414
3415         cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
3416                                     MISCS_REG_CHIP_TEST_REG) >> 4;
3417         MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
3418         cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
3419         MASK_FIELD(CHIP_METAL, cdev->chip_metal);
3420
3421         DP_INFO(cdev->hwfns,
3422                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
3423                 QED_IS_BB(cdev) ? "BB" : "AH",
3424                 'A' + cdev->chip_rev,
3425                 (int)cdev->chip_metal,
3426                 cdev->chip_num, cdev->chip_rev,
3427                 cdev->chip_bond_id, cdev->chip_metal);
3428
3429         return 0;
3430 }
3431
3432 static void qed_nvm_info_free(struct qed_hwfn *p_hwfn)
3433 {
3434         kfree(p_hwfn->nvm_info.image_att);
3435         p_hwfn->nvm_info.image_att = NULL;
3436 }
3437
3438 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
3439                                  void __iomem *p_regview,
3440                                  void __iomem *p_doorbells,
3441                                  enum qed_pci_personality personality)
3442 {
3443         int rc = 0;
3444
3445         /* Split PCI bars evenly between hwfns */
3446         p_hwfn->regview = p_regview;
3447         p_hwfn->doorbells = p_doorbells;
3448
3449         if (IS_VF(p_hwfn->cdev))
3450                 return qed_vf_hw_prepare(p_hwfn);
3451
3452         /* Validate that chip access is feasible */
3453         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3454                 DP_ERR(p_hwfn,
3455                        "Reading the ME register returns all Fs; Preventing further chip access\n");
3456                 return -EINVAL;
3457         }
3458
3459         get_function_id(p_hwfn);
3460
3461         /* Allocate PTT pool */
3462         rc = qed_ptt_pool_alloc(p_hwfn);
3463         if (rc)
3464                 goto err0;
3465
3466         /* Allocate the main PTT */
3467         p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3468
3469         /* First hwfn learns basic information, e.g., number of hwfns */
3470         if (!p_hwfn->my_id) {
3471                 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
3472                 if (rc)
3473                         goto err1;
3474         }
3475
3476         qed_hw_hwfn_prepare(p_hwfn);
3477
3478         /* Initialize MCP structure */
3479         rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3480         if (rc) {
3481                 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
3482                 goto err1;
3483         }
3484
3485         /* Read the device configuration information from the HW and SHMEM */
3486         rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
3487         if (rc) {
3488                 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
3489                 goto err2;
3490         }
3491
3492         /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
3493          * is called as it sets the ports number in an engine.
3494          */
3495         if (IS_LEAD_HWFN(p_hwfn)) {
3496                 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3497                 if (rc)
3498                         DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
3499         }
3500
3501         /* NVRAM info initialization and population */
3502         if (IS_LEAD_HWFN(p_hwfn)) {
3503                 rc = qed_mcp_nvm_info_populate(p_hwfn);
3504                 if (rc) {
3505                         DP_NOTICE(p_hwfn,
3506                                   "Failed to populate nvm info shadow\n");
3507                         goto err2;
3508                 }
3509         }
3510
3511         /* Allocate the init RT array and initialize the init-ops engine */
3512         rc = qed_init_alloc(p_hwfn);
3513         if (rc)
3514                 goto err3;
3515
3516         return rc;
3517 err3:
3518         if (IS_LEAD_HWFN(p_hwfn))
3519                 qed_nvm_info_free(p_hwfn);
3520 err2:
3521         if (IS_LEAD_HWFN(p_hwfn))
3522                 qed_iov_free_hw_info(p_hwfn->cdev);
3523         qed_mcp_free(p_hwfn);
3524 err1:
3525         qed_hw_hwfn_free(p_hwfn);
3526 err0:
3527         return rc;
3528 }
3529
3530 int qed_hw_prepare(struct qed_dev *cdev,
3531                    int personality)
3532 {
3533         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3534         int rc;
3535
3536         /* Store the precompiled init data ptrs */
3537         if (IS_PF(cdev))
3538                 qed_init_iro_array(cdev);
3539
3540         /* Initialize the first hwfn - will learn number of hwfns */
3541         rc = qed_hw_prepare_single(p_hwfn,
3542                                    cdev->regview,
3543                                    cdev->doorbells, personality);
3544         if (rc)
3545                 return rc;
3546
3547         personality = p_hwfn->hw_info.personality;
3548
3549         /* Initialize the rest of the hwfns */
3550         if (cdev->num_hwfns > 1) {
3551                 void __iomem *p_regview, *p_doorbell;
3552                 u8 __iomem *addr;
3553
3554                 /* adjust bar offset for second engine */
3555                 addr = cdev->regview +
3556                        qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
3557                                        BAR_ID_0) / 2;
3558                 p_regview = addr;
3559
3560                 addr = cdev->doorbells +
3561                        qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
3562                                        BAR_ID_1) / 2;
3563                 p_doorbell = addr;
3564
3565                 /* prepare second hw function */
3566                 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
3567                                            p_doorbell, personality);
3568
3569                 /* in case of error, need to free the previously
3570                  * initiliazed hwfn 0.
3571                  */
3572                 if (rc) {
3573                         if (IS_PF(cdev)) {
3574                                 qed_init_free(p_hwfn);
3575                                 qed_nvm_info_free(p_hwfn);
3576                                 qed_mcp_free(p_hwfn);
3577                                 qed_hw_hwfn_free(p_hwfn);
3578                         }
3579                 }
3580         }
3581
3582         return rc;
3583 }
3584
3585 void qed_hw_remove(struct qed_dev *cdev)
3586 {
3587         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3588         int i;
3589
3590         if (IS_PF(cdev))
3591                 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3592                                                QED_OV_DRIVER_STATE_NOT_LOADED);
3593
3594         for_each_hwfn(cdev, i) {
3595                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3596
3597                 if (IS_VF(cdev)) {
3598                         qed_vf_pf_release(p_hwfn);
3599                         continue;
3600                 }
3601
3602                 qed_init_free(p_hwfn);
3603                 qed_hw_hwfn_free(p_hwfn);
3604                 qed_mcp_free(p_hwfn);
3605         }
3606
3607         qed_iov_free_hw_info(cdev);
3608
3609         qed_nvm_info_free(p_hwfn);
3610 }
3611
3612 static void qed_chain_free_next_ptr(struct qed_dev *cdev,
3613                                     struct qed_chain *p_chain)
3614 {
3615         void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
3616         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3617         struct qed_chain_next *p_next;
3618         u32 size, i;
3619
3620         if (!p_virt)
3621                 return;
3622
3623         size = p_chain->elem_size * p_chain->usable_per_page;
3624
3625         for (i = 0; i < p_chain->page_cnt; i++) {
3626                 if (!p_virt)
3627                         break;
3628
3629                 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
3630                 p_virt_next = p_next->next_virt;
3631                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3632
3633                 dma_free_coherent(&cdev->pdev->dev,
3634                                   QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
3635
3636                 p_virt = p_virt_next;
3637                 p_phys = p_phys_next;
3638         }
3639 }
3640
3641 static void qed_chain_free_single(struct qed_dev *cdev,
3642                                   struct qed_chain *p_chain)
3643 {
3644         if (!p_chain->p_virt_addr)
3645                 return;
3646
3647         dma_free_coherent(&cdev->pdev->dev,
3648                           QED_CHAIN_PAGE_SIZE,
3649                           p_chain->p_virt_addr, p_chain->p_phys_addr);
3650 }
3651
3652 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
3653 {
3654         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3655         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3656         u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table;
3657
3658         if (!pp_virt_addr_tbl)
3659                 return;
3660
3661         if (!p_pbl_virt)
3662                 goto out;
3663
3664         for (i = 0; i < page_cnt; i++) {
3665                 if (!pp_virt_addr_tbl[i])
3666                         break;
3667
3668                 dma_free_coherent(&cdev->pdev->dev,
3669                                   QED_CHAIN_PAGE_SIZE,
3670                                   pp_virt_addr_tbl[i],
3671                                   *(dma_addr_t *)p_pbl_virt);
3672
3673                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3674         }
3675
3676         pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3677
3678         if (!p_chain->b_external_pbl)
3679                 dma_free_coherent(&cdev->pdev->dev,
3680                                   pbl_size,
3681                                   p_chain->pbl_sp.p_virt_table,
3682                                   p_chain->pbl_sp.p_phys_table);
3683 out:
3684         vfree(p_chain->pbl.pp_virt_addr_tbl);
3685         p_chain->pbl.pp_virt_addr_tbl = NULL;
3686 }
3687
3688 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
3689 {
3690         switch (p_chain->mode) {
3691         case QED_CHAIN_MODE_NEXT_PTR:
3692                 qed_chain_free_next_ptr(cdev, p_chain);
3693                 break;
3694         case QED_CHAIN_MODE_SINGLE:
3695                 qed_chain_free_single(cdev, p_chain);
3696                 break;
3697         case QED_CHAIN_MODE_PBL:
3698                 qed_chain_free_pbl(cdev, p_chain);
3699                 break;
3700         }
3701 }
3702
3703 static int
3704 qed_chain_alloc_sanity_check(struct qed_dev *cdev,
3705                              enum qed_chain_cnt_type cnt_type,
3706                              size_t elem_size, u32 page_cnt)
3707 {
3708         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3709
3710         /* The actual chain size can be larger than the maximal possible value
3711          * after rounding up the requested elements number to pages, and after
3712          * taking into acount the unusuable elements (next-ptr elements).
3713          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3714          * size/capacity fields are of a u32 type.
3715          */
3716         if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
3717              chain_size > ((u32)U16_MAX + 1)) ||
3718             (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
3719                 DP_NOTICE(cdev,
3720                           "The actual chain size (0x%llx) is larger than the maximal possible value\n",
3721                           chain_size);
3722                 return -EINVAL;
3723         }
3724
3725         return 0;
3726 }
3727
3728 static int
3729 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
3730 {
3731         void *p_virt = NULL, *p_virt_prev = NULL;
3732         dma_addr_t p_phys = 0;
3733         u32 i;
3734
3735         for (i = 0; i < p_chain->page_cnt; i++) {
3736                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3737                                             QED_CHAIN_PAGE_SIZE,
3738                                             &p_phys, GFP_KERNEL);
3739                 if (!p_virt)
3740                         return -ENOMEM;
3741
3742                 if (i == 0) {
3743                         qed_chain_init_mem(p_chain, p_virt, p_phys);
3744                         qed_chain_reset(p_chain);
3745                 } else {
3746                         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3747                                                      p_virt, p_phys);
3748                 }
3749
3750                 p_virt_prev = p_virt;
3751         }
3752         /* Last page's next element should point to the beginning of the
3753          * chain.
3754          */
3755         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3756                                      p_chain->p_virt_addr,
3757                                      p_chain->p_phys_addr);
3758
3759         return 0;
3760 }
3761
3762 static int
3763 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
3764 {
3765         dma_addr_t p_phys = 0;
3766         void *p_virt = NULL;
3767
3768         p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3769                                     QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
3770         if (!p_virt)
3771                 return -ENOMEM;
3772
3773         qed_chain_init_mem(p_chain, p_virt, p_phys);
3774         qed_chain_reset(p_chain);
3775
3776         return 0;
3777 }
3778
3779 static int
3780 qed_chain_alloc_pbl(struct qed_dev *cdev,
3781                     struct qed_chain *p_chain,
3782                     struct qed_chain_ext_pbl *ext_pbl)
3783 {
3784         u32 page_cnt = p_chain->page_cnt, size, i;
3785         dma_addr_t p_phys = 0, p_pbl_phys = 0;
3786         void **pp_virt_addr_tbl = NULL;
3787         u8 *p_pbl_virt = NULL;
3788         void *p_virt = NULL;
3789
3790         size = page_cnt * sizeof(*pp_virt_addr_tbl);
3791         pp_virt_addr_tbl = vzalloc(size);
3792         if (!pp_virt_addr_tbl)
3793                 return -ENOMEM;
3794
3795         /* The allocation of the PBL table is done with its full size, since it
3796          * is expected to be successive.
3797          * qed_chain_init_pbl_mem() is called even in a case of an allocation
3798          * failure, since pp_virt_addr_tbl was previously allocated, and it
3799          * should be saved to allow its freeing during the error flow.
3800          */
3801         size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3802
3803         if (!ext_pbl) {
3804                 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
3805                                                 size, &p_pbl_phys, GFP_KERNEL);
3806         } else {
3807                 p_pbl_virt = ext_pbl->p_pbl_virt;
3808                 p_pbl_phys = ext_pbl->p_pbl_phys;
3809                 p_chain->b_external_pbl = true;
3810         }
3811
3812         qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3813                                pp_virt_addr_tbl);
3814         if (!p_pbl_virt)
3815                 return -ENOMEM;
3816
3817         for (i = 0; i < page_cnt; i++) {
3818                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3819                                             QED_CHAIN_PAGE_SIZE,
3820                                             &p_phys, GFP_KERNEL);
3821                 if (!p_virt)
3822                         return -ENOMEM;
3823
3824                 if (i == 0) {
3825                         qed_chain_init_mem(p_chain, p_virt, p_phys);
3826                         qed_chain_reset(p_chain);
3827                 }
3828
3829                 /* Fill the PBL table with the physical address of the page */
3830                 *(dma_addr_t *)p_pbl_virt = p_phys;
3831                 /* Keep the virtual address of the page */
3832                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3833
3834                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3835         }
3836
3837         return 0;
3838 }
3839
3840 int qed_chain_alloc(struct qed_dev *cdev,
3841                     enum qed_chain_use_mode intended_use,
3842                     enum qed_chain_mode mode,
3843                     enum qed_chain_cnt_type cnt_type,
3844                     u32 num_elems,
3845                     size_t elem_size,
3846                     struct qed_chain *p_chain,
3847                     struct qed_chain_ext_pbl *ext_pbl)
3848 {
3849         u32 page_cnt;
3850         int rc = 0;
3851
3852         if (mode == QED_CHAIN_MODE_SINGLE)
3853                 page_cnt = 1;
3854         else
3855                 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3856
3857         rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
3858         if (rc) {
3859                 DP_NOTICE(cdev,
3860                           "Cannot allocate a chain with the given arguments:\n");
3861                 DP_NOTICE(cdev,
3862                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3863                           intended_use, mode, cnt_type, num_elems, elem_size);
3864                 return rc;
3865         }
3866
3867         qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
3868                               mode, cnt_type);
3869
3870         switch (mode) {
3871         case QED_CHAIN_MODE_NEXT_PTR:
3872                 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
3873                 break;
3874         case QED_CHAIN_MODE_SINGLE:
3875                 rc = qed_chain_alloc_single(cdev, p_chain);
3876                 break;
3877         case QED_CHAIN_MODE_PBL:
3878                 rc = qed_chain_alloc_pbl(cdev, p_chain, ext_pbl);
3879                 break;
3880         }
3881         if (rc)
3882                 goto nomem;
3883
3884         return 0;
3885
3886 nomem:
3887         qed_chain_free(cdev, p_chain);
3888         return rc;
3889 }
3890
3891 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
3892 {
3893         if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
3894                 u16 min, max;
3895
3896                 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
3897                 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
3898                 DP_NOTICE(p_hwfn,
3899                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3900                           src_id, min, max);
3901
3902                 return -EINVAL;
3903         }
3904
3905         *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
3906
3907         return 0;
3908 }
3909
3910 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3911 {
3912         if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
3913                 u8 min, max;
3914
3915                 min = (u8)RESC_START(p_hwfn, QED_VPORT);
3916                 max = min + RESC_NUM(p_hwfn, QED_VPORT);
3917                 DP_NOTICE(p_hwfn,
3918                           "vport id [%d] is not valid, available indices [%d - %d]\n",
3919                           src_id, min, max);
3920
3921                 return -EINVAL;
3922         }
3923
3924         *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
3925
3926         return 0;
3927 }
3928
3929 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3930 {
3931         if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
3932                 u8 min, max;
3933
3934                 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
3935                 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
3936                 DP_NOTICE(p_hwfn,
3937                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3938                           src_id, min, max);
3939
3940                 return -EINVAL;
3941         }
3942
3943         *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
3944
3945         return 0;
3946 }
3947
3948 static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low,
3949                                   u8 *p_filter)
3950 {
3951         *p_high = p_filter[1] | (p_filter[0] << 8);
3952         *p_low = p_filter[5] | (p_filter[4] << 8) |
3953                  (p_filter[3] << 16) | (p_filter[2] << 24);
3954 }
3955
3956 int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
3957                            struct qed_ptt *p_ptt, u8 *p_filter)
3958 {
3959         u32 high = 0, low = 0, en;
3960         int i;
3961
3962         if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))
3963                 return 0;
3964
3965         qed_llh_mac_to_filter(&high, &low, p_filter);
3966
3967         /* Find a free entry and utilize it */
3968         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3969                 en = qed_rd(p_hwfn, p_ptt,
3970                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3971                 if (en)
3972                         continue;
3973                 qed_wr(p_hwfn, p_ptt,
3974                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3975                        2 * i * sizeof(u32), low);
3976                 qed_wr(p_hwfn, p_ptt,
3977                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3978                        (2 * i + 1) * sizeof(u32), high);
3979                 qed_wr(p_hwfn, p_ptt,
3980                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3981                 qed_wr(p_hwfn, p_ptt,
3982                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3983                        i * sizeof(u32), 0);
3984                 qed_wr(p_hwfn, p_ptt,
3985                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3986                 break;
3987         }
3988         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3989                 DP_NOTICE(p_hwfn,
3990                           "Failed to find an empty LLH filter to utilize\n");
3991                 return -EINVAL;
3992         }
3993
3994         DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3995                    "mac: %pM is added at %d\n",
3996                    p_filter, i);
3997
3998         return 0;
3999 }
4000
4001 void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
4002                                struct qed_ptt *p_ptt, u8 *p_filter)
4003 {
4004         u32 high = 0, low = 0;
4005         int i;
4006
4007         if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))
4008                 return;
4009
4010         qed_llh_mac_to_filter(&high, &low, p_filter);
4011
4012         /* Find the entry and clean it */
4013         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4014                 if (qed_rd(p_hwfn, p_ptt,
4015                            NIG_REG_LLH_FUNC_FILTER_VALUE +
4016                            2 * i * sizeof(u32)) != low)
4017                         continue;
4018                 if (qed_rd(p_hwfn, p_ptt,
4019                            NIG_REG_LLH_FUNC_FILTER_VALUE +
4020                            (2 * i + 1) * sizeof(u32)) != high)
4021                         continue;
4022
4023                 qed_wr(p_hwfn, p_ptt,
4024                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4025                 qed_wr(p_hwfn, p_ptt,
4026                        NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
4027                 qed_wr(p_hwfn, p_ptt,
4028                        NIG_REG_LLH_FUNC_FILTER_VALUE +
4029                        (2 * i + 1) * sizeof(u32), 0);
4030
4031                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
4032                            "mac: %pM is removed from %d\n",
4033                            p_filter, i);
4034                 break;
4035         }
4036         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4037                 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
4038 }
4039
4040 int
4041 qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn,
4042                             struct qed_ptt *p_ptt,
4043                             u16 source_port_or_eth_type,
4044                             u16 dest_port, enum qed_llh_port_filter_type_t type)
4045 {
4046         u32 high = 0, low = 0, en;
4047         int i;
4048
4049         if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))
4050                 return 0;
4051
4052         switch (type) {
4053         case QED_LLH_FILTER_ETHERTYPE:
4054                 high = source_port_or_eth_type;
4055                 break;
4056         case QED_LLH_FILTER_TCP_SRC_PORT:
4057         case QED_LLH_FILTER_UDP_SRC_PORT:
4058                 low = source_port_or_eth_type << 16;
4059                 break;
4060         case QED_LLH_FILTER_TCP_DEST_PORT:
4061         case QED_LLH_FILTER_UDP_DEST_PORT:
4062                 low = dest_port;
4063                 break;
4064         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4065         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4066                 low = (source_port_or_eth_type << 16) | dest_port;
4067                 break;
4068         default:
4069                 DP_NOTICE(p_hwfn,
4070                           "Non valid LLH protocol filter type %d\n", type);
4071                 return -EINVAL;
4072         }
4073         /* Find a free entry and utilize it */
4074         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4075                 en = qed_rd(p_hwfn, p_ptt,
4076                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
4077                 if (en)
4078                         continue;
4079                 qed_wr(p_hwfn, p_ptt,
4080                        NIG_REG_LLH_FUNC_FILTER_VALUE +
4081                        2 * i * sizeof(u32), low);
4082                 qed_wr(p_hwfn, p_ptt,
4083                        NIG_REG_LLH_FUNC_FILTER_VALUE +
4084                        (2 * i + 1) * sizeof(u32), high);
4085                 qed_wr(p_hwfn, p_ptt,
4086                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
4087                 qed_wr(p_hwfn, p_ptt,
4088                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4089                        i * sizeof(u32), 1 << type);
4090                 qed_wr(p_hwfn, p_ptt,
4091                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
4092                 break;
4093         }
4094         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
4095                 DP_NOTICE(p_hwfn,
4096                           "Failed to find an empty LLH filter to utilize\n");
4097                 return -EINVAL;
4098         }
4099         switch (type) {
4100         case QED_LLH_FILTER_ETHERTYPE:
4101                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
4102                            "ETH type %x is added at %d\n",
4103                            source_port_or_eth_type, i);
4104                 break;
4105         case QED_LLH_FILTER_TCP_SRC_PORT:
4106                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
4107                            "TCP src port %x is added at %d\n",
4108                            source_port_or_eth_type, i);
4109                 break;
4110         case QED_LLH_FILTER_UDP_SRC_PORT:
4111                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
4112                            "UDP src port %x is added at %d\n",
4113                            source_port_or_eth_type, i);
4114                 break;
4115         case QED_LLH_FILTER_TCP_DEST_PORT:
4116                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
4117                            "TCP dst port %x is added at %d\n", dest_port, i);
4118                 break;
4119         case QED_LLH_FILTER_UDP_DEST_PORT:
4120                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
4121                            "UDP dst port %x is added at %d\n", dest_port, i);
4122                 break;
4123         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4124                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
4125                            "TCP src/dst ports %x/%x are added at %d\n",
4126                            source_port_or_eth_type, dest_port, i);
4127                 break;
4128         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4129                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
4130                            "UDP src/dst ports %x/%x are added at %d\n",
4131                            source_port_or_eth_type, dest_port, i);
4132                 break;
4133         }
4134         return 0;
4135 }
4136
4137 void
4138 qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn,
4139                                struct qed_ptt *p_ptt,
4140                                u16 source_port_or_eth_type,
4141                                u16 dest_port,
4142                                enum qed_llh_port_filter_type_t type)
4143 {
4144         u32 high = 0, low = 0;
4145         int i;
4146
4147         if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))
4148                 return;
4149
4150         switch (type) {
4151         case QED_LLH_FILTER_ETHERTYPE:
4152                 high = source_port_or_eth_type;
4153                 break;
4154         case QED_LLH_FILTER_TCP_SRC_PORT:
4155         case QED_LLH_FILTER_UDP_SRC_PORT:
4156                 low = source_port_or_eth_type << 16;
4157                 break;
4158         case QED_LLH_FILTER_TCP_DEST_PORT:
4159         case QED_LLH_FILTER_UDP_DEST_PORT:
4160                 low = dest_port;
4161                 break;
4162         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4163         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4164                 low = (source_port_or_eth_type << 16) | dest_port;
4165                 break;
4166         default:
4167                 DP_NOTICE(p_hwfn,
4168                           "Non valid LLH protocol filter type %d\n", type);
4169                 return;
4170         }
4171
4172         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4173                 if (!qed_rd(p_hwfn, p_ptt,
4174                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
4175                         continue;
4176                 if (!qed_rd(p_hwfn, p_ptt,
4177                             NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
4178                         continue;
4179                 if (!(qed_rd(p_hwfn, p_ptt,
4180                              NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4181                              i * sizeof(u32)) & BIT(type)))
4182                         continue;
4183                 if (qed_rd(p_hwfn, p_ptt,
4184                            NIG_REG_LLH_FUNC_FILTER_VALUE +
4185                            2 * i * sizeof(u32)) != low)
4186                         continue;
4187                 if (qed_rd(p_hwfn, p_ptt,
4188                            NIG_REG_LLH_FUNC_FILTER_VALUE +
4189                            (2 * i + 1) * sizeof(u32)) != high)
4190                         continue;
4191
4192                 qed_wr(p_hwfn, p_ptt,
4193                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4194                 qed_wr(p_hwfn, p_ptt,
4195                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
4196                 qed_wr(p_hwfn, p_ptt,
4197                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4198                        i * sizeof(u32), 0);
4199                 qed_wr(p_hwfn, p_ptt,
4200                        NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
4201                 qed_wr(p_hwfn, p_ptt,
4202                        NIG_REG_LLH_FUNC_FILTER_VALUE +
4203                        (2 * i + 1) * sizeof(u32), 0);
4204                 break;
4205         }
4206
4207         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4208                 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
4209 }
4210
4211 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
4212                             u32 hw_addr, void *p_eth_qzone,
4213                             size_t eth_qzone_size, u8 timeset)
4214 {
4215         struct coalescing_timeset *p_coal_timeset;
4216
4217         if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
4218                 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
4219                 return -EINVAL;
4220         }
4221
4222         p_coal_timeset = p_eth_qzone;
4223         memset(p_eth_qzone, 0, eth_qzone_size);
4224         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
4225         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
4226         qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
4227
4228         return 0;
4229 }
4230
4231 int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle)
4232 {
4233         struct qed_queue_cid *p_cid = p_handle;
4234         struct qed_hwfn *p_hwfn;
4235         struct qed_ptt *p_ptt;
4236         int rc = 0;
4237
4238         p_hwfn = p_cid->p_owner;
4239
4240         if (IS_VF(p_hwfn->cdev))
4241                 return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid);
4242
4243         p_ptt = qed_ptt_acquire(p_hwfn);
4244         if (!p_ptt)
4245                 return -EAGAIN;
4246
4247         if (rx_coal) {
4248                 rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
4249                 if (rc)
4250                         goto out;
4251                 p_hwfn->cdev->rx_coalesce_usecs = rx_coal;
4252         }
4253
4254         if (tx_coal) {
4255                 rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
4256                 if (rc)
4257                         goto out;
4258                 p_hwfn->cdev->tx_coalesce_usecs = tx_coal;
4259         }
4260 out:
4261         qed_ptt_release(p_hwfn, p_ptt);
4262         return rc;
4263 }
4264
4265 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn,
4266                          struct qed_ptt *p_ptt,
4267                          u16 coalesce, struct qed_queue_cid *p_cid)
4268 {
4269         struct ustorm_eth_queue_zone eth_qzone;
4270         u8 timeset, timer_res;
4271         u32 address;
4272         int rc;
4273
4274         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4275         if (coalesce <= 0x7F) {
4276                 timer_res = 0;
4277         } else if (coalesce <= 0xFF) {
4278                 timer_res = 1;
4279         } else if (coalesce <= 0x1FF) {
4280                 timer_res = 2;
4281         } else {
4282                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4283                 return -EINVAL;
4284         }
4285         timeset = (u8)(coalesce >> timer_res);
4286
4287         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4288                                    p_cid->sb_igu_id, false);
4289         if (rc)
4290                 goto out;
4291
4292         address = BAR0_MAP_REG_USDM_RAM +
4293                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4294
4295         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
4296                               sizeof(struct ustorm_eth_queue_zone), timeset);
4297         if (rc)
4298                 goto out;
4299
4300 out:
4301         return rc;
4302 }
4303
4304 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn,
4305                          struct qed_ptt *p_ptt,
4306                          u16 coalesce, struct qed_queue_cid *p_cid)
4307 {
4308         struct xstorm_eth_queue_zone eth_qzone;
4309         u8 timeset, timer_res;
4310         u32 address;
4311         int rc;
4312
4313         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4314         if (coalesce <= 0x7F) {
4315                 timer_res = 0;
4316         } else if (coalesce <= 0xFF) {
4317                 timer_res = 1;
4318         } else if (coalesce <= 0x1FF) {
4319                 timer_res = 2;
4320         } else {
4321                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4322                 return -EINVAL;
4323         }
4324         timeset = (u8)(coalesce >> timer_res);
4325
4326         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4327                                    p_cid->sb_igu_id, true);
4328         if (rc)
4329                 goto out;
4330
4331         address = BAR0_MAP_REG_XSDM_RAM +
4332                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4333
4334         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
4335                               sizeof(struct xstorm_eth_queue_zone), timeset);
4336 out:
4337         return rc;
4338 }
4339
4340 /* Calculate final WFQ values for all vports and configure them.
4341  * After this configuration each vport will have
4342  * approx min rate =  min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
4343  */
4344 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
4345                                              struct qed_ptt *p_ptt,
4346                                              u32 min_pf_rate)
4347 {
4348         struct init_qm_vport_params *vport_params;
4349         int i;
4350
4351         vport_params = p_hwfn->qm_info.qm_vport_params;
4352
4353         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4354                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4355
4356                 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
4357                                                 min_pf_rate;
4358                 qed_init_vport_wfq(p_hwfn, p_ptt,
4359                                    vport_params[i].first_tx_pq_id,
4360                                    vport_params[i].vport_wfq);
4361         }
4362 }
4363
4364 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
4365                                        u32 min_pf_rate)
4366
4367 {
4368         int i;
4369
4370         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4371                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
4372 }
4373
4374 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
4375                                            struct qed_ptt *p_ptt,
4376                                            u32 min_pf_rate)
4377 {
4378         struct init_qm_vport_params *vport_params;
4379         int i;
4380
4381         vport_params = p_hwfn->qm_info.qm_vport_params;
4382
4383         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4384                 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
4385                 qed_init_vport_wfq(p_hwfn, p_ptt,
4386                                    vport_params[i].first_tx_pq_id,
4387                                    vport_params[i].vport_wfq);
4388         }
4389 }
4390
4391 /* This function performs several validations for WFQ
4392  * configuration and required min rate for a given vport
4393  * 1. req_rate must be greater than one percent of min_pf_rate.
4394  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4395  *    rates to get less than one percent of min_pf_rate.
4396  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4397  */
4398 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
4399                               u16 vport_id, u32 req_rate, u32 min_pf_rate)
4400 {
4401         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4402         int non_requested_count = 0, req_count = 0, i, num_vports;
4403
4404         num_vports = p_hwfn->qm_info.num_vports;
4405
4406         /* Accounting for the vports which are configured for WFQ explicitly */
4407         for (i = 0; i < num_vports; i++) {
4408                 u32 tmp_speed;
4409
4410                 if ((i != vport_id) &&
4411                     p_hwfn->qm_info.wfq_data[i].configured) {
4412                         req_count++;
4413                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4414                         total_req_min_rate += tmp_speed;
4415                 }
4416         }
4417
4418         /* Include current vport data as well */
4419         req_count++;
4420         total_req_min_rate += req_rate;
4421         non_requested_count = num_vports - req_count;
4422
4423         if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
4424                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4425                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4426                            vport_id, req_rate, min_pf_rate);
4427                 return -EINVAL;
4428         }
4429
4430         if (num_vports > QED_WFQ_UNIT) {
4431                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4432                            "Number of vports is greater than %d\n",
4433                            QED_WFQ_UNIT);
4434                 return -EINVAL;
4435         }
4436
4437         if (total_req_min_rate > min_pf_rate) {
4438                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4439                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4440                            total_req_min_rate, min_pf_rate);
4441                 return -EINVAL;
4442         }
4443
4444         total_left_rate = min_pf_rate - total_req_min_rate;
4445
4446         left_rate_per_vp = total_left_rate / non_requested_count;
4447         if (left_rate_per_vp <  min_pf_rate / QED_WFQ_UNIT) {
4448                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4449                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4450                            left_rate_per_vp, min_pf_rate);
4451                 return -EINVAL;
4452         }
4453
4454         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4455         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4456
4457         for (i = 0; i < num_vports; i++) {
4458                 if (p_hwfn->qm_info.wfq_data[i].configured)
4459                         continue;
4460
4461                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4462         }
4463
4464         return 0;
4465 }
4466
4467 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
4468                                      struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
4469 {
4470         struct qed_mcp_link_state *p_link;
4471         int rc = 0;
4472
4473         p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
4474
4475         if (!p_link->min_pf_rate) {
4476                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4477                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4478                 return rc;
4479         }
4480
4481         rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4482
4483         if (!rc)
4484                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4485                                                  p_link->min_pf_rate);
4486         else
4487                 DP_NOTICE(p_hwfn,
4488                           "Validation failed while configuring min rate\n");
4489
4490         return rc;
4491 }
4492
4493 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
4494                                                  struct qed_ptt *p_ptt,
4495                                                  u32 min_pf_rate)
4496 {
4497         bool use_wfq = false;
4498         int rc = 0;
4499         u16 i;
4500
4501         /* Validate all pre configured vports for wfq */
4502         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4503                 u32 rate;
4504
4505                 if (!p_hwfn->qm_info.wfq_data[i].configured)
4506                         continue;
4507
4508                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4509                 use_wfq = true;
4510
4511                 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4512                 if (rc) {
4513                         DP_NOTICE(p_hwfn,
4514                                   "WFQ validation failed while configuring min rate\n");
4515                         break;
4516                 }
4517         }
4518
4519         if (!rc && use_wfq)
4520                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4521         else
4522                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4523
4524         return rc;
4525 }
4526
4527 /* Main API for qed clients to configure vport min rate.
4528  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4529  * rate - Speed in Mbps needs to be assigned to a given vport.
4530  */
4531 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
4532 {
4533         int i, rc = -EINVAL;
4534
4535         /* Currently not supported; Might change in future */
4536         if (cdev->num_hwfns > 1) {
4537                 DP_NOTICE(cdev,
4538                           "WFQ configuration is not supported for this device\n");
4539                 return rc;
4540         }
4541
4542         for_each_hwfn(cdev, i) {
4543                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4544                 struct qed_ptt *p_ptt;
4545
4546                 p_ptt = qed_ptt_acquire(p_hwfn);
4547                 if (!p_ptt)
4548                         return -EBUSY;
4549
4550                 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4551
4552                 if (rc) {
4553                         qed_ptt_release(p_hwfn, p_ptt);
4554                         return rc;
4555                 }
4556
4557                 qed_ptt_release(p_hwfn, p_ptt);
4558         }
4559
4560         return rc;
4561 }
4562
4563 /* API to configure WFQ from mcp link change */
4564 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
4565                                          struct qed_ptt *p_ptt, u32 min_pf_rate)
4566 {
4567         int i;
4568
4569         if (cdev->num_hwfns > 1) {
4570                 DP_VERBOSE(cdev,
4571                            NETIF_MSG_LINK,
4572                            "WFQ configuration is not supported for this device\n");
4573                 return;
4574         }
4575
4576         for_each_hwfn(cdev, i) {
4577                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4578
4579                 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
4580                                                       min_pf_rate);
4581         }
4582 }
4583
4584 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
4585                                      struct qed_ptt *p_ptt,
4586                                      struct qed_mcp_link_state *p_link,
4587                                      u8 max_bw)
4588 {
4589         int rc = 0;
4590
4591         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4592
4593         if (!p_link->line_speed && (max_bw != 100))
4594                 return rc;
4595
4596         p_link->speed = (p_link->line_speed * max_bw) / 100;
4597         p_hwfn->qm_info.pf_rl = p_link->speed;
4598
4599         /* Since the limiter also affects Tx-switched traffic, we don't want it
4600          * to limit such traffic in case there's no actual limit.
4601          * In that case, set limit to imaginary high boundary.
4602          */
4603         if (max_bw == 100)
4604                 p_hwfn->qm_info.pf_rl = 100000;
4605
4606         rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4607                             p_hwfn->qm_info.pf_rl);
4608
4609         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4610                    "Configured MAX bandwidth to be %08x Mb/sec\n",
4611                    p_link->speed);
4612
4613         return rc;
4614 }
4615
4616 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4617 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
4618 {
4619         int i, rc = -EINVAL;
4620
4621         if (max_bw < 1 || max_bw > 100) {
4622                 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
4623                 return rc;
4624         }
4625
4626         for_each_hwfn(cdev, i) {
4627                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4628                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4629                 struct qed_mcp_link_state *p_link;
4630                 struct qed_ptt *p_ptt;
4631
4632                 p_link = &p_lead->mcp_info->link_output;
4633
4634                 p_ptt = qed_ptt_acquire(p_hwfn);
4635                 if (!p_ptt)
4636                         return -EBUSY;
4637
4638                 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4639                                                       p_link, max_bw);
4640
4641                 qed_ptt_release(p_hwfn, p_ptt);
4642
4643                 if (rc)
4644                         break;
4645         }
4646
4647         return rc;
4648 }
4649
4650 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
4651                                      struct qed_ptt *p_ptt,
4652                                      struct qed_mcp_link_state *p_link,
4653                                      u8 min_bw)
4654 {
4655         int rc = 0;
4656
4657         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4658         p_hwfn->qm_info.pf_wfq = min_bw;
4659
4660         if (!p_link->line_speed)
4661                 return rc;
4662
4663         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4664
4665         rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4666
4667         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4668                    "Configured MIN bandwidth to be %d Mb/sec\n",
4669                    p_link->min_pf_rate);
4670
4671         return rc;
4672 }
4673
4674 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4675 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
4676 {
4677         int i, rc = -EINVAL;
4678
4679         if (min_bw < 1 || min_bw > 100) {
4680                 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
4681                 return rc;
4682         }
4683
4684         for_each_hwfn(cdev, i) {
4685                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4686                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4687                 struct qed_mcp_link_state *p_link;
4688                 struct qed_ptt *p_ptt;
4689
4690                 p_link = &p_lead->mcp_info->link_output;
4691
4692                 p_ptt = qed_ptt_acquire(p_hwfn);
4693                 if (!p_ptt)
4694                         return -EBUSY;
4695
4696                 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4697                                                       p_link, min_bw);
4698                 if (rc) {
4699                         qed_ptt_release(p_hwfn, p_ptt);
4700                         return rc;
4701                 }
4702
4703                 if (p_link->min_pf_rate) {
4704                         u32 min_rate = p_link->min_pf_rate;
4705
4706                         rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
4707                                                                    p_ptt,
4708                                                                    min_rate);
4709                 }
4710
4711                 qed_ptt_release(p_hwfn, p_ptt);
4712         }
4713
4714         return rc;
4715 }
4716
4717 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4718 {
4719         struct qed_mcp_link_state *p_link;
4720
4721         p_link = &p_hwfn->mcp_info->link_output;
4722
4723         if (p_link->min_pf_rate)
4724                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4725                                                p_link->min_pf_rate);
4726
4727         memset(p_hwfn->qm_info.wfq_data, 0,
4728                sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
4729 }
4730
4731 int qed_device_num_engines(struct qed_dev *cdev)
4732 {
4733         return QED_IS_BB(cdev) ? 2 : 1;
4734 }
4735
4736 static int qed_device_num_ports(struct qed_dev *cdev)
4737 {
4738         /* in CMT always only one port */
4739         if (cdev->num_hwfns > 1)
4740                 return 1;
4741
4742         return cdev->num_ports_in_engine * qed_device_num_engines(cdev);
4743 }
4744
4745 int qed_device_get_port_id(struct qed_dev *cdev)
4746 {
4747         return (QED_LEADING_HWFN(cdev)->abs_pf_id) % qed_device_num_ports(cdev);
4748 }
4749
4750 void qed_set_fw_mac_addr(__le16 *fw_msb,
4751                          __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
4752 {
4753         ((u8 *)fw_msb)[0] = mac[1];
4754         ((u8 *)fw_msb)[1] = mac[0];
4755         ((u8 *)fw_mid)[0] = mac[3];
4756         ((u8 *)fw_mid)[1] = mac[2];
4757         ((u8 *)fw_lsb)[0] = mac[5];
4758         ((u8 *)fw_lsb)[1] = mac[4];
4759 }