1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi Ocelot Switch driver
5 * Copyright (c) 2017 Microsemi Corporation
7 #include <linux/dsa/ocelot.h>
8 #include <linux/if_bridge.h>
9 #include <linux/ptp_classify.h>
10 #include <soc/mscc/ocelot_vcap.h>
12 #include "ocelot_vcap.h"
14 #define TABLE_UPDATE_SLEEP_US 10
15 #define TABLE_UPDATE_TIMEOUT_US 100000
17 struct ocelot_mact_entry {
20 enum macaccess_entry_type type;
23 /* Caller must hold &ocelot->mact_lock */
24 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot)
26 return ocelot_read(ocelot, ANA_TABLES_MACACCESS);
29 /* Caller must hold &ocelot->mact_lock */
30 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot)
34 return readx_poll_timeout(ocelot_mact_read_macaccess,
36 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) ==
38 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
41 /* Caller must hold &ocelot->mact_lock */
42 static void ocelot_mact_select(struct ocelot *ocelot,
43 const unsigned char mac[ETH_ALEN],
46 u32 macl = 0, mach = 0;
48 /* Set the MAC address to handle and the vlan associated in a format
49 * understood by the hardware.
59 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA);
60 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA);
64 static int __ocelot_mact_learn(struct ocelot *ocelot, int port,
65 const unsigned char mac[ETH_ALEN],
66 unsigned int vid, enum macaccess_entry_type type)
68 u32 cmd = ANA_TABLES_MACACCESS_VALID |
69 ANA_TABLES_MACACCESS_DEST_IDX(port) |
70 ANA_TABLES_MACACCESS_ENTRYTYPE(type) |
71 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN);
72 unsigned int mc_ports;
75 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */
76 if (type == ENTRYTYPE_MACv4)
77 mc_ports = (mac[1] << 8) | mac[2];
78 else if (type == ENTRYTYPE_MACv6)
79 mc_ports = (mac[0] << 8) | mac[1];
83 if (mc_ports & BIT(ocelot->num_phys_ports))
84 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY;
86 ocelot_mact_select(ocelot, mac, vid);
88 /* Issue a write command */
89 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS);
91 err = ocelot_mact_wait_for_completion(ocelot);
96 int ocelot_mact_learn(struct ocelot *ocelot, int port,
97 const unsigned char mac[ETH_ALEN],
98 unsigned int vid, enum macaccess_entry_type type)
102 mutex_lock(&ocelot->mact_lock);
103 ret = __ocelot_mact_learn(ocelot, port, mac, vid, type);
104 mutex_unlock(&ocelot->mact_lock);
108 EXPORT_SYMBOL(ocelot_mact_learn);
110 int ocelot_mact_forget(struct ocelot *ocelot,
111 const unsigned char mac[ETH_ALEN], unsigned int vid)
115 mutex_lock(&ocelot->mact_lock);
117 ocelot_mact_select(ocelot, mac, vid);
119 /* Issue a forget command */
121 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET),
122 ANA_TABLES_MACACCESS);
124 err = ocelot_mact_wait_for_completion(ocelot);
126 mutex_unlock(&ocelot->mact_lock);
130 EXPORT_SYMBOL(ocelot_mact_forget);
132 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx,
133 const unsigned char mac[ETH_ALEN],
134 unsigned int vid, enum macaccess_entry_type *type)
138 mutex_lock(&ocelot->mact_lock);
140 ocelot_mact_select(ocelot, mac, vid);
142 /* Issue a read command with MACACCESS_VALID=1. */
143 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID |
144 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
145 ANA_TABLES_MACACCESS);
147 if (ocelot_mact_wait_for_completion(ocelot)) {
148 mutex_unlock(&ocelot->mact_lock);
152 /* Read back the entry flags */
153 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
155 mutex_unlock(&ocelot->mact_lock);
157 if (!(val & ANA_TABLES_MACACCESS_VALID))
160 *dst_idx = ANA_TABLES_MACACCESS_DEST_IDX_X(val);
161 *type = ANA_TABLES_MACACCESS_ENTRYTYPE_X(val);
165 EXPORT_SYMBOL(ocelot_mact_lookup);
167 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx,
168 const unsigned char mac[ETH_ALEN],
170 enum macaccess_entry_type type,
175 mutex_lock(&ocelot->mact_lock);
178 (sfid < 0 ? 0 : ANA_TABLES_STREAMDATA_SFID_VALID) |
179 ANA_TABLES_STREAMDATA_SFID(sfid) |
180 (ssid < 0 ? 0 : ANA_TABLES_STREAMDATA_SSID_VALID) |
181 ANA_TABLES_STREAMDATA_SSID(ssid),
182 ANA_TABLES_STREAMDATA);
184 ret = __ocelot_mact_learn(ocelot, dst_idx, mac, vid, type);
186 mutex_unlock(&ocelot->mact_lock);
190 EXPORT_SYMBOL(ocelot_mact_learn_streamdata);
192 static void ocelot_mact_init(struct ocelot *ocelot)
194 /* Configure the learning mode entries attributes:
195 * - Do not copy the frame to the CPU extraction queues.
196 * - Use the vlan and mac_cpoy for dmac lookup.
198 ocelot_rmw(ocelot, 0,
199 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS
200 | ANA_AGENCTRL_LEARN_FWD_KILL
201 | ANA_AGENCTRL_LEARN_IGNORE_VLAN,
204 /* Clear the MAC table. We are not concurrent with anyone, so
205 * holding &ocelot->mact_lock is pointless.
207 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
210 static void ocelot_vcap_enable(struct ocelot *ocelot, int port)
212 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA |
213 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa),
214 ANA_PORT_VCAP_S2_CFG, port);
216 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA,
217 ANA_PORT_VCAP_CFG, port);
219 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN,
224 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot)
226 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
229 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot)
233 return readx_poll_timeout(ocelot_vlant_read_vlanaccess,
236 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) ==
237 ANA_TABLES_VLANACCESS_CMD_IDLE,
238 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
241 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask)
243 /* Select the VID to configure */
244 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid),
245 ANA_TABLES_VLANTIDX);
246 /* Set the vlan port members mask and issue a write command */
247 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) |
248 ANA_TABLES_VLANACCESS_CMD_WRITE,
249 ANA_TABLES_VLANACCESS);
251 return ocelot_vlant_wait_for_completion(ocelot);
254 static int ocelot_port_num_untagged_vlans(struct ocelot *ocelot, int port)
256 struct ocelot_bridge_vlan *vlan;
257 int num_untagged = 0;
259 list_for_each_entry(vlan, &ocelot->vlans, list) {
260 if (!(vlan->portmask & BIT(port)))
263 if (vlan->untagged & BIT(port))
270 static int ocelot_port_num_tagged_vlans(struct ocelot *ocelot, int port)
272 struct ocelot_bridge_vlan *vlan;
275 list_for_each_entry(vlan, &ocelot->vlans, list) {
276 if (!(vlan->portmask & BIT(port)))
279 if (!(vlan->untagged & BIT(port)))
286 /* We use native VLAN when we have to mix egress-tagged VLANs with exactly
287 * _one_ egress-untagged VLAN (_the_ native VLAN)
289 static bool ocelot_port_uses_native_vlan(struct ocelot *ocelot, int port)
291 return ocelot_port_num_tagged_vlans(ocelot, port) &&
292 ocelot_port_num_untagged_vlans(ocelot, port) == 1;
295 static struct ocelot_bridge_vlan *
296 ocelot_port_find_native_vlan(struct ocelot *ocelot, int port)
298 struct ocelot_bridge_vlan *vlan;
300 list_for_each_entry(vlan, &ocelot->vlans, list)
301 if (vlan->portmask & BIT(port) && vlan->untagged & BIT(port))
307 /* Keep in sync REW_TAG_CFG_TAG_CFG and, if applicable,
308 * REW_PORT_VLAN_CFG_PORT_VID, with the bridge VLAN table and VLAN awareness
311 static void ocelot_port_manage_port_tag(struct ocelot *ocelot, int port)
313 struct ocelot_port *ocelot_port = ocelot->ports[port];
314 enum ocelot_port_tag_config tag_cfg;
315 bool uses_native_vlan = false;
317 if (ocelot_port->vlan_aware) {
318 uses_native_vlan = ocelot_port_uses_native_vlan(ocelot, port);
320 if (uses_native_vlan)
321 tag_cfg = OCELOT_PORT_TAG_NATIVE;
322 else if (ocelot_port_num_untagged_vlans(ocelot, port))
323 tag_cfg = OCELOT_PORT_TAG_DISABLED;
325 tag_cfg = OCELOT_PORT_TAG_TRUNK;
327 tag_cfg = OCELOT_PORT_TAG_DISABLED;
330 ocelot_rmw_gix(ocelot, REW_TAG_CFG_TAG_CFG(tag_cfg),
331 REW_TAG_CFG_TAG_CFG_M,
334 if (uses_native_vlan) {
335 struct ocelot_bridge_vlan *native_vlan;
337 /* Not having a native VLAN is impossible, because
338 * ocelot_port_num_untagged_vlans has returned 1.
339 * So there is no use in checking for NULL here.
341 native_vlan = ocelot_port_find_native_vlan(ocelot, port);
343 ocelot_rmw_gix(ocelot,
344 REW_PORT_VLAN_CFG_PORT_VID(native_vlan->vid),
345 REW_PORT_VLAN_CFG_PORT_VID_M,
346 REW_PORT_VLAN_CFG, port);
350 /* Default vlan to clasify for untagged frames (may be zero) */
351 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port,
352 const struct ocelot_bridge_vlan *pvid_vlan)
354 struct ocelot_port *ocelot_port = ocelot->ports[port];
355 u16 pvid = OCELOT_VLAN_UNAWARE_PVID;
358 ocelot_port->pvid_vlan = pvid_vlan;
360 if (ocelot_port->vlan_aware && pvid_vlan)
361 pvid = pvid_vlan->vid;
363 ocelot_rmw_gix(ocelot,
364 ANA_PORT_VLAN_CFG_VLAN_VID(pvid),
365 ANA_PORT_VLAN_CFG_VLAN_VID_M,
366 ANA_PORT_VLAN_CFG, port);
368 /* If there's no pvid, we should drop not only untagged traffic (which
369 * happens automatically), but also 802.1p traffic which gets
370 * classified to VLAN 0, but that is always in our RX filter, so it
371 * would get accepted were it not for this setting.
373 if (!pvid_vlan && ocelot_port->vlan_aware)
374 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
375 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA;
377 ocelot_rmw_gix(ocelot, val,
378 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
379 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA,
380 ANA_PORT_DROP_CFG, port);
383 static struct ocelot_bridge_vlan *ocelot_bridge_vlan_find(struct ocelot *ocelot,
386 struct ocelot_bridge_vlan *vlan;
388 list_for_each_entry(vlan, &ocelot->vlans, list)
389 if (vlan->vid == vid)
395 static int ocelot_vlan_member_add(struct ocelot *ocelot, int port, u16 vid,
398 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid);
399 unsigned long portmask;
403 portmask = vlan->portmask | BIT(port);
405 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
409 vlan->portmask = portmask;
410 /* Bridge VLANs can be overwritten with a different
411 * egress-tagging setting, so make sure to override an untagged
412 * with a tagged VID if that's going on.
415 vlan->untagged |= BIT(port);
417 vlan->untagged &= ~BIT(port);
422 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
426 portmask = BIT(port);
428 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
435 vlan->portmask = portmask;
437 vlan->untagged = BIT(port);
438 INIT_LIST_HEAD(&vlan->list);
439 list_add_tail(&vlan->list, &ocelot->vlans);
444 static int ocelot_vlan_member_del(struct ocelot *ocelot, int port, u16 vid)
446 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid);
447 unsigned long portmask;
453 portmask = vlan->portmask & ~BIT(port);
455 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
459 vlan->portmask = portmask;
463 list_del(&vlan->list);
469 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
470 bool vlan_aware, struct netlink_ext_ack *extack)
472 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1];
473 struct ocelot_port *ocelot_port = ocelot->ports[port];
474 struct ocelot_vcap_filter *filter;
477 list_for_each_entry(filter, &block->rules, list) {
478 if (filter->ingress_port_mask & BIT(port) &&
479 filter->action.vid_replace_ena) {
480 NL_SET_ERR_MSG_MOD(extack,
481 "Cannot change VLAN state with vlan modify rules active");
486 ocelot_port->vlan_aware = vlan_aware;
489 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
490 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
493 ocelot_rmw_gix(ocelot, val,
494 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
495 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M,
496 ANA_PORT_VLAN_CFG, port);
498 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan);
499 ocelot_port_manage_port_tag(ocelot, port);
503 EXPORT_SYMBOL(ocelot_port_vlan_filtering);
505 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid,
506 bool untagged, struct netlink_ext_ack *extack)
509 /* We are adding an egress-tagged VLAN */
510 if (ocelot_port_uses_native_vlan(ocelot, port)) {
511 NL_SET_ERR_MSG_MOD(extack,
512 "Port with egress-tagged VLANs cannot have more than one egress-untagged (native) VLAN");
516 /* We are adding an egress-tagged VLAN */
517 if (ocelot_port_num_untagged_vlans(ocelot, port) > 1) {
518 NL_SET_ERR_MSG_MOD(extack,
519 "Port with more than one egress-untagged VLAN cannot have egress-tagged VLANs");
526 EXPORT_SYMBOL(ocelot_vlan_prepare);
528 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
533 err = ocelot_vlan_member_add(ocelot, port, vid, untagged);
537 /* Default ingress vlan classification */
539 ocelot_port_set_pvid(ocelot, port,
540 ocelot_bridge_vlan_find(ocelot, vid));
542 /* Untagged egress vlan clasification */
543 ocelot_port_manage_port_tag(ocelot, port);
547 EXPORT_SYMBOL(ocelot_vlan_add);
549 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid)
551 struct ocelot_port *ocelot_port = ocelot->ports[port];
554 err = ocelot_vlan_member_del(ocelot, port, vid);
559 if (ocelot_port->pvid_vlan && ocelot_port->pvid_vlan->vid == vid)
560 ocelot_port_set_pvid(ocelot, port, NULL);
563 ocelot_port_manage_port_tag(ocelot, port);
567 EXPORT_SYMBOL(ocelot_vlan_del);
569 static void ocelot_vlan_init(struct ocelot *ocelot)
571 unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0);
574 /* Clear VLAN table, by default all ports are members of all VLANs */
575 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT,
576 ANA_TABLES_VLANACCESS);
577 ocelot_vlant_wait_for_completion(ocelot);
579 /* Configure the port VLAN memberships */
580 for (vid = 1; vid < VLAN_N_VID; vid++)
581 ocelot_vlant_set_mask(ocelot, vid, 0);
583 /* Because VLAN filtering is enabled, we need VID 0 to get untagged
584 * traffic. It is added automatically if 8021q module is loaded, but
585 * we can't rely on it since module may be not loaded.
587 ocelot_vlant_set_mask(ocelot, OCELOT_VLAN_UNAWARE_PVID, all_ports);
589 /* Set vlan ingress filter mask to all ports but the CPU port by
592 ocelot_write(ocelot, all_ports, ANA_VLANMASK);
594 for (port = 0; port < ocelot->num_phys_ports; port++) {
595 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port);
596 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port);
600 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port)
602 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port);
605 static int ocelot_port_flush(struct ocelot *ocelot, int port)
607 unsigned int pause_ena;
610 /* Disable dequeuing from the egress queues */
611 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS,
612 QSYS_PORT_MODE_DEQUEUE_DIS,
613 QSYS_PORT_MODE, port);
615 /* Disable flow control */
616 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena);
617 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0);
619 /* Disable priority flow control */
620 ocelot_fields_write(ocelot, port,
621 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0);
623 /* Wait at least the time it takes to receive a frame of maximum length
625 * Worst-case delays for 10 kilobyte jumbo frames are:
627 * 800 μs on a 100M port
628 * 80 μs on a 1G port
629 * 32 μs on a 2.5G port
631 usleep_range(8000, 10000);
633 /* Disable half duplex backpressure. */
634 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE,
635 SYS_FRONT_PORT_MODE, port);
637 /* Flush the queues associated with the port. */
638 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA,
641 /* Enable dequeuing from the egress queues. */
642 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE,
645 /* Wait until flushing is complete. */
646 err = read_poll_timeout(ocelot_read_eq_avail, val, !val,
647 100, 2000000, false, ocelot, port);
649 /* Clear flushing again. */
650 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port);
652 /* Re-enable flow control */
653 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena);
658 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port,
659 unsigned int link_an_mode,
660 phy_interface_t interface,
661 unsigned long quirks)
663 struct ocelot_port *ocelot_port = ocelot->ports[port];
666 ocelot_port->speed = SPEED_UNKNOWN;
668 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA,
671 if (ocelot->ops->cut_through_fwd) {
672 mutex_lock(&ocelot->fwd_domain_lock);
673 ocelot->ops->cut_through_fwd(ocelot);
674 mutex_unlock(&ocelot->fwd_domain_lock);
677 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0);
679 err = ocelot_port_flush(ocelot, port);
681 dev_err(ocelot->dev, "failed to flush port %d: %d\n",
684 /* Put the port in reset. */
685 if (interface != PHY_INTERFACE_MODE_QSGMII ||
686 !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP))
687 ocelot_port_rmwl(ocelot_port,
688 DEV_CLOCK_CFG_MAC_TX_RST |
689 DEV_CLOCK_CFG_MAC_RX_RST,
690 DEV_CLOCK_CFG_MAC_TX_RST |
691 DEV_CLOCK_CFG_MAC_RX_RST,
694 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down);
696 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port,
697 struct phy_device *phydev,
698 unsigned int link_an_mode,
699 phy_interface_t interface,
700 int speed, int duplex,
701 bool tx_pause, bool rx_pause,
702 unsigned long quirks)
704 struct ocelot_port *ocelot_port = ocelot->ports[port];
705 int mac_speed, mode = 0;
708 ocelot_port->speed = speed;
710 /* The MAC might be integrated in systems where the MAC speed is fixed
711 * and it's the PCS who is performing the rate adaptation, so we have
712 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG
713 * (which is also its default value).
715 if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) ||
716 speed == SPEED_1000) {
717 mac_speed = OCELOT_SPEED_1000;
718 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
719 } else if (speed == SPEED_2500) {
720 mac_speed = OCELOT_SPEED_2500;
721 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
722 } else if (speed == SPEED_100) {
723 mac_speed = OCELOT_SPEED_100;
725 mac_speed = OCELOT_SPEED_10;
728 if (duplex == DUPLEX_FULL)
729 mode |= DEV_MAC_MODE_CFG_FDX_ENA;
731 ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG);
733 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and
734 * PORT_RST bits in DEV_CLOCK_CFG.
736 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed),
741 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10);
744 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100);
748 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000);
751 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n",
756 /* Handle RX pause in all cases, with 2500base-X this is used for rate
759 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA;
762 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA |
763 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
764 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
765 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA;
767 /* Flow control. Link speed is only used here to evaluate the time
768 * specification in incoming pause frames.
770 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port);
772 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
774 /* Don't attempt to send PAUSE frames on the NPI port, it's broken */
775 if (port != ocelot->npi)
776 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA,
779 /* Undo the effects of ocelot_phylink_mac_link_down:
782 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
783 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
785 /* If the port supports cut-through forwarding, update the masks before
786 * enabling forwarding on the port.
788 if (ocelot->ops->cut_through_fwd) {
789 mutex_lock(&ocelot->fwd_domain_lock);
790 ocelot->ops->cut_through_fwd(ocelot);
791 mutex_unlock(&ocelot->fwd_domain_lock);
794 /* Core: Enable port for frame transfer */
795 ocelot_fields_write(ocelot, port,
796 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
798 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up);
800 static int ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port,
801 struct sk_buff *clone)
803 struct ocelot_port *ocelot_port = ocelot->ports[port];
806 spin_lock_irqsave(&ocelot->ts_id_lock, flags);
808 if (ocelot_port->ptp_skbs_in_flight == OCELOT_MAX_PTP_ID ||
809 ocelot->ptp_skbs_in_flight == OCELOT_PTP_FIFO_SIZE) {
810 spin_unlock_irqrestore(&ocelot->ts_id_lock, flags);
814 skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS;
815 /* Store timestamp ID in OCELOT_SKB_CB(clone)->ts_id */
816 OCELOT_SKB_CB(clone)->ts_id = ocelot_port->ts_id;
818 ocelot_port->ts_id++;
819 if (ocelot_port->ts_id == OCELOT_MAX_PTP_ID)
820 ocelot_port->ts_id = 0;
822 ocelot_port->ptp_skbs_in_flight++;
823 ocelot->ptp_skbs_in_flight++;
825 skb_queue_tail(&ocelot_port->tx_skbs, clone);
827 spin_unlock_irqrestore(&ocelot->ts_id_lock, flags);
832 static bool ocelot_ptp_is_onestep_sync(struct sk_buff *skb,
833 unsigned int ptp_class)
835 struct ptp_header *hdr;
838 hdr = ptp_parse_header(skb, ptp_class);
842 msgtype = ptp_get_msgtype(hdr, ptp_class);
843 twostep = hdr->flag_field[0] & 0x2;
845 if (msgtype == PTP_MSGTYPE_SYNC && twostep == 0)
851 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port,
853 struct sk_buff **clone)
855 struct ocelot_port *ocelot_port = ocelot->ports[port];
856 u8 ptp_cmd = ocelot_port->ptp_cmd;
857 unsigned int ptp_class;
860 /* Don't do anything if PTP timestamping not enabled */
864 ptp_class = ptp_classify_raw(skb);
865 if (ptp_class == PTP_CLASS_NONE)
868 /* Store ptp_cmd in OCELOT_SKB_CB(skb)->ptp_cmd */
869 if (ptp_cmd == IFH_REW_OP_ORIGIN_PTP) {
870 if (ocelot_ptp_is_onestep_sync(skb, ptp_class)) {
871 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd;
875 /* Fall back to two-step timestamping */
876 ptp_cmd = IFH_REW_OP_TWO_STEP_PTP;
879 if (ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) {
880 *clone = skb_clone_sk(skb);
884 err = ocelot_port_add_txtstamp_skb(ocelot, port, *clone);
888 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd;
889 OCELOT_SKB_CB(*clone)->ptp_class = ptp_class;
894 EXPORT_SYMBOL(ocelot_port_txtstamp_request);
896 static void ocelot_get_hwtimestamp(struct ocelot *ocelot,
897 struct timespec64 *ts)
902 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
904 /* Read current PTP time to get seconds */
905 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
907 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
908 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE);
909 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
910 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN);
912 /* Read packet HW timestamp from FIFO */
913 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP);
914 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val);
916 /* Sec has incremented since the ts was registered */
917 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC))
920 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
923 static bool ocelot_validate_ptp_skb(struct sk_buff *clone, u16 seqid)
925 struct ptp_header *hdr;
927 hdr = ptp_parse_header(clone, OCELOT_SKB_CB(clone)->ptp_class);
931 return seqid == ntohs(hdr->sequence_id);
934 void ocelot_get_txtstamp(struct ocelot *ocelot)
936 int budget = OCELOT_PTP_QUEUE_SZ;
939 struct sk_buff *skb, *skb_tmp, *skb_match = NULL;
940 struct skb_shared_hwtstamps shhwtstamps;
941 u32 val, id, seqid, txport;
942 struct ocelot_port *port;
943 struct timespec64 ts;
946 val = ocelot_read(ocelot, SYS_PTP_STATUS);
948 /* Check if a timestamp can be retrieved */
949 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD))
952 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL);
954 /* Retrieve the ts ID and Tx port */
955 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val);
956 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val);
957 seqid = SYS_PTP_STATUS_PTP_MESS_SEQ_ID(val);
959 port = ocelot->ports[txport];
961 spin_lock(&ocelot->ts_id_lock);
962 port->ptp_skbs_in_flight--;
963 ocelot->ptp_skbs_in_flight--;
964 spin_unlock(&ocelot->ts_id_lock);
966 /* Retrieve its associated skb */
968 spin_lock_irqsave(&port->tx_skbs.lock, flags);
970 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) {
971 if (OCELOT_SKB_CB(skb)->ts_id != id)
973 __skb_unlink(skb, &port->tx_skbs);
978 spin_unlock_irqrestore(&port->tx_skbs.lock, flags);
980 if (WARN_ON(!skb_match))
983 if (!ocelot_validate_ptp_skb(skb_match, seqid)) {
984 dev_err_ratelimited(ocelot->dev,
985 "port %d received stale TX timestamp for seqid %d, discarding\n",
987 dev_kfree_skb_any(skb);
991 /* Get the h/w timestamp */
992 ocelot_get_hwtimestamp(ocelot, &ts);
994 /* Set the timestamp into the skb */
995 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
996 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec);
997 skb_complete_tx_timestamp(skb_match, &shhwtstamps);
1000 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT);
1003 EXPORT_SYMBOL(ocelot_get_txtstamp);
1005 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh,
1008 u32 bytes_valid, val;
1010 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1011 if (val == XTR_NOT_READY) {
1016 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1017 } while (val == XTR_NOT_READY);
1028 bytes_valid = XTR_VALID_BYTES(val);
1029 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1030 if (val == XTR_ESCAPE)
1031 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1037 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1047 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh)
1051 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) {
1052 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]);
1054 return (err < 0) ? err : -EIO;
1060 void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb,
1063 struct skb_shared_hwtstamps *shhwtstamps;
1064 u64 tod_in_ns, full_ts_in_ns;
1065 struct timespec64 ts;
1067 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
1069 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec);
1070 if ((tod_in_ns & 0xffffffff) < timestamp)
1071 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) |
1074 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) |
1077 shhwtstamps = skb_hwtstamps(skb);
1078 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
1079 shhwtstamps->hwtstamp = full_ts_in_ns;
1081 EXPORT_SYMBOL(ocelot_ptp_rx_timestamp);
1083 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb)
1085 u64 timestamp, src_port, len;
1086 u32 xfh[OCELOT_TAG_LEN / 4];
1087 struct net_device *dev;
1088 struct sk_buff *skb;
1093 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh);
1097 ocelot_xfh_get_src_port(xfh, &src_port);
1098 ocelot_xfh_get_len(xfh, &len);
1099 ocelot_xfh_get_rew_val(xfh, ×tamp);
1101 if (WARN_ON(src_port >= ocelot->num_phys_ports))
1104 dev = ocelot->ops->port_to_netdev(ocelot, src_port);
1108 skb = netdev_alloc_skb(dev, len);
1109 if (unlikely(!skb)) {
1110 netdev_err(dev, "Unable to allocate sk_buff\n");
1114 buf_len = len - ETH_FCS_LEN;
1115 buf = (u32 *)skb_put(skb, buf_len);
1119 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
1126 } while (len < buf_len);
1129 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
1135 /* Update the statistics if part of the FCS was read before */
1136 len -= ETH_FCS_LEN - sz;
1138 if (unlikely(dev->features & NETIF_F_RXFCS)) {
1139 buf = (u32 *)skb_put(skb, ETH_FCS_LEN);
1144 ocelot_ptp_rx_timestamp(ocelot, skb, timestamp);
1146 /* Everything we see on an interface that is in the HW bridge
1147 * has already been forwarded.
1149 if (ocelot->ports[src_port]->bridge)
1150 skb->offload_fwd_mark = 1;
1152 skb->protocol = eth_type_trans(skb, dev);
1162 EXPORT_SYMBOL(ocelot_xtr_poll_frame);
1164 bool ocelot_can_inject(struct ocelot *ocelot, int grp)
1166 u32 val = ocelot_read(ocelot, QS_INJ_STATUS);
1168 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))))
1170 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))
1175 EXPORT_SYMBOL(ocelot_can_inject);
1177 void ocelot_ifh_port_set(void *ifh, int port, u32 rew_op, u32 vlan_tag)
1179 ocelot_ifh_set_bypass(ifh, 1);
1180 ocelot_ifh_set_dest(ifh, BIT_ULL(port));
1181 ocelot_ifh_set_tag_type(ifh, IFH_TAG_TYPE_C);
1183 ocelot_ifh_set_vlan_tci(ifh, vlan_tag);
1185 ocelot_ifh_set_rew_op(ifh, rew_op);
1187 EXPORT_SYMBOL(ocelot_ifh_port_set);
1189 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp,
1190 u32 rew_op, struct sk_buff *skb)
1192 u32 ifh[OCELOT_TAG_LEN / 4] = {0};
1193 unsigned int i, count, last;
1195 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
1196 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp);
1198 ocelot_ifh_port_set(ifh, port, rew_op, skb_vlan_tag_get(skb));
1200 for (i = 0; i < OCELOT_TAG_LEN / 4; i++)
1201 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp);
1203 count = DIV_ROUND_UP(skb->len, 4);
1204 last = skb->len % 4;
1205 for (i = 0; i < count; i++)
1206 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp);
1209 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) {
1210 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
1214 /* Indicate EOF and valid bytes in last word */
1215 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
1216 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) |
1221 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
1222 skb_tx_timestamp(skb);
1224 skb->dev->stats.tx_packets++;
1225 skb->dev->stats.tx_bytes += skb->len;
1227 EXPORT_SYMBOL(ocelot_port_inject_frame);
1229 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp)
1231 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))
1232 ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1234 EXPORT_SYMBOL(ocelot_drain_cpu_queue);
1236 int ocelot_fdb_add(struct ocelot *ocelot, int port,
1237 const unsigned char *addr, u16 vid)
1241 if (port == ocelot->npi)
1244 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED);
1246 EXPORT_SYMBOL(ocelot_fdb_add);
1248 int ocelot_fdb_del(struct ocelot *ocelot, int port,
1249 const unsigned char *addr, u16 vid)
1251 return ocelot_mact_forget(ocelot, addr, vid);
1253 EXPORT_SYMBOL(ocelot_fdb_del);
1255 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid,
1256 bool is_static, void *data)
1258 struct ocelot_dump_ctx *dump = data;
1259 u32 portid = NETLINK_CB(dump->cb->skb).portid;
1260 u32 seq = dump->cb->nlh->nlmsg_seq;
1261 struct nlmsghdr *nlh;
1264 if (dump->idx < dump->cb->args[2])
1267 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH,
1268 sizeof(*ndm), NLM_F_MULTI);
1272 ndm = nlmsg_data(nlh);
1273 ndm->ndm_family = AF_BRIDGE;
1276 ndm->ndm_flags = NTF_SELF;
1278 ndm->ndm_ifindex = dump->dev->ifindex;
1279 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
1281 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr))
1282 goto nla_put_failure;
1284 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid))
1285 goto nla_put_failure;
1287 nlmsg_end(dump->skb, nlh);
1294 nlmsg_cancel(dump->skb, nlh);
1297 EXPORT_SYMBOL(ocelot_port_fdb_do_dump);
1299 /* Caller must hold &ocelot->mact_lock */
1300 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col,
1301 struct ocelot_mact_entry *entry)
1303 u32 val, dst, macl, mach;
1306 /* Set row and column to read from */
1307 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row);
1308 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col);
1310 /* Issue a read command */
1311 ocelot_write(ocelot,
1312 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
1313 ANA_TABLES_MACACCESS);
1315 if (ocelot_mact_wait_for_completion(ocelot))
1318 /* Read the entry flags */
1319 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
1320 if (!(val & ANA_TABLES_MACACCESS_VALID))
1323 /* If the entry read has another port configured as its destination,
1326 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3;
1330 /* Get the entry's MAC address and VLAN id */
1331 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA);
1332 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA);
1334 mac[0] = (mach >> 8) & 0xff;
1335 mac[1] = (mach >> 0) & 0xff;
1336 mac[2] = (macl >> 24) & 0xff;
1337 mac[3] = (macl >> 16) & 0xff;
1338 mac[4] = (macl >> 8) & 0xff;
1339 mac[5] = (macl >> 0) & 0xff;
1341 entry->vid = (mach >> 16) & 0xfff;
1342 ether_addr_copy(entry->mac, mac);
1347 int ocelot_mact_flush(struct ocelot *ocelot, int port)
1351 mutex_lock(&ocelot->mact_lock);
1353 /* Program ageing filter for a single port */
1354 ocelot_write(ocelot, ANA_ANAGEFIL_PID_EN | ANA_ANAGEFIL_PID_VAL(port),
1357 /* Flushing dynamic FDB entries requires two successive age scans */
1358 ocelot_write(ocelot,
1359 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE),
1360 ANA_TABLES_MACACCESS);
1362 err = ocelot_mact_wait_for_completion(ocelot);
1364 mutex_unlock(&ocelot->mact_lock);
1369 ocelot_write(ocelot,
1370 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE),
1371 ANA_TABLES_MACACCESS);
1373 err = ocelot_mact_wait_for_completion(ocelot);
1375 /* Restore ageing filter */
1376 ocelot_write(ocelot, 0, ANA_ANAGEFIL);
1378 mutex_unlock(&ocelot->mact_lock);
1382 EXPORT_SYMBOL_GPL(ocelot_mact_flush);
1384 int ocelot_fdb_dump(struct ocelot *ocelot, int port,
1385 dsa_fdb_dump_cb_t *cb, void *data)
1390 /* We could take the lock just around ocelot_mact_read, but doing so
1391 * thousands of times in a row seems rather pointless and inefficient.
1393 mutex_lock(&ocelot->mact_lock);
1395 /* Loop through all the mac tables entries. */
1396 for (i = 0; i < ocelot->num_mact_rows; i++) {
1397 for (j = 0; j < 4; j++) {
1398 struct ocelot_mact_entry entry;
1401 err = ocelot_mact_read(ocelot, port, i, j, &entry);
1402 /* If the entry is invalid (wrong port, invalid...),
1410 is_static = (entry.type == ENTRYTYPE_LOCKED);
1412 err = cb(entry.mac, entry.vid, is_static, data);
1418 mutex_unlock(&ocelot->mact_lock);
1422 EXPORT_SYMBOL(ocelot_fdb_dump);
1424 static void ocelot_populate_l2_ptp_trap_key(struct ocelot_vcap_filter *trap)
1426 trap->key_type = OCELOT_VCAP_KEY_ETYPE;
1427 *(__be16 *)trap->key.etype.etype.value = htons(ETH_P_1588);
1428 *(__be16 *)trap->key.etype.etype.mask = htons(0xffff);
1432 ocelot_populate_ipv4_ptp_event_trap_key(struct ocelot_vcap_filter *trap)
1434 trap->key_type = OCELOT_VCAP_KEY_IPV4;
1435 trap->key.ipv4.proto.value[0] = IPPROTO_UDP;
1436 trap->key.ipv4.proto.mask[0] = 0xff;
1437 trap->key.ipv4.dport.value = PTP_EV_PORT;
1438 trap->key.ipv4.dport.mask = 0xffff;
1442 ocelot_populate_ipv6_ptp_event_trap_key(struct ocelot_vcap_filter *trap)
1444 trap->key_type = OCELOT_VCAP_KEY_IPV6;
1445 trap->key.ipv4.proto.value[0] = IPPROTO_UDP;
1446 trap->key.ipv4.proto.mask[0] = 0xff;
1447 trap->key.ipv6.dport.value = PTP_EV_PORT;
1448 trap->key.ipv6.dport.mask = 0xffff;
1452 ocelot_populate_ipv4_ptp_general_trap_key(struct ocelot_vcap_filter *trap)
1454 trap->key_type = OCELOT_VCAP_KEY_IPV4;
1455 trap->key.ipv4.proto.value[0] = IPPROTO_UDP;
1456 trap->key.ipv4.proto.mask[0] = 0xff;
1457 trap->key.ipv4.dport.value = PTP_GEN_PORT;
1458 trap->key.ipv4.dport.mask = 0xffff;
1462 ocelot_populate_ipv6_ptp_general_trap_key(struct ocelot_vcap_filter *trap)
1464 trap->key_type = OCELOT_VCAP_KEY_IPV6;
1465 trap->key.ipv4.proto.value[0] = IPPROTO_UDP;
1466 trap->key.ipv4.proto.mask[0] = 0xff;
1467 trap->key.ipv6.dport.value = PTP_GEN_PORT;
1468 trap->key.ipv6.dport.mask = 0xffff;
1471 static int ocelot_trap_add(struct ocelot *ocelot, int port,
1472 unsigned long cookie,
1473 void (*populate)(struct ocelot_vcap_filter *f))
1475 struct ocelot_vcap_block *block_vcap_is2;
1476 struct ocelot_vcap_filter *trap;
1480 block_vcap_is2 = &ocelot->block[VCAP_IS2];
1482 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie,
1485 trap = kzalloc(sizeof(*trap), GFP_KERNEL);
1491 trap->id.cookie = cookie;
1492 trap->id.tc_offload = false;
1493 trap->block_id = VCAP_IS2;
1494 trap->type = OCELOT_VCAP_FILTER_OFFLOAD;
1496 trap->action.cpu_copy_ena = true;
1497 trap->action.mask_mode = OCELOT_MASK_MODE_PERMIT_DENY;
1498 trap->action.port_mask = 0;
1502 trap->ingress_port_mask |= BIT(port);
1505 err = ocelot_vcap_filter_add(ocelot, trap, NULL);
1507 err = ocelot_vcap_filter_replace(ocelot, trap);
1509 trap->ingress_port_mask &= ~BIT(port);
1510 if (!trap->ingress_port_mask)
1518 static int ocelot_trap_del(struct ocelot *ocelot, int port,
1519 unsigned long cookie)
1521 struct ocelot_vcap_block *block_vcap_is2;
1522 struct ocelot_vcap_filter *trap;
1524 block_vcap_is2 = &ocelot->block[VCAP_IS2];
1526 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie,
1531 trap->ingress_port_mask &= ~BIT(port);
1532 if (!trap->ingress_port_mask)
1533 return ocelot_vcap_filter_del(ocelot, trap);
1535 return ocelot_vcap_filter_replace(ocelot, trap);
1538 static int ocelot_l2_ptp_trap_add(struct ocelot *ocelot, int port)
1540 unsigned long l2_cookie = ocelot->num_phys_ports + 1;
1542 return ocelot_trap_add(ocelot, port, l2_cookie,
1543 ocelot_populate_l2_ptp_trap_key);
1546 static int ocelot_l2_ptp_trap_del(struct ocelot *ocelot, int port)
1548 unsigned long l2_cookie = ocelot->num_phys_ports + 1;
1550 return ocelot_trap_del(ocelot, port, l2_cookie);
1553 static int ocelot_ipv4_ptp_trap_add(struct ocelot *ocelot, int port)
1555 unsigned long ipv4_gen_cookie = ocelot->num_phys_ports + 2;
1556 unsigned long ipv4_ev_cookie = ocelot->num_phys_ports + 3;
1559 err = ocelot_trap_add(ocelot, port, ipv4_ev_cookie,
1560 ocelot_populate_ipv4_ptp_event_trap_key);
1564 err = ocelot_trap_add(ocelot, port, ipv4_gen_cookie,
1565 ocelot_populate_ipv4_ptp_general_trap_key);
1567 ocelot_trap_del(ocelot, port, ipv4_ev_cookie);
1572 static int ocelot_ipv4_ptp_trap_del(struct ocelot *ocelot, int port)
1574 unsigned long ipv4_gen_cookie = ocelot->num_phys_ports + 2;
1575 unsigned long ipv4_ev_cookie = ocelot->num_phys_ports + 3;
1578 err = ocelot_trap_del(ocelot, port, ipv4_ev_cookie);
1579 err |= ocelot_trap_del(ocelot, port, ipv4_gen_cookie);
1583 static int ocelot_ipv6_ptp_trap_add(struct ocelot *ocelot, int port)
1585 unsigned long ipv6_gen_cookie = ocelot->num_phys_ports + 4;
1586 unsigned long ipv6_ev_cookie = ocelot->num_phys_ports + 5;
1589 err = ocelot_trap_add(ocelot, port, ipv6_ev_cookie,
1590 ocelot_populate_ipv6_ptp_event_trap_key);
1594 err = ocelot_trap_add(ocelot, port, ipv6_gen_cookie,
1595 ocelot_populate_ipv6_ptp_general_trap_key);
1597 ocelot_trap_del(ocelot, port, ipv6_ev_cookie);
1602 static int ocelot_ipv6_ptp_trap_del(struct ocelot *ocelot, int port)
1604 unsigned long ipv6_gen_cookie = ocelot->num_phys_ports + 4;
1605 unsigned long ipv6_ev_cookie = ocelot->num_phys_ports + 5;
1608 err = ocelot_trap_del(ocelot, port, ipv6_ev_cookie);
1609 err |= ocelot_trap_del(ocelot, port, ipv6_gen_cookie);
1613 static int ocelot_setup_ptp_traps(struct ocelot *ocelot, int port,
1619 err = ocelot_l2_ptp_trap_add(ocelot, port);
1621 err = ocelot_l2_ptp_trap_del(ocelot, port);
1626 err = ocelot_ipv4_ptp_trap_add(ocelot, port);
1630 err = ocelot_ipv6_ptp_trap_add(ocelot, port);
1634 err = ocelot_ipv4_ptp_trap_del(ocelot, port);
1636 err |= ocelot_ipv6_ptp_trap_del(ocelot, port);
1644 ocelot_ipv4_ptp_trap_del(ocelot, port);
1647 ocelot_l2_ptp_trap_del(ocelot, port);
1651 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr)
1653 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config,
1654 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0;
1656 EXPORT_SYMBOL(ocelot_hwstamp_get);
1658 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr)
1660 struct ocelot_port *ocelot_port = ocelot->ports[port];
1661 bool l2 = false, l4 = false;
1662 struct hwtstamp_config cfg;
1665 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1668 /* Tx type sanity check */
1669 switch (cfg.tx_type) {
1670 case HWTSTAMP_TX_ON:
1671 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP;
1673 case HWTSTAMP_TX_ONESTEP_SYNC:
1674 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we
1675 * need to update the origin time.
1677 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP;
1679 case HWTSTAMP_TX_OFF:
1680 ocelot_port->ptp_cmd = 0;
1686 mutex_lock(&ocelot->ptp_lock);
1688 switch (cfg.rx_filter) {
1689 case HWTSTAMP_FILTER_NONE:
1691 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1692 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1693 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1696 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1697 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1698 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1701 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1702 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1703 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1708 mutex_unlock(&ocelot->ptp_lock);
1712 err = ocelot_setup_ptp_traps(ocelot, port, l2, l4);
1714 mutex_unlock(&ocelot->ptp_lock);
1719 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1721 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1723 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
1725 cfg.rx_filter = HWTSTAMP_FILTER_NONE;
1727 /* Commit back the result & save it */
1728 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg));
1729 mutex_unlock(&ocelot->ptp_lock);
1731 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1733 EXPORT_SYMBOL(ocelot_hwstamp_set);
1735 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data)
1739 if (sset != ETH_SS_STATS)
1742 for (i = 0; i < ocelot->num_stats; i++)
1743 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name,
1746 EXPORT_SYMBOL(ocelot_get_strings);
1748 /* Caller must hold &ocelot->stats_lock */
1749 static void ocelot_update_stats(struct ocelot *ocelot)
1753 for (i = 0; i < ocelot->num_phys_ports; i++) {
1754 /* Configure the port to read the stats from */
1755 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG);
1757 for (j = 0; j < ocelot->num_stats; j++) {
1759 unsigned int idx = i * ocelot->num_stats + j;
1761 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS,
1762 ocelot->stats_layout[j].offset);
1764 if (val < (ocelot->stats[idx] & U32_MAX))
1765 ocelot->stats[idx] += (u64)1 << 32;
1767 ocelot->stats[idx] = (ocelot->stats[idx] &
1768 ~(u64)U32_MAX) + val;
1773 static void ocelot_check_stats_work(struct work_struct *work)
1775 struct delayed_work *del_work = to_delayed_work(work);
1776 struct ocelot *ocelot = container_of(del_work, struct ocelot,
1779 mutex_lock(&ocelot->stats_lock);
1780 ocelot_update_stats(ocelot);
1781 mutex_unlock(&ocelot->stats_lock);
1783 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
1784 OCELOT_STATS_CHECK_DELAY);
1787 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data)
1791 mutex_lock(&ocelot->stats_lock);
1793 /* check and update now */
1794 ocelot_update_stats(ocelot);
1796 /* Copy all counters */
1797 for (i = 0; i < ocelot->num_stats; i++)
1798 *data++ = ocelot->stats[port * ocelot->num_stats + i];
1800 mutex_unlock(&ocelot->stats_lock);
1802 EXPORT_SYMBOL(ocelot_get_ethtool_stats);
1804 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset)
1806 if (sset != ETH_SS_STATS)
1809 return ocelot->num_stats;
1811 EXPORT_SYMBOL(ocelot_get_sset_count);
1813 int ocelot_get_ts_info(struct ocelot *ocelot, int port,
1814 struct ethtool_ts_info *info)
1816 info->phc_index = ocelot->ptp_clock ?
1817 ptp_clock_index(ocelot->ptp_clock) : -1;
1818 if (info->phc_index == -1) {
1819 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
1820 SOF_TIMESTAMPING_RX_SOFTWARE |
1821 SOF_TIMESTAMPING_SOFTWARE;
1824 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
1825 SOF_TIMESTAMPING_RX_SOFTWARE |
1826 SOF_TIMESTAMPING_SOFTWARE |
1827 SOF_TIMESTAMPING_TX_HARDWARE |
1828 SOF_TIMESTAMPING_RX_HARDWARE |
1829 SOF_TIMESTAMPING_RAW_HARDWARE;
1830 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) |
1831 BIT(HWTSTAMP_TX_ONESTEP_SYNC);
1832 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1833 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) |
1834 BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1835 BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
1839 EXPORT_SYMBOL(ocelot_get_ts_info);
1841 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond)
1846 for (port = 0; port < ocelot->num_phys_ports; port++) {
1847 struct ocelot_port *ocelot_port = ocelot->ports[port];
1852 if (ocelot_port->bond == bond)
1859 u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port)
1861 struct ocelot_port *ocelot_port = ocelot->ports[src_port];
1862 const struct net_device *bridge;
1866 if (!ocelot_port || ocelot_port->stp_state != BR_STATE_FORWARDING)
1869 bridge = ocelot_port->bridge;
1873 for (port = 0; port < ocelot->num_phys_ports; port++) {
1874 ocelot_port = ocelot->ports[port];
1879 if (ocelot_port->stp_state == BR_STATE_FORWARDING &&
1880 ocelot_port->bridge == bridge)
1886 EXPORT_SYMBOL_GPL(ocelot_get_bridge_fwd_mask);
1888 u32 ocelot_get_dsa_8021q_cpu_mask(struct ocelot *ocelot)
1893 for (port = 0; port < ocelot->num_phys_ports; port++) {
1894 struct ocelot_port *ocelot_port = ocelot->ports[port];
1899 if (ocelot_port->is_dsa_8021q_cpu)
1905 EXPORT_SYMBOL_GPL(ocelot_get_dsa_8021q_cpu_mask);
1907 void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining)
1909 unsigned long cpu_fwd_mask;
1912 lockdep_assert_held(&ocelot->fwd_domain_lock);
1914 /* If cut-through forwarding is supported, update the masks before a
1915 * port joins the forwarding domain, to avoid potential underruns if it
1916 * has the highest speed from the new domain.
1918 if (joining && ocelot->ops->cut_through_fwd)
1919 ocelot->ops->cut_through_fwd(ocelot);
1921 /* If a DSA tag_8021q CPU exists, it needs to be included in the
1922 * regular forwarding path of the front ports regardless of whether
1923 * those are bridged or standalone.
1924 * If DSA tag_8021q is not used, this returns 0, which is fine because
1925 * the hardware-based CPU port module can be a destination for packets
1926 * even if it isn't part of PGID_SRC.
1928 cpu_fwd_mask = ocelot_get_dsa_8021q_cpu_mask(ocelot);
1930 /* Apply FWD mask. The loop is needed to add/remove the current port as
1931 * a source for the other ports.
1933 for (port = 0; port < ocelot->num_phys_ports; port++) {
1934 struct ocelot_port *ocelot_port = ocelot->ports[port];
1938 /* Unused ports can't send anywhere */
1940 } else if (ocelot_port->is_dsa_8021q_cpu) {
1941 /* The DSA tag_8021q CPU ports need to be able to
1942 * forward packets to all other ports except for
1945 mask = GENMASK(ocelot->num_phys_ports - 1, 0);
1946 mask &= ~cpu_fwd_mask;
1947 } else if (ocelot_port->bridge) {
1948 struct net_device *bond = ocelot_port->bond;
1950 mask = ocelot_get_bridge_fwd_mask(ocelot, port);
1951 mask |= cpu_fwd_mask;
1954 mask &= ~ocelot_get_bond_mask(ocelot, bond);
1956 /* Standalone ports forward only to DSA tag_8021q CPU
1957 * ports (if those exist), or to the hardware CPU port
1960 mask = cpu_fwd_mask;
1963 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port);
1966 /* If cut-through forwarding is supported and a port is leaving, there
1967 * is a chance that cut-through was disabled on the other ports due to
1968 * the port which is leaving (it has a higher link speed). We need to
1969 * update the cut-through masks of the remaining ports no earlier than
1970 * after the port has left, to prevent underruns from happening between
1971 * the cut-through update and the forwarding domain update.
1973 if (!joining && ocelot->ops->cut_through_fwd)
1974 ocelot->ops->cut_through_fwd(ocelot);
1976 EXPORT_SYMBOL(ocelot_apply_bridge_fwd_mask);
1978 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
1980 struct ocelot_port *ocelot_port = ocelot->ports[port];
1983 mutex_lock(&ocelot->fwd_domain_lock);
1985 ocelot_port->stp_state = state;
1987 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) &&
1988 ocelot_port->learn_ena)
1989 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA;
1991 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA,
1992 ANA_PORT_PORT_CFG, port);
1994 ocelot_apply_bridge_fwd_mask(ocelot, state == BR_STATE_FORWARDING);
1996 mutex_unlock(&ocelot->fwd_domain_lock);
1998 EXPORT_SYMBOL(ocelot_bridge_stp_state_set);
2000 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
2002 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000);
2004 /* Setting AGE_PERIOD to zero effectively disables automatic aging,
2005 * which is clearly not what our intention is. So avoid that.
2010 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE);
2012 EXPORT_SYMBOL(ocelot_set_ageing_time);
2014 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot,
2015 const unsigned char *addr,
2018 struct ocelot_multicast *mc;
2020 list_for_each_entry(mc, &ocelot->multicast, list) {
2021 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid)
2028 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr)
2030 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e)
2031 return ENTRYTYPE_MACv4;
2032 if (addr[0] == 0x33 && addr[1] == 0x33)
2033 return ENTRYTYPE_MACv6;
2034 return ENTRYTYPE_LOCKED;
2037 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index,
2038 unsigned long ports)
2040 struct ocelot_pgid *pgid;
2042 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL);
2044 return ERR_PTR(-ENOMEM);
2046 pgid->ports = ports;
2047 pgid->index = index;
2048 refcount_set(&pgid->refcount, 1);
2049 list_add_tail(&pgid->list, &ocelot->pgids);
2054 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid)
2056 if (!refcount_dec_and_test(&pgid->refcount))
2059 list_del(&pgid->list);
2063 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot,
2064 const struct ocelot_multicast *mc)
2066 struct ocelot_pgid *pgid;
2069 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and
2070 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the
2071 * destination mask table (PGID), the destination set is programmed as
2072 * part of the entry MAC address.", and the DEST_IDX is set to 0.
2074 if (mc->entry_type == ENTRYTYPE_MACv4 ||
2075 mc->entry_type == ENTRYTYPE_MACv6)
2076 return ocelot_pgid_alloc(ocelot, 0, mc->ports);
2078 list_for_each_entry(pgid, &ocelot->pgids, list) {
2079 /* When searching for a nonreserved multicast PGID, ignore the
2080 * dummy PGID of zero that we have for MACv4/MACv6 entries
2082 if (pgid->index && pgid->ports == mc->ports) {
2083 refcount_inc(&pgid->refcount);
2088 /* Search for a free index in the nonreserved multicast PGID area */
2089 for_each_nonreserved_multicast_dest_pgid(ocelot, index) {
2092 list_for_each_entry(pgid, &ocelot->pgids, list) {
2093 if (pgid->index == index) {
2100 return ocelot_pgid_alloc(ocelot, index, mc->ports);
2103 return ERR_PTR(-ENOSPC);
2106 static void ocelot_encode_ports_to_mdb(unsigned char *addr,
2107 struct ocelot_multicast *mc)
2109 ether_addr_copy(addr, mc->addr);
2111 if (mc->entry_type == ENTRYTYPE_MACv4) {
2113 addr[1] = mc->ports >> 8;
2114 addr[2] = mc->ports & 0xff;
2115 } else if (mc->entry_type == ENTRYTYPE_MACv6) {
2116 addr[0] = mc->ports >> 8;
2117 addr[1] = mc->ports & 0xff;
2121 int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
2122 const struct switchdev_obj_port_mdb *mdb)
2124 unsigned char addr[ETH_ALEN];
2125 struct ocelot_multicast *mc;
2126 struct ocelot_pgid *pgid;
2129 if (port == ocelot->npi)
2130 port = ocelot->num_phys_ports;
2132 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
2135 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL);
2139 mc->entry_type = ocelot_classify_mdb(mdb->addr);
2140 ether_addr_copy(mc->addr, mdb->addr);
2143 list_add_tail(&mc->list, &ocelot->multicast);
2145 /* Existing entry. Clean up the current port mask from
2146 * hardware now, because we'll be modifying it.
2148 ocelot_pgid_free(ocelot, mc->pgid);
2149 ocelot_encode_ports_to_mdb(addr, mc);
2150 ocelot_mact_forget(ocelot, addr, vid);
2153 mc->ports |= BIT(port);
2155 pgid = ocelot_mdb_get_pgid(ocelot, mc);
2157 dev_err(ocelot->dev,
2158 "Cannot allocate PGID for mdb %pM vid %d\n",
2160 devm_kfree(ocelot->dev, mc);
2161 return PTR_ERR(pgid);
2165 ocelot_encode_ports_to_mdb(addr, mc);
2167 if (mc->entry_type != ENTRYTYPE_MACv4 &&
2168 mc->entry_type != ENTRYTYPE_MACv6)
2169 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
2172 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
2175 EXPORT_SYMBOL(ocelot_port_mdb_add);
2177 int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
2178 const struct switchdev_obj_port_mdb *mdb)
2180 unsigned char addr[ETH_ALEN];
2181 struct ocelot_multicast *mc;
2182 struct ocelot_pgid *pgid;
2185 if (port == ocelot->npi)
2186 port = ocelot->num_phys_ports;
2188 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
2192 ocelot_encode_ports_to_mdb(addr, mc);
2193 ocelot_mact_forget(ocelot, addr, vid);
2195 ocelot_pgid_free(ocelot, mc->pgid);
2196 mc->ports &= ~BIT(port);
2198 list_del(&mc->list);
2199 devm_kfree(ocelot->dev, mc);
2203 /* We have a PGID with fewer ports now */
2204 pgid = ocelot_mdb_get_pgid(ocelot, mc);
2206 return PTR_ERR(pgid);
2209 ocelot_encode_ports_to_mdb(addr, mc);
2211 if (mc->entry_type != ENTRYTYPE_MACv4 &&
2212 mc->entry_type != ENTRYTYPE_MACv6)
2213 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
2216 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
2219 EXPORT_SYMBOL(ocelot_port_mdb_del);
2221 void ocelot_port_bridge_join(struct ocelot *ocelot, int port,
2222 struct net_device *bridge)
2224 struct ocelot_port *ocelot_port = ocelot->ports[port];
2226 mutex_lock(&ocelot->fwd_domain_lock);
2228 ocelot_port->bridge = bridge;
2230 ocelot_apply_bridge_fwd_mask(ocelot, true);
2232 mutex_unlock(&ocelot->fwd_domain_lock);
2234 EXPORT_SYMBOL(ocelot_port_bridge_join);
2236 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
2237 struct net_device *bridge)
2239 struct ocelot_port *ocelot_port = ocelot->ports[port];
2241 mutex_lock(&ocelot->fwd_domain_lock);
2243 ocelot_port->bridge = NULL;
2245 ocelot_port_set_pvid(ocelot, port, NULL);
2246 ocelot_port_manage_port_tag(ocelot, port);
2247 ocelot_apply_bridge_fwd_mask(ocelot, false);
2249 mutex_unlock(&ocelot->fwd_domain_lock);
2251 EXPORT_SYMBOL(ocelot_port_bridge_leave);
2253 static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
2255 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0);
2258 /* Reset destination and aggregation PGIDS */
2259 for_each_unicast_dest_pgid(ocelot, port)
2260 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
2262 for_each_aggr_pgid(ocelot, i)
2263 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
2266 /* The visited ports bitmask holds the list of ports offloading any
2267 * bonding interface. Initially we mark all these ports as unvisited,
2268 * then every time we visit a port in this bitmask, we know that it is
2269 * the lowest numbered port, i.e. the one whose logical ID == physical
2270 * port ID == LAG ID. So we mark as visited all further ports in the
2271 * bitmask that are offloading the same bonding interface. This way,
2272 * we set up the aggregation PGIDs only once per bonding interface.
2274 for (port = 0; port < ocelot->num_phys_ports; port++) {
2275 struct ocelot_port *ocelot_port = ocelot->ports[port];
2277 if (!ocelot_port || !ocelot_port->bond)
2280 visited &= ~BIT(port);
2283 /* Now, set PGIDs for each active LAG */
2284 for (lag = 0; lag < ocelot->num_phys_ports; lag++) {
2285 struct net_device *bond = ocelot->ports[lag]->bond;
2286 int num_active_ports = 0;
2287 unsigned long bond_mask;
2290 if (!bond || (visited & BIT(lag)))
2293 bond_mask = ocelot_get_bond_mask(ocelot, bond);
2295 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) {
2296 struct ocelot_port *ocelot_port = ocelot->ports[port];
2299 ocelot_write_rix(ocelot, bond_mask,
2300 ANA_PGID_PGID, port);
2302 if (ocelot_port->lag_tx_active)
2303 aggr_idx[num_active_ports++] = port;
2306 for_each_aggr_pgid(ocelot, i) {
2309 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i);
2311 /* Don't do division by zero if there was no active
2312 * port. Just make all aggregation codes zero.
2314 if (num_active_ports)
2315 ac |= BIT(aggr_idx[i % num_active_ports]);
2316 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i);
2319 /* Mark all ports in the same LAG as visited to avoid applying
2320 * the same config again.
2322 for (port = lag; port < ocelot->num_phys_ports; port++) {
2323 struct ocelot_port *ocelot_port = ocelot->ports[port];
2328 if (ocelot_port->bond == bond)
2329 visited |= BIT(port);
2334 /* When offloading a bonding interface, the switch ports configured under the
2335 * same bond must have the same logical port ID, equal to the physical port ID
2336 * of the lowest numbered physical port in that bond. Otherwise, in standalone/
2337 * bridged mode, each port has a logical port ID equal to its physical port ID.
2339 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot)
2343 for (port = 0; port < ocelot->num_phys_ports; port++) {
2344 struct ocelot_port *ocelot_port = ocelot->ports[port];
2345 struct net_device *bond;
2350 bond = ocelot_port->bond;
2352 int lag = __ffs(ocelot_get_bond_mask(ocelot, bond));
2354 ocelot_rmw_gix(ocelot,
2355 ANA_PORT_PORT_CFG_PORTID_VAL(lag),
2356 ANA_PORT_PORT_CFG_PORTID_VAL_M,
2357 ANA_PORT_PORT_CFG, port);
2359 ocelot_rmw_gix(ocelot,
2360 ANA_PORT_PORT_CFG_PORTID_VAL(port),
2361 ANA_PORT_PORT_CFG_PORTID_VAL_M,
2362 ANA_PORT_PORT_CFG, port);
2367 int ocelot_port_lag_join(struct ocelot *ocelot, int port,
2368 struct net_device *bond,
2369 struct netdev_lag_upper_info *info)
2371 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
2374 mutex_lock(&ocelot->fwd_domain_lock);
2376 ocelot->ports[port]->bond = bond;
2378 ocelot_setup_logical_port_ids(ocelot);
2379 ocelot_apply_bridge_fwd_mask(ocelot, true);
2380 ocelot_set_aggr_pgids(ocelot);
2382 mutex_unlock(&ocelot->fwd_domain_lock);
2386 EXPORT_SYMBOL(ocelot_port_lag_join);
2388 void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
2389 struct net_device *bond)
2391 mutex_lock(&ocelot->fwd_domain_lock);
2393 ocelot->ports[port]->bond = NULL;
2395 ocelot_setup_logical_port_ids(ocelot);
2396 ocelot_apply_bridge_fwd_mask(ocelot, false);
2397 ocelot_set_aggr_pgids(ocelot);
2399 mutex_unlock(&ocelot->fwd_domain_lock);
2401 EXPORT_SYMBOL(ocelot_port_lag_leave);
2403 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active)
2405 struct ocelot_port *ocelot_port = ocelot->ports[port];
2407 ocelot_port->lag_tx_active = lag_tx_active;
2409 /* Rebalance the LAGs */
2410 ocelot_set_aggr_pgids(ocelot);
2412 EXPORT_SYMBOL(ocelot_port_lag_change);
2414 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu.
2415 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG.
2416 * In the special case that it's the NPI port that we're configuring, the
2417 * length of the tag and optional prefix needs to be accounted for privately,
2418 * in order to be able to sustain communication at the requested @sdu.
2420 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu)
2422 struct ocelot_port *ocelot_port = ocelot->ports[port];
2423 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN;
2424 int pause_start, pause_stop;
2427 if (port == ocelot->npi) {
2428 maxlen += OCELOT_TAG_LEN;
2430 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
2431 maxlen += OCELOT_SHORT_PREFIX_LEN;
2432 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
2433 maxlen += OCELOT_LONG_PREFIX_LEN;
2436 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG);
2438 /* Set Pause watermark hysteresis */
2439 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ;
2440 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ;
2441 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START,
2443 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP,
2446 /* Tail dropping watermarks */
2447 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) /
2448 OCELOT_BUFFER_CELL_SZ;
2449 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ;
2450 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port);
2451 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG);
2453 EXPORT_SYMBOL(ocelot_port_set_maxlen);
2455 int ocelot_get_max_mtu(struct ocelot *ocelot, int port)
2457 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN;
2459 if (port == ocelot->npi) {
2460 max_mtu -= OCELOT_TAG_LEN;
2462 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
2463 max_mtu -= OCELOT_SHORT_PREFIX_LEN;
2464 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
2465 max_mtu -= OCELOT_LONG_PREFIX_LEN;
2470 EXPORT_SYMBOL(ocelot_get_max_mtu);
2472 static void ocelot_port_set_learning(struct ocelot *ocelot, int port,
2475 struct ocelot_port *ocelot_port = ocelot->ports[port];
2479 val = ANA_PORT_PORT_CFG_LEARN_ENA;
2481 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA,
2482 ANA_PORT_PORT_CFG, port);
2484 ocelot_port->learn_ena = enabled;
2487 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port,
2495 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC);
2498 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port,
2506 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC);
2509 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port,
2517 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC);
2520 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port,
2521 struct switchdev_brport_flags flags)
2523 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
2529 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags);
2531 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port,
2532 struct switchdev_brport_flags flags)
2534 if (flags.mask & BR_LEARNING)
2535 ocelot_port_set_learning(ocelot, port,
2536 !!(flags.val & BR_LEARNING));
2538 if (flags.mask & BR_FLOOD)
2539 ocelot_port_set_ucast_flood(ocelot, port,
2540 !!(flags.val & BR_FLOOD));
2542 if (flags.mask & BR_MCAST_FLOOD)
2543 ocelot_port_set_mcast_flood(ocelot, port,
2544 !!(flags.val & BR_MCAST_FLOOD));
2546 if (flags.mask & BR_BCAST_FLOOD)
2547 ocelot_port_set_bcast_flood(ocelot, port,
2548 !!(flags.val & BR_BCAST_FLOOD));
2550 EXPORT_SYMBOL(ocelot_port_bridge_flags);
2552 void ocelot_init_port(struct ocelot *ocelot, int port)
2554 struct ocelot_port *ocelot_port = ocelot->ports[port];
2556 skb_queue_head_init(&ocelot_port->tx_skbs);
2558 /* Basic L2 initialization */
2561 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
2562 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
2564 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5),
2567 /* Load seed (0) and set MAC HDX late collision */
2568 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
2569 DEV_MAC_HDX_CFG_SEED_LOAD,
2572 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
2575 /* Set Max Length and maximum tags allowed */
2576 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN);
2577 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
2578 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
2579 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA |
2580 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
2583 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
2584 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
2585 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
2587 /* Enable transmission of pause frames */
2588 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1);
2590 /* Drop frames with multicast source address */
2591 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
2592 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
2593 ANA_PORT_DROP_CFG, port);
2595 /* Set default VLAN and tag type to 8021Q. */
2596 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q),
2597 REW_PORT_VLAN_CFG_PORT_TPID_M,
2598 REW_PORT_VLAN_CFG, port);
2600 /* Disable source address learning for standalone mode */
2601 ocelot_port_set_learning(ocelot, port, false);
2603 /* Set the port's initial logical port ID value, enable receiving
2604 * frames on it, and configure the MAC address learning type to
2607 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
2608 ANA_PORT_PORT_CFG_RECV_ENA |
2609 ANA_PORT_PORT_CFG_PORTID_VAL(port),
2610 ANA_PORT_PORT_CFG, port);
2612 /* Enable vcap lookups */
2613 ocelot_vcap_enable(ocelot, port);
2615 EXPORT_SYMBOL(ocelot_init_port);
2617 /* Configure and enable the CPU port module, which is a set of queues
2618 * accessible through register MMIO, frame DMA or Ethernet (in case
2619 * NPI mode is used).
2621 static void ocelot_cpu_port_init(struct ocelot *ocelot)
2623 int cpu = ocelot->num_phys_ports;
2625 /* The unicast destination PGID for the CPU port module is unused */
2626 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
2627 /* Instead set up a multicast destination PGID for traffic copied to
2628 * the CPU. Whitelisted MAC addresses like the port netdevice MAC
2629 * addresses will be copied to the CPU via this PGID.
2631 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
2632 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
2633 ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
2634 ANA_PORT_PORT_CFG, cpu);
2636 /* Enable CPU port module */
2637 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
2638 /* CPU port Injection/Extraction configuration */
2639 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR,
2640 OCELOT_TAG_PREFIX_NONE);
2641 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR,
2642 OCELOT_TAG_PREFIX_NONE);
2644 /* Configure the CPU port to be VLAN aware */
2645 ocelot_write_gix(ocelot,
2646 ANA_PORT_VLAN_CFG_VLAN_VID(OCELOT_VLAN_UNAWARE_PVID) |
2647 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
2648 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
2649 ANA_PORT_VLAN_CFG, cpu);
2652 static void ocelot_detect_features(struct ocelot *ocelot)
2656 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds
2657 * the number of 240-byte free memory words (aka 4-cell chunks) and not
2658 * 192 bytes as the documentation incorrectly says.
2660 mmgt = ocelot_read(ocelot, SYS_MMGT);
2661 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt);
2663 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL);
2664 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl);
2667 int ocelot_init(struct ocelot *ocelot)
2669 char queue_name[32];
2673 if (ocelot->ops->reset) {
2674 ret = ocelot->ops->reset(ocelot);
2676 dev_err(ocelot->dev, "Switch reset failed\n");
2681 ocelot->stats = devm_kcalloc(ocelot->dev,
2682 ocelot->num_phys_ports * ocelot->num_stats,
2683 sizeof(u64), GFP_KERNEL);
2687 mutex_init(&ocelot->stats_lock);
2688 mutex_init(&ocelot->ptp_lock);
2689 mutex_init(&ocelot->mact_lock);
2690 mutex_init(&ocelot->fwd_domain_lock);
2691 spin_lock_init(&ocelot->ptp_clock_lock);
2692 spin_lock_init(&ocelot->ts_id_lock);
2693 snprintf(queue_name, sizeof(queue_name), "%s-stats",
2694 dev_name(ocelot->dev));
2695 ocelot->stats_queue = create_singlethread_workqueue(queue_name);
2696 if (!ocelot->stats_queue)
2699 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0);
2701 destroy_workqueue(ocelot->stats_queue);
2705 INIT_LIST_HEAD(&ocelot->multicast);
2706 INIT_LIST_HEAD(&ocelot->pgids);
2707 INIT_LIST_HEAD(&ocelot->vlans);
2708 ocelot_detect_features(ocelot);
2709 ocelot_mact_init(ocelot);
2710 ocelot_vlan_init(ocelot);
2711 ocelot_vcap_init(ocelot);
2712 ocelot_cpu_port_init(ocelot);
2714 if (ocelot->ops->psfp_init)
2715 ocelot->ops->psfp_init(ocelot);
2717 for (port = 0; port < ocelot->num_phys_ports; port++) {
2718 /* Clear all counters (5 groups) */
2719 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
2720 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
2724 /* Only use S-Tag */
2725 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG);
2727 /* Aggregation mode */
2728 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA |
2729 ANA_AGGR_CFG_AC_DMAC_ENA |
2730 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA |
2731 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA |
2732 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA |
2733 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA,
2736 /* Set MAC age time to default value. The entry is aged after
2739 ocelot_write(ocelot,
2740 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ),
2743 /* Disable learning for frames discarded by VLAN ingress filtering */
2744 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1);
2746 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
2747 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA |
2748 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING);
2750 /* Setup flooding PGIDs */
2751 for (i = 0; i < ocelot->num_flooding_pgids; i++)
2752 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
2753 ANA_FLOODING_FLD_BROADCAST(PGID_BC) |
2754 ANA_FLOODING_FLD_UNICAST(PGID_UC),
2756 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) |
2757 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) |
2758 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) |
2759 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC),
2762 for (port = 0; port < ocelot->num_phys_ports; port++) {
2763 /* Transmit the frame to the local port. */
2764 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
2765 /* Do not forward BPDU frames to the front ports. */
2766 ocelot_write_gix(ocelot,
2767 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
2768 ANA_PORT_CPU_FWD_BPDU_CFG,
2770 /* Ensure bridging is disabled */
2771 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
2774 for_each_nonreserved_multicast_dest_pgid(ocelot, i) {
2775 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
2777 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
2780 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE);
2782 /* Allow broadcast and unknown L2 multicast to the CPU. */
2783 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2784 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2785 ANA_PGID_PGID, PGID_MC);
2786 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2787 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2788 ANA_PGID_PGID, PGID_BC);
2789 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
2790 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
2792 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
2793 * registers endianness.
2795 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
2796 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);
2797 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP |
2798 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0);
2799 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |
2800 ANA_CPUQ_CFG_CPUQ_LRN(2) |
2801 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) |
2802 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) |
2803 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) |
2804 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) |
2805 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) |
2806 ANA_CPUQ_CFG_CPUQ_IGMP(6) |
2807 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG);
2808 for (i = 0; i < 16; i++)
2809 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) |
2810 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6),
2811 ANA_CPUQ_8021_CFG, i);
2813 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work);
2814 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
2815 OCELOT_STATS_CHECK_DELAY);
2819 EXPORT_SYMBOL(ocelot_init);
2821 void ocelot_deinit(struct ocelot *ocelot)
2823 cancel_delayed_work(&ocelot->stats_work);
2824 destroy_workqueue(ocelot->stats_queue);
2825 destroy_workqueue(ocelot->owq);
2826 mutex_destroy(&ocelot->stats_lock);
2828 EXPORT_SYMBOL(ocelot_deinit);
2830 void ocelot_deinit_port(struct ocelot *ocelot, int port)
2832 struct ocelot_port *ocelot_port = ocelot->ports[port];
2834 skb_queue_purge(&ocelot_port->tx_skbs);
2836 EXPORT_SYMBOL(ocelot_deinit_port);
2838 MODULE_LICENSE("Dual MIT/GPL");