drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c

   1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
   2 /* Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. */
   3
   4 #include <linux/types.h>
   5 #include "mlx5_ifc_dr_ste_v1.h"
   6 #include "dr_ste.h"
   7
   8 #define DR_STE_CALC_DFNR_TYPE(lookup_type, inner) \
   9         ((inner) ? DR_STE_V1_LU_TYPE_##lookup_type##_I : \
  10                    DR_STE_V1_LU_TYPE_##lookup_type##_O)
  11
  12 enum dr_ste_v1_entry_format {
  13         DR_STE_V1_TYPE_BWC_BYTE = 0x0,
  14         DR_STE_V1_TYPE_BWC_DW   = 0x1,
  15         DR_STE_V1_TYPE_MATCH    = 0x2,
  16 };
  17
  18 /* Lookup type is built from 2B: [ Definer mode 1B ][ Definer index 1B ] */
  19 enum {
  20         DR_STE_V1_LU_TYPE_NOP                           = 0x0000,
  21         DR_STE_V1_LU_TYPE_ETHL2_TNL                     = 0x0002,
  22         DR_STE_V1_LU_TYPE_IBL3_EXT                      = 0x0102,
  23         DR_STE_V1_LU_TYPE_ETHL2_O                       = 0x0003,
  24         DR_STE_V1_LU_TYPE_IBL4                          = 0x0103,
  25         DR_STE_V1_LU_TYPE_ETHL2_I                       = 0x0004,
  26         DR_STE_V1_LU_TYPE_SRC_QP_GVMI                   = 0x0104,
  27         DR_STE_V1_LU_TYPE_ETHL2_SRC_O                   = 0x0005,
  28         DR_STE_V1_LU_TYPE_ETHL2_HEADERS_O               = 0x0105,
  29         DR_STE_V1_LU_TYPE_ETHL2_SRC_I                   = 0x0006,
  30         DR_STE_V1_LU_TYPE_ETHL2_HEADERS_I               = 0x0106,
  31         DR_STE_V1_LU_TYPE_ETHL3_IPV4_5_TUPLE_O          = 0x0007,
  32         DR_STE_V1_LU_TYPE_IPV6_DES_O                    = 0x0107,
  33         DR_STE_V1_LU_TYPE_ETHL3_IPV4_5_TUPLE_I          = 0x0008,
  34         DR_STE_V1_LU_TYPE_IPV6_DES_I                    = 0x0108,
  35         DR_STE_V1_LU_TYPE_ETHL4_O                       = 0x0009,
  36         DR_STE_V1_LU_TYPE_IPV6_SRC_O                    = 0x0109,
  37         DR_STE_V1_LU_TYPE_ETHL4_I                       = 0x000a,
  38         DR_STE_V1_LU_TYPE_IPV6_SRC_I                    = 0x010a,
  39         DR_STE_V1_LU_TYPE_ETHL2_SRC_DST_O               = 0x000b,
  40         DR_STE_V1_LU_TYPE_MPLS_O                        = 0x010b,
  41         DR_STE_V1_LU_TYPE_ETHL2_SRC_DST_I               = 0x000c,
  42         DR_STE_V1_LU_TYPE_MPLS_I                        = 0x010c,
  43         DR_STE_V1_LU_TYPE_ETHL3_IPV4_MISC_O             = 0x000d,
  44         DR_STE_V1_LU_TYPE_GRE                           = 0x010d,
  45         DR_STE_V1_LU_TYPE_FLEX_PARSER_TNL_HEADER        = 0x000e,
  46         DR_STE_V1_LU_TYPE_GENERAL_PURPOSE               = 0x010e,
  47         DR_STE_V1_LU_TYPE_ETHL3_IPV4_MISC_I             = 0x000f,
  48         DR_STE_V1_LU_TYPE_STEERING_REGISTERS_0          = 0x010f,
  49         DR_STE_V1_LU_TYPE_STEERING_REGISTERS_1          = 0x0110,
  50         DR_STE_V1_LU_TYPE_FLEX_PARSER_0                 = 0x0111,
  51         DR_STE_V1_LU_TYPE_FLEX_PARSER_1                 = 0x0112,
  52         DR_STE_V1_LU_TYPE_ETHL4_MISC_O                  = 0x0113,
  53         DR_STE_V1_LU_TYPE_ETHL4_MISC_I                  = 0x0114,
  54         DR_STE_V1_LU_TYPE_INVALID                       = 0x00ff,
  55         DR_STE_V1_LU_TYPE_DONT_CARE                     = MLX5DR_STE_LU_TYPE_DONT_CARE,
  56 };
  57
  58 enum dr_ste_v1_header_anchors {
  59         DR_STE_HEADER_ANCHOR_START_OUTER                = 0x00,
  60         DR_STE_HEADER_ANCHOR_1ST_VLAN                   = 0x02,
  61         DR_STE_HEADER_ANCHOR_IPV6_IPV4                  = 0x07,
  62         DR_STE_HEADER_ANCHOR_INNER_MAC                  = 0x13,
  63         DR_STE_HEADER_ANCHOR_INNER_IPV6_IPV4            = 0x19,
  64 };
  65
  66 enum dr_ste_v1_action_size {
  67         DR_STE_ACTION_SINGLE_SZ = 4,
  68         DR_STE_ACTION_DOUBLE_SZ = 8,
  69         DR_STE_ACTION_TRIPLE_SZ = 12,
  70 };
  71
  72 enum dr_ste_v1_action_insert_ptr_attr {
  73         DR_STE_V1_ACTION_INSERT_PTR_ATTR_NONE = 0,  /* Regular push header (e.g. push vlan) */
  74         DR_STE_V1_ACTION_INSERT_PTR_ATTR_ENCAP = 1, /* Encapsulation / Tunneling */
  75         DR_STE_V1_ACTION_INSERT_PTR_ATTR_ESP = 2,   /* IPsec */
  76 };
  77
  78 enum dr_ste_v1_action_id {
  79         DR_STE_V1_ACTION_ID_NOP                         = 0x00,
  80         DR_STE_V1_ACTION_ID_COPY                        = 0x05,
  81         DR_STE_V1_ACTION_ID_SET                         = 0x06,
  82         DR_STE_V1_ACTION_ID_ADD                         = 0x07,
  83         DR_STE_V1_ACTION_ID_REMOVE_BY_SIZE              = 0x08,
  84         DR_STE_V1_ACTION_ID_REMOVE_HEADER_TO_HEADER     = 0x09,
  85         DR_STE_V1_ACTION_ID_INSERT_INLINE               = 0x0a,
  86         DR_STE_V1_ACTION_ID_INSERT_POINTER              = 0x0b,
  87         DR_STE_V1_ACTION_ID_FLOW_TAG                    = 0x0c,
  88         DR_STE_V1_ACTION_ID_QUEUE_ID_SEL                = 0x0d,
  89         DR_STE_V1_ACTION_ID_ACCELERATED_LIST            = 0x0e,
  90         DR_STE_V1_ACTION_ID_MODIFY_LIST                 = 0x0f,
  91         DR_STE_V1_ACTION_ID_TRAILER                     = 0x13,
  92         DR_STE_V1_ACTION_ID_COUNTER_ID                  = 0x14,
  93         DR_STE_V1_ACTION_ID_MAX                         = 0x21,
  94         /* use for special cases */
  95         DR_STE_V1_ACTION_ID_SPECIAL_ENCAP_L3            = 0x22,
  96 };
  97
  98 enum {
  99         DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_0              = 0x00,
 100         DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_1              = 0x01,
 101         DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_2              = 0x02,
 102         DR_STE_V1_ACTION_MDFY_FLD_SRC_L2_OUT_0          = 0x08,
 103         DR_STE_V1_ACTION_MDFY_FLD_SRC_L2_OUT_1          = 0x09,
 104         DR_STE_V1_ACTION_MDFY_FLD_L3_OUT_0              = 0x0e,
 105         DR_STE_V1_ACTION_MDFY_FLD_L4_OUT_0              = 0x18,
 106         DR_STE_V1_ACTION_MDFY_FLD_L4_OUT_1              = 0x19,
 107         DR_STE_V1_ACTION_MDFY_FLD_IPV4_OUT_0            = 0x40,
 108         DR_STE_V1_ACTION_MDFY_FLD_IPV4_OUT_1            = 0x41,
 109         DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_0        = 0x44,
 110         DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_1        = 0x45,
 111         DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_2        = 0x46,
 112         DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_3        = 0x47,
 113         DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_0        = 0x4c,
 114         DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_1        = 0x4d,
 115         DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_2        = 0x4e,
 116         DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_3        = 0x4f,
 117         DR_STE_V1_ACTION_MDFY_FLD_TCP_MISC_0            = 0x5e,
 118         DR_STE_V1_ACTION_MDFY_FLD_TCP_MISC_1            = 0x5f,
 119         DR_STE_V1_ACTION_MDFY_FLD_METADATA_2_CQE        = 0x7b,
 120         DR_STE_V1_ACTION_MDFY_FLD_GNRL_PURPOSE          = 0x7c,
 121         DR_STE_V1_ACTION_MDFY_FLD_REGISTER_2            = 0x8c,
 122         DR_STE_V1_ACTION_MDFY_FLD_REGISTER_3            = 0x8d,
 123         DR_STE_V1_ACTION_MDFY_FLD_REGISTER_4            = 0x8e,
 124         DR_STE_V1_ACTION_MDFY_FLD_REGISTER_5            = 0x8f,
 125         DR_STE_V1_ACTION_MDFY_FLD_REGISTER_6            = 0x90,
 126         DR_STE_V1_ACTION_MDFY_FLD_REGISTER_7            = 0x91,
 127 };
 128
 129 static const struct mlx5dr_ste_action_modify_field dr_ste_v1_action_modify_field_arr[] = {
 130         [MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16] = {
 131                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_SRC_L2_OUT_0, .start = 0, .end = 31,
 132         },
 133         [MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0] = {
 134                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_SRC_L2_OUT_1, .start = 16, .end = 31,
 135         },
 136         [MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE] = {
 137                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_1, .start = 0, .end = 15,
 138         },
 139         [MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16] = {
 140                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_0, .start = 0, .end = 31,
 141         },
 142         [MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0] = {
 143                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_1, .start = 16, .end = 31,
 144         },
 145         [MLX5_ACTION_IN_FIELD_OUT_IP_DSCP] = {
 146                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_L3_OUT_0, .start = 18, .end = 23,
 147         },
 148         [MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS] = {
 149                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_L4_OUT_1, .start = 16, .end = 24,
 150                 .l4_type = DR_STE_ACTION_MDFY_TYPE_L4_TCP,
 151         },
 152         [MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT] = {
 153                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_L4_OUT_0, .start = 16, .end = 31,
 154                 .l4_type = DR_STE_ACTION_MDFY_TYPE_L4_TCP,
 155         },
 156         [MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT] = {
 157                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_L4_OUT_0, .start = 0, .end = 15,
 158                 .l4_type = DR_STE_ACTION_MDFY_TYPE_L4_TCP,
 159         },
 160         [MLX5_ACTION_IN_FIELD_OUT_IP_TTL] = {
 161                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_L3_OUT_0, .start = 8, .end = 15,
 162                 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV4,
 163         },
 164         [MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT] = {
 165                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_L3_OUT_0, .start = 8, .end = 15,
 166                 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
 167         },
 168         [MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT] = {
 169                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_L4_OUT_0, .start = 16, .end = 31,
 170                 .l4_type = DR_STE_ACTION_MDFY_TYPE_L4_UDP,
 171         },
 172         [MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT] = {
 173                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_L4_OUT_0, .start = 0, .end = 15,
 174                 .l4_type = DR_STE_ACTION_MDFY_TYPE_L4_UDP,
 175         },
 176         [MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96] = {
 177                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_0, .start = 0, .end = 31,
 178                 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
 179         },
 180         [MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64] = {
 181                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_1, .start = 0, .end = 31,
 182                 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
 183         },
 184         [MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32] = {
 185                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_2, .start = 0, .end = 31,
 186                 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
 187         },
 188         [MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0] = {
 189                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_3, .start = 0, .end = 31,
 190                 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
 191         },
 192         [MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96] = {
 193                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_0, .start = 0, .end = 31,
 194                 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
 195         },
 196         [MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64] = {
 197                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_1, .start = 0, .end = 31,
 198                 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
 199         },
 200         [MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32] = {
 201                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_2, .start = 0, .end = 31,
 202                 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
 203         },
 204         [MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0] = {
 205                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_3, .start = 0, .end = 31,
 206                 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
 207         },
 208         [MLX5_ACTION_IN_FIELD_OUT_SIPV4] = {
 209                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_IPV4_OUT_0, .start = 0, .end = 31,
 210                 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV4,
 211         },
 212         [MLX5_ACTION_IN_FIELD_OUT_DIPV4] = {
 213                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_IPV4_OUT_1, .start = 0, .end = 31,
 214                 .l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV4,
 215         },
 216         [MLX5_ACTION_IN_FIELD_METADATA_REG_A] = {
 217                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_GNRL_PURPOSE, .start = 0, .end = 31,
 218         },
 219         [MLX5_ACTION_IN_FIELD_METADATA_REG_B] = {
 220                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_METADATA_2_CQE, .start = 0, .end = 31,
 221         },
 222         [MLX5_ACTION_IN_FIELD_METADATA_REG_C_0] = {
 223                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_REGISTER_6, .start = 0, .end = 31,
 224         },
 225         [MLX5_ACTION_IN_FIELD_METADATA_REG_C_1] = {
 226                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_REGISTER_7, .start = 0, .end = 31,
 227         },
 228         [MLX5_ACTION_IN_FIELD_METADATA_REG_C_2] = {
 229                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_REGISTER_4, .start = 0, .end = 31,
 230         },
 231         [MLX5_ACTION_IN_FIELD_METADATA_REG_C_3] = {
 232                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_REGISTER_5, .start = 0, .end = 31,
 233         },
 234         [MLX5_ACTION_IN_FIELD_METADATA_REG_C_4] = {
 235                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_REGISTER_2, .start = 0, .end = 31,
 236         },
 237         [MLX5_ACTION_IN_FIELD_METADATA_REG_C_5] = {
 238                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_REGISTER_3, .start = 0, .end = 31,
 239         },
 240         [MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM] = {
 241                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_TCP_MISC_0, .start = 0, .end = 31,
 242         },
 243         [MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM] = {
 244                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_TCP_MISC_1, .start = 0, .end = 31,
 245         },
 246         [MLX5_ACTION_IN_FIELD_OUT_FIRST_VID] = {
 247                 .hw_field = DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_2, .start = 0, .end = 15,
 248         },
 249 };
 250
 251 static void dr_ste_v1_set_entry_type(u8 *hw_ste_p, u8 entry_type)
 252 {
 253         MLX5_SET(ste_match_bwc_v1, hw_ste_p, entry_format, entry_type);
 254 }
 255
 256 static void dr_ste_v1_set_miss_addr(u8 *hw_ste_p, u64 miss_addr)
 257 {
 258         u64 index = miss_addr >> 6;
 259
 260         MLX5_SET(ste_match_bwc_v1, hw_ste_p, miss_address_39_32, index >> 26);
 261         MLX5_SET(ste_match_bwc_v1, hw_ste_p, miss_address_31_6, index);
 262 }
 263
 264 static u64 dr_ste_v1_get_miss_addr(u8 *hw_ste_p)
 265 {
 266         u64 index =
 267                 (MLX5_GET(ste_match_bwc_v1, hw_ste_p, miss_address_31_6) |
 268                  MLX5_GET(ste_match_bwc_v1, hw_ste_p, miss_address_39_32) << 26);
 269
 270         return index << 6;
 271 }
 272
 273 static void dr_ste_v1_set_byte_mask(u8 *hw_ste_p, u16 byte_mask)
 274 {
 275         MLX5_SET(ste_match_bwc_v1, hw_ste_p, byte_mask, byte_mask);
 276 }
 277
 278 static u16 dr_ste_v1_get_byte_mask(u8 *hw_ste_p)
 279 {
 280         return MLX5_GET(ste_match_bwc_v1, hw_ste_p, byte_mask);
 281 }
 282
 283 static void dr_ste_v1_set_lu_type(u8 *hw_ste_p, u16 lu_type)
 284 {
 285         MLX5_SET(ste_match_bwc_v1, hw_ste_p, entry_format, lu_type >> 8);
 286         MLX5_SET(ste_match_bwc_v1, hw_ste_p, match_definer_ctx_idx, lu_type & 0xFF);
 287 }
 288
 289 static void dr_ste_v1_set_next_lu_type(u8 *hw_ste_p, u16 lu_type)
 290 {
 291         MLX5_SET(ste_match_bwc_v1, hw_ste_p, next_entry_format, lu_type >> 8);
 292         MLX5_SET(ste_match_bwc_v1, hw_ste_p, hash_definer_ctx_idx, lu_type & 0xFF);
 293 }
 294
 295 static u16 dr_ste_v1_get_next_lu_type(u8 *hw_ste_p)
 296 {
 297         u8 mode = MLX5_GET(ste_match_bwc_v1, hw_ste_p, next_entry_format);
 298         u8 index = MLX5_GET(ste_match_bwc_v1, hw_ste_p, hash_definer_ctx_idx);
 299
 300         return (mode << 8 | index);
 301 }
 302
 303 static void dr_ste_v1_set_hit_gvmi(u8 *hw_ste_p, u16 gvmi)
 304 {
 305         MLX5_SET(ste_match_bwc_v1, hw_ste_p, next_table_base_63_48, gvmi);
 306 }
 307
 308 static void dr_ste_v1_set_hit_addr(u8 *hw_ste_p, u64 icm_addr, u32 ht_size)
 309 {
 310         u64 index = (icm_addr >> 5) | ht_size;
 311
 312         MLX5_SET(ste_match_bwc_v1, hw_ste_p, next_table_base_39_32_size, index >> 27);
 313         MLX5_SET(ste_match_bwc_v1, hw_ste_p, next_table_base_31_5_size, index);
 314 }
 315
 316 static void dr_ste_v1_init(u8 *hw_ste_p, u16 lu_type,
 317                            u8 entry_type, u16 gvmi)
 318 {
 319         dr_ste_v1_set_lu_type(hw_ste_p, lu_type);
 320         dr_ste_v1_set_next_lu_type(hw_ste_p, MLX5DR_STE_LU_TYPE_DONT_CARE);
 321
 322         MLX5_SET(ste_match_bwc_v1, hw_ste_p, gvmi, gvmi);
 323         MLX5_SET(ste_match_bwc_v1, hw_ste_p, next_table_base_63_48, gvmi);
 324         MLX5_SET(ste_match_bwc_v1, hw_ste_p, miss_address_63_48, gvmi);
 325 }
 326
 327 static void dr_ste_v1_prepare_for_postsend(u8 *hw_ste_p,
 328                                            u32 ste_size)
 329 {
 330         u8 *tag = hw_ste_p + DR_STE_SIZE_CTRL;
 331         u8 *mask = tag + DR_STE_SIZE_TAG;
 332         u8 tmp_tag[DR_STE_SIZE_TAG] = {};
 333
 334         if (ste_size == DR_STE_SIZE_CTRL)
 335                 return;
 336
 337         WARN_ON(ste_size != DR_STE_SIZE);
 338
 339         /* Backup tag */
 340         memcpy(tmp_tag, tag, DR_STE_SIZE_TAG);
 341
 342         /* Swap mask and tag  both are the same size */
 343         memcpy(tag, mask, DR_STE_SIZE_MASK);
 344         memcpy(mask, tmp_tag, DR_STE_SIZE_TAG);
 345 }
 346
 347 static void dr_ste_v1_set_rx_flow_tag(u8 *s_action, u32 flow_tag)
 348 {
 349         MLX5_SET(ste_single_action_flow_tag_v1, s_action, action_id,
 350                  DR_STE_V1_ACTION_ID_FLOW_TAG);
 351         MLX5_SET(ste_single_action_flow_tag_v1, s_action, flow_tag, flow_tag);
 352 }
 353
 354 static void dr_ste_v1_set_counter_id(u8 *hw_ste_p, u32 ctr_id)
 355 {
 356         MLX5_SET(ste_match_bwc_v1, hw_ste_p, counter_id, ctr_id);
 357 }
 358
 359 static void dr_ste_v1_set_reparse(u8 *hw_ste_p)
 360 {
 361         MLX5_SET(ste_match_bwc_v1, hw_ste_p, reparse, 1);
 362 }
 363
 364 static void dr_ste_v1_set_tx_encap(u8 *hw_ste_p, u8 *d_action,
 365                                    u32 reformat_id, int size)
 366 {
 367         MLX5_SET(ste_double_action_insert_with_ptr_v1, d_action, action_id,
 368                  DR_STE_V1_ACTION_ID_INSERT_POINTER);
 369         /* The hardware expects here size in words (2 byte) */
 370         MLX5_SET(ste_double_action_insert_with_ptr_v1, d_action, size, size / 2);
 371         MLX5_SET(ste_double_action_insert_with_ptr_v1, d_action, pointer, reformat_id);
 372         MLX5_SET(ste_double_action_insert_with_ptr_v1, d_action, attributes,
 373                  DR_STE_V1_ACTION_INSERT_PTR_ATTR_ENCAP);
 374         dr_ste_v1_set_reparse(hw_ste_p);
 375 }
 376
 377 static void dr_ste_v1_set_tx_push_vlan(u8 *hw_ste_p, u8 *d_action,
 378                                        u32 vlan_hdr)
 379 {
 380         MLX5_SET(ste_double_action_insert_with_inline_v1, d_action,
 381                  action_id, DR_STE_V1_ACTION_ID_INSERT_INLINE);
 382         /* The hardware expects offset to vlan header in words (2 byte) */
 383         MLX5_SET(ste_double_action_insert_with_inline_v1, d_action,
 384                  start_offset, HDR_LEN_L2_MACS >> 1);
 385         MLX5_SET(ste_double_action_insert_with_inline_v1, d_action,
 386                  inline_data, vlan_hdr);
 387
 388         dr_ste_v1_set_reparse(hw_ste_p);
 389 }
 390
 391 static void dr_ste_v1_set_rx_pop_vlan(u8 *hw_ste_p, u8 *s_action, u8 vlans_num)
 392 {
 393         MLX5_SET(ste_single_action_remove_header_size_v1, s_action,
 394                  action_id, DR_STE_V1_ACTION_ID_REMOVE_BY_SIZE);
 395         MLX5_SET(ste_single_action_remove_header_size_v1, s_action,
 396                  start_anchor, DR_STE_HEADER_ANCHOR_1ST_VLAN);
 397         /* The hardware expects here size in words (2 byte) */
 398         MLX5_SET(ste_single_action_remove_header_size_v1, s_action,
 399                  remove_size, (HDR_LEN_L2_VLAN >> 1) * vlans_num);
 400
 401         dr_ste_v1_set_reparse(hw_ste_p);
 402 }
 403
 404 static void dr_ste_v1_set_tx_encap_l3(u8 *hw_ste_p,
 405                                       u8 *frst_s_action,
 406                                       u8 *scnd_d_action,
 407                                       u32 reformat_id,
 408                                       int size)
 409 {
 410         /* Remove L2 headers */
 411         MLX5_SET(ste_single_action_remove_header_v1, frst_s_action, action_id,
 412                  DR_STE_V1_ACTION_ID_REMOVE_HEADER_TO_HEADER);
 413         MLX5_SET(ste_single_action_remove_header_v1, frst_s_action, end_anchor,
 414                  DR_STE_HEADER_ANCHOR_IPV6_IPV4);
 415
 416         /* Encapsulate with given reformat ID */
 417         MLX5_SET(ste_double_action_insert_with_ptr_v1, scnd_d_action, action_id,
 418                  DR_STE_V1_ACTION_ID_INSERT_POINTER);
 419         /* The hardware expects here size in words (2 byte) */
 420         MLX5_SET(ste_double_action_insert_with_ptr_v1, scnd_d_action, size, size / 2);
 421         MLX5_SET(ste_double_action_insert_with_ptr_v1, scnd_d_action, pointer, reformat_id);
 422         MLX5_SET(ste_double_action_insert_with_ptr_v1, scnd_d_action, attributes,
 423                  DR_STE_V1_ACTION_INSERT_PTR_ATTR_ENCAP);
 424
 425         dr_ste_v1_set_reparse(hw_ste_p);
 426 }
 427
 428 static void dr_ste_v1_set_rx_decap(u8 *hw_ste_p, u8 *s_action)
 429 {
 430         MLX5_SET(ste_single_action_remove_header_v1, s_action, action_id,
 431                  DR_STE_V1_ACTION_ID_REMOVE_HEADER_TO_HEADER);
 432         MLX5_SET(ste_single_action_remove_header_v1, s_action, decap, 1);
 433         MLX5_SET(ste_single_action_remove_header_v1, s_action, vni_to_cqe, 1);
 434         MLX5_SET(ste_single_action_remove_header_v1, s_action, end_anchor,
 435                  DR_STE_HEADER_ANCHOR_INNER_MAC);
 436
 437         dr_ste_v1_set_reparse(hw_ste_p);
 438 }
 439
 440 static void dr_ste_v1_set_rx_decap_l3(u8 *hw_ste_p,
 441                                       u8 *s_action,
 442                                       u16 decap_actions,
 443                                       u32 decap_index)
 444 {
 445         MLX5_SET(ste_single_action_modify_list_v1, s_action, action_id,
 446                  DR_STE_V1_ACTION_ID_MODIFY_LIST);
 447         MLX5_SET(ste_single_action_modify_list_v1, s_action, num_of_modify_actions,
 448                  decap_actions);
 449         MLX5_SET(ste_single_action_modify_list_v1, s_action, modify_actions_ptr,
 450                  decap_index);
 451
 452         dr_ste_v1_set_reparse(hw_ste_p);
 453 }
 454
 455 static void dr_ste_v1_set_rewrite_actions(u8 *hw_ste_p,
 456                                           u8 *s_action,
 457                                           u16 num_of_actions,
 458                                           u32 re_write_index)
 459 {
 460         MLX5_SET(ste_single_action_modify_list_v1, s_action, action_id,
 461                  DR_STE_V1_ACTION_ID_MODIFY_LIST);
 462         MLX5_SET(ste_single_action_modify_list_v1, s_action, num_of_modify_actions,
 463                  num_of_actions);
 464         MLX5_SET(ste_single_action_modify_list_v1, s_action, modify_actions_ptr,
 465                  re_write_index);
 466
 467         dr_ste_v1_set_reparse(hw_ste_p);
 468 }
 469
 470 static void dr_ste_v1_arr_init_next_match(u8 **last_ste,
 471                                           u32 *added_stes,
 472                                           u16 gvmi)
 473 {
 474         u8 *action;
 475
 476         (*added_stes)++;
 477         *last_ste += DR_STE_SIZE;
 478         dr_ste_v1_init(*last_ste, MLX5DR_STE_LU_TYPE_DONT_CARE, 0, gvmi);
 479         dr_ste_v1_set_entry_type(*last_ste, DR_STE_V1_TYPE_MATCH);
 480
 481         action = MLX5_ADDR_OF(ste_mask_and_match_v1, *last_ste, action);
 482         memset(action, 0, MLX5_FLD_SZ_BYTES(ste_mask_and_match_v1, action));
 483 }
 484
 485 static void dr_ste_v1_set_actions_tx(struct mlx5dr_domain *dmn,
 486                                      u8 *action_type_set,
 487                                      u8 *last_ste,
 488                                      struct mlx5dr_ste_actions_attr *attr,
 489                                      u32 *added_stes)
 490 {
 491         u8 *action = MLX5_ADDR_OF(ste_match_bwc_v1, last_ste, action);
 492         u8 action_sz = DR_STE_ACTION_DOUBLE_SZ;
 493         bool allow_encap = true;
 494
 495         if (action_type_set[DR_ACTION_TYP_CTR])
 496                 dr_ste_v1_set_counter_id(last_ste, attr->ctr_id);
 497
 498         if (action_type_set[DR_ACTION_TYP_MODIFY_HDR]) {
 499                 if (action_sz < DR_STE_ACTION_DOUBLE_SZ) {
 500                         dr_ste_v1_arr_init_next_match(&last_ste, added_stes,
 501                                                       attr->gvmi);
 502                         action = MLX5_ADDR_OF(ste_mask_and_match_v1,
 503                                               last_ste, action);
 504                         action_sz = DR_STE_ACTION_TRIPLE_SZ;
 505                 }
 506                 dr_ste_v1_set_rewrite_actions(last_ste, action,
 507                                               attr->modify_actions,
 508                                               attr->modify_index);
 509                 action_sz -= DR_STE_ACTION_DOUBLE_SZ;
 510                 action += DR_STE_ACTION_DOUBLE_SZ;
 511                 allow_encap = false;
 512         }
 513
 514         if (action_type_set[DR_ACTION_TYP_PUSH_VLAN]) {
 515                 int i;
 516
 517                 for (i = 0; i < attr->vlans.count; i++) {
 518                         if (action_sz < DR_STE_ACTION_DOUBLE_SZ || !allow_encap) {
 519                                 dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi);
 520                                 action = MLX5_ADDR_OF(ste_mask_and_match_v1, last_ste, action);
 521                                 action_sz = DR_STE_ACTION_TRIPLE_SZ;
 522                                 allow_encap = true;
 523                         }
 524                         dr_ste_v1_set_tx_push_vlan(last_ste, action, attr->vlans.headers[i]);
 525                         action_sz -= DR_STE_ACTION_DOUBLE_SZ;
 526                         action += DR_STE_ACTION_DOUBLE_SZ;
 527                 }
 528         }
 529
 530         if (action_type_set[DR_ACTION_TYP_L2_TO_TNL_L2]) {
 531                 if (!allow_encap || action_sz < DR_STE_ACTION_DOUBLE_SZ) {
 532                         dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi);
 533                         action = MLX5_ADDR_OF(ste_mask_and_match_v1, last_ste, action);
 534                         action_sz = DR_STE_ACTION_TRIPLE_SZ;
 535                         allow_encap = true;
 536                 }
 537                 dr_ste_v1_set_tx_encap(last_ste, action,
 538                                        attr->reformat_id,
 539                                        attr->reformat_size);
 540                 action_sz -= DR_STE_ACTION_DOUBLE_SZ;
 541                 action += DR_STE_ACTION_DOUBLE_SZ;
 542         } else if (action_type_set[DR_ACTION_TYP_L2_TO_TNL_L3]) {
 543                 u8 *d_action;
 544
 545                 dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi);
 546                 action = MLX5_ADDR_OF(ste_mask_and_match_v1, last_ste, action);
 547                 action_sz = DR_STE_ACTION_TRIPLE_SZ;
 548                 d_action = action + DR_STE_ACTION_SINGLE_SZ;
 549
 550                 dr_ste_v1_set_tx_encap_l3(last_ste,
 551                                           action, d_action,
 552                                           attr->reformat_id,
 553                                           attr->reformat_size);
 554                 action_sz -= DR_STE_ACTION_TRIPLE_SZ;
 555                 action += DR_STE_ACTION_TRIPLE_SZ;
 556         }
 557
 558         dr_ste_v1_set_hit_gvmi(last_ste, attr->hit_gvmi);
 559         dr_ste_v1_set_hit_addr(last_ste, attr->final_icm_addr, 1);
 560 }
 561
 562 static void dr_ste_v1_set_actions_rx(struct mlx5dr_domain *dmn,
 563                                      u8 *action_type_set,
 564                                      u8 *last_ste,
 565                                      struct mlx5dr_ste_actions_attr *attr,
 566                                      u32 *added_stes)
 567 {
 568         u8 *action = MLX5_ADDR_OF(ste_match_bwc_v1, last_ste, action);
 569         u8 action_sz = DR_STE_ACTION_DOUBLE_SZ;
 570         bool allow_modify_hdr = true;
 571         bool allow_ctr = true;
 572
 573         if (action_type_set[DR_ACTION_TYP_TNL_L3_TO_L2]) {
 574                 dr_ste_v1_set_rx_decap_l3(last_ste, action,
 575                                           attr->decap_actions,
 576                                           attr->decap_index);
 577                 dr_ste_v1_set_rewrite_actions(last_ste, action,
 578                                               attr->decap_actions,
 579                                               attr->decap_index);
 580                 action_sz -= DR_STE_ACTION_DOUBLE_SZ;
 581                 action += DR_STE_ACTION_DOUBLE_SZ;
 582                 allow_modify_hdr = false;
 583                 allow_ctr = false;
 584         } else if (action_type_set[DR_ACTION_TYP_TNL_L2_TO_L2]) {
 585                 dr_ste_v1_set_rx_decap(last_ste, action);
 586                 action_sz -= DR_STE_ACTION_SINGLE_SZ;
 587                 action += DR_STE_ACTION_SINGLE_SZ;
 588                 allow_modify_hdr = false;
 589                 allow_ctr = false;
 590         }
 591
 592         if (action_type_set[DR_ACTION_TYP_TAG]) {
 593                 if (action_sz < DR_STE_ACTION_SINGLE_SZ) {
 594                         dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi);
 595                         action = MLX5_ADDR_OF(ste_mask_and_match_v1, last_ste, action);
 596                         action_sz = DR_STE_ACTION_TRIPLE_SZ;
 597                         allow_modify_hdr = true;
 598                         allow_ctr = true;
 599                 }
 600                 dr_ste_v1_set_rx_flow_tag(action, attr->flow_tag);
 601                 action_sz -= DR_STE_ACTION_SINGLE_SZ;
 602                 action += DR_STE_ACTION_SINGLE_SZ;
 603         }
 604
 605         if (action_type_set[DR_ACTION_TYP_POP_VLAN]) {
 606                 if (action_sz < DR_STE_ACTION_SINGLE_SZ ||
 607                     !allow_modify_hdr) {
 608                         dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi);
 609                         action = MLX5_ADDR_OF(ste_mask_and_match_v1, last_ste, action);
 610                         action_sz = DR_STE_ACTION_TRIPLE_SZ;
 611                         allow_modify_hdr = false;
 612                         allow_ctr = false;
 613                 }
 614
 615                 dr_ste_v1_set_rx_pop_vlan(last_ste, action, attr->vlans.count);
 616                 action_sz -= DR_STE_ACTION_SINGLE_SZ;
 617                 action += DR_STE_ACTION_SINGLE_SZ;
 618         }
 619
 620         if (action_type_set[DR_ACTION_TYP_MODIFY_HDR]) {
 621                 /* Modify header and decapsulation must use different STEs */
 622                 if (!allow_modify_hdr || action_sz < DR_STE_ACTION_DOUBLE_SZ) {
 623                         dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi);
 624                         action = MLX5_ADDR_OF(ste_mask_and_match_v1, last_ste, action);
 625                         action_sz = DR_STE_ACTION_TRIPLE_SZ;
 626                         allow_modify_hdr = true;
 627                         allow_ctr = true;
 628                 }
 629                 dr_ste_v1_set_rewrite_actions(last_ste, action,
 630                                               attr->modify_actions,
 631                                               attr->modify_index);
 632                 action_sz -= DR_STE_ACTION_DOUBLE_SZ;
 633                 action += DR_STE_ACTION_DOUBLE_SZ;
 634         }
 635
 636         if (action_type_set[DR_ACTION_TYP_CTR]) {
 637                 /* Counter action set after decap to exclude decaped header */
 638                 if (!allow_ctr) {
 639                         dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi);
 640                         action = MLX5_ADDR_OF(ste_mask_and_match_v1, last_ste, action);
 641                         action_sz = DR_STE_ACTION_TRIPLE_SZ;
 642                         allow_modify_hdr = true;
 643                         allow_ctr = false;
 644                 }
 645                 dr_ste_v1_set_counter_id(last_ste, attr->ctr_id);
 646         }
 647
 648         dr_ste_v1_set_hit_gvmi(last_ste, attr->hit_gvmi);
 649         dr_ste_v1_set_hit_addr(last_ste, attr->final_icm_addr, 1);
 650 }
 651
 652 static void dr_ste_v1_set_action_set(u8 *d_action,
 653                                      u8 hw_field,
 654                                      u8 shifter,
 655                                      u8 length,
 656                                      u32 data)
 657 {
 658         shifter += MLX5_MODIFY_HEADER_V1_QW_OFFSET;
 659         MLX5_SET(ste_double_action_set_v1, d_action, action_id, DR_STE_V1_ACTION_ID_SET);
 660         MLX5_SET(ste_double_action_set_v1, d_action, destination_dw_offset, hw_field);
 661         MLX5_SET(ste_double_action_set_v1, d_action, destination_left_shifter, shifter);
 662         MLX5_SET(ste_double_action_set_v1, d_action, destination_length, length);
 663         MLX5_SET(ste_double_action_set_v1, d_action, inline_data, data);
 664 }
 665
 666 static void dr_ste_v1_set_action_add(u8 *d_action,
 667                                      u8 hw_field,
 668                                      u8 shifter,
 669                                      u8 length,
 670                                      u32 data)
 671 {
 672         shifter += MLX5_MODIFY_HEADER_V1_QW_OFFSET;
 673         MLX5_SET(ste_double_action_add_v1, d_action, action_id, DR_STE_V1_ACTION_ID_ADD);
 674         MLX5_SET(ste_double_action_add_v1, d_action, destination_dw_offset, hw_field);
 675         MLX5_SET(ste_double_action_add_v1, d_action, destination_left_shifter, shifter);
 676         MLX5_SET(ste_double_action_add_v1, d_action, destination_length, length);
 677         MLX5_SET(ste_double_action_add_v1, d_action, add_value, data);
 678 }
 679
 680 static void dr_ste_v1_set_action_copy(u8 *d_action,
 681                                       u8 dst_hw_field,
 682                                       u8 dst_shifter,
 683                                       u8 dst_len,
 684                                       u8 src_hw_field,
 685                                       u8 src_shifter)
 686 {
 687         dst_shifter += MLX5_MODIFY_HEADER_V1_QW_OFFSET;
 688         src_shifter += MLX5_MODIFY_HEADER_V1_QW_OFFSET;
 689         MLX5_SET(ste_double_action_copy_v1, d_action, action_id, DR_STE_V1_ACTION_ID_COPY);
 690         MLX5_SET(ste_double_action_copy_v1, d_action, destination_dw_offset, dst_hw_field);
 691         MLX5_SET(ste_double_action_copy_v1, d_action, destination_left_shifter, dst_shifter);
 692         MLX5_SET(ste_double_action_copy_v1, d_action, destination_length, dst_len);
 693         MLX5_SET(ste_double_action_copy_v1, d_action, source_dw_offset, src_hw_field);
 694         MLX5_SET(ste_double_action_copy_v1, d_action, source_right_shifter, src_shifter);
 695 }
 696
 697 #define DR_STE_DECAP_L3_ACTION_NUM      8
 698 #define DR_STE_L2_HDR_MAX_SZ            20
 699
 700 static int dr_ste_v1_set_action_decap_l3_list(void *data,
 701                                               u32 data_sz,
 702                                               u8 *hw_action,
 703                                               u32 hw_action_sz,
 704                                               u16 *used_hw_action_num)
 705 {
 706         u8 padded_data[DR_STE_L2_HDR_MAX_SZ] = {};
 707         void *data_ptr = padded_data;
 708         u16 used_actions = 0;
 709         u32 inline_data_sz;
 710         u32 i;
 711
 712         if (hw_action_sz / DR_STE_ACTION_DOUBLE_SZ < DR_STE_DECAP_L3_ACTION_NUM)
 713                 return -EINVAL;
 714
 715         memcpy(padded_data, data, data_sz);
 716
 717         /* Remove L2L3 outer headers */
 718         MLX5_SET(ste_single_action_remove_header_v1, hw_action, action_id,
 719                  DR_STE_V1_ACTION_ID_REMOVE_HEADER_TO_HEADER);
 720         MLX5_SET(ste_single_action_remove_header_v1, hw_action, decap, 1);
 721         MLX5_SET(ste_single_action_remove_header_v1, hw_action, vni_to_cqe, 1);
 722         MLX5_SET(ste_single_action_remove_header_v1, hw_action, end_anchor,
 723                  DR_STE_HEADER_ANCHOR_INNER_IPV6_IPV4);
 724         hw_action += DR_STE_ACTION_DOUBLE_SZ;
 725         used_actions++; /* Remove and NOP are a single double action */
 726
 727         inline_data_sz =
 728                 MLX5_FLD_SZ_BYTES(ste_double_action_insert_with_inline_v1, inline_data);
 729
 730         /* Add the new header inline + 2 extra bytes */
 731         for (i = 0; i < data_sz / inline_data_sz + 1; i++) {
 732                 void *addr_inline;
 733
 734                 MLX5_SET(ste_double_action_insert_with_inline_v1, hw_action, action_id,
 735                          DR_STE_V1_ACTION_ID_INSERT_INLINE);
 736                 /* The hardware expects here offset to words (2 bytes) */
 737                 MLX5_SET(ste_double_action_insert_with_inline_v1, hw_action, start_offset,
 738                          i * 2);
 739
 740                 /* Copy bytes one by one to avoid endianness problem */
 741                 addr_inline = MLX5_ADDR_OF(ste_double_action_insert_with_inline_v1,
 742                                            hw_action, inline_data);
 743                 memcpy(addr_inline, data_ptr, inline_data_sz);
 744                 hw_action += DR_STE_ACTION_DOUBLE_SZ;
 745                 data_ptr += inline_data_sz;
 746                 used_actions++;
 747         }
 748
 749         /* Remove 2 extra bytes */
 750         MLX5_SET(ste_single_action_remove_header_size_v1, hw_action, action_id,
 751                  DR_STE_V1_ACTION_ID_REMOVE_BY_SIZE);
 752         MLX5_SET(ste_single_action_remove_header_size_v1, hw_action, start_offset, data_sz / 2);
 753         /* The hardware expects here size in words (2 bytes) */
 754         MLX5_SET(ste_single_action_remove_header_size_v1, hw_action, remove_size, 1);
 755         used_actions++;
 756
 757         *used_hw_action_num = used_actions;
 758
 759         return 0;
 760 }
 761
 762 static void dr_ste_v1_build_eth_l2_src_dst_bit_mask(struct mlx5dr_match_param *value,
 763                                                     bool inner, u8 *bit_mask)
 764 {
 765         struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer;
 766
 767         DR_STE_SET_TAG(eth_l2_src_dst_v1, bit_mask, dmac_47_16, mask, dmac_47_16);
 768         DR_STE_SET_TAG(eth_l2_src_dst_v1, bit_mask, dmac_15_0, mask, dmac_15_0);
 769
 770         DR_STE_SET_TAG(eth_l2_src_dst_v1, bit_mask, smac_47_16, mask, smac_47_16);
 771         DR_STE_SET_TAG(eth_l2_src_dst_v1, bit_mask, smac_15_0, mask, smac_15_0);
 772
 773         DR_STE_SET_TAG(eth_l2_src_dst_v1, bit_mask, first_vlan_id, mask, first_vid);
 774         DR_STE_SET_TAG(eth_l2_src_dst_v1, bit_mask, first_cfi, mask, first_cfi);
 775         DR_STE_SET_TAG(eth_l2_src_dst_v1, bit_mask, first_priority, mask, first_prio);
 776         DR_STE_SET_ONES(eth_l2_src_dst_v1, bit_mask, l3_type, mask, ip_version);
 777
 778         if (mask->cvlan_tag) {
 779                 MLX5_SET(ste_eth_l2_src_dst_v1, bit_mask, first_vlan_qualifier, -1);
 780                 mask->cvlan_tag = 0;
 781         } else if (mask->svlan_tag) {
 782                 MLX5_SET(ste_eth_l2_src_dst_v1, bit_mask, first_vlan_qualifier, -1);
 783                 mask->svlan_tag = 0;
 784         }
 785 }
 786
 787 static int dr_ste_v1_build_eth_l2_src_dst_tag(struct mlx5dr_match_param *value,
 788                                               struct mlx5dr_ste_build *sb,
 789                                               u8 *tag)
 790 {
 791         struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer;
 792
 793         DR_STE_SET_TAG(eth_l2_src_dst_v1, tag, dmac_47_16, spec, dmac_47_16);
 794         DR_STE_SET_TAG(eth_l2_src_dst_v1, tag, dmac_15_0, spec, dmac_15_0);
 795
 796         DR_STE_SET_TAG(eth_l2_src_dst_v1, tag, smac_47_16, spec, smac_47_16);
 797         DR_STE_SET_TAG(eth_l2_src_dst_v1, tag, smac_15_0, spec, smac_15_0);
 798
 799         if (spec->ip_version == IP_VERSION_IPV4) {
 800                 MLX5_SET(ste_eth_l2_src_dst_v1, tag, l3_type, STE_IPV4);
 801                 spec->ip_version = 0;
 802         } else if (spec->ip_version == IP_VERSION_IPV6) {
 803                 MLX5_SET(ste_eth_l2_src_dst_v1, tag, l3_type, STE_IPV6);
 804                 spec->ip_version = 0;
 805         } else if (spec->ip_version) {
 806                 return -EINVAL;
 807         }
 808
 809         DR_STE_SET_TAG(eth_l2_src_dst_v1, tag, first_vlan_id, spec, first_vid);
 810         DR_STE_SET_TAG(eth_l2_src_dst_v1, tag, first_cfi, spec, first_cfi);
 811         DR_STE_SET_TAG(eth_l2_src_dst_v1, tag, first_priority, spec, first_prio);
 812
 813         if (spec->cvlan_tag) {
 814                 MLX5_SET(ste_eth_l2_src_dst_v1, tag, first_vlan_qualifier, DR_STE_CVLAN);
 815                 spec->cvlan_tag = 0;
 816         } else if (spec->svlan_tag) {
 817                 MLX5_SET(ste_eth_l2_src_dst_v1, tag, first_vlan_qualifier, DR_STE_SVLAN);
 818                 spec->svlan_tag = 0;
 819         }
 820         return 0;
 821 }
 822
 823 static void dr_ste_v1_build_eth_l2_src_dst_init(struct mlx5dr_ste_build *sb,
 824                                                 struct mlx5dr_match_param *mask)
 825 {
 826         dr_ste_v1_build_eth_l2_src_dst_bit_mask(mask, sb->inner, sb->bit_mask);
 827
 828         sb->lu_type = DR_STE_CALC_DFNR_TYPE(ETHL2_SRC_DST, sb->inner);
 829         sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
 830         sb->ste_build_tag_func = &dr_ste_v1_build_eth_l2_src_dst_tag;
 831 }
 832
 833 static int dr_ste_v1_build_eth_l3_ipv6_dst_tag(struct mlx5dr_match_param *value,
 834                                                struct mlx5dr_ste_build *sb,
 835                                                u8 *tag)
 836 {
 837         struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer;
 838
 839         DR_STE_SET_TAG(eth_l3_ipv6_dst, tag, dst_ip_127_96, spec, dst_ip_127_96);
 840         DR_STE_SET_TAG(eth_l3_ipv6_dst, tag, dst_ip_95_64, spec, dst_ip_95_64);
 841         DR_STE_SET_TAG(eth_l3_ipv6_dst, tag, dst_ip_63_32, spec, dst_ip_63_32);
 842         DR_STE_SET_TAG(eth_l3_ipv6_dst, tag, dst_ip_31_0, spec, dst_ip_31_0);
 843
 844         return 0;
 845 }
 846
 847 static void dr_ste_v1_build_eth_l3_ipv6_dst_init(struct mlx5dr_ste_build *sb,
 848                                                  struct mlx5dr_match_param *mask)
 849 {
 850         dr_ste_v1_build_eth_l3_ipv6_dst_tag(mask, sb, sb->bit_mask);
 851
 852         sb->lu_type = DR_STE_CALC_DFNR_TYPE(IPV6_DES, sb->inner);
 853         sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
 854         sb->ste_build_tag_func = &dr_ste_v1_build_eth_l3_ipv6_dst_tag;
 855 }
 856
 857 static int dr_ste_v1_build_eth_l3_ipv6_src_tag(struct mlx5dr_match_param *value,
 858                                                struct mlx5dr_ste_build *sb,
 859                                                u8 *tag)
 860 {
 861         struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer;
 862
 863         DR_STE_SET_TAG(eth_l3_ipv6_src, tag, src_ip_127_96, spec, src_ip_127_96);
 864         DR_STE_SET_TAG(eth_l3_ipv6_src, tag, src_ip_95_64, spec, src_ip_95_64);
 865         DR_STE_SET_TAG(eth_l3_ipv6_src, tag, src_ip_63_32, spec, src_ip_63_32);
 866         DR_STE_SET_TAG(eth_l3_ipv6_src, tag, src_ip_31_0, spec, src_ip_31_0);
 867
 868         return 0;
 869 }
 870
 871 static void dr_ste_v1_build_eth_l3_ipv6_src_init(struct mlx5dr_ste_build *sb,
 872                                                  struct mlx5dr_match_param *mask)
 873 {
 874         dr_ste_v1_build_eth_l3_ipv6_src_tag(mask, sb, sb->bit_mask);
 875
 876         sb->lu_type = DR_STE_CALC_DFNR_TYPE(IPV6_SRC, sb->inner);
 877         sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
 878         sb->ste_build_tag_func = &dr_ste_v1_build_eth_l3_ipv6_src_tag;
 879 }
 880
 881 static int dr_ste_v1_build_eth_l3_ipv4_5_tuple_tag(struct mlx5dr_match_param *value,
 882                                                    struct mlx5dr_ste_build *sb,
 883                                                    u8 *tag)
 884 {
 885         struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer;
 886
 887         DR_STE_SET_TAG(eth_l3_ipv4_5_tuple_v1, tag, destination_address, spec, dst_ip_31_0);
 888         DR_STE_SET_TAG(eth_l3_ipv4_5_tuple_v1, tag, source_address, spec, src_ip_31_0);
 889         DR_STE_SET_TAG(eth_l3_ipv4_5_tuple_v1, tag, destination_port, spec, tcp_dport);
 890         DR_STE_SET_TAG(eth_l3_ipv4_5_tuple_v1, tag, destination_port, spec, udp_dport);
 891         DR_STE_SET_TAG(eth_l3_ipv4_5_tuple_v1, tag, source_port, spec, tcp_sport);
 892         DR_STE_SET_TAG(eth_l3_ipv4_5_tuple_v1, tag, source_port, spec, udp_sport);
 893         DR_STE_SET_TAG(eth_l3_ipv4_5_tuple_v1, tag, protocol, spec, ip_protocol);
 894         DR_STE_SET_TAG(eth_l3_ipv4_5_tuple_v1, tag, fragmented, spec, frag);
 895         DR_STE_SET_TAG(eth_l3_ipv4_5_tuple_v1, tag, dscp, spec, ip_dscp);
 896         DR_STE_SET_TAG(eth_l3_ipv4_5_tuple_v1, tag, ecn, spec, ip_ecn);
 897
 898         if (spec->tcp_flags) {
 899                 DR_STE_SET_TCP_FLAGS(eth_l3_ipv4_5_tuple_v1, tag, spec);
 900                 spec->tcp_flags = 0;
 901         }
 902
 903         return 0;
 904 }
 905
 906 static void dr_ste_v1_build_eth_l3_ipv4_5_tuple_init(struct mlx5dr_ste_build *sb,
 907                                                      struct mlx5dr_match_param *mask)
 908 {
 909         dr_ste_v1_build_eth_l3_ipv4_5_tuple_tag(mask, sb, sb->bit_mask);
 910
 911         sb->lu_type = DR_STE_CALC_DFNR_TYPE(ETHL3_IPV4_5_TUPLE, sb->inner);
 912         sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
 913         sb->ste_build_tag_func = &dr_ste_v1_build_eth_l3_ipv4_5_tuple_tag;
 914 }
 915
 916 static void dr_ste_v1_build_eth_l2_src_or_dst_bit_mask(struct mlx5dr_match_param *value,
 917                                                        bool inner, u8 *bit_mask)
 918 {
 919         struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer;
 920         struct mlx5dr_match_misc *misc_mask = &value->misc;
 921
 922         DR_STE_SET_TAG(eth_l2_src_v1, bit_mask, first_vlan_id, mask, first_vid);
 923         DR_STE_SET_TAG(eth_l2_src_v1, bit_mask, first_cfi, mask, first_cfi);
 924         DR_STE_SET_TAG(eth_l2_src_v1, bit_mask, first_priority, mask, first_prio);
 925         DR_STE_SET_TAG(eth_l2_src_v1, bit_mask, ip_fragmented, mask, frag); // ?
 926         DR_STE_SET_TAG(eth_l2_src_v1, bit_mask, l3_ethertype, mask, ethertype); // ?
 927         DR_STE_SET_ONES(eth_l2_src_v1, bit_mask, l3_type, mask, ip_version);
 928
 929         if (mask->svlan_tag || mask->cvlan_tag) {
 930                 MLX5_SET(ste_eth_l2_src_v1, bit_mask, first_vlan_qualifier, -1);
 931                 mask->cvlan_tag = 0;
 932                 mask->svlan_tag = 0;
 933         }
 934
 935         if (inner) {
 936                 if (misc_mask->inner_second_cvlan_tag ||
 937                     misc_mask->inner_second_svlan_tag) {
 938                         MLX5_SET(ste_eth_l2_src_v1, bit_mask, second_vlan_qualifier, -1);
 939                         misc_mask->inner_second_cvlan_tag = 0;
 940                         misc_mask->inner_second_svlan_tag = 0;
 941                 }
 942
 943                 DR_STE_SET_TAG(eth_l2_src_v1, bit_mask,
 944                                second_vlan_id, misc_mask, inner_second_vid);
 945                 DR_STE_SET_TAG(eth_l2_src_v1, bit_mask,
 946                                second_cfi, misc_mask, inner_second_cfi);
 947                 DR_STE_SET_TAG(eth_l2_src_v1, bit_mask,
 948                                second_priority, misc_mask, inner_second_prio);
 949         } else {
 950                 if (misc_mask->outer_second_cvlan_tag ||
 951                     misc_mask->outer_second_svlan_tag) {
 952                         MLX5_SET(ste_eth_l2_src_v1, bit_mask, second_vlan_qualifier, -1);
 953                         misc_mask->outer_second_cvlan_tag = 0;
 954                         misc_mask->outer_second_svlan_tag = 0;
 955                 }
 956
 957                 DR_STE_SET_TAG(eth_l2_src_v1, bit_mask,
 958                                second_vlan_id, misc_mask, outer_second_vid);
 959                 DR_STE_SET_TAG(eth_l2_src_v1, bit_mask,
 960                                second_cfi, misc_mask, outer_second_cfi);
 961                 DR_STE_SET_TAG(eth_l2_src_v1, bit_mask,
 962                                second_priority, misc_mask, outer_second_prio);
 963         }
 964 }
 965
 966 static int dr_ste_v1_build_eth_l2_src_or_dst_tag(struct mlx5dr_match_param *value,
 967                                                  bool inner, u8 *tag)
 968 {
 969         struct mlx5dr_match_spec *spec = inner ? &value->inner : &value->outer;
 970         struct mlx5dr_match_misc *misc_spec = &value->misc;
 971
 972         DR_STE_SET_TAG(eth_l2_src_v1, tag, first_vlan_id, spec, first_vid);
 973         DR_STE_SET_TAG(eth_l2_src_v1, tag, first_cfi, spec, first_cfi);
 974         DR_STE_SET_TAG(eth_l2_src_v1, tag, first_priority, spec, first_prio);
 975         DR_STE_SET_TAG(eth_l2_src_v1, tag, ip_fragmented, spec, frag);
 976         DR_STE_SET_TAG(eth_l2_src_v1, tag, l3_ethertype, spec, ethertype);
 977
 978         if (spec->ip_version == IP_VERSION_IPV4) {
 979                 MLX5_SET(ste_eth_l2_src_v1, tag, l3_type, STE_IPV4);
 980                 spec->ip_version = 0;
 981         } else if (spec->ip_version == IP_VERSION_IPV6) {
 982                 MLX5_SET(ste_eth_l2_src_v1, tag, l3_type, STE_IPV6);
 983                 spec->ip_version = 0;
 984         } else if (spec->ip_version) {
 985                 return -EINVAL;
 986         }
 987
 988         if (spec->cvlan_tag) {
 989                 MLX5_SET(ste_eth_l2_src_v1, tag, first_vlan_qualifier, DR_STE_CVLAN);
 990                 spec->cvlan_tag = 0;
 991         } else if (spec->svlan_tag) {
 992                 MLX5_SET(ste_eth_l2_src_v1, tag, first_vlan_qualifier, DR_STE_SVLAN);
 993                 spec->svlan_tag = 0;
 994         }
 995
 996         if (inner) {
 997                 if (misc_spec->inner_second_cvlan_tag) {
 998                         MLX5_SET(ste_eth_l2_src_v1, tag, second_vlan_qualifier, DR_STE_CVLAN);
 999                         misc_spec->inner_second_cvlan_tag = 0;
1000                 } else if (misc_spec->inner_second_svlan_tag) {
1001                         MLX5_SET(ste_eth_l2_src_v1, tag, second_vlan_qualifier, DR_STE_SVLAN);
1002                         misc_spec->inner_second_svlan_tag = 0;
1003                 }
1004
1005                 DR_STE_SET_TAG(eth_l2_src_v1, tag, second_vlan_id, misc_spec, inner_second_vid);
1006                 DR_STE_SET_TAG(eth_l2_src_v1, tag, second_cfi, misc_spec, inner_second_cfi);
1007                 DR_STE_SET_TAG(eth_l2_src_v1, tag, second_priority, misc_spec, inner_second_prio);
1008         } else {
1009                 if (misc_spec->outer_second_cvlan_tag) {
1010                         MLX5_SET(ste_eth_l2_src_v1, tag, second_vlan_qualifier, DR_STE_CVLAN);
1011                         misc_spec->outer_second_cvlan_tag = 0;
1012                 } else if (misc_spec->outer_second_svlan_tag) {
1013                         MLX5_SET(ste_eth_l2_src_v1, tag, second_vlan_qualifier, DR_STE_SVLAN);
1014                         misc_spec->outer_second_svlan_tag = 0;
1015                 }
1016                 DR_STE_SET_TAG(eth_l2_src_v1, tag, second_vlan_id, misc_spec, outer_second_vid);
1017                 DR_STE_SET_TAG(eth_l2_src_v1, tag, second_cfi, misc_spec, outer_second_cfi);
1018                 DR_STE_SET_TAG(eth_l2_src_v1, tag, second_priority, misc_spec, outer_second_prio);
1019         }
1020
1021         return 0;
1022 }
1023
1024 static void dr_ste_v1_build_eth_l2_src_bit_mask(struct mlx5dr_match_param *value,
1025                                                 bool inner, u8 *bit_mask)
1026 {
1027         struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer;
1028
1029         DR_STE_SET_TAG(eth_l2_src_v1, bit_mask, smac_47_16, mask, smac_47_16);
1030         DR_STE_SET_TAG(eth_l2_src_v1, bit_mask, smac_15_0, mask, smac_15_0);
1031
1032         dr_ste_v1_build_eth_l2_src_or_dst_bit_mask(value, inner, bit_mask);
1033 }
1034
1035 static int dr_ste_v1_build_eth_l2_src_tag(struct mlx5dr_match_param *value,
1036                                           struct mlx5dr_ste_build *sb,
1037                                           u8 *tag)
1038 {
1039         struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer;
1040
1041         DR_STE_SET_TAG(eth_l2_src_v1, tag, smac_47_16, spec, smac_47_16);
1042         DR_STE_SET_TAG(eth_l2_src_v1, tag, smac_15_0, spec, smac_15_0);
1043
1044         return dr_ste_v1_build_eth_l2_src_or_dst_tag(value, sb->inner, tag);
1045 }
1046
1047 static void dr_ste_v1_build_eth_l2_src_init(struct mlx5dr_ste_build *sb,
1048                                             struct mlx5dr_match_param *mask)
1049 {
1050         dr_ste_v1_build_eth_l2_src_bit_mask(mask, sb->inner, sb->bit_mask);
1051
1052         sb->lu_type = DR_STE_CALC_DFNR_TYPE(ETHL2_SRC, sb->inner);
1053         sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
1054         sb->ste_build_tag_func = &dr_ste_v1_build_eth_l2_src_tag;
1055 }
1056
1057 static void dr_ste_v1_build_eth_l2_dst_bit_mask(struct mlx5dr_match_param *value,
1058                                                 bool inner, u8 *bit_mask)
1059 {
1060         struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer;
1061
1062         DR_STE_SET_TAG(eth_l2_dst_v1, bit_mask, dmac_47_16, mask, dmac_47_16);
1063         DR_STE_SET_TAG(eth_l2_dst_v1, bit_mask, dmac_15_0, mask, dmac_15_0);
1064
1065         dr_ste_v1_build_eth_l2_src_or_dst_bit_mask(value, inner, bit_mask);
1066 }
1067
1068 static int dr_ste_v1_build_eth_l2_dst_tag(struct mlx5dr_match_param *value,
1069                                           struct mlx5dr_ste_build *sb,
1070                                           u8 *tag)
1071 {
1072         struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer;
1073
1074         DR_STE_SET_TAG(eth_l2_dst_v1, tag, dmac_47_16, spec, dmac_47_16);
1075         DR_STE_SET_TAG(eth_l2_dst_v1, tag, dmac_15_0, spec, dmac_15_0);
1076
1077         return dr_ste_v1_build_eth_l2_src_or_dst_tag(value, sb->inner, tag);
1078 }
1079
1080 static void dr_ste_v1_build_eth_l2_dst_init(struct mlx5dr_ste_build *sb,
1081                                             struct mlx5dr_match_param *mask)
1082 {
1083         dr_ste_v1_build_eth_l2_dst_bit_mask(mask, sb->inner, sb->bit_mask);
1084
1085         sb->lu_type = DR_STE_CALC_DFNR_TYPE(ETHL2, sb->inner);
1086         sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
1087         sb->ste_build_tag_func = &dr_ste_v1_build_eth_l2_dst_tag;
1088 }
1089
1090 static void dr_ste_v1_build_eth_l2_tnl_bit_mask(struct mlx5dr_match_param *value,
1091                                                 bool inner, u8 *bit_mask)
1092 {
1093         struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer;
1094         struct mlx5dr_match_misc *misc = &value->misc;
1095
1096         DR_STE_SET_TAG(eth_l2_tnl_v1, bit_mask, dmac_47_16, mask, dmac_47_16);
1097         DR_STE_SET_TAG(eth_l2_tnl_v1, bit_mask, dmac_15_0, mask, dmac_15_0);
1098         DR_STE_SET_TAG(eth_l2_tnl_v1, bit_mask, first_vlan_id, mask, first_vid);
1099         DR_STE_SET_TAG(eth_l2_tnl_v1, bit_mask, first_cfi, mask, first_cfi);
1100         DR_STE_SET_TAG(eth_l2_tnl_v1, bit_mask, first_priority, mask, first_prio);
1101         DR_STE_SET_TAG(eth_l2_tnl_v1, bit_mask, ip_fragmented, mask, frag);
1102         DR_STE_SET_TAG(eth_l2_tnl_v1, bit_mask, l3_ethertype, mask, ethertype);
1103         DR_STE_SET_ONES(eth_l2_tnl_v1, bit_mask, l3_type, mask, ip_version);
1104
1105         if (misc->vxlan_vni) {
1106                 MLX5_SET(ste_eth_l2_tnl_v1, bit_mask,
1107                          l2_tunneling_network_id, (misc->vxlan_vni << 8));
1108                 misc->vxlan_vni = 0;
1109         }
1110
1111         if (mask->svlan_tag || mask->cvlan_tag) {
1112                 MLX5_SET(ste_eth_l2_tnl_v1, bit_mask, first_vlan_qualifier, -1);
1113                 mask->cvlan_tag = 0;
1114                 mask->svlan_tag = 0;
1115         }
1116 }
1117
1118 static int dr_ste_v1_build_eth_l2_tnl_tag(struct mlx5dr_match_param *value,
1119                                           struct mlx5dr_ste_build *sb,
1120                                           u8 *tag)
1121 {
1122         struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer;
1123         struct mlx5dr_match_misc *misc = &value->misc;
1124
1125         DR_STE_SET_TAG(eth_l2_tnl_v1, tag, dmac_47_16, spec, dmac_47_16);
1126         DR_STE_SET_TAG(eth_l2_tnl_v1, tag, dmac_15_0, spec, dmac_15_0);
1127         DR_STE_SET_TAG(eth_l2_tnl_v1, tag, first_vlan_id, spec, first_vid);
1128         DR_STE_SET_TAG(eth_l2_tnl_v1, tag, first_cfi, spec, first_cfi);
1129         DR_STE_SET_TAG(eth_l2_tnl_v1, tag, ip_fragmented, spec, frag);
1130         DR_STE_SET_TAG(eth_l2_tnl_v1, tag, first_priority, spec, first_prio);
1131         DR_STE_SET_TAG(eth_l2_tnl_v1, tag, l3_ethertype, spec, ethertype);
1132
1133         if (misc->vxlan_vni) {
1134                 MLX5_SET(ste_eth_l2_tnl_v1, tag, l2_tunneling_network_id,
1135                          (misc->vxlan_vni << 8));
1136                 misc->vxlan_vni = 0;
1137         }
1138
1139         if (spec->cvlan_tag) {
1140                 MLX5_SET(ste_eth_l2_tnl_v1, tag, first_vlan_qualifier, DR_STE_CVLAN);
1141                 spec->cvlan_tag = 0;
1142         } else if (spec->svlan_tag) {
1143                 MLX5_SET(ste_eth_l2_tnl_v1, tag, first_vlan_qualifier, DR_STE_SVLAN);
1144                 spec->svlan_tag = 0;
1145         }
1146
1147         if (spec->ip_version == IP_VERSION_IPV4) {
1148                 MLX5_SET(ste_eth_l2_tnl_v1, tag, l3_type, STE_IPV4);
1149                 spec->ip_version = 0;
1150         } else if (spec->ip_version == IP_VERSION_IPV6) {
1151                 MLX5_SET(ste_eth_l2_tnl_v1, tag, l3_type, STE_IPV6);
1152                 spec->ip_version = 0;
1153         } else if (spec->ip_version) {
1154                 return -EINVAL;
1155         }
1156
1157         return 0;
1158 }
1159
1160 static void dr_ste_v1_build_eth_l2_tnl_init(struct mlx5dr_ste_build *sb,
1161                                             struct mlx5dr_match_param *mask)
1162 {
1163         dr_ste_v1_build_eth_l2_tnl_bit_mask(mask, sb->inner, sb->bit_mask);
1164
1165         sb->lu_type = DR_STE_V1_LU_TYPE_ETHL2_TNL;
1166         sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
1167         sb->ste_build_tag_func = &dr_ste_v1_build_eth_l2_tnl_tag;
1168 }
1169
1170 static int dr_ste_v1_build_eth_l3_ipv4_misc_tag(struct mlx5dr_match_param *value,
1171                                                 struct mlx5dr_ste_build *sb,
1172                                                 u8 *tag)
1173 {
1174         struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer;
1175
1176         DR_STE_SET_TAG(eth_l3_ipv4_misc_v1, tag, time_to_live, spec, ttl_hoplimit);
1177
1178         return 0;
1179 }
1180
1181 static void dr_ste_v1_build_eth_l3_ipv4_misc_init(struct mlx5dr_ste_build *sb,
1182                                                   struct mlx5dr_match_param *mask)
1183 {
1184         dr_ste_v1_build_eth_l3_ipv4_misc_tag(mask, sb, sb->bit_mask);
1185
1186         sb->lu_type = DR_STE_CALC_DFNR_TYPE(ETHL3_IPV4_MISC, sb->inner);
1187         sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
1188         sb->ste_build_tag_func = &dr_ste_v1_build_eth_l3_ipv4_misc_tag;
1189 }
1190
1191 static int dr_ste_v1_build_eth_ipv6_l3_l4_tag(struct mlx5dr_match_param *value,
1192                                               struct mlx5dr_ste_build *sb,
1193                                               u8 *tag)
1194 {
1195         struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer;
1196         struct mlx5dr_match_misc *misc = &value->misc;
1197
1198         DR_STE_SET_TAG(eth_l4_v1, tag, dst_port, spec, tcp_dport);
1199         DR_STE_SET_TAG(eth_l4_v1, tag, src_port, spec, tcp_sport);
1200         DR_STE_SET_TAG(eth_l4_v1, tag, dst_port, spec, udp_dport);
1201         DR_STE_SET_TAG(eth_l4_v1, tag, src_port, spec, udp_sport);
1202         DR_STE_SET_TAG(eth_l4_v1, tag, protocol, spec, ip_protocol);
1203         DR_STE_SET_TAG(eth_l4_v1, tag, fragmented, spec, frag);
1204         DR_STE_SET_TAG(eth_l4_v1, tag, dscp, spec, ip_dscp);
1205         DR_STE_SET_TAG(eth_l4_v1, tag, ecn, spec, ip_ecn);
1206         DR_STE_SET_TAG(eth_l4_v1, tag, ipv6_hop_limit, spec, ttl_hoplimit);
1207
1208         if (sb->inner)
1209                 DR_STE_SET_TAG(eth_l4_v1, tag, flow_label, misc, inner_ipv6_flow_label);
1210         else
1211                 DR_STE_SET_TAG(eth_l4_v1, tag, flow_label, misc, outer_ipv6_flow_label);
1212
1213         if (spec->tcp_flags) {
1214                 DR_STE_SET_TCP_FLAGS(eth_l4_v1, tag, spec);
1215                 spec->tcp_flags = 0;
1216         }
1217
1218         return 0;
1219 }
1220
1221 static void dr_ste_v1_build_eth_ipv6_l3_l4_init(struct mlx5dr_ste_build *sb,
1222                                                 struct mlx5dr_match_param *mask)
1223 {
1224         dr_ste_v1_build_eth_ipv6_l3_l4_tag(mask, sb, sb->bit_mask);
1225
1226         sb->lu_type = DR_STE_CALC_DFNR_TYPE(ETHL4, sb->inner);
1227         sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
1228         sb->ste_build_tag_func = &dr_ste_v1_build_eth_ipv6_l3_l4_tag;
1229 }
1230
1231 static int dr_ste_v1_build_mpls_tag(struct mlx5dr_match_param *value,
1232                                     struct mlx5dr_ste_build *sb,
1233                                     u8 *tag)
1234 {
1235         struct mlx5dr_match_misc2 *misc2 = &value->misc2;
1236
1237         if (sb->inner)
1238                 DR_STE_SET_MPLS(mpls_v1, misc2, inner, tag);
1239         else
1240                 DR_STE_SET_MPLS(mpls_v1, misc2, outer, tag);
1241
1242         return 0;
1243 }
1244
1245 static void dr_ste_v1_build_mpls_init(struct mlx5dr_ste_build *sb,
1246                                       struct mlx5dr_match_param *mask)
1247 {
1248         dr_ste_v1_build_mpls_tag(mask, sb, sb->bit_mask);
1249
1250         sb->lu_type = DR_STE_CALC_DFNR_TYPE(MPLS, sb->inner);
1251         sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
1252         sb->ste_build_tag_func = &dr_ste_v1_build_mpls_tag;
1253 }
1254
1255 static int dr_ste_v1_build_tnl_gre_tag(struct mlx5dr_match_param *value,
1256                                        struct mlx5dr_ste_build *sb,
1257                                        u8 *tag)
1258 {
1259         struct  mlx5dr_match_misc *misc = &value->misc;
1260
1261         DR_STE_SET_TAG(gre_v1, tag, gre_protocol, misc, gre_protocol);
1262         DR_STE_SET_TAG(gre_v1, tag, gre_k_present, misc, gre_k_present);
1263         DR_STE_SET_TAG(gre_v1, tag, gre_key_h, misc, gre_key_h);
1264         DR_STE_SET_TAG(gre_v1, tag, gre_key_l, misc, gre_key_l);
1265
1266         DR_STE_SET_TAG(gre_v1, tag, gre_c_present, misc, gre_c_present);
1267         DR_STE_SET_TAG(gre_v1, tag, gre_s_present, misc, gre_s_present);
1268
1269         return 0;
1270 }
1271
1272 static void dr_ste_v1_build_tnl_gre_init(struct mlx5dr_ste_build *sb,
1273                                          struct mlx5dr_match_param *mask)
1274 {
1275         dr_ste_v1_build_tnl_gre_tag(mask, sb, sb->bit_mask);
1276
1277         sb->lu_type = DR_STE_V1_LU_TYPE_GRE;
1278         sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
1279         sb->ste_build_tag_func = &dr_ste_v1_build_tnl_gre_tag;
1280 }
1281
1282 static int dr_ste_v1_build_tnl_mpls_tag(struct mlx5dr_match_param *value,
1283                                         struct mlx5dr_ste_build *sb,
1284                                         u8 *tag)
1285 {
1286         struct mlx5dr_match_misc2 *misc2 = &value->misc2;
1287
1288         if (DR_STE_IS_OUTER_MPLS_OVER_GRE_SET(misc2)) {
1289                 DR_STE_SET_TAG(mpls_v1, tag, mpls0_label,
1290                                misc2, outer_first_mpls_over_gre_label);
1291
1292                 DR_STE_SET_TAG(mpls_v1, tag, mpls0_exp,
1293                                misc2, outer_first_mpls_over_gre_exp);
1294
1295                 DR_STE_SET_TAG(mpls_v1, tag, mpls0_s_bos,
1296                                misc2, outer_first_mpls_over_gre_s_bos);
1297
1298                 DR_STE_SET_TAG(mpls_v1, tag, mpls0_ttl,
1299                                misc2, outer_first_mpls_over_gre_ttl);
1300         } else {
1301                 DR_STE_SET_TAG(mpls_v1, tag, mpls0_label,
1302                                misc2, outer_first_mpls_over_udp_label);
1303
1304                 DR_STE_SET_TAG(mpls_v1, tag, mpls0_exp,
1305                                misc2, outer_first_mpls_over_udp_exp);
1306
1307                 DR_STE_SET_TAG(mpls_v1, tag, mpls0_s_bos,
1308                                misc2, outer_first_mpls_over_udp_s_bos);
1309
1310                 DR_STE_SET_TAG(mpls_v1, tag, mpls0_ttl,
1311                                misc2, outer_first_mpls_over_udp_ttl);
1312         }
1313
1314         return 0;
1315 }
1316
1317 static void dr_ste_v1_build_tnl_mpls_init(struct mlx5dr_ste_build *sb,
1318                                           struct mlx5dr_match_param *mask)
1319 {
1320         dr_ste_v1_build_tnl_mpls_tag(mask, sb, sb->bit_mask);
1321
1322         sb->lu_type = DR_STE_V1_LU_TYPE_MPLS_I;
1323         sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
1324         sb->ste_build_tag_func = &dr_ste_v1_build_tnl_mpls_tag;
1325 }
1326
1327 static int dr_ste_v1_build_icmp_tag(struct mlx5dr_match_param *value,
1328                                     struct mlx5dr_ste_build *sb,
1329                                     u8 *tag)
1330 {
1331         struct mlx5dr_match_misc3 *misc3 = &value->misc3;
1332         bool is_ipv4 = DR_MASK_IS_ICMPV4_SET(misc3);
1333         u32 *icmp_header_data;
1334         u8 *icmp_type;
1335         u8 *icmp_code;
1336
1337         if (is_ipv4) {
1338                 icmp_header_data        = &misc3->icmpv4_header_data;
1339                 icmp_type               = &misc3->icmpv4_type;
1340                 icmp_code               = &misc3->icmpv4_code;
1341         } else {
1342                 icmp_header_data        = &misc3->icmpv6_header_data;
1343                 icmp_type               = &misc3->icmpv6_type;
1344                 icmp_code               = &misc3->icmpv6_code;
1345         }
1346
1347         MLX5_SET(ste_icmp_v1, tag, icmp_header_data, *icmp_header_data);
1348         MLX5_SET(ste_icmp_v1, tag, icmp_type, *icmp_type);
1349         MLX5_SET(ste_icmp_v1, tag, icmp_code, *icmp_code);
1350
1351         *icmp_header_data = 0;
1352         *icmp_type = 0;
1353         *icmp_code = 0;
1354
1355         return 0;
1356 }
1357
1358 static int dr_ste_v1_build_icmp_init(struct mlx5dr_ste_build *sb,
1359                                      struct mlx5dr_match_param *mask)
1360 {
1361         dr_ste_v1_build_icmp_tag(mask, sb, sb->bit_mask);
1362
1363         sb->lu_type = DR_STE_V1_LU_TYPE_ETHL4_MISC_O;
1364         sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
1365         sb->ste_build_tag_func = &dr_ste_v1_build_icmp_tag;
1366
1367         return 0;
1368 }
1369
1370 static int dr_ste_v1_build_general_purpose_tag(struct mlx5dr_match_param *value,
1371                                                struct mlx5dr_ste_build *sb,
1372                                                u8 *tag)
1373 {
1374         struct mlx5dr_match_misc2 *misc2 = &value->misc2;
1375
1376         DR_STE_SET_TAG(general_purpose, tag, general_purpose_lookup_field,
1377                        misc2, metadata_reg_a);
1378
1379         return 0;
1380 }
1381
1382 static void dr_ste_v1_build_general_purpose_init(struct mlx5dr_ste_build *sb,
1383                                                  struct mlx5dr_match_param *mask)
1384 {
1385         dr_ste_v1_build_general_purpose_tag(mask, sb, sb->bit_mask);
1386
1387         sb->lu_type = DR_STE_V1_LU_TYPE_GENERAL_PURPOSE;
1388         sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
1389         sb->ste_build_tag_func = &dr_ste_v1_build_general_purpose_tag;
1390 }
1391
1392 static int dr_ste_v1_build_eth_l4_misc_tag(struct mlx5dr_match_param *value,
1393                                            struct mlx5dr_ste_build *sb,
1394                                            u8 *tag)
1395 {
1396         struct mlx5dr_match_misc3 *misc3 = &value->misc3;
1397
1398         if (sb->inner) {
1399                 DR_STE_SET_TAG(eth_l4_misc_v1, tag, seq_num, misc3, inner_tcp_seq_num);
1400                 DR_STE_SET_TAG(eth_l4_misc_v1, tag, ack_num, misc3, inner_tcp_ack_num);
1401         } else {
1402                 DR_STE_SET_TAG(eth_l4_misc_v1, tag, seq_num, misc3, outer_tcp_seq_num);
1403                 DR_STE_SET_TAG(eth_l4_misc_v1, tag, ack_num, misc3, outer_tcp_ack_num);
1404         }
1405
1406         return 0;
1407 }
1408
1409 static void dr_ste_v1_build_eth_l4_misc_init(struct mlx5dr_ste_build *sb,
1410                                              struct mlx5dr_match_param *mask)
1411 {
1412         dr_ste_v1_build_eth_l4_misc_tag(mask, sb, sb->bit_mask);
1413
1414         sb->lu_type = DR_STE_V1_LU_TYPE_ETHL4_MISC_O;
1415         sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
1416         sb->ste_build_tag_func = &dr_ste_v1_build_eth_l4_misc_tag;
1417 }
1418
1419 static int
1420 dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_tag(struct mlx5dr_match_param *value,
1421                                               struct mlx5dr_ste_build *sb,
1422                                               u8 *tag)
1423 {
1424         struct mlx5dr_match_misc3 *misc3 = &value->misc3;
1425
1426         DR_STE_SET_TAG(flex_parser_tnl_vxlan_gpe, tag,
1427                        outer_vxlan_gpe_flags, misc3,
1428                        outer_vxlan_gpe_flags);
1429         DR_STE_SET_TAG(flex_parser_tnl_vxlan_gpe, tag,
1430                        outer_vxlan_gpe_next_protocol, misc3,
1431                        outer_vxlan_gpe_next_protocol);
1432         DR_STE_SET_TAG(flex_parser_tnl_vxlan_gpe, tag,
1433                        outer_vxlan_gpe_vni, misc3,
1434                        outer_vxlan_gpe_vni);
1435
1436         return 0;
1437 }
1438
1439 static void
1440 dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_init(struct mlx5dr_ste_build *sb,
1441                                                struct mlx5dr_match_param *mask)
1442 {
1443         dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_tag(mask, sb, sb->bit_mask);
1444
1445         sb->lu_type = DR_STE_V1_LU_TYPE_FLEX_PARSER_TNL_HEADER;
1446         sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
1447         sb->ste_build_tag_func = &dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_tag;
1448 }
1449
1450 static int
1451 dr_ste_v1_build_flex_parser_tnl_geneve_tag(struct mlx5dr_match_param *value,
1452                                            struct mlx5dr_ste_build *sb,
1453                                            u8 *tag)
1454 {
1455         struct mlx5dr_match_misc *misc = &value->misc;
1456
1457         DR_STE_SET_TAG(flex_parser_tnl_geneve, tag,
1458                        geneve_protocol_type, misc, geneve_protocol_type);
1459         DR_STE_SET_TAG(flex_parser_tnl_geneve, tag,
1460                        geneve_oam, misc, geneve_oam);
1461         DR_STE_SET_TAG(flex_parser_tnl_geneve, tag,
1462                        geneve_opt_len, misc, geneve_opt_len);
1463         DR_STE_SET_TAG(flex_parser_tnl_geneve, tag,
1464                        geneve_vni, misc, geneve_vni);
1465
1466         return 0;
1467 }
1468
1469 static void
1470 dr_ste_v1_build_flex_parser_tnl_geneve_init(struct mlx5dr_ste_build *sb,
1471                                             struct mlx5dr_match_param *mask)
1472 {
1473         dr_ste_v1_build_flex_parser_tnl_geneve_tag(mask, sb, sb->bit_mask);
1474
1475         sb->lu_type = DR_STE_V1_LU_TYPE_FLEX_PARSER_TNL_HEADER;
1476         sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
1477         sb->ste_build_tag_func = &dr_ste_v1_build_flex_parser_tnl_geneve_tag;
1478 }
1479
1480 static int dr_ste_v1_build_register_0_tag(struct mlx5dr_match_param *value,
1481                                           struct mlx5dr_ste_build *sb,
1482                                           u8 *tag)
1483 {
1484         struct mlx5dr_match_misc2 *misc2 = &value->misc2;
1485
1486         DR_STE_SET_TAG(register_0, tag, register_0_h, misc2, metadata_reg_c_0);
1487         DR_STE_SET_TAG(register_0, tag, register_0_l, misc2, metadata_reg_c_1);
1488         DR_STE_SET_TAG(register_0, tag, register_1_h, misc2, metadata_reg_c_2);
1489         DR_STE_SET_TAG(register_0, tag, register_1_l, misc2, metadata_reg_c_3);
1490
1491         return 0;
1492 }
1493
1494 static void dr_ste_v1_build_register_0_init(struct mlx5dr_ste_build *sb,
1495                                             struct mlx5dr_match_param *mask)
1496 {
1497         dr_ste_v1_build_register_0_tag(mask, sb, sb->bit_mask);
1498
1499         sb->lu_type = DR_STE_V1_LU_TYPE_STEERING_REGISTERS_0;
1500         sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
1501         sb->ste_build_tag_func = &dr_ste_v1_build_register_0_tag;
1502 }
1503
1504 static int dr_ste_v1_build_register_1_tag(struct mlx5dr_match_param *value,
1505                                           struct mlx5dr_ste_build *sb,
1506                                           u8 *tag)
1507 {
1508         struct mlx5dr_match_misc2 *misc2 = &value->misc2;
1509
1510         DR_STE_SET_TAG(register_1, tag, register_2_h, misc2, metadata_reg_c_4);
1511         DR_STE_SET_TAG(register_1, tag, register_2_l, misc2, metadata_reg_c_5);
1512         DR_STE_SET_TAG(register_1, tag, register_3_h, misc2, metadata_reg_c_6);
1513         DR_STE_SET_TAG(register_1, tag, register_3_l, misc2, metadata_reg_c_7);
1514
1515         return 0;
1516 }
1517
1518 static void dr_ste_v1_build_register_1_init(struct mlx5dr_ste_build *sb,
1519                                             struct mlx5dr_match_param *mask)
1520 {
1521         dr_ste_v1_build_register_1_tag(mask, sb, sb->bit_mask);
1522
1523         sb->lu_type = DR_STE_V1_LU_TYPE_STEERING_REGISTERS_1;
1524         sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
1525         sb->ste_build_tag_func = &dr_ste_v1_build_register_1_tag;
1526 }
1527
1528 static void dr_ste_v1_build_src_gvmi_qpn_bit_mask(struct mlx5dr_match_param *value,
1529                                                   u8 *bit_mask)
1530 {
1531         struct mlx5dr_match_misc *misc_mask = &value->misc;
1532
1533         DR_STE_SET_ONES(src_gvmi_qp_v1, bit_mask, source_gvmi, misc_mask, source_port);
1534         DR_STE_SET_ONES(src_gvmi_qp_v1, bit_mask, source_qp, misc_mask, source_sqn);
1535 }
1536
1537 static int dr_ste_v1_build_src_gvmi_qpn_tag(struct mlx5dr_match_param *value,
1538                                             struct mlx5dr_ste_build *sb,
1539                                             u8 *tag)
1540 {
1541         struct mlx5dr_match_misc *misc = &value->misc;
1542         struct mlx5dr_cmd_vport_cap *vport_cap;
1543         struct mlx5dr_domain *dmn = sb->dmn;
1544         struct mlx5dr_cmd_caps *caps;
1545         u8 *bit_mask = sb->bit_mask;
1546
1547         DR_STE_SET_TAG(src_gvmi_qp_v1, tag, source_qp, misc, source_sqn);
1548
1549         if (sb->vhca_id_valid) {
1550                 /* Find port GVMI based on the eswitch_owner_vhca_id */
1551                 if (misc->source_eswitch_owner_vhca_id == dmn->info.caps.gvmi)
1552                         caps = &dmn->info.caps;
1553                 else if (dmn->peer_dmn && (misc->source_eswitch_owner_vhca_id ==
1554                                            dmn->peer_dmn->info.caps.gvmi))
1555                         caps = &dmn->peer_dmn->info.caps;
1556                 else
1557                         return -EINVAL;
1558
1559                  misc->source_eswitch_owner_vhca_id = 0;
1560         } else {
1561                 caps = &dmn->info.caps;
1562         }
1563
1564         if (!MLX5_GET(ste_src_gvmi_qp_v1, bit_mask, source_gvmi))
1565                 return 0;
1566
1567         vport_cap = mlx5dr_get_vport_cap(caps, misc->source_port);
1568         if (!vport_cap) {
1569                 mlx5dr_err(dmn, "Vport 0x%x is disabled or invalid\n",
1570                            misc->source_port);
1571                 return -EINVAL;
1572         }
1573
1574         if (vport_cap->vport_gvmi)
1575                 MLX5_SET(ste_src_gvmi_qp_v1, tag, source_gvmi, vport_cap->vport_gvmi);
1576
1577         misc->source_port = 0;
1578         return 0;
1579 }
1580
1581 static void dr_ste_v1_build_src_gvmi_qpn_init(struct mlx5dr_ste_build *sb,
1582                                               struct mlx5dr_match_param *mask)
1583 {
1584         dr_ste_v1_build_src_gvmi_qpn_bit_mask(mask, sb->bit_mask);
1585
1586         sb->lu_type = DR_STE_V1_LU_TYPE_SRC_QP_GVMI;
1587         sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask);
1588         sb->ste_build_tag_func = &dr_ste_v1_build_src_gvmi_qpn_tag;
1589 }
1590
1591 struct mlx5dr_ste_ctx ste_ctx_v1 = {
1592         /* Builders */
1593         .build_eth_l2_src_dst_init      = &dr_ste_v1_build_eth_l2_src_dst_init,
1594         .build_eth_l3_ipv6_src_init     = &dr_ste_v1_build_eth_l3_ipv6_src_init,
1595         .build_eth_l3_ipv6_dst_init     = &dr_ste_v1_build_eth_l3_ipv6_dst_init,
1596         .build_eth_l3_ipv4_5_tuple_init = &dr_ste_v1_build_eth_l3_ipv4_5_tuple_init,
1597         .build_eth_l2_src_init          = &dr_ste_v1_build_eth_l2_src_init,
1598         .build_eth_l2_dst_init          = &dr_ste_v1_build_eth_l2_dst_init,
1599         .build_eth_l2_tnl_init          = &dr_ste_v1_build_eth_l2_tnl_init,
1600         .build_eth_l3_ipv4_misc_init    = &dr_ste_v1_build_eth_l3_ipv4_misc_init,
1601         .build_eth_ipv6_l3_l4_init      = &dr_ste_v1_build_eth_ipv6_l3_l4_init,
1602         .build_mpls_init                = &dr_ste_v1_build_mpls_init,
1603         .build_tnl_gre_init             = &dr_ste_v1_build_tnl_gre_init,
1604         .build_tnl_mpls_init            = &dr_ste_v1_build_tnl_mpls_init,
1605         .build_icmp_init                = &dr_ste_v1_build_icmp_init,
1606         .build_general_purpose_init     = &dr_ste_v1_build_general_purpose_init,
1607         .build_eth_l4_misc_init         = &dr_ste_v1_build_eth_l4_misc_init,
1608         .build_tnl_vxlan_gpe_init       = &dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_init,
1609         .build_tnl_geneve_init          = &dr_ste_v1_build_flex_parser_tnl_geneve_init,
1610         .build_register_0_init          = &dr_ste_v1_build_register_0_init,
1611         .build_register_1_init          = &dr_ste_v1_build_register_1_init,
1612         .build_src_gvmi_qpn_init        = &dr_ste_v1_build_src_gvmi_qpn_init,
1613         /* Getters and Setters */
1614         .ste_init                       = &dr_ste_v1_init,
1615         .set_next_lu_type               = &dr_ste_v1_set_next_lu_type,
1616         .get_next_lu_type               = &dr_ste_v1_get_next_lu_type,
1617         .set_miss_addr                  = &dr_ste_v1_set_miss_addr,
1618         .get_miss_addr                  = &dr_ste_v1_get_miss_addr,
1619         .set_hit_addr                   = &dr_ste_v1_set_hit_addr,
1620         .set_byte_mask                  = &dr_ste_v1_set_byte_mask,
1621         .get_byte_mask                  = &dr_ste_v1_get_byte_mask,
1622         /* Actions */
1623         .set_actions_rx                 = &dr_ste_v1_set_actions_rx,
1624         .set_actions_tx                 = &dr_ste_v1_set_actions_tx,
1625         .modify_field_arr_sz            = ARRAY_SIZE(dr_ste_v1_action_modify_field_arr),
1626         .modify_field_arr               = dr_ste_v1_action_modify_field_arr,
1627         .set_action_set                 = &dr_ste_v1_set_action_set,
1628         .set_action_add                 = &dr_ste_v1_set_action_add,
1629         .set_action_copy                = &dr_ste_v1_set_action_copy,
1630         .set_action_decap_l3_list       = &dr_ste_v1_set_action_decap_l3_list,
1631         /* Send */
1632         .prepare_for_postsend           = &dr_ste_v1_prepare_for_postsend,
1633 };