2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/etherdevice.h>
34 #include <linux/idr.h>
35 #include <linux/mlx5/driver.h>
36 #include <linux/mlx5/mlx5_ifc.h>
37 #include <linux/mlx5/vport.h>
38 #include <linux/mlx5/fs.h>
39 #include "mlx5_core.h"
41 #include "esw/indir_table.h"
42 #include "esw/acl/ofld.h"
46 #include "lib/devcom.h"
48 #include "lib/fs_chains.h"
50 #include "en/mapping.h"
52 #define mlx5_esw_for_each_rep(esw, i, rep) \
53 xa_for_each(&((esw)->offloads.vport_reps), i, rep)
55 #define mlx5_esw_for_each_sf_rep(esw, i, rep) \
56 xa_for_each_marked(&((esw)->offloads.vport_reps), i, rep, MLX5_ESW_VPT_SF)
58 #define mlx5_esw_for_each_vf_rep(esw, index, rep) \
59 mlx5_esw_for_each_entry_marked(&((esw)->offloads.vport_reps), index, \
60 rep, (esw)->esw_funcs.num_vfs, MLX5_ESW_VPT_VF)
62 /* There are two match-all miss flows, one for unicast dst mac and
65 #define MLX5_ESW_MISS_FLOWS (2)
66 #define UPLINK_REP_INDEX 0
68 #define MLX5_ESW_VPORT_TBL_SIZE 128
69 #define MLX5_ESW_VPORT_TBL_NUM_GROUPS 4
71 static const struct esw_vport_tbl_namespace mlx5_esw_vport_tbl_mirror_ns = {
72 .max_fte = MLX5_ESW_VPORT_TBL_SIZE,
73 .max_num_groups = MLX5_ESW_VPORT_TBL_NUM_GROUPS,
77 static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
80 return xa_load(&esw->offloads.vport_reps, vport_num);
84 mlx5_eswitch_set_rule_flow_source(struct mlx5_eswitch *esw,
85 struct mlx5_flow_spec *spec,
86 struct mlx5_esw_flow_attr *attr)
88 if (MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) &&
90 spec->flow_context.flow_source =
91 attr->in_rep->vport == MLX5_VPORT_UPLINK ?
92 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK :
93 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
96 /* Actually only the upper 16 bits of reg c0 need to be cleared, but the lower 16 bits
97 * are not needed as well in the following process. So clear them all for simplicity.
100 mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch *esw, struct mlx5_flow_spec *spec)
102 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
105 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
106 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
108 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
109 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
111 if (!memchr_inv(misc2, 0, MLX5_ST_SZ_BYTES(fte_match_set_misc2)))
112 spec->match_criteria_enable &= ~MLX5_MATCH_MISC_PARAMETERS_2;
117 mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
118 struct mlx5_flow_spec *spec,
119 struct mlx5_flow_attr *attr,
120 struct mlx5_eswitch *src_esw,
126 /* Use metadata matching because vport is not represented by single
127 * VHCA in dual-port RoCE mode, and matching on source vport may fail.
129 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
130 if (mlx5_esw_indir_table_decap_vport(attr))
131 vport = mlx5_esw_indir_table_decap_vport(attr);
132 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
133 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
134 mlx5_eswitch_get_vport_metadata_for_match(src_esw,
137 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
138 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
139 mlx5_eswitch_get_vport_metadata_mask());
141 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
143 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
144 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
146 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
147 MLX5_SET(fte_match_set_misc, misc,
148 source_eswitch_owner_vhca_id,
149 MLX5_CAP_GEN(src_esw->dev, vhca_id));
151 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
152 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
153 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
154 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
155 source_eswitch_owner_vhca_id);
157 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
162 esw_setup_decap_indir(struct mlx5_eswitch *esw,
163 struct mlx5_flow_attr *attr,
164 struct mlx5_flow_spec *spec)
166 struct mlx5_flow_table *ft;
168 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE))
171 ft = mlx5_esw_indir_table_get(esw, attr, spec,
172 mlx5_esw_indir_table_decap_vport(attr), true);
173 return PTR_ERR_OR_ZERO(ft);
177 esw_cleanup_decap_indir(struct mlx5_eswitch *esw,
178 struct mlx5_flow_attr *attr)
180 if (mlx5_esw_indir_table_decap_vport(attr))
181 mlx5_esw_indir_table_put(esw, attr,
182 mlx5_esw_indir_table_decap_vport(attr),
187 esw_setup_sampler_dest(struct mlx5_flow_destination *dest,
188 struct mlx5_flow_act *flow_act,
189 struct mlx5_esw_flow_attr *esw_attr,
192 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
193 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER;
194 dest[i].sampler_id = esw_attr->sample->sampler_id;
200 esw_setup_ft_dest(struct mlx5_flow_destination *dest,
201 struct mlx5_flow_act *flow_act,
202 struct mlx5_eswitch *esw,
203 struct mlx5_flow_attr *attr,
204 struct mlx5_flow_spec *spec,
207 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
208 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
209 dest[i].ft = attr->dest_ft;
211 if (mlx5_esw_indir_table_decap_vport(attr))
212 return esw_setup_decap_indir(esw, attr, spec);
217 esw_setup_slow_path_dest(struct mlx5_flow_destination *dest,
218 struct mlx5_flow_act *flow_act,
219 struct mlx5_fs_chains *chains,
222 if (mlx5_chains_ignore_flow_level_supported(chains))
223 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
224 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
225 dest[i].ft = mlx5_chains_get_tc_end_ft(chains);
229 esw_setup_chain_dest(struct mlx5_flow_destination *dest,
230 struct mlx5_flow_act *flow_act,
231 struct mlx5_fs_chains *chains,
232 u32 chain, u32 prio, u32 level,
235 struct mlx5_flow_table *ft;
237 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
238 ft = mlx5_chains_get_table(chains, chain, prio, level);
242 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
247 static void esw_put_dest_tables_loop(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr,
250 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
251 struct mlx5_fs_chains *chains = esw_chains(esw);
254 for (i = from; i < to; i++)
255 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
256 mlx5_chains_put_table(chains, 0, 1, 0);
257 else if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport,
258 esw_attr->dests[i].mdev))
259 mlx5_esw_indir_table_put(esw, attr, esw_attr->dests[i].rep->vport,
264 esw_is_chain_src_port_rewrite(struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr)
268 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
269 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
275 esw_setup_chain_src_port_rewrite(struct mlx5_flow_destination *dest,
276 struct mlx5_flow_act *flow_act,
277 struct mlx5_eswitch *esw,
278 struct mlx5_fs_chains *chains,
279 struct mlx5_flow_attr *attr,
282 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
285 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE))
288 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) {
289 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain, 1, 0, *i);
291 goto err_setup_chain;
292 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
293 flow_act->pkt_reformat = esw_attr->dests[j].pkt_reformat;
298 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j);
302 static void esw_cleanup_chain_src_port_rewrite(struct mlx5_eswitch *esw,
303 struct mlx5_flow_attr *attr)
305 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
307 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
311 esw_is_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
313 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
316 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
317 if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport,
318 esw_attr->dests[i].mdev))
324 esw_setup_indir_table(struct mlx5_flow_destination *dest,
325 struct mlx5_flow_act *flow_act,
326 struct mlx5_eswitch *esw,
327 struct mlx5_flow_attr *attr,
328 struct mlx5_flow_spec *spec,
329 bool ignore_flow_lvl,
332 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
335 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE))
338 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) {
340 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
341 dest[*i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
343 dest[*i].ft = mlx5_esw_indir_table_get(esw, attr, spec,
344 esw_attr->dests[j].rep->vport, false);
345 if (IS_ERR(dest[*i].ft)) {
346 err = PTR_ERR(dest[*i].ft);
347 goto err_indir_tbl_get;
351 if (mlx5_esw_indir_table_decap_vport(attr)) {
352 err = esw_setup_decap_indir(esw, attr, spec);
354 goto err_indir_tbl_get;
360 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j);
364 static void esw_cleanup_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
366 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
368 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
369 esw_cleanup_decap_indir(esw, attr);
373 esw_cleanup_chain_dest(struct mlx5_fs_chains *chains, u32 chain, u32 prio, u32 level)
375 mlx5_chains_put_table(chains, chain, prio, level);
379 esw_setup_vport_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
380 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
381 int attr_idx, int dest_idx, bool pkt_reformat)
383 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
384 dest[dest_idx].vport.num = esw_attr->dests[attr_idx].rep->vport;
385 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
386 dest[dest_idx].vport.vhca_id =
387 MLX5_CAP_GEN(esw_attr->dests[attr_idx].mdev, vhca_id);
388 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
390 if (esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP) {
392 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
393 flow_act->pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
395 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
396 dest[dest_idx].vport.pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
401 esw_setup_vport_dests(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
402 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
407 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, i++)
408 esw_setup_vport_dest(dest, flow_act, esw, esw_attr, j, i, true);
413 esw_src_port_rewrite_supported(struct mlx5_eswitch *esw)
415 return MLX5_CAP_GEN(esw->dev, reg_c_preserve) &&
416 mlx5_eswitch_vport_match_metadata_enabled(esw) &&
417 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level);
421 esw_setup_dests(struct mlx5_flow_destination *dest,
422 struct mlx5_flow_act *flow_act,
423 struct mlx5_eswitch *esw,
424 struct mlx5_flow_attr *attr,
425 struct mlx5_flow_spec *spec,
428 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
429 struct mlx5_fs_chains *chains = esw_chains(esw);
432 if (!mlx5_eswitch_termtbl_required(esw, attr, flow_act, spec) &&
433 esw_src_port_rewrite_supported(esw))
434 attr->flags |= MLX5_ESW_ATTR_FLAG_SRC_REWRITE;
436 if (attr->flags & MLX5_ESW_ATTR_FLAG_SAMPLE) {
437 esw_setup_sampler_dest(dest, flow_act, esw_attr, *i);
439 } else if (attr->dest_ft) {
440 esw_setup_ft_dest(dest, flow_act, esw, attr, spec, *i);
442 } else if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH) {
443 esw_setup_slow_path_dest(dest, flow_act, chains, *i);
445 } else if (attr->dest_chain) {
446 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain,
449 } else if (esw_is_indir_table(esw, attr)) {
450 err = esw_setup_indir_table(dest, flow_act, esw, attr, spec, true, i);
451 } else if (esw_is_chain_src_port_rewrite(esw, esw_attr)) {
452 err = esw_setup_chain_src_port_rewrite(dest, flow_act, esw, chains, attr, i);
454 *i = esw_setup_vport_dests(dest, flow_act, esw, esw_attr, *i);
461 esw_cleanup_dests(struct mlx5_eswitch *esw,
462 struct mlx5_flow_attr *attr)
464 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
465 struct mlx5_fs_chains *chains = esw_chains(esw);
468 esw_cleanup_decap_indir(esw, attr);
469 } else if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)) {
470 if (attr->dest_chain)
471 esw_cleanup_chain_dest(chains, attr->dest_chain, 1, 0);
472 else if (esw_is_indir_table(esw, attr))
473 esw_cleanup_indir_table(esw, attr);
474 else if (esw_is_chain_src_port_rewrite(esw, esw_attr))
475 esw_cleanup_chain_src_port_rewrite(esw, attr);
479 struct mlx5_flow_handle *
480 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
481 struct mlx5_flow_spec *spec,
482 struct mlx5_flow_attr *attr)
484 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
485 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
486 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
487 struct mlx5_fs_chains *chains = esw_chains(esw);
488 bool split = !!(esw_attr->split_count);
489 struct mlx5_vport_tbl_attr fwd_attr;
490 struct mlx5_flow_handle *rule;
491 struct mlx5_flow_table *fdb;
494 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
495 return ERR_PTR(-EOPNOTSUPP);
497 flow_act.action = attr->action;
498 /* if per flow vlan pop/push is emulated, don't set that into the firmware */
499 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
500 flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
501 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
502 else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
503 flow_act.vlan[0].ethtype = ntohs(esw_attr->vlan_proto[0]);
504 flow_act.vlan[0].vid = esw_attr->vlan_vid[0];
505 flow_act.vlan[0].prio = esw_attr->vlan_prio[0];
506 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
507 flow_act.vlan[1].ethtype = ntohs(esw_attr->vlan_proto[1]);
508 flow_act.vlan[1].vid = esw_attr->vlan_vid[1];
509 flow_act.vlan[1].prio = esw_attr->vlan_prio[1];
513 mlx5_eswitch_set_rule_flow_source(esw, spec, esw_attr);
515 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
518 err = esw_setup_dests(dest, &flow_act, esw, attr, spec, &i);
521 goto err_create_goto_table;
525 if (esw_attr->decap_pkt_reformat)
526 flow_act.pkt_reformat = esw_attr->decap_pkt_reformat;
528 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
529 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
530 dest[i].counter_id = mlx5_fc_id(attr->counter);
534 if (attr->outer_match_level != MLX5_MATCH_NONE)
535 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
536 if (attr->inner_match_level != MLX5_MATCH_NONE)
537 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
539 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
540 flow_act.modify_hdr = attr->modify_hdr;
542 /* esw_attr->sample is allocated only when there is a sample action */
543 if (esw_attr->sample && esw_attr->sample->sample_default_tbl) {
544 fdb = esw_attr->sample->sample_default_tbl;
546 fwd_attr.chain = attr->chain;
547 fwd_attr.prio = attr->prio;
548 fwd_attr.vport = esw_attr->in_rep->vport;
549 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
551 fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
553 if (attr->chain || attr->prio)
554 fdb = mlx5_chains_get_table(chains, attr->chain,
559 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_NO_IN_PORT))
560 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
561 esw_attr->in_mdev->priv.eswitch,
562 esw_attr->in_rep->vport);
565 rule = ERR_CAST(fdb);
569 if (mlx5_eswitch_termtbl_required(esw, attr, &flow_act, spec))
570 rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, esw_attr,
573 rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
577 atomic64_inc(&esw->offloads.num_flows);
583 mlx5_esw_vporttbl_put(esw, &fwd_attr);
584 else if (attr->chain || attr->prio)
585 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
587 esw_cleanup_dests(esw, attr);
588 err_create_goto_table:
592 struct mlx5_flow_handle *
593 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
594 struct mlx5_flow_spec *spec,
595 struct mlx5_flow_attr *attr)
597 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
598 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
599 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
600 struct mlx5_fs_chains *chains = esw_chains(esw);
601 struct mlx5_vport_tbl_attr fwd_attr;
602 struct mlx5_flow_table *fast_fdb;
603 struct mlx5_flow_table *fwd_fdb;
604 struct mlx5_flow_handle *rule;
607 fast_fdb = mlx5_chains_get_table(chains, attr->chain, attr->prio, 0);
608 if (IS_ERR(fast_fdb)) {
609 rule = ERR_CAST(fast_fdb);
613 fwd_attr.chain = attr->chain;
614 fwd_attr.prio = attr->prio;
615 fwd_attr.vport = esw_attr->in_rep->vport;
616 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
617 fwd_fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
618 if (IS_ERR(fwd_fdb)) {
619 rule = ERR_CAST(fwd_fdb);
623 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
624 for (i = 0; i < esw_attr->split_count; i++) {
625 if (esw_is_indir_table(esw, attr))
626 err = esw_setup_indir_table(dest, &flow_act, esw, attr, spec, false, &i);
627 else if (esw_is_chain_src_port_rewrite(esw, esw_attr))
628 err = esw_setup_chain_src_port_rewrite(dest, &flow_act, esw, chains, attr,
631 esw_setup_vport_dest(dest, &flow_act, esw, esw_attr, i, i, false);
635 goto err_chain_src_rewrite;
638 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
639 dest[i].ft = fwd_fdb;
642 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
643 esw_attr->in_mdev->priv.eswitch,
644 esw_attr->in_rep->vport);
646 if (attr->outer_match_level != MLX5_MATCH_NONE)
647 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
649 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
650 rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
653 i = esw_attr->split_count;
654 goto err_chain_src_rewrite;
657 atomic64_inc(&esw->offloads.num_flows);
660 err_chain_src_rewrite:
661 esw_put_dest_tables_loop(esw, attr, 0, i);
662 mlx5_esw_vporttbl_put(esw, &fwd_attr);
664 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
670 __mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
671 struct mlx5_flow_handle *rule,
672 struct mlx5_flow_attr *attr,
675 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
676 struct mlx5_fs_chains *chains = esw_chains(esw);
677 bool split = (esw_attr->split_count > 0);
678 struct mlx5_vport_tbl_attr fwd_attr;
681 mlx5_del_flow_rules(rule);
683 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)) {
684 /* unref the term table */
685 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
686 if (esw_attr->dests[i].termtbl)
687 mlx5_eswitch_termtbl_put(esw, esw_attr->dests[i].termtbl);
691 atomic64_dec(&esw->offloads.num_flows);
693 if (fwd_rule || split) {
694 fwd_attr.chain = attr->chain;
695 fwd_attr.prio = attr->prio;
696 fwd_attr.vport = esw_attr->in_rep->vport;
697 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
701 mlx5_esw_vporttbl_put(esw, &fwd_attr);
702 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
703 esw_put_dest_tables_loop(esw, attr, 0, esw_attr->split_count);
706 mlx5_esw_vporttbl_put(esw, &fwd_attr);
707 else if (attr->chain || attr->prio)
708 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
709 esw_cleanup_dests(esw, attr);
714 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
715 struct mlx5_flow_handle *rule,
716 struct mlx5_flow_attr *attr)
718 __mlx5_eswitch_del_rule(esw, rule, attr, false);
722 mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
723 struct mlx5_flow_handle *rule,
724 struct mlx5_flow_attr *attr)
726 __mlx5_eswitch_del_rule(esw, rule, attr, true);
729 static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val)
731 struct mlx5_eswitch_rep *rep;
735 esw_debug(esw->dev, "%s applying global %s policy\n", __func__, val ? "pop" : "none");
736 mlx5_esw_for_each_host_func_vport(esw, i, rep, esw->esw_funcs.num_vfs) {
737 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
740 err = __mlx5_eswitch_set_vport_vlan(esw, rep->vport, 0, 0, val);
749 static struct mlx5_eswitch_rep *
750 esw_vlan_action_get_vport(struct mlx5_esw_flow_attr *attr, bool push, bool pop)
752 struct mlx5_eswitch_rep *in_rep, *out_rep, *vport = NULL;
754 in_rep = attr->in_rep;
755 out_rep = attr->dests[0].rep;
767 static int esw_add_vlan_action_check(struct mlx5_esw_flow_attr *attr,
768 bool push, bool pop, bool fwd)
770 struct mlx5_eswitch_rep *in_rep, *out_rep;
772 if ((push || pop) && !fwd)
775 in_rep = attr->in_rep;
776 out_rep = attr->dests[0].rep;
778 if (push && in_rep->vport == MLX5_VPORT_UPLINK)
781 if (pop && out_rep->vport == MLX5_VPORT_UPLINK)
784 /* vport has vlan push configured, can't offload VF --> wire rules w.o it */
785 if (!push && !pop && fwd)
786 if (in_rep->vlan && out_rep->vport == MLX5_VPORT_UPLINK)
789 /* protects against (1) setting rules with different vlans to push and
790 * (2) setting rules w.o vlans (attr->vlan = 0) && w. vlans to push (!= 0)
792 if (push && in_rep->vlan_refcount && (in_rep->vlan != attr->vlan_vid[0]))
801 int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
802 struct mlx5_flow_attr *attr)
804 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
805 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
806 struct mlx5_eswitch_rep *vport = NULL;
810 /* nop if we're on the vlan push/pop non emulation mode */
811 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
814 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
815 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
816 fwd = !!((attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) &&
819 mutex_lock(&esw->state_lock);
821 err = esw_add_vlan_action_check(esw_attr, push, pop, fwd);
825 attr->flags &= ~MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
827 vport = esw_vlan_action_get_vport(esw_attr, push, pop);
829 if (!push && !pop && fwd) {
830 /* tracks VF --> wire rules without vlan push action */
831 if (esw_attr->dests[0].rep->vport == MLX5_VPORT_UPLINK) {
832 vport->vlan_refcount++;
833 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
842 if (!(offloads->vlan_push_pop_refcount)) {
843 /* it's the 1st vlan rule, apply global vlan pop policy */
844 err = esw_set_global_vlan_pop(esw, SET_VLAN_STRIP);
848 offloads->vlan_push_pop_refcount++;
851 if (vport->vlan_refcount)
854 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport, esw_attr->vlan_vid[0],
855 0, SET_VLAN_INSERT | SET_VLAN_STRIP);
858 vport->vlan = esw_attr->vlan_vid[0];
860 vport->vlan_refcount++;
864 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
866 mutex_unlock(&esw->state_lock);
870 int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
871 struct mlx5_flow_attr *attr)
873 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
874 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
875 struct mlx5_eswitch_rep *vport = NULL;
879 /* nop if we're on the vlan push/pop non emulation mode */
880 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
883 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_VLAN_HANDLED))
886 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
887 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
888 fwd = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);
890 mutex_lock(&esw->state_lock);
892 vport = esw_vlan_action_get_vport(esw_attr, push, pop);
894 if (!push && !pop && fwd) {
895 /* tracks VF --> wire rules without vlan push action */
896 if (esw_attr->dests[0].rep->vport == MLX5_VPORT_UPLINK)
897 vport->vlan_refcount--;
903 vport->vlan_refcount--;
904 if (vport->vlan_refcount)
905 goto skip_unset_push;
908 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport,
909 0, 0, SET_VLAN_STRIP);
915 offloads->vlan_push_pop_refcount--;
916 if (offloads->vlan_push_pop_refcount)
919 /* no more vlan rules, stop global vlan pop policy */
920 err = esw_set_global_vlan_pop(esw, 0);
923 mutex_unlock(&esw->state_lock);
927 struct mlx5_flow_handle *
928 mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *on_esw,
929 struct mlx5_eswitch_rep *rep,
932 struct mlx5_flow_act flow_act = {0};
933 struct mlx5_flow_destination dest = {};
934 struct mlx5_flow_handle *flow_rule;
935 struct mlx5_flow_spec *spec;
938 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
940 flow_rule = ERR_PTR(-ENOMEM);
944 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
945 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
946 /* source vport is the esw manager */
947 MLX5_SET(fte_match_set_misc, misc, source_port, rep->esw->manager_vport);
948 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
949 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
950 MLX5_CAP_GEN(rep->esw->dev, vhca_id));
952 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
953 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
954 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
955 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
956 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
957 source_eswitch_owner_vhca_id);
959 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
960 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
961 dest.vport.num = rep->vport;
962 dest.vport.vhca_id = MLX5_CAP_GEN(rep->esw->dev, vhca_id);
963 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
964 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
966 flow_rule = mlx5_add_flow_rules(on_esw->fdb_table.offloads.slow_fdb,
967 spec, &flow_act, &dest, 1);
968 if (IS_ERR(flow_rule))
969 esw_warn(on_esw->dev, "FDB: Failed to add send to vport rule err %ld\n",
975 EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
977 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
979 mlx5_del_flow_rules(rule);
982 static void mlx5_eswitch_del_send_to_vport_meta_rules(struct mlx5_eswitch *esw)
984 struct mlx5_flow_handle **flows = esw->fdb_table.offloads.send_to_vport_meta_rules;
985 int i = 0, num_vfs = esw->esw_funcs.num_vfs;
987 if (!num_vfs || !flows)
990 for (i = 0; i < num_vfs; i++)
991 mlx5_del_flow_rules(flows[i]);
997 mlx5_eswitch_add_send_to_vport_meta_rules(struct mlx5_eswitch *esw)
999 struct mlx5_flow_destination dest = {};
1000 struct mlx5_flow_act flow_act = {0};
1001 int num_vfs, rule_idx = 0, err = 0;
1002 struct mlx5_flow_handle *flow_rule;
1003 struct mlx5_flow_handle **flows;
1004 struct mlx5_flow_spec *spec;
1005 struct mlx5_vport *vport;
1009 num_vfs = esw->esw_funcs.num_vfs;
1010 flows = kvzalloc(num_vfs * sizeof(*flows), GFP_KERNEL);
1014 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1020 MLX5_SET(fte_match_param, spec->match_criteria,
1021 misc_parameters_2.metadata_reg_c_0, mlx5_eswitch_get_vport_metadata_mask());
1022 MLX5_SET(fte_match_param, spec->match_criteria,
1023 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1024 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_1,
1025 ESW_TUN_SLOW_TABLE_GOTO_VPORT_MARK);
1027 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1028 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1029 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1031 mlx5_esw_for_each_vf_vport(esw, i, vport, num_vfs) {
1032 vport_num = vport->vport;
1033 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_0,
1034 mlx5_eswitch_get_vport_metadata_for_match(esw, vport_num));
1035 dest.vport.num = vport_num;
1037 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1038 spec, &flow_act, &dest, 1);
1039 if (IS_ERR(flow_rule)) {
1040 err = PTR_ERR(flow_rule);
1041 esw_warn(esw->dev, "FDB: Failed to add send to vport meta rule idx %d, err %ld\n",
1042 rule_idx, PTR_ERR(flow_rule));
1045 flows[rule_idx++] = flow_rule;
1048 esw->fdb_table.offloads.send_to_vport_meta_rules = flows;
1053 while (--rule_idx >= 0)
1054 mlx5_del_flow_rules(flows[rule_idx]);
1061 static bool mlx5_eswitch_reg_c1_loopback_supported(struct mlx5_eswitch *esw)
1063 return MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
1064 MLX5_FDB_TO_VPORT_REG_C_1;
1067 static int esw_set_passing_vport_metadata(struct mlx5_eswitch *esw, bool enable)
1069 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
1070 u32 min[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
1071 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {};
1075 if (!mlx5_eswitch_reg_c1_loopback_supported(esw) &&
1076 !mlx5_eswitch_vport_match_metadata_enabled(esw))
1079 MLX5_SET(query_esw_vport_context_in, in, opcode,
1080 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
1081 err = mlx5_cmd_exec_inout(esw->dev, query_esw_vport_context, in, out);
1085 curr = MLX5_GET(query_esw_vport_context_out, out,
1086 esw_vport_context.fdb_to_vport_reg_c_id);
1087 wanted = MLX5_FDB_TO_VPORT_REG_C_0;
1088 if (mlx5_eswitch_reg_c1_loopback_supported(esw))
1089 wanted |= MLX5_FDB_TO_VPORT_REG_C_1;
1096 MLX5_SET(modify_esw_vport_context_in, min,
1097 esw_vport_context.fdb_to_vport_reg_c_id, curr);
1098 MLX5_SET(modify_esw_vport_context_in, min,
1099 field_select.fdb_to_vport_reg_c_id, 1);
1101 err = mlx5_eswitch_modify_esw_vport_context(esw->dev, 0, false, min);
1103 if (enable && (curr & MLX5_FDB_TO_VPORT_REG_C_1))
1104 esw->flags |= MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1106 esw->flags &= ~MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1112 static void peer_miss_rules_setup(struct mlx5_eswitch *esw,
1113 struct mlx5_core_dev *peer_dev,
1114 struct mlx5_flow_spec *spec,
1115 struct mlx5_flow_destination *dest)
1119 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1120 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1122 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1123 mlx5_eswitch_get_vport_metadata_mask());
1125 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1127 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1130 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
1131 MLX5_CAP_GEN(peer_dev, vhca_id));
1133 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1135 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1137 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1138 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
1139 source_eswitch_owner_vhca_id);
1142 dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1143 dest->vport.num = peer_dev->priv.eswitch->manager_vport;
1144 dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
1145 dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
1148 static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw,
1149 struct mlx5_eswitch *peer_esw,
1150 struct mlx5_flow_spec *spec,
1155 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1156 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1158 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1159 mlx5_eswitch_get_vport_metadata_for_match(peer_esw,
1162 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1164 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1168 static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
1169 struct mlx5_core_dev *peer_dev)
1171 struct mlx5_flow_destination dest = {};
1172 struct mlx5_flow_act flow_act = {0};
1173 struct mlx5_flow_handle **flows;
1174 /* total vports is the same for both e-switches */
1175 int nvports = esw->total_vports;
1176 struct mlx5_flow_handle *flow;
1177 struct mlx5_flow_spec *spec;
1178 struct mlx5_vport *vport;
1183 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1187 peer_miss_rules_setup(esw, peer_dev, spec, &dest);
1189 flows = kvzalloc(nvports * sizeof(*flows), GFP_KERNEL);
1192 goto alloc_flows_err;
1195 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1196 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1199 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1200 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1201 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
1202 spec, MLX5_VPORT_PF);
1204 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1205 spec, &flow_act, &dest, 1);
1207 err = PTR_ERR(flow);
1208 goto add_pf_flow_err;
1210 flows[vport->index] = flow;
1213 if (mlx5_ecpf_vport_exists(esw->dev)) {
1214 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1215 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
1216 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1217 spec, &flow_act, &dest, 1);
1219 err = PTR_ERR(flow);
1220 goto add_ecpf_flow_err;
1222 flows[vport->index] = flow;
1225 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
1226 esw_set_peer_miss_rule_source_port(esw,
1227 peer_dev->priv.eswitch,
1228 spec, vport->vport);
1230 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1231 spec, &flow_act, &dest, 1);
1233 err = PTR_ERR(flow);
1234 goto add_vf_flow_err;
1236 flows[vport->index] = flow;
1239 esw->fdb_table.offloads.peer_miss_rules = flows;
1245 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
1246 if (!flows[vport->index])
1248 mlx5_del_flow_rules(flows[vport->index]);
1250 if (mlx5_ecpf_vport_exists(esw->dev)) {
1251 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1252 mlx5_del_flow_rules(flows[vport->index]);
1255 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1256 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1257 mlx5_del_flow_rules(flows[vport->index]);
1260 esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
1267 static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw)
1269 struct mlx5_flow_handle **flows;
1270 struct mlx5_vport *vport;
1273 flows = esw->fdb_table.offloads.peer_miss_rules;
1275 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev))
1276 mlx5_del_flow_rules(flows[vport->index]);
1278 if (mlx5_ecpf_vport_exists(esw->dev)) {
1279 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1280 mlx5_del_flow_rules(flows[vport->index]);
1283 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1284 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1285 mlx5_del_flow_rules(flows[vport->index]);
1290 static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
1292 struct mlx5_flow_act flow_act = {0};
1293 struct mlx5_flow_destination dest = {};
1294 struct mlx5_flow_handle *flow_rule = NULL;
1295 struct mlx5_flow_spec *spec;
1302 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1308 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1309 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1311 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
1312 outer_headers.dmac_47_16);
1315 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1316 dest.vport.num = esw->manager_vport;
1317 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1319 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1320 spec, &flow_act, &dest, 1);
1321 if (IS_ERR(flow_rule)) {
1322 err = PTR_ERR(flow_rule);
1323 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
1327 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
1329 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1331 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
1332 outer_headers.dmac_47_16);
1334 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1335 spec, &flow_act, &dest, 1);
1336 if (IS_ERR(flow_rule)) {
1337 err = PTR_ERR(flow_rule);
1338 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
1339 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1343 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
1350 struct mlx5_flow_handle *
1351 esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag)
1353 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
1354 struct mlx5_flow_table *ft = esw->offloads.ft_offloads_restore;
1355 struct mlx5_flow_context *flow_context;
1356 struct mlx5_flow_handle *flow_rule;
1357 struct mlx5_flow_destination dest;
1358 struct mlx5_flow_spec *spec;
1361 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1362 return ERR_PTR(-EOPNOTSUPP);
1364 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1366 return ERR_PTR(-ENOMEM);
1368 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1370 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1371 ESW_REG_C0_USER_DATA_METADATA_MASK);
1372 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1374 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, tag);
1375 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1376 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1377 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1378 flow_act.modify_hdr = esw->offloads.restore_copy_hdr_id;
1380 flow_context = &spec->flow_context;
1381 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1382 flow_context->flow_tag = tag;
1383 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1384 dest.ft = esw->offloads.ft_offloads;
1386 flow_rule = mlx5_add_flow_rules(ft, spec, &flow_act, &dest, 1);
1389 if (IS_ERR(flow_rule))
1391 "Failed to create restore rule for tag: %d, err(%d)\n",
1392 tag, (int)PTR_ERR(flow_rule));
1397 #define MAX_PF_SQ 256
1398 #define MAX_SQ_NVPORTS 32
1400 static void esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
1403 void *match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1407 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1408 MLX5_SET(create_flow_group_in, flow_group_in,
1409 match_criteria_enable,
1410 MLX5_MATCH_MISC_PARAMETERS_2);
1412 MLX5_SET(fte_match_param, match_criteria,
1413 misc_parameters_2.metadata_reg_c_0,
1414 mlx5_eswitch_get_vport_metadata_mask());
1416 MLX5_SET(create_flow_group_in, flow_group_in,
1417 match_criteria_enable,
1418 MLX5_MATCH_MISC_PARAMETERS);
1420 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1421 misc_parameters.source_port);
1425 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
1426 static void esw_vport_tbl_put(struct mlx5_eswitch *esw)
1428 struct mlx5_vport_tbl_attr attr;
1429 struct mlx5_vport *vport;
1434 mlx5_esw_for_each_vport(esw, i, vport) {
1435 attr.vport = vport->vport;
1436 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
1437 mlx5_esw_vporttbl_put(esw, &attr);
1441 static int esw_vport_tbl_get(struct mlx5_eswitch *esw)
1443 struct mlx5_vport_tbl_attr attr;
1444 struct mlx5_flow_table *fdb;
1445 struct mlx5_vport *vport;
1450 mlx5_esw_for_each_vport(esw, i, vport) {
1451 attr.vport = vport->vport;
1452 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
1453 fdb = mlx5_esw_vporttbl_get(esw, &attr);
1460 esw_vport_tbl_put(esw);
1461 return PTR_ERR(fdb);
1464 #define fdb_modify_header_fwd_to_table_supported(esw) \
1465 (MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table))
1466 static void esw_init_chains_offload_flags(struct mlx5_eswitch *esw, u32 *flags)
1468 struct mlx5_core_dev *dev = esw->dev;
1470 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, ignore_flow_level))
1471 *flags |= MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
1473 if (!MLX5_CAP_ESW_FLOWTABLE(dev, multi_fdb_encap) &&
1474 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
1475 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1476 esw_warn(dev, "Tc chains and priorities offload aren't supported, update firmware if needed\n");
1477 } else if (!mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
1478 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1479 esw_warn(dev, "Tc chains and priorities offload aren't supported\n");
1480 } else if (!fdb_modify_header_fwd_to_table_supported(esw)) {
1481 /* Disabled when ttl workaround is needed, e.g
1482 * when ESWITCH_IPV4_TTL_MODIFY_ENABLE = true in mlxconfig
1485 "Tc chains and priorities offload aren't supported, check firmware version, or mlxconfig settings\n");
1486 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1488 *flags |= MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1489 esw_info(dev, "Supported tc chains and prios offload\n");
1492 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1493 *flags |= MLX5_CHAINS_FT_TUNNEL_SUPPORTED;
1497 esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1499 struct mlx5_core_dev *dev = esw->dev;
1500 struct mlx5_flow_table *nf_ft, *ft;
1501 struct mlx5_chains_attr attr = {};
1502 struct mlx5_fs_chains *chains;
1506 fdb_max = 1 << MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size);
1508 esw_init_chains_offload_flags(esw, &attr.flags);
1509 attr.ns = MLX5_FLOW_NAMESPACE_FDB;
1510 attr.max_ft_sz = fdb_max;
1511 attr.max_grp_num = esw->params.large_group_num;
1512 attr.default_ft = miss_fdb;
1513 attr.mapping = esw->offloads.reg_c0_obj_pool;
1515 chains = mlx5_chains_create(dev, &attr);
1516 if (IS_ERR(chains)) {
1517 err = PTR_ERR(chains);
1518 esw_warn(dev, "Failed to create fdb chains err(%d)\n", err);
1522 esw->fdb_table.offloads.esw_chains_priv = chains;
1524 /* Create tc_end_ft which is the always created ft chain */
1525 nf_ft = mlx5_chains_get_table(chains, mlx5_chains_get_nf_ft_chain(chains),
1527 if (IS_ERR(nf_ft)) {
1528 err = PTR_ERR(nf_ft);
1532 /* Always open the root for fast path */
1533 ft = mlx5_chains_get_table(chains, 0, 1, 0);
1539 /* Open level 1 for split fdb rules now if prios isn't supported */
1540 if (!mlx5_chains_prios_supported(chains)) {
1541 err = esw_vport_tbl_get(esw);
1546 mlx5_chains_set_end_ft(chains, nf_ft);
1551 mlx5_chains_put_table(chains, 0, 1, 0);
1553 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1555 mlx5_chains_destroy(chains);
1556 esw->fdb_table.offloads.esw_chains_priv = NULL;
1562 esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1564 if (!mlx5_chains_prios_supported(chains))
1565 esw_vport_tbl_put(esw);
1566 mlx5_chains_put_table(chains, 0, 1, 0);
1567 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1568 mlx5_chains_destroy(chains);
1571 #else /* CONFIG_MLX5_CLS_ACT */
1574 esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1578 esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1583 static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw)
1585 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1586 struct mlx5_flow_table_attr ft_attr = {};
1587 int num_vfs, table_size, ix, err = 0;
1588 struct mlx5_core_dev *dev = esw->dev;
1589 struct mlx5_flow_namespace *root_ns;
1590 struct mlx5_flow_table *fdb = NULL;
1591 u32 flags = 0, *flow_group_in;
1592 struct mlx5_flow_group *g;
1593 void *match_criteria;
1596 esw_debug(esw->dev, "Create offloads FDB Tables\n");
1598 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1602 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
1604 esw_warn(dev, "Failed to get FDB flow namespace\n");
1608 esw->fdb_table.offloads.ns = root_ns;
1609 err = mlx5_flow_namespace_set_mode(root_ns,
1610 esw->dev->priv.steering->mode);
1612 esw_warn(dev, "Failed to set FDB namespace steering mode\n");
1616 table_size = esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ +
1617 MLX5_ESW_MISS_FLOWS + esw->total_vports + esw->esw_funcs.num_vfs;
1619 /* create the slow path fdb with encap set, so further table instances
1620 * can be created at run time while VFs are probed if the FW allows that.
1622 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1623 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
1624 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
1626 ft_attr.flags = flags;
1627 ft_attr.max_fte = table_size;
1628 ft_attr.prio = FDB_SLOW_PATH;
1630 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
1633 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
1636 esw->fdb_table.offloads.slow_fdb = fdb;
1638 /* Create empty TC-miss managed table. This allows plugging in following
1639 * priorities without directly exposing their level 0 table to
1640 * eswitch_offloads and passing it as miss_fdb to following call to
1641 * esw_chains_create().
1643 memset(&ft_attr, 0, sizeof(ft_attr));
1644 ft_attr.prio = FDB_TC_MISS;
1645 esw->fdb_table.offloads.tc_miss_table = mlx5_create_flow_table(root_ns, &ft_attr);
1646 if (IS_ERR(esw->fdb_table.offloads.tc_miss_table)) {
1647 err = PTR_ERR(esw->fdb_table.offloads.tc_miss_table);
1648 esw_warn(dev, "Failed to create TC miss FDB Table err %d\n", err);
1649 goto tc_miss_table_err;
1652 err = esw_chains_create(esw, esw->fdb_table.offloads.tc_miss_table);
1654 esw_warn(dev, "Failed to open fdb chains err(%d)\n", err);
1655 goto fdb_chains_err;
1658 /* create send-to-vport group */
1659 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1660 MLX5_MATCH_MISC_PARAMETERS);
1662 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1664 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
1665 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
1666 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
1667 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1668 misc_parameters.source_eswitch_owner_vhca_id);
1669 MLX5_SET(create_flow_group_in, flow_group_in,
1670 source_eswitch_owner_vhca_id_valid, 1);
1673 ix = esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ;
1674 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1675 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ix - 1);
1677 g = mlx5_create_flow_group(fdb, flow_group_in);
1680 esw_warn(dev, "Failed to create send-to-vport flow group err(%d)\n", err);
1681 goto send_vport_err;
1683 esw->fdb_table.offloads.send_to_vport_grp = g;
1685 if (esw_src_port_rewrite_supported(esw)) {
1686 /* meta send to vport */
1687 memset(flow_group_in, 0, inlen);
1688 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1689 MLX5_MATCH_MISC_PARAMETERS_2);
1691 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1693 MLX5_SET(fte_match_param, match_criteria,
1694 misc_parameters_2.metadata_reg_c_0,
1695 mlx5_eswitch_get_vport_metadata_mask());
1696 MLX5_SET(fte_match_param, match_criteria,
1697 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1699 num_vfs = esw->esw_funcs.num_vfs;
1701 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1702 MLX5_SET(create_flow_group_in, flow_group_in,
1703 end_flow_index, ix + num_vfs - 1);
1706 g = mlx5_create_flow_group(fdb, flow_group_in);
1709 esw_warn(dev, "Failed to create send-to-vport meta flow group err(%d)\n",
1711 goto send_vport_meta_err;
1713 esw->fdb_table.offloads.send_to_vport_meta_grp = g;
1715 err = mlx5_eswitch_add_send_to_vport_meta_rules(esw);
1721 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
1722 /* create peer esw miss group */
1723 memset(flow_group_in, 0, inlen);
1725 esw_set_flow_group_source_port(esw, flow_group_in);
1727 if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1728 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1732 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1733 misc_parameters.source_eswitch_owner_vhca_id);
1735 MLX5_SET(create_flow_group_in, flow_group_in,
1736 source_eswitch_owner_vhca_id_valid, 1);
1739 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1740 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1741 ix + esw->total_vports - 1);
1742 ix += esw->total_vports;
1744 g = mlx5_create_flow_group(fdb, flow_group_in);
1747 esw_warn(dev, "Failed to create peer miss flow group err(%d)\n", err);
1750 esw->fdb_table.offloads.peer_miss_grp = g;
1753 /* create miss group */
1754 memset(flow_group_in, 0, inlen);
1755 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1756 MLX5_MATCH_OUTER_HEADERS);
1757 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1759 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
1760 outer_headers.dmac_47_16);
1763 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1764 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1765 ix + MLX5_ESW_MISS_FLOWS);
1767 g = mlx5_create_flow_group(fdb, flow_group_in);
1770 esw_warn(dev, "Failed to create miss flow group err(%d)\n", err);
1773 esw->fdb_table.offloads.miss_grp = g;
1775 err = esw_add_fdb_miss_rule(esw);
1779 kvfree(flow_group_in);
1783 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1785 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1786 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1788 mlx5_eswitch_del_send_to_vport_meta_rules(esw);
1790 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1791 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
1792 send_vport_meta_err:
1793 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1795 esw_chains_destroy(esw, esw_chains(esw));
1797 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
1799 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
1801 /* Holds true only as long as DMFS is the default */
1802 mlx5_flow_namespace_set_mode(root_ns, MLX5_FLOW_STEERING_MODE_DMFS);
1804 kvfree(flow_group_in);
1808 static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
1810 if (!esw->fdb_table.offloads.slow_fdb)
1813 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
1814 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
1815 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1816 mlx5_eswitch_del_send_to_vport_meta_rules(esw);
1817 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1818 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1819 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
1820 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1821 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1822 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1824 esw_chains_destroy(esw, esw_chains(esw));
1826 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
1827 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
1828 /* Holds true only as long as DMFS is the default */
1829 mlx5_flow_namespace_set_mode(esw->fdb_table.offloads.ns,
1830 MLX5_FLOW_STEERING_MODE_DMFS);
1831 atomic64_set(&esw->user_count, 0);
1834 static int esw_create_offloads_table(struct mlx5_eswitch *esw)
1836 struct mlx5_flow_table_attr ft_attr = {};
1837 struct mlx5_core_dev *dev = esw->dev;
1838 struct mlx5_flow_table *ft_offloads;
1839 struct mlx5_flow_namespace *ns;
1842 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1844 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
1848 ft_attr.max_fte = esw->total_vports + MLX5_ESW_MISS_FLOWS;
1851 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
1852 if (IS_ERR(ft_offloads)) {
1853 err = PTR_ERR(ft_offloads);
1854 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
1858 esw->offloads.ft_offloads = ft_offloads;
1862 static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
1864 struct mlx5_esw_offload *offloads = &esw->offloads;
1866 mlx5_destroy_flow_table(offloads->ft_offloads);
1869 static int esw_create_vport_rx_group(struct mlx5_eswitch *esw)
1871 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1872 struct mlx5_flow_group *g;
1877 nvports = esw->total_vports + MLX5_ESW_MISS_FLOWS;
1878 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1882 /* create vport rx group */
1883 esw_set_flow_group_source_port(esw, flow_group_in);
1885 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1886 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
1888 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
1892 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
1896 esw->offloads.vport_rx_group = g;
1898 kvfree(flow_group_in);
1902 static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
1904 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
1907 struct mlx5_flow_handle *
1908 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
1909 struct mlx5_flow_destination *dest)
1911 struct mlx5_flow_act flow_act = {0};
1912 struct mlx5_flow_handle *flow_rule;
1913 struct mlx5_flow_spec *spec;
1916 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1918 flow_rule = ERR_PTR(-ENOMEM);
1922 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1923 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
1924 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1925 mlx5_eswitch_get_vport_metadata_for_match(esw, vport));
1927 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
1928 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1929 mlx5_eswitch_get_vport_metadata_mask());
1931 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1933 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
1934 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1936 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
1937 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1939 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1942 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1943 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
1944 &flow_act, dest, 1);
1945 if (IS_ERR(flow_rule)) {
1946 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
1955 static int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode)
1957 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
1958 struct mlx5_core_dev *dev = esw->dev;
1959 struct mlx5_vport *vport;
1962 if (!MLX5_CAP_GEN(dev, vport_group_manager))
1965 if (esw->mode == MLX5_ESWITCH_NONE)
1968 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
1969 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1970 mlx5_mode = MLX5_INLINE_MODE_NONE;
1972 case MLX5_CAP_INLINE_MODE_L2:
1973 mlx5_mode = MLX5_INLINE_MODE_L2;
1975 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1980 mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode);
1981 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
1982 mlx5_query_nic_vport_min_inline(dev, vport->vport, &mlx5_mode);
1983 if (prev_mlx5_mode != mlx5_mode)
1985 prev_mlx5_mode = mlx5_mode;
1993 static void esw_destroy_restore_table(struct mlx5_eswitch *esw)
1995 struct mlx5_esw_offload *offloads = &esw->offloads;
1997 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2000 mlx5_modify_header_dealloc(esw->dev, offloads->restore_copy_hdr_id);
2001 mlx5_destroy_flow_group(offloads->restore_group);
2002 mlx5_destroy_flow_table(offloads->ft_offloads_restore);
2005 static int esw_create_restore_table(struct mlx5_eswitch *esw)
2007 u8 modact[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] = {};
2008 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2009 struct mlx5_flow_table_attr ft_attr = {};
2010 struct mlx5_core_dev *dev = esw->dev;
2011 struct mlx5_flow_namespace *ns;
2012 struct mlx5_modify_hdr *mod_hdr;
2013 void *match_criteria, *misc;
2014 struct mlx5_flow_table *ft;
2015 struct mlx5_flow_group *g;
2019 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2022 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
2024 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
2028 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2029 if (!flow_group_in) {
2034 ft_attr.max_fte = 1 << ESW_REG_C0_USER_DATA_METADATA_BITS;
2035 ft = mlx5_create_flow_table(ns, &ft_attr);
2038 esw_warn(esw->dev, "Failed to create restore table, err %d\n",
2043 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
2045 misc = MLX5_ADDR_OF(fte_match_param, match_criteria,
2048 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
2049 ESW_REG_C0_USER_DATA_METADATA_MASK);
2050 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2051 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
2052 ft_attr.max_fte - 1);
2053 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
2054 MLX5_MATCH_MISC_PARAMETERS_2);
2055 g = mlx5_create_flow_group(ft, flow_group_in);
2058 esw_warn(dev, "Failed to create restore flow group, err: %d\n",
2063 MLX5_SET(copy_action_in, modact, action_type, MLX5_ACTION_TYPE_COPY);
2064 MLX5_SET(copy_action_in, modact, src_field,
2065 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1);
2066 MLX5_SET(copy_action_in, modact, dst_field,
2067 MLX5_ACTION_IN_FIELD_METADATA_REG_B);
2068 mod_hdr = mlx5_modify_header_alloc(esw->dev,
2069 MLX5_FLOW_NAMESPACE_KERNEL, 1,
2071 if (IS_ERR(mod_hdr)) {
2072 err = PTR_ERR(mod_hdr);
2073 esw_warn(dev, "Failed to create restore mod header, err: %d\n",
2078 esw->offloads.ft_offloads_restore = ft;
2079 esw->offloads.restore_group = g;
2080 esw->offloads.restore_copy_hdr_id = mod_hdr;
2082 kvfree(flow_group_in);
2087 mlx5_destroy_flow_group(g);
2089 mlx5_destroy_flow_table(ft);
2091 kvfree(flow_group_in);
2096 static int esw_offloads_start(struct mlx5_eswitch *esw,
2097 struct netlink_ext_ack *extack)
2101 mlx5_eswitch_disable_locked(esw, false);
2102 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS,
2103 esw->dev->priv.sriov.num_vfs);
2105 NL_SET_ERR_MSG_MOD(extack,
2106 "Failed setting eswitch to offloads");
2107 err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY,
2108 MLX5_ESWITCH_IGNORE_NUM_VFS);
2110 NL_SET_ERR_MSG_MOD(extack,
2111 "Failed setting eswitch back to legacy");
2114 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
2115 if (mlx5_eswitch_inline_mode_get(esw,
2116 &esw->offloads.inline_mode)) {
2117 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
2118 NL_SET_ERR_MSG_MOD(extack,
2119 "Inline mode is different between vports");
2125 static void mlx5_esw_offloads_rep_mark_set(struct mlx5_eswitch *esw,
2126 struct mlx5_eswitch_rep *rep,
2131 /* Copy the mark from vport to its rep */
2132 mark_set = xa_get_mark(&esw->vports, rep->vport, mark);
2134 xa_set_mark(&esw->offloads.vport_reps, rep->vport, mark);
2137 static int mlx5_esw_offloads_rep_init(struct mlx5_eswitch *esw, const struct mlx5_vport *vport)
2139 struct mlx5_eswitch_rep *rep;
2143 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
2147 rep->vport = vport->vport;
2148 rep->vport_index = vport->index;
2149 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
2150 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
2152 err = xa_insert(&esw->offloads.vport_reps, rep->vport, rep, GFP_KERNEL);
2156 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_HOST_FN);
2157 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_VF);
2158 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_SF);
2166 static void mlx5_esw_offloads_rep_cleanup(struct mlx5_eswitch *esw,
2167 struct mlx5_eswitch_rep *rep)
2169 xa_erase(&esw->offloads.vport_reps, rep->vport);
2173 void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
2175 struct mlx5_eswitch_rep *rep;
2178 mlx5_esw_for_each_rep(esw, i, rep)
2179 mlx5_esw_offloads_rep_cleanup(esw, rep);
2180 xa_destroy(&esw->offloads.vport_reps);
2183 int esw_offloads_init_reps(struct mlx5_eswitch *esw)
2185 struct mlx5_vport *vport;
2189 xa_init(&esw->offloads.vport_reps);
2191 mlx5_esw_for_each_vport(esw, i, vport) {
2192 err = mlx5_esw_offloads_rep_init(esw, vport);
2199 esw_offloads_cleanup_reps(esw);
2203 static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw,
2204 struct mlx5_eswitch_rep *rep, u8 rep_type)
2206 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
2207 REP_LOADED, REP_REGISTERED) == REP_LOADED)
2208 esw->offloads.rep_ops[rep_type]->unload(rep);
2211 static void __unload_reps_sf_vport(struct mlx5_eswitch *esw, u8 rep_type)
2213 struct mlx5_eswitch_rep *rep;
2216 mlx5_esw_for_each_sf_rep(esw, i, rep)
2217 __esw_offloads_unload_rep(esw, rep, rep_type);
2220 static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
2222 struct mlx5_eswitch_rep *rep;
2225 __unload_reps_sf_vport(esw, rep_type);
2227 mlx5_esw_for_each_vf_rep(esw, i, rep)
2228 __esw_offloads_unload_rep(esw, rep, rep_type);
2230 if (mlx5_ecpf_vport_exists(esw->dev)) {
2231 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF);
2232 __esw_offloads_unload_rep(esw, rep, rep_type);
2235 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
2236 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
2237 __esw_offloads_unload_rep(esw, rep, rep_type);
2240 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
2241 __esw_offloads_unload_rep(esw, rep, rep_type);
2244 int mlx5_esw_offloads_rep_load(struct mlx5_eswitch *esw, u16 vport_num)
2246 struct mlx5_eswitch_rep *rep;
2250 rep = mlx5_eswitch_get_rep(esw, vport_num);
2251 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
2252 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
2253 REP_REGISTERED, REP_LOADED) == REP_REGISTERED) {
2254 err = esw->offloads.rep_ops[rep_type]->load(esw->dev, rep);
2262 atomic_set(&rep->rep_data[rep_type].state, REP_REGISTERED);
2263 for (--rep_type; rep_type >= 0; rep_type--)
2264 __esw_offloads_unload_rep(esw, rep, rep_type);
2268 void mlx5_esw_offloads_rep_unload(struct mlx5_eswitch *esw, u16 vport_num)
2270 struct mlx5_eswitch_rep *rep;
2273 rep = mlx5_eswitch_get_rep(esw, vport_num);
2274 for (rep_type = NUM_REP_TYPES - 1; rep_type >= 0; rep_type--)
2275 __esw_offloads_unload_rep(esw, rep, rep_type);
2278 int esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num)
2282 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2285 if (vport_num != MLX5_VPORT_UPLINK) {
2286 err = mlx5_esw_offloads_devlink_port_register(esw, vport_num);
2291 err = mlx5_esw_offloads_rep_load(esw, vport_num);
2297 if (vport_num != MLX5_VPORT_UPLINK)
2298 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
2302 void esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num)
2304 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2307 mlx5_esw_offloads_rep_unload(esw, vport_num);
2309 if (vport_num != MLX5_VPORT_UPLINK)
2310 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
2313 #define ESW_OFFLOADS_DEVCOM_PAIR (0)
2314 #define ESW_OFFLOADS_DEVCOM_UNPAIR (1)
2316 static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw,
2317 struct mlx5_eswitch *peer_esw)
2320 return esw_add_fdb_peer_miss_rules(esw, peer_esw->dev);
2323 static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw)
2325 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
2326 mlx5e_tc_clean_fdb_peer_flows(esw);
2328 esw_del_fdb_peer_miss_rules(esw);
2331 static int mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch *esw,
2332 struct mlx5_eswitch *peer_esw,
2335 struct mlx5_flow_root_namespace *peer_ns;
2336 struct mlx5_flow_root_namespace *ns;
2339 peer_ns = peer_esw->dev->priv.steering->fdb_root_ns;
2340 ns = esw->dev->priv.steering->fdb_root_ns;
2343 err = mlx5_flow_namespace_set_peer(ns, peer_ns);
2347 err = mlx5_flow_namespace_set_peer(peer_ns, ns);
2349 mlx5_flow_namespace_set_peer(ns, NULL);
2353 mlx5_flow_namespace_set_peer(ns, NULL);
2354 mlx5_flow_namespace_set_peer(peer_ns, NULL);
2360 static int mlx5_esw_offloads_devcom_event(int event,
2364 struct mlx5_eswitch *esw = my_data;
2365 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2366 struct mlx5_eswitch *peer_esw = event_data;
2370 case ESW_OFFLOADS_DEVCOM_PAIR:
2371 if (mlx5_get_next_phys_dev(esw->dev) != peer_esw->dev)
2374 if (mlx5_eswitch_vport_match_metadata_enabled(esw) !=
2375 mlx5_eswitch_vport_match_metadata_enabled(peer_esw))
2378 err = mlx5_esw_offloads_set_ns_peer(esw, peer_esw, true);
2381 err = mlx5_esw_offloads_pair(esw, peer_esw);
2385 err = mlx5_esw_offloads_pair(peer_esw, esw);
2389 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, true);
2392 case ESW_OFFLOADS_DEVCOM_UNPAIR:
2393 if (!mlx5_devcom_is_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS))
2396 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, false);
2397 mlx5_esw_offloads_unpair(peer_esw);
2398 mlx5_esw_offloads_unpair(esw);
2399 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
2406 mlx5_esw_offloads_unpair(esw);
2408 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
2410 mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d",
2415 static void esw_offloads_devcom_init(struct mlx5_eswitch *esw)
2417 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2419 INIT_LIST_HEAD(&esw->offloads.peer_flows);
2420 mutex_init(&esw->offloads.peer_mutex);
2422 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
2425 mlx5_devcom_register_component(devcom,
2426 MLX5_DEVCOM_ESW_OFFLOADS,
2427 mlx5_esw_offloads_devcom_event,
2430 mlx5_devcom_send_event(devcom,
2431 MLX5_DEVCOM_ESW_OFFLOADS,
2432 ESW_OFFLOADS_DEVCOM_PAIR, esw);
2435 static void esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw)
2437 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2439 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
2442 mlx5_devcom_send_event(devcom, MLX5_DEVCOM_ESW_OFFLOADS,
2443 ESW_OFFLOADS_DEVCOM_UNPAIR, esw);
2445 mlx5_devcom_unregister_component(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2448 bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw)
2450 if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl))
2453 if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
2454 MLX5_FDB_TO_VPORT_REG_C_0))
2457 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source))
2460 if (mlx5_core_is_ecpf_esw_manager(esw->dev) ||
2461 mlx5_ecpf_vport_exists(esw->dev))
2467 u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw)
2469 u32 vport_end_ida = (1 << ESW_VPORT_BITS) - 1;
2470 u32 max_pf_num = (1 << ESW_PFNUM_BITS) - 1;
2474 /* Only 4 bits of pf_num */
2475 pf_num = PCI_FUNC(esw->dev->pdev->devfn);
2476 if (pf_num > max_pf_num)
2479 /* Metadata is 4 bits of PFNUM and 12 bits of unique id */
2480 /* Use only non-zero vport_id (1-4095) for all PF's */
2481 id = ida_alloc_range(&esw->offloads.vport_metadata_ida, 1, vport_end_ida, GFP_KERNEL);
2484 id = (pf_num << ESW_VPORT_BITS) | id;
2488 void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata)
2490 u32 vport_bit_mask = (1 << ESW_VPORT_BITS) - 1;
2492 /* Metadata contains only 12 bits of actual ida id */
2493 ida_free(&esw->offloads.vport_metadata_ida, metadata & vport_bit_mask);
2496 static int esw_offloads_vport_metadata_setup(struct mlx5_eswitch *esw,
2497 struct mlx5_vport *vport)
2499 vport->default_metadata = mlx5_esw_match_metadata_alloc(esw);
2500 vport->metadata = vport->default_metadata;
2501 return vport->metadata ? 0 : -ENOSPC;
2504 static void esw_offloads_vport_metadata_cleanup(struct mlx5_eswitch *esw,
2505 struct mlx5_vport *vport)
2507 if (!vport->default_metadata)
2510 WARN_ON(vport->metadata != vport->default_metadata);
2511 mlx5_esw_match_metadata_free(esw, vport->default_metadata);
2514 static void esw_offloads_metadata_uninit(struct mlx5_eswitch *esw)
2516 struct mlx5_vport *vport;
2519 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
2522 mlx5_esw_for_each_vport(esw, i, vport)
2523 esw_offloads_vport_metadata_cleanup(esw, vport);
2526 static int esw_offloads_metadata_init(struct mlx5_eswitch *esw)
2528 struct mlx5_vport *vport;
2532 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
2535 mlx5_esw_for_each_vport(esw, i, vport) {
2536 err = esw_offloads_vport_metadata_setup(esw, vport);
2544 esw_offloads_metadata_uninit(esw);
2548 int mlx5_esw_offloads_vport_metadata_set(struct mlx5_eswitch *esw, bool enable)
2552 down_write(&esw->mode_lock);
2553 if (esw->mode != MLX5_ESWITCH_NONE) {
2557 if (!mlx5_esw_vport_match_metadata_supported(esw)) {
2562 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
2564 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
2566 up_write(&esw->mode_lock);
2571 esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
2572 struct mlx5_vport *vport)
2576 err = esw_acl_ingress_ofld_setup(esw, vport);
2580 err = esw_acl_egress_ofld_setup(esw, vport);
2587 esw_acl_ingress_ofld_cleanup(esw, vport);
2592 esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
2593 struct mlx5_vport *vport)
2595 esw_acl_egress_ofld_cleanup(vport);
2596 esw_acl_ingress_ofld_cleanup(esw, vport);
2599 static int esw_create_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
2601 struct mlx5_vport *vport;
2603 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
2605 return PTR_ERR(vport);
2607 return esw_vport_create_offloads_acl_tables(esw, vport);
2610 static void esw_destroy_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
2612 struct mlx5_vport *vport;
2614 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
2618 esw_vport_destroy_offloads_acl_tables(esw, vport);
2621 static int esw_offloads_steering_init(struct mlx5_eswitch *esw)
2623 struct mlx5_esw_indir_table *indir;
2626 memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb));
2627 mutex_init(&esw->fdb_table.offloads.vports.lock);
2628 hash_init(esw->fdb_table.offloads.vports.table);
2629 atomic64_set(&esw->user_count, 0);
2631 indir = mlx5_esw_indir_table_init();
2632 if (IS_ERR(indir)) {
2633 err = PTR_ERR(indir);
2634 goto create_indir_err;
2636 esw->fdb_table.offloads.indir = indir;
2638 err = esw_create_uplink_offloads_acl_tables(esw);
2640 goto create_acl_err;
2642 err = esw_create_offloads_table(esw);
2644 goto create_offloads_err;
2646 err = esw_create_restore_table(esw);
2648 goto create_restore_err;
2650 err = esw_create_offloads_fdb_tables(esw);
2652 goto create_fdb_err;
2654 err = esw_create_vport_rx_group(esw);
2661 esw_destroy_offloads_fdb_tables(esw);
2663 esw_destroy_restore_table(esw);
2665 esw_destroy_offloads_table(esw);
2666 create_offloads_err:
2667 esw_destroy_uplink_offloads_acl_tables(esw);
2669 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
2671 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
2675 static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw)
2677 esw_destroy_vport_rx_group(esw);
2678 esw_destroy_offloads_fdb_tables(esw);
2679 esw_destroy_restore_table(esw);
2680 esw_destroy_offloads_table(esw);
2681 esw_destroy_uplink_offloads_acl_tables(esw);
2682 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
2683 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
2687 esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out)
2689 bool host_pf_disabled;
2692 new_num_vfs = MLX5_GET(query_esw_functions_out, out,
2693 host_params_context.host_num_of_vfs);
2694 host_pf_disabled = MLX5_GET(query_esw_functions_out, out,
2695 host_params_context.host_pf_disabled);
2697 if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled)
2700 /* Number of VFs can only change from "0 to x" or "x to 0". */
2701 if (esw->esw_funcs.num_vfs > 0) {
2702 mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs);
2706 err = mlx5_eswitch_load_vf_vports(esw, new_num_vfs,
2707 MLX5_VPORT_UC_ADDR_CHANGE);
2711 esw->esw_funcs.num_vfs = new_num_vfs;
2714 static void esw_functions_changed_event_handler(struct work_struct *work)
2716 struct mlx5_host_work *host_work;
2717 struct mlx5_eswitch *esw;
2720 host_work = container_of(work, struct mlx5_host_work, work);
2721 esw = host_work->esw;
2723 out = mlx5_esw_query_functions(esw->dev);
2727 esw_vfs_changed_event_handler(esw, out);
2733 int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data)
2735 struct mlx5_esw_functions *esw_funcs;
2736 struct mlx5_host_work *host_work;
2737 struct mlx5_eswitch *esw;
2739 host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC);
2743 esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb);
2744 esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs);
2746 host_work->esw = esw;
2748 INIT_WORK(&host_work->work, esw_functions_changed_event_handler);
2749 queue_work(esw->work_queue, &host_work->work);
2754 static int mlx5_esw_host_number_init(struct mlx5_eswitch *esw)
2756 const u32 *query_host_out;
2758 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
2761 query_host_out = mlx5_esw_query_functions(esw->dev);
2762 if (IS_ERR(query_host_out))
2763 return PTR_ERR(query_host_out);
2765 /* Mark non local controller with non zero controller number. */
2766 esw->offloads.host_number = MLX5_GET(query_esw_functions_out, query_host_out,
2767 host_params_context.host_number);
2768 kvfree(query_host_out);
2772 bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 controller)
2774 /* Local controller is always valid */
2775 if (controller == 0)
2778 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
2781 /* External host number starts with zero in device */
2782 return (controller == esw->offloads.host_number + 1);
2785 int esw_offloads_enable(struct mlx5_eswitch *esw)
2787 struct mapping_ctx *reg_c0_obj_pool;
2788 struct mlx5_vport *vport;
2792 if (MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, reformat) &&
2793 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, decap))
2794 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_BASIC;
2796 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
2798 mutex_init(&esw->offloads.termtbl_mutex);
2799 mlx5_rdma_enable_roce(esw->dev);
2801 err = mlx5_esw_host_number_init(esw);
2805 err = esw_offloads_metadata_init(esw);
2809 err = esw_set_passing_vport_metadata(esw, true);
2811 goto err_vport_metadata;
2813 reg_c0_obj_pool = mapping_create(sizeof(struct mlx5_mapped_obj),
2814 ESW_REG_C0_USER_DATA_METADATA_MASK,
2816 if (IS_ERR(reg_c0_obj_pool)) {
2817 err = PTR_ERR(reg_c0_obj_pool);
2820 esw->offloads.reg_c0_obj_pool = reg_c0_obj_pool;
2822 err = esw_offloads_steering_init(esw);
2824 goto err_steering_init;
2826 /* Representor will control the vport link state */
2827 mlx5_esw_for_each_vf_vport(esw, i, vport, esw->esw_funcs.num_vfs)
2828 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2830 /* Uplink vport rep must load first. */
2831 err = esw_offloads_load_rep(esw, MLX5_VPORT_UPLINK);
2835 err = mlx5_eswitch_enable_pf_vf_vports(esw, MLX5_VPORT_UC_ADDR_CHANGE);
2839 esw_offloads_devcom_init(esw);
2844 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
2846 esw_offloads_steering_cleanup(esw);
2848 mapping_destroy(reg_c0_obj_pool);
2850 esw_set_passing_vport_metadata(esw, false);
2852 esw_offloads_metadata_uninit(esw);
2854 mlx5_rdma_disable_roce(esw->dev);
2855 mutex_destroy(&esw->offloads.termtbl_mutex);
2859 static int esw_offloads_stop(struct mlx5_eswitch *esw,
2860 struct netlink_ext_ack *extack)
2864 mlx5_eswitch_disable_locked(esw, false);
2865 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY,
2866 MLX5_ESWITCH_IGNORE_NUM_VFS);
2868 NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
2869 err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS,
2870 MLX5_ESWITCH_IGNORE_NUM_VFS);
2872 NL_SET_ERR_MSG_MOD(extack,
2873 "Failed setting eswitch back to offloads");
2880 void esw_offloads_disable(struct mlx5_eswitch *esw)
2882 esw_offloads_devcom_cleanup(esw);
2883 mlx5_eswitch_disable_pf_vf_vports(esw);
2884 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
2885 esw_set_passing_vport_metadata(esw, false);
2886 esw_offloads_steering_cleanup(esw);
2887 mapping_destroy(esw->offloads.reg_c0_obj_pool);
2888 esw_offloads_metadata_uninit(esw);
2889 mlx5_rdma_disable_roce(esw->dev);
2890 mutex_destroy(&esw->offloads.termtbl_mutex);
2891 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
2894 static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
2897 case DEVLINK_ESWITCH_MODE_LEGACY:
2898 *mlx5_mode = MLX5_ESWITCH_LEGACY;
2900 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
2901 *mlx5_mode = MLX5_ESWITCH_OFFLOADS;
2910 static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
2912 switch (mlx5_mode) {
2913 case MLX5_ESWITCH_LEGACY:
2914 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
2916 case MLX5_ESWITCH_OFFLOADS:
2917 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
2926 static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
2929 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
2930 *mlx5_mode = MLX5_INLINE_MODE_NONE;
2932 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
2933 *mlx5_mode = MLX5_INLINE_MODE_L2;
2935 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
2936 *mlx5_mode = MLX5_INLINE_MODE_IP;
2938 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
2939 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
2948 static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
2950 switch (mlx5_mode) {
2951 case MLX5_INLINE_MODE_NONE:
2952 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
2954 case MLX5_INLINE_MODE_L2:
2955 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
2957 case MLX5_INLINE_MODE_IP:
2958 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
2960 case MLX5_INLINE_MODE_TCP_UDP:
2961 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
2970 static int eswitch_devlink_esw_mode_check(const struct mlx5_eswitch *esw)
2972 /* devlink commands in NONE eswitch mode are currently supported only
2975 return (esw->mode == MLX5_ESWITCH_NONE &&
2976 !mlx5_core_is_ecpf_esw_manager(esw->dev)) ? -EOPNOTSUPP : 0;
2979 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
2980 struct netlink_ext_ack *extack)
2982 u16 cur_mlx5_mode, mlx5_mode = 0;
2983 struct mlx5_eswitch *esw;
2986 esw = mlx5_devlink_eswitch_get(devlink);
2988 return PTR_ERR(esw);
2990 if (esw_mode_from_devlink(mode, &mlx5_mode))
2993 err = mlx5_esw_try_lock(esw);
2995 NL_SET_ERR_MSG_MOD(extack, "Can't change mode, E-Switch is busy");
2998 cur_mlx5_mode = err;
3001 if (cur_mlx5_mode == mlx5_mode)
3004 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV)
3005 err = esw_offloads_start(esw, extack);
3006 else if (mode == DEVLINK_ESWITCH_MODE_LEGACY)
3007 err = esw_offloads_stop(esw, extack);
3012 mlx5_esw_unlock(esw);
3016 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
3018 struct mlx5_eswitch *esw;
3021 esw = mlx5_devlink_eswitch_get(devlink);
3023 return PTR_ERR(esw);
3025 down_write(&esw->mode_lock);
3026 err = eswitch_devlink_esw_mode_check(esw);
3030 err = esw_mode_to_devlink(esw->mode, mode);
3032 up_write(&esw->mode_lock);
3036 static int mlx5_esw_vports_inline_set(struct mlx5_eswitch *esw, u8 mlx5_mode,
3037 struct netlink_ext_ack *extack)
3039 struct mlx5_core_dev *dev = esw->dev;
3040 struct mlx5_vport *vport;
3041 u16 err_vport_num = 0;
3045 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3046 err = mlx5_modify_nic_vport_min_inline(dev, vport->vport, mlx5_mode);
3048 err_vport_num = vport->vport;
3049 NL_SET_ERR_MSG_MOD(extack,
3050 "Failed to set min inline on vport");
3051 goto revert_inline_mode;
3057 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3058 if (vport->vport == err_vport_num)
3060 mlx5_modify_nic_vport_min_inline(dev,
3062 esw->offloads.inline_mode);
3067 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
3068 struct netlink_ext_ack *extack)
3070 struct mlx5_core_dev *dev = devlink_priv(devlink);
3071 struct mlx5_eswitch *esw;
3075 esw = mlx5_devlink_eswitch_get(devlink);
3077 return PTR_ERR(esw);
3079 down_write(&esw->mode_lock);
3080 err = eswitch_devlink_esw_mode_check(esw);
3084 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
3085 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
3086 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE)
3089 case MLX5_CAP_INLINE_MODE_L2:
3090 NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set");
3093 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
3097 if (atomic64_read(&esw->offloads.num_flows) > 0) {
3098 NL_SET_ERR_MSG_MOD(extack,
3099 "Can't set inline mode when flows are configured");
3104 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
3108 err = mlx5_esw_vports_inline_set(esw, mlx5_mode, extack);
3112 esw->offloads.inline_mode = mlx5_mode;
3113 up_write(&esw->mode_lock);
3117 up_write(&esw->mode_lock);
3121 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
3123 struct mlx5_eswitch *esw;
3126 esw = mlx5_devlink_eswitch_get(devlink);
3128 return PTR_ERR(esw);
3130 down_write(&esw->mode_lock);
3131 err = eswitch_devlink_esw_mode_check(esw);
3135 err = esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
3137 up_write(&esw->mode_lock);
3141 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
3142 enum devlink_eswitch_encap_mode encap,
3143 struct netlink_ext_ack *extack)
3145 struct mlx5_core_dev *dev = devlink_priv(devlink);
3146 struct mlx5_eswitch *esw;
3149 esw = mlx5_devlink_eswitch_get(devlink);
3151 return PTR_ERR(esw);
3153 down_write(&esw->mode_lock);
3154 err = eswitch_devlink_esw_mode_check(esw);
3158 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
3159 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) ||
3160 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap))) {
3165 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC) {
3170 if (esw->mode == MLX5_ESWITCH_LEGACY) {
3171 esw->offloads.encap = encap;
3175 if (esw->offloads.encap == encap)
3178 if (atomic64_read(&esw->offloads.num_flows) > 0) {
3179 NL_SET_ERR_MSG_MOD(extack,
3180 "Can't set encapsulation when flows are configured");
3185 esw_destroy_offloads_fdb_tables(esw);
3187 esw->offloads.encap = encap;
3189 err = esw_create_offloads_fdb_tables(esw);
3192 NL_SET_ERR_MSG_MOD(extack,
3193 "Failed re-creating fast FDB table");
3194 esw->offloads.encap = !encap;
3195 (void)esw_create_offloads_fdb_tables(esw);
3199 up_write(&esw->mode_lock);
3203 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
3204 enum devlink_eswitch_encap_mode *encap)
3206 struct mlx5_eswitch *esw;
3209 esw = mlx5_devlink_eswitch_get(devlink);
3211 return PTR_ERR(esw);
3214 down_write(&esw->mode_lock);
3215 err = eswitch_devlink_esw_mode_check(esw);
3219 *encap = esw->offloads.encap;
3221 up_write(&esw->mode_lock);
3226 mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch *esw, u16 vport_num)
3228 /* Currently, only ECPF based device has representor for host PF. */
3229 if (vport_num == MLX5_VPORT_PF &&
3230 !mlx5_core_is_ecpf_esw_manager(esw->dev))
3233 if (vport_num == MLX5_VPORT_ECPF &&
3234 !mlx5_ecpf_vport_exists(esw->dev))
3240 void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
3241 const struct mlx5_eswitch_rep_ops *ops,
3244 struct mlx5_eswitch_rep_data *rep_data;
3245 struct mlx5_eswitch_rep *rep;
3248 esw->offloads.rep_ops[rep_type] = ops;
3249 mlx5_esw_for_each_rep(esw, i, rep) {
3250 if (likely(mlx5_eswitch_vport_has_rep(esw, rep->vport))) {
3252 rep_data = &rep->rep_data[rep_type];
3253 atomic_set(&rep_data->state, REP_REGISTERED);
3257 EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps);
3259 void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type)
3261 struct mlx5_eswitch_rep *rep;
3264 if (esw->mode == MLX5_ESWITCH_OFFLOADS)
3265 __unload_reps_all_vport(esw, rep_type);
3267 mlx5_esw_for_each_rep(esw, i, rep)
3268 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
3270 EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps);
3272 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
3274 struct mlx5_eswitch_rep *rep;
3276 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
3277 return rep->rep_data[rep_type].priv;
3280 void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
3284 struct mlx5_eswitch_rep *rep;
3286 rep = mlx5_eswitch_get_rep(esw, vport);
3288 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
3289 esw->offloads.rep_ops[rep_type]->get_proto_dev)
3290 return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep);
3293 EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
3295 void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
3297 return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type);
3299 EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
3301 struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
3304 return mlx5_eswitch_get_rep(esw, vport);
3306 EXPORT_SYMBOL(mlx5_eswitch_vport_rep);
3308 bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw)
3310 return !!(esw->flags & MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED);
3312 EXPORT_SYMBOL(mlx5_eswitch_reg_c1_loopback_enabled);
3314 bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
3316 return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA);
3318 EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled);
3320 u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw,
3323 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
3325 if (WARN_ON_ONCE(IS_ERR(vport)))
3328 return vport->metadata << (32 - ESW_SOURCE_PORT_METADATA_BITS);
3330 EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match);
3332 int mlx5_esw_offloads_sf_vport_enable(struct mlx5_eswitch *esw, struct devlink_port *dl_port,
3333 u16 vport_num, u32 controller, u32 sfnum)
3337 err = mlx5_esw_vport_enable(esw, vport_num, MLX5_VPORT_UC_ADDR_CHANGE);
3341 err = mlx5_esw_devlink_sf_port_register(esw, dl_port, vport_num, controller, sfnum);
3345 err = mlx5_esw_offloads_rep_load(esw, vport_num);
3351 mlx5_esw_devlink_sf_port_unregister(esw, vport_num);
3353 mlx5_esw_vport_disable(esw, vport_num);
3357 void mlx5_esw_offloads_sf_vport_disable(struct mlx5_eswitch *esw, u16 vport_num)
3359 mlx5_esw_offloads_rep_unload(esw, vport_num);
3360 mlx5_esw_devlink_sf_port_unregister(esw, vport_num);
3361 mlx5_esw_vport_disable(esw, vport_num);
3364 static int mlx5_esw_query_vport_vhca_id(struct mlx5_eswitch *esw, u16 vport_num, u16 *vhca_id)
3366 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
3372 if (mlx5_esw_is_manager_vport(esw, vport_num) ||
3373 !MLX5_CAP_GEN(esw->dev, vhca_resource_manager))
3376 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
3380 err = mlx5_vport_get_other_func_cap(esw->dev, vport_num, query_ctx);
3384 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
3385 *vhca_id = MLX5_GET(cmd_hca_cap, hca_caps, vhca_id);
3392 int mlx5_esw_vport_vhca_id_set(struct mlx5_eswitch *esw, u16 vport_num)
3394 u16 *old_entry, *vhca_map_entry, vhca_id;
3397 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
3399 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%u,err=%d)\n",
3404 vhca_map_entry = kmalloc(sizeof(*vhca_map_entry), GFP_KERNEL);
3405 if (!vhca_map_entry)
3408 *vhca_map_entry = vport_num;
3409 old_entry = xa_store(&esw->offloads.vhca_map, vhca_id, vhca_map_entry, GFP_KERNEL);
3410 if (xa_is_err(old_entry)) {
3411 kfree(vhca_map_entry);
3412 return xa_err(old_entry);
3418 void mlx5_esw_vport_vhca_id_clear(struct mlx5_eswitch *esw, u16 vport_num)
3420 u16 *vhca_map_entry, vhca_id;
3423 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
3425 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%hu,err=%d)\n",
3428 vhca_map_entry = xa_erase(&esw->offloads.vhca_map, vhca_id);
3429 kfree(vhca_map_entry);
3432 int mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch *esw, u16 vhca_id, u16 *vport_num)
3434 u16 *res = xa_load(&esw->offloads.vhca_map, vhca_id);
3443 u32 mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch *esw,
3446 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
3448 if (WARN_ON_ONCE(IS_ERR(vport)))
3451 return vport->metadata;
3453 EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_set);