2 * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved.
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6 * General Public License (GPL) Version 2, available from the file
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8 * OpenIB.org BSD license below:
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11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef __MLX5_ESWITCH_H__
34 #define __MLX5_ESWITCH_H__
36 #include <linux/if_ether.h>
37 #include <linux/if_link.h>
38 #include <net/devlink.h>
39 #include <linux/mlx5/device.h>
40 #include <linux/mlx5/eswitch.h>
41 #include <linux/mlx5/vport.h>
42 #include <linux/mlx5/fs.h>
45 #ifdef CONFIG_MLX5_ESWITCH
47 #define MLX5_MAX_UC_PER_VPORT(dev) \
48 (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list))
50 #define MLX5_MAX_MC_PER_VPORT(dev) \
51 (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list))
53 #define MLX5_MIN_BW_SHARE 1
55 #define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \
56 min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit)
58 #define mlx5_esw_has_fwd_fdb(dev) \
59 MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table)
61 #define FDB_MAX_CHAIN 3
62 #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1)
63 #define FDB_MAX_PRIO 16
65 struct vport_ingress {
66 struct mlx5_flow_table *acl;
67 struct mlx5_flow_group *allow_untagged_spoofchk_grp;
68 struct mlx5_flow_group *allow_spoofchk_only_grp;
69 struct mlx5_flow_group *allow_untagged_only_grp;
70 struct mlx5_flow_group *drop_grp;
71 struct mlx5_flow_handle *allow_rule;
72 struct mlx5_flow_handle *drop_rule;
73 struct mlx5_fc *drop_counter;
77 struct mlx5_flow_table *acl;
78 struct mlx5_flow_group *allowed_vlans_grp;
79 struct mlx5_flow_group *drop_grp;
80 struct mlx5_flow_handle *allowed_vlan;
81 struct mlx5_flow_handle *drop_rule;
82 struct mlx5_fc *drop_counter;
85 struct mlx5_vport_drop_stats {
90 struct mlx5_vport_info {
103 struct mlx5_core_dev *dev;
105 struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE];
106 struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE];
107 struct mlx5_flow_handle *promisc_rule;
108 struct mlx5_flow_handle *allmulti_rule;
109 struct work_struct vport_change_handler;
111 struct vport_ingress ingress;
112 struct vport_egress egress;
114 struct mlx5_vport_info info;
126 enum offloads_fdb_flags {
127 ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED = BIT(0),
130 extern const unsigned int ESW_POOLS[4];
132 #define PRIO_LEVELS 2
133 struct mlx5_eswitch_fdb {
136 struct mlx5_flow_table *fdb;
137 struct mlx5_flow_group *addr_grp;
138 struct mlx5_flow_group *allmulti_grp;
139 struct mlx5_flow_group *promisc_grp;
140 struct mlx5_flow_table *vepa_fdb;
141 struct mlx5_flow_handle *vepa_uplink_rule;
142 struct mlx5_flow_handle *vepa_star_rule;
145 struct offloads_fdb {
146 struct mlx5_flow_table *slow_fdb;
147 struct mlx5_flow_group *send_to_vport_grp;
148 struct mlx5_flow_group *peer_miss_grp;
149 struct mlx5_flow_handle **peer_miss_rules;
150 struct mlx5_flow_group *miss_grp;
151 struct mlx5_flow_handle *miss_rule_uni;
152 struct mlx5_flow_handle *miss_rule_multi;
153 int vlan_push_pop_refcount;
156 struct mlx5_flow_table *fdb;
158 } fdb_prio[FDB_MAX_CHAIN + 1][FDB_MAX_PRIO + 1][PRIO_LEVELS];
159 /* Protects fdb_prio table */
160 struct mutex fdb_prio_lock;
162 int fdb_left[ARRAY_SIZE(ESW_POOLS)];
168 struct mlx5_esw_offload {
169 struct mlx5_flow_table *ft_offloads;
170 struct mlx5_flow_group *vport_rx_group;
171 struct mlx5_eswitch_rep *vport_reps;
172 struct list_head peer_flows;
173 struct mutex peer_mutex;
174 DECLARE_HASHTABLE(encap_tbl, 8);
175 DECLARE_HASHTABLE(mod_hdr_tbl, 8);
181 /* E-Switch MC FDB table hash node */
182 struct esw_mc_addr { /* SRIOV only */
183 struct l2addr_node node;
184 struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */
188 struct mlx5_host_work {
189 struct work_struct work;
190 struct mlx5_eswitch *esw;
193 struct mlx5_host_info {
198 struct mlx5_eswitch {
199 struct mlx5_core_dev *dev;
201 struct mlx5_eswitch_fdb fdb_table;
202 struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE];
203 struct workqueue_struct *work_queue;
204 struct mlx5_vport *vports;
207 /* Synchronize between vport change events
208 * and async SRIOV admin state changes
210 struct mutex state_lock;
211 struct esw_mc_addr mc_promisc;
218 struct mlx5_esw_offload offloads;
222 struct mlx5_host_info host_info;
225 void esw_offloads_cleanup(struct mlx5_eswitch *esw);
226 int esw_offloads_init(struct mlx5_eswitch *esw, int vf_nvports,
228 void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw);
229 int esw_offloads_init_reps(struct mlx5_eswitch *esw);
230 void esw_vport_cleanup_ingress_rules(struct mlx5_eswitch *esw,
231 struct mlx5_vport *vport);
232 int esw_vport_enable_ingress_acl(struct mlx5_eswitch *esw,
233 struct mlx5_vport *vport);
234 void esw_vport_cleanup_egress_rules(struct mlx5_eswitch *esw,
235 struct mlx5_vport *vport);
236 int esw_vport_enable_egress_acl(struct mlx5_eswitch *esw,
237 struct mlx5_vport *vport);
238 void esw_vport_disable_egress_acl(struct mlx5_eswitch *esw,
239 struct mlx5_vport *vport);
240 void esw_vport_disable_ingress_acl(struct mlx5_eswitch *esw,
241 struct mlx5_vport *vport);
244 int mlx5_eswitch_init(struct mlx5_core_dev *dev);
245 void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw);
246 int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode);
247 void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw);
248 int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
249 u16 vport, u8 mac[ETH_ALEN]);
250 int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
251 u16 vport, int link_state);
252 int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
253 u16 vport, u16 vlan, u8 qos);
254 int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
255 u16 vport, bool spoofchk);
256 int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
257 u16 vport_num, bool setting);
258 int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, u16 vport,
259 u32 max_rate, u32 min_rate);
260 int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting);
261 int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting);
262 int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
263 u16 vport, struct ifla_vf_info *ivi);
264 int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
266 struct ifla_vf_stats *vf_stats);
267 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule);
269 struct mlx5_flow_spec;
270 struct mlx5_esw_flow_attr;
272 struct mlx5_flow_handle *
273 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
274 struct mlx5_flow_spec *spec,
275 struct mlx5_esw_flow_attr *attr);
276 struct mlx5_flow_handle *
277 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
278 struct mlx5_flow_spec *spec,
279 struct mlx5_esw_flow_attr *attr);
281 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
282 struct mlx5_flow_handle *rule,
283 struct mlx5_esw_flow_attr *attr);
285 mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
286 struct mlx5_flow_handle *rule,
287 struct mlx5_esw_flow_attr *attr);
290 mlx5_eswitch_prios_supported(struct mlx5_eswitch *esw);
293 mlx5_eswitch_get_prio_range(struct mlx5_eswitch *esw);
296 mlx5_eswitch_get_chain_range(struct mlx5_eswitch *esw);
298 struct mlx5_flow_handle *
299 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
300 struct mlx5_flow_destination *dest);
303 SET_VLAN_STRIP = BIT(0),
304 SET_VLAN_INSERT = BIT(1)
307 enum mlx5_flow_match_level {
308 MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE,
309 MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2,
310 MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP,
311 MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP,
314 /* current maximum for flow based vport multicasting */
315 #define MLX5_MAX_FLOW_FWD_VPORTS 2
318 MLX5_ESW_DEST_ENCAP = BIT(0),
319 MLX5_ESW_DEST_ENCAP_VALID = BIT(1),
322 struct mlx5_esw_flow_attr {
323 struct mlx5_eswitch_rep *in_rep;
324 struct mlx5_core_dev *in_mdev;
325 struct mlx5_core_dev *counter_dev;
331 __be16 vlan_proto[MLX5_FS_VLAN_DEPTH];
332 u16 vlan_vid[MLX5_FS_VLAN_DEPTH];
333 u8 vlan_prio[MLX5_FS_VLAN_DEPTH];
338 struct mlx5_eswitch_rep *rep;
339 struct mlx5_core_dev *mdev;
341 } dests[MLX5_MAX_FLOW_FWD_VPORTS];
344 u8 tunnel_match_level;
345 struct mlx5_fc *counter;
349 struct mlx5e_tc_flow_parse_attr *parse_attr;
352 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
353 struct netlink_ext_ack *extack);
354 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode);
355 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
356 struct netlink_ext_ack *extack);
357 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode);
358 int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, int nvfs, u8 *mode);
359 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, u8 encap,
360 struct netlink_ext_ack *extack);
361 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, u8 *encap);
362 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type);
364 int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
365 struct mlx5_esw_flow_attr *attr);
366 int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
367 struct mlx5_esw_flow_attr *attr);
368 int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
369 u16 vport, u16 vlan, u8 qos, u8 set_flags);
371 static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev,
374 bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) &&
375 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan);
380 return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) &&
381 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2);
384 bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0,
385 struct mlx5_core_dev *dev1);
386 bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0,
387 struct mlx5_core_dev *dev1);
389 #define MLX5_DEBUG_ESWITCH_MASK BIT(3)
391 #define esw_info(__dev, format, ...) \
392 dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)
394 #define esw_warn(__dev, format, ...) \
395 dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)
397 #define esw_debug(dev, format, ...) \
398 mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)
400 /* The returned number is valid only when the dev is eswitch manager. */
401 static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev)
403 return mlx5_core_is_ecpf_esw_manager(dev) ?
404 MLX5_VPORT_ECPF : MLX5_VPORT_PF;
407 static inline int mlx5_eswitch_uplink_idx(struct mlx5_eswitch *esw)
409 /* Uplink always locate at the last element of the array.*/
410 return esw->total_vports - 1;
413 static inline int mlx5_eswitch_ecpf_idx(struct mlx5_eswitch *esw)
415 return esw->total_vports - 2;
418 static inline int mlx5_eswitch_vport_num_to_index(struct mlx5_eswitch *esw,
421 if (vport_num == MLX5_VPORT_ECPF) {
422 if (!mlx5_ecpf_vport_exists(esw->dev))
423 esw_warn(esw->dev, "ECPF vport doesn't exist!\n");
424 return mlx5_eswitch_ecpf_idx(esw);
427 if (vport_num == MLX5_VPORT_UPLINK)
428 return mlx5_eswitch_uplink_idx(esw);
433 static inline u16 mlx5_eswitch_index_to_vport_num(struct mlx5_eswitch *esw,
436 if (index == mlx5_eswitch_ecpf_idx(esw) &&
437 mlx5_ecpf_vport_exists(esw->dev))
438 return MLX5_VPORT_ECPF;
440 if (index == mlx5_eswitch_uplink_idx(esw))
441 return MLX5_VPORT_UPLINK;
446 /* TODO: This mlx5e_tc function shouldn't be called by eswitch */
447 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw);
449 /* The vport getter/iterator are only valid after esw->total_vports
450 * and vport->vport are initialized in mlx5_eswitch_init.
452 #define mlx5_esw_for_all_vports(esw, i, vport) \
453 for ((i) = MLX5_VPORT_PF; \
454 (vport) = &(esw)->vports[i], \
455 (i) < (esw)->total_vports; (i)++)
457 #define mlx5_esw_for_each_vf_vport(esw, i, vport, nvfs) \
458 for ((i) = MLX5_VPORT_FIRST_VF; \
459 (vport) = &(esw)->vports[(i)], \
460 (i) <= (nvfs); (i)++)
462 #define mlx5_esw_for_each_vf_vport_reverse(esw, i, vport, nvfs) \
464 (vport) = &(esw)->vports[(i)], \
465 (i) >= MLX5_VPORT_FIRST_VF; (i)--)
467 /* The rep getter/iterator are only valid after esw->total_vports
468 * and vport->vport are initialized in mlx5_eswitch_init.
470 #define mlx5_esw_for_all_reps(esw, i, rep) \
471 for ((i) = MLX5_VPORT_PF; \
472 (rep) = &(esw)->offloads.vport_reps[i], \
473 (i) < (esw)->total_vports; (i)++)
475 #define mlx5_esw_for_each_vf_rep(esw, i, rep, nvfs) \
476 for ((i) = MLX5_VPORT_FIRST_VF; \
477 (rep) = &(esw)->offloads.vport_reps[i], \
478 (i) <= (nvfs); (i)++)
480 #define mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, nvfs) \
482 (rep) = &(esw)->offloads.vport_reps[i], \
483 (i) >= MLX5_VPORT_FIRST_VF; (i)--)
485 #define mlx5_esw_for_each_vf_vport_num(esw, vport, nvfs) \
486 for ((vport) = MLX5_VPORT_FIRST_VF; (vport) <= (nvfs); (vport)++)
488 #define mlx5_esw_for_each_vf_vport_num_reverse(esw, vport, nvfs) \
489 for ((vport) = (nvfs); (vport) >= MLX5_VPORT_FIRST_VF; (vport)--)
491 struct mlx5_vport *__must_check
492 mlx5_eswitch_get_vport(struct mlx5_eswitch *esw, u16 vport_num);
494 #else /* CONFIG_MLX5_ESWITCH */
495 /* eswitch API stubs */
496 static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; }
497 static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {}
498 static inline int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode) { return 0; }
499 static inline void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw) {}
500 static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, struct mlx5_core_dev *dev1) { return true; }
502 #define FDB_MAX_CHAIN 1
503 #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1)
504 #define FDB_MAX_PRIO 1
506 #endif /* CONFIG_MLX5_ESWITCH */
508 #endif /* __MLX5_ESWITCH_H__ */