2 * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include "lib/events.h"
35 #include "en_accel/ktls.h"
36 #include "en_accel/en_accel.h"
40 #ifdef CONFIG_PAGE_POOL_STATS
41 #include <net/page_pool/helpers.h>
44 static unsigned int stats_grps_num(struct mlx5e_priv *priv)
46 return !priv->profile->stats_grps_num ? 0 :
47 priv->profile->stats_grps_num(priv);
50 unsigned int mlx5e_stats_total_num(struct mlx5e_priv *priv)
52 mlx5e_stats_grp_t *stats_grps = priv->profile->stats_grps;
53 const unsigned int num_stats_grps = stats_grps_num(priv);
54 unsigned int total = 0;
57 for (i = 0; i < num_stats_grps; i++)
58 total += stats_grps[i]->get_num_stats(priv);
63 void mlx5e_stats_update_ndo_stats(struct mlx5e_priv *priv)
65 mlx5e_stats_grp_t *stats_grps = priv->profile->stats_grps;
66 const unsigned int num_stats_grps = stats_grps_num(priv);
69 for (i = num_stats_grps - 1; i >= 0; i--)
70 if (stats_grps[i]->update_stats &&
71 stats_grps[i]->update_stats_mask & MLX5E_NDO_UPDATE_STATS)
72 stats_grps[i]->update_stats(priv);
75 void mlx5e_stats_update(struct mlx5e_priv *priv)
77 mlx5e_stats_grp_t *stats_grps = priv->profile->stats_grps;
78 const unsigned int num_stats_grps = stats_grps_num(priv);
81 for (i = num_stats_grps - 1; i >= 0; i--)
82 if (stats_grps[i]->update_stats)
83 stats_grps[i]->update_stats(priv);
86 void mlx5e_stats_fill(struct mlx5e_priv *priv, u64 *data, int idx)
88 mlx5e_stats_grp_t *stats_grps = priv->profile->stats_grps;
89 const unsigned int num_stats_grps = stats_grps_num(priv);
92 for (i = 0; i < num_stats_grps; i++)
93 idx = stats_grps[i]->fill_stats(priv, data, idx);
96 void mlx5e_stats_fill_strings(struct mlx5e_priv *priv, u8 *data)
98 mlx5e_stats_grp_t *stats_grps = priv->profile->stats_grps;
99 const unsigned int num_stats_grps = stats_grps_num(priv);
102 for (i = 0; i < num_stats_grps; i++)
103 idx = stats_grps[i]->fill_strings(priv, data, idx);
106 /* Concrete NIC Stats */
108 static const struct counter_desc sw_stats_desc[] = {
109 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_packets) },
110 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_bytes) },
111 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_packets) },
112 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_bytes) },
113 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_packets) },
114 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_bytes) },
115 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_packets) },
116 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_bytes) },
117 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_added_vlan_packets) },
118 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_nop) },
119 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_mpwqe_blks) },
120 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_mpwqe_pkts) },
122 #ifdef CONFIG_MLX5_EN_TLS
123 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_encrypted_packets) },
124 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_encrypted_bytes) },
125 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_ooo) },
126 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_dump_packets) },
127 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_dump_bytes) },
128 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_resync_bytes) },
129 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_skip_no_sync_data) },
130 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_drop_no_sync_data) },
131 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tls_drop_bypass_req) },
134 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_packets) },
135 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_bytes) },
136 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_gro_packets) },
137 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_gro_bytes) },
138 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_gro_skbs) },
139 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_gro_match_packets) },
140 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_gro_large_hds) },
141 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_ecn_mark) },
142 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_removed_vlan_packets) },
143 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary) },
144 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_none) },
145 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete) },
146 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete_tail) },
147 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete_tail_slow) },
148 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary_inner) },
149 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_drop) },
150 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_redirect) },
151 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_xmit) },
152 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_mpwqe) },
153 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_inlnw) },
154 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_nops) },
155 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_full) },
156 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_err) },
157 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_cqe) },
158 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_none) },
159 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial) },
160 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial_inner) },
161 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_stopped) },
162 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_dropped) },
163 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xmit_more) },
164 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_recover) },
165 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_cqes) },
166 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_wake) },
167 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_cqe_err) },
168 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_xmit) },
169 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_mpwqe) },
170 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_inlnw) },
171 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_nops) },
172 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_full) },
173 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_err) },
174 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xdp_cqes) },
175 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_wqe_err) },
176 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler_cqes) },
177 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler_strides) },
178 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_oversize_pkts_sw_drop) },
179 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_buff_alloc_err) },
180 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_blks) },
181 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_pkts) },
182 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_congst_umr) },
183 #ifdef CONFIG_MLX5_EN_ARFS
184 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_arfs_add) },
185 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_arfs_request_in) },
186 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_arfs_request_out) },
187 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_arfs_expired) },
188 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_arfs_err) },
190 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_recover) },
191 #ifdef CONFIG_PAGE_POOL_STATS
192 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_alloc_fast) },
193 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_alloc_slow) },
194 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_alloc_slow_high_order) },
195 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_alloc_empty) },
196 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_alloc_refill) },
197 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_alloc_waive) },
198 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_recycle_cached) },
199 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_recycle_cache_full) },
200 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_recycle_ring) },
201 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_recycle_ring_full) },
202 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_pp_recycle_released_ref) },
204 #ifdef CONFIG_MLX5_EN_TLS
205 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_decrypted_packets) },
206 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_decrypted_bytes) },
207 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_resync_req_pkt) },
208 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_resync_req_start) },
209 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_resync_req_end) },
210 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_resync_req_skip) },
211 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_resync_res_ok) },
212 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_resync_res_retry) },
213 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_resync_res_skip) },
214 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_tls_err) },
216 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_events) },
217 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_poll) },
218 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_arm) },
219 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_aff_change) },
220 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_force_irq) },
221 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, ch_eq_rearm) },
222 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_packets) },
223 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_bytes) },
224 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_csum_complete) },
225 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_csum_unnecessary) },
226 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_csum_unnecessary_inner) },
227 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_csum_none) },
228 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_ecn_mark) },
229 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_removed_vlan_packets) },
230 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_xdp_drop) },
231 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_xdp_redirect) },
232 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_wqe_err) },
233 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_mpwqe_filler_cqes) },
234 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_mpwqe_filler_strides) },
235 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_oversize_pkts_sw_drop) },
236 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_buff_alloc_err) },
237 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_cqe_compress_blks) },
238 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_cqe_compress_pkts) },
239 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xsk_congst_umr) },
240 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_xmit) },
241 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_mpwqe) },
242 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_inlnw) },
243 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_full) },
244 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_err) },
245 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xsk_cqes) },
248 #define NUM_SW_COUNTERS ARRAY_SIZE(sw_stats_desc)
250 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(sw)
252 return NUM_SW_COUNTERS;
255 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(sw)
259 for (i = 0; i < NUM_SW_COUNTERS; i++)
260 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format);
264 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(sw)
268 for (i = 0; i < NUM_SW_COUNTERS; i++)
269 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw, sw_stats_desc, i);
273 static void mlx5e_stats_grp_sw_update_stats_xdp_red(struct mlx5e_sw_stats *s,
274 struct mlx5e_xdpsq_stats *xdpsq_red_stats)
276 s->tx_xdp_xmit += xdpsq_red_stats->xmit;
277 s->tx_xdp_mpwqe += xdpsq_red_stats->mpwqe;
278 s->tx_xdp_inlnw += xdpsq_red_stats->inlnw;
279 s->tx_xdp_nops += xdpsq_red_stats->nops;
280 s->tx_xdp_full += xdpsq_red_stats->full;
281 s->tx_xdp_err += xdpsq_red_stats->err;
282 s->tx_xdp_cqes += xdpsq_red_stats->cqes;
285 static void mlx5e_stats_grp_sw_update_stats_xdpsq(struct mlx5e_sw_stats *s,
286 struct mlx5e_xdpsq_stats *xdpsq_stats)
288 s->rx_xdp_tx_xmit += xdpsq_stats->xmit;
289 s->rx_xdp_tx_mpwqe += xdpsq_stats->mpwqe;
290 s->rx_xdp_tx_inlnw += xdpsq_stats->inlnw;
291 s->rx_xdp_tx_nops += xdpsq_stats->nops;
292 s->rx_xdp_tx_full += xdpsq_stats->full;
293 s->rx_xdp_tx_err += xdpsq_stats->err;
294 s->rx_xdp_tx_cqe += xdpsq_stats->cqes;
297 static void mlx5e_stats_grp_sw_update_stats_xsksq(struct mlx5e_sw_stats *s,
298 struct mlx5e_xdpsq_stats *xsksq_stats)
300 s->tx_xsk_xmit += xsksq_stats->xmit;
301 s->tx_xsk_mpwqe += xsksq_stats->mpwqe;
302 s->tx_xsk_inlnw += xsksq_stats->inlnw;
303 s->tx_xsk_full += xsksq_stats->full;
304 s->tx_xsk_err += xsksq_stats->err;
305 s->tx_xsk_cqes += xsksq_stats->cqes;
308 static void mlx5e_stats_grp_sw_update_stats_xskrq(struct mlx5e_sw_stats *s,
309 struct mlx5e_rq_stats *xskrq_stats)
311 s->rx_xsk_packets += xskrq_stats->packets;
312 s->rx_xsk_bytes += xskrq_stats->bytes;
313 s->rx_xsk_csum_complete += xskrq_stats->csum_complete;
314 s->rx_xsk_csum_unnecessary += xskrq_stats->csum_unnecessary;
315 s->rx_xsk_csum_unnecessary_inner += xskrq_stats->csum_unnecessary_inner;
316 s->rx_xsk_csum_none += xskrq_stats->csum_none;
317 s->rx_xsk_ecn_mark += xskrq_stats->ecn_mark;
318 s->rx_xsk_removed_vlan_packets += xskrq_stats->removed_vlan_packets;
319 s->rx_xsk_xdp_drop += xskrq_stats->xdp_drop;
320 s->rx_xsk_xdp_redirect += xskrq_stats->xdp_redirect;
321 s->rx_xsk_wqe_err += xskrq_stats->wqe_err;
322 s->rx_xsk_mpwqe_filler_cqes += xskrq_stats->mpwqe_filler_cqes;
323 s->rx_xsk_mpwqe_filler_strides += xskrq_stats->mpwqe_filler_strides;
324 s->rx_xsk_oversize_pkts_sw_drop += xskrq_stats->oversize_pkts_sw_drop;
325 s->rx_xsk_buff_alloc_err += xskrq_stats->buff_alloc_err;
326 s->rx_xsk_cqe_compress_blks += xskrq_stats->cqe_compress_blks;
327 s->rx_xsk_cqe_compress_pkts += xskrq_stats->cqe_compress_pkts;
328 s->rx_xsk_congst_umr += xskrq_stats->congst_umr;
331 static void mlx5e_stats_grp_sw_update_stats_rq_stats(struct mlx5e_sw_stats *s,
332 struct mlx5e_rq_stats *rq_stats)
334 s->rx_packets += rq_stats->packets;
335 s->rx_bytes += rq_stats->bytes;
336 s->rx_lro_packets += rq_stats->lro_packets;
337 s->rx_lro_bytes += rq_stats->lro_bytes;
338 s->rx_gro_packets += rq_stats->gro_packets;
339 s->rx_gro_bytes += rq_stats->gro_bytes;
340 s->rx_gro_skbs += rq_stats->gro_skbs;
341 s->rx_gro_match_packets += rq_stats->gro_match_packets;
342 s->rx_gro_large_hds += rq_stats->gro_large_hds;
343 s->rx_ecn_mark += rq_stats->ecn_mark;
344 s->rx_removed_vlan_packets += rq_stats->removed_vlan_packets;
345 s->rx_csum_none += rq_stats->csum_none;
346 s->rx_csum_complete += rq_stats->csum_complete;
347 s->rx_csum_complete_tail += rq_stats->csum_complete_tail;
348 s->rx_csum_complete_tail_slow += rq_stats->csum_complete_tail_slow;
349 s->rx_csum_unnecessary += rq_stats->csum_unnecessary;
350 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
351 s->rx_xdp_drop += rq_stats->xdp_drop;
352 s->rx_xdp_redirect += rq_stats->xdp_redirect;
353 s->rx_wqe_err += rq_stats->wqe_err;
354 s->rx_mpwqe_filler_cqes += rq_stats->mpwqe_filler_cqes;
355 s->rx_mpwqe_filler_strides += rq_stats->mpwqe_filler_strides;
356 s->rx_oversize_pkts_sw_drop += rq_stats->oversize_pkts_sw_drop;
357 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
358 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
359 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
360 s->rx_congst_umr += rq_stats->congst_umr;
361 #ifdef CONFIG_MLX5_EN_ARFS
362 s->rx_arfs_add += rq_stats->arfs_add;
363 s->rx_arfs_request_in += rq_stats->arfs_request_in;
364 s->rx_arfs_request_out += rq_stats->arfs_request_out;
365 s->rx_arfs_expired += rq_stats->arfs_expired;
366 s->rx_arfs_err += rq_stats->arfs_err;
368 s->rx_recover += rq_stats->recover;
369 #ifdef CONFIG_PAGE_POOL_STATS
370 s->rx_pp_alloc_fast += rq_stats->pp_alloc_fast;
371 s->rx_pp_alloc_slow += rq_stats->pp_alloc_slow;
372 s->rx_pp_alloc_empty += rq_stats->pp_alloc_empty;
373 s->rx_pp_alloc_refill += rq_stats->pp_alloc_refill;
374 s->rx_pp_alloc_waive += rq_stats->pp_alloc_waive;
375 s->rx_pp_alloc_slow_high_order += rq_stats->pp_alloc_slow_high_order;
376 s->rx_pp_recycle_cached += rq_stats->pp_recycle_cached;
377 s->rx_pp_recycle_cache_full += rq_stats->pp_recycle_cache_full;
378 s->rx_pp_recycle_ring += rq_stats->pp_recycle_ring;
379 s->rx_pp_recycle_ring_full += rq_stats->pp_recycle_ring_full;
380 s->rx_pp_recycle_released_ref += rq_stats->pp_recycle_released_ref;
382 #ifdef CONFIG_MLX5_EN_TLS
383 s->rx_tls_decrypted_packets += rq_stats->tls_decrypted_packets;
384 s->rx_tls_decrypted_bytes += rq_stats->tls_decrypted_bytes;
385 s->rx_tls_resync_req_pkt += rq_stats->tls_resync_req_pkt;
386 s->rx_tls_resync_req_start += rq_stats->tls_resync_req_start;
387 s->rx_tls_resync_req_end += rq_stats->tls_resync_req_end;
388 s->rx_tls_resync_req_skip += rq_stats->tls_resync_req_skip;
389 s->rx_tls_resync_res_ok += rq_stats->tls_resync_res_ok;
390 s->rx_tls_resync_res_retry += rq_stats->tls_resync_res_retry;
391 s->rx_tls_resync_res_skip += rq_stats->tls_resync_res_skip;
392 s->rx_tls_err += rq_stats->tls_err;
396 static void mlx5e_stats_grp_sw_update_stats_ch_stats(struct mlx5e_sw_stats *s,
397 struct mlx5e_ch_stats *ch_stats)
399 s->ch_events += ch_stats->events;
400 s->ch_poll += ch_stats->poll;
401 s->ch_arm += ch_stats->arm;
402 s->ch_aff_change += ch_stats->aff_change;
403 s->ch_force_irq += ch_stats->force_irq;
404 s->ch_eq_rearm += ch_stats->eq_rearm;
407 static void mlx5e_stats_grp_sw_update_stats_sq(struct mlx5e_sw_stats *s,
408 struct mlx5e_sq_stats *sq_stats)
410 s->tx_packets += sq_stats->packets;
411 s->tx_bytes += sq_stats->bytes;
412 s->tx_tso_packets += sq_stats->tso_packets;
413 s->tx_tso_bytes += sq_stats->tso_bytes;
414 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
415 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
416 s->tx_added_vlan_packets += sq_stats->added_vlan_packets;
417 s->tx_nop += sq_stats->nop;
418 s->tx_mpwqe_blks += sq_stats->mpwqe_blks;
419 s->tx_mpwqe_pkts += sq_stats->mpwqe_pkts;
420 s->tx_queue_stopped += sq_stats->stopped;
421 s->tx_queue_wake += sq_stats->wake;
422 s->tx_queue_dropped += sq_stats->dropped;
423 s->tx_cqe_err += sq_stats->cqe_err;
424 s->tx_recover += sq_stats->recover;
425 s->tx_xmit_more += sq_stats->xmit_more;
426 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
427 s->tx_csum_none += sq_stats->csum_none;
428 s->tx_csum_partial += sq_stats->csum_partial;
429 #ifdef CONFIG_MLX5_EN_TLS
430 s->tx_tls_encrypted_packets += sq_stats->tls_encrypted_packets;
431 s->tx_tls_encrypted_bytes += sq_stats->tls_encrypted_bytes;
432 s->tx_tls_ooo += sq_stats->tls_ooo;
433 s->tx_tls_dump_bytes += sq_stats->tls_dump_bytes;
434 s->tx_tls_dump_packets += sq_stats->tls_dump_packets;
435 s->tx_tls_resync_bytes += sq_stats->tls_resync_bytes;
436 s->tx_tls_skip_no_sync_data += sq_stats->tls_skip_no_sync_data;
437 s->tx_tls_drop_no_sync_data += sq_stats->tls_drop_no_sync_data;
438 s->tx_tls_drop_bypass_req += sq_stats->tls_drop_bypass_req;
440 s->tx_cqes += sq_stats->cqes;
443 static void mlx5e_stats_grp_sw_update_stats_ptp(struct mlx5e_priv *priv,
444 struct mlx5e_sw_stats *s)
448 if (!priv->tx_ptp_opened && !priv->rx_ptp_opened)
451 mlx5e_stats_grp_sw_update_stats_ch_stats(s, &priv->ptp_stats.ch);
453 if (priv->tx_ptp_opened) {
454 for (i = 0; i < priv->max_opened_tc; i++) {
455 mlx5e_stats_grp_sw_update_stats_sq(s, &priv->ptp_stats.sq[i]);
457 /* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92657 */
461 if (priv->rx_ptp_opened) {
462 mlx5e_stats_grp_sw_update_stats_rq_stats(s, &priv->ptp_stats.rq);
464 /* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92657 */
469 static void mlx5e_stats_grp_sw_update_stats_qos(struct mlx5e_priv *priv,
470 struct mlx5e_sw_stats *s)
472 struct mlx5e_sq_stats **stats;
476 /* Pairs with smp_store_release in mlx5e_open_qos_sq. */
477 max_qos_sqs = smp_load_acquire(&priv->htb_max_qos_sqs);
478 stats = READ_ONCE(priv->htb_qos_sq_stats);
480 for (i = 0; i < max_qos_sqs; i++) {
481 mlx5e_stats_grp_sw_update_stats_sq(s, READ_ONCE(stats[i]));
483 /* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92657 */
488 #ifdef CONFIG_PAGE_POOL_STATS
489 static void mlx5e_stats_update_stats_rq_page_pool(struct mlx5e_channel *c)
491 struct mlx5e_rq_stats *rq_stats = c->rq.stats;
492 struct page_pool *pool = c->rq.page_pool;
493 struct page_pool_stats stats = { 0 };
495 if (!page_pool_get_stats(pool, &stats))
498 rq_stats->pp_alloc_fast = stats.alloc_stats.fast;
499 rq_stats->pp_alloc_slow = stats.alloc_stats.slow;
500 rq_stats->pp_alloc_slow_high_order = stats.alloc_stats.slow_high_order;
501 rq_stats->pp_alloc_empty = stats.alloc_stats.empty;
502 rq_stats->pp_alloc_waive = stats.alloc_stats.waive;
503 rq_stats->pp_alloc_refill = stats.alloc_stats.refill;
505 rq_stats->pp_recycle_cached = stats.recycle_stats.cached;
506 rq_stats->pp_recycle_cache_full = stats.recycle_stats.cache_full;
507 rq_stats->pp_recycle_ring = stats.recycle_stats.ring;
508 rq_stats->pp_recycle_ring_full = stats.recycle_stats.ring_full;
509 rq_stats->pp_recycle_released_ref = stats.recycle_stats.released_refcnt;
512 static void mlx5e_stats_update_stats_rq_page_pool(struct mlx5e_channel *c)
517 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(sw)
519 struct mlx5e_sw_stats *s = &priv->stats.sw;
522 memset(s, 0, sizeof(*s));
524 for (i = 0; i < priv->channels.num; i++) /* for active channels only */
525 mlx5e_stats_update_stats_rq_page_pool(priv->channels.c[i]);
527 for (i = 0; i < priv->stats_nch; i++) {
528 struct mlx5e_channel_stats *channel_stats =
529 priv->channel_stats[i];
533 mlx5e_stats_grp_sw_update_stats_rq_stats(s, &channel_stats->rq);
534 mlx5e_stats_grp_sw_update_stats_xdpsq(s, &channel_stats->rq_xdpsq);
535 mlx5e_stats_grp_sw_update_stats_ch_stats(s, &channel_stats->ch);
537 mlx5e_stats_grp_sw_update_stats_xdp_red(s, &channel_stats->xdpsq);
538 /* AF_XDP zero-copy */
539 mlx5e_stats_grp_sw_update_stats_xskrq(s, &channel_stats->xskrq);
540 mlx5e_stats_grp_sw_update_stats_xsksq(s, &channel_stats->xsksq);
542 for (j = 0; j < priv->max_opened_tc; j++) {
543 mlx5e_stats_grp_sw_update_stats_sq(s, &channel_stats->sq[j]);
545 /* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92657 */
549 mlx5e_stats_grp_sw_update_stats_ptp(priv, s);
550 mlx5e_stats_grp_sw_update_stats_qos(priv, s);
553 static const struct counter_desc q_stats_desc[] = {
554 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_out_of_buffer) },
557 static const struct counter_desc drop_rq_stats_desc[] = {
558 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_if_down_packets) },
561 #define NUM_Q_COUNTERS ARRAY_SIZE(q_stats_desc)
562 #define NUM_DROP_RQ_COUNTERS ARRAY_SIZE(drop_rq_stats_desc)
564 static bool q_counter_any(struct mlx5e_priv *priv)
566 struct mlx5_core_dev *pos;
569 mlx5_sd_for_each_dev(i, priv->mdev, pos)
570 if (priv->q_counter[i++])
576 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(qcnt)
580 if (q_counter_any(priv))
581 num_stats += NUM_Q_COUNTERS;
583 if (priv->drop_rq_q_counter)
584 num_stats += NUM_DROP_RQ_COUNTERS;
589 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(qcnt)
593 for (i = 0; i < NUM_Q_COUNTERS && q_counter_any(priv); i++)
594 strcpy(data + (idx++) * ETH_GSTRING_LEN,
595 q_stats_desc[i].format);
597 for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++)
598 strcpy(data + (idx++) * ETH_GSTRING_LEN,
599 drop_rq_stats_desc[i].format);
604 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(qcnt)
608 for (i = 0; i < NUM_Q_COUNTERS && q_counter_any(priv); i++)
609 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
611 for (i = 0; i < NUM_DROP_RQ_COUNTERS && priv->drop_rq_q_counter; i++)
612 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
613 drop_rq_stats_desc, i);
617 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(qcnt)
619 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
620 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)] = {};
621 u32 in[MLX5_ST_SZ_DW(query_q_counter_in)] = {};
622 struct mlx5_core_dev *pos;
623 u32 rx_out_of_buffer = 0;
626 MLX5_SET(query_q_counter_in, in, opcode, MLX5_CMD_OP_QUERY_Q_COUNTER);
628 mlx5_sd_for_each_dev(i, priv->mdev, pos) {
629 if (priv->q_counter[i]) {
630 MLX5_SET(query_q_counter_in, in, counter_set_id,
632 ret = mlx5_cmd_exec_inout(pos, query_q_counter, in, out);
634 rx_out_of_buffer += MLX5_GET(query_q_counter_out,
638 qcnt->rx_out_of_buffer = rx_out_of_buffer;
640 if (priv->drop_rq_q_counter) {
641 MLX5_SET(query_q_counter_in, in, counter_set_id,
642 priv->drop_rq_q_counter);
643 ret = mlx5_cmd_exec_inout(priv->mdev, query_q_counter, in, out);
645 qcnt->rx_if_down_packets = MLX5_GET(query_q_counter_out,
650 #define VNIC_ENV_OFF(c) MLX5_BYTE_OFF(query_vnic_env_out, c)
651 static const struct counter_desc vnic_env_stats_steer_desc[] = {
652 { "rx_steer_missed_packets",
653 VNIC_ENV_OFF(vport_env.nic_receive_steering_discard) },
656 static const struct counter_desc vnic_env_stats_dev_oob_desc[] = {
657 { "dev_internal_queue_oob",
658 VNIC_ENV_OFF(vport_env.internal_rq_out_of_buffer) },
661 static const struct counter_desc vnic_env_stats_drop_desc[] = {
662 { "rx_oversize_pkts_buffer",
663 VNIC_ENV_OFF(vport_env.eth_wqe_too_small) },
666 #define NUM_VNIC_ENV_STEER_COUNTERS(dev) \
667 (MLX5_CAP_GEN(dev, nic_receive_steering_discard) ? \
668 ARRAY_SIZE(vnic_env_stats_steer_desc) : 0)
669 #define NUM_VNIC_ENV_DEV_OOB_COUNTERS(dev) \
670 (MLX5_CAP_GEN(dev, vnic_env_int_rq_oob) ? \
671 ARRAY_SIZE(vnic_env_stats_dev_oob_desc) : 0)
672 #define NUM_VNIC_ENV_DROP_COUNTERS(dev) \
673 (MLX5_CAP_GEN(dev, eth_wqe_too_small) ? \
674 ARRAY_SIZE(vnic_env_stats_drop_desc) : 0)
676 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(vnic_env)
678 return NUM_VNIC_ENV_STEER_COUNTERS(priv->mdev) +
679 NUM_VNIC_ENV_DEV_OOB_COUNTERS(priv->mdev) +
680 NUM_VNIC_ENV_DROP_COUNTERS(priv->mdev);
683 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(vnic_env)
687 for (i = 0; i < NUM_VNIC_ENV_STEER_COUNTERS(priv->mdev); i++)
688 strcpy(data + (idx++) * ETH_GSTRING_LEN,
689 vnic_env_stats_steer_desc[i].format);
691 for (i = 0; i < NUM_VNIC_ENV_DEV_OOB_COUNTERS(priv->mdev); i++)
692 strcpy(data + (idx++) * ETH_GSTRING_LEN,
693 vnic_env_stats_dev_oob_desc[i].format);
695 for (i = 0; i < NUM_VNIC_ENV_DROP_COUNTERS(priv->mdev); i++)
696 strcpy(data + (idx++) * ETH_GSTRING_LEN,
697 vnic_env_stats_drop_desc[i].format);
702 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(vnic_env)
706 for (i = 0; i < NUM_VNIC_ENV_STEER_COUNTERS(priv->mdev); i++)
707 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vnic.query_vnic_env_out,
708 vnic_env_stats_steer_desc, i);
710 for (i = 0; i < NUM_VNIC_ENV_DEV_OOB_COUNTERS(priv->mdev); i++)
711 data[idx++] = MLX5E_READ_CTR32_BE(priv->stats.vnic.query_vnic_env_out,
712 vnic_env_stats_dev_oob_desc, i);
714 for (i = 0; i < NUM_VNIC_ENV_DROP_COUNTERS(priv->mdev); i++)
715 data[idx++] = MLX5E_READ_CTR32_BE(priv->stats.vnic.query_vnic_env_out,
716 vnic_env_stats_drop_desc, i);
721 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(vnic_env)
723 u32 *out = (u32 *)priv->stats.vnic.query_vnic_env_out;
724 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {};
725 struct mlx5_core_dev *mdev = priv->mdev;
727 if (!mlx5e_stats_grp_vnic_env_num_stats(priv))
730 MLX5_SET(query_vnic_env_in, in, opcode, MLX5_CMD_OP_QUERY_VNIC_ENV);
731 mlx5_cmd_exec_inout(mdev, query_vnic_env, in, out);
734 #define VPORT_COUNTER_OFF(c) MLX5_BYTE_OFF(query_vport_counter_out, c)
735 static const struct counter_desc vport_stats_desc[] = {
736 { "rx_vport_unicast_packets",
737 VPORT_COUNTER_OFF(received_eth_unicast.packets) },
738 { "rx_vport_unicast_bytes",
739 VPORT_COUNTER_OFF(received_eth_unicast.octets) },
740 { "tx_vport_unicast_packets",
741 VPORT_COUNTER_OFF(transmitted_eth_unicast.packets) },
742 { "tx_vport_unicast_bytes",
743 VPORT_COUNTER_OFF(transmitted_eth_unicast.octets) },
744 { "rx_vport_multicast_packets",
745 VPORT_COUNTER_OFF(received_eth_multicast.packets) },
746 { "rx_vport_multicast_bytes",
747 VPORT_COUNTER_OFF(received_eth_multicast.octets) },
748 { "tx_vport_multicast_packets",
749 VPORT_COUNTER_OFF(transmitted_eth_multicast.packets) },
750 { "tx_vport_multicast_bytes",
751 VPORT_COUNTER_OFF(transmitted_eth_multicast.octets) },
752 { "rx_vport_broadcast_packets",
753 VPORT_COUNTER_OFF(received_eth_broadcast.packets) },
754 { "rx_vport_broadcast_bytes",
755 VPORT_COUNTER_OFF(received_eth_broadcast.octets) },
756 { "tx_vport_broadcast_packets",
757 VPORT_COUNTER_OFF(transmitted_eth_broadcast.packets) },
758 { "tx_vport_broadcast_bytes",
759 VPORT_COUNTER_OFF(transmitted_eth_broadcast.octets) },
760 { "rx_vport_rdma_unicast_packets",
761 VPORT_COUNTER_OFF(received_ib_unicast.packets) },
762 { "rx_vport_rdma_unicast_bytes",
763 VPORT_COUNTER_OFF(received_ib_unicast.octets) },
764 { "tx_vport_rdma_unicast_packets",
765 VPORT_COUNTER_OFF(transmitted_ib_unicast.packets) },
766 { "tx_vport_rdma_unicast_bytes",
767 VPORT_COUNTER_OFF(transmitted_ib_unicast.octets) },
768 { "rx_vport_rdma_multicast_packets",
769 VPORT_COUNTER_OFF(received_ib_multicast.packets) },
770 { "rx_vport_rdma_multicast_bytes",
771 VPORT_COUNTER_OFF(received_ib_multicast.octets) },
772 { "tx_vport_rdma_multicast_packets",
773 VPORT_COUNTER_OFF(transmitted_ib_multicast.packets) },
774 { "tx_vport_rdma_multicast_bytes",
775 VPORT_COUNTER_OFF(transmitted_ib_multicast.octets) },
778 static const struct counter_desc vport_loopback_stats_desc[] = {
779 { "vport_loopback_packets",
780 VPORT_COUNTER_OFF(local_loopback.packets) },
781 { "vport_loopback_bytes",
782 VPORT_COUNTER_OFF(local_loopback.octets) },
785 #define NUM_VPORT_COUNTERS ARRAY_SIZE(vport_stats_desc)
786 #define NUM_VPORT_LOOPBACK_COUNTERS(dev) \
787 (MLX5_CAP_GEN(dev, vport_counter_local_loopback) ? \
788 ARRAY_SIZE(vport_loopback_stats_desc) : 0)
790 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(vport)
792 return NUM_VPORT_COUNTERS +
793 NUM_VPORT_LOOPBACK_COUNTERS(priv->mdev);
796 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(vport)
800 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
801 strcpy(data + (idx++) * ETH_GSTRING_LEN, vport_stats_desc[i].format);
803 for (i = 0; i < NUM_VPORT_LOOPBACK_COUNTERS(priv->mdev); i++)
804 strcpy(data + (idx++) * ETH_GSTRING_LEN,
805 vport_loopback_stats_desc[i].format);
810 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(vport)
814 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
815 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
816 vport_stats_desc, i);
818 for (i = 0; i < NUM_VPORT_LOOPBACK_COUNTERS(priv->mdev); i++)
819 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
820 vport_loopback_stats_desc, i);
825 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(vport)
827 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
828 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {};
829 struct mlx5_core_dev *mdev = priv->mdev;
831 MLX5_SET(query_vport_counter_in, in, opcode, MLX5_CMD_OP_QUERY_VPORT_COUNTER);
832 mlx5_cmd_exec_inout(mdev, query_vport_counter, in, out);
835 #define PPORT_802_3_OFF(c) \
836 MLX5_BYTE_OFF(ppcnt_reg, \
837 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
838 static const struct counter_desc pport_802_3_stats_desc[] = {
839 { "tx_packets_phy", PPORT_802_3_OFF(a_frames_transmitted_ok) },
840 { "rx_packets_phy", PPORT_802_3_OFF(a_frames_received_ok) },
841 { "rx_crc_errors_phy", PPORT_802_3_OFF(a_frame_check_sequence_errors) },
842 { "tx_bytes_phy", PPORT_802_3_OFF(a_octets_transmitted_ok) },
843 { "rx_bytes_phy", PPORT_802_3_OFF(a_octets_received_ok) },
844 { "tx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_xmitted_ok) },
845 { "tx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_xmitted_ok) },
846 { "rx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_received_ok) },
847 { "rx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_received_ok) },
848 { "rx_in_range_len_errors_phy", PPORT_802_3_OFF(a_in_range_length_errors) },
849 { "rx_out_of_range_len_phy", PPORT_802_3_OFF(a_out_of_range_length_field) },
850 { "rx_oversize_pkts_phy", PPORT_802_3_OFF(a_frame_too_long_errors) },
851 { "rx_symbol_err_phy", PPORT_802_3_OFF(a_symbol_error_during_carrier) },
852 { "tx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_transmitted) },
853 { "rx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_received) },
854 { "rx_unsupported_op_phy", PPORT_802_3_OFF(a_unsupported_opcodes_received) },
855 { "rx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_received) },
856 { "tx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_transmitted) },
859 #define NUM_PPORT_802_3_COUNTERS ARRAY_SIZE(pport_802_3_stats_desc)
861 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(802_3)
863 return NUM_PPORT_802_3_COUNTERS;
866 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(802_3)
870 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
871 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_802_3_stats_desc[i].format);
875 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(802_3)
879 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
880 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
881 pport_802_3_stats_desc, i);
885 #define MLX5_BASIC_PPCNT_SUPPORTED(mdev) \
886 (MLX5_CAP_GEN(mdev, pcam_reg) ? MLX5_CAP_PCAM_REG(mdev, ppcnt) : 1)
888 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(802_3)
890 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
891 struct mlx5_core_dev *mdev = priv->mdev;
892 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
893 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
896 if (!MLX5_BASIC_PPCNT_SUPPORTED(mdev))
899 MLX5_SET(ppcnt_reg, in, local_port, 1);
900 out = pstats->IEEE_802_3_counters;
901 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
902 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
905 #define MLX5E_READ_CTR64_BE_F(ptr, set, c) \
906 be64_to_cpu(*(__be64 *)((char *)ptr + \
907 MLX5_BYTE_OFF(ppcnt_reg, \
908 counter_set.set.c##_high)))
910 static int mlx5e_stats_get_ieee(struct mlx5_core_dev *mdev,
911 u32 *ppcnt_ieee_802_3)
913 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
914 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
916 if (!MLX5_BASIC_PPCNT_SUPPORTED(mdev))
919 MLX5_SET(ppcnt_reg, in, local_port, 1);
920 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
921 return mlx5_core_access_reg(mdev, in, sz, ppcnt_ieee_802_3,
922 sz, MLX5_REG_PPCNT, 0, 0);
925 void mlx5e_stats_pause_get(struct mlx5e_priv *priv,
926 struct ethtool_pause_stats *pause_stats)
928 u32 ppcnt_ieee_802_3[MLX5_ST_SZ_DW(ppcnt_reg)];
929 struct mlx5_core_dev *mdev = priv->mdev;
931 if (mlx5e_stats_get_ieee(mdev, ppcnt_ieee_802_3))
934 pause_stats->tx_pause_frames =
935 MLX5E_READ_CTR64_BE_F(ppcnt_ieee_802_3,
936 eth_802_3_cntrs_grp_data_layout,
937 a_pause_mac_ctrl_frames_transmitted);
938 pause_stats->rx_pause_frames =
939 MLX5E_READ_CTR64_BE_F(ppcnt_ieee_802_3,
940 eth_802_3_cntrs_grp_data_layout,
941 a_pause_mac_ctrl_frames_received);
944 void mlx5e_stats_eth_phy_get(struct mlx5e_priv *priv,
945 struct ethtool_eth_phy_stats *phy_stats)
947 u32 ppcnt_ieee_802_3[MLX5_ST_SZ_DW(ppcnt_reg)];
948 struct mlx5_core_dev *mdev = priv->mdev;
950 if (mlx5e_stats_get_ieee(mdev, ppcnt_ieee_802_3))
953 phy_stats->SymbolErrorDuringCarrier =
954 MLX5E_READ_CTR64_BE_F(ppcnt_ieee_802_3,
955 eth_802_3_cntrs_grp_data_layout,
956 a_symbol_error_during_carrier);
959 void mlx5e_stats_eth_mac_get(struct mlx5e_priv *priv,
960 struct ethtool_eth_mac_stats *mac_stats)
962 u32 ppcnt_ieee_802_3[MLX5_ST_SZ_DW(ppcnt_reg)];
963 struct mlx5_core_dev *mdev = priv->mdev;
965 if (mlx5e_stats_get_ieee(mdev, ppcnt_ieee_802_3))
969 MLX5E_READ_CTR64_BE_F(ppcnt_ieee_802_3, \
970 eth_802_3_cntrs_grp_data_layout, \
973 mac_stats->FramesTransmittedOK = RD(a_frames_transmitted_ok);
974 mac_stats->FramesReceivedOK = RD(a_frames_received_ok);
975 mac_stats->FrameCheckSequenceErrors = RD(a_frame_check_sequence_errors);
976 mac_stats->OctetsTransmittedOK = RD(a_octets_transmitted_ok);
977 mac_stats->OctetsReceivedOK = RD(a_octets_received_ok);
978 mac_stats->MulticastFramesXmittedOK = RD(a_multicast_frames_xmitted_ok);
979 mac_stats->BroadcastFramesXmittedOK = RD(a_broadcast_frames_xmitted_ok);
980 mac_stats->MulticastFramesReceivedOK = RD(a_multicast_frames_received_ok);
981 mac_stats->BroadcastFramesReceivedOK = RD(a_broadcast_frames_received_ok);
982 mac_stats->InRangeLengthErrors = RD(a_in_range_length_errors);
983 mac_stats->OutOfRangeLengthField = RD(a_out_of_range_length_field);
984 mac_stats->FrameTooLongErrors = RD(a_frame_too_long_errors);
988 void mlx5e_stats_eth_ctrl_get(struct mlx5e_priv *priv,
989 struct ethtool_eth_ctrl_stats *ctrl_stats)
991 u32 ppcnt_ieee_802_3[MLX5_ST_SZ_DW(ppcnt_reg)];
992 struct mlx5_core_dev *mdev = priv->mdev;
994 if (mlx5e_stats_get_ieee(mdev, ppcnt_ieee_802_3))
997 ctrl_stats->MACControlFramesTransmitted =
998 MLX5E_READ_CTR64_BE_F(ppcnt_ieee_802_3,
999 eth_802_3_cntrs_grp_data_layout,
1000 a_mac_control_frames_transmitted);
1001 ctrl_stats->MACControlFramesReceived =
1002 MLX5E_READ_CTR64_BE_F(ppcnt_ieee_802_3,
1003 eth_802_3_cntrs_grp_data_layout,
1004 a_mac_control_frames_received);
1005 ctrl_stats->UnsupportedOpcodesReceived =
1006 MLX5E_READ_CTR64_BE_F(ppcnt_ieee_802_3,
1007 eth_802_3_cntrs_grp_data_layout,
1008 a_unsupported_opcodes_received);
1011 #define PPORT_2863_OFF(c) \
1012 MLX5_BYTE_OFF(ppcnt_reg, \
1013 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
1014 static const struct counter_desc pport_2863_stats_desc[] = {
1015 { "rx_discards_phy", PPORT_2863_OFF(if_in_discards) },
1016 { "tx_discards_phy", PPORT_2863_OFF(if_out_discards) },
1017 { "tx_errors_phy", PPORT_2863_OFF(if_out_errors) },
1020 #define NUM_PPORT_2863_COUNTERS ARRAY_SIZE(pport_2863_stats_desc)
1022 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(2863)
1024 return NUM_PPORT_2863_COUNTERS;
1027 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(2863)
1031 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
1032 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2863_stats_desc[i].format);
1036 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(2863)
1040 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
1041 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
1042 pport_2863_stats_desc, i);
1046 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(2863)
1048 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
1049 struct mlx5_core_dev *mdev = priv->mdev;
1050 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
1051 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1054 MLX5_SET(ppcnt_reg, in, local_port, 1);
1055 out = pstats->RFC_2863_counters;
1056 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
1057 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1060 #define PPORT_2819_OFF(c) \
1061 MLX5_BYTE_OFF(ppcnt_reg, \
1062 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
1063 static const struct counter_desc pport_2819_stats_desc[] = {
1064 { "rx_undersize_pkts_phy", PPORT_2819_OFF(ether_stats_undersize_pkts) },
1065 { "rx_fragments_phy", PPORT_2819_OFF(ether_stats_fragments) },
1066 { "rx_jabbers_phy", PPORT_2819_OFF(ether_stats_jabbers) },
1067 { "rx_64_bytes_phy", PPORT_2819_OFF(ether_stats_pkts64octets) },
1068 { "rx_65_to_127_bytes_phy", PPORT_2819_OFF(ether_stats_pkts65to127octets) },
1069 { "rx_128_to_255_bytes_phy", PPORT_2819_OFF(ether_stats_pkts128to255octets) },
1070 { "rx_256_to_511_bytes_phy", PPORT_2819_OFF(ether_stats_pkts256to511octets) },
1071 { "rx_512_to_1023_bytes_phy", PPORT_2819_OFF(ether_stats_pkts512to1023octets) },
1072 { "rx_1024_to_1518_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1024to1518octets) },
1073 { "rx_1519_to_2047_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1519to2047octets) },
1074 { "rx_2048_to_4095_bytes_phy", PPORT_2819_OFF(ether_stats_pkts2048to4095octets) },
1075 { "rx_4096_to_8191_bytes_phy", PPORT_2819_OFF(ether_stats_pkts4096to8191octets) },
1076 { "rx_8192_to_10239_bytes_phy", PPORT_2819_OFF(ether_stats_pkts8192to10239octets) },
1079 #define NUM_PPORT_2819_COUNTERS ARRAY_SIZE(pport_2819_stats_desc)
1081 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(2819)
1083 return NUM_PPORT_2819_COUNTERS;
1086 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(2819)
1090 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
1091 strcpy(data + (idx++) * ETH_GSTRING_LEN, pport_2819_stats_desc[i].format);
1095 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(2819)
1099 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
1100 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
1101 pport_2819_stats_desc, i);
1105 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(2819)
1107 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
1108 struct mlx5_core_dev *mdev = priv->mdev;
1109 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
1110 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1113 if (!MLX5_BASIC_PPCNT_SUPPORTED(mdev))
1116 MLX5_SET(ppcnt_reg, in, local_port, 1);
1117 out = pstats->RFC_2819_counters;
1118 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
1119 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1122 static const struct ethtool_rmon_hist_range mlx5e_rmon_ranges[] = {
1136 void mlx5e_stats_rmon_get(struct mlx5e_priv *priv,
1137 struct ethtool_rmon_stats *rmon,
1138 const struct ethtool_rmon_hist_range **ranges)
1140 u32 ppcnt_RFC_2819_counters[MLX5_ST_SZ_DW(ppcnt_reg)];
1141 struct mlx5_core_dev *mdev = priv->mdev;
1142 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
1143 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1145 MLX5_SET(ppcnt_reg, in, local_port, 1);
1146 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
1147 if (mlx5_core_access_reg(mdev, in, sz, ppcnt_RFC_2819_counters,
1148 sz, MLX5_REG_PPCNT, 0, 0))
1152 MLX5E_READ_CTR64_BE_F(ppcnt_RFC_2819_counters, \
1153 eth_2819_cntrs_grp_data_layout, \
1156 rmon->undersize_pkts = RD(ether_stats_undersize_pkts);
1157 rmon->fragments = RD(ether_stats_fragments);
1158 rmon->jabbers = RD(ether_stats_jabbers);
1160 rmon->hist[0] = RD(ether_stats_pkts64octets);
1161 rmon->hist[1] = RD(ether_stats_pkts65to127octets);
1162 rmon->hist[2] = RD(ether_stats_pkts128to255octets);
1163 rmon->hist[3] = RD(ether_stats_pkts256to511octets);
1164 rmon->hist[4] = RD(ether_stats_pkts512to1023octets);
1165 rmon->hist[5] = RD(ether_stats_pkts1024to1518octets);
1166 rmon->hist[6] = RD(ether_stats_pkts1519to2047octets);
1167 rmon->hist[7] = RD(ether_stats_pkts2048to4095octets);
1168 rmon->hist[8] = RD(ether_stats_pkts4096to8191octets);
1169 rmon->hist[9] = RD(ether_stats_pkts8192to10239octets);
1172 *ranges = mlx5e_rmon_ranges;
1175 #define PPORT_PHY_STATISTICAL_OFF(c) \
1176 MLX5_BYTE_OFF(ppcnt_reg, \
1177 counter_set.phys_layer_statistical_cntrs.c##_high)
1178 static const struct counter_desc pport_phy_statistical_stats_desc[] = {
1179 { "rx_pcs_symbol_err_phy", PPORT_PHY_STATISTICAL_OFF(phy_symbol_errors) },
1180 { "rx_corrected_bits_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits) },
1183 static const struct counter_desc
1184 pport_phy_statistical_err_lanes_stats_desc[] = {
1185 { "rx_err_lane_0_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane0) },
1186 { "rx_err_lane_1_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane1) },
1187 { "rx_err_lane_2_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane2) },
1188 { "rx_err_lane_3_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits_lane3) },
1191 #define NUM_PPORT_PHY_STATISTICAL_COUNTERS \
1192 ARRAY_SIZE(pport_phy_statistical_stats_desc)
1193 #define NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS \
1194 ARRAY_SIZE(pport_phy_statistical_err_lanes_stats_desc)
1196 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(phy)
1198 struct mlx5_core_dev *mdev = priv->mdev;
1201 /* "1" for link_down_events special counter */
1204 num_stats += MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) ?
1205 NUM_PPORT_PHY_STATISTICAL_COUNTERS : 0;
1207 num_stats += MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters) ?
1208 NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS : 0;
1213 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(phy)
1215 struct mlx5_core_dev *mdev = priv->mdev;
1218 strcpy(data + (idx++) * ETH_GSTRING_LEN, "link_down_events_phy");
1220 if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group))
1223 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++)
1224 strcpy(data + (idx++) * ETH_GSTRING_LEN,
1225 pport_phy_statistical_stats_desc[i].format);
1227 if (MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters))
1228 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS; i++)
1229 strcpy(data + (idx++) * ETH_GSTRING_LEN,
1230 pport_phy_statistical_err_lanes_stats_desc[i].format);
1235 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(phy)
1237 struct mlx5_core_dev *mdev = priv->mdev;
1240 /* link_down_events_phy has special handling since it is not stored in __be64 format */
1241 data[idx++] = MLX5_GET(ppcnt_reg, priv->stats.pport.phy_counters,
1242 counter_set.phys_layer_cntrs.link_down_events);
1244 if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group))
1247 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS; i++)
1249 MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters,
1250 pport_phy_statistical_stats_desc, i);
1252 if (MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters))
1253 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_PER_LANE_COUNTERS; i++)
1255 MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters,
1256 pport_phy_statistical_err_lanes_stats_desc,
1261 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(phy)
1263 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
1264 struct mlx5_core_dev *mdev = priv->mdev;
1265 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
1266 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1269 MLX5_SET(ppcnt_reg, in, local_port, 1);
1270 out = pstats->phy_counters;
1271 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
1272 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1274 if (!MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group))
1277 out = pstats->phy_statistical_counters;
1278 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
1279 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1282 void mlx5e_get_link_ext_stats(struct net_device *dev,
1283 struct ethtool_link_ext_stats *stats)
1285 struct mlx5e_priv *priv = netdev_priv(dev);
1286 u32 out[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
1287 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
1288 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1290 MLX5_SET(ppcnt_reg, in, local_port, 1);
1291 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
1292 mlx5_core_access_reg(priv->mdev, in, sz, out,
1293 MLX5_ST_SZ_BYTES(ppcnt_reg), MLX5_REG_PPCNT, 0, 0);
1295 stats->link_down_events = MLX5_GET(ppcnt_reg, out,
1296 counter_set.phys_layer_cntrs.link_down_events);
1299 static int fec_num_lanes(struct mlx5_core_dev *dev)
1301 u32 out[MLX5_ST_SZ_DW(pmlp_reg)] = {};
1302 u32 in[MLX5_ST_SZ_DW(pmlp_reg)] = {};
1305 MLX5_SET(pmlp_reg, in, local_port, 1);
1306 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
1307 MLX5_REG_PMLP, 0, 0);
1311 return MLX5_GET(pmlp_reg, out, width);
1314 static int fec_active_mode(struct mlx5_core_dev *mdev)
1316 unsigned long fec_active_long;
1319 if (mlx5e_get_fec_mode(mdev, &fec_active, NULL))
1320 return MLX5E_FEC_NOFEC;
1322 fec_active_long = fec_active;
1323 return find_first_bit(&fec_active_long, sizeof(unsigned long) * BITS_PER_BYTE);
1326 #define MLX5E_STATS_SET_FEC_BLOCK(idx) ({ \
1327 fec_stats->corrected_blocks.lanes[(idx)] = \
1328 MLX5E_READ_CTR64_BE_F(ppcnt, phys_layer_cntrs, \
1329 fc_fec_corrected_blocks_lane##idx); \
1330 fec_stats->uncorrectable_blocks.lanes[(idx)] = \
1331 MLX5E_READ_CTR64_BE_F(ppcnt, phys_layer_cntrs, \
1332 fc_fec_uncorrectable_blocks_lane##idx); \
1335 static void fec_set_fc_stats(struct ethtool_fec_stats *fec_stats,
1336 u32 *ppcnt, u8 lanes)
1338 if (lanes > 3) { /* 4 lanes */
1339 MLX5E_STATS_SET_FEC_BLOCK(3);
1340 MLX5E_STATS_SET_FEC_BLOCK(2);
1342 if (lanes > 1) /* 2 lanes */
1343 MLX5E_STATS_SET_FEC_BLOCK(1);
1344 if (lanes > 0) /* 1 lane */
1345 MLX5E_STATS_SET_FEC_BLOCK(0);
1348 static void fec_set_rs_stats(struct ethtool_fec_stats *fec_stats, u32 *ppcnt)
1350 fec_stats->corrected_blocks.total =
1351 MLX5E_READ_CTR64_BE_F(ppcnt, phys_layer_cntrs,
1352 rs_fec_corrected_blocks);
1353 fec_stats->uncorrectable_blocks.total =
1354 MLX5E_READ_CTR64_BE_F(ppcnt, phys_layer_cntrs,
1355 rs_fec_uncorrectable_blocks);
1358 static void fec_set_block_stats(struct mlx5e_priv *priv,
1359 struct ethtool_fec_stats *fec_stats)
1361 struct mlx5_core_dev *mdev = priv->mdev;
1362 u32 out[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
1363 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
1364 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1365 int mode = fec_active_mode(mdev);
1367 if (mode == MLX5E_FEC_NOFEC)
1370 MLX5_SET(ppcnt_reg, in, local_port, 1);
1371 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
1372 if (mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0))
1376 case MLX5E_FEC_RS_528_514:
1377 case MLX5E_FEC_RS_544_514:
1378 case MLX5E_FEC_LLRS_272_257_1:
1379 fec_set_rs_stats(fec_stats, out);
1381 case MLX5E_FEC_FIRECODE:
1382 fec_set_fc_stats(fec_stats, out, fec_num_lanes(mdev));
1386 static void fec_set_corrected_bits_total(struct mlx5e_priv *priv,
1387 struct ethtool_fec_stats *fec_stats)
1389 u32 ppcnt_phy_statistical[MLX5_ST_SZ_DW(ppcnt_reg)];
1390 struct mlx5_core_dev *mdev = priv->mdev;
1391 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
1392 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1394 MLX5_SET(ppcnt_reg, in, local_port, 1);
1395 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
1396 if (mlx5_core_access_reg(mdev, in, sz, ppcnt_phy_statistical,
1397 sz, MLX5_REG_PPCNT, 0, 0))
1400 fec_stats->corrected_bits.total =
1401 MLX5E_READ_CTR64_BE_F(ppcnt_phy_statistical,
1402 phys_layer_statistical_cntrs,
1403 phy_corrected_bits);
1406 void mlx5e_stats_fec_get(struct mlx5e_priv *priv,
1407 struct ethtool_fec_stats *fec_stats)
1409 if (!MLX5_CAP_PCAM_FEATURE(priv->mdev, ppcnt_statistical_group))
1412 fec_set_corrected_bits_total(priv, fec_stats);
1413 fec_set_block_stats(priv, fec_stats);
1416 #define PPORT_ETH_EXT_OFF(c) \
1417 MLX5_BYTE_OFF(ppcnt_reg, \
1418 counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
1419 static const struct counter_desc pport_eth_ext_stats_desc[] = {
1420 { "rx_buffer_passed_thres_phy", PPORT_ETH_EXT_OFF(rx_buffer_almost_full) },
1423 #define NUM_PPORT_ETH_EXT_COUNTERS ARRAY_SIZE(pport_eth_ext_stats_desc)
1425 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(eth_ext)
1427 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
1428 return NUM_PPORT_ETH_EXT_COUNTERS;
1433 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(eth_ext)
1437 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
1438 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++)
1439 strcpy(data + (idx++) * ETH_GSTRING_LEN,
1440 pport_eth_ext_stats_desc[i].format);
1444 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(eth_ext)
1448 if (MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
1449 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS; i++)
1451 MLX5E_READ_CTR64_BE(&priv->stats.pport.eth_ext_counters,
1452 pport_eth_ext_stats_desc, i);
1456 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(eth_ext)
1458 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
1459 struct mlx5_core_dev *mdev = priv->mdev;
1460 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
1461 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1464 if (!MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters))
1467 MLX5_SET(ppcnt_reg, in, local_port, 1);
1468 out = pstats->eth_ext_counters;
1469 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
1470 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1473 #define PCIE_PERF_OFF(c) \
1474 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c)
1475 static const struct counter_desc pcie_perf_stats_desc[] = {
1476 { "rx_pci_signal_integrity", PCIE_PERF_OFF(rx_errors) },
1477 { "tx_pci_signal_integrity", PCIE_PERF_OFF(tx_errors) },
1480 #define PCIE_PERF_OFF64(c) \
1481 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
1482 static const struct counter_desc pcie_perf_stats_desc64[] = {
1483 { "outbound_pci_buffer_overflow", PCIE_PERF_OFF64(tx_overflow_buffer_pkt) },
1486 static const struct counter_desc pcie_perf_stall_stats_desc[] = {
1487 { "outbound_pci_stalled_rd", PCIE_PERF_OFF(outbound_stalled_reads) },
1488 { "outbound_pci_stalled_wr", PCIE_PERF_OFF(outbound_stalled_writes) },
1489 { "outbound_pci_stalled_rd_events", PCIE_PERF_OFF(outbound_stalled_reads_events) },
1490 { "outbound_pci_stalled_wr_events", PCIE_PERF_OFF(outbound_stalled_writes_events) },
1493 #define NUM_PCIE_PERF_COUNTERS ARRAY_SIZE(pcie_perf_stats_desc)
1494 #define NUM_PCIE_PERF_COUNTERS64 ARRAY_SIZE(pcie_perf_stats_desc64)
1495 #define NUM_PCIE_PERF_STALL_COUNTERS ARRAY_SIZE(pcie_perf_stall_stats_desc)
1497 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(pcie)
1501 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
1502 num_stats += NUM_PCIE_PERF_COUNTERS;
1504 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
1505 num_stats += NUM_PCIE_PERF_COUNTERS64;
1507 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
1508 num_stats += NUM_PCIE_PERF_STALL_COUNTERS;
1513 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(pcie)
1517 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
1518 for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)
1519 strcpy(data + (idx++) * ETH_GSTRING_LEN,
1520 pcie_perf_stats_desc[i].format);
1522 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
1523 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++)
1524 strcpy(data + (idx++) * ETH_GSTRING_LEN,
1525 pcie_perf_stats_desc64[i].format);
1527 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
1528 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++)
1529 strcpy(data + (idx++) * ETH_GSTRING_LEN,
1530 pcie_perf_stall_stats_desc[i].format);
1534 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(pcie)
1538 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
1539 for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)
1541 MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
1542 pcie_perf_stats_desc, i);
1544 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
1545 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64; i++)
1547 MLX5E_READ_CTR64_BE(&priv->stats.pcie.pcie_perf_counters,
1548 pcie_perf_stats_desc64, i);
1550 if (MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
1551 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS; i++)
1553 MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
1554 pcie_perf_stall_stats_desc, i);
1558 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(pcie)
1560 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
1561 struct mlx5_core_dev *mdev = priv->mdev;
1562 u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
1563 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
1566 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
1569 out = pcie_stats->pcie_perf_counters;
1570 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
1571 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
1574 #define PPORT_PER_TC_PRIO_OFF(c) \
1575 MLX5_BYTE_OFF(ppcnt_reg, \
1576 counter_set.eth_per_tc_prio_grp_data_layout.c##_high)
1578 static const struct counter_desc pport_per_tc_prio_stats_desc[] = {
1579 { "rx_prio%d_buf_discard", PPORT_PER_TC_PRIO_OFF(no_buffer_discard_uc) },
1582 #define NUM_PPORT_PER_TC_PRIO_COUNTERS ARRAY_SIZE(pport_per_tc_prio_stats_desc)
1584 #define PPORT_PER_TC_CONGEST_PRIO_OFF(c) \
1585 MLX5_BYTE_OFF(ppcnt_reg, \
1586 counter_set.eth_per_tc_congest_prio_grp_data_layout.c##_high)
1588 static const struct counter_desc pport_per_tc_congest_prio_stats_desc[] = {
1589 { "rx_prio%d_cong_discard", PPORT_PER_TC_CONGEST_PRIO_OFF(wred_discard) },
1590 { "rx_prio%d_marked", PPORT_PER_TC_CONGEST_PRIO_OFF(ecn_marked_tc) },
1593 #define NUM_PPORT_PER_TC_CONGEST_PRIO_COUNTERS \
1594 ARRAY_SIZE(pport_per_tc_congest_prio_stats_desc)
1596 static int mlx5e_grp_per_tc_prio_get_num_stats(struct mlx5e_priv *priv)
1598 struct mlx5_core_dev *mdev = priv->mdev;
1600 if (!MLX5_CAP_GEN(mdev, sbcam_reg))
1603 return NUM_PPORT_PER_TC_PRIO_COUNTERS * NUM_PPORT_PRIO;
1606 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(per_port_buff_congest)
1608 struct mlx5_core_dev *mdev = priv->mdev;
1611 if (!MLX5_CAP_GEN(mdev, sbcam_reg))
1614 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1615 for (i = 0; i < NUM_PPORT_PER_TC_PRIO_COUNTERS; i++)
1616 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1617 pport_per_tc_prio_stats_desc[i].format, prio);
1618 for (i = 0; i < NUM_PPORT_PER_TC_CONGEST_PRIO_COUNTERS; i++)
1619 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1620 pport_per_tc_congest_prio_stats_desc[i].format, prio);
1626 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(per_port_buff_congest)
1628 struct mlx5e_pport_stats *pport = &priv->stats.pport;
1629 struct mlx5_core_dev *mdev = priv->mdev;
1632 if (!MLX5_CAP_GEN(mdev, sbcam_reg))
1635 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1636 for (i = 0; i < NUM_PPORT_PER_TC_PRIO_COUNTERS; i++)
1638 MLX5E_READ_CTR64_BE(&pport->per_tc_prio_counters[prio],
1639 pport_per_tc_prio_stats_desc, i);
1640 for (i = 0; i < NUM_PPORT_PER_TC_CONGEST_PRIO_COUNTERS ; i++)
1642 MLX5E_READ_CTR64_BE(&pport->per_tc_congest_prio_counters[prio],
1643 pport_per_tc_congest_prio_stats_desc, i);
1649 static void mlx5e_grp_per_tc_prio_update_stats(struct mlx5e_priv *priv)
1651 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
1652 struct mlx5_core_dev *mdev = priv->mdev;
1653 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
1654 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1658 if (!MLX5_CAP_GEN(mdev, sbcam_reg))
1661 MLX5_SET(ppcnt_reg, in, pnat, 2);
1662 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP);
1663 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1664 out = pstats->per_tc_prio_counters[prio];
1665 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
1666 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1670 static int mlx5e_grp_per_tc_congest_prio_get_num_stats(struct mlx5e_priv *priv)
1672 struct mlx5_core_dev *mdev = priv->mdev;
1674 if (!MLX5_CAP_GEN(mdev, sbcam_reg))
1677 return NUM_PPORT_PER_TC_CONGEST_PRIO_COUNTERS * NUM_PPORT_PRIO;
1680 static void mlx5e_grp_per_tc_congest_prio_update_stats(struct mlx5e_priv *priv)
1682 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
1683 struct mlx5_core_dev *mdev = priv->mdev;
1684 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {};
1685 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1689 if (!MLX5_CAP_GEN(mdev, sbcam_reg))
1692 MLX5_SET(ppcnt_reg, in, pnat, 2);
1693 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP);
1694 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1695 out = pstats->per_tc_congest_prio_counters[prio];
1696 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
1697 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
1701 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(per_port_buff_congest)
1703 return mlx5e_grp_per_tc_prio_get_num_stats(priv) +
1704 mlx5e_grp_per_tc_congest_prio_get_num_stats(priv);
1707 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(per_port_buff_congest)
1709 mlx5e_grp_per_tc_prio_update_stats(priv);
1710 mlx5e_grp_per_tc_congest_prio_update_stats(priv);
1713 #define PPORT_PER_PRIO_OFF(c) \
1714 MLX5_BYTE_OFF(ppcnt_reg, \
1715 counter_set.eth_per_prio_grp_data_layout.c##_high)
1716 static const struct counter_desc pport_per_prio_traffic_stats_desc[] = {
1717 { "rx_prio%d_bytes", PPORT_PER_PRIO_OFF(rx_octets) },
1718 { "rx_prio%d_packets", PPORT_PER_PRIO_OFF(rx_frames) },
1719 { "rx_prio%d_discards", PPORT_PER_PRIO_OFF(rx_discards) },
1720 { "tx_prio%d_bytes", PPORT_PER_PRIO_OFF(tx_octets) },
1721 { "tx_prio%d_packets", PPORT_PER_PRIO_OFF(tx_frames) },
1724 #define NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS ARRAY_SIZE(pport_per_prio_traffic_stats_desc)
1726 static int mlx5e_grp_per_prio_traffic_get_num_stats(void)
1728 return NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS * NUM_PPORT_PRIO;
1731 static int mlx5e_grp_per_prio_traffic_fill_strings(struct mlx5e_priv *priv,
1737 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1738 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
1739 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1740 pport_per_prio_traffic_stats_desc[i].format, prio);
1746 static int mlx5e_grp_per_prio_traffic_fill_stats(struct mlx5e_priv *priv,
1752 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1753 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
1755 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
1756 pport_per_prio_traffic_stats_desc, i);
1762 static const struct counter_desc pport_per_prio_pfc_stats_desc[] = {
1763 /* %s is "global" or "prio{i}" */
1764 { "rx_%s_pause", PPORT_PER_PRIO_OFF(rx_pause) },
1765 { "rx_%s_pause_duration", PPORT_PER_PRIO_OFF(rx_pause_duration) },
1766 { "tx_%s_pause", PPORT_PER_PRIO_OFF(tx_pause) },
1767 { "tx_%s_pause_duration", PPORT_PER_PRIO_OFF(tx_pause_duration) },
1768 { "rx_%s_pause_transition", PPORT_PER_PRIO_OFF(rx_pause_transition) },
1771 static const struct counter_desc pport_pfc_stall_stats_desc[] = {
1772 { "tx_pause_storm_warning_events", PPORT_PER_PRIO_OFF(device_stall_minor_watermark_cnt) },
1773 { "tx_pause_storm_error_events", PPORT_PER_PRIO_OFF(device_stall_critical_watermark_cnt) },
1776 #define NUM_PPORT_PER_PRIO_PFC_COUNTERS ARRAY_SIZE(pport_per_prio_pfc_stats_desc)
1777 #define NUM_PPORT_PFC_STALL_COUNTERS(priv) (ARRAY_SIZE(pport_pfc_stall_stats_desc) * \
1778 MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) * \
1779 MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1781 static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
1783 struct mlx5_core_dev *mdev = priv->mdev;
1788 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1791 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
1793 return err ? 0 : pfc_en_tx | pfc_en_rx;
1796 static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
1798 struct mlx5_core_dev *mdev = priv->mdev;
1803 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1806 err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
1808 return err ? false : rx_pause | tx_pause;
1811 static int mlx5e_grp_per_prio_pfc_get_num_stats(struct mlx5e_priv *priv)
1813 return (mlx5e_query_global_pause_combined(priv) +
1814 hweight8(mlx5e_query_pfc_combined(priv))) *
1815 NUM_PPORT_PER_PRIO_PFC_COUNTERS +
1816 NUM_PPORT_PFC_STALL_COUNTERS(priv);
1819 static int mlx5e_grp_per_prio_pfc_fill_strings(struct mlx5e_priv *priv,
1823 unsigned long pfc_combined;
1826 pfc_combined = mlx5e_query_pfc_combined(priv);
1827 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
1828 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
1829 char pfc_string[ETH_GSTRING_LEN];
1831 snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
1832 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1833 pport_per_prio_pfc_stats_desc[i].format, pfc_string);
1837 if (mlx5e_query_global_pause_combined(priv)) {
1838 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
1839 sprintf(data + (idx++) * ETH_GSTRING_LEN,
1840 pport_per_prio_pfc_stats_desc[i].format, "global");
1844 for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)
1845 strcpy(data + (idx++) * ETH_GSTRING_LEN,
1846 pport_pfc_stall_stats_desc[i].format);
1851 static int mlx5e_grp_per_prio_pfc_fill_stats(struct mlx5e_priv *priv,
1855 unsigned long pfc_combined;
1858 pfc_combined = mlx5e_query_pfc_combined(priv);
1859 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
1860 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
1862 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
1863 pport_per_prio_pfc_stats_desc, i);
1867 if (mlx5e_query_global_pause_combined(priv)) {
1868 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
1870 MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
1871 pport_per_prio_pfc_stats_desc, i);
1875 for (i = 0; i < NUM_PPORT_PFC_STALL_COUNTERS(priv); i++)
1876 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
1877 pport_pfc_stall_stats_desc, i);
1882 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(per_prio)
1884 return mlx5e_grp_per_prio_traffic_get_num_stats() +
1885 mlx5e_grp_per_prio_pfc_get_num_stats(priv);
1888 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(per_prio)
1890 idx = mlx5e_grp_per_prio_traffic_fill_strings(priv, data, idx);
1891 idx = mlx5e_grp_per_prio_pfc_fill_strings(priv, data, idx);
1895 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(per_prio)
1897 idx = mlx5e_grp_per_prio_traffic_fill_stats(priv, data, idx);
1898 idx = mlx5e_grp_per_prio_pfc_fill_stats(priv, data, idx);
1902 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(per_prio)
1904 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
1905 struct mlx5_core_dev *mdev = priv->mdev;
1906 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
1907 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
1911 if (!MLX5_BASIC_PPCNT_SUPPORTED(mdev))
1914 MLX5_SET(ppcnt_reg, in, local_port, 1);
1915 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
1916 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
1917 out = pstats->per_prio_counters[prio];
1918 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
1919 mlx5_core_access_reg(mdev, in, sz, out, sz,
1920 MLX5_REG_PPCNT, 0, 0);
1924 static const struct counter_desc mlx5e_pme_status_desc[] = {
1925 { "module_unplug", sizeof(u64) * MLX5_MODULE_STATUS_UNPLUGGED },
1928 static const struct counter_desc mlx5e_pme_error_desc[] = {
1929 { "module_bus_stuck", sizeof(u64) * MLX5_MODULE_EVENT_ERROR_BUS_STUCK },
1930 { "module_high_temp", sizeof(u64) * MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE },
1931 { "module_bad_shorted", sizeof(u64) * MLX5_MODULE_EVENT_ERROR_BAD_CABLE },
1934 #define NUM_PME_STATUS_STATS ARRAY_SIZE(mlx5e_pme_status_desc)
1935 #define NUM_PME_ERR_STATS ARRAY_SIZE(mlx5e_pme_error_desc)
1937 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(pme)
1939 return NUM_PME_STATUS_STATS + NUM_PME_ERR_STATS;
1942 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(pme)
1946 for (i = 0; i < NUM_PME_STATUS_STATS; i++)
1947 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format);
1949 for (i = 0; i < NUM_PME_ERR_STATS; i++)
1950 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format);
1955 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(pme)
1957 struct mlx5_pme_stats pme_stats;
1960 mlx5_get_pme_stats(priv->mdev, &pme_stats);
1962 for (i = 0; i < NUM_PME_STATUS_STATS; i++)
1963 data[idx++] = MLX5E_READ_CTR64_CPU(pme_stats.status_counters,
1964 mlx5e_pme_status_desc, i);
1966 for (i = 0; i < NUM_PME_ERR_STATS; i++)
1967 data[idx++] = MLX5E_READ_CTR64_CPU(pme_stats.error_counters,
1968 mlx5e_pme_error_desc, i);
1973 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(pme) { return; }
1975 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(tls)
1977 return mlx5e_ktls_get_count(priv);
1980 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(tls)
1982 return idx + mlx5e_ktls_get_strings(priv, data + idx * ETH_GSTRING_LEN);
1985 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(tls)
1987 return idx + mlx5e_ktls_get_stats(priv, data + idx);
1990 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(tls) { return; }
1992 static const struct counter_desc rq_stats_desc[] = {
1993 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, packets) },
1994 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, bytes) },
1995 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete) },
1996 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete_tail) },
1997 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete_tail_slow) },
1998 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary) },
1999 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) },
2000 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_none) },
2001 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_drop) },
2002 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_redirect) },
2003 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_packets) },
2004 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_bytes) },
2005 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, gro_packets) },
2006 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, gro_bytes) },
2007 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, gro_skbs) },
2008 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, gro_match_packets) },
2009 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, gro_large_hds) },
2010 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, ecn_mark) },
2011 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, removed_vlan_packets) },
2012 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, wqe_err) },
2013 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler_cqes) },
2014 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler_strides) },
2015 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, oversize_pkts_sw_drop) },
2016 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, buff_alloc_err) },
2017 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_blks) },
2018 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) },
2019 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, congst_umr) },
2020 #ifdef CONFIG_MLX5_EN_ARFS
2021 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, arfs_add) },
2022 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, arfs_request_in) },
2023 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, arfs_request_out) },
2024 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, arfs_expired) },
2025 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, arfs_err) },
2027 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, recover) },
2028 #ifdef CONFIG_PAGE_POOL_STATS
2029 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_alloc_fast) },
2030 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_alloc_slow) },
2031 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_alloc_slow_high_order) },
2032 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_alloc_empty) },
2033 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_alloc_refill) },
2034 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_alloc_waive) },
2035 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_recycle_cached) },
2036 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_recycle_cache_full) },
2037 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_recycle_ring) },
2038 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_recycle_ring_full) },
2039 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, pp_recycle_released_ref) },
2041 #ifdef CONFIG_MLX5_EN_TLS
2042 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_decrypted_packets) },
2043 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_decrypted_bytes) },
2044 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_resync_req_pkt) },
2045 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_resync_req_start) },
2046 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_resync_req_end) },
2047 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_resync_req_skip) },
2048 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_resync_res_ok) },
2049 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_resync_res_retry) },
2050 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_resync_res_skip) },
2051 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, tls_err) },
2055 static const struct counter_desc sq_stats_desc[] = {
2056 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, packets) },
2057 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, bytes) },
2058 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_packets) },
2059 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_bytes) },
2060 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_packets) },
2061 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_bytes) },
2062 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial) },
2063 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial_inner) },
2064 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, added_vlan_packets) },
2065 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, nop) },
2066 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, mpwqe_blks) },
2067 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, mpwqe_pkts) },
2068 #ifdef CONFIG_MLX5_EN_TLS
2069 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_encrypted_packets) },
2070 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_encrypted_bytes) },
2071 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_ooo) },
2072 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_dump_packets) },
2073 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_dump_bytes) },
2074 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_resync_bytes) },
2075 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_skip_no_sync_data) },
2076 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_drop_no_sync_data) },
2077 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tls_drop_bypass_req) },
2079 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_none) },
2080 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, stopped) },
2081 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, dropped) },
2082 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, xmit_more) },
2083 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, recover) },
2084 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, cqes) },
2085 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, wake) },
2086 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, cqe_err) },
2089 static const struct counter_desc rq_xdpsq_stats_desc[] = {
2090 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, xmit) },
2091 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, mpwqe) },
2092 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, inlnw) },
2093 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, nops) },
2094 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, full) },
2095 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, err) },
2096 { MLX5E_DECLARE_RQ_XDPSQ_STAT(struct mlx5e_xdpsq_stats, cqes) },
2099 static const struct counter_desc xdpsq_stats_desc[] = {
2100 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, xmit) },
2101 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, mpwqe) },
2102 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, inlnw) },
2103 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, nops) },
2104 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, full) },
2105 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, err) },
2106 { MLX5E_DECLARE_XDPSQ_STAT(struct mlx5e_xdpsq_stats, cqes) },
2109 static const struct counter_desc xskrq_stats_desc[] = {
2110 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, packets) },
2111 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, bytes) },
2112 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, csum_complete) },
2113 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, csum_unnecessary) },
2114 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) },
2115 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, csum_none) },
2116 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, ecn_mark) },
2117 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, removed_vlan_packets) },
2118 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, xdp_drop) },
2119 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, xdp_redirect) },
2120 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, wqe_err) },
2121 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, mpwqe_filler_cqes) },
2122 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, mpwqe_filler_strides) },
2123 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, oversize_pkts_sw_drop) },
2124 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, buff_alloc_err) },
2125 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, cqe_compress_blks) },
2126 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) },
2127 { MLX5E_DECLARE_XSKRQ_STAT(struct mlx5e_rq_stats, congst_umr) },
2130 static const struct counter_desc xsksq_stats_desc[] = {
2131 { MLX5E_DECLARE_XSKSQ_STAT(struct mlx5e_xdpsq_stats, xmit) },
2132 { MLX5E_DECLARE_XSKSQ_STAT(struct mlx5e_xdpsq_stats, mpwqe) },
2133 { MLX5E_DECLARE_XSKSQ_STAT(struct mlx5e_xdpsq_stats, inlnw) },
2134 { MLX5E_DECLARE_XSKSQ_STAT(struct mlx5e_xdpsq_stats, full) },
2135 { MLX5E_DECLARE_XSKSQ_STAT(struct mlx5e_xdpsq_stats, err) },
2136 { MLX5E_DECLARE_XSKSQ_STAT(struct mlx5e_xdpsq_stats, cqes) },
2139 static const struct counter_desc ch_stats_desc[] = {
2140 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, events) },
2141 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, poll) },
2142 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, arm) },
2143 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, aff_change) },
2144 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, force_irq) },
2145 { MLX5E_DECLARE_CH_STAT(struct mlx5e_ch_stats, eq_rearm) },
2148 static const struct counter_desc ptp_sq_stats_desc[] = {
2149 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, packets) },
2150 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, bytes) },
2151 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, csum_partial) },
2152 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, csum_partial_inner) },
2153 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, added_vlan_packets) },
2154 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, nop) },
2155 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, csum_none) },
2156 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, stopped) },
2157 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, dropped) },
2158 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, xmit_more) },
2159 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, recover) },
2160 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, cqes) },
2161 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, wake) },
2162 { MLX5E_DECLARE_PTP_TX_STAT(struct mlx5e_sq_stats, cqe_err) },
2165 static const struct counter_desc ptp_ch_stats_desc[] = {
2166 { MLX5E_DECLARE_PTP_CH_STAT(struct mlx5e_ch_stats, events) },
2167 { MLX5E_DECLARE_PTP_CH_STAT(struct mlx5e_ch_stats, poll) },
2168 { MLX5E_DECLARE_PTP_CH_STAT(struct mlx5e_ch_stats, arm) },
2169 { MLX5E_DECLARE_PTP_CH_STAT(struct mlx5e_ch_stats, eq_rearm) },
2172 static const struct counter_desc ptp_cq_stats_desc[] = {
2173 { MLX5E_DECLARE_PTP_CQ_STAT(struct mlx5e_ptp_cq_stats, cqe) },
2174 { MLX5E_DECLARE_PTP_CQ_STAT(struct mlx5e_ptp_cq_stats, err_cqe) },
2175 { MLX5E_DECLARE_PTP_CQ_STAT(struct mlx5e_ptp_cq_stats, abort) },
2176 { MLX5E_DECLARE_PTP_CQ_STAT(struct mlx5e_ptp_cq_stats, abort_abs_diff_ns) },
2177 { MLX5E_DECLARE_PTP_CQ_STAT(struct mlx5e_ptp_cq_stats, late_cqe) },
2180 static const struct counter_desc ptp_rq_stats_desc[] = {
2181 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, packets) },
2182 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, bytes) },
2183 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, csum_complete) },
2184 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, csum_complete_tail) },
2185 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, csum_complete_tail_slow) },
2186 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, csum_unnecessary) },
2187 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) },
2188 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, csum_none) },
2189 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, xdp_drop) },
2190 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, xdp_redirect) },
2191 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, lro_packets) },
2192 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, lro_bytes) },
2193 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, ecn_mark) },
2194 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, removed_vlan_packets) },
2195 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, wqe_err) },
2196 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, mpwqe_filler_cqes) },
2197 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, mpwqe_filler_strides) },
2198 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, oversize_pkts_sw_drop) },
2199 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, buff_alloc_err) },
2200 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, cqe_compress_blks) },
2201 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) },
2202 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, congst_umr) },
2203 { MLX5E_DECLARE_PTP_RQ_STAT(struct mlx5e_rq_stats, recover) },
2206 static const struct counter_desc qos_sq_stats_desc[] = {
2207 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, packets) },
2208 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, bytes) },
2209 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tso_packets) },
2210 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tso_bytes) },
2211 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tso_inner_packets) },
2212 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tso_inner_bytes) },
2213 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, csum_partial) },
2214 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, csum_partial_inner) },
2215 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, added_vlan_packets) },
2216 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, nop) },
2217 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, mpwqe_blks) },
2218 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, mpwqe_pkts) },
2219 #ifdef CONFIG_MLX5_EN_TLS
2220 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tls_encrypted_packets) },
2221 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tls_encrypted_bytes) },
2222 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tls_ooo) },
2223 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tls_dump_packets) },
2224 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tls_dump_bytes) },
2225 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tls_resync_bytes) },
2226 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tls_skip_no_sync_data) },
2227 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tls_drop_no_sync_data) },
2228 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, tls_drop_bypass_req) },
2230 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, csum_none) },
2231 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, stopped) },
2232 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, dropped) },
2233 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, xmit_more) },
2234 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, recover) },
2235 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, cqes) },
2236 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, wake) },
2237 { MLX5E_DECLARE_QOS_TX_STAT(struct mlx5e_sq_stats, cqe_err) },
2240 #define NUM_RQ_STATS ARRAY_SIZE(rq_stats_desc)
2241 #define NUM_SQ_STATS ARRAY_SIZE(sq_stats_desc)
2242 #define NUM_XDPSQ_STATS ARRAY_SIZE(xdpsq_stats_desc)
2243 #define NUM_RQ_XDPSQ_STATS ARRAY_SIZE(rq_xdpsq_stats_desc)
2244 #define NUM_XSKRQ_STATS ARRAY_SIZE(xskrq_stats_desc)
2245 #define NUM_XSKSQ_STATS ARRAY_SIZE(xsksq_stats_desc)
2246 #define NUM_CH_STATS ARRAY_SIZE(ch_stats_desc)
2247 #define NUM_PTP_SQ_STATS ARRAY_SIZE(ptp_sq_stats_desc)
2248 #define NUM_PTP_CH_STATS ARRAY_SIZE(ptp_ch_stats_desc)
2249 #define NUM_PTP_CQ_STATS ARRAY_SIZE(ptp_cq_stats_desc)
2250 #define NUM_PTP_RQ_STATS ARRAY_SIZE(ptp_rq_stats_desc)
2251 #define NUM_QOS_SQ_STATS ARRAY_SIZE(qos_sq_stats_desc)
2253 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(qos)
2255 /* Pairs with smp_store_release in mlx5e_open_qos_sq. */
2256 return NUM_QOS_SQ_STATS * smp_load_acquire(&priv->htb_max_qos_sqs);
2259 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(qos)
2261 /* Pairs with smp_store_release in mlx5e_open_qos_sq. */
2262 u16 max_qos_sqs = smp_load_acquire(&priv->htb_max_qos_sqs);
2265 for (qid = 0; qid < max_qos_sqs; qid++)
2266 for (i = 0; i < NUM_QOS_SQ_STATS; i++)
2267 sprintf(data + (idx++) * ETH_GSTRING_LEN,
2268 qos_sq_stats_desc[i].format, qid);
2273 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(qos)
2275 struct mlx5e_sq_stats **stats;
2279 /* Pairs with smp_store_release in mlx5e_open_qos_sq. */
2280 max_qos_sqs = smp_load_acquire(&priv->htb_max_qos_sqs);
2281 stats = READ_ONCE(priv->htb_qos_sq_stats);
2283 for (qid = 0; qid < max_qos_sqs; qid++) {
2284 struct mlx5e_sq_stats *s = READ_ONCE(stats[qid]);
2286 for (i = 0; i < NUM_QOS_SQ_STATS; i++)
2287 data[idx++] = MLX5E_READ_CTR64_CPU(s, qos_sq_stats_desc, i);
2293 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(qos) { return; }
2295 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(ptp)
2297 int num = NUM_PTP_CH_STATS;
2299 if (!priv->tx_ptp_opened && !priv->rx_ptp_opened)
2302 if (priv->tx_ptp_opened)
2303 num += (NUM_PTP_SQ_STATS + NUM_PTP_CQ_STATS) * priv->max_opened_tc;
2304 if (priv->rx_ptp_opened)
2305 num += NUM_PTP_RQ_STATS;
2310 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(ptp)
2314 if (!priv->tx_ptp_opened && !priv->rx_ptp_opened)
2317 for (i = 0; i < NUM_PTP_CH_STATS; i++)
2318 sprintf(data + (idx++) * ETH_GSTRING_LEN,
2319 "%s", ptp_ch_stats_desc[i].format);
2321 if (priv->tx_ptp_opened) {
2322 for (tc = 0; tc < priv->max_opened_tc; tc++)
2323 for (i = 0; i < NUM_PTP_SQ_STATS; i++)
2324 sprintf(data + (idx++) * ETH_GSTRING_LEN,
2325 ptp_sq_stats_desc[i].format, tc);
2327 for (tc = 0; tc < priv->max_opened_tc; tc++)
2328 for (i = 0; i < NUM_PTP_CQ_STATS; i++)
2329 sprintf(data + (idx++) * ETH_GSTRING_LEN,
2330 ptp_cq_stats_desc[i].format, tc);
2332 if (priv->rx_ptp_opened) {
2333 for (i = 0; i < NUM_PTP_RQ_STATS; i++)
2334 sprintf(data + (idx++) * ETH_GSTRING_LEN,
2335 ptp_rq_stats_desc[i].format, MLX5E_PTP_CHANNEL_IX);
2340 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(ptp)
2344 if (!priv->tx_ptp_opened && !priv->rx_ptp_opened)
2347 for (i = 0; i < NUM_PTP_CH_STATS; i++)
2349 MLX5E_READ_CTR64_CPU(&priv->ptp_stats.ch,
2350 ptp_ch_stats_desc, i);
2352 if (priv->tx_ptp_opened) {
2353 for (tc = 0; tc < priv->max_opened_tc; tc++)
2354 for (i = 0; i < NUM_PTP_SQ_STATS; i++)
2356 MLX5E_READ_CTR64_CPU(&priv->ptp_stats.sq[tc],
2357 ptp_sq_stats_desc, i);
2359 for (tc = 0; tc < priv->max_opened_tc; tc++)
2360 for (i = 0; i < NUM_PTP_CQ_STATS; i++)
2362 MLX5E_READ_CTR64_CPU(&priv->ptp_stats.cq[tc],
2363 ptp_cq_stats_desc, i);
2365 if (priv->rx_ptp_opened) {
2366 for (i = 0; i < NUM_PTP_RQ_STATS; i++)
2368 MLX5E_READ_CTR64_CPU(&priv->ptp_stats.rq,
2369 ptp_rq_stats_desc, i);
2374 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(ptp) { return; }
2376 static MLX5E_DECLARE_STATS_GRP_OP_NUM_STATS(channels)
2378 int max_nch = priv->stats_nch;
2380 return (NUM_RQ_STATS * max_nch) +
2381 (NUM_CH_STATS * max_nch) +
2382 (NUM_SQ_STATS * max_nch * priv->max_opened_tc) +
2383 (NUM_RQ_XDPSQ_STATS * max_nch) +
2384 (NUM_XDPSQ_STATS * max_nch) +
2385 (NUM_XSKRQ_STATS * max_nch * priv->xsk.ever_used) +
2386 (NUM_XSKSQ_STATS * max_nch * priv->xsk.ever_used);
2389 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STRS(channels)
2391 bool is_xsk = priv->xsk.ever_used;
2392 int max_nch = priv->stats_nch;
2395 for (i = 0; i < max_nch; i++)
2396 for (j = 0; j < NUM_CH_STATS; j++)
2397 sprintf(data + (idx++) * ETH_GSTRING_LEN,
2398 ch_stats_desc[j].format, i);
2400 for (i = 0; i < max_nch; i++) {
2401 for (j = 0; j < NUM_RQ_STATS; j++)
2402 sprintf(data + (idx++) * ETH_GSTRING_LEN,
2403 rq_stats_desc[j].format, i);
2404 for (j = 0; j < NUM_XSKRQ_STATS * is_xsk; j++)
2405 sprintf(data + (idx++) * ETH_GSTRING_LEN,
2406 xskrq_stats_desc[j].format, i);
2407 for (j = 0; j < NUM_RQ_XDPSQ_STATS; j++)
2408 sprintf(data + (idx++) * ETH_GSTRING_LEN,
2409 rq_xdpsq_stats_desc[j].format, i);
2412 for (tc = 0; tc < priv->max_opened_tc; tc++)
2413 for (i = 0; i < max_nch; i++)
2414 for (j = 0; j < NUM_SQ_STATS; j++)
2415 sprintf(data + (idx++) * ETH_GSTRING_LEN,
2416 sq_stats_desc[j].format,
2419 for (i = 0; i < max_nch; i++) {
2420 for (j = 0; j < NUM_XSKSQ_STATS * is_xsk; j++)
2421 sprintf(data + (idx++) * ETH_GSTRING_LEN,
2422 xsksq_stats_desc[j].format, i);
2423 for (j = 0; j < NUM_XDPSQ_STATS; j++)
2424 sprintf(data + (idx++) * ETH_GSTRING_LEN,
2425 xdpsq_stats_desc[j].format, i);
2431 static MLX5E_DECLARE_STATS_GRP_OP_FILL_STATS(channels)
2433 bool is_xsk = priv->xsk.ever_used;
2434 int max_nch = priv->stats_nch;
2437 for (i = 0; i < max_nch; i++)
2438 for (j = 0; j < NUM_CH_STATS; j++)
2440 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i]->ch,
2443 for (i = 0; i < max_nch; i++) {
2444 for (j = 0; j < NUM_RQ_STATS; j++)
2446 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i]->rq,
2448 for (j = 0; j < NUM_XSKRQ_STATS * is_xsk; j++)
2450 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i]->xskrq,
2451 xskrq_stats_desc, j);
2452 for (j = 0; j < NUM_RQ_XDPSQ_STATS; j++)
2454 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i]->rq_xdpsq,
2455 rq_xdpsq_stats_desc, j);
2458 for (tc = 0; tc < priv->max_opened_tc; tc++)
2459 for (i = 0; i < max_nch; i++)
2460 for (j = 0; j < NUM_SQ_STATS; j++)
2462 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i]->sq[tc],
2465 for (i = 0; i < max_nch; i++) {
2466 for (j = 0; j < NUM_XSKSQ_STATS * is_xsk; j++)
2468 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i]->xsksq,
2469 xsksq_stats_desc, j);
2470 for (j = 0; j < NUM_XDPSQ_STATS; j++)
2472 MLX5E_READ_CTR64_CPU(&priv->channel_stats[i]->xdpsq,
2473 xdpsq_stats_desc, j);
2479 static MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS(channels) { return; }
2481 MLX5E_DEFINE_STATS_GRP(sw, 0);
2482 MLX5E_DEFINE_STATS_GRP(qcnt, MLX5E_NDO_UPDATE_STATS);
2483 MLX5E_DEFINE_STATS_GRP(vnic_env, 0);
2484 MLX5E_DEFINE_STATS_GRP(vport, MLX5E_NDO_UPDATE_STATS);
2485 MLX5E_DEFINE_STATS_GRP(802_3, MLX5E_NDO_UPDATE_STATS);
2486 MLX5E_DEFINE_STATS_GRP(2863, 0);
2487 MLX5E_DEFINE_STATS_GRP(2819, 0);
2488 MLX5E_DEFINE_STATS_GRP(phy, 0);
2489 MLX5E_DEFINE_STATS_GRP(pcie, 0);
2490 MLX5E_DEFINE_STATS_GRP(per_prio, 0);
2491 MLX5E_DEFINE_STATS_GRP(pme, 0);
2492 MLX5E_DEFINE_STATS_GRP(channels, 0);
2493 MLX5E_DEFINE_STATS_GRP(per_port_buff_congest, 0);
2494 MLX5E_DEFINE_STATS_GRP(eth_ext, 0);
2495 static MLX5E_DEFINE_STATS_GRP(tls, 0);
2496 MLX5E_DEFINE_STATS_GRP(ptp, 0);
2497 static MLX5E_DEFINE_STATS_GRP(qos, 0);
2499 /* The stats groups order is opposite to the update_stats() order calls */
2500 mlx5e_stats_grp_t mlx5e_nic_stats_grps[] = {
2501 &MLX5E_STATS_GRP(sw),
2502 &MLX5E_STATS_GRP(qcnt),
2503 &MLX5E_STATS_GRP(vnic_env),
2504 &MLX5E_STATS_GRP(vport),
2505 &MLX5E_STATS_GRP(802_3),
2506 &MLX5E_STATS_GRP(2863),
2507 &MLX5E_STATS_GRP(2819),
2508 &MLX5E_STATS_GRP(phy),
2509 &MLX5E_STATS_GRP(eth_ext),
2510 &MLX5E_STATS_GRP(pcie),
2511 &MLX5E_STATS_GRP(per_prio),
2512 &MLX5E_STATS_GRP(pme),
2513 #ifdef CONFIG_MLX5_EN_IPSEC
2514 &MLX5E_STATS_GRP(ipsec_hw),
2515 &MLX5E_STATS_GRP(ipsec_sw),
2517 &MLX5E_STATS_GRP(tls),
2518 &MLX5E_STATS_GRP(channels),
2519 &MLX5E_STATS_GRP(per_port_buff_congest),
2520 &MLX5E_STATS_GRP(ptp),
2521 &MLX5E_STATS_GRP(qos),
2522 #ifdef CONFIG_MLX5_MACSEC
2523 &MLX5E_STATS_GRP(macsec_hw),
2527 unsigned int mlx5e_nic_stats_grps_num(struct mlx5e_priv *priv)
2529 return ARRAY_SIZE(mlx5e_nic_stats_grps);