drivers/net/ethernet/mellanox/mlx5/core/en_rx.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/ip.h>
  34 #include <linux/ipv6.h>
  35 #include <linux/tcp.h>
  36 #include <net/ip6_checksum.h>
  37 #include <net/page_pool.h>
  38 #include <net/inet_ecn.h>
  39 #include "en.h"
  40 #include "en/txrx.h"
  41 #include "en_tc.h"
  42 #include "eswitch.h"
  43 #include "en_rep.h"
  44 #include "en/rep/tc.h"
  45 #include "ipoib/ipoib.h"
  46 #include "accel/ipsec.h"
  47 #include "fpga/ipsec.h"
  48 #include "en_accel/ipsec_rxtx.h"
  49 #include "en_accel/tls_rxtx.h"
  50 #include "en/xdp.h"
  51 #include "en/xsk/rx.h"
  52 #include "en/health.h"
  53 #include "en/params.h"
  54 #include "devlink.h"
  55
  56 static struct sk_buff *
  57 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
  58                                 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
  59 static struct sk_buff *
  60 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
  61                                    u16 cqe_bcnt, u32 head_offset, u32 page_idx);
  62 static void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
  63 static void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
  64
  65 const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic = {
  66         .handle_rx_cqe       = mlx5e_handle_rx_cqe,
  67         .handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
  68 };
  69
  70 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
  71 {
  72         return config->rx_filter == HWTSTAMP_FILTER_ALL;
  73 }
  74
  75 static inline void mlx5e_read_cqe_slot(struct mlx5_cqwq *wq,
  76                                        u32 cqcc, void *data)
  77 {
  78         u32 ci = mlx5_cqwq_ctr2ix(wq, cqcc);
  79
  80         memcpy(data, mlx5_cqwq_get_wqe(wq, ci), sizeof(struct mlx5_cqe64));
  81 }
  82
  83 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
  84                                          struct mlx5_cqwq *wq,
  85                                          u32 cqcc)
  86 {
  87         struct mlx5e_cq_decomp *cqd = &rq->cqd;
  88         struct mlx5_cqe64 *title = &cqd->title;
  89
  90         mlx5e_read_cqe_slot(wq, cqcc, title);
  91         cqd->left        = be32_to_cpu(title->byte_cnt);
  92         cqd->wqe_counter = be16_to_cpu(title->wqe_counter);
  93         rq->stats->cqe_compress_blks++;
  94 }
  95
  96 static inline void mlx5e_read_mini_arr_slot(struct mlx5_cqwq *wq,
  97                                             struct mlx5e_cq_decomp *cqd,
  98                                             u32 cqcc)
  99 {
 100         mlx5e_read_cqe_slot(wq, cqcc, cqd->mini_arr);
 101         cqd->mini_arr_idx = 0;
 102 }
 103
 104 static inline void mlx5e_cqes_update_owner(struct mlx5_cqwq *wq, int n)
 105 {
 106         u32 cqcc   = wq->cc;
 107         u8  op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1;
 108         u32 ci     = mlx5_cqwq_ctr2ix(wq, cqcc);
 109         u32 wq_sz  = mlx5_cqwq_get_size(wq);
 110         u32 ci_top = min_t(u32, wq_sz, ci + n);
 111
 112         for (; ci < ci_top; ci++, n--) {
 113                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
 114
 115                 cqe->op_own = op_own;
 116         }
 117
 118         if (unlikely(ci == wq_sz)) {
 119                 op_own = !op_own;
 120                 for (ci = 0; ci < n; ci++) {
 121                         struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
 122
 123                         cqe->op_own = op_own;
 124                 }
 125         }
 126 }
 127
 128 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
 129                                         struct mlx5_cqwq *wq,
 130                                         u32 cqcc)
 131 {
 132         struct mlx5e_cq_decomp *cqd = &rq->cqd;
 133         struct mlx5_mini_cqe8 *mini_cqe = &cqd->mini_arr[cqd->mini_arr_idx];
 134         struct mlx5_cqe64 *title = &cqd->title;
 135
 136         title->byte_cnt     = mini_cqe->byte_cnt;
 137         title->check_sum    = mini_cqe->checksum;
 138         title->op_own      &= 0xf0;
 139         title->op_own      |= 0x01 & (cqcc >> wq->fbc.log_sz);
 140
 141         /* state bit set implies linked-list striding RQ wq type and
 142          * HW stride index capability supported
 143          */
 144         if (test_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state)) {
 145                 title->wqe_counter = mini_cqe->stridx;
 146                 return;
 147         }
 148
 149         /* HW stride index capability not supported */
 150         title->wqe_counter = cpu_to_be16(cqd->wqe_counter);
 151         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 152                 cqd->wqe_counter += mpwrq_get_cqe_consumed_strides(title);
 153         else
 154                 cqd->wqe_counter =
 155                         mlx5_wq_cyc_ctr2ix(&rq->wqe.wq, cqd->wqe_counter + 1);
 156 }
 157
 158 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
 159                                                 struct mlx5_cqwq *wq,
 160                                                 u32 cqcc)
 161 {
 162         struct mlx5e_cq_decomp *cqd = &rq->cqd;
 163
 164         mlx5e_decompress_cqe(rq, wq, cqcc);
 165         cqd->title.rss_hash_type   = 0;
 166         cqd->title.rss_hash_result = 0;
 167 }
 168
 169 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
 170                                              struct mlx5_cqwq *wq,
 171                                              int update_owner_only,
 172                                              int budget_rem)
 173 {
 174         struct mlx5e_cq_decomp *cqd = &rq->cqd;
 175         u32 cqcc = wq->cc + update_owner_only;
 176         u32 cqe_count;
 177         u32 i;
 178
 179         cqe_count = min_t(u32, cqd->left, budget_rem);
 180
 181         for (i = update_owner_only; i < cqe_count;
 182              i++, cqd->mini_arr_idx++, cqcc++) {
 183                 if (cqd->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
 184                         mlx5e_read_mini_arr_slot(wq, cqd, cqcc);
 185
 186                 mlx5e_decompress_cqe_no_hash(rq, wq, cqcc);
 187                 INDIRECT_CALL_2(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq,
 188                                 mlx5e_handle_rx_cqe, rq, &cqd->title);
 189         }
 190         mlx5e_cqes_update_owner(wq, cqcc - wq->cc);
 191         wq->cc = cqcc;
 192         cqd->left -= cqe_count;
 193         rq->stats->cqe_compress_pkts += cqe_count;
 194
 195         return cqe_count;
 196 }
 197
 198 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
 199                                               struct mlx5_cqwq *wq,
 200                                               int budget_rem)
 201 {
 202         struct mlx5e_cq_decomp *cqd = &rq->cqd;
 203         u32 cc = wq->cc;
 204
 205         mlx5e_read_title_slot(rq, wq, cc);
 206         mlx5e_read_mini_arr_slot(wq, cqd, cc + 1);
 207         mlx5e_decompress_cqe(rq, wq, cc);
 208         INDIRECT_CALL_2(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq,
 209                         mlx5e_handle_rx_cqe, rq, &cqd->title);
 210         cqd->mini_arr_idx++;
 211
 212         return mlx5e_decompress_cqes_cont(rq, wq, 1, budget_rem) - 1;
 213 }
 214
 215 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
 216                                       struct mlx5e_dma_info *dma_info)
 217 {
 218         struct mlx5e_page_cache *cache = &rq->page_cache;
 219         u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
 220         struct mlx5e_rq_stats *stats = rq->stats;
 221
 222         if (tail_next == cache->head) {
 223                 stats->cache_full++;
 224                 return false;
 225         }
 226
 227         if (!dev_page_is_reusable(dma_info->page)) {
 228                 stats->cache_waive++;
 229                 return false;
 230         }
 231
 232         cache->page_cache[cache->tail] = *dma_info;
 233         cache->tail = tail_next;
 234         return true;
 235 }
 236
 237 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
 238                                       struct mlx5e_dma_info *dma_info)
 239 {
 240         struct mlx5e_page_cache *cache = &rq->page_cache;
 241         struct mlx5e_rq_stats *stats = rq->stats;
 242
 243         if (unlikely(cache->head == cache->tail)) {
 244                 stats->cache_empty++;
 245                 return false;
 246         }
 247
 248         if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
 249                 stats->cache_busy++;
 250                 return false;
 251         }
 252
 253         *dma_info = cache->page_cache[cache->head];
 254         cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
 255         stats->cache_reuse++;
 256
 257         dma_sync_single_for_device(rq->pdev, dma_info->addr,
 258                                    PAGE_SIZE,
 259                                    DMA_FROM_DEVICE);
 260         return true;
 261 }
 262
 263 static inline int mlx5e_page_alloc_pool(struct mlx5e_rq *rq,
 264                                         struct mlx5e_dma_info *dma_info)
 265 {
 266         if (mlx5e_rx_cache_get(rq, dma_info))
 267                 return 0;
 268
 269         dma_info->page = page_pool_dev_alloc_pages(rq->page_pool);
 270         if (unlikely(!dma_info->page))
 271                 return -ENOMEM;
 272
 273         dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
 274                                       PAGE_SIZE, rq->buff.map_dir);
 275         if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
 276                 page_pool_recycle_direct(rq->page_pool, dma_info->page);
 277                 dma_info->page = NULL;
 278                 return -ENOMEM;
 279         }
 280
 281         return 0;
 282 }
 283
 284 static inline int mlx5e_page_alloc(struct mlx5e_rq *rq,
 285                                    struct mlx5e_dma_info *dma_info)
 286 {
 287         if (rq->xsk_pool)
 288                 return mlx5e_xsk_page_alloc_pool(rq, dma_info);
 289         else
 290                 return mlx5e_page_alloc_pool(rq, dma_info);
 291 }
 292
 293 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info)
 294 {
 295         dma_unmap_page(rq->pdev, dma_info->addr, PAGE_SIZE, rq->buff.map_dir);
 296 }
 297
 298 void mlx5e_page_release_dynamic(struct mlx5e_rq *rq,
 299                                 struct mlx5e_dma_info *dma_info,
 300                                 bool recycle)
 301 {
 302         if (likely(recycle)) {
 303                 if (mlx5e_rx_cache_put(rq, dma_info))
 304                         return;
 305
 306                 mlx5e_page_dma_unmap(rq, dma_info);
 307                 page_pool_recycle_direct(rq->page_pool, dma_info->page);
 308         } else {
 309                 mlx5e_page_dma_unmap(rq, dma_info);
 310                 page_pool_release_page(rq->page_pool, dma_info->page);
 311                 put_page(dma_info->page);
 312         }
 313 }
 314
 315 static inline void mlx5e_page_release(struct mlx5e_rq *rq,
 316                                       struct mlx5e_dma_info *dma_info,
 317                                       bool recycle)
 318 {
 319         if (rq->xsk_pool)
 320                 /* The `recycle` parameter is ignored, and the page is always
 321                  * put into the Reuse Ring, because there is no way to return
 322                  * the page to the userspace when the interface goes down.
 323                  */
 324                 xsk_buff_free(dma_info->xsk);
 325         else
 326                 mlx5e_page_release_dynamic(rq, dma_info, recycle);
 327 }
 328
 329 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq,
 330                                     struct mlx5e_wqe_frag_info *frag)
 331 {
 332         int err = 0;
 333
 334         if (!frag->offset)
 335                 /* On first frag (offset == 0), replenish page (dma_info actually).
 336                  * Other frags that point to the same dma_info (with a different
 337                  * offset) should just use the new one without replenishing again
 338                  * by themselves.
 339                  */
 340                 err = mlx5e_page_alloc(rq, frag->di);
 341
 342         return err;
 343 }
 344
 345 static inline void mlx5e_put_rx_frag(struct mlx5e_rq *rq,
 346                                      struct mlx5e_wqe_frag_info *frag,
 347                                      bool recycle)
 348 {
 349         if (frag->last_in_page)
 350                 mlx5e_page_release(rq, frag->di, recycle);
 351 }
 352
 353 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u16 ix)
 354 {
 355         return &rq->wqe.frags[ix << rq->wqe.info.log_num_frags];
 356 }
 357
 358 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe_cyc *wqe,
 359                               u16 ix)
 360 {
 361         struct mlx5e_wqe_frag_info *frag = get_frag(rq, ix);
 362         int err;
 363         int i;
 364
 365         for (i = 0; i < rq->wqe.info.num_frags; i++, frag++) {
 366                 err = mlx5e_get_rx_frag(rq, frag);
 367                 if (unlikely(err))
 368                         goto free_frags;
 369
 370                 wqe->data[i].addr = cpu_to_be64(frag->di->addr +
 371                                                 frag->offset + rq->buff.headroom);
 372         }
 373
 374         return 0;
 375
 376 free_frags:
 377         while (--i >= 0)
 378                 mlx5e_put_rx_frag(rq, --frag, true);
 379
 380         return err;
 381 }
 382
 383 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
 384                                      struct mlx5e_wqe_frag_info *wi,
 385                                      bool recycle)
 386 {
 387         int i;
 388
 389         for (i = 0; i < rq->wqe.info.num_frags; i++, wi++)
 390                 mlx5e_put_rx_frag(rq, wi, recycle);
 391 }
 392
 393 static void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
 394 {
 395         struct mlx5e_wqe_frag_info *wi = get_frag(rq, ix);
 396
 397         mlx5e_free_rx_wqe(rq, wi, false);
 398 }
 399
 400 static int mlx5e_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, u8 wqe_bulk)
 401 {
 402         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 403         int err;
 404         int i;
 405
 406         if (rq->xsk_pool) {
 407                 int pages_desired = wqe_bulk << rq->wqe.info.log_num_frags;
 408
 409                 /* Check in advance that we have enough frames, instead of
 410                  * allocating one-by-one, failing and moving frames to the
 411                  * Reuse Ring.
 412                  */
 413                 if (unlikely(!xsk_buff_can_alloc(rq->xsk_pool, pages_desired)))
 414                         return -ENOMEM;
 415         }
 416
 417         for (i = 0; i < wqe_bulk; i++) {
 418                 struct mlx5e_rx_wqe_cyc *wqe = mlx5_wq_cyc_get_wqe(wq, ix + i);
 419
 420                 err = mlx5e_alloc_rx_wqe(rq, wqe, ix + i);
 421                 if (unlikely(err))
 422                         goto free_wqes;
 423         }
 424
 425         return 0;
 426
 427 free_wqes:
 428         while (--i >= 0)
 429                 mlx5e_dealloc_rx_wqe(rq, ix + i);
 430
 431         return err;
 432 }
 433
 434 static inline void
 435 mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buff *skb,
 436                    struct mlx5e_dma_info *di, u32 frag_offset, u32 len,
 437                    unsigned int truesize)
 438 {
 439         dma_sync_single_for_cpu(rq->pdev,
 440                                 di->addr + frag_offset,
 441                                 len, DMA_FROM_DEVICE);
 442         page_ref_inc(di->page);
 443         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
 444                         di->page, frag_offset, len, truesize);
 445 }
 446
 447 static inline void
 448 mlx5e_copy_skb_header(struct device *pdev, struct sk_buff *skb,
 449                       struct mlx5e_dma_info *dma_info,
 450                       int offset_from, u32 headlen)
 451 {
 452         const void *from = page_address(dma_info->page) + offset_from;
 453         /* Aligning len to sizeof(long) optimizes memcpy performance */
 454         unsigned int len = ALIGN(headlen, sizeof(long));
 455
 456         dma_sync_single_for_cpu(pdev, dma_info->addr + offset_from, len,
 457                                 DMA_FROM_DEVICE);
 458         skb_copy_to_linear_data(skb, from, len);
 459 }
 460
 461 static void
 462 mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, bool recycle)
 463 {
 464         bool no_xdp_xmit;
 465         struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
 466         int i;
 467
 468         /* A common case for AF_XDP. */
 469         if (bitmap_full(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE))
 470                 return;
 471
 472         no_xdp_xmit = bitmap_empty(wi->xdp_xmit_bitmap,
 473                                    MLX5_MPWRQ_PAGES_PER_WQE);
 474
 475         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++)
 476                 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
 477                         mlx5e_page_release(rq, &dma_info[i], recycle);
 478 }
 479
 480 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq, u8 n)
 481 {
 482         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 483
 484         do {
 485                 u16 next_wqe_index = mlx5_wq_ll_get_wqe_next_ix(wq, wq->head);
 486
 487                 mlx5_wq_ll_push(wq, next_wqe_index);
 488         } while (--n);
 489
 490         /* ensure wqes are visible to device before updating doorbell record */
 491         dma_wmb();
 492
 493         mlx5_wq_ll_update_db_record(wq);
 494 }
 495
 496 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 497 {
 498         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 499         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
 500         struct mlx5e_icosq *sq = rq->icosq;
 501         struct mlx5_wq_cyc *wq = &sq->wq;
 502         struct mlx5e_umr_wqe *umr_wqe;
 503         u16 pi;
 504         int err;
 505         int i;
 506
 507         /* Check in advance that we have enough frames, instead of allocating
 508          * one-by-one, failing and moving frames to the Reuse Ring.
 509          */
 510         if (rq->xsk_pool &&
 511             unlikely(!xsk_buff_can_alloc(rq->xsk_pool, MLX5_MPWRQ_PAGES_PER_WQE))) {
 512                 err = -ENOMEM;
 513                 goto err;
 514         }
 515
 516         pi = mlx5e_icosq_get_next_pi(sq, MLX5E_UMR_WQEBBS);
 517         umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
 518         memcpy(umr_wqe, &rq->mpwqe.umr_wqe, offsetof(struct mlx5e_umr_wqe, inline_mtts));
 519
 520         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
 521                 err = mlx5e_page_alloc(rq, dma_info);
 522                 if (unlikely(err))
 523                         goto err_unmap;
 524                 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
 525         }
 526
 527         bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
 528         wi->consumed_strides = 0;
 529
 530         umr_wqe->ctrl.opmod_idx_opcode =
 531                 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
 532                             MLX5_OPCODE_UMR);
 533         umr_wqe->uctrl.xlt_offset =
 534                 cpu_to_be16(MLX5_ALIGNED_MTTS_OCTW(MLX5E_REQUIRED_MTTS(ix)));
 535
 536         sq->db.wqe_info[pi] = (struct mlx5e_icosq_wqe_info) {
 537                 .wqe_type   = MLX5E_ICOSQ_WQE_UMR_RX,
 538                 .num_wqebbs = MLX5E_UMR_WQEBBS,
 539                 .umr.rq     = rq,
 540         };
 541
 542         sq->pc += MLX5E_UMR_WQEBBS;
 543
 544         sq->doorbell_cseg = &umr_wqe->ctrl;
 545
 546         return 0;
 547
 548 err_unmap:
 549         while (--i >= 0) {
 550                 dma_info--;
 551                 mlx5e_page_release(rq, dma_info, true);
 552         }
 553
 554 err:
 555         rq->stats->buff_alloc_err++;
 556
 557         return err;
 558 }
 559
 560 static void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 561 {
 562         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 563         /* Don't recycle, this function is called on rq/netdev close */
 564         mlx5e_free_rx_mpwqe(rq, wi, false);
 565 }
 566
 567 INDIRECT_CALLABLE_SCOPE bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
 568 {
 569         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 570         u8 wqe_bulk;
 571         int err;
 572
 573         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
 574                 return false;
 575
 576         wqe_bulk = rq->wqe.info.wqe_bulk;
 577
 578         if (mlx5_wq_cyc_missing(wq) < wqe_bulk)
 579                 return false;
 580
 581         do {
 582                 u16 head = mlx5_wq_cyc_get_head(wq);
 583
 584                 err = mlx5e_alloc_rx_wqes(rq, head, wqe_bulk);
 585                 if (unlikely(err)) {
 586                         rq->stats->buff_alloc_err++;
 587                         break;
 588                 }
 589
 590                 mlx5_wq_cyc_push_n(wq, wqe_bulk);
 591         } while (mlx5_wq_cyc_missing(wq) >= wqe_bulk);
 592
 593         /* ensure wqes are visible to device before updating doorbell record */
 594         dma_wmb();
 595
 596         mlx5_wq_cyc_update_db_record(wq);
 597
 598         return !!err;
 599 }
 600
 601 void mlx5e_free_icosq_descs(struct mlx5e_icosq *sq)
 602 {
 603         u16 sqcc;
 604
 605         sqcc = sq->cc;
 606
 607         while (sqcc != sq->pc) {
 608                 struct mlx5e_icosq_wqe_info *wi;
 609                 u16 ci;
 610
 611                 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
 612                 wi = &sq->db.wqe_info[ci];
 613                 sqcc += wi->num_wqebbs;
 614 #ifdef CONFIG_MLX5_EN_TLS
 615                 switch (wi->wqe_type) {
 616                 case MLX5E_ICOSQ_WQE_SET_PSV_TLS:
 617                         mlx5e_ktls_handle_ctx_completion(wi);
 618                         break;
 619                 case MLX5E_ICOSQ_WQE_GET_PSV_TLS:
 620                         mlx5e_ktls_handle_get_psv_completion(wi, sq);
 621                         break;
 622                 }
 623 #endif
 624         }
 625         sq->cc = sqcc;
 626 }
 627
 628 int mlx5e_poll_ico_cq(struct mlx5e_cq *cq)
 629 {
 630         struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
 631         struct mlx5_cqe64 *cqe;
 632         u16 sqcc;
 633         int i;
 634
 635         if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
 636                 return 0;
 637
 638         cqe = mlx5_cqwq_get_cqe(&cq->wq);
 639         if (likely(!cqe))
 640                 return 0;
 641
 642         /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
 643          * otherwise a cq overrun may occur
 644          */
 645         sqcc = sq->cc;
 646
 647         i = 0;
 648         do {
 649                 u16 wqe_counter;
 650                 bool last_wqe;
 651
 652                 mlx5_cqwq_pop(&cq->wq);
 653
 654                 wqe_counter = be16_to_cpu(cqe->wqe_counter);
 655
 656                 do {
 657                         struct mlx5e_icosq_wqe_info *wi;
 658                         u16 ci;
 659
 660                         last_wqe = (sqcc == wqe_counter);
 661
 662                         ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
 663                         wi = &sq->db.wqe_info[ci];
 664                         sqcc += wi->num_wqebbs;
 665
 666                         if (last_wqe && unlikely(get_cqe_opcode(cqe) != MLX5_CQE_REQ)) {
 667                                 netdev_WARN_ONCE(cq->netdev,
 668                                                  "Bad OP in ICOSQ CQE: 0x%x\n",
 669                                                  get_cqe_opcode(cqe));
 670                                 mlx5e_dump_error_cqe(&sq->cq, sq->sqn,
 671                                                      (struct mlx5_err_cqe *)cqe);
 672                                 if (!test_and_set_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state))
 673                                         queue_work(cq->priv->wq, &sq->recover_work);
 674                                 break;
 675                         }
 676
 677                         switch (wi->wqe_type) {
 678                         case MLX5E_ICOSQ_WQE_UMR_RX:
 679                                 wi->umr.rq->mpwqe.umr_completed++;
 680                                 break;
 681                         case MLX5E_ICOSQ_WQE_NOP:
 682                                 break;
 683 #ifdef CONFIG_MLX5_EN_TLS
 684                         case MLX5E_ICOSQ_WQE_UMR_TLS:
 685                                 break;
 686                         case MLX5E_ICOSQ_WQE_SET_PSV_TLS:
 687                                 mlx5e_ktls_handle_ctx_completion(wi);
 688                                 break;
 689                         case MLX5E_ICOSQ_WQE_GET_PSV_TLS:
 690                                 mlx5e_ktls_handle_get_psv_completion(wi, sq);
 691                                 break;
 692 #endif
 693                         default:
 694                                 netdev_WARN_ONCE(cq->netdev,
 695                                                  "Bad WQE type in ICOSQ WQE info: 0x%x\n",
 696                                                  wi->wqe_type);
 697                         }
 698                 } while (!last_wqe);
 699         } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
 700
 701         sq->cc = sqcc;
 702
 703         mlx5_cqwq_update_db_record(&cq->wq);
 704
 705         return i;
 706 }
 707
 708 INDIRECT_CALLABLE_SCOPE bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
 709 {
 710         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 711         u8  umr_completed = rq->mpwqe.umr_completed;
 712         struct mlx5e_icosq *sq = rq->icosq;
 713         int alloc_err = 0;
 714         u8  missing, i;
 715         u16 head;
 716
 717         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
 718                 return false;
 719
 720         if (umr_completed) {
 721                 mlx5e_post_rx_mpwqe(rq, umr_completed);
 722                 rq->mpwqe.umr_in_progress -= umr_completed;
 723                 rq->mpwqe.umr_completed = 0;
 724         }
 725
 726         missing = mlx5_wq_ll_missing(wq) - rq->mpwqe.umr_in_progress;
 727
 728         if (unlikely(rq->mpwqe.umr_in_progress > rq->mpwqe.umr_last_bulk))
 729                 rq->stats->congst_umr++;
 730
 731 #define UMR_WQE_BULK (2)
 732         if (likely(missing < UMR_WQE_BULK))
 733                 return false;
 734
 735         head = rq->mpwqe.actual_wq_head;
 736         i = missing;
 737         do {
 738                 alloc_err = mlx5e_alloc_rx_mpwqe(rq, head);
 739
 740                 if (unlikely(alloc_err))
 741                         break;
 742                 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 743         } while (--i);
 744
 745         rq->mpwqe.umr_last_bulk    = missing - i;
 746         if (sq->doorbell_cseg) {
 747                 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, sq->doorbell_cseg);
 748                 sq->doorbell_cseg = NULL;
 749         }
 750
 751         rq->mpwqe.umr_in_progress += rq->mpwqe.umr_last_bulk;
 752         rq->mpwqe.actual_wq_head   = head;
 753
 754         /* If XSK Fill Ring doesn't have enough frames, report the error, so
 755          * that one of the actions can be performed:
 756          * 1. If need_wakeup is used, signal that the application has to kick
 757          * the driver when it refills the Fill Ring.
 758          * 2. Otherwise, busy poll by rescheduling the NAPI poll.
 759          */
 760         if (unlikely(alloc_err == -ENOMEM && rq->xsk_pool))
 761                 return true;
 762
 763         return false;
 764 }
 765
 766 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
 767 {
 768         u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
 769         u8 tcp_ack     = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
 770                          (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
 771
 772         tcp->check                      = 0;
 773         tcp->psh                        = get_cqe_lro_tcppsh(cqe);
 774
 775         if (tcp_ack) {
 776                 tcp->ack                = 1;
 777                 tcp->ack_seq            = cqe->lro_ack_seq_num;
 778                 tcp->window             = cqe->lro_tcp_win;
 779         }
 780 }
 781
 782 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
 783                                  u32 cqe_bcnt)
 784 {
 785         struct ethhdr   *eth = (struct ethhdr *)(skb->data);
 786         struct tcphdr   *tcp;
 787         int network_depth = 0;
 788         __wsum check;
 789         __be16 proto;
 790         u16 tot_len;
 791         void *ip_p;
 792
 793         proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
 794
 795         tot_len = cqe_bcnt - network_depth;
 796         ip_p = skb->data + network_depth;
 797
 798         if (proto == htons(ETH_P_IP)) {
 799                 struct iphdr *ipv4 = ip_p;
 800
 801                 tcp = ip_p + sizeof(struct iphdr);
 802                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
 803
 804                 ipv4->ttl               = cqe->lro_min_ttl;
 805                 ipv4->tot_len           = cpu_to_be16(tot_len);
 806                 ipv4->check             = 0;
 807                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
 808                                                        ipv4->ihl);
 809
 810                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 811                 check = csum_partial(tcp, tcp->doff * 4,
 812                                      csum_unfold((__force __sum16)cqe->check_sum));
 813                 /* Almost done, don't forget the pseudo header */
 814                 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
 815                                                tot_len - sizeof(struct iphdr),
 816                                                IPPROTO_TCP, check);
 817         } else {
 818                 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
 819                 struct ipv6hdr *ipv6 = ip_p;
 820
 821                 tcp = ip_p + sizeof(struct ipv6hdr);
 822                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
 823
 824                 ipv6->hop_limit         = cqe->lro_min_ttl;
 825                 ipv6->payload_len       = cpu_to_be16(payload_len);
 826
 827                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 828                 check = csum_partial(tcp, tcp->doff * 4,
 829                                      csum_unfold((__force __sum16)cqe->check_sum));
 830                 /* Almost done, don't forget the pseudo header */
 831                 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
 832                                              IPPROTO_TCP, check);
 833         }
 834 }
 835
 836 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
 837                                       struct sk_buff *skb)
 838 {
 839         u8 cht = cqe->rss_hash_type;
 840         int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
 841                  (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
 842                                             PKT_HASH_TYPE_NONE;
 843         skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
 844 }
 845
 846 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth,
 847                                         __be16 *proto)
 848 {
 849         *proto = ((struct ethhdr *)skb->data)->h_proto;
 850         *proto = __vlan_get_protocol(skb, *proto, network_depth);
 851
 852         if (*proto == htons(ETH_P_IP))
 853                 return pskb_may_pull(skb, *network_depth + sizeof(struct iphdr));
 854
 855         if (*proto == htons(ETH_P_IPV6))
 856                 return pskb_may_pull(skb, *network_depth + sizeof(struct ipv6hdr));
 857
 858         return false;
 859 }
 860
 861 static inline void mlx5e_enable_ecn(struct mlx5e_rq *rq, struct sk_buff *skb)
 862 {
 863         int network_depth = 0;
 864         __be16 proto;
 865         void *ip;
 866         int rc;
 867
 868         if (unlikely(!is_last_ethertype_ip(skb, &network_depth, &proto)))
 869                 return;
 870
 871         ip = skb->data + network_depth;
 872         rc = ((proto == htons(ETH_P_IP)) ? IP_ECN_set_ce((struct iphdr *)ip) :
 873                                          IP6_ECN_set_ce(skb, (struct ipv6hdr *)ip));
 874
 875         rq->stats->ecn_mark += !!rc;
 876 }
 877
 878 static u8 get_ip_proto(struct sk_buff *skb, int network_depth, __be16 proto)
 879 {
 880         void *ip_p = skb->data + network_depth;
 881
 882         return (proto == htons(ETH_P_IP)) ? ((struct iphdr *)ip_p)->protocol :
 883                                             ((struct ipv6hdr *)ip_p)->nexthdr;
 884 }
 885
 886 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN)
 887
 888 #define MAX_PADDING 8
 889
 890 static void
 891 tail_padding_csum_slow(struct sk_buff *skb, int offset, int len,
 892                        struct mlx5e_rq_stats *stats)
 893 {
 894         stats->csum_complete_tail_slow++;
 895         skb->csum = csum_block_add(skb->csum,
 896                                    skb_checksum(skb, offset, len, 0),
 897                                    offset);
 898 }
 899
 900 static void
 901 tail_padding_csum(struct sk_buff *skb, int offset,
 902                   struct mlx5e_rq_stats *stats)
 903 {
 904         u8 tail_padding[MAX_PADDING];
 905         int len = skb->len - offset;
 906         void *tail;
 907
 908         if (unlikely(len > MAX_PADDING)) {
 909                 tail_padding_csum_slow(skb, offset, len, stats);
 910                 return;
 911         }
 912
 913         tail = skb_header_pointer(skb, offset, len, tail_padding);
 914         if (unlikely(!tail)) {
 915                 tail_padding_csum_slow(skb, offset, len, stats);
 916                 return;
 917         }
 918
 919         stats->csum_complete_tail++;
 920         skb->csum = csum_block_add(skb->csum, csum_partial(tail, len, 0), offset);
 921 }
 922
 923 static void
 924 mlx5e_skb_csum_fixup(struct sk_buff *skb, int network_depth, __be16 proto,
 925                      struct mlx5e_rq_stats *stats)
 926 {
 927         struct ipv6hdr *ip6;
 928         struct iphdr   *ip4;
 929         int pkt_len;
 930
 931         /* Fixup vlan headers, if any */
 932         if (network_depth > ETH_HLEN)
 933                 /* CQE csum is calculated from the IP header and does
 934                  * not cover VLAN headers (if present). This will add
 935                  * the checksum manually.
 936                  */
 937                 skb->csum = csum_partial(skb->data + ETH_HLEN,
 938                                          network_depth - ETH_HLEN,
 939                                          skb->csum);
 940
 941         /* Fixup tail padding, if any */
 942         switch (proto) {
 943         case htons(ETH_P_IP):
 944                 ip4 = (struct iphdr *)(skb->data + network_depth);
 945                 pkt_len = network_depth + ntohs(ip4->tot_len);
 946                 break;
 947         case htons(ETH_P_IPV6):
 948                 ip6 = (struct ipv6hdr *)(skb->data + network_depth);
 949                 pkt_len = network_depth + sizeof(*ip6) + ntohs(ip6->payload_len);
 950                 break;
 951         default:
 952                 return;
 953         }
 954
 955         if (likely(pkt_len >= skb->len))
 956                 return;
 957
 958         tail_padding_csum(skb, pkt_len, stats);
 959 }
 960
 961 static inline void mlx5e_handle_csum(struct net_device *netdev,
 962                                      struct mlx5_cqe64 *cqe,
 963                                      struct mlx5e_rq *rq,
 964                                      struct sk_buff *skb,
 965                                      bool   lro)
 966 {
 967         struct mlx5e_rq_stats *stats = rq->stats;
 968         int network_depth = 0;
 969         __be16 proto;
 970
 971         if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
 972                 goto csum_none;
 973
 974         if (lro) {
 975                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 976                 stats->csum_unnecessary++;
 977                 return;
 978         }
 979
 980         /* True when explicitly set via priv flag, or XDP prog is loaded */
 981         if (test_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state))
 982                 goto csum_unnecessary;
 983
 984         /* CQE csum doesn't cover padding octets in short ethernet
 985          * frames. And the pad field is appended prior to calculating
 986          * and appending the FCS field.
 987          *
 988          * Detecting these padded frames requires to verify and parse
 989          * IP headers, so we simply force all those small frames to be
 990          * CHECKSUM_UNNECESSARY even if they are not padded.
 991          */
 992         if (short_frame(skb->len))
 993                 goto csum_unnecessary;
 994
 995         if (likely(is_last_ethertype_ip(skb, &network_depth, &proto))) {
 996                 u8 ipproto = get_ip_proto(skb, network_depth, proto);
 997
 998                 if (unlikely(ipproto == IPPROTO_SCTP))
 999                         goto csum_unnecessary;
1000
1001                 if (unlikely(mlx5_ipsec_is_rx_flow(cqe)))
1002                         goto csum_none;
1003
1004                 stats->csum_complete++;
1005                 skb->ip_summed = CHECKSUM_COMPLETE;
1006                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1007
1008                 if (test_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state))
1009                         return; /* CQE csum covers all received bytes */
1010
1011                 /* csum might need some fixups ...*/
1012                 mlx5e_skb_csum_fixup(skb, network_depth, proto, stats);
1013                 return;
1014         }
1015
1016 csum_unnecessary:
1017         if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
1018                    (cqe->hds_ip_ext & CQE_L4_OK))) {
1019                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1020                 if (cqe_is_tunneled(cqe)) {
1021                         skb->csum_level = 1;
1022                         skb->encapsulation = 1;
1023                         stats->csum_unnecessary_inner++;
1024                         return;
1025                 }
1026                 stats->csum_unnecessary++;
1027                 return;
1028         }
1029 csum_none:
1030         skb->ip_summed = CHECKSUM_NONE;
1031         stats->csum_none++;
1032 }
1033
1034 #define MLX5E_CE_BIT_MASK 0x80
1035
1036 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
1037                                       u32 cqe_bcnt,
1038                                       struct mlx5e_rq *rq,
1039                                       struct sk_buff *skb)
1040 {
1041         u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
1042         struct mlx5e_rq_stats *stats = rq->stats;
1043         struct net_device *netdev = rq->netdev;
1044
1045         skb->mac_len = ETH_HLEN;
1046
1047         mlx5e_tls_handle_rx_skb(rq, skb, cqe, &cqe_bcnt);
1048
1049         if (unlikely(mlx5_ipsec_is_rx_flow(cqe)))
1050                 mlx5e_ipsec_offload_handle_rx_skb(netdev, skb, cqe);
1051
1052         if (lro_num_seg > 1) {
1053                 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
1054                 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
1055                 /* Subtract one since we already counted this as one
1056                  * "regular" packet in mlx5e_complete_rx_cqe()
1057                  */
1058                 stats->packets += lro_num_seg - 1;
1059                 stats->lro_packets++;
1060                 stats->lro_bytes += cqe_bcnt;
1061         }
1062
1063         if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
1064                 skb_hwtstamps(skb)->hwtstamp = mlx5e_cqe_ts_to_ns(rq->ptp_cyc2time,
1065                                                                   rq->clock, get_cqe_ts(cqe));
1066         skb_record_rx_queue(skb, rq->ix);
1067
1068         if (likely(netdev->features & NETIF_F_RXHASH))
1069                 mlx5e_skb_set_hash(cqe, skb);
1070
1071         if (cqe_has_vlan(cqe)) {
1072                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1073                                        be16_to_cpu(cqe->vlan_info));
1074                 stats->removed_vlan_packets++;
1075         }
1076
1077         skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
1078
1079         mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
1080         /* checking CE bit in cqe - MSB in ml_path field */
1081         if (unlikely(cqe->ml_path & MLX5E_CE_BIT_MASK))
1082                 mlx5e_enable_ecn(rq, skb);
1083
1084         skb->protocol = eth_type_trans(skb, netdev);
1085
1086         if (unlikely(mlx5e_skb_is_multicast(skb)))
1087                 stats->mcast_packets++;
1088 }
1089
1090 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
1091                                          struct mlx5_cqe64 *cqe,
1092                                          u32 cqe_bcnt,
1093                                          struct sk_buff *skb)
1094 {
1095         struct mlx5e_rq_stats *stats = rq->stats;
1096
1097         stats->packets++;
1098         stats->bytes += cqe_bcnt;
1099         mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
1100 }
1101
1102 static inline
1103 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
1104                                        u32 frag_size, u16 headroom,
1105                                        u32 cqe_bcnt)
1106 {
1107         struct sk_buff *skb = build_skb(va, frag_size);
1108
1109         if (unlikely(!skb)) {
1110                 rq->stats->buff_alloc_err++;
1111                 return NULL;
1112         }
1113
1114         skb_reserve(skb, headroom);
1115         skb_put(skb, cqe_bcnt);
1116
1117         return skb;
1118 }
1119
1120 static void mlx5e_fill_xdp_buff(struct mlx5e_rq *rq, void *va, u16 headroom,
1121                                 u32 len, struct xdp_buff *xdp)
1122 {
1123         xdp_init_buff(xdp, rq->buff.frame0_sz, &rq->xdp_rxq);
1124         xdp_prepare_buff(xdp, va, headroom, len, false);
1125 }
1126
1127 static struct sk_buff *
1128 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
1129                           struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
1130 {
1131         struct mlx5e_dma_info *di = wi->di;
1132         u16 rx_headroom = rq->buff.headroom;
1133         struct xdp_buff xdp;
1134         struct sk_buff *skb;
1135         void *va, *data;
1136         u32 frag_size;
1137
1138         va             = page_address(di->page) + wi->offset;
1139         data           = va + rx_headroom;
1140         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
1141
1142         dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
1143                                       frag_size, DMA_FROM_DEVICE);
1144         net_prefetchw(va); /* xdp_frame data area */
1145         net_prefetch(data);
1146
1147         mlx5e_fill_xdp_buff(rq, va, rx_headroom, cqe_bcnt, &xdp);
1148         if (mlx5e_xdp_handle(rq, di, &cqe_bcnt, &xdp))
1149                 return NULL; /* page/packet was consumed by XDP */
1150
1151         rx_headroom = xdp.data - xdp.data_hard_start;
1152         frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
1153         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
1154         if (unlikely(!skb))
1155                 return NULL;
1156
1157         /* queue up for recycling/reuse */
1158         page_ref_inc(di->page);
1159
1160         return skb;
1161 }
1162
1163 static struct sk_buff *
1164 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
1165                              struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
1166 {
1167         struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
1168         struct mlx5e_wqe_frag_info *head_wi = wi;
1169         u16 headlen      = min_t(u32, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1170         u16 frag_headlen = headlen;
1171         u16 byte_cnt     = cqe_bcnt - headlen;
1172         struct sk_buff *skb;
1173
1174         /* XDP is not supported in this configuration, as incoming packets
1175          * might spread among multiple pages.
1176          */
1177         skb = napi_alloc_skb(rq->cq.napi,
1178                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1179         if (unlikely(!skb)) {
1180                 rq->stats->buff_alloc_err++;
1181                 return NULL;
1182         }
1183
1184         net_prefetchw(skb->data);
1185
1186         while (byte_cnt) {
1187                 u16 frag_consumed_bytes =
1188                         min_t(u16, frag_info->frag_size - frag_headlen, byte_cnt);
1189
1190                 mlx5e_add_skb_frag(rq, skb, wi->di, wi->offset + frag_headlen,
1191                                    frag_consumed_bytes, frag_info->frag_stride);
1192                 byte_cnt -= frag_consumed_bytes;
1193                 frag_headlen = 0;
1194                 frag_info++;
1195                 wi++;
1196         }
1197
1198         /* copy header */
1199         mlx5e_copy_skb_header(rq->pdev, skb, head_wi->di, head_wi->offset, headlen);
1200         /* skb linear part was allocated with headlen and aligned to long */
1201         skb->tail += headlen;
1202         skb->len  += headlen;
1203
1204         return skb;
1205 }
1206
1207 static void trigger_report(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1208 {
1209         struct mlx5_err_cqe *err_cqe = (struct mlx5_err_cqe *)cqe;
1210         struct mlx5e_priv *priv = rq->priv;
1211
1212         if (cqe_syndrome_needs_recover(err_cqe->syndrome) &&
1213             !test_and_set_bit(MLX5E_RQ_STATE_RECOVERING, &rq->state)) {
1214                 mlx5e_dump_error_cqe(&rq->cq, rq->rqn, err_cqe);
1215                 queue_work(priv->wq, &rq->recover_work);
1216         }
1217 }
1218
1219 static void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1220 {
1221         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1222         struct mlx5e_wqe_frag_info *wi;
1223         struct sk_buff *skb;
1224         u32 cqe_bcnt;
1225         u16 ci;
1226
1227         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1228         wi       = get_frag(rq, ci);
1229         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1230
1231         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1232                 trigger_report(rq, cqe);
1233                 rq->stats->wqe_err++;
1234                 goto free_wqe;
1235         }
1236
1237         skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1238                               mlx5e_skb_from_cqe_linear,
1239                               mlx5e_skb_from_cqe_nonlinear,
1240                               rq, cqe, wi, cqe_bcnt);
1241         if (!skb) {
1242                 /* probably for XDP */
1243                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1244                         /* do not return page to cache,
1245                          * it will be returned on XDP_TX completion.
1246                          */
1247                         goto wq_cyc_pop;
1248                 }
1249                 goto free_wqe;
1250         }
1251
1252         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1253
1254         if (mlx5e_cqe_regb_chain(cqe))
1255                 if (!mlx5e_tc_update_skb(cqe, skb)) {
1256                         dev_kfree_skb_any(skb);
1257                         goto free_wqe;
1258                 }
1259
1260         napi_gro_receive(rq->cq.napi, skb);
1261
1262 free_wqe:
1263         mlx5e_free_rx_wqe(rq, wi, true);
1264 wq_cyc_pop:
1265         mlx5_wq_cyc_pop(wq);
1266 }
1267
1268 #ifdef CONFIG_MLX5_ESWITCH
1269 static void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1270 {
1271         struct net_device *netdev = rq->netdev;
1272         struct mlx5e_priv *priv = netdev_priv(netdev);
1273         struct mlx5e_rep_priv *rpriv  = priv->ppriv;
1274         struct mlx5_eswitch_rep *rep = rpriv->rep;
1275         struct mlx5e_tc_update_priv tc_priv = {};
1276         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1277         struct mlx5e_wqe_frag_info *wi;
1278         struct sk_buff *skb;
1279         u32 cqe_bcnt;
1280         u16 ci;
1281
1282         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1283         wi       = get_frag(rq, ci);
1284         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1285
1286         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1287                 rq->stats->wqe_err++;
1288                 goto free_wqe;
1289         }
1290
1291         skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1292                               mlx5e_skb_from_cqe_linear,
1293                               mlx5e_skb_from_cqe_nonlinear,
1294                               rq, cqe, wi, cqe_bcnt);
1295         if (!skb) {
1296                 /* probably for XDP */
1297                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1298                         /* do not return page to cache,
1299                          * it will be returned on XDP_TX completion.
1300                          */
1301                         goto wq_cyc_pop;
1302                 }
1303                 goto free_wqe;
1304         }
1305
1306         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1307
1308         if (rep->vlan && skb_vlan_tag_present(skb))
1309                 skb_vlan_pop(skb);
1310
1311         if (!mlx5e_rep_tc_update_skb(cqe, skb, &tc_priv)) {
1312                 dev_kfree_skb_any(skb);
1313                 goto free_wqe;
1314         }
1315
1316         napi_gro_receive(rq->cq.napi, skb);
1317
1318         mlx5_rep_tc_post_napi_receive(&tc_priv);
1319
1320 free_wqe:
1321         mlx5e_free_rx_wqe(rq, wi, true);
1322 wq_cyc_pop:
1323         mlx5_wq_cyc_pop(wq);
1324 }
1325
1326 static void mlx5e_handle_rx_cqe_mpwrq_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1327 {
1328         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1329         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1330         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1331         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
1332         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
1333         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
1334         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
1335         struct mlx5e_tc_update_priv tc_priv = {};
1336         struct mlx5e_rx_wqe_ll *wqe;
1337         struct mlx5_wq_ll *wq;
1338         struct sk_buff *skb;
1339         u16 cqe_bcnt;
1340
1341         wi->consumed_strides += cstrides;
1342
1343         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1344                 trigger_report(rq, cqe);
1345                 rq->stats->wqe_err++;
1346                 goto mpwrq_cqe_out;
1347         }
1348
1349         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1350                 struct mlx5e_rq_stats *stats = rq->stats;
1351
1352                 stats->mpwqe_filler_cqes++;
1353                 stats->mpwqe_filler_strides += cstrides;
1354                 goto mpwrq_cqe_out;
1355         }
1356
1357         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1358
1359         skb = INDIRECT_CALL_2(rq->mpwqe.skb_from_cqe_mpwrq,
1360                               mlx5e_skb_from_cqe_mpwrq_linear,
1361                               mlx5e_skb_from_cqe_mpwrq_nonlinear,
1362                               rq, wi, cqe_bcnt, head_offset, page_idx);
1363         if (!skb)
1364                 goto mpwrq_cqe_out;
1365
1366         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1367
1368         if (!mlx5e_rep_tc_update_skb(cqe, skb, &tc_priv)) {
1369                 dev_kfree_skb_any(skb);
1370                 goto mpwrq_cqe_out;
1371         }
1372
1373         napi_gro_receive(rq->cq.napi, skb);
1374
1375         mlx5_rep_tc_post_napi_receive(&tc_priv);
1376
1377 mpwrq_cqe_out:
1378         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1379                 return;
1380
1381         wq  = &rq->mpwqe.wq;
1382         wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1383         mlx5e_free_rx_mpwqe(rq, wi, true);
1384         mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1385 }
1386
1387 const struct mlx5e_rx_handlers mlx5e_rx_handlers_rep = {
1388         .handle_rx_cqe       = mlx5e_handle_rx_cqe_rep,
1389         .handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq_rep,
1390 };
1391 #endif
1392
1393 static struct sk_buff *
1394 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1395                                    u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1396 {
1397         u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1398         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1399         u32 frag_offset    = head_offset + headlen;
1400         u32 byte_cnt       = cqe_bcnt - headlen;
1401         struct mlx5e_dma_info *head_di = di;
1402         struct sk_buff *skb;
1403
1404         skb = napi_alloc_skb(rq->cq.napi,
1405                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1406         if (unlikely(!skb)) {
1407                 rq->stats->buff_alloc_err++;
1408                 return NULL;
1409         }
1410
1411         net_prefetchw(skb->data);
1412
1413         if (unlikely(frag_offset >= PAGE_SIZE)) {
1414                 di++;
1415                 frag_offset -= PAGE_SIZE;
1416         }
1417
1418         while (byte_cnt) {
1419                 u32 pg_consumed_bytes =
1420                         min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1421                 unsigned int truesize =
1422                         ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz));
1423
1424                 mlx5e_add_skb_frag(rq, skb, di, frag_offset,
1425                                    pg_consumed_bytes, truesize);
1426                 byte_cnt -= pg_consumed_bytes;
1427                 frag_offset = 0;
1428                 di++;
1429         }
1430         /* copy header */
1431         mlx5e_copy_skb_header(rq->pdev, skb, head_di, head_offset, headlen);
1432         /* skb linear part was allocated with headlen and aligned to long */
1433         skb->tail += headlen;
1434         skb->len  += headlen;
1435
1436         return skb;
1437 }
1438
1439 static struct sk_buff *
1440 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1441                                 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1442 {
1443         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1444         u16 rx_headroom = rq->buff.headroom;
1445         u32 cqe_bcnt32 = cqe_bcnt;
1446         struct xdp_buff xdp;
1447         struct sk_buff *skb;
1448         void *va, *data;
1449         u32 frag_size;
1450
1451         /* Check packet size. Note LRO doesn't use linear SKB */
1452         if (unlikely(cqe_bcnt > rq->hw_mtu)) {
1453                 rq->stats->oversize_pkts_sw_drop++;
1454                 return NULL;
1455         }
1456
1457         va             = page_address(di->page) + head_offset;
1458         data           = va + rx_headroom;
1459         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1460
1461         dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1462                                       frag_size, DMA_FROM_DEVICE);
1463         net_prefetchw(va); /* xdp_frame data area */
1464         net_prefetch(data);
1465
1466         mlx5e_fill_xdp_buff(rq, va, rx_headroom, cqe_bcnt32, &xdp);
1467         if (mlx5e_xdp_handle(rq, di, &cqe_bcnt32, &xdp)) {
1468                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1469                         __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1470                 return NULL; /* page/packet was consumed by XDP */
1471         }
1472
1473         rx_headroom = xdp.data - xdp.data_hard_start;
1474         frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1475         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1476         if (unlikely(!skb))
1477                 return NULL;
1478
1479         /* queue up for recycling/reuse */
1480         page_ref_inc(di->page);
1481
1482         return skb;
1483 }
1484
1485 static void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1486 {
1487         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1488         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1489         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1490         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
1491         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
1492         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
1493         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
1494         struct mlx5e_rx_wqe_ll *wqe;
1495         struct mlx5_wq_ll *wq;
1496         struct sk_buff *skb;
1497         u16 cqe_bcnt;
1498
1499         wi->consumed_strides += cstrides;
1500
1501         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1502                 trigger_report(rq, cqe);
1503                 rq->stats->wqe_err++;
1504                 goto mpwrq_cqe_out;
1505         }
1506
1507         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1508                 struct mlx5e_rq_stats *stats = rq->stats;
1509
1510                 stats->mpwqe_filler_cqes++;
1511                 stats->mpwqe_filler_strides += cstrides;
1512                 goto mpwrq_cqe_out;
1513         }
1514
1515         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1516
1517         skb = INDIRECT_CALL_2(rq->mpwqe.skb_from_cqe_mpwrq,
1518                               mlx5e_skb_from_cqe_mpwrq_linear,
1519                               mlx5e_skb_from_cqe_mpwrq_nonlinear,
1520                               rq, wi, cqe_bcnt, head_offset, page_idx);
1521         if (!skb)
1522                 goto mpwrq_cqe_out;
1523
1524         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1525
1526         if (mlx5e_cqe_regb_chain(cqe))
1527                 if (!mlx5e_tc_update_skb(cqe, skb)) {
1528                         dev_kfree_skb_any(skb);
1529                         goto mpwrq_cqe_out;
1530                 }
1531
1532         napi_gro_receive(rq->cq.napi, skb);
1533
1534 mpwrq_cqe_out:
1535         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1536                 return;
1537
1538         wq  = &rq->mpwqe.wq;
1539         wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1540         mlx5e_free_rx_mpwqe(rq, wi, true);
1541         mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1542 }
1543
1544 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1545 {
1546         struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1547         struct mlx5_cqwq *cqwq = &cq->wq;
1548         struct mlx5_cqe64 *cqe;
1549         int work_done = 0;
1550
1551         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
1552                 return 0;
1553
1554         if (rq->page_pool)
1555                 page_pool_nid_changed(rq->page_pool, numa_mem_id());
1556
1557         if (rq->cqd.left) {
1558                 work_done += mlx5e_decompress_cqes_cont(rq, cqwq, 0, budget);
1559                 if (rq->cqd.left || work_done >= budget)
1560                         goto out;
1561         }
1562
1563         cqe = mlx5_cqwq_get_cqe(cqwq);
1564         if (!cqe) {
1565                 if (unlikely(work_done))
1566                         goto out;
1567                 return 0;
1568         }
1569
1570         do {
1571                 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1572                         work_done +=
1573                                 mlx5e_decompress_cqes_start(rq, cqwq,
1574                                                             budget - work_done);
1575                         continue;
1576                 }
1577
1578                 mlx5_cqwq_pop(cqwq);
1579
1580                 INDIRECT_CALL_2(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq,
1581                                 mlx5e_handle_rx_cqe, rq, cqe);
1582         } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(cqwq)));
1583
1584 out:
1585         if (rcu_access_pointer(rq->xdp_prog))
1586                 mlx5e_xdp_rx_poll_complete(rq);
1587
1588         mlx5_cqwq_update_db_record(cqwq);
1589
1590         /* ensure cq space is freed before enabling more cqes */
1591         wmb();
1592
1593         return work_done;
1594 }
1595
1596 #ifdef CONFIG_MLX5_CORE_IPOIB
1597
1598 #define MLX5_IB_GRH_SGID_OFFSET 8
1599 #define MLX5_IB_GRH_DGID_OFFSET 24
1600 #define MLX5_GID_SIZE           16
1601
1602 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1603                                          struct mlx5_cqe64 *cqe,
1604                                          u32 cqe_bcnt,
1605                                          struct sk_buff *skb)
1606 {
1607         struct hwtstamp_config *tstamp;
1608         struct mlx5e_rq_stats *stats;
1609         struct net_device *netdev;
1610         struct mlx5e_priv *priv;
1611         char *pseudo_header;
1612         u32 flags_rqpn;
1613         u32 qpn;
1614         u8 *dgid;
1615         u8 g;
1616
1617         qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1618         netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1619
1620         /* No mapping present, cannot process SKB. This might happen if a child
1621          * interface is going down while having unprocessed CQEs on parent RQ
1622          */
1623         if (unlikely(!netdev)) {
1624                 /* TODO: add drop counters support */
1625                 skb->dev = NULL;
1626                 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1627                 return;
1628         }
1629
1630         priv = mlx5i_epriv(netdev);
1631         tstamp = &priv->tstamp;
1632         stats = &priv->channel_stats[rq->ix].rq;
1633
1634         flags_rqpn = be32_to_cpu(cqe->flags_rqpn);
1635         g = (flags_rqpn >> 28) & 3;
1636         dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1637         if ((!g) || dgid[0] != 0xff)
1638                 skb->pkt_type = PACKET_HOST;
1639         else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1640                 skb->pkt_type = PACKET_BROADCAST;
1641         else
1642                 skb->pkt_type = PACKET_MULTICAST;
1643
1644         /* Drop packets that this interface sent, ie multicast packets
1645          * that the HCA has replicated.
1646          */
1647         if (g && (qpn == (flags_rqpn & 0xffffff)) &&
1648             (memcmp(netdev->dev_addr + 4, skb->data + MLX5_IB_GRH_SGID_OFFSET,
1649                     MLX5_GID_SIZE) == 0)) {
1650                 skb->dev = NULL;
1651                 return;
1652         }
1653
1654         skb_pull(skb, MLX5_IB_GRH_BYTES);
1655
1656         skb->protocol = *((__be16 *)(skb->data));
1657
1658         if (netdev->features & NETIF_F_RXCSUM) {
1659                 skb->ip_summed = CHECKSUM_COMPLETE;
1660                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1661                 stats->csum_complete++;
1662         } else {
1663                 skb->ip_summed = CHECKSUM_NONE;
1664                 stats->csum_none++;
1665         }
1666
1667         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1668                 skb_hwtstamps(skb)->hwtstamp = mlx5e_cqe_ts_to_ns(rq->ptp_cyc2time,
1669                                                                   rq->clock, get_cqe_ts(cqe));
1670         skb_record_rx_queue(skb, rq->ix);
1671
1672         if (likely(netdev->features & NETIF_F_RXHASH))
1673                 mlx5e_skb_set_hash(cqe, skb);
1674
1675         /* 20 bytes of ipoib header and 4 for encap existing */
1676         pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1677         memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1678         skb_reset_mac_header(skb);
1679         skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1680
1681         skb->dev = netdev;
1682
1683         stats->packets++;
1684         stats->bytes += cqe_bcnt;
1685 }
1686
1687 static void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1688 {
1689         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1690         struct mlx5e_wqe_frag_info *wi;
1691         struct sk_buff *skb;
1692         u32 cqe_bcnt;
1693         u16 ci;
1694
1695         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1696         wi       = get_frag(rq, ci);
1697         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1698
1699         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1700                 rq->stats->wqe_err++;
1701                 goto wq_free_wqe;
1702         }
1703
1704         skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1705                               mlx5e_skb_from_cqe_linear,
1706                               mlx5e_skb_from_cqe_nonlinear,
1707                               rq, cqe, wi, cqe_bcnt);
1708         if (!skb)
1709                 goto wq_free_wqe;
1710
1711         mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1712         if (unlikely(!skb->dev)) {
1713                 dev_kfree_skb_any(skb);
1714                 goto wq_free_wqe;
1715         }
1716         napi_gro_receive(rq->cq.napi, skb);
1717
1718 wq_free_wqe:
1719         mlx5e_free_rx_wqe(rq, wi, true);
1720         mlx5_wq_cyc_pop(wq);
1721 }
1722
1723 const struct mlx5e_rx_handlers mlx5i_rx_handlers = {
1724         .handle_rx_cqe       = mlx5i_handle_rx_cqe,
1725         .handle_rx_cqe_mpwqe = NULL, /* Not supported */
1726 };
1727 #endif /* CONFIG_MLX5_CORE_IPOIB */
1728
1729 #ifdef CONFIG_MLX5_EN_IPSEC
1730
1731 static void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1732 {
1733         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1734         struct mlx5e_wqe_frag_info *wi;
1735         struct sk_buff *skb;
1736         u32 cqe_bcnt;
1737         u16 ci;
1738
1739         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1740         wi       = get_frag(rq, ci);
1741         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1742
1743         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1744                 rq->stats->wqe_err++;
1745                 goto wq_free_wqe;
1746         }
1747
1748         skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1749                               mlx5e_skb_from_cqe_linear,
1750                               mlx5e_skb_from_cqe_nonlinear,
1751                               rq, cqe, wi, cqe_bcnt);
1752         if (unlikely(!skb)) /* a DROP, save the page-reuse checks */
1753                 goto wq_free_wqe;
1754
1755         skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb, &cqe_bcnt);
1756         if (unlikely(!skb))
1757                 goto wq_free_wqe;
1758
1759         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1760         napi_gro_receive(rq->cq.napi, skb);
1761
1762 wq_free_wqe:
1763         mlx5e_free_rx_wqe(rq, wi, true);
1764         mlx5_wq_cyc_pop(wq);
1765 }
1766
1767 #endif /* CONFIG_MLX5_EN_IPSEC */
1768
1769 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk)
1770 {
1771         struct net_device *netdev = rq->netdev;
1772         struct mlx5_core_dev *mdev = rq->mdev;
1773         struct mlx5e_priv *priv = rq->priv;
1774
1775         switch (rq->wq_type) {
1776         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1777                 rq->mpwqe.skb_from_cqe_mpwrq = xsk ?
1778                         mlx5e_xsk_skb_from_cqe_mpwrq_linear :
1779                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ?
1780                                 mlx5e_skb_from_cqe_mpwrq_linear :
1781                                 mlx5e_skb_from_cqe_mpwrq_nonlinear;
1782                 rq->post_wqes = mlx5e_post_rx_mpwqes;
1783                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
1784
1785                 rq->handle_rx_cqe = priv->profile->rx_handlers->handle_rx_cqe_mpwqe;
1786                 if (mlx5_fpga_is_ipsec_device(mdev)) {
1787                         netdev_err(netdev, "MPWQE RQ with Innova IPSec offload not supported\n");
1788                         return -EINVAL;
1789                 }
1790                 if (!rq->handle_rx_cqe) {
1791                         netdev_err(netdev, "RX handler of MPWQE RQ is not set\n");
1792                         return -EINVAL;
1793                 }
1794                 break;
1795         default: /* MLX5_WQ_TYPE_CYCLIC */
1796                 rq->wqe.skb_from_cqe = xsk ?
1797                         mlx5e_xsk_skb_from_cqe_linear :
1798                         mlx5e_rx_is_linear_skb(params, NULL) ?
1799                                 mlx5e_skb_from_cqe_linear :
1800                                 mlx5e_skb_from_cqe_nonlinear;
1801                 rq->post_wqes = mlx5e_post_rx_wqes;
1802                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
1803
1804 #ifdef CONFIG_MLX5_EN_IPSEC
1805                 if ((mlx5_fpga_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) &&
1806                     priv->ipsec)
1807                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
1808                 else
1809 #endif
1810                         rq->handle_rx_cqe = priv->profile->rx_handlers->handle_rx_cqe;
1811                 if (!rq->handle_rx_cqe) {
1812                         netdev_err(netdev, "RX handler of RQ is not set\n");
1813                         return -EINVAL;
1814                 }
1815         }
1816
1817         return 0;
1818 }
1819
1820 static void mlx5e_trap_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1821 {
1822         struct mlx5e_priv *priv = netdev_priv(rq->netdev);
1823         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1824         struct mlx5e_wqe_frag_info *wi;
1825         struct sk_buff *skb;
1826         u32 cqe_bcnt;
1827         u16 trap_id;
1828         u16 ci;
1829
1830         trap_id  = get_cqe_flow_tag(cqe);
1831         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1832         wi       = get_frag(rq, ci);
1833         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1834
1835         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1836                 rq->stats->wqe_err++;
1837                 goto free_wqe;
1838         }
1839
1840         skb = mlx5e_skb_from_cqe_nonlinear(rq, cqe, wi, cqe_bcnt);
1841         if (!skb)
1842                 goto free_wqe;
1843
1844         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1845         skb_push(skb, ETH_HLEN);
1846
1847         mlx5_devlink_trap_report(rq->mdev, trap_id, skb, &priv->dl_port);
1848         dev_kfree_skb_any(skb);
1849
1850 free_wqe:
1851         mlx5e_free_rx_wqe(rq, wi, false);
1852         mlx5_wq_cyc_pop(wq);
1853 }
1854
1855 void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params)
1856 {
1857         rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(params, NULL) ?
1858                                mlx5e_skb_from_cqe_linear :
1859                                mlx5e_skb_from_cqe_nonlinear;
1860         rq->post_wqes = mlx5e_post_rx_wqes;
1861         rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
1862         rq->handle_rx_cqe = mlx5e_trap_handle_rx_cqe;
1863 }