2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <net/geneve.h>
38 #include <linux/bpf.h>
39 #include <linux/if_bridge.h>
40 #include <net/page_pool.h>
41 #include <net/xdp_sock_drv.h>
47 #include "en_accel/ipsec.h"
48 #include "en_accel/en_accel.h"
49 #include "en_accel/tls.h"
50 #include "accel/ipsec.h"
51 #include "accel/tls.h"
52 #include "lib/vxlan.h"
53 #include "lib/clock.h"
57 #include "en/monitor_stats.h"
58 #include "en/health.h"
59 #include "en/params.h"
60 #include "en/xsk/pool.h"
61 #include "en/xsk/setup.h"
62 #include "en/xsk/rx.h"
63 #include "en/xsk/tx.h"
64 #include "en/hv_vhca_stats.h"
65 #include "en/devlink.h"
70 #include "fpga/ipsec.h"
72 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
74 bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
75 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
76 MLX5_CAP_ETH(mdev, reg_umr_sq);
77 u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
78 bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
83 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
84 (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
90 void mlx5e_update_carrier(struct mlx5e_priv *priv)
92 struct mlx5_core_dev *mdev = priv->mdev;
96 port_state = mlx5_query_vport_state(mdev,
97 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
100 up = port_state == VPORT_STATE_UP;
101 if (up == netif_carrier_ok(priv->netdev))
102 netif_carrier_event(priv->netdev);
104 netdev_info(priv->netdev, "Link up\n");
105 netif_carrier_on(priv->netdev);
107 netdev_info(priv->netdev, "Link down\n");
108 netif_carrier_off(priv->netdev);
112 static void mlx5e_update_carrier_work(struct work_struct *work)
114 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
115 update_carrier_work);
117 mutex_lock(&priv->state_lock);
118 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
119 if (priv->profile->update_carrier)
120 priv->profile->update_carrier(priv);
121 mutex_unlock(&priv->state_lock);
124 static void mlx5e_update_stats_work(struct work_struct *work)
126 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
129 mutex_lock(&priv->state_lock);
130 priv->profile->update_stats(priv);
131 mutex_unlock(&priv->state_lock);
134 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
136 if (!priv->profile->update_stats)
139 if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
142 queue_work(priv->wq, &priv->update_stats_work);
145 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
147 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
148 struct mlx5_eqe *eqe = data;
150 if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
153 switch (eqe->sub_type) {
154 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
155 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
156 queue_work(priv->wq, &priv->update_carrier_work);
165 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
167 priv->events_nb.notifier_call = async_event;
168 mlx5_notifier_register(priv->mdev, &priv->events_nb);
171 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
173 mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
176 static int blocking_event(struct notifier_block *nb, unsigned long event, void *data)
178 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb);
182 case MLX5_DRIVER_EVENT_TYPE_TRAP:
183 err = mlx5e_handle_trap_event(priv, data);
186 netdev_warn(priv->netdev, "Sync event: Unknown event %ld\n", event);
192 static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv)
194 priv->blocking_events_nb.notifier_call = blocking_event;
195 mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb);
198 static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv)
200 mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb);
203 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
204 struct mlx5e_icosq *sq,
205 struct mlx5e_umr_wqe *wqe)
207 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
208 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
209 u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
211 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
213 cseg->umr_mkey = rq->mkey_be;
215 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
216 ucseg->xlt_octowords =
217 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
218 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
221 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node)
223 int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
225 rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
226 sizeof(*rq->mpwqe.info)),
231 mlx5e_build_umr_wqe(rq, rq->icosq, &rq->mpwqe.umr_wqe);
236 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
237 u64 npages, u8 page_shift,
238 struct mlx5_core_mkey *umr_mkey,
239 dma_addr_t filler_addr)
241 struct mlx5_mtt *mtt;
248 inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + sizeof(*mtt) * npages;
250 in = kvzalloc(inlen, GFP_KERNEL);
254 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
256 MLX5_SET(mkc, mkc, free, 1);
257 MLX5_SET(mkc, mkc, umr_en, 1);
258 MLX5_SET(mkc, mkc, lw, 1);
259 MLX5_SET(mkc, mkc, lr, 1);
260 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
261 mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
262 MLX5_SET(mkc, mkc, qpn, 0xffffff);
263 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
264 MLX5_SET64(mkc, mkc, len, npages << page_shift);
265 MLX5_SET(mkc, mkc, translations_octword_size,
266 MLX5_MTT_OCTW(npages));
267 MLX5_SET(mkc, mkc, log_page_size, page_shift);
268 MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
269 MLX5_MTT_OCTW(npages));
271 /* Initialize the mkey with all MTTs pointing to a default
272 * page (filler_addr). When the channels are activated, UMR
273 * WQEs will redirect the RX WQEs to the actual memory from
274 * the RQ's pool, while the gaps (wqe_overflow) remain mapped
275 * to the default page.
277 mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
278 for (i = 0 ; i < npages ; i++)
279 mtt[i].ptag = cpu_to_be64(filler_addr);
281 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
287 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
289 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
291 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey,
292 rq->wqe_overflow.addr);
295 static u64 mlx5e_get_mpwqe_offset(u16 wqe_ix)
297 return MLX5E_REQUIRED_MTTS(wqe_ix) << PAGE_SHIFT;
300 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
302 struct mlx5e_wqe_frag_info next_frag = {};
303 struct mlx5e_wqe_frag_info *prev = NULL;
306 next_frag.di = &rq->wqe.di[0];
308 for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
309 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
310 struct mlx5e_wqe_frag_info *frag =
311 &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
314 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
315 if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
317 next_frag.offset = 0;
319 prev->last_in_page = true;
324 next_frag.offset += frag_info[f].frag_stride;
330 prev->last_in_page = true;
333 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node)
335 int len = wq_sz << rq->wqe.info.log_num_frags;
337 rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)), GFP_KERNEL, node);
341 mlx5e_init_frags_partition(rq);
346 void mlx5e_free_di_list(struct mlx5e_rq *rq)
351 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
353 struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
355 mlx5e_reporter_rq_cqe_err(rq);
358 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
360 rq->wqe_overflow.page = alloc_page(GFP_KERNEL);
361 if (!rq->wqe_overflow.page)
364 rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0,
365 PAGE_SIZE, rq->buff.map_dir);
366 if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) {
367 __free_page(rq->wqe_overflow.page);
373 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
375 dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE,
377 __free_page(rq->wqe_overflow.page);
380 static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
383 struct mlx5_core_dev *mdev = c->mdev;
386 rq->wq_type = params->rq_wq_type;
388 rq->netdev = c->netdev;
390 rq->tstamp = c->tstamp;
391 rq->clock = &mdev->clock;
392 rq->icosq = &c->icosq;
395 rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
396 rq->xdpsq = &c->rq_xdpsq;
397 rq->stats = &c->priv->channel_stats[c->ix].rq;
398 rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev);
399 err = mlx5e_rq_set_handlers(rq, params, NULL);
403 return xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, 0);
406 static int mlx5e_alloc_rq(struct mlx5e_params *params,
407 struct mlx5e_xsk_param *xsk,
408 struct mlx5e_rq_param *rqp,
409 int node, struct mlx5e_rq *rq)
411 struct page_pool_params pp_params = { 0 };
412 struct mlx5_core_dev *mdev = rq->mdev;
413 void *rqc = rqp->rqc;
414 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
420 rqp->wq.db_numa_node = node;
421 INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
423 if (params->xdp_prog)
424 bpf_prog_inc(params->xdp_prog);
425 RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog);
427 rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
428 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
429 pool_size = 1 << params->log_rq_mtu_frames;
431 switch (rq->wq_type) {
432 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
433 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
436 goto err_rq_xdp_prog;
438 err = mlx5e_alloc_mpwqe_rq_drop_page(rq);
440 goto err_rq_wq_destroy;
442 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
444 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
446 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
447 mlx5e_mpwqe_get_log_rq_size(params, xsk);
449 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
450 rq->mpwqe.num_strides =
451 BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
453 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
455 err = mlx5e_create_rq_umr_mkey(mdev, rq);
457 goto err_rq_drop_page;
458 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
460 err = mlx5e_rq_alloc_mpwqe_info(rq, node);
464 default: /* MLX5_WQ_TYPE_CYCLIC */
465 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
468 goto err_rq_xdp_prog;
470 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
472 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
474 rq->wqe.info = rqp->frags_info;
475 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
478 kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
479 (wq_sz << rq->wqe.info.log_num_frags)),
481 if (!rq->wqe.frags) {
483 goto err_rq_wq_destroy;
486 err = mlx5e_init_di_list(rq, wq_sz, node);
490 rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey.key);
494 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
495 MEM_TYPE_XSK_BUFF_POOL, NULL);
496 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq);
498 /* Create a page_pool and register it with rxq */
500 pp_params.flags = 0; /* No-internal DMA mapping in page_pool */
501 pp_params.pool_size = pool_size;
502 pp_params.nid = node;
503 pp_params.dev = rq->pdev;
504 pp_params.dma_dir = rq->buff.map_dir;
506 /* page_pool can be used even when there is no rq->xdp_prog,
507 * given page_pool does not handle DMA mapping there is no
508 * required state to clear. And page_pool gracefully handle
511 rq->page_pool = page_pool_create(&pp_params);
512 if (IS_ERR(rq->page_pool)) {
513 err = PTR_ERR(rq->page_pool);
514 rq->page_pool = NULL;
515 goto err_free_by_rq_type;
517 if (xdp_rxq_info_is_reg(&rq->xdp_rxq))
518 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
519 MEM_TYPE_PAGE_POOL, rq->page_pool);
522 goto err_free_by_rq_type;
524 for (i = 0; i < wq_sz; i++) {
525 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
526 struct mlx5e_rx_wqe_ll *wqe =
527 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
529 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
530 u64 dma_offset = mlx5e_get_mpwqe_offset(i);
532 wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
533 wqe->data[0].byte_count = cpu_to_be32(byte_count);
534 wqe->data[0].lkey = rq->mkey_be;
536 struct mlx5e_rx_wqe_cyc *wqe =
537 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
540 for (f = 0; f < rq->wqe.info.num_frags; f++) {
541 u32 frag_size = rq->wqe.info.arr[f].frag_size |
542 MLX5_HW_START_PADDING;
544 wqe->data[f].byte_count = cpu_to_be32(frag_size);
545 wqe->data[f].lkey = rq->mkey_be;
547 /* check if num_frags is not a pow of two */
548 if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
549 wqe->data[f].byte_count = 0;
550 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
551 wqe->data[f].addr = 0;
556 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
558 switch (params->rx_cq_moderation.cq_period_mode) {
559 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
560 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
562 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
564 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
567 rq->page_cache.head = 0;
568 rq->page_cache.tail = 0;
573 switch (rq->wq_type) {
574 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
575 kvfree(rq->mpwqe.info);
577 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
579 mlx5e_free_mpwqe_rq_drop_page(rq);
581 default: /* MLX5_WQ_TYPE_CYCLIC */
582 mlx5e_free_di_list(rq);
584 kvfree(rq->wqe.frags);
587 mlx5_wq_destroy(&rq->wq_ctrl);
589 if (params->xdp_prog)
590 bpf_prog_put(params->xdp_prog);
595 static void mlx5e_free_rq(struct mlx5e_rq *rq)
597 struct bpf_prog *old_prog;
600 if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) {
601 old_prog = rcu_dereference_protected(rq->xdp_prog,
602 lockdep_is_held(&rq->priv->state_lock));
604 bpf_prog_put(old_prog);
607 switch (rq->wq_type) {
608 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
609 kvfree(rq->mpwqe.info);
610 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
611 mlx5e_free_mpwqe_rq_drop_page(rq);
613 default: /* MLX5_WQ_TYPE_CYCLIC */
614 kvfree(rq->wqe.frags);
615 mlx5e_free_di_list(rq);
618 for (i = rq->page_cache.head; i != rq->page_cache.tail;
619 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
620 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
622 /* With AF_XDP, page_cache is not used, so this loop is not
623 * entered, and it's safe to call mlx5e_page_release_dynamic
626 mlx5e_page_release_dynamic(rq, dma_info, false);
629 xdp_rxq_info_unreg(&rq->xdp_rxq);
630 page_pool_destroy(rq->page_pool);
631 mlx5_wq_destroy(&rq->wq_ctrl);
634 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
636 struct mlx5_core_dev *mdev = rq->mdev;
644 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
645 sizeof(u64) * rq->wq_ctrl.buf.npages;
646 in = kvzalloc(inlen, GFP_KERNEL);
650 ts_format = mlx5_is_real_time_rq(mdev) ?
651 MLX5_TIMESTAMP_FORMAT_REAL_TIME :
652 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
653 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
654 wq = MLX5_ADDR_OF(rqc, rqc, wq);
656 memcpy(rqc, param->rqc, sizeof(param->rqc));
658 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
659 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
660 MLX5_SET(rqc, rqc, ts_format, ts_format);
661 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
662 MLX5_ADAPTER_PAGE_SHIFT);
663 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
665 mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
666 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
668 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
675 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
677 struct mlx5_core_dev *mdev = rq->mdev;
684 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
685 in = kvzalloc(inlen, GFP_KERNEL);
689 if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
690 mlx5e_rqwq_reset(rq);
692 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
694 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
695 MLX5_SET(rqc, rqc, state, next_state);
697 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
704 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
706 struct mlx5_core_dev *mdev = rq->mdev;
713 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
714 in = kvzalloc(inlen, GFP_KERNEL);
718 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
720 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
721 MLX5_SET64(modify_rq_in, in, modify_bitmask,
722 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
723 MLX5_SET(rqc, rqc, scatter_fcs, enable);
724 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
726 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
733 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
735 struct mlx5_core_dev *mdev = rq->mdev;
741 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
742 in = kvzalloc(inlen, GFP_KERNEL);
746 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
748 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
749 MLX5_SET64(modify_rq_in, in, modify_bitmask,
750 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
751 MLX5_SET(rqc, rqc, vsd, vsd);
752 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
754 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
761 void mlx5e_destroy_rq(struct mlx5e_rq *rq)
763 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
766 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
768 unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
770 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
773 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
777 } while (time_before(jiffies, exp_time));
779 netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
780 rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
782 mlx5e_reporter_rx_timeout(rq);
786 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq)
788 struct mlx5_wq_ll *wq;
792 if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
798 /* Outstanding UMR WQEs (in progress) start at wq->head */
799 for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
800 rq->dealloc_wqe(rq, head);
801 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
804 rq->mpwqe.actual_wq_head = wq->head;
805 rq->mpwqe.umr_in_progress = 0;
806 rq->mpwqe.umr_completed = 0;
809 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
814 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
815 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
817 mlx5e_free_rx_in_progress_descs(rq);
819 while (!mlx5_wq_ll_is_empty(wq)) {
820 struct mlx5e_rx_wqe_ll *wqe;
822 wqe_ix_be = *wq->tail_next;
823 wqe_ix = be16_to_cpu(wqe_ix_be);
824 wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix);
825 rq->dealloc_wqe(rq, wqe_ix);
826 mlx5_wq_ll_pop(wq, wqe_ix_be,
827 &wqe->next.next_wqe_index);
830 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
832 while (!mlx5_wq_cyc_is_empty(wq)) {
833 wqe_ix = mlx5_wq_cyc_get_tail(wq);
834 rq->dealloc_wqe(rq, wqe_ix);
841 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
842 struct mlx5e_xsk_param *xsk, int node,
845 struct mlx5_core_dev *mdev = rq->mdev;
848 err = mlx5e_alloc_rq(params, xsk, param, node, rq);
852 err = mlx5e_create_rq(rq, param);
856 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
860 if (mlx5e_is_tls_on(rq->priv) && !mlx5e_accel_is_ktls_device(mdev))
861 __set_bit(MLX5E_RQ_STATE_FPGA_TLS, &rq->state); /* must be FPGA */
863 if (MLX5_CAP_ETH(mdev, cqe_checksum_full))
864 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state);
866 if (params->rx_dim_enabled)
867 __set_bit(MLX5E_RQ_STATE_AM, &rq->state);
869 /* We disable csum_complete when XDP is enabled since
870 * XDP programs might manipulate packets which will render
871 * skb->checksum incorrect.
873 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || params->xdp_prog)
874 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state);
876 /* For CQE compression on striding RQ, use stride index provided by
877 * HW if capability is supported.
879 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) &&
880 MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index))
881 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state);
886 mlx5e_destroy_rq(rq);
893 void mlx5e_activate_rq(struct mlx5e_rq *rq)
895 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
897 mlx5e_trigger_irq(rq->icosq);
900 napi_schedule(rq->cq.napi);
905 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
907 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
908 synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */
911 void mlx5e_close_rq(struct mlx5e_rq *rq)
913 cancel_work_sync(&rq->dim.work);
915 cancel_work_sync(&rq->icosq->recover_work);
916 cancel_work_sync(&rq->recover_work);
917 mlx5e_destroy_rq(rq);
918 mlx5e_free_rx_descs(rq);
922 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
924 kvfree(sq->db.xdpi_fifo.xi);
925 kvfree(sq->db.wqe_info);
928 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
930 struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
931 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
932 int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
934 xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
939 xdpi_fifo->pc = &sq->xdpi_fifo_pc;
940 xdpi_fifo->cc = &sq->xdpi_fifo_cc;
941 xdpi_fifo->mask = dsegs_per_wq - 1;
946 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
948 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
951 sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
953 if (!sq->db.wqe_info)
956 err = mlx5e_alloc_xdpsq_fifo(sq, numa);
958 mlx5e_free_xdpsq_db(sq);
965 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
966 struct mlx5e_params *params,
967 struct xsk_buff_pool *xsk_pool,
968 struct mlx5e_sq_param *param,
969 struct mlx5e_xdpsq *sq,
972 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
973 struct mlx5_core_dev *mdev = c->mdev;
974 struct mlx5_wq_cyc *wq = &sq->wq;
978 sq->mkey_be = c->mkey_be;
980 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
981 sq->min_inline_mode = params->tx_min_inline_mode;
982 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
983 sq->xsk_pool = xsk_pool;
985 sq->stats = sq->xsk_pool ?
986 &c->priv->channel_stats[c->ix].xsksq :
988 &c->priv->channel_stats[c->ix].xdpsq :
989 &c->priv->channel_stats[c->ix].rq_xdpsq;
991 param->wq.db_numa_node = cpu_to_node(c->cpu);
992 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
995 wq->db = &wq->db[MLX5_SND_DBR];
997 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
999 goto err_sq_wq_destroy;
1004 mlx5_wq_destroy(&sq->wq_ctrl);
1009 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1011 mlx5e_free_xdpsq_db(sq);
1012 mlx5_wq_destroy(&sq->wq_ctrl);
1015 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1017 kvfree(sq->db.wqe_info);
1020 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1022 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1025 size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1026 sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1027 if (!sq->db.wqe_info)
1033 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1035 struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1038 mlx5e_reporter_icosq_cqe_err(sq);
1041 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1042 struct mlx5e_sq_param *param,
1043 struct mlx5e_icosq *sq)
1045 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1046 struct mlx5_core_dev *mdev = c->mdev;
1047 struct mlx5_wq_cyc *wq = &sq->wq;
1051 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
1052 sq->reserved_room = param->stop_room;
1054 param->wq.db_numa_node = cpu_to_node(c->cpu);
1055 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1058 wq->db = &wq->db[MLX5_SND_DBR];
1060 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1062 goto err_sq_wq_destroy;
1064 INIT_WORK(&sq->recover_work, mlx5e_icosq_err_cqe_work);
1069 mlx5_wq_destroy(&sq->wq_ctrl);
1074 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1076 mlx5e_free_icosq_db(sq);
1077 mlx5_wq_destroy(&sq->wq_ctrl);
1080 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1082 kvfree(sq->db.wqe_info);
1083 kvfree(sq->db.skb_fifo.fifo);
1084 kvfree(sq->db.dma_fifo);
1087 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1089 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1090 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1092 sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1093 sizeof(*sq->db.dma_fifo)),
1095 sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz,
1096 sizeof(*sq->db.skb_fifo.fifo)),
1098 sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1099 sizeof(*sq->db.wqe_info)),
1101 if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) {
1102 mlx5e_free_txqsq_db(sq);
1106 sq->dma_fifo_mask = df_sz - 1;
1108 sq->db.skb_fifo.pc = &sq->skb_fifo_pc;
1109 sq->db.skb_fifo.cc = &sq->skb_fifo_cc;
1110 sq->db.skb_fifo.mask = df_sz - 1;
1115 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1117 struct mlx5e_params *params,
1118 struct mlx5e_sq_param *param,
1119 struct mlx5e_txqsq *sq,
1122 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1123 struct mlx5_core_dev *mdev = c->mdev;
1124 struct mlx5_wq_cyc *wq = &sq->wq;
1128 sq->tstamp = c->tstamp;
1129 sq->clock = &mdev->clock;
1130 sq->mkey_be = c->mkey_be;
1131 sq->netdev = c->netdev;
1135 sq->txq_ix = txq_ix;
1136 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
1137 sq->min_inline_mode = params->tx_min_inline_mode;
1138 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1139 INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1140 if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1141 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1142 if (MLX5_IPSEC_DEV(c->priv->mdev))
1143 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1145 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state);
1146 sq->stop_room = param->stop_room;
1147 sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev);
1149 param->wq.db_numa_node = cpu_to_node(c->cpu);
1150 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1153 wq->db = &wq->db[MLX5_SND_DBR];
1155 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1157 goto err_sq_wq_destroy;
1159 INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1160 sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1165 mlx5_wq_destroy(&sq->wq_ctrl);
1170 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1172 mlx5e_free_txqsq_db(sq);
1173 mlx5_wq_destroy(&sq->wq_ctrl);
1176 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1177 struct mlx5e_sq_param *param,
1178 struct mlx5e_create_sq_param *csp,
1188 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1189 sizeof(u64) * csp->wq_ctrl->buf.npages;
1190 in = kvzalloc(inlen, GFP_KERNEL);
1194 ts_format = mlx5_is_real_time_sq(mdev) ?
1195 MLX5_TIMESTAMP_FORMAT_REAL_TIME :
1196 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
1197 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1198 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1200 memcpy(sqc, param->sqc, sizeof(param->sqc));
1201 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1202 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1203 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1204 MLX5_SET(sqc, sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn);
1205 MLX5_SET(sqc, sqc, ts_format, ts_format);
1208 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1209 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1211 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1212 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1214 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1215 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.hw_objs.bfreg.index);
1216 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1217 MLX5_ADAPTER_PAGE_SHIFT);
1218 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1220 mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1221 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1223 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1230 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1231 struct mlx5e_modify_sq_param *p)
1239 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1240 in = kvzalloc(inlen, GFP_KERNEL);
1244 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1246 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1247 MLX5_SET(sqc, sqc, state, p->next_state);
1248 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1250 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1252 if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) {
1254 MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id);
1256 MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask);
1258 err = mlx5_core_modify_sq(mdev, sqn, in);
1265 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1267 mlx5_core_destroy_sq(mdev, sqn);
1270 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1271 struct mlx5e_sq_param *param,
1272 struct mlx5e_create_sq_param *csp,
1273 u16 qos_queue_group_id,
1276 struct mlx5e_modify_sq_param msp = {0};
1279 err = mlx5e_create_sq(mdev, param, csp, sqn);
1283 msp.curr_state = MLX5_SQC_STATE_RST;
1284 msp.next_state = MLX5_SQC_STATE_RDY;
1285 if (qos_queue_group_id) {
1286 msp.qos_update = true;
1287 msp.qos_queue_group_id = qos_queue_group_id;
1289 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1291 mlx5e_destroy_sq(mdev, *sqn);
1296 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1297 struct mlx5e_txqsq *sq, u32 rate);
1299 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1300 struct mlx5e_params *params, struct mlx5e_sq_param *param,
1301 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, u16 qos_qid)
1303 struct mlx5e_create_sq_param csp = {};
1307 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1311 if (qos_queue_group_id)
1312 sq->stats = c->priv->htb.qos_sq_stats[qos_qid];
1314 sq->stats = &c->priv->channel_stats[c->ix].sq[tc];
1318 csp.cqn = sq->cq.mcq.cqn;
1319 csp.wq_ctrl = &sq->wq_ctrl;
1320 csp.min_inline_mode = sq->min_inline_mode;
1321 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn);
1323 goto err_free_txqsq;
1325 tx_rate = c->priv->tx_rates[sq->txq_ix];
1327 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1329 if (params->tx_dim_enabled)
1330 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1335 mlx5e_free_txqsq(sq);
1340 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1342 sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix);
1343 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1344 netdev_tx_reset_queue(sq->txq);
1345 netif_tx_start_queue(sq->txq);
1348 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1350 __netif_tx_lock_bh(txq);
1351 netif_tx_stop_queue(txq);
1352 __netif_tx_unlock_bh(txq);
1355 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1357 struct mlx5_wq_cyc *wq = &sq->wq;
1359 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1360 synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */
1362 mlx5e_tx_disable_queue(sq->txq);
1364 /* last doorbell out, godspeed .. */
1365 if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1366 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1367 struct mlx5e_tx_wqe *nop;
1369 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1373 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1374 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1378 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1380 struct mlx5_core_dev *mdev = sq->mdev;
1381 struct mlx5_rate_limit rl = {0};
1383 cancel_work_sync(&sq->dim.work);
1384 cancel_work_sync(&sq->recover_work);
1385 mlx5e_destroy_sq(mdev, sq->sqn);
1386 if (sq->rate_limit) {
1387 rl.rate = sq->rate_limit;
1388 mlx5_rl_remove_rate(mdev, &rl);
1390 mlx5e_free_txqsq_descs(sq);
1391 mlx5e_free_txqsq(sq);
1394 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1396 struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1399 mlx5e_reporter_tx_err_cqe(sq);
1402 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1403 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1405 struct mlx5e_create_sq_param csp = {};
1408 err = mlx5e_alloc_icosq(c, param, sq);
1412 csp.cqn = sq->cq.mcq.cqn;
1413 csp.wq_ctrl = &sq->wq_ctrl;
1414 csp.min_inline_mode = params->tx_min_inline_mode;
1415 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1417 goto err_free_icosq;
1419 if (param->is_tls) {
1420 sq->ktls_resync = mlx5e_ktls_rx_resync_create_resp_list();
1421 if (IS_ERR(sq->ktls_resync)) {
1422 err = PTR_ERR(sq->ktls_resync);
1423 goto err_destroy_icosq;
1429 mlx5e_destroy_sq(c->mdev, sq->sqn);
1431 mlx5e_free_icosq(sq);
1436 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1438 set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1441 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1443 clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1444 synchronize_net(); /* Sync with NAPI. */
1447 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1449 struct mlx5e_channel *c = sq->channel;
1451 if (sq->ktls_resync)
1452 mlx5e_ktls_rx_resync_destroy_resp_list(sq->ktls_resync);
1453 mlx5e_destroy_sq(c->mdev, sq->sqn);
1454 mlx5e_free_icosq_descs(sq);
1455 mlx5e_free_icosq(sq);
1458 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1459 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1460 struct mlx5e_xdpsq *sq, bool is_redirect)
1462 struct mlx5e_create_sq_param csp = {};
1465 err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect);
1470 csp.tisn = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1471 csp.cqn = sq->cq.mcq.cqn;
1472 csp.wq_ctrl = &sq->wq_ctrl;
1473 csp.min_inline_mode = sq->min_inline_mode;
1474 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1475 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1477 goto err_free_xdpsq;
1479 mlx5e_set_xmit_fp(sq, param->is_mpw);
1481 if (!param->is_mpw) {
1482 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1483 unsigned int inline_hdr_sz = 0;
1486 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1487 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1491 /* Pre initialize fixed WQE fields */
1492 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1493 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1494 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1495 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1496 struct mlx5_wqe_data_seg *dseg;
1498 sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1503 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1504 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1506 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1507 dseg->lkey = sq->mkey_be;
1514 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1515 mlx5e_free_xdpsq(sq);
1520 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1522 struct mlx5e_channel *c = sq->channel;
1524 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1525 synchronize_net(); /* Sync with NAPI. */
1527 mlx5e_destroy_sq(c->mdev, sq->sqn);
1528 mlx5e_free_xdpsq_descs(sq);
1529 mlx5e_free_xdpsq(sq);
1532 static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv,
1533 struct mlx5e_cq_param *param,
1534 struct mlx5e_cq *cq)
1536 struct mlx5_core_dev *mdev = priv->mdev;
1537 struct mlx5_core_cq *mcq = &cq->mcq;
1543 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1547 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1553 mcq->set_ci_db = cq->wq_ctrl.db.db;
1554 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1555 *mcq->set_ci_db = 0;
1557 mcq->vector = param->eq_ix;
1558 mcq->comp = mlx5e_completion_event;
1559 mcq->event = mlx5e_cq_error_event;
1562 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1563 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1569 cq->netdev = priv->netdev;
1575 static int mlx5e_alloc_cq(struct mlx5e_priv *priv,
1576 struct mlx5e_cq_param *param,
1577 struct mlx5e_create_cq_param *ccp,
1578 struct mlx5e_cq *cq)
1582 param->wq.buf_numa_node = ccp->node;
1583 param->wq.db_numa_node = ccp->node;
1584 param->eq_ix = ccp->ix;
1586 err = mlx5e_alloc_cq_common(priv, param, cq);
1588 cq->napi = ccp->napi;
1589 cq->ch_stats = ccp->ch_stats;
1594 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1596 mlx5_wq_destroy(&cq->wq_ctrl);
1599 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1601 u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1602 struct mlx5_core_dev *mdev = cq->mdev;
1603 struct mlx5_core_cq *mcq = &cq->mcq;
1608 unsigned int irqn_not_used;
1612 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1616 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1617 sizeof(u64) * cq->wq_ctrl.buf.npages;
1618 in = kvzalloc(inlen, GFP_KERNEL);
1622 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1624 memcpy(cqc, param->cqc, sizeof(param->cqc));
1626 mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1627 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1629 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1630 MLX5_SET(cqc, cqc, c_eqn, eqn);
1631 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1632 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1633 MLX5_ADAPTER_PAGE_SHIFT);
1634 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1636 err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1648 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1650 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1653 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
1654 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1655 struct mlx5e_cq *cq)
1657 struct mlx5_core_dev *mdev = priv->mdev;
1660 err = mlx5e_alloc_cq(priv, param, ccp, cq);
1664 err = mlx5e_create_cq(cq, param);
1668 if (MLX5_CAP_GEN(mdev, cq_moderation))
1669 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1678 void mlx5e_close_cq(struct mlx5e_cq *cq)
1680 mlx5e_destroy_cq(cq);
1684 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1685 struct mlx5e_params *params,
1686 struct mlx5e_create_cq_param *ccp,
1687 struct mlx5e_channel_param *cparam)
1692 for (tc = 0; tc < c->num_tc; tc++) {
1693 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->txq_sq.cqp,
1694 ccp, &c->sq[tc].cq);
1696 goto err_close_tx_cqs;
1702 for (tc--; tc >= 0; tc--)
1703 mlx5e_close_cq(&c->sq[tc].cq);
1708 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1712 for (tc = 0; tc < c->num_tc; tc++)
1713 mlx5e_close_cq(&c->sq[tc].cq);
1716 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1717 struct mlx5e_params *params,
1718 struct mlx5e_channel_param *cparam)
1722 for (tc = 0; tc < params->num_tc; tc++) {
1723 int txq_ix = c->ix + tc * params->num_channels;
1725 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1726 params, &cparam->txq_sq, &c->sq[tc], tc, 0, 0);
1734 for (tc--; tc >= 0; tc--)
1735 mlx5e_close_txqsq(&c->sq[tc]);
1740 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1744 for (tc = 0; tc < c->num_tc; tc++)
1745 mlx5e_close_txqsq(&c->sq[tc]);
1748 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1749 struct mlx5e_txqsq *sq, u32 rate)
1751 struct mlx5e_priv *priv = netdev_priv(dev);
1752 struct mlx5_core_dev *mdev = priv->mdev;
1753 struct mlx5e_modify_sq_param msp = {0};
1754 struct mlx5_rate_limit rl = {0};
1758 if (rate == sq->rate_limit)
1762 if (sq->rate_limit) {
1763 rl.rate = sq->rate_limit;
1764 /* remove current rl index to free space to next ones */
1765 mlx5_rl_remove_rate(mdev, &rl);
1772 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1774 netdev_err(dev, "Failed configuring rate %u: %d\n",
1780 msp.curr_state = MLX5_SQC_STATE_RDY;
1781 msp.next_state = MLX5_SQC_STATE_RDY;
1782 msp.rl_index = rl_index;
1783 msp.rl_update = true;
1784 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1786 netdev_err(dev, "Failed configuring rate %u: %d\n",
1788 /* remove the rate from the table */
1790 mlx5_rl_remove_rate(mdev, &rl);
1794 sq->rate_limit = rate;
1798 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1800 struct mlx5e_priv *priv = netdev_priv(dev);
1801 struct mlx5_core_dev *mdev = priv->mdev;
1802 struct mlx5e_txqsq *sq = priv->txq2sq[index];
1805 if (!mlx5_rl_is_supported(mdev)) {
1806 netdev_err(dev, "Rate limiting is not supported on this device\n");
1810 /* rate is given in Mb/sec, HW config is in Kb/sec */
1813 /* Check whether rate in valid range, 0 is always valid */
1814 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1815 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1819 mutex_lock(&priv->state_lock);
1820 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1821 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1823 priv->tx_rates[index] = rate;
1824 mutex_unlock(&priv->state_lock);
1829 static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
1830 struct mlx5e_rq_param *rq_params)
1834 err = mlx5e_init_rxq_rq(c, params, &c->rq);
1838 return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), &c->rq);
1841 static int mlx5e_open_queues(struct mlx5e_channel *c,
1842 struct mlx5e_params *params,
1843 struct mlx5e_channel_param *cparam)
1845 struct dim_cq_moder icocq_moder = {0, 0};
1846 struct mlx5e_create_cq_param ccp;
1849 mlx5e_build_create_cq_param(&ccp, c);
1851 err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->async_icosq.cqp, &ccp,
1852 &c->async_icosq.cq);
1856 err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->icosq.cqp, &ccp,
1859 goto err_close_async_icosq_cq;
1861 err = mlx5e_open_tx_cqs(c, params, &ccp, cparam);
1863 goto err_close_icosq_cq;
1865 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp,
1868 goto err_close_tx_cqs;
1870 err = mlx5e_open_cq(c->priv, params->rx_cq_moderation, &cparam->rq.cqp, &ccp,
1873 goto err_close_xdp_tx_cqs;
1875 err = c->xdp ? mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp,
1876 &ccp, &c->rq_xdpsq.cq) : 0;
1878 goto err_close_rx_cq;
1880 spin_lock_init(&c->async_icosq_lock);
1882 err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq);
1884 goto err_close_xdpsq_cq;
1886 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1888 goto err_close_async_icosq;
1890 err = mlx5e_open_sqs(c, params, cparam);
1892 goto err_close_icosq;
1895 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1896 &c->rq_xdpsq, false);
1901 err = mlx5e_open_rxq_rq(c, params, &cparam->rq);
1903 goto err_close_xdp_sq;
1905 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1912 mlx5e_close_rq(&c->rq);
1916 mlx5e_close_xdpsq(&c->rq_xdpsq);
1922 mlx5e_close_icosq(&c->icosq);
1924 err_close_async_icosq:
1925 mlx5e_close_icosq(&c->async_icosq);
1929 mlx5e_close_cq(&c->rq_xdpsq.cq);
1932 mlx5e_close_cq(&c->rq.cq);
1934 err_close_xdp_tx_cqs:
1935 mlx5e_close_cq(&c->xdpsq.cq);
1938 mlx5e_close_tx_cqs(c);
1941 mlx5e_close_cq(&c->icosq.cq);
1943 err_close_async_icosq_cq:
1944 mlx5e_close_cq(&c->async_icosq.cq);
1949 static void mlx5e_close_queues(struct mlx5e_channel *c)
1951 mlx5e_close_xdpsq(&c->xdpsq);
1952 mlx5e_close_rq(&c->rq);
1954 mlx5e_close_xdpsq(&c->rq_xdpsq);
1956 mlx5e_close_icosq(&c->icosq);
1957 mlx5e_close_icosq(&c->async_icosq);
1959 mlx5e_close_cq(&c->rq_xdpsq.cq);
1960 mlx5e_close_cq(&c->rq.cq);
1961 mlx5e_close_cq(&c->xdpsq.cq);
1962 mlx5e_close_tx_cqs(c);
1963 mlx5e_close_cq(&c->icosq.cq);
1964 mlx5e_close_cq(&c->async_icosq.cq);
1967 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
1969 u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
1971 return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
1974 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1975 struct mlx5e_params *params,
1976 struct mlx5e_channel_param *cparam,
1977 struct xsk_buff_pool *xsk_pool,
1978 struct mlx5e_channel **cp)
1980 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1981 struct net_device *netdev = priv->netdev;
1982 struct mlx5e_xsk_param xsk;
1983 struct mlx5e_channel *c;
1988 err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1992 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1997 c->mdev = priv->mdev;
1998 c->tstamp = &priv->tstamp;
2001 c->pdev = mlx5_core_dma_dev(priv->mdev);
2002 c->netdev = priv->netdev;
2003 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey.key);
2004 c->num_tc = params->num_tc;
2005 c->xdp = !!params->xdp_prog;
2006 c->stats = &priv->channel_stats[ix].ch;
2007 c->aff_mask = irq_get_effective_affinity_mask(irq);
2008 c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
2010 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
2012 err = mlx5e_open_queues(c, params, cparam);
2017 mlx5e_build_xsk_param(xsk_pool, &xsk);
2018 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c);
2020 goto err_close_queues;
2028 mlx5e_close_queues(c);
2031 netif_napi_del(&c->napi);
2038 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2042 napi_enable(&c->napi);
2044 for (tc = 0; tc < c->num_tc; tc++)
2045 mlx5e_activate_txqsq(&c->sq[tc]);
2046 mlx5e_activate_icosq(&c->icosq);
2047 mlx5e_activate_icosq(&c->async_icosq);
2048 mlx5e_activate_rq(&c->rq);
2050 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2051 mlx5e_activate_xsk(c);
2054 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2058 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2059 mlx5e_deactivate_xsk(c);
2061 mlx5e_deactivate_rq(&c->rq);
2062 mlx5e_deactivate_icosq(&c->async_icosq);
2063 mlx5e_deactivate_icosq(&c->icosq);
2064 for (tc = 0; tc < c->num_tc; tc++)
2065 mlx5e_deactivate_txqsq(&c->sq[tc]);
2066 mlx5e_qos_deactivate_queues(c);
2068 napi_disable(&c->napi);
2071 static void mlx5e_close_channel(struct mlx5e_channel *c)
2073 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2075 mlx5e_close_queues(c);
2076 mlx5e_qos_close_queues(c);
2077 netif_napi_del(&c->napi);
2082 int mlx5e_open_channels(struct mlx5e_priv *priv,
2083 struct mlx5e_channels *chs)
2085 struct mlx5e_channel_param *cparam;
2089 chs->num = chs->params.num_channels;
2091 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2092 cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2093 if (!chs->c || !cparam)
2096 err = mlx5e_build_channel_param(priv->mdev, &chs->params, priv->q_counter, cparam);
2100 for (i = 0; i < chs->num; i++) {
2101 struct xsk_buff_pool *xsk_pool = NULL;
2103 if (chs->params.xdp_prog)
2104 xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i);
2106 err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]);
2108 goto err_close_channels;
2111 if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) {
2112 err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp);
2114 goto err_close_channels;
2117 err = mlx5e_qos_open_queues(priv, chs);
2121 mlx5e_health_channels_update(priv);
2127 mlx5e_ptp_close(chs->ptp);
2130 for (i--; i >= 0; i--)
2131 mlx5e_close_channel(chs->c[i]);
2140 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2144 for (i = 0; i < chs->num; i++)
2145 mlx5e_activate_channel(chs->c[i]);
2148 mlx5e_ptp_activate_channel(chs->ptp);
2151 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2153 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2158 for (i = 0; i < chs->num; i++) {
2159 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2161 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2163 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2164 * doesn't provide any Fill Ring entries at the setup stage.
2168 return err ? -ETIMEDOUT : 0;
2171 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2176 mlx5e_ptp_deactivate_channel(chs->ptp);
2178 for (i = 0; i < chs->num; i++)
2179 mlx5e_deactivate_channel(chs->c[i]);
2182 void mlx5e_close_channels(struct mlx5e_channels *chs)
2187 mlx5e_ptp_close(chs->ptp);
2190 for (i = 0; i < chs->num; i++)
2191 mlx5e_close_channel(chs->c[i]);
2198 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2200 struct mlx5_core_dev *mdev = priv->mdev;
2207 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2208 in = kvzalloc(inlen, GFP_KERNEL);
2212 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2214 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2215 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2217 for (i = 0; i < sz; i++)
2218 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2220 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2222 rqt->enabled = true;
2228 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2230 rqt->enabled = false;
2231 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2234 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2236 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2239 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2241 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2245 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n)
2250 for (ix = 0; ix < n; ix++) {
2251 err = mlx5e_create_rqt(priv, 1 /*size */, &tirs[ix].rqt);
2253 goto err_destroy_rqts;
2259 mlx5_core_warn(priv->mdev, "create rqts failed, %d\n", err);
2260 for (ix--; ix >= 0; ix--)
2261 mlx5e_destroy_rqt(priv, &tirs[ix].rqt);
2266 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n)
2270 for (i = 0; i < n; i++)
2271 mlx5e_destroy_rqt(priv, &tirs[i].rqt);
2274 static int mlx5e_rx_hash_fn(int hfunc)
2276 return (hfunc == ETH_RSS_HASH_TOP) ?
2277 MLX5_RX_HASH_FN_TOEPLITZ :
2278 MLX5_RX_HASH_FN_INVERTED_XOR8;
2281 int mlx5e_bits_invert(unsigned long a, int size)
2286 for (i = 0; i < size; i++)
2287 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2292 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2293 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2297 for (i = 0; i < sz; i++) {
2303 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2304 ix = mlx5e_bits_invert(i, ilog2(sz));
2306 ix = priv->rss_params.indirection_rqt[ix];
2307 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2311 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2315 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2316 struct mlx5e_redirect_rqt_param rrp)
2318 struct mlx5_core_dev *mdev = priv->mdev;
2324 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2325 in = kvzalloc(inlen, GFP_KERNEL);
2329 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2331 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2332 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2333 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2334 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2340 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2341 struct mlx5e_redirect_rqt_param rrp)
2346 if (ix >= rrp.rss.channels->num)
2347 return priv->drop_rq.rqn;
2349 return rrp.rss.channels->c[ix]->rq.rqn;
2352 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2353 struct mlx5e_redirect_rqt_param rrp,
2354 struct mlx5e_redirect_rqt_param *ptp_rrp)
2359 if (priv->indir_rqt.enabled) {
2361 rqtn = priv->indir_rqt.rqtn;
2362 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2365 for (ix = 0; ix < priv->max_nch; ix++) {
2366 struct mlx5e_redirect_rqt_param direct_rrp = {
2369 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2373 /* Direct RQ Tables */
2374 if (!priv->direct_tir[ix].rqt.enabled)
2377 rqtn = priv->direct_tir[ix].rqt.rqtn;
2378 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2381 rqtn = priv->ptp_tir.rqt.rqtn;
2382 mlx5e_redirect_rqt(priv, rqtn, 1, *ptp_rrp);
2386 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2387 struct mlx5e_channels *chs)
2389 bool rx_ptp_support = priv->profile->rx_ptp_support;
2390 struct mlx5e_redirect_rqt_param *ptp_rrp_p = NULL;
2391 struct mlx5e_redirect_rqt_param rrp = {
2396 .hfunc = priv->rss_params.hfunc,
2400 struct mlx5e_redirect_rqt_param ptp_rrp;
2402 if (rx_ptp_support) {
2405 ptp_rrp.is_rss = false;
2406 ptp_rrp.rqn = mlx5e_ptp_get_rqn(priv->channels.ptp, &ptp_rqn) ?
2407 priv->drop_rq.rqn : ptp_rqn;
2408 ptp_rrp_p = &ptp_rrp;
2410 mlx5e_redirect_rqts(priv, rrp, ptp_rrp_p);
2413 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2415 bool rx_ptp_support = priv->profile->rx_ptp_support;
2416 struct mlx5e_redirect_rqt_param drop_rrp = {
2419 .rqn = priv->drop_rq.rqn,
2423 mlx5e_redirect_rqts(priv, drop_rrp, rx_ptp_support ? &drop_rrp : NULL);
2426 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2427 [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2428 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2429 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2431 [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2432 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2433 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2435 [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2436 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2437 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2439 [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2440 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2441 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2443 [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2445 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2447 [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2449 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2451 [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2453 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2455 [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2457 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2459 [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2461 .rx_hash_fields = MLX5_HASH_IP,
2463 [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2465 .rx_hash_fields = MLX5_HASH_IP,
2469 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2471 return tirc_default_config[tt];
2474 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2476 if (!params->lro_en)
2479 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2481 MLX5_SET(tirc, tirc, lro_enable_mask,
2482 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2483 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2484 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2485 (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2486 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2489 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2490 const struct mlx5e_tirc_config *ttconfig,
2491 void *tirc, bool inner)
2493 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2494 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2496 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2497 if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2498 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2499 rx_hash_toeplitz_key);
2500 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2501 rx_hash_toeplitz_key);
2503 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2504 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2506 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2507 ttconfig->l3_prot_type);
2508 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2509 ttconfig->l4_prot_type);
2510 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2511 ttconfig->rx_hash_fields);
2514 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2515 enum mlx5e_traffic_types tt,
2518 *ttconfig = tirc_default_config[tt];
2519 ttconfig->rx_hash_fields = rx_hash_fields;
2522 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in)
2524 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2525 struct mlx5e_rss_params *rss = &priv->rss_params;
2526 struct mlx5_core_dev *mdev = priv->mdev;
2527 int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2528 struct mlx5e_tirc_config ttconfig;
2531 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2533 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2534 memset(tirc, 0, ctxlen);
2535 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2536 rss->rx_hash_fields[tt]);
2537 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2538 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
2541 /* Verify inner tirs resources allocated */
2542 if (!priv->inner_indir_tir[0].tirn)
2545 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2546 memset(tirc, 0, ctxlen);
2547 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2548 rss->rx_hash_fields[tt]);
2549 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2550 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in);
2554 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2556 struct mlx5_core_dev *mdev = priv->mdev;
2565 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2566 in = kvzalloc(inlen, GFP_KERNEL);
2570 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2571 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2573 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2575 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2576 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
2581 for (ix = 0; ix < priv->max_nch; ix++) {
2582 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn, in);
2593 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_lro);
2595 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2596 struct mlx5e_params *params, u16 mtu)
2598 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2601 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2605 /* Update vport context MTU */
2606 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2610 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2611 struct mlx5e_params *params, u16 *mtu)
2616 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2617 if (err || !hw_mtu) /* fallback to port oper mtu */
2618 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2620 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2623 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2625 struct mlx5e_params *params = &priv->channels.params;
2626 struct net_device *netdev = priv->netdev;
2627 struct mlx5_core_dev *mdev = priv->mdev;
2631 err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2635 mlx5e_query_mtu(mdev, params, &mtu);
2636 if (mtu != params->sw_mtu)
2637 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2638 __func__, mtu, params->sw_mtu);
2640 params->sw_mtu = mtu;
2644 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2646 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2648 struct mlx5e_params *params = &priv->channels.params;
2649 struct net_device *netdev = priv->netdev;
2650 struct mlx5_core_dev *mdev = priv->mdev;
2653 /* MTU range: 68 - hw-specific max */
2654 netdev->min_mtu = ETH_MIN_MTU;
2656 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2657 netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2661 static void mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc)
2665 netdev_reset_tc(netdev);
2670 netdev_set_num_tc(netdev, ntc);
2672 /* Map netdev TCs to offset 0
2673 * We have our own UP to TXQ mapping for QoS
2675 for (tc = 0; tc < ntc; tc++)
2676 netdev_set_tc_queue(netdev, tc, nch, 0);
2679 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv)
2681 int qos_queues, nch, ntc, num_txqs, err;
2683 qos_queues = mlx5e_qos_cur_leaf_nodes(priv);
2685 nch = priv->channels.params.num_channels;
2686 ntc = priv->channels.params.num_tc;
2687 num_txqs = nch * ntc + qos_queues;
2688 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS))
2691 mlx5e_dbg(DRV, priv, "Setting num_txqs %d\n", num_txqs);
2692 err = netif_set_real_num_tx_queues(priv->netdev, num_txqs);
2694 netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2699 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2701 struct net_device *netdev = priv->netdev;
2702 int old_num_txqs, old_ntc;
2703 int num_rxqs, nch, ntc;
2706 old_num_txqs = netdev->real_num_tx_queues;
2707 old_ntc = netdev->num_tc ? : 1;
2709 nch = priv->channels.params.num_channels;
2710 ntc = priv->channels.params.num_tc;
2711 num_rxqs = nch * priv->profile->rq_groups;
2713 mlx5e_netdev_set_tcs(netdev, nch, ntc);
2715 err = mlx5e_update_tx_netdev_queues(priv);
2718 err = netif_set_real_num_rx_queues(netdev, num_rxqs);
2720 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
2727 /* netif_set_real_num_rx_queues could fail only when nch increased. Only
2728 * one of nch and ntc is changed in this function. That means, the call
2729 * to netif_set_real_num_tx_queues below should not fail, because it
2730 * decreases the number of TX queues.
2732 WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2735 mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc);
2739 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2740 struct mlx5e_params *params)
2742 struct mlx5_core_dev *mdev = priv->mdev;
2743 int num_comp_vectors, ix, irq;
2745 num_comp_vectors = mlx5_comp_vectors_count(mdev);
2747 for (ix = 0; ix < params->num_channels; ix++) {
2748 cpumask_clear(priv->scratchpad.cpumask);
2750 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2751 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq));
2753 cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
2756 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
2760 int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2762 u16 count = priv->channels.params.num_channels;
2765 err = mlx5e_update_netdev_queues(priv);
2769 mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
2771 if (!netif_is_rxfh_configured(priv->netdev))
2772 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
2773 MLX5E_INDIR_RQT_SIZE, count);
2778 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
2780 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2782 int i, ch, tc, num_tc;
2784 ch = priv->channels.num;
2785 num_tc = priv->channels.params.num_tc;
2787 for (i = 0; i < ch; i++) {
2788 for (tc = 0; tc < num_tc; tc++) {
2789 struct mlx5e_channel *c = priv->channels.c[i];
2790 struct mlx5e_txqsq *sq = &c->sq[tc];
2792 priv->txq2sq[sq->txq_ix] = sq;
2793 priv->channel_tc2realtxq[i][tc] = i + tc * ch;
2797 if (!priv->channels.ptp)
2800 if (!test_bit(MLX5E_PTP_STATE_TX, priv->channels.ptp->state))
2803 for (tc = 0; tc < num_tc; tc++) {
2804 struct mlx5e_ptp *c = priv->channels.ptp;
2805 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq;
2807 priv->txq2sq[sq->txq_ix] = sq;
2808 priv->port_ptp_tc2realtxq[tc] = priv->num_tc_x_num_ch + tc;
2812 static void mlx5e_update_num_tc_x_num_ch(struct mlx5e_priv *priv)
2814 /* Sync with mlx5e_select_queue. */
2815 WRITE_ONCE(priv->num_tc_x_num_ch,
2816 priv->channels.params.num_tc * priv->channels.num);
2819 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2821 mlx5e_update_num_tc_x_num_ch(priv);
2822 mlx5e_build_txq_maps(priv);
2823 mlx5e_activate_channels(&priv->channels);
2824 mlx5e_qos_activate_queues(priv);
2825 mlx5e_xdp_tx_enable(priv);
2826 netif_tx_start_all_queues(priv->netdev);
2828 if (mlx5e_is_vport_rep(priv))
2829 mlx5e_add_sqs_fwd_rules(priv);
2831 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2832 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2834 mlx5e_xsk_redirect_rqts_to_channels(priv, &priv->channels);
2837 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2839 mlx5e_xsk_redirect_rqts_to_drop(priv, &priv->channels);
2841 mlx5e_redirect_rqts_to_drop(priv);
2843 if (mlx5e_is_vport_rep(priv))
2844 mlx5e_remove_sqs_fwd_rules(priv);
2846 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2847 * polling for inactive tx queues.
2849 netif_tx_stop_all_queues(priv->netdev);
2850 netif_tx_disable(priv->netdev);
2851 mlx5e_xdp_tx_disable(priv);
2852 mlx5e_deactivate_channels(&priv->channels);
2855 static int mlx5e_switch_priv_params(struct mlx5e_priv *priv,
2856 struct mlx5e_params *new_params,
2857 mlx5e_fp_preactivate preactivate,
2860 struct mlx5e_params old_params;
2862 old_params = priv->channels.params;
2863 priv->channels.params = *new_params;
2868 err = preactivate(priv, context);
2870 priv->channels.params = old_params;
2878 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2879 struct mlx5e_channels *new_chs,
2880 mlx5e_fp_preactivate preactivate,
2883 struct net_device *netdev = priv->netdev;
2884 struct mlx5e_channels old_chs;
2888 carrier_ok = netif_carrier_ok(netdev);
2889 netif_carrier_off(netdev);
2891 mlx5e_deactivate_priv_channels(priv);
2893 old_chs = priv->channels;
2894 priv->channels = *new_chs;
2896 /* New channels are ready to roll, call the preactivate hook if needed
2897 * to modify HW settings or update kernel parameters.
2900 err = preactivate(priv, context);
2902 priv->channels = old_chs;
2907 mlx5e_close_channels(&old_chs);
2908 priv->profile->update_rx(priv);
2911 mlx5e_activate_priv_channels(priv);
2913 /* return carrier back if needed */
2915 netif_carrier_on(netdev);
2920 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
2921 struct mlx5e_params *params,
2922 mlx5e_fp_preactivate preactivate,
2923 void *context, bool reset)
2925 struct mlx5e_channels new_chs = {};
2928 reset &= test_bit(MLX5E_STATE_OPENED, &priv->state);
2930 return mlx5e_switch_priv_params(priv, params, preactivate, context);
2932 new_chs.params = *params;
2933 err = mlx5e_open_channels(priv, &new_chs);
2936 err = mlx5e_switch_priv_channels(priv, &new_chs, preactivate, context);
2938 mlx5e_close_channels(&new_chs);
2943 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2945 return mlx5e_safe_switch_params(priv, &priv->channels.params, NULL, NULL, true);
2948 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2950 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
2951 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2954 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev,
2955 enum mlx5_port_status state)
2957 struct mlx5_eswitch *esw = mdev->priv.eswitch;
2958 int vport_admin_state;
2960 mlx5_set_port_admin_status(mdev, state);
2962 if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS ||
2963 !MLX5_CAP_GEN(mdev, uplink_follow))
2966 if (state == MLX5_PORT_UP)
2967 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO;
2969 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2971 mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state);
2974 int mlx5e_open_locked(struct net_device *netdev)
2976 struct mlx5e_priv *priv = netdev_priv(netdev);
2979 set_bit(MLX5E_STATE_OPENED, &priv->state);
2981 err = mlx5e_open_channels(priv, &priv->channels);
2983 goto err_clear_state_opened_flag;
2985 priv->profile->update_rx(priv);
2986 mlx5e_activate_priv_channels(priv);
2987 mlx5e_apply_traps(priv, true);
2988 if (priv->profile->update_carrier)
2989 priv->profile->update_carrier(priv);
2991 mlx5e_queue_update_stats(priv);
2994 err_clear_state_opened_flag:
2995 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2999 int mlx5e_open(struct net_device *netdev)
3001 struct mlx5e_priv *priv = netdev_priv(netdev);
3004 mutex_lock(&priv->state_lock);
3005 err = mlx5e_open_locked(netdev);
3007 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP);
3008 mutex_unlock(&priv->state_lock);
3013 int mlx5e_close_locked(struct net_device *netdev)
3015 struct mlx5e_priv *priv = netdev_priv(netdev);
3017 /* May already be CLOSED in case a previous configuration operation
3018 * (e.g RX/TX queue size change) that involves close&open failed.
3020 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3023 mlx5e_apply_traps(priv, false);
3024 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3026 netif_carrier_off(priv->netdev);
3027 mlx5e_deactivate_priv_channels(priv);
3028 mlx5e_close_channels(&priv->channels);
3033 int mlx5e_close(struct net_device *netdev)
3035 struct mlx5e_priv *priv = netdev_priv(netdev);
3038 if (!netif_device_present(netdev))
3041 mutex_lock(&priv->state_lock);
3042 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN);
3043 err = mlx5e_close_locked(netdev);
3044 mutex_unlock(&priv->state_lock);
3049 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq)
3051 mlx5_wq_destroy(&rq->wq_ctrl);
3054 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3055 struct mlx5e_rq *rq,
3056 struct mlx5e_rq_param *param)
3058 void *rqc = param->rqc;
3059 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3062 param->wq.db_numa_node = param->wq.buf_numa_node;
3064 err = mlx5_wq_cyc_create(mdev, ¶m->wq, rqc_wq, &rq->wqe.wq,
3069 /* Mark as unused given "Drop-RQ" packets never reach XDP */
3070 xdp_rxq_info_unused(&rq->xdp_rxq);
3077 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv,
3078 struct mlx5e_cq *cq,
3079 struct mlx5e_cq_param *param)
3081 struct mlx5_core_dev *mdev = priv->mdev;
3083 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
3084 param->wq.db_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
3086 return mlx5e_alloc_cq_common(priv, param, cq);
3089 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3090 struct mlx5e_rq *drop_rq)
3092 struct mlx5_core_dev *mdev = priv->mdev;
3093 struct mlx5e_cq_param cq_param = {};
3094 struct mlx5e_rq_param rq_param = {};
3095 struct mlx5e_cq *cq = &drop_rq->cq;
3098 mlx5e_build_drop_rq_param(mdev, priv->drop_rq_q_counter, &rq_param);
3100 err = mlx5e_alloc_drop_cq(priv, cq, &cq_param);
3104 err = mlx5e_create_cq(cq, &cq_param);
3108 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3110 goto err_destroy_cq;
3112 err = mlx5e_create_rq(drop_rq, &rq_param);
3116 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3118 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3123 mlx5e_free_drop_rq(drop_rq);
3126 mlx5e_destroy_cq(cq);
3134 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3136 mlx5e_destroy_rq(drop_rq);
3137 mlx5e_free_drop_rq(drop_rq);
3138 mlx5e_destroy_cq(&drop_rq->cq);
3139 mlx5e_free_cq(&drop_rq->cq);
3142 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3144 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3146 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn);
3148 if (MLX5_GET(tisc, tisc, tls_en))
3149 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.hw_objs.pdn);
3151 if (mlx5_lag_is_lacp_owner(mdev))
3152 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3154 return mlx5_core_create_tis(mdev, in, tisn);
3157 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3159 mlx5_core_destroy_tis(mdev, tisn);
3162 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3166 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3167 for (tc = 0; tc < priv->profile->max_tc; tc++)
3168 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3171 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3173 return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3176 int mlx5e_create_tises(struct mlx5e_priv *priv)
3181 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3182 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3183 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3186 tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3188 MLX5_SET(tisc, tisc, prio, tc << 1);
3190 if (mlx5e_lag_should_assign_affinity(priv->mdev))
3191 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3193 err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3195 goto err_close_tises;
3202 for (; i >= 0; i--) {
3203 for (tc--; tc >= 0; tc--)
3204 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3205 tc = priv->profile->max_tc;
3211 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3213 mlx5e_destroy_tises(priv);
3216 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
3217 u32 rqtn, u32 *tirc)
3219 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.hw_objs.td.tdn);
3220 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3221 MLX5_SET(tirc, tirc, indirect_table, rqtn);
3222 MLX5_SET(tirc, tirc, tunneled_offload_en,
3223 priv->channels.params.tunneled_offload_en);
3225 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3228 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3229 enum mlx5e_traffic_types tt,
3232 mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3233 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3234 &tirc_default_config[tt], tirc, false);
3237 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3239 mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc);
3240 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3243 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
3244 enum mlx5e_traffic_types tt,
3247 mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3248 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3249 &tirc_default_config[tt], tirc, true);
3252 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3254 struct mlx5e_tir *tir;
3262 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3263 in = kvzalloc(inlen, GFP_KERNEL);
3267 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3268 memset(in, 0, inlen);
3269 tir = &priv->indir_tir[tt];
3270 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3271 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3272 err = mlx5e_create_tir(priv->mdev, tir, in);
3274 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3275 goto err_destroy_inner_tirs;
3279 if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3282 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3283 memset(in, 0, inlen);
3284 tir = &priv->inner_indir_tir[i];
3285 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3286 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3287 err = mlx5e_create_tir(priv->mdev, tir, in);
3289 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3290 goto err_destroy_inner_tirs;
3299 err_destroy_inner_tirs:
3300 for (i--; i >= 0; i--)
3301 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3303 for (tt--; tt >= 0; tt--)
3304 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3311 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n)
3313 struct mlx5e_tir *tir;
3320 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3321 in = kvzalloc(inlen, GFP_KERNEL);
3325 for (ix = 0; ix < n; ix++) {
3326 memset(in, 0, inlen);
3328 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3329 mlx5e_build_direct_tir_ctx(priv, tir->rqt.rqtn, tirc);
3330 err = mlx5e_create_tir(priv->mdev, tir, in);
3332 goto err_destroy_ch_tirs;
3337 err_destroy_ch_tirs:
3338 mlx5_core_warn(priv->mdev, "create tirs failed, %d\n", err);
3339 for (ix--; ix >= 0; ix--)
3340 mlx5e_destroy_tir(priv->mdev, &tirs[ix]);
3348 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3352 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3353 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3355 /* Verify inner tirs resources allocated */
3356 if (!priv->inner_indir_tir[0].tirn)
3359 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3360 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3363 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n)
3367 for (i = 0; i < n; i++)
3368 mlx5e_destroy_tir(priv->mdev, &tirs[i]);
3371 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3376 for (i = 0; i < chs->num; i++) {
3377 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3385 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3390 for (i = 0; i < chs->num; i++) {
3391 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3399 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3400 struct tc_mqprio_qopt *mqprio)
3402 struct mlx5e_params new_params;
3403 u8 tc = mqprio->num_tc;
3406 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3408 if (tc && tc != MLX5E_MAX_NUM_TC)
3411 mutex_lock(&priv->state_lock);
3413 /* MQPRIO is another toplevel qdisc that can't be attached
3414 * simultaneously with the offloaded HTB.
3416 if (WARN_ON(priv->htb.maj_id)) {
3421 new_params = priv->channels.params;
3422 new_params.num_tc = tc ? tc : 1;
3424 err = mlx5e_safe_switch_params(priv, &new_params,
3425 mlx5e_num_channels_changed_ctx, NULL, true);
3428 priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3429 priv->channels.params.num_tc);
3430 mutex_unlock(&priv->state_lock);
3434 static int mlx5e_setup_tc_htb(struct mlx5e_priv *priv, struct tc_htb_qopt_offload *htb)
3438 switch (htb->command) {
3440 return mlx5e_htb_root_add(priv, htb->parent_classid, htb->classid,
3442 case TC_HTB_DESTROY:
3443 return mlx5e_htb_root_del(priv);
3444 case TC_HTB_LEAF_ALLOC_QUEUE:
3445 res = mlx5e_htb_leaf_alloc_queue(priv, htb->classid, htb->parent_classid,
3446 htb->rate, htb->ceil, htb->extack);
3451 case TC_HTB_LEAF_TO_INNER:
3452 return mlx5e_htb_leaf_to_inner(priv, htb->parent_classid, htb->classid,
3453 htb->rate, htb->ceil, htb->extack);
3454 case TC_HTB_LEAF_DEL:
3455 return mlx5e_htb_leaf_del(priv, htb->classid, &htb->moved_qid, &htb->qid,
3457 case TC_HTB_LEAF_DEL_LAST:
3458 case TC_HTB_LEAF_DEL_LAST_FORCE:
3459 return mlx5e_htb_leaf_del_last(priv, htb->classid,
3460 htb->command == TC_HTB_LEAF_DEL_LAST_FORCE,
3462 case TC_HTB_NODE_MODIFY:
3463 return mlx5e_htb_node_modify(priv, htb->classid, htb->rate, htb->ceil,
3465 case TC_HTB_LEAF_QUERY_QUEUE:
3466 res = mlx5e_get_txq_by_classid(priv, htb->classid);
3476 static LIST_HEAD(mlx5e_block_cb_list);
3478 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3481 struct mlx5e_priv *priv = netdev_priv(dev);
3482 bool tc_unbind = false;
3485 if (type == TC_SETUP_BLOCK &&
3486 ((struct flow_block_offload *)type_data)->command == FLOW_BLOCK_UNBIND)
3489 if (!netif_device_present(dev) && !tc_unbind)
3493 case TC_SETUP_BLOCK: {
3494 struct flow_block_offload *f = type_data;
3496 f->unlocked_driver_cb = true;
3497 return flow_block_cb_setup_simple(type_data,
3498 &mlx5e_block_cb_list,
3499 mlx5e_setup_tc_block_cb,
3502 case TC_SETUP_QDISC_MQPRIO:
3503 return mlx5e_setup_tc_mqprio(priv, type_data);
3504 case TC_SETUP_QDISC_HTB:
3505 mutex_lock(&priv->state_lock);
3506 err = mlx5e_setup_tc_htb(priv, type_data);
3507 mutex_unlock(&priv->state_lock);
3514 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3518 for (i = 0; i < priv->max_nch; i++) {
3519 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3520 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3521 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3524 s->rx_packets += rq_stats->packets + xskrq_stats->packets;
3525 s->rx_bytes += rq_stats->bytes + xskrq_stats->bytes;
3526 s->multicast += rq_stats->mcast_packets + xskrq_stats->mcast_packets;
3528 for (j = 0; j < priv->max_opened_tc; j++) {
3529 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3531 s->tx_packets += sq_stats->packets;
3532 s->tx_bytes += sq_stats->bytes;
3533 s->tx_dropped += sq_stats->dropped;
3536 if (priv->tx_ptp_opened) {
3537 for (i = 0; i < priv->max_opened_tc; i++) {
3538 struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[i];
3540 s->tx_packets += sq_stats->packets;
3541 s->tx_bytes += sq_stats->bytes;
3542 s->tx_dropped += sq_stats->dropped;
3545 if (priv->rx_ptp_opened) {
3546 struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq;
3548 s->rx_packets += rq_stats->packets;
3549 s->rx_bytes += rq_stats->bytes;
3550 s->multicast += rq_stats->mcast_packets;
3555 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3557 struct mlx5e_priv *priv = netdev_priv(dev);
3558 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3560 if (!netif_device_present(dev))
3563 /* In switchdev mode, monitor counters doesn't monitor
3564 * rx/tx stats of 802_3. The update stats mechanism
3565 * should keep the 802_3 layout counters updated
3567 if (!mlx5e_monitor_counter_supported(priv) ||
3568 mlx5e_is_uplink_rep(priv)) {
3569 /* update HW stats in background for next time */
3570 mlx5e_queue_update_stats(priv);
3573 if (mlx5e_is_uplink_rep(priv)) {
3574 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3576 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3577 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3578 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3579 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3581 /* vport multicast also counts packets that are dropped due to steering
3582 * or rx out of buffer
3584 stats->multicast = VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3586 mlx5e_fold_sw_stats64(priv, stats);
3589 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3591 stats->rx_length_errors =
3592 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3593 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3594 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3595 stats->rx_crc_errors =
3596 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3597 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3598 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3599 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3600 stats->rx_frame_errors;
3601 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3604 static void mlx5e_nic_set_rx_mode(struct mlx5e_priv *priv)
3606 if (mlx5e_is_uplink_rep(priv))
3607 return; /* no rx mode for uplink rep */
3609 queue_work(priv->wq, &priv->set_rx_mode_work);
3612 static void mlx5e_set_rx_mode(struct net_device *dev)
3614 struct mlx5e_priv *priv = netdev_priv(dev);
3616 mlx5e_nic_set_rx_mode(priv);
3619 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3621 struct mlx5e_priv *priv = netdev_priv(netdev);
3622 struct sockaddr *saddr = addr;
3624 if (!is_valid_ether_addr(saddr->sa_data))
3625 return -EADDRNOTAVAIL;
3627 netif_addr_lock_bh(netdev);
3628 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3629 netif_addr_unlock_bh(netdev);
3631 mlx5e_nic_set_rx_mode(priv);
3636 #define MLX5E_SET_FEATURE(features, feature, enable) \
3639 *features |= feature; \
3641 *features &= ~feature; \
3644 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3646 static int set_feature_lro(struct net_device *netdev, bool enable)
3648 struct mlx5e_priv *priv = netdev_priv(netdev);
3649 struct mlx5_core_dev *mdev = priv->mdev;
3650 struct mlx5e_params *cur_params;
3651 struct mlx5e_params new_params;
3655 mutex_lock(&priv->state_lock);
3657 if (enable && priv->xsk.refcnt) {
3658 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n",
3664 cur_params = &priv->channels.params;
3665 if (enable && !MLX5E_GET_PFLAG(cur_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3666 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3671 new_params = *cur_params;
3672 new_params.lro_en = enable;
3674 if (cur_params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3675 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) ==
3676 mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_params, NULL))
3680 err = mlx5e_safe_switch_params(priv, &new_params,
3681 mlx5e_modify_tirs_lro_ctx, NULL, reset);
3683 mutex_unlock(&priv->state_lock);
3687 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3689 struct mlx5e_priv *priv = netdev_priv(netdev);
3692 mlx5e_enable_cvlan_filter(priv);
3694 mlx5e_disable_cvlan_filter(priv);
3699 static int set_feature_hw_tc(struct net_device *netdev, bool enable)
3701 struct mlx5e_priv *priv = netdev_priv(netdev);
3703 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3704 if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3706 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3711 if (!enable && priv->htb.maj_id) {
3712 netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n");
3719 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3721 struct mlx5e_priv *priv = netdev_priv(netdev);
3722 struct mlx5_core_dev *mdev = priv->mdev;
3724 return mlx5_set_port_fcs(mdev, !enable);
3727 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3729 struct mlx5e_priv *priv = netdev_priv(netdev);
3732 mutex_lock(&priv->state_lock);
3734 priv->channels.params.scatter_fcs_en = enable;
3735 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3737 priv->channels.params.scatter_fcs_en = !enable;
3739 mutex_unlock(&priv->state_lock);
3744 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3746 struct mlx5e_priv *priv = netdev_priv(netdev);
3749 mutex_lock(&priv->state_lock);
3751 priv->channels.params.vlan_strip_disable = !enable;
3752 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3755 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3757 priv->channels.params.vlan_strip_disable = enable;
3760 mutex_unlock(&priv->state_lock);
3765 #ifdef CONFIG_MLX5_EN_ARFS
3766 static int set_feature_arfs(struct net_device *netdev, bool enable)
3768 struct mlx5e_priv *priv = netdev_priv(netdev);
3772 err = mlx5e_arfs_enable(priv);
3774 err = mlx5e_arfs_disable(priv);
3780 static int mlx5e_handle_feature(struct net_device *netdev,
3781 netdev_features_t *features,
3782 netdev_features_t wanted_features,
3783 netdev_features_t feature,
3784 mlx5e_feature_handler feature_handler)
3786 netdev_features_t changes = wanted_features ^ netdev->features;
3787 bool enable = !!(wanted_features & feature);
3790 if (!(changes & feature))
3793 err = feature_handler(netdev, enable);
3795 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3796 enable ? "Enable" : "Disable", &feature, err);
3800 MLX5E_SET_FEATURE(features, feature, enable);
3804 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3806 netdev_features_t oper_features = netdev->features;
3809 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3810 mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3812 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3813 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3814 set_feature_cvlan_filter);
3815 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc);
3816 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3817 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3818 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3819 #ifdef CONFIG_MLX5_EN_ARFS
3820 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3822 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx);
3825 netdev->features = oper_features;
3832 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3833 netdev_features_t features)
3835 struct mlx5e_priv *priv = netdev_priv(netdev);
3836 struct mlx5e_params *params;
3838 mutex_lock(&priv->state_lock);
3839 params = &priv->channels.params;
3840 if (!priv->fs.vlan ||
3841 !bitmap_empty(mlx5e_vlan_get_active_svlans(priv->fs.vlan), VLAN_N_VID)) {
3842 /* HW strips the outer C-tag header, this is a problem
3843 * for S-tag traffic.
3845 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3846 if (!params->vlan_strip_disable)
3847 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3850 if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3851 if (features & NETIF_F_LRO) {
3852 netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3853 features &= ~NETIF_F_LRO;
3857 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3858 features &= ~NETIF_F_RXHASH;
3859 if (netdev->features & NETIF_F_RXHASH)
3860 netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3863 if (mlx5e_is_uplink_rep(priv)) {
3864 features &= ~NETIF_F_HW_TLS_RX;
3865 if (netdev->features & NETIF_F_HW_TLS_RX)
3866 netdev_warn(netdev, "Disabling hw_tls_rx, not supported in switchdev mode\n");
3868 features &= ~NETIF_F_HW_TLS_TX;
3869 if (netdev->features & NETIF_F_HW_TLS_TX)
3870 netdev_warn(netdev, "Disabling hw_tls_tx, not supported in switchdev mode\n");
3873 mutex_unlock(&priv->state_lock);
3878 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3879 struct mlx5e_channels *chs,
3880 struct mlx5e_params *new_params,
3881 struct mlx5_core_dev *mdev)
3885 for (ix = 0; ix < chs->params.num_channels; ix++) {
3886 struct xsk_buff_pool *xsk_pool =
3887 mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix);
3888 struct mlx5e_xsk_param xsk;
3893 mlx5e_build_xsk_param(xsk_pool, &xsk);
3895 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3896 u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3897 int max_mtu_frame, max_mtu_page, max_mtu;
3899 /* Two criteria must be met:
3900 * 1. HW MTU + all headrooms <= XSK frame size.
3901 * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3903 max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3904 max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3905 max_mtu = min(max_mtu_frame, max_mtu_page);
3907 netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u. Try MTU <= %d\n",
3908 new_params->sw_mtu, ix, max_mtu);
3916 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3917 mlx5e_fp_preactivate preactivate)
3919 struct mlx5e_priv *priv = netdev_priv(netdev);
3920 struct mlx5e_params new_params;
3921 struct mlx5e_params *params;
3925 mutex_lock(&priv->state_lock);
3927 params = &priv->channels.params;
3929 new_params = *params;
3930 new_params.sw_mtu = new_mtu;
3931 err = mlx5e_validate_params(priv->mdev, &new_params);
3935 if (params->xdp_prog &&
3936 !mlx5e_rx_is_linear_skb(&new_params, NULL)) {
3937 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3938 new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3943 if (priv->xsk.refcnt &&
3944 !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3945 &new_params, priv->mdev)) {
3953 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3954 bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, params, NULL);
3955 bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3957 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3958 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_params, NULL);
3960 /* Always reset in linear mode - hw_mtu is used in data path.
3961 * Check that the mode was non-linear and didn't change.
3962 * If XSK is active, XSK RQs are linear.
3964 if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt &&
3969 err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, reset);
3972 netdev->mtu = params->sw_mtu;
3973 mutex_unlock(&priv->state_lock);
3977 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3979 return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
3982 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx)
3984 bool set = *(bool *)ctx;
3986 return mlx5e_ptp_rx_manage_fs(priv, set);
3989 static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter)
3991 bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
3995 /* Reset CQE compression to Admin default */
3996 return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def);
3998 if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4001 /* Disable CQE compression */
4002 netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
4003 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
4005 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
4010 static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx)
4012 struct mlx5e_params new_params;
4014 if (ptp_rx == priv->channels.params.ptp_rx)
4017 new_params = priv->channels.params;
4018 new_params.ptp_rx = ptp_rx;
4019 return mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
4020 &new_params.ptp_rx, true);
4023 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
4025 struct hwtstamp_config config;
4026 bool rx_cqe_compress_def;
4030 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
4031 (mlx5_clock_get_ptp_index(priv->mdev) == -1))
4034 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4037 /* TX HW timestamp */
4038 switch (config.tx_type) {
4039 case HWTSTAMP_TX_OFF:
4040 case HWTSTAMP_TX_ON:
4046 mutex_lock(&priv->state_lock);
4047 rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4049 /* RX HW timestamp */
4050 switch (config.rx_filter) {
4051 case HWTSTAMP_FILTER_NONE:
4054 case HWTSTAMP_FILTER_ALL:
4055 case HWTSTAMP_FILTER_SOME:
4056 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4057 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4058 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4059 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4060 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4061 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4062 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4063 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4064 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4065 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4066 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4067 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4068 case HWTSTAMP_FILTER_NTP_ALL:
4069 config.rx_filter = HWTSTAMP_FILTER_ALL;
4070 /* ptp_rx is set if both HW TS is set and CQE
4071 * compression is set
4073 ptp_rx = rx_cqe_compress_def;
4080 if (!priv->profile->rx_ptp_support)
4081 err = mlx5e_hwstamp_config_no_ptp_rx(priv,
4082 config.rx_filter != HWTSTAMP_FILTER_NONE);
4084 err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx);
4088 memcpy(&priv->tstamp, &config, sizeof(config));
4089 mutex_unlock(&priv->state_lock);
4091 /* might need to fix some features */
4092 netdev_update_features(priv->netdev);
4094 return copy_to_user(ifr->ifr_data, &config,
4095 sizeof(config)) ? -EFAULT : 0;
4097 mutex_unlock(&priv->state_lock);
4101 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4103 struct hwtstamp_config *cfg = &priv->tstamp;
4105 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4108 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4111 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4113 struct mlx5e_priv *priv = netdev_priv(dev);
4117 return mlx5e_hwstamp_set(priv, ifr);
4119 return mlx5e_hwstamp_get(priv, ifr);
4125 #ifdef CONFIG_MLX5_ESWITCH
4126 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4128 struct mlx5e_priv *priv = netdev_priv(dev);
4129 struct mlx5_core_dev *mdev = priv->mdev;
4131 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4134 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4137 struct mlx5e_priv *priv = netdev_priv(dev);
4138 struct mlx5_core_dev *mdev = priv->mdev;
4140 if (vlan_proto != htons(ETH_P_8021Q))
4141 return -EPROTONOSUPPORT;
4143 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4147 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4149 struct mlx5e_priv *priv = netdev_priv(dev);
4150 struct mlx5_core_dev *mdev = priv->mdev;
4152 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4155 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4157 struct mlx5e_priv *priv = netdev_priv(dev);
4158 struct mlx5_core_dev *mdev = priv->mdev;
4160 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4163 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4166 struct mlx5e_priv *priv = netdev_priv(dev);
4167 struct mlx5_core_dev *mdev = priv->mdev;
4169 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4170 max_tx_rate, min_tx_rate);
4173 static int mlx5_vport_link2ifla(u8 esw_link)
4176 case MLX5_VPORT_ADMIN_STATE_DOWN:
4177 return IFLA_VF_LINK_STATE_DISABLE;
4178 case MLX5_VPORT_ADMIN_STATE_UP:
4179 return IFLA_VF_LINK_STATE_ENABLE;
4181 return IFLA_VF_LINK_STATE_AUTO;
4184 static int mlx5_ifla_link2vport(u8 ifla_link)
4186 switch (ifla_link) {
4187 case IFLA_VF_LINK_STATE_DISABLE:
4188 return MLX5_VPORT_ADMIN_STATE_DOWN;
4189 case IFLA_VF_LINK_STATE_ENABLE:
4190 return MLX5_VPORT_ADMIN_STATE_UP;
4192 return MLX5_VPORT_ADMIN_STATE_AUTO;
4195 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4198 struct mlx5e_priv *priv = netdev_priv(dev);
4199 struct mlx5_core_dev *mdev = priv->mdev;
4201 if (mlx5e_is_uplink_rep(priv))
4204 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4205 mlx5_ifla_link2vport(link_state));
4208 int mlx5e_get_vf_config(struct net_device *dev,
4209 int vf, struct ifla_vf_info *ivi)
4211 struct mlx5e_priv *priv = netdev_priv(dev);
4212 struct mlx5_core_dev *mdev = priv->mdev;
4215 if (!netif_device_present(dev))
4218 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4221 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4225 int mlx5e_get_vf_stats(struct net_device *dev,
4226 int vf, struct ifla_vf_stats *vf_stats)
4228 struct mlx5e_priv *priv = netdev_priv(dev);
4229 struct mlx5_core_dev *mdev = priv->mdev;
4231 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4236 mlx5e_has_offload_stats(const struct net_device *dev, int attr_id)
4238 struct mlx5e_priv *priv = netdev_priv(dev);
4240 if (!netif_device_present(dev))
4243 if (!mlx5e_is_uplink_rep(priv))
4246 return mlx5e_rep_has_offload_stats(dev, attr_id);
4250 mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
4253 struct mlx5e_priv *priv = netdev_priv(dev);
4255 if (!mlx5e_is_uplink_rep(priv))
4258 return mlx5e_rep_get_offload_stats(attr_id, dev, sp);
4262 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type)
4264 switch (proto_type) {
4266 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre);
4269 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) ||
4270 MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx));
4276 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev,
4277 struct sk_buff *skb)
4279 switch (skb->inner_protocol) {
4280 case htons(ETH_P_IP):
4281 case htons(ETH_P_IPV6):
4282 case htons(ETH_P_TEB):
4284 case htons(ETH_P_MPLS_UC):
4285 case htons(ETH_P_MPLS_MC):
4286 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre);
4291 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4292 struct sk_buff *skb,
4293 netdev_features_t features)
4295 unsigned int offset = 0;
4296 struct udphdr *udph;
4300 switch (vlan_get_protocol(skb)) {
4301 case htons(ETH_P_IP):
4302 proto = ip_hdr(skb)->protocol;
4304 case htons(ETH_P_IPV6):
4305 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4313 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb))
4318 if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP))
4322 udph = udp_hdr(skb);
4323 port = be16_to_cpu(udph->dest);
4325 /* Verify if UDP port is being offloaded by HW */
4326 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4329 #if IS_ENABLED(CONFIG_GENEVE)
4330 /* Support Geneve offload for default UDP port */
4331 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4335 #ifdef CONFIG_MLX5_EN_IPSEC
4337 return mlx5e_ipsec_feature_check(skb, features);
4342 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4343 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4346 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4347 struct net_device *netdev,
4348 netdev_features_t features)
4350 struct mlx5e_priv *priv = netdev_priv(netdev);
4352 features = vlan_features_check(skb, features);
4353 features = vxlan_features_check(skb, features);
4355 /* Validate if the tunneled packet is being offloaded by HW */
4356 if (skb->encapsulation &&
4357 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4358 return mlx5e_tunnel_features_check(priv, skb, features);
4363 static void mlx5e_tx_timeout_work(struct work_struct *work)
4365 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4367 struct net_device *netdev = priv->netdev;
4371 mutex_lock(&priv->state_lock);
4373 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4376 for (i = 0; i < netdev->real_num_tx_queues; i++) {
4377 struct netdev_queue *dev_queue =
4378 netdev_get_tx_queue(netdev, i);
4379 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4381 if (!netif_xmit_stopped(dev_queue))
4384 if (mlx5e_reporter_tx_timeout(sq))
4385 /* break if tried to reopened channels */
4390 mutex_unlock(&priv->state_lock);
4394 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4396 struct mlx5e_priv *priv = netdev_priv(dev);
4398 netdev_err(dev, "TX timeout detected\n");
4399 queue_work(priv->wq, &priv->tx_timeout_work);
4402 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4404 struct net_device *netdev = priv->netdev;
4405 struct mlx5e_params new_params;
4407 if (priv->channels.params.lro_en) {
4408 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4412 if (mlx5_fpga_is_ipsec_device(priv->mdev)) {
4414 "XDP is not available on Innova cards with IPsec support\n");
4418 new_params = priv->channels.params;
4419 new_params.xdp_prog = prog;
4421 /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4424 if (!mlx5e_rx_is_linear_skb(&new_params, NULL)) {
4425 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4427 mlx5e_xdp_max_mtu(&new_params, NULL));
4434 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog)
4436 struct bpf_prog *old_prog;
4438 old_prog = rcu_replace_pointer(rq->xdp_prog, prog,
4439 lockdep_is_held(&rq->priv->state_lock));
4441 bpf_prog_put(old_prog);
4444 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4446 struct mlx5e_priv *priv = netdev_priv(netdev);
4447 struct mlx5e_params new_params;
4448 struct bpf_prog *old_prog;
4453 mutex_lock(&priv->state_lock);
4456 err = mlx5e_xdp_allowed(priv, prog);
4461 /* no need for full reset when exchanging programs */
4462 reset = (!priv->channels.params.xdp_prog || !prog);
4464 new_params = priv->channels.params;
4465 new_params.xdp_prog = prog;
4467 mlx5e_set_rq_type(priv->mdev, &new_params);
4468 old_prog = priv->channels.params.xdp_prog;
4470 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
4475 bpf_prog_put(old_prog);
4477 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4480 /* exchanging programs w/o reset, we update ref counts on behalf
4481 * of the channels RQs here.
4483 bpf_prog_add(prog, priv->channels.num);
4484 for (i = 0; i < priv->channels.num; i++) {
4485 struct mlx5e_channel *c = priv->channels.c[i];
4487 mlx5e_rq_replace_xdp_prog(&c->rq, prog);
4488 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) {
4490 mlx5e_rq_replace_xdp_prog(&c->xskrq, prog);
4495 mutex_unlock(&priv->state_lock);
4499 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4501 switch (xdp->command) {
4502 case XDP_SETUP_PROG:
4503 return mlx5e_xdp_set(dev, xdp->prog);
4504 case XDP_SETUP_XSK_POOL:
4505 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool,
4512 #ifdef CONFIG_MLX5_ESWITCH
4513 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4514 struct net_device *dev, u32 filter_mask,
4517 struct mlx5e_priv *priv = netdev_priv(dev);
4518 struct mlx5_core_dev *mdev = priv->mdev;
4522 err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4525 mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4526 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4528 0, 0, nlflags, filter_mask, NULL);
4531 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4532 u16 flags, struct netlink_ext_ack *extack)
4534 struct mlx5e_priv *priv = netdev_priv(dev);
4535 struct mlx5_core_dev *mdev = priv->mdev;
4536 struct nlattr *attr, *br_spec;
4537 u16 mode = BRIDGE_MODE_UNDEF;
4541 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4545 nla_for_each_nested(attr, br_spec, rem) {
4546 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4549 if (nla_len(attr) < sizeof(mode))
4552 mode = nla_get_u16(attr);
4553 if (mode > BRIDGE_MODE_VEPA)
4559 if (mode == BRIDGE_MODE_UNDEF)
4562 setting = (mode == BRIDGE_MODE_VEPA) ? 1 : 0;
4563 return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4567 const struct net_device_ops mlx5e_netdev_ops = {
4568 .ndo_open = mlx5e_open,
4569 .ndo_stop = mlx5e_close,
4570 .ndo_start_xmit = mlx5e_xmit,
4571 .ndo_setup_tc = mlx5e_setup_tc,
4572 .ndo_select_queue = mlx5e_select_queue,
4573 .ndo_get_stats64 = mlx5e_get_stats,
4574 .ndo_set_rx_mode = mlx5e_set_rx_mode,
4575 .ndo_set_mac_address = mlx5e_set_mac,
4576 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
4577 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
4578 .ndo_set_features = mlx5e_set_features,
4579 .ndo_fix_features = mlx5e_fix_features,
4580 .ndo_change_mtu = mlx5e_change_nic_mtu,
4581 .ndo_do_ioctl = mlx5e_ioctl,
4582 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
4583 .ndo_features_check = mlx5e_features_check,
4584 .ndo_tx_timeout = mlx5e_tx_timeout,
4585 .ndo_bpf = mlx5e_xdp,
4586 .ndo_xdp_xmit = mlx5e_xdp_xmit,
4587 .ndo_xsk_wakeup = mlx5e_xsk_wakeup,
4588 #ifdef CONFIG_MLX5_EN_ARFS
4589 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
4591 #ifdef CONFIG_MLX5_ESWITCH
4592 .ndo_bridge_setlink = mlx5e_bridge_setlink,
4593 .ndo_bridge_getlink = mlx5e_bridge_getlink,
4595 /* SRIOV E-Switch NDOs */
4596 .ndo_set_vf_mac = mlx5e_set_vf_mac,
4597 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
4598 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
4599 .ndo_set_vf_trust = mlx5e_set_vf_trust,
4600 .ndo_set_vf_rate = mlx5e_set_vf_rate,
4601 .ndo_get_vf_config = mlx5e_get_vf_config,
4602 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
4603 .ndo_get_vf_stats = mlx5e_get_vf_stats,
4604 .ndo_has_offload_stats = mlx5e_has_offload_stats,
4605 .ndo_get_offload_stats = mlx5e_get_offload_stats,
4607 .ndo_get_devlink_port = mlx5e_get_devlink_port,
4610 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4615 for (i = 0; i < len; i++)
4616 indirection_rqt[i] = i % num_channels;
4619 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4623 /* The supported periods are organized in ascending order */
4624 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4625 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4628 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4631 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4634 enum mlx5e_traffic_types tt;
4636 rss_params->hfunc = ETH_RSS_HASH_TOP;
4637 netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4638 sizeof(rss_params->toeplitz_hash_key));
4639 mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4640 MLX5E_INDIR_RQT_SIZE, num_channels);
4641 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4642 rss_params->rx_hash_fields[tt] =
4643 tirc_default_config[tt].rx_hash_fields;
4646 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu)
4648 struct mlx5e_rss_params *rss_params = &priv->rss_params;
4649 struct mlx5e_params *params = &priv->channels.params;
4650 struct mlx5_core_dev *mdev = priv->mdev;
4651 u8 rx_cq_period_mode;
4653 priv->max_nch = mlx5e_calc_max_nch(priv, priv->profile);
4655 params->sw_mtu = mtu;
4656 params->hard_mtu = MLX5E_ETH_HARD_MTU;
4657 params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
4661 /* Set an initial non-zero value, so that mlx5e_select_queue won't
4662 * divide by zero if called before first activating channels.
4664 priv->num_tc_x_num_ch = params->num_channels * params->num_tc;
4667 params->log_sq_size = is_kdump_kernel() ?
4668 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4669 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4670 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4673 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4675 /* set CQE compression */
4676 params->rx_cqe_compress_def = false;
4677 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4678 MLX5_CAP_GEN(mdev, vport_group_manager))
4679 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4681 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4682 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4685 mlx5e_build_rq_params(mdev, params);
4688 if (MLX5_CAP_ETH(mdev, lro_cap) &&
4689 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4690 /* No XSK params: checking the availability of striding RQ in general. */
4691 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4692 params->lro_en = !slow_pci_heuristic(mdev);
4694 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4696 /* CQ moderation params */
4697 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4698 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4699 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4700 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4701 params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4702 mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4703 mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4706 mlx5_query_min_inline(mdev, ¶ms->tx_min_inline_mode);
4709 mlx5e_build_rss_params(rss_params, params->num_channels);
4710 params->tunneled_offload_en =
4711 mlx5e_tunnel_inner_ft_supported(mdev);
4716 /* Do not update netdev->features directly in here
4717 * on mlx5e_attach_netdev() we will call mlx5e_update_features()
4718 * To update netdev->features please modify mlx5e_fix_features()
4722 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4724 struct mlx5e_priv *priv = netdev_priv(netdev);
4726 mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
4727 if (is_zero_ether_addr(netdev->dev_addr) &&
4728 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4729 eth_hw_addr_random(netdev);
4730 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4734 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table,
4735 unsigned int entry, struct udp_tunnel_info *ti)
4737 struct mlx5e_priv *priv = netdev_priv(netdev);
4739 return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port));
4742 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table,
4743 unsigned int entry, struct udp_tunnel_info *ti)
4745 struct mlx5e_priv *priv = netdev_priv(netdev);
4747 return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port));
4750 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv)
4752 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4755 priv->nic_info.set_port = mlx5e_vxlan_set_port;
4756 priv->nic_info.unset_port = mlx5e_vxlan_unset_port;
4757 priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
4758 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN;
4759 priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN;
4760 /* Don't count the space hard-coded to the IANA port */
4761 priv->nic_info.tables[0].n_entries =
4762 mlx5_vxlan_max_udp_ports(priv->mdev) - 1;
4764 priv->netdev->udp_tunnel_nic_info = &priv->nic_info;
4767 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev)
4771 for (tt = 0; tt < MLX5E_NUM_TUNNEL_TT; tt++) {
4772 if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5e_get_proto_by_tunnel_type(tt)))
4775 return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev));
4778 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4780 struct mlx5e_priv *priv = netdev_priv(netdev);
4781 struct mlx5_core_dev *mdev = priv->mdev;
4785 SET_NETDEV_DEV(netdev, mdev->device);
4787 netdev->netdev_ops = &mlx5e_netdev_ops;
4789 mlx5e_dcbnl_build_netdev(netdev);
4791 netdev->watchdog_timeo = 15 * HZ;
4793 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4795 netdev->vlan_features |= NETIF_F_SG;
4796 netdev->vlan_features |= NETIF_F_HW_CSUM;
4797 netdev->vlan_features |= NETIF_F_GRO;
4798 netdev->vlan_features |= NETIF_F_TSO;
4799 netdev->vlan_features |= NETIF_F_TSO6;
4800 netdev->vlan_features |= NETIF_F_RXCSUM;
4801 netdev->vlan_features |= NETIF_F_RXHASH;
4803 netdev->mpls_features |= NETIF_F_SG;
4804 netdev->mpls_features |= NETIF_F_HW_CSUM;
4805 netdev->mpls_features |= NETIF_F_TSO;
4806 netdev->mpls_features |= NETIF_F_TSO6;
4808 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX;
4809 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX;
4811 if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4812 mlx5e_check_fragmented_striding_rq_cap(mdev))
4813 netdev->vlan_features |= NETIF_F_LRO;
4815 netdev->hw_features = netdev->vlan_features;
4816 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
4817 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4818 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4819 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
4821 if (mlx5e_tunnel_any_tx_proto_supported(mdev)) {
4822 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4823 netdev->hw_enc_features |= NETIF_F_TSO;
4824 netdev->hw_enc_features |= NETIF_F_TSO6;
4825 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4828 if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4829 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL;
4830 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
4831 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL;
4834 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) {
4835 netdev->hw_features |= NETIF_F_GSO_GRE;
4836 netdev->hw_enc_features |= NETIF_F_GSO_GRE;
4837 netdev->gso_partial_features |= NETIF_F_GSO_GRE;
4840 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) {
4841 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4843 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4845 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4849 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
4850 netdev->gso_partial_features |= NETIF_F_GSO_UDP_L4;
4851 netdev->hw_features |= NETIF_F_GSO_UDP_L4;
4852 netdev->features |= NETIF_F_GSO_UDP_L4;
4854 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4857 netdev->hw_features |= NETIF_F_RXALL;
4859 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4860 netdev->hw_features |= NETIF_F_RXFCS;
4862 netdev->features = netdev->hw_features;
4866 netdev->features &= ~NETIF_F_RXALL;
4867 netdev->features &= ~NETIF_F_LRO;
4868 netdev->features &= ~NETIF_F_RXFCS;
4870 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4871 if (FT_CAP(flow_modify_en) &&
4872 FT_CAP(modify_root) &&
4873 FT_CAP(identified_miss_table_mode) &&
4874 FT_CAP(flow_table_modify)) {
4875 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
4876 netdev->hw_features |= NETIF_F_HW_TC;
4878 #ifdef CONFIG_MLX5_EN_ARFS
4879 netdev->hw_features |= NETIF_F_NTUPLE;
4882 if (mlx5_qos_is_supported(mdev))
4883 netdev->features |= NETIF_F_HW_TC;
4885 netdev->features |= NETIF_F_HIGHDMA;
4886 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
4888 netdev->priv_flags |= IFF_UNICAST_FLT;
4890 mlx5e_set_netdev_dev_addr(netdev);
4891 mlx5e_ipsec_build_netdev(priv);
4892 mlx5e_tls_build_netdev(priv);
4895 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4897 u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
4898 u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
4899 struct mlx5_core_dev *mdev = priv->mdev;
4902 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
4903 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4906 MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4908 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4910 priv->drop_rq_q_counter =
4911 MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4914 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4916 u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
4918 MLX5_SET(dealloc_q_counter_in, in, opcode,
4919 MLX5_CMD_OP_DEALLOC_Q_COUNTER);
4920 if (priv->q_counter) {
4921 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4923 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4926 if (priv->drop_rq_q_counter) {
4927 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4928 priv->drop_rq_q_counter);
4929 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4933 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4934 struct net_device *netdev)
4936 struct mlx5e_priv *priv = netdev_priv(netdev);
4937 struct devlink_port *dl_port;
4940 mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu);
4941 mlx5e_vxlan_set_netdev_info(priv);
4943 mlx5e_timestamp_init(priv);
4945 err = mlx5e_ipsec_init(priv);
4947 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4949 err = mlx5e_tls_init(priv);
4951 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4953 dl_port = mlx5e_devlink_get_dl_port(priv);
4954 if (dl_port->registered)
4955 mlx5e_health_create_reporters(priv);
4960 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4962 struct devlink_port *dl_port = mlx5e_devlink_get_dl_port(priv);
4964 if (dl_port->registered)
4965 mlx5e_health_destroy_reporters(priv);
4966 mlx5e_tls_cleanup(priv);
4967 mlx5e_ipsec_cleanup(priv);
4970 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4972 struct mlx5_core_dev *mdev = priv->mdev;
4973 u16 max_nch = priv->max_nch;
4976 mlx5e_create_q_counters(priv);
4978 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4980 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4981 goto err_destroy_q_counters;
4984 err = mlx5e_create_indirect_rqt(priv);
4986 goto err_close_drop_rq;
4988 err = mlx5e_create_direct_rqts(priv, priv->direct_tir, max_nch);
4990 goto err_destroy_indirect_rqts;
4992 err = mlx5e_create_indirect_tirs(priv, true);
4994 goto err_destroy_direct_rqts;
4996 err = mlx5e_create_direct_tirs(priv, priv->direct_tir, max_nch);
4998 goto err_destroy_indirect_tirs;
5000 err = mlx5e_create_direct_rqts(priv, priv->xsk_tir, max_nch);
5002 goto err_destroy_direct_tirs;
5004 err = mlx5e_create_direct_tirs(priv, priv->xsk_tir, max_nch);
5006 goto err_destroy_xsk_rqts;
5008 err = mlx5e_create_direct_rqts(priv, &priv->ptp_tir, 1);
5010 goto err_destroy_xsk_tirs;
5012 err = mlx5e_create_direct_tirs(priv, &priv->ptp_tir, 1);
5014 goto err_destroy_ptp_rqt;
5016 err = mlx5e_create_flow_steering(priv);
5018 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5019 goto err_destroy_ptp_direct_tir;
5022 err = mlx5e_tc_nic_init(priv);
5024 goto err_destroy_flow_steering;
5026 err = mlx5e_accel_init_rx(priv);
5028 goto err_tc_nic_cleanup;
5030 #ifdef CONFIG_MLX5_EN_ARFS
5031 priv->netdev->rx_cpu_rmap = mlx5_eq_table_get_rmap(priv->mdev);
5037 mlx5e_tc_nic_cleanup(priv);
5038 err_destroy_flow_steering:
5039 mlx5e_destroy_flow_steering(priv);
5040 err_destroy_ptp_direct_tir:
5041 mlx5e_destroy_direct_tirs(priv, &priv->ptp_tir, 1);
5042 err_destroy_ptp_rqt:
5043 mlx5e_destroy_direct_rqts(priv, &priv->ptp_tir, 1);
5044 err_destroy_xsk_tirs:
5045 mlx5e_destroy_direct_tirs(priv, priv->xsk_tir, max_nch);
5046 err_destroy_xsk_rqts:
5047 mlx5e_destroy_direct_rqts(priv, priv->xsk_tir, max_nch);
5048 err_destroy_direct_tirs:
5049 mlx5e_destroy_direct_tirs(priv, priv->direct_tir, max_nch);
5050 err_destroy_indirect_tirs:
5051 mlx5e_destroy_indirect_tirs(priv);
5052 err_destroy_direct_rqts:
5053 mlx5e_destroy_direct_rqts(priv, priv->direct_tir, max_nch);
5054 err_destroy_indirect_rqts:
5055 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5057 mlx5e_close_drop_rq(&priv->drop_rq);
5058 err_destroy_q_counters:
5059 mlx5e_destroy_q_counters(priv);
5063 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5065 u16 max_nch = priv->max_nch;
5067 mlx5e_accel_cleanup_rx(priv);
5068 mlx5e_tc_nic_cleanup(priv);
5069 mlx5e_destroy_flow_steering(priv);
5070 mlx5e_destroy_direct_tirs(priv, &priv->ptp_tir, 1);
5071 mlx5e_destroy_direct_rqts(priv, &priv->ptp_tir, 1);
5072 mlx5e_destroy_direct_tirs(priv, priv->xsk_tir, max_nch);
5073 mlx5e_destroy_direct_rqts(priv, priv->xsk_tir, max_nch);
5074 mlx5e_destroy_direct_tirs(priv, priv->direct_tir, max_nch);
5075 mlx5e_destroy_indirect_tirs(priv);
5076 mlx5e_destroy_direct_rqts(priv, priv->direct_tir, max_nch);
5077 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5078 mlx5e_close_drop_rq(&priv->drop_rq);
5079 mlx5e_destroy_q_counters(priv);
5082 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5086 err = mlx5e_create_tises(priv);
5088 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5092 mlx5e_dcbnl_initialize(priv);
5096 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5098 struct net_device *netdev = priv->netdev;
5099 struct mlx5_core_dev *mdev = priv->mdev;
5101 mlx5e_init_l2_addr(priv);
5103 /* Marking the link as currently not needed by the Driver */
5104 if (!netif_running(netdev))
5105 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN);
5107 mlx5e_set_netdev_mtu_boundaries(priv);
5108 mlx5e_set_dev_port_mtu(priv);
5110 mlx5_lag_add_netdev(mdev, netdev);
5112 mlx5e_enable_async_events(priv);
5113 mlx5e_enable_blocking_events(priv);
5114 if (mlx5e_monitor_counter_supported(priv))
5115 mlx5e_monitor_counter_init(priv);
5117 mlx5e_hv_vhca_stats_create(priv);
5118 if (netdev->reg_state != NETREG_REGISTERED)
5120 mlx5e_dcbnl_init_app(priv);
5122 mlx5e_nic_set_rx_mode(priv);
5125 if (netif_running(netdev))
5127 udp_tunnel_nic_reset_ntf(priv->netdev);
5128 netif_device_attach(netdev);
5132 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5134 struct mlx5_core_dev *mdev = priv->mdev;
5136 if (priv->netdev->reg_state == NETREG_REGISTERED)
5137 mlx5e_dcbnl_delete_app(priv);
5140 if (netif_running(priv->netdev))
5141 mlx5e_close(priv->netdev);
5142 netif_device_detach(priv->netdev);
5145 mlx5e_nic_set_rx_mode(priv);
5147 mlx5e_hv_vhca_stats_destroy(priv);
5148 if (mlx5e_monitor_counter_supported(priv))
5149 mlx5e_monitor_counter_cleanup(priv);
5151 mlx5e_disable_blocking_events(priv);
5152 if (priv->en_trap) {
5153 mlx5e_deactivate_trap(priv);
5154 mlx5e_close_trap(priv->en_trap);
5155 priv->en_trap = NULL;
5157 mlx5e_disable_async_events(priv);
5158 mlx5_lag_remove_netdev(mdev, priv->netdev);
5159 mlx5_vxlan_reset_to_default(mdev->vxlan);
5162 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5164 return mlx5e_refresh_tirs(priv, false, false);
5167 static const struct mlx5e_profile mlx5e_nic_profile = {
5168 .init = mlx5e_nic_init,
5169 .cleanup = mlx5e_nic_cleanup,
5170 .init_rx = mlx5e_init_nic_rx,
5171 .cleanup_rx = mlx5e_cleanup_nic_rx,
5172 .init_tx = mlx5e_init_nic_tx,
5173 .cleanup_tx = mlx5e_cleanup_nic_tx,
5174 .enable = mlx5e_nic_enable,
5175 .disable = mlx5e_nic_disable,
5176 .update_rx = mlx5e_update_nic_rx,
5177 .update_stats = mlx5e_stats_update_ndo_stats,
5178 .update_carrier = mlx5e_update_carrier,
5179 .rx_handlers = &mlx5e_rx_handlers_nic,
5180 .max_tc = MLX5E_MAX_NUM_TC,
5181 .rq_groups = MLX5E_NUM_RQ_GROUPS(XSK),
5182 .stats_grps = mlx5e_nic_stats_grps,
5183 .stats_grps_num = mlx5e_nic_stats_grps_num,
5184 .rx_ptp_support = true,
5187 /* mlx5e generic netdev management API (move to en_common.c) */
5188 int mlx5e_priv_init(struct mlx5e_priv *priv,
5189 struct net_device *netdev,
5190 struct mlx5_core_dev *mdev)
5194 priv->netdev = netdev;
5195 priv->msglevel = MLX5E_MSG_LEVEL;
5196 priv->max_opened_tc = 1;
5198 if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
5201 mutex_init(&priv->state_lock);
5202 hash_init(priv->htb.qos_tc2node);
5203 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5204 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5205 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5206 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5208 priv->wq = create_singlethread_workqueue("mlx5e");
5210 goto err_free_cpumask;
5215 free_cpumask_var(priv->scratchpad.cpumask);
5220 void mlx5e_priv_cleanup(struct mlx5e_priv *priv)
5224 /* bail if change profile failed and also rollback failed */
5228 destroy_workqueue(priv->wq);
5229 free_cpumask_var(priv->scratchpad.cpumask);
5231 for (i = 0; i < priv->htb.max_qos_sqs; i++)
5232 kfree(priv->htb.qos_sq_stats[i]);
5233 kvfree(priv->htb.qos_sq_stats);
5235 memset(priv, 0, sizeof(*priv));
5239 mlx5e_create_netdev(struct mlx5_core_dev *mdev, unsigned int txqs, unsigned int rxqs)
5241 struct net_device *netdev;
5244 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs);
5246 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5250 err = mlx5e_priv_init(netdev_priv(netdev), netdev, mdev);
5252 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5253 goto err_free_netdev;
5256 netif_carrier_off(netdev);
5257 dev_net_set(netdev, mlx5_core_net(mdev));
5262 free_netdev(netdev);
5267 static void mlx5e_update_features(struct net_device *netdev)
5269 if (netdev->reg_state != NETREG_REGISTERED)
5270 return; /* features will be updated on netdev registration */
5273 netdev_update_features(netdev);
5277 static void mlx5e_reset_channels(struct net_device *netdev)
5279 netdev_reset_tc(netdev);
5282 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5284 const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
5285 const struct mlx5e_profile *profile = priv->profile;
5289 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5291 /* max number of channels may have changed */
5292 max_nch = mlx5e_get_max_num_channels(priv->mdev);
5293 if (priv->channels.params.num_channels > max_nch) {
5294 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5295 /* Reducing the number of channels - RXFH has to be reset, and
5296 * mlx5e_num_channels_changed below will build the RQT.
5298 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
5299 priv->channels.params.num_channels = max_nch;
5301 /* 1. Set the real number of queues in the kernel the first time.
5302 * 2. Set our default XPS cpumask.
5305 * rtnl_lock is required by netif_set_real_num_*_queues in case the
5306 * netdev has been registered by this point (if this function was called
5307 * in the reload or resume flow).
5311 err = mlx5e_num_channels_changed(priv);
5317 err = profile->init_tx(priv);
5321 err = profile->init_rx(priv);
5323 goto err_cleanup_tx;
5325 if (profile->enable)
5326 profile->enable(priv);
5328 mlx5e_update_features(priv->netdev);
5333 profile->cleanup_tx(priv);
5336 mlx5e_reset_channels(priv->netdev);
5337 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5338 cancel_work_sync(&priv->update_stats_work);
5342 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5344 const struct mlx5e_profile *profile = priv->profile;
5346 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5348 if (profile->disable)
5349 profile->disable(priv);
5350 flush_workqueue(priv->wq);
5352 profile->cleanup_rx(priv);
5353 profile->cleanup_tx(priv);
5354 mlx5e_reset_channels(priv->netdev);
5355 cancel_work_sync(&priv->update_stats_work);
5359 mlx5e_netdev_attach_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
5360 const struct mlx5e_profile *new_profile, void *new_ppriv)
5362 struct mlx5e_priv *priv = netdev_priv(netdev);
5365 err = mlx5e_priv_init(priv, netdev, mdev);
5367 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5370 netif_carrier_off(netdev);
5371 priv->profile = new_profile;
5372 priv->ppriv = new_ppriv;
5373 err = new_profile->init(priv->mdev, priv->netdev);
5376 err = mlx5e_attach_netdev(priv);
5378 goto profile_cleanup;
5382 new_profile->cleanup(priv);
5384 mlx5e_priv_cleanup(priv);
5388 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
5389 const struct mlx5e_profile *new_profile, void *new_ppriv)
5391 unsigned int new_max_nch = mlx5e_calc_max_nch(priv, new_profile);
5392 const struct mlx5e_profile *orig_profile = priv->profile;
5393 struct net_device *netdev = priv->netdev;
5394 struct mlx5_core_dev *mdev = priv->mdev;
5395 void *orig_ppriv = priv->ppriv;
5396 int err, rollback_err;
5399 if (new_max_nch != priv->max_nch) {
5400 netdev_warn(netdev, "%s: Replacing profile with different max channels\n",
5405 /* cleanup old profile */
5406 mlx5e_detach_netdev(priv);
5407 priv->profile->cleanup(priv);
5408 mlx5e_priv_cleanup(priv);
5410 err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile, new_ppriv);
5411 if (err) { /* roll back to original profile */
5412 netdev_warn(netdev, "%s: new profile init failed, %d\n", __func__, err);
5419 rollback_err = mlx5e_netdev_attach_profile(netdev, mdev, orig_profile, orig_ppriv);
5421 netdev_err(netdev, "%s: failed to rollback to orig profile, %d\n",
5422 __func__, rollback_err);
5426 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv)
5428 mlx5e_netdev_change_profile(priv, &mlx5e_nic_profile, NULL);
5431 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5433 struct net_device *netdev = priv->netdev;
5435 mlx5e_priv_cleanup(priv);
5436 free_netdev(netdev);
5439 static int mlx5e_resume(struct auxiliary_device *adev)
5441 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5442 struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5443 struct net_device *netdev = priv->netdev;
5444 struct mlx5_core_dev *mdev = edev->mdev;
5447 if (netif_device_present(netdev))
5450 err = mlx5e_create_mdev_resources(mdev);
5454 err = mlx5e_attach_netdev(priv);
5456 mlx5e_destroy_mdev_resources(mdev);
5463 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)
5465 struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5466 struct net_device *netdev = priv->netdev;
5467 struct mlx5_core_dev *mdev = priv->mdev;
5469 if (!netif_device_present(netdev))
5472 mlx5e_detach_netdev(priv);
5473 mlx5e_destroy_mdev_resources(mdev);
5477 static int mlx5e_probe(struct auxiliary_device *adev,
5478 const struct auxiliary_device_id *id)
5480 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5481 const struct mlx5e_profile *profile = &mlx5e_nic_profile;
5482 struct mlx5_core_dev *mdev = edev->mdev;
5483 struct net_device *netdev;
5484 pm_message_t state = {};
5485 unsigned int txqs, rxqs, ptp_txqs = 0;
5486 struct mlx5e_priv *priv;
5491 if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
5492 ptp_txqs = profile->max_tc;
5494 if (mlx5_qos_is_supported(mdev))
5495 qos_sqs = mlx5e_qos_max_leaf_nodes(mdev);
5497 nch = mlx5e_get_max_num_channels(mdev);
5498 txqs = nch * profile->max_tc + ptp_txqs + qos_sqs;
5499 rxqs = nch * profile->rq_groups;
5500 netdev = mlx5e_create_netdev(mdev, txqs, rxqs);
5502 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5506 mlx5e_build_nic_netdev(netdev);
5508 priv = netdev_priv(netdev);
5509 dev_set_drvdata(&adev->dev, priv);
5511 priv->profile = profile;
5514 err = mlx5e_devlink_port_register(priv);
5516 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
5517 goto err_destroy_netdev;
5520 err = profile->init(mdev, netdev);
5522 mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err);
5523 goto err_devlink_cleanup;
5526 err = mlx5e_resume(adev);
5528 mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err);
5529 goto err_profile_cleanup;
5532 err = register_netdev(netdev);
5534 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5538 mlx5e_devlink_port_type_eth_set(priv);
5540 mlx5e_dcbnl_init_app(priv);
5541 mlx5_uplink_netdev_set(mdev, netdev);
5545 mlx5e_suspend(adev, state);
5546 err_profile_cleanup:
5547 profile->cleanup(priv);
5548 err_devlink_cleanup:
5549 mlx5e_devlink_port_unregister(priv);
5551 mlx5e_destroy_netdev(priv);
5555 static void mlx5e_remove(struct auxiliary_device *adev)
5557 struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5558 pm_message_t state = {};
5560 mlx5e_dcbnl_delete_app(priv);
5561 unregister_netdev(priv->netdev);
5562 mlx5e_suspend(adev, state);
5563 priv->profile->cleanup(priv);
5564 mlx5e_devlink_port_unregister(priv);
5565 mlx5e_destroy_netdev(priv);
5568 static const struct auxiliary_device_id mlx5e_id_table[] = {
5569 { .name = MLX5_ADEV_NAME ".eth", },
5573 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table);
5575 static struct auxiliary_driver mlx5e_driver = {
5577 .probe = mlx5e_probe,
5578 .remove = mlx5e_remove,
5579 .suspend = mlx5e_suspend,
5580 .resume = mlx5e_resume,
5581 .id_table = mlx5e_id_table,
5584 int mlx5e_init(void)
5588 mlx5e_ipsec_build_inverse_table();
5589 mlx5e_build_ptys2ethtool_map();
5590 ret = auxiliary_driver_register(&mlx5e_driver);
5594 ret = mlx5e_rep_init();
5596 auxiliary_driver_unregister(&mlx5e_driver);
5600 void mlx5e_cleanup(void)
5602 mlx5e_rep_cleanup();
5603 auxiliary_driver_unregister(&mlx5e_driver);