drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <net/page_pool.h>
  41 #include <net/xdp_sock_drv.h>
  42 #include "eswitch.h"
  43 #include "en.h"
  44 #include "en/txrx.h"
  45 #include "en_tc.h"
  46 #include "en_rep.h"
  47 #include "en_accel/ipsec.h"
  48 #include "en_accel/en_accel.h"
  49 #include "en_accel/tls.h"
  50 #include "accel/ipsec.h"
  51 #include "accel/tls.h"
  52 #include "lib/vxlan.h"
  53 #include "lib/clock.h"
  54 #include "en/port.h"
  55 #include "en/xdp.h"
  56 #include "lib/eq.h"
  57 #include "en/monitor_stats.h"
  58 #include "en/health.h"
  59 #include "en/params.h"
  60 #include "en/xsk/pool.h"
  61 #include "en/xsk/setup.h"
  62 #include "en/xsk/rx.h"
  63 #include "en/xsk/tx.h"
  64 #include "en/hv_vhca_stats.h"
  65 #include "en/devlink.h"
  66 #include "lib/mlx5.h"
  67 #include "en/ptp.h"
  68 #include "qos.h"
  69 #include "en/trap.h"
  70 #include "fpga/ipsec.h"
  71
  72 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  73 {
  74         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  75                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  76                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  77         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  78         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  79
  80         if (!striding_rq_umr)
  81                 return false;
  82         if (!inline_umr) {
  83                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  84                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  85                 return false;
  86         }
  87         return true;
  88 }
  89
  90 void mlx5e_update_carrier(struct mlx5e_priv *priv)
  91 {
  92         struct mlx5_core_dev *mdev = priv->mdev;
  93         u8 port_state;
  94         bool up;
  95
  96         port_state = mlx5_query_vport_state(mdev,
  97                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
  98                                             0);
  99
 100         up = port_state == VPORT_STATE_UP;
 101         if (up == netif_carrier_ok(priv->netdev))
 102                 netif_carrier_event(priv->netdev);
 103         if (up) {
 104                 netdev_info(priv->netdev, "Link up\n");
 105                 netif_carrier_on(priv->netdev);
 106         } else {
 107                 netdev_info(priv->netdev, "Link down\n");
 108                 netif_carrier_off(priv->netdev);
 109         }
 110 }
 111
 112 static void mlx5e_update_carrier_work(struct work_struct *work)
 113 {
 114         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 115                                                update_carrier_work);
 116
 117         mutex_lock(&priv->state_lock);
 118         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 119                 if (priv->profile->update_carrier)
 120                         priv->profile->update_carrier(priv);
 121         mutex_unlock(&priv->state_lock);
 122 }
 123
 124 static void mlx5e_update_stats_work(struct work_struct *work)
 125 {
 126         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 127                                                update_stats_work);
 128
 129         mutex_lock(&priv->state_lock);
 130         priv->profile->update_stats(priv);
 131         mutex_unlock(&priv->state_lock);
 132 }
 133
 134 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 135 {
 136         if (!priv->profile->update_stats)
 137                 return;
 138
 139         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 140                 return;
 141
 142         queue_work(priv->wq, &priv->update_stats_work);
 143 }
 144
 145 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 146 {
 147         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 148         struct mlx5_eqe   *eqe = data;
 149
 150         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 151                 return NOTIFY_DONE;
 152
 153         switch (eqe->sub_type) {
 154         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 155         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 156                 queue_work(priv->wq, &priv->update_carrier_work);
 157                 break;
 158         default:
 159                 return NOTIFY_DONE;
 160         }
 161
 162         return NOTIFY_OK;
 163 }
 164
 165 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 166 {
 167         priv->events_nb.notifier_call = async_event;
 168         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 169 }
 170
 171 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 172 {
 173         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 174 }
 175
 176 static int blocking_event(struct notifier_block *nb, unsigned long event, void *data)
 177 {
 178         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb);
 179         int err;
 180
 181         switch (event) {
 182         case MLX5_DRIVER_EVENT_TYPE_TRAP:
 183                 err = mlx5e_handle_trap_event(priv, data);
 184                 break;
 185         default:
 186                 netdev_warn(priv->netdev, "Sync event: Unknown event %ld\n", event);
 187                 err = -EINVAL;
 188         }
 189         return err;
 190 }
 191
 192 static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv)
 193 {
 194         priv->blocking_events_nb.notifier_call = blocking_event;
 195         mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb);
 196 }
 197
 198 static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv)
 199 {
 200         mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb);
 201 }
 202
 203 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 204                                        struct mlx5e_icosq *sq,
 205                                        struct mlx5e_umr_wqe *wqe)
 206 {
 207         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 208         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 209         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 210
 211         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 212                                       ds_cnt);
 213         cseg->umr_mkey  = rq->mkey_be;
 214
 215         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 216         ucseg->xlt_octowords =
 217                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 218         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 219 }
 220
 221 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node)
 222 {
 223         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 224
 225         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 226                                                   sizeof(*rq->mpwqe.info)),
 227                                        GFP_KERNEL, node);
 228         if (!rq->mpwqe.info)
 229                 return -ENOMEM;
 230
 231         mlx5e_build_umr_wqe(rq, rq->icosq, &rq->mpwqe.umr_wqe);
 232
 233         return 0;
 234 }
 235
 236 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 237                                  u64 npages, u8 page_shift,
 238                                  struct mlx5_core_mkey *umr_mkey,
 239                                  dma_addr_t filler_addr)
 240 {
 241         struct mlx5_mtt *mtt;
 242         int inlen;
 243         void *mkc;
 244         u32 *in;
 245         int err;
 246         int i;
 247
 248         inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + sizeof(*mtt) * npages;
 249
 250         in = kvzalloc(inlen, GFP_KERNEL);
 251         if (!in)
 252                 return -ENOMEM;
 253
 254         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 255
 256         MLX5_SET(mkc, mkc, free, 1);
 257         MLX5_SET(mkc, mkc, umr_en, 1);
 258         MLX5_SET(mkc, mkc, lw, 1);
 259         MLX5_SET(mkc, mkc, lr, 1);
 260         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 261         mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
 262         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 263         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
 264         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 265         MLX5_SET(mkc, mkc, translations_octword_size,
 266                  MLX5_MTT_OCTW(npages));
 267         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 268         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 269                  MLX5_MTT_OCTW(npages));
 270
 271         /* Initialize the mkey with all MTTs pointing to a default
 272          * page (filler_addr). When the channels are activated, UMR
 273          * WQEs will redirect the RX WQEs to the actual memory from
 274          * the RQ's pool, while the gaps (wqe_overflow) remain mapped
 275          * to the default page.
 276          */
 277         mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
 278         for (i = 0 ; i < npages ; i++)
 279                 mtt[i].ptag = cpu_to_be64(filler_addr);
 280
 281         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 282
 283         kvfree(in);
 284         return err;
 285 }
 286
 287 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 288 {
 289         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 290
 291         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey,
 292                                      rq->wqe_overflow.addr);
 293 }
 294
 295 static u64 mlx5e_get_mpwqe_offset(u16 wqe_ix)
 296 {
 297         return MLX5E_REQUIRED_MTTS(wqe_ix) << PAGE_SHIFT;
 298 }
 299
 300 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 301 {
 302         struct mlx5e_wqe_frag_info next_frag = {};
 303         struct mlx5e_wqe_frag_info *prev = NULL;
 304         int i;
 305
 306         next_frag.di = &rq->wqe.di[0];
 307
 308         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 309                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 310                 struct mlx5e_wqe_frag_info *frag =
 311                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 312                 int f;
 313
 314                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 315                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 316                                 next_frag.di++;
 317                                 next_frag.offset = 0;
 318                                 if (prev)
 319                                         prev->last_in_page = true;
 320                         }
 321                         *frag = next_frag;
 322
 323                         /* prepare next */
 324                         next_frag.offset += frag_info[f].frag_stride;
 325                         prev = frag;
 326                 }
 327         }
 328
 329         if (prev)
 330                 prev->last_in_page = true;
 331 }
 332
 333 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node)
 334 {
 335         int len = wq_sz << rq->wqe.info.log_num_frags;
 336
 337         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)), GFP_KERNEL, node);
 338         if (!rq->wqe.di)
 339                 return -ENOMEM;
 340
 341         mlx5e_init_frags_partition(rq);
 342
 343         return 0;
 344 }
 345
 346 void mlx5e_free_di_list(struct mlx5e_rq *rq)
 347 {
 348         kvfree(rq->wqe.di);
 349 }
 350
 351 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
 352 {
 353         struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
 354
 355         mlx5e_reporter_rq_cqe_err(rq);
 356 }
 357
 358 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 359 {
 360         rq->wqe_overflow.page = alloc_page(GFP_KERNEL);
 361         if (!rq->wqe_overflow.page)
 362                 return -ENOMEM;
 363
 364         rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0,
 365                                              PAGE_SIZE, rq->buff.map_dir);
 366         if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) {
 367                 __free_page(rq->wqe_overflow.page);
 368                 return -ENOMEM;
 369         }
 370         return 0;
 371 }
 372
 373 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
 374 {
 375          dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE,
 376                         rq->buff.map_dir);
 377          __free_page(rq->wqe_overflow.page);
 378 }
 379
 380 static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
 381                              struct mlx5e_rq *rq)
 382 {
 383         struct mlx5_core_dev *mdev = c->mdev;
 384         int err;
 385
 386         rq->wq_type      = params->rq_wq_type;
 387         rq->pdev         = c->pdev;
 388         rq->netdev       = c->netdev;
 389         rq->priv         = c->priv;
 390         rq->tstamp       = c->tstamp;
 391         rq->clock        = &mdev->clock;
 392         rq->icosq        = &c->icosq;
 393         rq->ix           = c->ix;
 394         rq->mdev         = mdev;
 395         rq->hw_mtu       = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 396         rq->xdpsq        = &c->rq_xdpsq;
 397         rq->stats        = &c->priv->channel_stats[c->ix].rq;
 398         rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev);
 399         err = mlx5e_rq_set_handlers(rq, params, NULL);
 400         if (err)
 401                 return err;
 402
 403         return xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, 0);
 404 }
 405
 406 static int mlx5e_alloc_rq(struct mlx5e_params *params,
 407                           struct mlx5e_xsk_param *xsk,
 408                           struct mlx5e_rq_param *rqp,
 409                           int node, struct mlx5e_rq *rq)
 410 {
 411         struct page_pool_params pp_params = { 0 };
 412         struct mlx5_core_dev *mdev = rq->mdev;
 413         void *rqc = rqp->rqc;
 414         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 415         u32 pool_size;
 416         int wq_sz;
 417         int err;
 418         int i;
 419
 420         rqp->wq.db_numa_node = node;
 421         INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
 422
 423         if (params->xdp_prog)
 424                 bpf_prog_inc(params->xdp_prog);
 425         RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog);
 426
 427         rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 428         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
 429         pool_size = 1 << params->log_rq_mtu_frames;
 430
 431         switch (rq->wq_type) {
 432         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 433                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 434                                         &rq->wq_ctrl);
 435                 if (err)
 436                         goto err_rq_xdp_prog;
 437
 438                 err = mlx5e_alloc_mpwqe_rq_drop_page(rq);
 439                 if (err)
 440                         goto err_rq_wq_destroy;
 441
 442                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 443
 444                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 445
 446                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
 447                         mlx5e_mpwqe_get_log_rq_size(params, xsk);
 448
 449                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
 450                 rq->mpwqe.num_strides =
 451                         BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
 452
 453                 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
 454
 455                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 456                 if (err)
 457                         goto err_rq_drop_page;
 458                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 459
 460                 err = mlx5e_rq_alloc_mpwqe_info(rq, node);
 461                 if (err)
 462                         goto err_rq_mkey;
 463                 break;
 464         default: /* MLX5_WQ_TYPE_CYCLIC */
 465                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 466                                          &rq->wq_ctrl);
 467                 if (err)
 468                         goto err_rq_xdp_prog;
 469
 470                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 471
 472                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 473
 474                 rq->wqe.info = rqp->frags_info;
 475                 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
 476
 477                 rq->wqe.frags =
 478                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 479                                         (wq_sz << rq->wqe.info.log_num_frags)),
 480                                       GFP_KERNEL, node);
 481                 if (!rq->wqe.frags) {
 482                         err = -ENOMEM;
 483                         goto err_rq_wq_destroy;
 484                 }
 485
 486                 err = mlx5e_init_di_list(rq, wq_sz, node);
 487                 if (err)
 488                         goto err_rq_frags;
 489
 490                 rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey.key);
 491         }
 492
 493         if (xsk) {
 494                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 495                                                  MEM_TYPE_XSK_BUFF_POOL, NULL);
 496                 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq);
 497         } else {
 498                 /* Create a page_pool and register it with rxq */
 499                 pp_params.order     = 0;
 500                 pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 501                 pp_params.pool_size = pool_size;
 502                 pp_params.nid       = node;
 503                 pp_params.dev       = rq->pdev;
 504                 pp_params.dma_dir   = rq->buff.map_dir;
 505
 506                 /* page_pool can be used even when there is no rq->xdp_prog,
 507                  * given page_pool does not handle DMA mapping there is no
 508                  * required state to clear. And page_pool gracefully handle
 509                  * elevated refcnt.
 510                  */
 511                 rq->page_pool = page_pool_create(&pp_params);
 512                 if (IS_ERR(rq->page_pool)) {
 513                         err = PTR_ERR(rq->page_pool);
 514                         rq->page_pool = NULL;
 515                         goto err_free_by_rq_type;
 516                 }
 517                 if (xdp_rxq_info_is_reg(&rq->xdp_rxq))
 518                         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 519                                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 520         }
 521         if (err)
 522                 goto err_free_by_rq_type;
 523
 524         for (i = 0; i < wq_sz; i++) {
 525                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 526                         struct mlx5e_rx_wqe_ll *wqe =
 527                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 528                         u32 byte_count =
 529                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 530                         u64 dma_offset = mlx5e_get_mpwqe_offset(i);
 531
 532                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 533                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 534                         wqe->data[0].lkey = rq->mkey_be;
 535                 } else {
 536                         struct mlx5e_rx_wqe_cyc *wqe =
 537                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 538                         int f;
 539
 540                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 541                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 542                                         MLX5_HW_START_PADDING;
 543
 544                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 545                                 wqe->data[f].lkey = rq->mkey_be;
 546                         }
 547                         /* check if num_frags is not a pow of two */
 548                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 549                                 wqe->data[f].byte_count = 0;
 550                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 551                                 wqe->data[f].addr = 0;
 552                         }
 553                 }
 554         }
 555
 556         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 557
 558         switch (params->rx_cq_moderation.cq_period_mode) {
 559         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 560                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 561                 break;
 562         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 563         default:
 564                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 565         }
 566
 567         rq->page_cache.head = 0;
 568         rq->page_cache.tail = 0;
 569
 570         return 0;
 571
 572 err_free_by_rq_type:
 573         switch (rq->wq_type) {
 574         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 575                 kvfree(rq->mpwqe.info);
 576 err_rq_mkey:
 577                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 578 err_rq_drop_page:
 579                 mlx5e_free_mpwqe_rq_drop_page(rq);
 580                 break;
 581         default: /* MLX5_WQ_TYPE_CYCLIC */
 582                 mlx5e_free_di_list(rq);
 583 err_rq_frags:
 584                 kvfree(rq->wqe.frags);
 585         }
 586 err_rq_wq_destroy:
 587         mlx5_wq_destroy(&rq->wq_ctrl);
 588 err_rq_xdp_prog:
 589         if (params->xdp_prog)
 590                 bpf_prog_put(params->xdp_prog);
 591
 592         return err;
 593 }
 594
 595 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 596 {
 597         struct bpf_prog *old_prog;
 598         int i;
 599
 600         if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) {
 601                 old_prog = rcu_dereference_protected(rq->xdp_prog,
 602                                                      lockdep_is_held(&rq->priv->state_lock));
 603                 if (old_prog)
 604                         bpf_prog_put(old_prog);
 605         }
 606
 607         switch (rq->wq_type) {
 608         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 609                 kvfree(rq->mpwqe.info);
 610                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 611                 mlx5e_free_mpwqe_rq_drop_page(rq);
 612                 break;
 613         default: /* MLX5_WQ_TYPE_CYCLIC */
 614                 kvfree(rq->wqe.frags);
 615                 mlx5e_free_di_list(rq);
 616         }
 617
 618         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 619              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 620                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 621
 622                 /* With AF_XDP, page_cache is not used, so this loop is not
 623                  * entered, and it's safe to call mlx5e_page_release_dynamic
 624                  * directly.
 625                  */
 626                 mlx5e_page_release_dynamic(rq, dma_info, false);
 627         }
 628
 629         xdp_rxq_info_unreg(&rq->xdp_rxq);
 630         page_pool_destroy(rq->page_pool);
 631         mlx5_wq_destroy(&rq->wq_ctrl);
 632 }
 633
 634 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 635 {
 636         struct mlx5_core_dev *mdev = rq->mdev;
 637         u8 ts_format;
 638         void *in;
 639         void *rqc;
 640         void *wq;
 641         int inlen;
 642         int err;
 643
 644         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 645                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 646         in = kvzalloc(inlen, GFP_KERNEL);
 647         if (!in)
 648                 return -ENOMEM;
 649
 650         ts_format = mlx5_is_real_time_rq(mdev) ?
 651                             MLX5_TIMESTAMP_FORMAT_REAL_TIME :
 652                             MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
 653         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 654         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 655
 656         memcpy(rqc, param->rqc, sizeof(param->rqc));
 657
 658         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 659         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 660         MLX5_SET(rqc,  rqc, ts_format,          ts_format);
 661         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 662                                                 MLX5_ADAPTER_PAGE_SHIFT);
 663         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 664
 665         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 666                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 667
 668         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 669
 670         kvfree(in);
 671
 672         return err;
 673 }
 674
 675 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
 676 {
 677         struct mlx5_core_dev *mdev = rq->mdev;
 678
 679         void *in;
 680         void *rqc;
 681         int inlen;
 682         int err;
 683
 684         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 685         in = kvzalloc(inlen, GFP_KERNEL);
 686         if (!in)
 687                 return -ENOMEM;
 688
 689         if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
 690                 mlx5e_rqwq_reset(rq);
 691
 692         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 693
 694         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 695         MLX5_SET(rqc, rqc, state, next_state);
 696
 697         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 698
 699         kvfree(in);
 700
 701         return err;
 702 }
 703
 704 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 705 {
 706         struct mlx5_core_dev *mdev = rq->mdev;
 707
 708         void *in;
 709         void *rqc;
 710         int inlen;
 711         int err;
 712
 713         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 714         in = kvzalloc(inlen, GFP_KERNEL);
 715         if (!in)
 716                 return -ENOMEM;
 717
 718         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 719
 720         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 721         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 722                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 723         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 724         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 725
 726         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 727
 728         kvfree(in);
 729
 730         return err;
 731 }
 732
 733 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 734 {
 735         struct mlx5_core_dev *mdev = rq->mdev;
 736         void *in;
 737         void *rqc;
 738         int inlen;
 739         int err;
 740
 741         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 742         in = kvzalloc(inlen, GFP_KERNEL);
 743         if (!in)
 744                 return -ENOMEM;
 745
 746         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 747
 748         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 749         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 750                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 751         MLX5_SET(rqc, rqc, vsd, vsd);
 752         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 753
 754         err = mlx5_core_modify_rq(mdev, rq->rqn, in);
 755
 756         kvfree(in);
 757
 758         return err;
 759 }
 760
 761 void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 762 {
 763         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 764 }
 765
 766 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 767 {
 768         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 769
 770         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 771
 772         do {
 773                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 774                         return 0;
 775
 776                 msleep(20);
 777         } while (time_before(jiffies, exp_time));
 778
 779         netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 780                     rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 781
 782         mlx5e_reporter_rx_timeout(rq);
 783         return -ETIMEDOUT;
 784 }
 785
 786 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq)
 787 {
 788         struct mlx5_wq_ll *wq;
 789         u16 head;
 790         int i;
 791
 792         if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 793                 return;
 794
 795         wq = &rq->mpwqe.wq;
 796         head = wq->head;
 797
 798         /* Outstanding UMR WQEs (in progress) start at wq->head */
 799         for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 800                 rq->dealloc_wqe(rq, head);
 801                 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 802         }
 803
 804         rq->mpwqe.actual_wq_head = wq->head;
 805         rq->mpwqe.umr_in_progress = 0;
 806         rq->mpwqe.umr_completed = 0;
 807 }
 808
 809 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 810 {
 811         __be16 wqe_ix_be;
 812         u16 wqe_ix;
 813
 814         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 815                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 816
 817                 mlx5e_free_rx_in_progress_descs(rq);
 818
 819                 while (!mlx5_wq_ll_is_empty(wq)) {
 820                         struct mlx5e_rx_wqe_ll *wqe;
 821
 822                         wqe_ix_be = *wq->tail_next;
 823                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 824                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 825                         rq->dealloc_wqe(rq, wqe_ix);
 826                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 827                                        &wqe->next.next_wqe_index);
 828                 }
 829         } else {
 830                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 831
 832                 while (!mlx5_wq_cyc_is_empty(wq)) {
 833                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 834                         rq->dealloc_wqe(rq, wqe_ix);
 835                         mlx5_wq_cyc_pop(wq);
 836                 }
 837         }
 838
 839 }
 840
 841 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
 842                   struct mlx5e_xsk_param *xsk, int node,
 843                   struct mlx5e_rq *rq)
 844 {
 845         struct mlx5_core_dev *mdev = rq->mdev;
 846         int err;
 847
 848         err = mlx5e_alloc_rq(params, xsk, param, node, rq);
 849         if (err)
 850                 return err;
 851
 852         err = mlx5e_create_rq(rq, param);
 853         if (err)
 854                 goto err_free_rq;
 855
 856         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 857         if (err)
 858                 goto err_destroy_rq;
 859
 860         if (mlx5e_is_tls_on(rq->priv) && !mlx5e_accel_is_ktls_device(mdev))
 861                 __set_bit(MLX5E_RQ_STATE_FPGA_TLS, &rq->state); /* must be FPGA */
 862
 863         if (MLX5_CAP_ETH(mdev, cqe_checksum_full))
 864                 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state);
 865
 866         if (params->rx_dim_enabled)
 867                 __set_bit(MLX5E_RQ_STATE_AM, &rq->state);
 868
 869         /* We disable csum_complete when XDP is enabled since
 870          * XDP programs might manipulate packets which will render
 871          * skb->checksum incorrect.
 872          */
 873         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || params->xdp_prog)
 874                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state);
 875
 876         /* For CQE compression on striding RQ, use stride index provided by
 877          * HW if capability is supported.
 878          */
 879         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) &&
 880             MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index))
 881                 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state);
 882
 883         return 0;
 884
 885 err_destroy_rq:
 886         mlx5e_destroy_rq(rq);
 887 err_free_rq:
 888         mlx5e_free_rq(rq);
 889
 890         return err;
 891 }
 892
 893 void mlx5e_activate_rq(struct mlx5e_rq *rq)
 894 {
 895         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 896         if (rq->icosq) {
 897                 mlx5e_trigger_irq(rq->icosq);
 898         } else {
 899                 local_bh_disable();
 900                 napi_schedule(rq->cq.napi);
 901                 local_bh_enable();
 902         }
 903 }
 904
 905 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 906 {
 907         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 908         synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */
 909 }
 910
 911 void mlx5e_close_rq(struct mlx5e_rq *rq)
 912 {
 913         cancel_work_sync(&rq->dim.work);
 914         if (rq->icosq)
 915                 cancel_work_sync(&rq->icosq->recover_work);
 916         cancel_work_sync(&rq->recover_work);
 917         mlx5e_destroy_rq(rq);
 918         mlx5e_free_rx_descs(rq);
 919         mlx5e_free_rq(rq);
 920 }
 921
 922 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 923 {
 924         kvfree(sq->db.xdpi_fifo.xi);
 925         kvfree(sq->db.wqe_info);
 926 }
 927
 928 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
 929 {
 930         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
 931         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
 932         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 933
 934         xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
 935                                       GFP_KERNEL, numa);
 936         if (!xdpi_fifo->xi)
 937                 return -ENOMEM;
 938
 939         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
 940         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
 941         xdpi_fifo->mask = dsegs_per_wq - 1;
 942
 943         return 0;
 944 }
 945
 946 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 947 {
 948         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 949         int err;
 950
 951         sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
 952                                         GFP_KERNEL, numa);
 953         if (!sq->db.wqe_info)
 954                 return -ENOMEM;
 955
 956         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
 957         if (err) {
 958                 mlx5e_free_xdpsq_db(sq);
 959                 return err;
 960         }
 961
 962         return 0;
 963 }
 964
 965 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 966                              struct mlx5e_params *params,
 967                              struct xsk_buff_pool *xsk_pool,
 968                              struct mlx5e_sq_param *param,
 969                              struct mlx5e_xdpsq *sq,
 970                              bool is_redirect)
 971 {
 972         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 973         struct mlx5_core_dev *mdev = c->mdev;
 974         struct mlx5_wq_cyc *wq = &sq->wq;
 975         int err;
 976
 977         sq->pdev      = c->pdev;
 978         sq->mkey_be   = c->mkey_be;
 979         sq->channel   = c;
 980         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
 981         sq->min_inline_mode = params->tx_min_inline_mode;
 982         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 983         sq->xsk_pool  = xsk_pool;
 984
 985         sq->stats = sq->xsk_pool ?
 986                 &c->priv->channel_stats[c->ix].xsksq :
 987                 is_redirect ?
 988                         &c->priv->channel_stats[c->ix].xdpsq :
 989                         &c->priv->channel_stats[c->ix].rq_xdpsq;
 990
 991         param->wq.db_numa_node = cpu_to_node(c->cpu);
 992         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
 993         if (err)
 994                 return err;
 995         wq->db = &wq->db[MLX5_SND_DBR];
 996
 997         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
 998         if (err)
 999                 goto err_sq_wq_destroy;
1000
1001         return 0;
1002
1003 err_sq_wq_destroy:
1004         mlx5_wq_destroy(&sq->wq_ctrl);
1005
1006         return err;
1007 }
1008
1009 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1010 {
1011         mlx5e_free_xdpsq_db(sq);
1012         mlx5_wq_destroy(&sq->wq_ctrl);
1013 }
1014
1015 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1016 {
1017         kvfree(sq->db.wqe_info);
1018 }
1019
1020 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1021 {
1022         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1023         size_t size;
1024
1025         size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1026         sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1027         if (!sq->db.wqe_info)
1028                 return -ENOMEM;
1029
1030         return 0;
1031 }
1032
1033 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1034 {
1035         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1036                                               recover_work);
1037
1038         mlx5e_reporter_icosq_cqe_err(sq);
1039 }
1040
1041 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1042                              struct mlx5e_sq_param *param,
1043                              struct mlx5e_icosq *sq)
1044 {
1045         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1046         struct mlx5_core_dev *mdev = c->mdev;
1047         struct mlx5_wq_cyc *wq = &sq->wq;
1048         int err;
1049
1050         sq->channel   = c;
1051         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1052         sq->reserved_room = param->stop_room;
1053
1054         param->wq.db_numa_node = cpu_to_node(c->cpu);
1055         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1056         if (err)
1057                 return err;
1058         wq->db = &wq->db[MLX5_SND_DBR];
1059
1060         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1061         if (err)
1062                 goto err_sq_wq_destroy;
1063
1064         INIT_WORK(&sq->recover_work, mlx5e_icosq_err_cqe_work);
1065
1066         return 0;
1067
1068 err_sq_wq_destroy:
1069         mlx5_wq_destroy(&sq->wq_ctrl);
1070
1071         return err;
1072 }
1073
1074 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1075 {
1076         mlx5e_free_icosq_db(sq);
1077         mlx5_wq_destroy(&sq->wq_ctrl);
1078 }
1079
1080 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1081 {
1082         kvfree(sq->db.wqe_info);
1083         kvfree(sq->db.skb_fifo.fifo);
1084         kvfree(sq->db.dma_fifo);
1085 }
1086
1087 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1088 {
1089         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1090         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1091
1092         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1093                                                    sizeof(*sq->db.dma_fifo)),
1094                                         GFP_KERNEL, numa);
1095         sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz,
1096                                                         sizeof(*sq->db.skb_fifo.fifo)),
1097                                         GFP_KERNEL, numa);
1098         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1099                                                    sizeof(*sq->db.wqe_info)),
1100                                         GFP_KERNEL, numa);
1101         if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) {
1102                 mlx5e_free_txqsq_db(sq);
1103                 return -ENOMEM;
1104         }
1105
1106         sq->dma_fifo_mask = df_sz - 1;
1107
1108         sq->db.skb_fifo.pc   = &sq->skb_fifo_pc;
1109         sq->db.skb_fifo.cc   = &sq->skb_fifo_cc;
1110         sq->db.skb_fifo.mask = df_sz - 1;
1111
1112         return 0;
1113 }
1114
1115 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1116                              int txq_ix,
1117                              struct mlx5e_params *params,
1118                              struct mlx5e_sq_param *param,
1119                              struct mlx5e_txqsq *sq,
1120                              int tc)
1121 {
1122         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1123         struct mlx5_core_dev *mdev = c->mdev;
1124         struct mlx5_wq_cyc *wq = &sq->wq;
1125         int err;
1126
1127         sq->pdev      = c->pdev;
1128         sq->tstamp    = c->tstamp;
1129         sq->clock     = &mdev->clock;
1130         sq->mkey_be   = c->mkey_be;
1131         sq->netdev    = c->netdev;
1132         sq->mdev      = c->mdev;
1133         sq->priv      = c->priv;
1134         sq->ch_ix     = c->ix;
1135         sq->txq_ix    = txq_ix;
1136         sq->uar_map   = mdev->mlx5e_res.hw_objs.bfreg.map;
1137         sq->min_inline_mode = params->tx_min_inline_mode;
1138         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1139         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1140         if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1141                 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1142         if (MLX5_IPSEC_DEV(c->priv->mdev))
1143                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1144         if (param->is_mpw)
1145                 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state);
1146         sq->stop_room = param->stop_room;
1147         sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev);
1148
1149         param->wq.db_numa_node = cpu_to_node(c->cpu);
1150         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1151         if (err)
1152                 return err;
1153         wq->db    = &wq->db[MLX5_SND_DBR];
1154
1155         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1156         if (err)
1157                 goto err_sq_wq_destroy;
1158
1159         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1160         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1161
1162         return 0;
1163
1164 err_sq_wq_destroy:
1165         mlx5_wq_destroy(&sq->wq_ctrl);
1166
1167         return err;
1168 }
1169
1170 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1171 {
1172         mlx5e_free_txqsq_db(sq);
1173         mlx5_wq_destroy(&sq->wq_ctrl);
1174 }
1175
1176 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1177                            struct mlx5e_sq_param *param,
1178                            struct mlx5e_create_sq_param *csp,
1179                            u32 *sqn)
1180 {
1181         u8 ts_format;
1182         void *in;
1183         void *sqc;
1184         void *wq;
1185         int inlen;
1186         int err;
1187
1188         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1189                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1190         in = kvzalloc(inlen, GFP_KERNEL);
1191         if (!in)
1192                 return -ENOMEM;
1193
1194         ts_format = mlx5_is_real_time_sq(mdev) ?
1195                             MLX5_TIMESTAMP_FORMAT_REAL_TIME :
1196                             MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
1197         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1198         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1199
1200         memcpy(sqc, param->sqc, sizeof(param->sqc));
1201         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1202         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1203         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1204         MLX5_SET(sqc,  sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn);
1205         MLX5_SET(sqc,  sqc, ts_format, ts_format);
1206
1207
1208         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1209                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1210
1211         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1212         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1213
1214         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1215         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.hw_objs.bfreg.index);
1216         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1217                                           MLX5_ADAPTER_PAGE_SHIFT);
1218         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1219
1220         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1221                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1222
1223         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1224
1225         kvfree(in);
1226
1227         return err;
1228 }
1229
1230 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1231                     struct mlx5e_modify_sq_param *p)
1232 {
1233         u64 bitmask = 0;
1234         void *in;
1235         void *sqc;
1236         int inlen;
1237         int err;
1238
1239         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1240         in = kvzalloc(inlen, GFP_KERNEL);
1241         if (!in)
1242                 return -ENOMEM;
1243
1244         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1245
1246         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1247         MLX5_SET(sqc, sqc, state, p->next_state);
1248         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1249                 bitmask |= 1;
1250                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1251         }
1252         if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) {
1253                 bitmask |= 1 << 2;
1254                 MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id);
1255         }
1256         MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask);
1257
1258         err = mlx5_core_modify_sq(mdev, sqn, in);
1259
1260         kvfree(in);
1261
1262         return err;
1263 }
1264
1265 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1266 {
1267         mlx5_core_destroy_sq(mdev, sqn);
1268 }
1269
1270 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1271                         struct mlx5e_sq_param *param,
1272                         struct mlx5e_create_sq_param *csp,
1273                         u16 qos_queue_group_id,
1274                         u32 *sqn)
1275 {
1276         struct mlx5e_modify_sq_param msp = {0};
1277         int err;
1278
1279         err = mlx5e_create_sq(mdev, param, csp, sqn);
1280         if (err)
1281                 return err;
1282
1283         msp.curr_state = MLX5_SQC_STATE_RST;
1284         msp.next_state = MLX5_SQC_STATE_RDY;
1285         if (qos_queue_group_id) {
1286                 msp.qos_update = true;
1287                 msp.qos_queue_group_id = qos_queue_group_id;
1288         }
1289         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1290         if (err)
1291                 mlx5e_destroy_sq(mdev, *sqn);
1292
1293         return err;
1294 }
1295
1296 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1297                                 struct mlx5e_txqsq *sq, u32 rate);
1298
1299 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1300                      struct mlx5e_params *params, struct mlx5e_sq_param *param,
1301                      struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, u16 qos_qid)
1302 {
1303         struct mlx5e_create_sq_param csp = {};
1304         u32 tx_rate;
1305         int err;
1306
1307         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1308         if (err)
1309                 return err;
1310
1311         if (qos_queue_group_id)
1312                 sq->stats = c->priv->htb.qos_sq_stats[qos_qid];
1313         else
1314                 sq->stats = &c->priv->channel_stats[c->ix].sq[tc];
1315
1316         csp.tisn            = tisn;
1317         csp.tis_lst_sz      = 1;
1318         csp.cqn             = sq->cq.mcq.cqn;
1319         csp.wq_ctrl         = &sq->wq_ctrl;
1320         csp.min_inline_mode = sq->min_inline_mode;
1321         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn);
1322         if (err)
1323                 goto err_free_txqsq;
1324
1325         tx_rate = c->priv->tx_rates[sq->txq_ix];
1326         if (tx_rate)
1327                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1328
1329         if (params->tx_dim_enabled)
1330                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1331
1332         return 0;
1333
1334 err_free_txqsq:
1335         mlx5e_free_txqsq(sq);
1336
1337         return err;
1338 }
1339
1340 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1341 {
1342         sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix);
1343         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1344         netdev_tx_reset_queue(sq->txq);
1345         netif_tx_start_queue(sq->txq);
1346 }
1347
1348 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1349 {
1350         __netif_tx_lock_bh(txq);
1351         netif_tx_stop_queue(txq);
1352         __netif_tx_unlock_bh(txq);
1353 }
1354
1355 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1356 {
1357         struct mlx5_wq_cyc *wq = &sq->wq;
1358
1359         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1360         synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */
1361
1362         mlx5e_tx_disable_queue(sq->txq);
1363
1364         /* last doorbell out, godspeed .. */
1365         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1366                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1367                 struct mlx5e_tx_wqe *nop;
1368
1369                 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1370                         .num_wqebbs = 1,
1371                 };
1372
1373                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1374                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1375         }
1376 }
1377
1378 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1379 {
1380         struct mlx5_core_dev *mdev = sq->mdev;
1381         struct mlx5_rate_limit rl = {0};
1382
1383         cancel_work_sync(&sq->dim.work);
1384         cancel_work_sync(&sq->recover_work);
1385         mlx5e_destroy_sq(mdev, sq->sqn);
1386         if (sq->rate_limit) {
1387                 rl.rate = sq->rate_limit;
1388                 mlx5_rl_remove_rate(mdev, &rl);
1389         }
1390         mlx5e_free_txqsq_descs(sq);
1391         mlx5e_free_txqsq(sq);
1392 }
1393
1394 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1395 {
1396         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1397                                               recover_work);
1398
1399         mlx5e_reporter_tx_err_cqe(sq);
1400 }
1401
1402 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1403                      struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1404 {
1405         struct mlx5e_create_sq_param csp = {};
1406         int err;
1407
1408         err = mlx5e_alloc_icosq(c, param, sq);
1409         if (err)
1410                 return err;
1411
1412         csp.cqn             = sq->cq.mcq.cqn;
1413         csp.wq_ctrl         = &sq->wq_ctrl;
1414         csp.min_inline_mode = params->tx_min_inline_mode;
1415         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1416         if (err)
1417                 goto err_free_icosq;
1418
1419         if (param->is_tls) {
1420                 sq->ktls_resync = mlx5e_ktls_rx_resync_create_resp_list();
1421                 if (IS_ERR(sq->ktls_resync)) {
1422                         err = PTR_ERR(sq->ktls_resync);
1423                         goto err_destroy_icosq;
1424                 }
1425         }
1426         return 0;
1427
1428 err_destroy_icosq:
1429         mlx5e_destroy_sq(c->mdev, sq->sqn);
1430 err_free_icosq:
1431         mlx5e_free_icosq(sq);
1432
1433         return err;
1434 }
1435
1436 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1437 {
1438         set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1439 }
1440
1441 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1442 {
1443         clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1444         synchronize_net(); /* Sync with NAPI. */
1445 }
1446
1447 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1448 {
1449         struct mlx5e_channel *c = sq->channel;
1450
1451         if (sq->ktls_resync)
1452                 mlx5e_ktls_rx_resync_destroy_resp_list(sq->ktls_resync);
1453         mlx5e_destroy_sq(c->mdev, sq->sqn);
1454         mlx5e_free_icosq_descs(sq);
1455         mlx5e_free_icosq(sq);
1456 }
1457
1458 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1459                      struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1460                      struct mlx5e_xdpsq *sq, bool is_redirect)
1461 {
1462         struct mlx5e_create_sq_param csp = {};
1463         int err;
1464
1465         err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect);
1466         if (err)
1467                 return err;
1468
1469         csp.tis_lst_sz      = 1;
1470         csp.tisn            = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1471         csp.cqn             = sq->cq.mcq.cqn;
1472         csp.wq_ctrl         = &sq->wq_ctrl;
1473         csp.min_inline_mode = sq->min_inline_mode;
1474         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1475         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1476         if (err)
1477                 goto err_free_xdpsq;
1478
1479         mlx5e_set_xmit_fp(sq, param->is_mpw);
1480
1481         if (!param->is_mpw) {
1482                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1483                 unsigned int inline_hdr_sz = 0;
1484                 int i;
1485
1486                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1487                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1488                         ds_cnt++;
1489                 }
1490
1491                 /* Pre initialize fixed WQE fields */
1492                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1493                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1494                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1495                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1496                         struct mlx5_wqe_data_seg *dseg;
1497
1498                         sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1499                                 .num_wqebbs = 1,
1500                                 .num_pkts   = 1,
1501                         };
1502
1503                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1504                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1505
1506                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1507                         dseg->lkey = sq->mkey_be;
1508                 }
1509         }
1510
1511         return 0;
1512
1513 err_free_xdpsq:
1514         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1515         mlx5e_free_xdpsq(sq);
1516
1517         return err;
1518 }
1519
1520 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1521 {
1522         struct mlx5e_channel *c = sq->channel;
1523
1524         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1525         synchronize_net(); /* Sync with NAPI. */
1526
1527         mlx5e_destroy_sq(c->mdev, sq->sqn);
1528         mlx5e_free_xdpsq_descs(sq);
1529         mlx5e_free_xdpsq(sq);
1530 }
1531
1532 static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv,
1533                                  struct mlx5e_cq_param *param,
1534                                  struct mlx5e_cq *cq)
1535 {
1536         struct mlx5_core_dev *mdev = priv->mdev;
1537         struct mlx5_core_cq *mcq = &cq->mcq;
1538         int eqn_not_used;
1539         unsigned int irqn;
1540         int err;
1541         u32 i;
1542
1543         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1544         if (err)
1545                 return err;
1546
1547         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1548                                &cq->wq_ctrl);
1549         if (err)
1550                 return err;
1551
1552         mcq->cqe_sz     = 64;
1553         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1554         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1555         *mcq->set_ci_db = 0;
1556         *mcq->arm_db    = 0;
1557         mcq->vector     = param->eq_ix;
1558         mcq->comp       = mlx5e_completion_event;
1559         mcq->event      = mlx5e_cq_error_event;
1560         mcq->irqn       = irqn;
1561
1562         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1563                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1564
1565                 cqe->op_own = 0xf1;
1566         }
1567
1568         cq->mdev = mdev;
1569         cq->netdev = priv->netdev;
1570         cq->priv = priv;
1571
1572         return 0;
1573 }
1574
1575 static int mlx5e_alloc_cq(struct mlx5e_priv *priv,
1576                           struct mlx5e_cq_param *param,
1577                           struct mlx5e_create_cq_param *ccp,
1578                           struct mlx5e_cq *cq)
1579 {
1580         int err;
1581
1582         param->wq.buf_numa_node = ccp->node;
1583         param->wq.db_numa_node  = ccp->node;
1584         param->eq_ix            = ccp->ix;
1585
1586         err = mlx5e_alloc_cq_common(priv, param, cq);
1587
1588         cq->napi     = ccp->napi;
1589         cq->ch_stats = ccp->ch_stats;
1590
1591         return err;
1592 }
1593
1594 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1595 {
1596         mlx5_wq_destroy(&cq->wq_ctrl);
1597 }
1598
1599 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1600 {
1601         u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1602         struct mlx5_core_dev *mdev = cq->mdev;
1603         struct mlx5_core_cq *mcq = &cq->mcq;
1604
1605         void *in;
1606         void *cqc;
1607         int inlen;
1608         unsigned int irqn_not_used;
1609         int eqn;
1610         int err;
1611
1612         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1613         if (err)
1614                 return err;
1615
1616         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1617                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1618         in = kvzalloc(inlen, GFP_KERNEL);
1619         if (!in)
1620                 return -ENOMEM;
1621
1622         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1623
1624         memcpy(cqc, param->cqc, sizeof(param->cqc));
1625
1626         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1627                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1628
1629         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1630         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1631         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1632         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1633                                             MLX5_ADAPTER_PAGE_SHIFT);
1634         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1635
1636         err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1637
1638         kvfree(in);
1639
1640         if (err)
1641                 return err;
1642
1643         mlx5e_cq_arm(cq);
1644
1645         return 0;
1646 }
1647
1648 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1649 {
1650         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1651 }
1652
1653 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
1654                   struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1655                   struct mlx5e_cq *cq)
1656 {
1657         struct mlx5_core_dev *mdev = priv->mdev;
1658         int err;
1659
1660         err = mlx5e_alloc_cq(priv, param, ccp, cq);
1661         if (err)
1662                 return err;
1663
1664         err = mlx5e_create_cq(cq, param);
1665         if (err)
1666                 goto err_free_cq;
1667
1668         if (MLX5_CAP_GEN(mdev, cq_moderation))
1669                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1670         return 0;
1671
1672 err_free_cq:
1673         mlx5e_free_cq(cq);
1674
1675         return err;
1676 }
1677
1678 void mlx5e_close_cq(struct mlx5e_cq *cq)
1679 {
1680         mlx5e_destroy_cq(cq);
1681         mlx5e_free_cq(cq);
1682 }
1683
1684 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1685                              struct mlx5e_params *params,
1686                              struct mlx5e_create_cq_param *ccp,
1687                              struct mlx5e_channel_param *cparam)
1688 {
1689         int err;
1690         int tc;
1691
1692         for (tc = 0; tc < c->num_tc; tc++) {
1693                 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->txq_sq.cqp,
1694                                     ccp, &c->sq[tc].cq);
1695                 if (err)
1696                         goto err_close_tx_cqs;
1697         }
1698
1699         return 0;
1700
1701 err_close_tx_cqs:
1702         for (tc--; tc >= 0; tc--)
1703                 mlx5e_close_cq(&c->sq[tc].cq);
1704
1705         return err;
1706 }
1707
1708 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1709 {
1710         int tc;
1711
1712         for (tc = 0; tc < c->num_tc; tc++)
1713                 mlx5e_close_cq(&c->sq[tc].cq);
1714 }
1715
1716 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1717                           struct mlx5e_params *params,
1718                           struct mlx5e_channel_param *cparam)
1719 {
1720         int err, tc;
1721
1722         for (tc = 0; tc < params->num_tc; tc++) {
1723                 int txq_ix = c->ix + tc * params->num_channels;
1724
1725                 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1726                                        params, &cparam->txq_sq, &c->sq[tc], tc, 0, 0);
1727                 if (err)
1728                         goto err_close_sqs;
1729         }
1730
1731         return 0;
1732
1733 err_close_sqs:
1734         for (tc--; tc >= 0; tc--)
1735                 mlx5e_close_txqsq(&c->sq[tc]);
1736
1737         return err;
1738 }
1739
1740 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1741 {
1742         int tc;
1743
1744         for (tc = 0; tc < c->num_tc; tc++)
1745                 mlx5e_close_txqsq(&c->sq[tc]);
1746 }
1747
1748 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1749                                 struct mlx5e_txqsq *sq, u32 rate)
1750 {
1751         struct mlx5e_priv *priv = netdev_priv(dev);
1752         struct mlx5_core_dev *mdev = priv->mdev;
1753         struct mlx5e_modify_sq_param msp = {0};
1754         struct mlx5_rate_limit rl = {0};
1755         u16 rl_index = 0;
1756         int err;
1757
1758         if (rate == sq->rate_limit)
1759                 /* nothing to do */
1760                 return 0;
1761
1762         if (sq->rate_limit) {
1763                 rl.rate = sq->rate_limit;
1764                 /* remove current rl index to free space to next ones */
1765                 mlx5_rl_remove_rate(mdev, &rl);
1766         }
1767
1768         sq->rate_limit = 0;
1769
1770         if (rate) {
1771                 rl.rate = rate;
1772                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1773                 if (err) {
1774                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1775                                    rate, err);
1776                         return err;
1777                 }
1778         }
1779
1780         msp.curr_state = MLX5_SQC_STATE_RDY;
1781         msp.next_state = MLX5_SQC_STATE_RDY;
1782         msp.rl_index   = rl_index;
1783         msp.rl_update  = true;
1784         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1785         if (err) {
1786                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1787                            rate, err);
1788                 /* remove the rate from the table */
1789                 if (rate)
1790                         mlx5_rl_remove_rate(mdev, &rl);
1791                 return err;
1792         }
1793
1794         sq->rate_limit = rate;
1795         return 0;
1796 }
1797
1798 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1799 {
1800         struct mlx5e_priv *priv = netdev_priv(dev);
1801         struct mlx5_core_dev *mdev = priv->mdev;
1802         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1803         int err = 0;
1804
1805         if (!mlx5_rl_is_supported(mdev)) {
1806                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1807                 return -EINVAL;
1808         }
1809
1810         /* rate is given in Mb/sec, HW config is in Kb/sec */
1811         rate = rate << 10;
1812
1813         /* Check whether rate in valid range, 0 is always valid */
1814         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1815                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1816                 return -ERANGE;
1817         }
1818
1819         mutex_lock(&priv->state_lock);
1820         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1821                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1822         if (!err)
1823                 priv->tx_rates[index] = rate;
1824         mutex_unlock(&priv->state_lock);
1825
1826         return err;
1827 }
1828
1829 static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
1830                              struct mlx5e_rq_param *rq_params)
1831 {
1832         int err;
1833
1834         err = mlx5e_init_rxq_rq(c, params, &c->rq);
1835         if (err)
1836                 return err;
1837
1838         return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), &c->rq);
1839 }
1840
1841 static int mlx5e_open_queues(struct mlx5e_channel *c,
1842                              struct mlx5e_params *params,
1843                              struct mlx5e_channel_param *cparam)
1844 {
1845         struct dim_cq_moder icocq_moder = {0, 0};
1846         struct mlx5e_create_cq_param ccp;
1847         int err;
1848
1849         mlx5e_build_create_cq_param(&ccp, c);
1850
1851         err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->async_icosq.cqp, &ccp,
1852                             &c->async_icosq.cq);
1853         if (err)
1854                 return err;
1855
1856         err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->icosq.cqp, &ccp,
1857                             &c->icosq.cq);
1858         if (err)
1859                 goto err_close_async_icosq_cq;
1860
1861         err = mlx5e_open_tx_cqs(c, params, &ccp, cparam);
1862         if (err)
1863                 goto err_close_icosq_cq;
1864
1865         err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp,
1866                             &c->xdpsq.cq);
1867         if (err)
1868                 goto err_close_tx_cqs;
1869
1870         err = mlx5e_open_cq(c->priv, params->rx_cq_moderation, &cparam->rq.cqp, &ccp,
1871                             &c->rq.cq);
1872         if (err)
1873                 goto err_close_xdp_tx_cqs;
1874
1875         err = c->xdp ? mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp,
1876                                      &ccp, &c->rq_xdpsq.cq) : 0;
1877         if (err)
1878                 goto err_close_rx_cq;
1879
1880         spin_lock_init(&c->async_icosq_lock);
1881
1882         err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq);
1883         if (err)
1884                 goto err_close_xdpsq_cq;
1885
1886         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1887         if (err)
1888                 goto err_close_async_icosq;
1889
1890         err = mlx5e_open_sqs(c, params, cparam);
1891         if (err)
1892                 goto err_close_icosq;
1893
1894         err = mlx5e_open_rxq_rq(c, params, &cparam->rq);
1895         if (err)
1896                 goto err_close_sqs;
1897
1898         if (c->xdp) {
1899                 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1900                                        &c->rq_xdpsq, false);
1901                 if (err)
1902                         goto err_close_rq;
1903         }
1904
1905         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1906         if (err)
1907                 goto err_close_xdp_sq;
1908
1909         return 0;
1910
1911 err_close_xdp_sq:
1912         if (c->xdp)
1913                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1914
1915 err_close_rq:
1916         mlx5e_close_rq(&c->rq);
1917
1918 err_close_sqs:
1919         mlx5e_close_sqs(c);
1920
1921 err_close_icosq:
1922         mlx5e_close_icosq(&c->icosq);
1923
1924 err_close_async_icosq:
1925         mlx5e_close_icosq(&c->async_icosq);
1926
1927 err_close_xdpsq_cq:
1928         if (c->xdp)
1929                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1930
1931 err_close_rx_cq:
1932         mlx5e_close_cq(&c->rq.cq);
1933
1934 err_close_xdp_tx_cqs:
1935         mlx5e_close_cq(&c->xdpsq.cq);
1936
1937 err_close_tx_cqs:
1938         mlx5e_close_tx_cqs(c);
1939
1940 err_close_icosq_cq:
1941         mlx5e_close_cq(&c->icosq.cq);
1942
1943 err_close_async_icosq_cq:
1944         mlx5e_close_cq(&c->async_icosq.cq);
1945
1946         return err;
1947 }
1948
1949 static void mlx5e_close_queues(struct mlx5e_channel *c)
1950 {
1951         mlx5e_close_xdpsq(&c->xdpsq);
1952         if (c->xdp)
1953                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1954         mlx5e_close_rq(&c->rq);
1955         mlx5e_close_sqs(c);
1956         mlx5e_close_icosq(&c->icosq);
1957         mlx5e_close_icosq(&c->async_icosq);
1958         if (c->xdp)
1959                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1960         mlx5e_close_cq(&c->rq.cq);
1961         mlx5e_close_cq(&c->xdpsq.cq);
1962         mlx5e_close_tx_cqs(c);
1963         mlx5e_close_cq(&c->icosq.cq);
1964         mlx5e_close_cq(&c->async_icosq.cq);
1965 }
1966
1967 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
1968 {
1969         u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
1970
1971         return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
1972 }
1973
1974 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1975                               struct mlx5e_params *params,
1976                               struct mlx5e_channel_param *cparam,
1977                               struct xsk_buff_pool *xsk_pool,
1978                               struct mlx5e_channel **cp)
1979 {
1980         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1981         struct net_device *netdev = priv->netdev;
1982         struct mlx5e_xsk_param xsk;
1983         struct mlx5e_channel *c;
1984         unsigned int irq;
1985         int err;
1986         int eqn;
1987
1988         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1989         if (err)
1990                 return err;
1991
1992         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1993         if (!c)
1994                 return -ENOMEM;
1995
1996         c->priv     = priv;
1997         c->mdev     = priv->mdev;
1998         c->tstamp   = &priv->tstamp;
1999         c->ix       = ix;
2000         c->cpu      = cpu;
2001         c->pdev     = mlx5_core_dma_dev(priv->mdev);
2002         c->netdev   = priv->netdev;
2003         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey.key);
2004         c->num_tc   = params->num_tc;
2005         c->xdp      = !!params->xdp_prog;
2006         c->stats    = &priv->channel_stats[ix].ch;
2007         c->aff_mask = irq_get_effective_affinity_mask(irq);
2008         c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
2009
2010         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
2011
2012         err = mlx5e_open_queues(c, params, cparam);
2013         if (unlikely(err))
2014                 goto err_napi_del;
2015
2016         if (xsk_pool) {
2017                 mlx5e_build_xsk_param(xsk_pool, &xsk);
2018                 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c);
2019                 if (unlikely(err))
2020                         goto err_close_queues;
2021         }
2022
2023         *cp = c;
2024
2025         return 0;
2026
2027 err_close_queues:
2028         mlx5e_close_queues(c);
2029
2030 err_napi_del:
2031         netif_napi_del(&c->napi);
2032
2033         kvfree(c);
2034
2035         return err;
2036 }
2037
2038 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2039 {
2040         int tc;
2041
2042         napi_enable(&c->napi);
2043
2044         for (tc = 0; tc < c->num_tc; tc++)
2045                 mlx5e_activate_txqsq(&c->sq[tc]);
2046         mlx5e_activate_icosq(&c->icosq);
2047         mlx5e_activate_icosq(&c->async_icosq);
2048         mlx5e_activate_rq(&c->rq);
2049
2050         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2051                 mlx5e_activate_xsk(c);
2052 }
2053
2054 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2055 {
2056         int tc;
2057
2058         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2059                 mlx5e_deactivate_xsk(c);
2060
2061         mlx5e_deactivate_rq(&c->rq);
2062         mlx5e_deactivate_icosq(&c->async_icosq);
2063         mlx5e_deactivate_icosq(&c->icosq);
2064         for (tc = 0; tc < c->num_tc; tc++)
2065                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2066         mlx5e_qos_deactivate_queues(c);
2067
2068         napi_disable(&c->napi);
2069 }
2070
2071 static void mlx5e_close_channel(struct mlx5e_channel *c)
2072 {
2073         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2074                 mlx5e_close_xsk(c);
2075         mlx5e_close_queues(c);
2076         mlx5e_qos_close_queues(c);
2077         netif_napi_del(&c->napi);
2078
2079         kvfree(c);
2080 }
2081
2082 int mlx5e_open_channels(struct mlx5e_priv *priv,
2083                         struct mlx5e_channels *chs)
2084 {
2085         struct mlx5e_channel_param *cparam;
2086         int err = -ENOMEM;
2087         int i;
2088
2089         chs->num = chs->params.num_channels;
2090
2091         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2092         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2093         if (!chs->c || !cparam)
2094                 goto err_free;
2095
2096         err = mlx5e_build_channel_param(priv->mdev, &chs->params, priv->q_counter, cparam);
2097         if (err)
2098                 goto err_free;
2099
2100         for (i = 0; i < chs->num; i++) {
2101                 struct xsk_buff_pool *xsk_pool = NULL;
2102
2103                 if (chs->params.xdp_prog)
2104                         xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i);
2105
2106                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]);
2107                 if (err)
2108                         goto err_close_channels;
2109         }
2110
2111         if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) {
2112                 err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp);
2113                 if (err)
2114                         goto err_close_channels;
2115         }
2116
2117         err = mlx5e_qos_open_queues(priv, chs);
2118         if (err)
2119                 goto err_close_ptp;
2120
2121         mlx5e_health_channels_update(priv);
2122         kvfree(cparam);
2123         return 0;
2124
2125 err_close_ptp:
2126         if (chs->ptp)
2127                 mlx5e_ptp_close(chs->ptp);
2128
2129 err_close_channels:
2130         for (i--; i >= 0; i--)
2131                 mlx5e_close_channel(chs->c[i]);
2132
2133 err_free:
2134         kfree(chs->c);
2135         kvfree(cparam);
2136         chs->num = 0;
2137         return err;
2138 }
2139
2140 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2141 {
2142         int i;
2143
2144         for (i = 0; i < chs->num; i++)
2145                 mlx5e_activate_channel(chs->c[i]);
2146
2147         if (chs->ptp)
2148                 mlx5e_ptp_activate_channel(chs->ptp);
2149 }
2150
2151 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2152
2153 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2154 {
2155         int err = 0;
2156         int i;
2157
2158         for (i = 0; i < chs->num; i++) {
2159                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2160
2161                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2162
2163                 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2164                  * doesn't provide any Fill Ring entries at the setup stage.
2165                  */
2166         }
2167
2168         return err ? -ETIMEDOUT : 0;
2169 }
2170
2171 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2172 {
2173         int i;
2174
2175         if (chs->ptp)
2176                 mlx5e_ptp_deactivate_channel(chs->ptp);
2177
2178         for (i = 0; i < chs->num; i++)
2179                 mlx5e_deactivate_channel(chs->c[i]);
2180 }
2181
2182 void mlx5e_close_channels(struct mlx5e_channels *chs)
2183 {
2184         int i;
2185
2186         if (chs->ptp) {
2187                 mlx5e_ptp_close(chs->ptp);
2188                 chs->ptp = NULL;
2189         }
2190         for (i = 0; i < chs->num; i++)
2191                 mlx5e_close_channel(chs->c[i]);
2192
2193         kfree(chs->c);
2194         chs->num = 0;
2195 }
2196
2197 static int
2198 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2199 {
2200         struct mlx5_core_dev *mdev = priv->mdev;
2201         void *rqtc;
2202         int inlen;
2203         int err;
2204         u32 *in;
2205         int i;
2206
2207         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2208         in = kvzalloc(inlen, GFP_KERNEL);
2209         if (!in)
2210                 return -ENOMEM;
2211
2212         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2213
2214         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2215         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2216
2217         for (i = 0; i < sz; i++)
2218                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2219
2220         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2221         if (!err)
2222                 rqt->enabled = true;
2223
2224         kvfree(in);
2225         return err;
2226 }
2227
2228 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2229 {
2230         rqt->enabled = false;
2231         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2232 }
2233
2234 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2235 {
2236         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2237         int err;
2238
2239         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2240         if (err)
2241                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2242         return err;
2243 }
2244
2245 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n)
2246 {
2247         int err;
2248         int ix;
2249
2250         for (ix = 0; ix < n; ix++) {
2251                 err = mlx5e_create_rqt(priv, 1 /*size */, &tirs[ix].rqt);
2252                 if (unlikely(err))
2253                         goto err_destroy_rqts;
2254         }
2255
2256         return 0;
2257
2258 err_destroy_rqts:
2259         mlx5_core_warn(priv->mdev, "create rqts failed, %d\n", err);
2260         for (ix--; ix >= 0; ix--)
2261                 mlx5e_destroy_rqt(priv, &tirs[ix].rqt);
2262
2263         return err;
2264 }
2265
2266 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n)
2267 {
2268         int i;
2269
2270         for (i = 0; i < n; i++)
2271                 mlx5e_destroy_rqt(priv, &tirs[i].rqt);
2272 }
2273
2274 static int mlx5e_rx_hash_fn(int hfunc)
2275 {
2276         return (hfunc == ETH_RSS_HASH_TOP) ?
2277                MLX5_RX_HASH_FN_TOEPLITZ :
2278                MLX5_RX_HASH_FN_INVERTED_XOR8;
2279 }
2280
2281 int mlx5e_bits_invert(unsigned long a, int size)
2282 {
2283         int inv = 0;
2284         int i;
2285
2286         for (i = 0; i < size; i++)
2287                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2288
2289         return inv;
2290 }
2291
2292 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2293                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2294 {
2295         int i;
2296
2297         for (i = 0; i < sz; i++) {
2298                 u32 rqn;
2299
2300                 if (rrp.is_rss) {
2301                         int ix = i;
2302
2303                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2304                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2305
2306                         ix = priv->rss_params.indirection_rqt[ix];
2307                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2308                 } else {
2309                         rqn = rrp.rqn;
2310                 }
2311                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2312         }
2313 }
2314
2315 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2316                        struct mlx5e_redirect_rqt_param rrp)
2317 {
2318         struct mlx5_core_dev *mdev = priv->mdev;
2319         void *rqtc;
2320         int inlen;
2321         u32 *in;
2322         int err;
2323
2324         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2325         in = kvzalloc(inlen, GFP_KERNEL);
2326         if (!in)
2327                 return -ENOMEM;
2328
2329         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2330
2331         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2332         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2333         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2334         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2335
2336         kvfree(in);
2337         return err;
2338 }
2339
2340 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2341                                 struct mlx5e_redirect_rqt_param rrp)
2342 {
2343         if (!rrp.is_rss)
2344                 return rrp.rqn;
2345
2346         if (ix >= rrp.rss.channels->num)
2347                 return priv->drop_rq.rqn;
2348
2349         return rrp.rss.channels->c[ix]->rq.rqn;
2350 }
2351
2352 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2353                                 struct mlx5e_redirect_rqt_param rrp,
2354                                 struct mlx5e_redirect_rqt_param *ptp_rrp)
2355 {
2356         u32 rqtn;
2357         int ix;
2358
2359         if (priv->indir_rqt.enabled) {
2360                 /* RSS RQ table */
2361                 rqtn = priv->indir_rqt.rqtn;
2362                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2363         }
2364
2365         for (ix = 0; ix < priv->max_nch; ix++) {
2366                 struct mlx5e_redirect_rqt_param direct_rrp = {
2367                         .is_rss = false,
2368                         {
2369                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2370                         },
2371                 };
2372
2373                 /* Direct RQ Tables */
2374                 if (!priv->direct_tir[ix].rqt.enabled)
2375                         continue;
2376
2377                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2378                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2379         }
2380         if (ptp_rrp) {
2381                 rqtn = priv->ptp_tir.rqt.rqtn;
2382                 mlx5e_redirect_rqt(priv, rqtn, 1, *ptp_rrp);
2383         }
2384 }
2385
2386 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2387                                             struct mlx5e_channels *chs)
2388 {
2389         bool rx_ptp_support = priv->profile->rx_ptp_support;
2390         struct mlx5e_redirect_rqt_param *ptp_rrp_p = NULL;
2391         struct mlx5e_redirect_rqt_param rrp = {
2392                 .is_rss        = true,
2393                 {
2394                         .rss = {
2395                                 .channels  = chs,
2396                                 .hfunc     = priv->rss_params.hfunc,
2397                         }
2398                 },
2399         };
2400         struct mlx5e_redirect_rqt_param ptp_rrp;
2401
2402         if (rx_ptp_support) {
2403                 u32 ptp_rqn;
2404
2405                 ptp_rrp.is_rss = false;
2406                 ptp_rrp.rqn = mlx5e_ptp_get_rqn(priv->channels.ptp, &ptp_rqn) ?
2407                               priv->drop_rq.rqn : ptp_rqn;
2408                 ptp_rrp_p = &ptp_rrp;
2409         }
2410         mlx5e_redirect_rqts(priv, rrp, ptp_rrp_p);
2411 }
2412
2413 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2414 {
2415         bool rx_ptp_support = priv->profile->rx_ptp_support;
2416         struct mlx5e_redirect_rqt_param drop_rrp = {
2417                 .is_rss = false,
2418                 {
2419                         .rqn = priv->drop_rq.rqn,
2420                 },
2421         };
2422
2423         mlx5e_redirect_rqts(priv, drop_rrp, rx_ptp_support ? &drop_rrp : NULL);
2424 }
2425
2426 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2427         [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2428                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2429                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2430         },
2431         [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2432                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2433                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2434         },
2435         [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2436                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2437                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2438         },
2439         [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2440                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2441                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2442         },
2443         [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2444                                      .l4_prot_type = 0,
2445                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2446         },
2447         [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2448                                      .l4_prot_type = 0,
2449                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2450         },
2451         [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2452                                       .l4_prot_type = 0,
2453                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2454         },
2455         [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2456                                       .l4_prot_type = 0,
2457                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2458         },
2459         [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2460                             .l4_prot_type = 0,
2461                             .rx_hash_fields = MLX5_HASH_IP,
2462         },
2463         [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2464                             .l4_prot_type = 0,
2465                             .rx_hash_fields = MLX5_HASH_IP,
2466         },
2467 };
2468
2469 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2470 {
2471         return tirc_default_config[tt];
2472 }
2473
2474 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2475 {
2476         if (!params->lro_en)
2477                 return;
2478
2479 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2480
2481         MLX5_SET(tirc, tirc, lro_enable_mask,
2482                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2483                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2484         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2485                  (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2486         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2487 }
2488
2489 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2490                                     const struct mlx5e_tirc_config *ttconfig,
2491                                     void *tirc, bool inner)
2492 {
2493         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2494                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2495
2496         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2497         if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2498                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2499                                              rx_hash_toeplitz_key);
2500                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2501                                                rx_hash_toeplitz_key);
2502
2503                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2504                 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2505         }
2506         MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2507                  ttconfig->l3_prot_type);
2508         MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2509                  ttconfig->l4_prot_type);
2510         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2511                  ttconfig->rx_hash_fields);
2512 }
2513
2514 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2515                                         enum mlx5e_traffic_types tt,
2516                                         u32 rx_hash_fields)
2517 {
2518         *ttconfig                = tirc_default_config[tt];
2519         ttconfig->rx_hash_fields = rx_hash_fields;
2520 }
2521
2522 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in)
2523 {
2524         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2525         struct mlx5e_rss_params *rss = &priv->rss_params;
2526         struct mlx5_core_dev *mdev = priv->mdev;
2527         int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2528         struct mlx5e_tirc_config ttconfig;
2529         int tt;
2530
2531         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2532
2533         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2534                 memset(tirc, 0, ctxlen);
2535                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2536                                             rss->rx_hash_fields[tt]);
2537                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2538                 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
2539         }
2540
2541         /* Verify inner tirs resources allocated */
2542         if (!priv->inner_indir_tir[0].tirn)
2543                 return;
2544
2545         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2546                 memset(tirc, 0, ctxlen);
2547                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2548                                             rss->rx_hash_fields[tt]);
2549                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2550                 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in);
2551         }
2552 }
2553
2554 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2555 {
2556         struct mlx5_core_dev *mdev = priv->mdev;
2557
2558         void *in;
2559         void *tirc;
2560         int inlen;
2561         int err;
2562         int tt;
2563         int ix;
2564
2565         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2566         in = kvzalloc(inlen, GFP_KERNEL);
2567         if (!in)
2568                 return -ENOMEM;
2569
2570         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2571         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2572
2573         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2574
2575         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2576                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in);
2577                 if (err)
2578                         goto free_in;
2579         }
2580
2581         for (ix = 0; ix < priv->max_nch; ix++) {
2582                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn, in);
2583                 if (err)
2584                         goto free_in;
2585         }
2586
2587 free_in:
2588         kvfree(in);
2589
2590         return err;
2591 }
2592
2593 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_lro);
2594
2595 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2596                          struct mlx5e_params *params, u16 mtu)
2597 {
2598         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2599         int err;
2600
2601         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2602         if (err)
2603                 return err;
2604
2605         /* Update vport context MTU */
2606         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2607         return 0;
2608 }
2609
2610 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2611                             struct mlx5e_params *params, u16 *mtu)
2612 {
2613         u16 hw_mtu = 0;
2614         int err;
2615
2616         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2617         if (err || !hw_mtu) /* fallback to port oper mtu */
2618                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2619
2620         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2621 }
2622
2623 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2624 {
2625         struct mlx5e_params *params = &priv->channels.params;
2626         struct net_device *netdev = priv->netdev;
2627         struct mlx5_core_dev *mdev = priv->mdev;
2628         u16 mtu;
2629         int err;
2630
2631         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2632         if (err)
2633                 return err;
2634
2635         mlx5e_query_mtu(mdev, params, &mtu);
2636         if (mtu != params->sw_mtu)
2637                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2638                             __func__, mtu, params->sw_mtu);
2639
2640         params->sw_mtu = mtu;
2641         return 0;
2642 }
2643
2644 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2645
2646 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2647 {
2648         struct mlx5e_params *params = &priv->channels.params;
2649         struct net_device *netdev   = priv->netdev;
2650         struct mlx5_core_dev *mdev  = priv->mdev;
2651         u16 max_mtu;
2652
2653         /* MTU range: 68 - hw-specific max */
2654         netdev->min_mtu = ETH_MIN_MTU;
2655
2656         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2657         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2658                                 ETH_MAX_MTU);
2659 }
2660
2661 static void mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc)
2662 {
2663         int tc;
2664
2665         netdev_reset_tc(netdev);
2666
2667         if (ntc == 1)
2668                 return;
2669
2670         netdev_set_num_tc(netdev, ntc);
2671
2672         /* Map netdev TCs to offset 0
2673          * We have our own UP to TXQ mapping for QoS
2674          */
2675         for (tc = 0; tc < ntc; tc++)
2676                 netdev_set_tc_queue(netdev, tc, nch, 0);
2677 }
2678
2679 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv)
2680 {
2681         int qos_queues, nch, ntc, num_txqs, err;
2682
2683         qos_queues = mlx5e_qos_cur_leaf_nodes(priv);
2684
2685         nch = priv->channels.params.num_channels;
2686         ntc = priv->channels.params.num_tc;
2687         num_txqs = nch * ntc + qos_queues;
2688         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS))
2689                 num_txqs += ntc;
2690
2691         mlx5e_dbg(DRV, priv, "Setting num_txqs %d\n", num_txqs);
2692         err = netif_set_real_num_tx_queues(priv->netdev, num_txqs);
2693         if (err)
2694                 netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2695
2696         return err;
2697 }
2698
2699 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2700 {
2701         struct net_device *netdev = priv->netdev;
2702         int old_num_txqs, old_ntc;
2703         int num_rxqs, nch, ntc;
2704         int err;
2705
2706         old_num_txqs = netdev->real_num_tx_queues;
2707         old_ntc = netdev->num_tc ? : 1;
2708
2709         nch = priv->channels.params.num_channels;
2710         ntc = priv->channels.params.num_tc;
2711         num_rxqs = nch * priv->profile->rq_groups;
2712
2713         mlx5e_netdev_set_tcs(netdev, nch, ntc);
2714
2715         err = mlx5e_update_tx_netdev_queues(priv);
2716         if (err)
2717                 goto err_tcs;
2718         err = netif_set_real_num_rx_queues(netdev, num_rxqs);
2719         if (err) {
2720                 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
2721                 goto err_txqs;
2722         }
2723
2724         return 0;
2725
2726 err_txqs:
2727         /* netif_set_real_num_rx_queues could fail only when nch increased. Only
2728          * one of nch and ntc is changed in this function. That means, the call
2729          * to netif_set_real_num_tx_queues below should not fail, because it
2730          * decreases the number of TX queues.
2731          */
2732         WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2733
2734 err_tcs:
2735         mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc);
2736         return err;
2737 }
2738
2739 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2740                                            struct mlx5e_params *params)
2741 {
2742         struct mlx5_core_dev *mdev = priv->mdev;
2743         int num_comp_vectors, ix, irq;
2744
2745         num_comp_vectors = mlx5_comp_vectors_count(mdev);
2746
2747         for (ix = 0; ix < params->num_channels; ix++) {
2748                 cpumask_clear(priv->scratchpad.cpumask);
2749
2750                 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2751                         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq));
2752
2753                         cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
2754                 }
2755
2756                 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
2757         }
2758 }
2759
2760 int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2761 {
2762         u16 count = priv->channels.params.num_channels;
2763         int err;
2764
2765         err = mlx5e_update_netdev_queues(priv);
2766         if (err)
2767                 return err;
2768
2769         mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
2770
2771         if (!netif_is_rxfh_configured(priv->netdev))
2772                 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
2773                                               MLX5E_INDIR_RQT_SIZE, count);
2774
2775         return 0;
2776 }
2777
2778 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
2779
2780 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2781 {
2782         int i, ch, tc, num_tc;
2783
2784         ch = priv->channels.num;
2785         num_tc = priv->channels.params.num_tc;
2786
2787         for (i = 0; i < ch; i++) {
2788                 for (tc = 0; tc < num_tc; tc++) {
2789                         struct mlx5e_channel *c = priv->channels.c[i];
2790                         struct mlx5e_txqsq *sq = &c->sq[tc];
2791
2792                         priv->txq2sq[sq->txq_ix] = sq;
2793                         priv->channel_tc2realtxq[i][tc] = i + tc * ch;
2794                 }
2795         }
2796
2797         if (!priv->channels.ptp)
2798                 return;
2799
2800         if (!test_bit(MLX5E_PTP_STATE_TX, priv->channels.ptp->state))
2801                 return;
2802
2803         for (tc = 0; tc < num_tc; tc++) {
2804                 struct mlx5e_ptp *c = priv->channels.ptp;
2805                 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq;
2806
2807                 priv->txq2sq[sq->txq_ix] = sq;
2808                 priv->port_ptp_tc2realtxq[tc] = priv->num_tc_x_num_ch + tc;
2809         }
2810 }
2811
2812 static void mlx5e_update_num_tc_x_num_ch(struct mlx5e_priv *priv)
2813 {
2814         /* Sync with mlx5e_select_queue. */
2815         WRITE_ONCE(priv->num_tc_x_num_ch,
2816                    priv->channels.params.num_tc * priv->channels.num);
2817 }
2818
2819 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2820 {
2821         mlx5e_update_num_tc_x_num_ch(priv);
2822         mlx5e_build_txq_maps(priv);
2823         mlx5e_activate_channels(&priv->channels);
2824         mlx5e_qos_activate_queues(priv);
2825         mlx5e_xdp_tx_enable(priv);
2826         netif_tx_start_all_queues(priv->netdev);
2827
2828         if (mlx5e_is_vport_rep(priv))
2829                 mlx5e_add_sqs_fwd_rules(priv);
2830
2831         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2832         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2833
2834         mlx5e_xsk_redirect_rqts_to_channels(priv, &priv->channels);
2835 }
2836
2837 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2838 {
2839         mlx5e_xsk_redirect_rqts_to_drop(priv, &priv->channels);
2840
2841         mlx5e_redirect_rqts_to_drop(priv);
2842
2843         if (mlx5e_is_vport_rep(priv))
2844                 mlx5e_remove_sqs_fwd_rules(priv);
2845
2846         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2847          * polling for inactive tx queues.
2848          */
2849         netif_tx_stop_all_queues(priv->netdev);
2850         netif_tx_disable(priv->netdev);
2851         mlx5e_xdp_tx_disable(priv);
2852         mlx5e_deactivate_channels(&priv->channels);
2853 }
2854
2855 static int mlx5e_switch_priv_params(struct mlx5e_priv *priv,
2856                                     struct mlx5e_params *new_params,
2857                                     mlx5e_fp_preactivate preactivate,
2858                                     void *context)
2859 {
2860         struct mlx5e_params old_params;
2861
2862         old_params = priv->channels.params;
2863         priv->channels.params = *new_params;
2864
2865         if (preactivate) {
2866                 int err;
2867
2868                 err = preactivate(priv, context);
2869                 if (err) {
2870                         priv->channels.params = old_params;
2871                         return err;
2872                 }
2873         }
2874
2875         return 0;
2876 }
2877
2878 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2879                                       struct mlx5e_channels *new_chs,
2880                                       mlx5e_fp_preactivate preactivate,
2881                                       void *context)
2882 {
2883         struct net_device *netdev = priv->netdev;
2884         struct mlx5e_channels old_chs;
2885         int carrier_ok;
2886         int err = 0;
2887
2888         carrier_ok = netif_carrier_ok(netdev);
2889         netif_carrier_off(netdev);
2890
2891         mlx5e_deactivate_priv_channels(priv);
2892
2893         old_chs = priv->channels;
2894         priv->channels = *new_chs;
2895
2896         /* New channels are ready to roll, call the preactivate hook if needed
2897          * to modify HW settings or update kernel parameters.
2898          */
2899         if (preactivate) {
2900                 err = preactivate(priv, context);
2901                 if (err) {
2902                         priv->channels = old_chs;
2903                         goto out;
2904                 }
2905         }
2906
2907         mlx5e_close_channels(&old_chs);
2908         priv->profile->update_rx(priv);
2909
2910 out:
2911         mlx5e_activate_priv_channels(priv);
2912
2913         /* return carrier back if needed */
2914         if (carrier_ok)
2915                 netif_carrier_on(netdev);
2916
2917         return err;
2918 }
2919
2920 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
2921                              struct mlx5e_params *params,
2922                              mlx5e_fp_preactivate preactivate,
2923                              void *context, bool reset)
2924 {
2925         struct mlx5e_channels new_chs = {};
2926         int err;
2927
2928         reset &= test_bit(MLX5E_STATE_OPENED, &priv->state);
2929         if (!reset)
2930                 return mlx5e_switch_priv_params(priv, params, preactivate, context);
2931
2932         new_chs.params = *params;
2933         err = mlx5e_open_channels(priv, &new_chs);
2934         if (err)
2935                 return err;
2936         err = mlx5e_switch_priv_channels(priv, &new_chs, preactivate, context);
2937         if (err)
2938                 mlx5e_close_channels(&new_chs);
2939
2940         return err;
2941 }
2942
2943 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2944 {
2945         return mlx5e_safe_switch_params(priv, &priv->channels.params, NULL, NULL, true);
2946 }
2947
2948 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2949 {
2950         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2951         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2952 }
2953
2954 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev,
2955                                      enum mlx5_port_status state)
2956 {
2957         struct mlx5_eswitch *esw = mdev->priv.eswitch;
2958         int vport_admin_state;
2959
2960         mlx5_set_port_admin_status(mdev, state);
2961
2962         if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS ||
2963             !MLX5_CAP_GEN(mdev, uplink_follow))
2964                 return;
2965
2966         if (state == MLX5_PORT_UP)
2967                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO;
2968         else
2969                 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2970
2971         mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state);
2972 }
2973
2974 int mlx5e_open_locked(struct net_device *netdev)
2975 {
2976         struct mlx5e_priv *priv = netdev_priv(netdev);
2977         int err;
2978
2979         set_bit(MLX5E_STATE_OPENED, &priv->state);
2980
2981         err = mlx5e_open_channels(priv, &priv->channels);
2982         if (err)
2983                 goto err_clear_state_opened_flag;
2984
2985         priv->profile->update_rx(priv);
2986         mlx5e_activate_priv_channels(priv);
2987         mlx5e_apply_traps(priv, true);
2988         if (priv->profile->update_carrier)
2989                 priv->profile->update_carrier(priv);
2990
2991         mlx5e_queue_update_stats(priv);
2992         return 0;
2993
2994 err_clear_state_opened_flag:
2995         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2996         return err;
2997 }
2998
2999 int mlx5e_open(struct net_device *netdev)
3000 {
3001         struct mlx5e_priv *priv = netdev_priv(netdev);
3002         int err;
3003
3004         mutex_lock(&priv->state_lock);
3005         err = mlx5e_open_locked(netdev);
3006         if (!err)
3007                 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP);
3008         mutex_unlock(&priv->state_lock);
3009
3010         return err;
3011 }
3012
3013 int mlx5e_close_locked(struct net_device *netdev)
3014 {
3015         struct mlx5e_priv *priv = netdev_priv(netdev);
3016
3017         /* May already be CLOSED in case a previous configuration operation
3018          * (e.g RX/TX queue size change) that involves close&open failed.
3019          */
3020         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3021                 return 0;
3022
3023         mlx5e_apply_traps(priv, false);
3024         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3025
3026         netif_carrier_off(priv->netdev);
3027         mlx5e_deactivate_priv_channels(priv);
3028         mlx5e_close_channels(&priv->channels);
3029
3030         return 0;
3031 }
3032
3033 int mlx5e_close(struct net_device *netdev)
3034 {
3035         struct mlx5e_priv *priv = netdev_priv(netdev);
3036         int err;
3037
3038         if (!netif_device_present(netdev))
3039                 return -ENODEV;
3040
3041         mutex_lock(&priv->state_lock);
3042         mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN);
3043         err = mlx5e_close_locked(netdev);
3044         mutex_unlock(&priv->state_lock);
3045
3046         return err;
3047 }
3048
3049 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq)
3050 {
3051         mlx5_wq_destroy(&rq->wq_ctrl);
3052 }
3053
3054 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3055                                struct mlx5e_rq *rq,
3056                                struct mlx5e_rq_param *param)
3057 {
3058         void *rqc = param->rqc;
3059         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3060         int err;
3061
3062         param->wq.db_numa_node = param->wq.buf_numa_node;
3063
3064         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3065                                  &rq->wq_ctrl);
3066         if (err)
3067                 return err;
3068
3069         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3070         xdp_rxq_info_unused(&rq->xdp_rxq);
3071
3072         rq->mdev = mdev;
3073
3074         return 0;
3075 }
3076
3077 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv,
3078                                struct mlx5e_cq *cq,
3079                                struct mlx5e_cq_param *param)
3080 {
3081         struct mlx5_core_dev *mdev = priv->mdev;
3082
3083         param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
3084         param->wq.db_numa_node  = dev_to_node(mlx5_core_dma_dev(mdev));
3085
3086         return mlx5e_alloc_cq_common(priv, param, cq);
3087 }
3088
3089 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3090                        struct mlx5e_rq *drop_rq)
3091 {
3092         struct mlx5_core_dev *mdev = priv->mdev;
3093         struct mlx5e_cq_param cq_param = {};
3094         struct mlx5e_rq_param rq_param = {};
3095         struct mlx5e_cq *cq = &drop_rq->cq;
3096         int err;
3097
3098         mlx5e_build_drop_rq_param(mdev, priv->drop_rq_q_counter, &rq_param);
3099
3100         err = mlx5e_alloc_drop_cq(priv, cq, &cq_param);
3101         if (err)
3102                 return err;
3103
3104         err = mlx5e_create_cq(cq, &cq_param);
3105         if (err)
3106                 goto err_free_cq;
3107
3108         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3109         if (err)
3110                 goto err_destroy_cq;
3111
3112         err = mlx5e_create_rq(drop_rq, &rq_param);
3113         if (err)
3114                 goto err_free_rq;
3115
3116         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3117         if (err)
3118                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3119
3120         return 0;
3121
3122 err_free_rq:
3123         mlx5e_free_drop_rq(drop_rq);
3124
3125 err_destroy_cq:
3126         mlx5e_destroy_cq(cq);
3127
3128 err_free_cq:
3129         mlx5e_free_cq(cq);
3130
3131         return err;
3132 }
3133
3134 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3135 {
3136         mlx5e_destroy_rq(drop_rq);
3137         mlx5e_free_drop_rq(drop_rq);
3138         mlx5e_destroy_cq(&drop_rq->cq);
3139         mlx5e_free_cq(&drop_rq->cq);
3140 }
3141
3142 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3143 {
3144         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3145
3146         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn);
3147
3148         if (MLX5_GET(tisc, tisc, tls_en))
3149                 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.hw_objs.pdn);
3150
3151         if (mlx5_lag_is_lacp_owner(mdev))
3152                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3153
3154         return mlx5_core_create_tis(mdev, in, tisn);
3155 }
3156
3157 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3158 {
3159         mlx5_core_destroy_tis(mdev, tisn);
3160 }
3161
3162 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3163 {
3164         int tc, i;
3165
3166         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3167                 for (tc = 0; tc < priv->profile->max_tc; tc++)
3168                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3169 }
3170
3171 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3172 {
3173         return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3174 }
3175
3176 int mlx5e_create_tises(struct mlx5e_priv *priv)
3177 {
3178         int tc, i;
3179         int err;
3180
3181         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3182                 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3183                         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3184                         void *tisc;
3185
3186                         tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3187
3188                         MLX5_SET(tisc, tisc, prio, tc << 1);
3189
3190                         if (mlx5e_lag_should_assign_affinity(priv->mdev))
3191                                 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3192
3193                         err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3194                         if (err)
3195                                 goto err_close_tises;
3196                 }
3197         }
3198
3199         return 0;
3200
3201 err_close_tises:
3202         for (; i >= 0; i--) {
3203                 for (tc--; tc >= 0; tc--)
3204                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3205                 tc = priv->profile->max_tc;
3206         }
3207
3208         return err;
3209 }
3210
3211 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3212 {
3213         mlx5e_destroy_tises(priv);
3214 }
3215
3216 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
3217                                              u32 rqtn, u32 *tirc)
3218 {
3219         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.hw_objs.td.tdn);
3220         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3221         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3222         MLX5_SET(tirc, tirc, tunneled_offload_en,
3223                  priv->channels.params.tunneled_offload_en);
3224
3225         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3226 }
3227
3228 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3229                                       enum mlx5e_traffic_types tt,
3230                                       u32 *tirc)
3231 {
3232         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3233         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3234                                        &tirc_default_config[tt], tirc, false);
3235 }
3236
3237 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3238 {
3239         mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc);
3240         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3241 }
3242
3243 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
3244                                             enum mlx5e_traffic_types tt,
3245                                             u32 *tirc)
3246 {
3247         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3248         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3249                                        &tirc_default_config[tt], tirc, true);
3250 }
3251
3252 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3253 {
3254         struct mlx5e_tir *tir;
3255         void *tirc;
3256         int inlen;
3257         int i = 0;
3258         int err;
3259         u32 *in;
3260         int tt;
3261
3262         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3263         in = kvzalloc(inlen, GFP_KERNEL);
3264         if (!in)
3265                 return -ENOMEM;
3266
3267         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3268                 memset(in, 0, inlen);
3269                 tir = &priv->indir_tir[tt];
3270                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3271                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3272                 err = mlx5e_create_tir(priv->mdev, tir, in);
3273                 if (err) {
3274                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3275                         goto err_destroy_inner_tirs;
3276                 }
3277         }
3278
3279         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3280                 goto out;
3281
3282         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3283                 memset(in, 0, inlen);
3284                 tir = &priv->inner_indir_tir[i];
3285                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3286                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3287                 err = mlx5e_create_tir(priv->mdev, tir, in);
3288                 if (err) {
3289                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3290                         goto err_destroy_inner_tirs;
3291                 }
3292         }
3293
3294 out:
3295         kvfree(in);
3296
3297         return 0;
3298
3299 err_destroy_inner_tirs:
3300         for (i--; i >= 0; i--)
3301                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3302
3303         for (tt--; tt >= 0; tt--)
3304                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3305
3306         kvfree(in);
3307
3308         return err;
3309 }
3310
3311 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n)
3312 {
3313         struct mlx5e_tir *tir;
3314         void *tirc;
3315         int inlen;
3316         int err = 0;
3317         u32 *in;
3318         int ix;
3319
3320         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3321         in = kvzalloc(inlen, GFP_KERNEL);
3322         if (!in)
3323                 return -ENOMEM;
3324
3325         for (ix = 0; ix < n; ix++) {
3326                 memset(in, 0, inlen);
3327                 tir = &tirs[ix];
3328                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3329                 mlx5e_build_direct_tir_ctx(priv, tir->rqt.rqtn, tirc);
3330                 err = mlx5e_create_tir(priv->mdev, tir, in);
3331                 if (unlikely(err))
3332                         goto err_destroy_ch_tirs;
3333         }
3334
3335         goto out;
3336
3337 err_destroy_ch_tirs:
3338         mlx5_core_warn(priv->mdev, "create tirs failed, %d\n", err);
3339         for (ix--; ix >= 0; ix--)
3340                 mlx5e_destroy_tir(priv->mdev, &tirs[ix]);
3341
3342 out:
3343         kvfree(in);
3344
3345         return err;
3346 }
3347
3348 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3349 {
3350         int i;
3351
3352         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3353                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3354
3355         /* Verify inner tirs resources allocated */
3356         if (!priv->inner_indir_tir[0].tirn)
3357                 return;
3358
3359         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3360                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3361 }
3362
3363 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n)
3364 {
3365         int i;
3366
3367         for (i = 0; i < n; i++)
3368                 mlx5e_destroy_tir(priv->mdev, &tirs[i]);
3369 }
3370
3371 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3372 {
3373         int err = 0;
3374         int i;
3375
3376         for (i = 0; i < chs->num; i++) {
3377                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3378                 if (err)
3379                         return err;
3380         }
3381
3382         return 0;
3383 }
3384
3385 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3386 {
3387         int err;
3388         int i;
3389
3390         for (i = 0; i < chs->num; i++) {
3391                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3392                 if (err)
3393                         return err;
3394         }
3395         if (chs->ptp && test_bit(MLX5E_PTP_STATE_RX, chs->ptp->state))
3396                 return mlx5e_modify_rq_vsd(&chs->ptp->rq, vsd);
3397
3398         return 0;
3399 }
3400
3401 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3402                                  struct tc_mqprio_qopt *mqprio)
3403 {
3404         struct mlx5e_params new_params;
3405         u8 tc = mqprio->num_tc;
3406         int err = 0;
3407
3408         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3409
3410         if (tc && tc != MLX5E_MAX_NUM_TC)
3411                 return -EINVAL;
3412
3413         mutex_lock(&priv->state_lock);
3414
3415         /* MQPRIO is another toplevel qdisc that can't be attached
3416          * simultaneously with the offloaded HTB.
3417          */
3418         if (WARN_ON(priv->htb.maj_id)) {
3419                 err = -EINVAL;
3420                 goto out;
3421         }
3422
3423         new_params = priv->channels.params;
3424         new_params.num_tc = tc ? tc : 1;
3425
3426         err = mlx5e_safe_switch_params(priv, &new_params,
3427                                        mlx5e_num_channels_changed_ctx, NULL, true);
3428
3429 out:
3430         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3431                                     priv->channels.params.num_tc);
3432         mutex_unlock(&priv->state_lock);
3433         return err;
3434 }
3435
3436 static int mlx5e_setup_tc_htb(struct mlx5e_priv *priv, struct tc_htb_qopt_offload *htb)
3437 {
3438         int res;
3439
3440         switch (htb->command) {
3441         case TC_HTB_CREATE:
3442                 return mlx5e_htb_root_add(priv, htb->parent_classid, htb->classid,
3443                                           htb->extack);
3444         case TC_HTB_DESTROY:
3445                 return mlx5e_htb_root_del(priv);
3446         case TC_HTB_LEAF_ALLOC_QUEUE:
3447                 res = mlx5e_htb_leaf_alloc_queue(priv, htb->classid, htb->parent_classid,
3448                                                  htb->rate, htb->ceil, htb->extack);
3449                 if (res < 0)
3450                         return res;
3451                 htb->qid = res;
3452                 return 0;
3453         case TC_HTB_LEAF_TO_INNER:
3454                 return mlx5e_htb_leaf_to_inner(priv, htb->parent_classid, htb->classid,
3455                                                htb->rate, htb->ceil, htb->extack);
3456         case TC_HTB_LEAF_DEL:
3457                 return mlx5e_htb_leaf_del(priv, htb->classid, &htb->moved_qid, &htb->qid,
3458                                           htb->extack);
3459         case TC_HTB_LEAF_DEL_LAST:
3460         case TC_HTB_LEAF_DEL_LAST_FORCE:
3461                 return mlx5e_htb_leaf_del_last(priv, htb->classid,
3462                                                htb->command == TC_HTB_LEAF_DEL_LAST_FORCE,
3463                                                htb->extack);
3464         case TC_HTB_NODE_MODIFY:
3465                 return mlx5e_htb_node_modify(priv, htb->classid, htb->rate, htb->ceil,
3466                                              htb->extack);
3467         case TC_HTB_LEAF_QUERY_QUEUE:
3468                 res = mlx5e_get_txq_by_classid(priv, htb->classid);
3469                 if (res < 0)
3470                         return res;
3471                 htb->qid = res;
3472                 return 0;
3473         default:
3474                 return -EOPNOTSUPP;
3475         }
3476 }
3477
3478 static LIST_HEAD(mlx5e_block_cb_list);
3479
3480 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3481                           void *type_data)
3482 {
3483         struct mlx5e_priv *priv = netdev_priv(dev);
3484         bool tc_unbind = false;
3485         int err;
3486
3487         if (type == TC_SETUP_BLOCK &&
3488             ((struct flow_block_offload *)type_data)->command == FLOW_BLOCK_UNBIND)
3489                 tc_unbind = true;
3490
3491         if (!netif_device_present(dev) && !tc_unbind)
3492                 return -ENODEV;
3493
3494         switch (type) {
3495         case TC_SETUP_BLOCK: {
3496                 struct flow_block_offload *f = type_data;
3497
3498                 f->unlocked_driver_cb = true;
3499                 return flow_block_cb_setup_simple(type_data,
3500                                                   &mlx5e_block_cb_list,
3501                                                   mlx5e_setup_tc_block_cb,
3502                                                   priv, priv, true);
3503         }
3504         case TC_SETUP_QDISC_MQPRIO:
3505                 return mlx5e_setup_tc_mqprio(priv, type_data);
3506         case TC_SETUP_QDISC_HTB:
3507                 mutex_lock(&priv->state_lock);
3508                 err = mlx5e_setup_tc_htb(priv, type_data);
3509                 mutex_unlock(&priv->state_lock);
3510                 return err;
3511         default:
3512                 return -EOPNOTSUPP;
3513         }
3514 }
3515
3516 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3517 {
3518         int i;
3519
3520         for (i = 0; i < priv->max_nch; i++) {
3521                 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3522                 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3523                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3524                 int j;
3525
3526                 s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
3527                 s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
3528                 s->multicast    += rq_stats->mcast_packets + xskrq_stats->mcast_packets;
3529
3530                 for (j = 0; j < priv->max_opened_tc; j++) {
3531                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3532
3533                         s->tx_packets    += sq_stats->packets;
3534                         s->tx_bytes      += sq_stats->bytes;
3535                         s->tx_dropped    += sq_stats->dropped;
3536                 }
3537         }
3538         if (priv->tx_ptp_opened) {
3539                 for (i = 0; i < priv->max_opened_tc; i++) {
3540                         struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[i];
3541
3542                         s->tx_packets    += sq_stats->packets;
3543                         s->tx_bytes      += sq_stats->bytes;
3544                         s->tx_dropped    += sq_stats->dropped;
3545                 }
3546         }
3547         if (priv->rx_ptp_opened) {
3548                 struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq;
3549
3550                 s->rx_packets   += rq_stats->packets;
3551                 s->rx_bytes     += rq_stats->bytes;
3552                 s->multicast    += rq_stats->mcast_packets;
3553         }
3554 }
3555
3556 void
3557 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3558 {
3559         struct mlx5e_priv *priv = netdev_priv(dev);
3560         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3561
3562         if (!netif_device_present(dev))
3563                 return;
3564
3565         /* In switchdev mode, monitor counters doesn't monitor
3566          * rx/tx stats of 802_3. The update stats mechanism
3567          * should keep the 802_3 layout counters updated
3568          */
3569         if (!mlx5e_monitor_counter_supported(priv) ||
3570             mlx5e_is_uplink_rep(priv)) {
3571                 /* update HW stats in background for next time */
3572                 mlx5e_queue_update_stats(priv);
3573         }
3574
3575         if (mlx5e_is_uplink_rep(priv)) {
3576                 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3577
3578                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3579                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3580                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3581                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3582
3583                 /* vport multicast also counts packets that are dropped due to steering
3584                  * or rx out of buffer
3585                  */
3586                 stats->multicast = VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3587         } else {
3588                 mlx5e_fold_sw_stats64(priv, stats);
3589         }
3590
3591         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3592
3593         stats->rx_length_errors =
3594                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3595                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3596                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3597         stats->rx_crc_errors =
3598                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3599         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3600         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3601         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3602                            stats->rx_frame_errors;
3603         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3604 }
3605
3606 static void mlx5e_nic_set_rx_mode(struct mlx5e_priv *priv)
3607 {
3608         if (mlx5e_is_uplink_rep(priv))
3609                 return; /* no rx mode for uplink rep */
3610
3611         queue_work(priv->wq, &priv->set_rx_mode_work);
3612 }
3613
3614 static void mlx5e_set_rx_mode(struct net_device *dev)
3615 {
3616         struct mlx5e_priv *priv = netdev_priv(dev);
3617
3618         mlx5e_nic_set_rx_mode(priv);
3619 }
3620
3621 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3622 {
3623         struct mlx5e_priv *priv = netdev_priv(netdev);
3624         struct sockaddr *saddr = addr;
3625
3626         if (!is_valid_ether_addr(saddr->sa_data))
3627                 return -EADDRNOTAVAIL;
3628
3629         netif_addr_lock_bh(netdev);
3630         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3631         netif_addr_unlock_bh(netdev);
3632
3633         mlx5e_nic_set_rx_mode(priv);
3634
3635         return 0;
3636 }
3637
3638 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3639         do {                                            \
3640                 if (enable)                             \
3641                         *features |= feature;           \
3642                 else                                    \
3643                         *features &= ~feature;          \
3644         } while (0)
3645
3646 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3647
3648 static int set_feature_lro(struct net_device *netdev, bool enable)
3649 {
3650         struct mlx5e_priv *priv = netdev_priv(netdev);
3651         struct mlx5_core_dev *mdev = priv->mdev;
3652         struct mlx5e_params *cur_params;
3653         struct mlx5e_params new_params;
3654         bool reset = true;
3655         int err = 0;
3656
3657         mutex_lock(&priv->state_lock);
3658
3659         if (enable && priv->xsk.refcnt) {
3660                 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n",
3661                             priv->xsk.refcnt);
3662                 err = -EINVAL;
3663                 goto out;
3664         }
3665
3666         cur_params = &priv->channels.params;
3667         if (enable && !MLX5E_GET_PFLAG(cur_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3668                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3669                 err = -EINVAL;
3670                 goto out;
3671         }
3672
3673         new_params = *cur_params;
3674         new_params.lro_en = enable;
3675
3676         if (cur_params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3677                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) ==
3678                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_params, NULL))
3679                         reset = false;
3680         }
3681
3682         err = mlx5e_safe_switch_params(priv, &new_params,
3683                                        mlx5e_modify_tirs_lro_ctx, NULL, reset);
3684 out:
3685         mutex_unlock(&priv->state_lock);
3686         return err;
3687 }
3688
3689 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3690 {
3691         struct mlx5e_priv *priv = netdev_priv(netdev);
3692
3693         if (enable)
3694                 mlx5e_enable_cvlan_filter(priv);
3695         else
3696                 mlx5e_disable_cvlan_filter(priv);
3697
3698         return 0;
3699 }
3700
3701 static int set_feature_hw_tc(struct net_device *netdev, bool enable)
3702 {
3703         struct mlx5e_priv *priv = netdev_priv(netdev);
3704
3705 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3706         if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3707                 netdev_err(netdev,
3708                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3709                 return -EINVAL;
3710         }
3711 #endif
3712
3713         if (!enable && priv->htb.maj_id) {
3714                 netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n");
3715                 return -EINVAL;
3716         }
3717
3718         return 0;
3719 }
3720
3721 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3722 {
3723         struct mlx5e_priv *priv = netdev_priv(netdev);
3724         struct mlx5_core_dev *mdev = priv->mdev;
3725
3726         return mlx5_set_port_fcs(mdev, !enable);
3727 }
3728
3729 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3730 {
3731         struct mlx5e_priv *priv = netdev_priv(netdev);
3732         int err;
3733
3734         mutex_lock(&priv->state_lock);
3735
3736         priv->channels.params.scatter_fcs_en = enable;
3737         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3738         if (err)
3739                 priv->channels.params.scatter_fcs_en = !enable;
3740
3741         mutex_unlock(&priv->state_lock);
3742
3743         return err;
3744 }
3745
3746 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3747 {
3748         struct mlx5e_priv *priv = netdev_priv(netdev);
3749         int err = 0;
3750
3751         mutex_lock(&priv->state_lock);
3752
3753         priv->channels.params.vlan_strip_disable = !enable;
3754         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3755                 goto unlock;
3756
3757         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3758         if (err)
3759                 priv->channels.params.vlan_strip_disable = enable;
3760
3761 unlock:
3762         mutex_unlock(&priv->state_lock);
3763
3764         return err;
3765 }
3766
3767 #ifdef CONFIG_MLX5_EN_ARFS
3768 static int set_feature_arfs(struct net_device *netdev, bool enable)
3769 {
3770         struct mlx5e_priv *priv = netdev_priv(netdev);
3771         int err;
3772
3773         if (enable)
3774                 err = mlx5e_arfs_enable(priv);
3775         else
3776                 err = mlx5e_arfs_disable(priv);
3777
3778         return err;
3779 }
3780 #endif
3781
3782 static int mlx5e_handle_feature(struct net_device *netdev,
3783                                 netdev_features_t *features,
3784                                 netdev_features_t wanted_features,
3785                                 netdev_features_t feature,
3786                                 mlx5e_feature_handler feature_handler)
3787 {
3788         netdev_features_t changes = wanted_features ^ netdev->features;
3789         bool enable = !!(wanted_features & feature);
3790         int err;
3791
3792         if (!(changes & feature))
3793                 return 0;
3794
3795         err = feature_handler(netdev, enable);
3796         if (err) {
3797                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3798                            enable ? "Enable" : "Disable", &feature, err);
3799                 return err;
3800         }
3801
3802         MLX5E_SET_FEATURE(features, feature, enable);
3803         return 0;
3804 }
3805
3806 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3807 {
3808         netdev_features_t oper_features = netdev->features;
3809         int err = 0;
3810
3811 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3812         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3813
3814         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3815         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3816                                     set_feature_cvlan_filter);
3817         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc);
3818         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3819         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3820         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3821 #ifdef CONFIG_MLX5_EN_ARFS
3822         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3823 #endif
3824         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx);
3825
3826         if (err) {
3827                 netdev->features = oper_features;
3828                 return -EINVAL;
3829         }
3830
3831         return 0;
3832 }
3833
3834 static netdev_features_t mlx5e_fix_uplink_rep_features(struct net_device *netdev,
3835                                                        netdev_features_t features)
3836 {
3837         features &= ~NETIF_F_HW_TLS_RX;
3838         if (netdev->features & NETIF_F_HW_TLS_RX)
3839                 netdev_warn(netdev, "Disabling hw_tls_rx, not supported in switchdev mode\n");
3840
3841         features &= ~NETIF_F_HW_TLS_TX;
3842         if (netdev->features & NETIF_F_HW_TLS_TX)
3843                 netdev_warn(netdev, "Disabling hw_tls_tx, not supported in switchdev mode\n");
3844
3845         features &= ~NETIF_F_NTUPLE;
3846         if (netdev->features & NETIF_F_NTUPLE)
3847                 netdev_warn(netdev, "Disabling ntuple, not supported in switchdev mode\n");
3848
3849         return features;
3850 }
3851
3852 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3853                                             netdev_features_t features)
3854 {
3855         struct mlx5e_priv *priv = netdev_priv(netdev);
3856         struct mlx5e_params *params;
3857
3858         mutex_lock(&priv->state_lock);
3859         params = &priv->channels.params;
3860         if (!priv->fs.vlan ||
3861             !bitmap_empty(mlx5e_vlan_get_active_svlans(priv->fs.vlan), VLAN_N_VID)) {
3862                 /* HW strips the outer C-tag header, this is a problem
3863                  * for S-tag traffic.
3864                  */
3865                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3866                 if (!params->vlan_strip_disable)
3867                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3868         }
3869
3870         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3871                 if (features & NETIF_F_LRO) {
3872                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3873                         features &= ~NETIF_F_LRO;
3874                 }
3875         }
3876
3877         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3878                 features &= ~NETIF_F_RXHASH;
3879                 if (netdev->features & NETIF_F_RXHASH)
3880                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3881         }
3882
3883         if (mlx5e_is_uplink_rep(priv))
3884                 features = mlx5e_fix_uplink_rep_features(netdev, features);
3885
3886         mutex_unlock(&priv->state_lock);
3887
3888         return features;
3889 }
3890
3891 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3892                                    struct mlx5e_channels *chs,
3893                                    struct mlx5e_params *new_params,
3894                                    struct mlx5_core_dev *mdev)
3895 {
3896         u16 ix;
3897
3898         for (ix = 0; ix < chs->params.num_channels; ix++) {
3899                 struct xsk_buff_pool *xsk_pool =
3900                         mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix);
3901                 struct mlx5e_xsk_param xsk;
3902
3903                 if (!xsk_pool)
3904                         continue;
3905
3906                 mlx5e_build_xsk_param(xsk_pool, &xsk);
3907
3908                 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3909                         u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3910                         int max_mtu_frame, max_mtu_page, max_mtu;
3911
3912                         /* Two criteria must be met:
3913                          * 1. HW MTU + all headrooms <= XSK frame size.
3914                          * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3915                          */
3916                         max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3917                         max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3918                         max_mtu = min(max_mtu_frame, max_mtu_page);
3919
3920                         netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u. Try MTU <= %d\n",
3921                                    new_params->sw_mtu, ix, max_mtu);
3922                         return false;
3923                 }
3924         }
3925
3926         return true;
3927 }
3928
3929 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3930                      mlx5e_fp_preactivate preactivate)
3931 {
3932         struct mlx5e_priv *priv = netdev_priv(netdev);
3933         struct mlx5e_params new_params;
3934         struct mlx5e_params *params;
3935         bool reset = true;
3936         int err = 0;
3937
3938         mutex_lock(&priv->state_lock);
3939
3940         params = &priv->channels.params;
3941
3942         new_params = *params;
3943         new_params.sw_mtu = new_mtu;
3944         err = mlx5e_validate_params(priv->mdev, &new_params);
3945         if (err)
3946                 goto out;
3947
3948         if (params->xdp_prog &&
3949             !mlx5e_rx_is_linear_skb(&new_params, NULL)) {
3950                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3951                            new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3952                 err = -EINVAL;
3953                 goto out;
3954         }
3955
3956         if (priv->xsk.refcnt &&
3957             !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3958                                     &new_params, priv->mdev)) {
3959                 err = -EINVAL;
3960                 goto out;
3961         }
3962
3963         if (params->lro_en)
3964                 reset = false;
3965
3966         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3967                 bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, params, NULL);
3968                 bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3969                                                                   &new_params, NULL);
3970                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3971                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_params, NULL);
3972
3973                 /* Always reset in linear mode - hw_mtu is used in data path.
3974                  * Check that the mode was non-linear and didn't change.
3975                  * If XSK is active, XSK RQs are linear.
3976                  */
3977                 if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt &&
3978                     ppw_old == ppw_new)
3979                         reset = false;
3980         }
3981
3982         err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, reset);
3983
3984 out:
3985         netdev->mtu = params->sw_mtu;
3986         mutex_unlock(&priv->state_lock);
3987         return err;
3988 }
3989
3990 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3991 {
3992         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
3993 }
3994
3995 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx)
3996 {
3997         bool set  = *(bool *)ctx;
3998
3999         return mlx5e_ptp_rx_manage_fs(priv, set);
4000 }
4001
4002 static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter)
4003 {
4004         bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4005         int err;
4006
4007         if (!rx_filter)
4008                 /* Reset CQE compression to Admin default */
4009                 return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def);
4010
4011         if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4012                 return 0;
4013
4014         /* Disable CQE compression */
4015         netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
4016         err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
4017         if (err)
4018                 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
4019
4020         return err;
4021 }
4022
4023 static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx)
4024 {
4025         struct mlx5e_params new_params;
4026
4027         if (ptp_rx == priv->channels.params.ptp_rx)
4028                 return 0;
4029
4030         new_params = priv->channels.params;
4031         new_params.ptp_rx = ptp_rx;
4032         return mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
4033                                         &new_params.ptp_rx, true);
4034 }
4035
4036 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
4037 {
4038         struct hwtstamp_config config;
4039         bool rx_cqe_compress_def;
4040         bool ptp_rx;
4041         int err;
4042
4043         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
4044             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
4045                 return -EOPNOTSUPP;
4046
4047         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4048                 return -EFAULT;
4049
4050         /* TX HW timestamp */
4051         switch (config.tx_type) {
4052         case HWTSTAMP_TX_OFF:
4053         case HWTSTAMP_TX_ON:
4054                 break;
4055         default:
4056                 return -ERANGE;
4057         }
4058
4059         mutex_lock(&priv->state_lock);
4060         rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4061
4062         /* RX HW timestamp */
4063         switch (config.rx_filter) {
4064         case HWTSTAMP_FILTER_NONE:
4065                 ptp_rx = false;
4066                 break;
4067         case HWTSTAMP_FILTER_ALL:
4068         case HWTSTAMP_FILTER_SOME:
4069         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4070         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4071         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4072         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4073         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4074         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4075         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4076         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4077         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4078         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4079         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4080         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4081         case HWTSTAMP_FILTER_NTP_ALL:
4082                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4083                 /* ptp_rx is set if both HW TS is set and CQE
4084                  * compression is set
4085                  */
4086                 ptp_rx = rx_cqe_compress_def;
4087                 break;
4088         default:
4089                 err = -ERANGE;
4090                 goto err_unlock;
4091         }
4092
4093         if (!priv->profile->rx_ptp_support)
4094                 err = mlx5e_hwstamp_config_no_ptp_rx(priv,
4095                                                      config.rx_filter != HWTSTAMP_FILTER_NONE);
4096         else
4097                 err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx);
4098         if (err)
4099                 goto err_unlock;
4100
4101         memcpy(&priv->tstamp, &config, sizeof(config));
4102         mutex_unlock(&priv->state_lock);
4103
4104         /* might need to fix some features */
4105         netdev_update_features(priv->netdev);
4106
4107         return copy_to_user(ifr->ifr_data, &config,
4108                             sizeof(config)) ? -EFAULT : 0;
4109 err_unlock:
4110         mutex_unlock(&priv->state_lock);
4111         return err;
4112 }
4113
4114 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4115 {
4116         struct hwtstamp_config *cfg = &priv->tstamp;
4117
4118         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4119                 return -EOPNOTSUPP;
4120
4121         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4122 }
4123
4124 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4125 {
4126         struct mlx5e_priv *priv = netdev_priv(dev);
4127
4128         switch (cmd) {
4129         case SIOCSHWTSTAMP:
4130                 return mlx5e_hwstamp_set(priv, ifr);
4131         case SIOCGHWTSTAMP:
4132                 return mlx5e_hwstamp_get(priv, ifr);
4133         default:
4134                 return -EOPNOTSUPP;
4135         }
4136 }
4137
4138 #ifdef CONFIG_MLX5_ESWITCH
4139 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4140 {
4141         struct mlx5e_priv *priv = netdev_priv(dev);
4142         struct mlx5_core_dev *mdev = priv->mdev;
4143
4144         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4145 }
4146
4147 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4148                              __be16 vlan_proto)
4149 {
4150         struct mlx5e_priv *priv = netdev_priv(dev);
4151         struct mlx5_core_dev *mdev = priv->mdev;
4152
4153         if (vlan_proto != htons(ETH_P_8021Q))
4154                 return -EPROTONOSUPPORT;
4155
4156         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4157                                            vlan, qos);
4158 }
4159
4160 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4161 {
4162         struct mlx5e_priv *priv = netdev_priv(dev);
4163         struct mlx5_core_dev *mdev = priv->mdev;
4164
4165         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4166 }
4167
4168 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4169 {
4170         struct mlx5e_priv *priv = netdev_priv(dev);
4171         struct mlx5_core_dev *mdev = priv->mdev;
4172
4173         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4174 }
4175
4176 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4177                       int max_tx_rate)
4178 {
4179         struct mlx5e_priv *priv = netdev_priv(dev);
4180         struct mlx5_core_dev *mdev = priv->mdev;
4181
4182         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4183                                            max_tx_rate, min_tx_rate);
4184 }
4185
4186 static int mlx5_vport_link2ifla(u8 esw_link)
4187 {
4188         switch (esw_link) {
4189         case MLX5_VPORT_ADMIN_STATE_DOWN:
4190                 return IFLA_VF_LINK_STATE_DISABLE;
4191         case MLX5_VPORT_ADMIN_STATE_UP:
4192                 return IFLA_VF_LINK_STATE_ENABLE;
4193         }
4194         return IFLA_VF_LINK_STATE_AUTO;
4195 }
4196
4197 static int mlx5_ifla_link2vport(u8 ifla_link)
4198 {
4199         switch (ifla_link) {
4200         case IFLA_VF_LINK_STATE_DISABLE:
4201                 return MLX5_VPORT_ADMIN_STATE_DOWN;
4202         case IFLA_VF_LINK_STATE_ENABLE:
4203                 return MLX5_VPORT_ADMIN_STATE_UP;
4204         }
4205         return MLX5_VPORT_ADMIN_STATE_AUTO;
4206 }
4207
4208 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4209                                    int link_state)
4210 {
4211         struct mlx5e_priv *priv = netdev_priv(dev);
4212         struct mlx5_core_dev *mdev = priv->mdev;
4213
4214         if (mlx5e_is_uplink_rep(priv))
4215                 return -EOPNOTSUPP;
4216
4217         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4218                                             mlx5_ifla_link2vport(link_state));
4219 }
4220
4221 int mlx5e_get_vf_config(struct net_device *dev,
4222                         int vf, struct ifla_vf_info *ivi)
4223 {
4224         struct mlx5e_priv *priv = netdev_priv(dev);
4225         struct mlx5_core_dev *mdev = priv->mdev;
4226         int err;
4227
4228         if (!netif_device_present(dev))
4229                 return -EOPNOTSUPP;
4230
4231         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4232         if (err)
4233                 return err;
4234         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4235         return 0;
4236 }
4237
4238 int mlx5e_get_vf_stats(struct net_device *dev,
4239                        int vf, struct ifla_vf_stats *vf_stats)
4240 {
4241         struct mlx5e_priv *priv = netdev_priv(dev);
4242         struct mlx5_core_dev *mdev = priv->mdev;
4243
4244         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4245                                             vf_stats);
4246 }
4247
4248 static bool
4249 mlx5e_has_offload_stats(const struct net_device *dev, int attr_id)
4250 {
4251         struct mlx5e_priv *priv = netdev_priv(dev);
4252
4253         if (!netif_device_present(dev))
4254                 return false;
4255
4256         if (!mlx5e_is_uplink_rep(priv))
4257                 return false;
4258
4259         return mlx5e_rep_has_offload_stats(dev, attr_id);
4260 }
4261
4262 static int
4263 mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
4264                         void *sp)
4265 {
4266         struct mlx5e_priv *priv = netdev_priv(dev);
4267
4268         if (!mlx5e_is_uplink_rep(priv))
4269                 return -EOPNOTSUPP;
4270
4271         return mlx5e_rep_get_offload_stats(attr_id, dev, sp);
4272 }
4273 #endif
4274
4275 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type)
4276 {
4277         switch (proto_type) {
4278         case IPPROTO_GRE:
4279                 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre);
4280         case IPPROTO_IPIP:
4281         case IPPROTO_IPV6:
4282                 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) ||
4283                         MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx));
4284         default:
4285                 return false;
4286         }
4287 }
4288
4289 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev,
4290                                                            struct sk_buff *skb)
4291 {
4292         switch (skb->inner_protocol) {
4293         case htons(ETH_P_IP):
4294         case htons(ETH_P_IPV6):
4295         case htons(ETH_P_TEB):
4296                 return true;
4297         case htons(ETH_P_MPLS_UC):
4298         case htons(ETH_P_MPLS_MC):
4299                 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre);
4300         }
4301         return false;
4302 }
4303
4304 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4305                                                      struct sk_buff *skb,
4306                                                      netdev_features_t features)
4307 {
4308         unsigned int offset = 0;
4309         struct udphdr *udph;
4310         u8 proto;
4311         u16 port;
4312
4313         switch (vlan_get_protocol(skb)) {
4314         case htons(ETH_P_IP):
4315                 proto = ip_hdr(skb)->protocol;
4316                 break;
4317         case htons(ETH_P_IPV6):
4318                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4319                 break;
4320         default:
4321                 goto out;
4322         }
4323
4324         switch (proto) {
4325         case IPPROTO_GRE:
4326                 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb))
4327                         return features;
4328                 break;
4329         case IPPROTO_IPIP:
4330         case IPPROTO_IPV6:
4331                 if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP))
4332                         return features;
4333                 break;
4334         case IPPROTO_UDP:
4335                 udph = udp_hdr(skb);
4336                 port = be16_to_cpu(udph->dest);
4337
4338                 /* Verify if UDP port is being offloaded by HW */
4339                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4340                         return features;
4341
4342 #if IS_ENABLED(CONFIG_GENEVE)
4343                 /* Support Geneve offload for default UDP port */
4344                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4345                         return features;
4346 #endif
4347                 break;
4348 #ifdef CONFIG_MLX5_EN_IPSEC
4349         case IPPROTO_ESP:
4350                 return mlx5e_ipsec_feature_check(skb, features);
4351 #endif
4352         }
4353
4354 out:
4355         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4356         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4357 }
4358
4359 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4360                                        struct net_device *netdev,
4361                                        netdev_features_t features)
4362 {
4363         struct mlx5e_priv *priv = netdev_priv(netdev);
4364
4365         features = vlan_features_check(skb, features);
4366         features = vxlan_features_check(skb, features);
4367
4368         /* Validate if the tunneled packet is being offloaded by HW */
4369         if (skb->encapsulation &&
4370             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4371                 return mlx5e_tunnel_features_check(priv, skb, features);
4372
4373         return features;
4374 }
4375
4376 static void mlx5e_tx_timeout_work(struct work_struct *work)
4377 {
4378         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4379                                                tx_timeout_work);
4380         struct net_device *netdev = priv->netdev;
4381         int i;
4382
4383         rtnl_lock();
4384         mutex_lock(&priv->state_lock);
4385
4386         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4387                 goto unlock;
4388
4389         for (i = 0; i < netdev->real_num_tx_queues; i++) {
4390                 struct netdev_queue *dev_queue =
4391                         netdev_get_tx_queue(netdev, i);
4392                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4393
4394                 if (!netif_xmit_stopped(dev_queue))
4395                         continue;
4396
4397                 if (mlx5e_reporter_tx_timeout(sq))
4398                 /* break if tried to reopened channels */
4399                         break;
4400         }
4401
4402 unlock:
4403         mutex_unlock(&priv->state_lock);
4404         rtnl_unlock();
4405 }
4406
4407 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4408 {
4409         struct mlx5e_priv *priv = netdev_priv(dev);
4410
4411         netdev_err(dev, "TX timeout detected\n");
4412         queue_work(priv->wq, &priv->tx_timeout_work);
4413 }
4414
4415 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4416 {
4417         struct net_device *netdev = priv->netdev;
4418         struct mlx5e_params new_params;
4419
4420         if (priv->channels.params.lro_en) {
4421                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4422                 return -EINVAL;
4423         }
4424
4425         if (mlx5_fpga_is_ipsec_device(priv->mdev)) {
4426                 netdev_warn(netdev,
4427                             "XDP is not available on Innova cards with IPsec support\n");
4428                 return -EINVAL;
4429         }
4430
4431         new_params = priv->channels.params;
4432         new_params.xdp_prog = prog;
4433
4434         /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4435          * the XDP program.
4436          */
4437         if (!mlx5e_rx_is_linear_skb(&new_params, NULL)) {
4438                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4439                             new_params.sw_mtu,
4440                             mlx5e_xdp_max_mtu(&new_params, NULL));
4441                 return -EINVAL;
4442         }
4443
4444         return 0;
4445 }
4446
4447 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog)
4448 {
4449         struct bpf_prog *old_prog;
4450
4451         old_prog = rcu_replace_pointer(rq->xdp_prog, prog,
4452                                        lockdep_is_held(&rq->priv->state_lock));
4453         if (old_prog)
4454                 bpf_prog_put(old_prog);
4455 }
4456
4457 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4458 {
4459         struct mlx5e_priv *priv = netdev_priv(netdev);
4460         struct mlx5e_params new_params;
4461         struct bpf_prog *old_prog;
4462         int err = 0;
4463         bool reset;
4464         int i;
4465
4466         mutex_lock(&priv->state_lock);
4467
4468         if (prog) {
4469                 err = mlx5e_xdp_allowed(priv, prog);
4470                 if (err)
4471                         goto unlock;
4472         }
4473
4474         /* no need for full reset when exchanging programs */
4475         reset = (!priv->channels.params.xdp_prog || !prog);
4476
4477         new_params = priv->channels.params;
4478         new_params.xdp_prog = prog;
4479         if (reset)
4480                 mlx5e_set_rq_type(priv->mdev, &new_params);
4481         old_prog = priv->channels.params.xdp_prog;
4482
4483         err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
4484         if (err)
4485                 goto unlock;
4486
4487         if (old_prog)
4488                 bpf_prog_put(old_prog);
4489
4490         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4491                 goto unlock;
4492
4493         /* exchanging programs w/o reset, we update ref counts on behalf
4494          * of the channels RQs here.
4495          */
4496         bpf_prog_add(prog, priv->channels.num);
4497         for (i = 0; i < priv->channels.num; i++) {
4498                 struct mlx5e_channel *c = priv->channels.c[i];
4499
4500                 mlx5e_rq_replace_xdp_prog(&c->rq, prog);
4501                 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) {
4502                         bpf_prog_inc(prog);
4503                         mlx5e_rq_replace_xdp_prog(&c->xskrq, prog);
4504                 }
4505         }
4506
4507 unlock:
4508         mutex_unlock(&priv->state_lock);
4509         return err;
4510 }
4511
4512 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4513 {
4514         switch (xdp->command) {
4515         case XDP_SETUP_PROG:
4516                 return mlx5e_xdp_set(dev, xdp->prog);
4517         case XDP_SETUP_XSK_POOL:
4518                 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool,
4519                                             xdp->xsk.queue_id);
4520         default:
4521                 return -EINVAL;
4522         }
4523 }
4524
4525 #ifdef CONFIG_MLX5_ESWITCH
4526 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4527                                 struct net_device *dev, u32 filter_mask,
4528                                 int nlflags)
4529 {
4530         struct mlx5e_priv *priv = netdev_priv(dev);
4531         struct mlx5_core_dev *mdev = priv->mdev;
4532         u8 mode, setting;
4533         int err;
4534
4535         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4536         if (err)
4537                 return err;
4538         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4539         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4540                                        mode,
4541                                        0, 0, nlflags, filter_mask, NULL);
4542 }
4543
4544 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4545                                 u16 flags, struct netlink_ext_ack *extack)
4546 {
4547         struct mlx5e_priv *priv = netdev_priv(dev);
4548         struct mlx5_core_dev *mdev = priv->mdev;
4549         struct nlattr *attr, *br_spec;
4550         u16 mode = BRIDGE_MODE_UNDEF;
4551         u8 setting;
4552         int rem;
4553
4554         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4555         if (!br_spec)
4556                 return -EINVAL;
4557
4558         nla_for_each_nested(attr, br_spec, rem) {
4559                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4560                         continue;
4561
4562                 if (nla_len(attr) < sizeof(mode))
4563                         return -EINVAL;
4564
4565                 mode = nla_get_u16(attr);
4566                 if (mode > BRIDGE_MODE_VEPA)
4567                         return -EINVAL;
4568
4569                 break;
4570         }
4571
4572         if (mode == BRIDGE_MODE_UNDEF)
4573                 return -EINVAL;
4574
4575         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4576         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4577 }
4578 #endif
4579
4580 const struct net_device_ops mlx5e_netdev_ops = {
4581         .ndo_open                = mlx5e_open,
4582         .ndo_stop                = mlx5e_close,
4583         .ndo_start_xmit          = mlx5e_xmit,
4584         .ndo_setup_tc            = mlx5e_setup_tc,
4585         .ndo_select_queue        = mlx5e_select_queue,
4586         .ndo_get_stats64         = mlx5e_get_stats,
4587         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4588         .ndo_set_mac_address     = mlx5e_set_mac,
4589         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4590         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4591         .ndo_set_features        = mlx5e_set_features,
4592         .ndo_fix_features        = mlx5e_fix_features,
4593         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4594         .ndo_do_ioctl            = mlx5e_ioctl,
4595         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4596         .ndo_features_check      = mlx5e_features_check,
4597         .ndo_tx_timeout          = mlx5e_tx_timeout,
4598         .ndo_bpf                 = mlx5e_xdp,
4599         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4600         .ndo_xsk_wakeup          = mlx5e_xsk_wakeup,
4601 #ifdef CONFIG_MLX5_EN_ARFS
4602         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4603 #endif
4604 #ifdef CONFIG_MLX5_ESWITCH
4605         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4606         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4607
4608         /* SRIOV E-Switch NDOs */
4609         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4610         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4611         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4612         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4613         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4614         .ndo_get_vf_config       = mlx5e_get_vf_config,
4615         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4616         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4617         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
4618         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
4619 #endif
4620         .ndo_get_devlink_port    = mlx5e_get_devlink_port,
4621 };
4622
4623 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4624                                    int num_channels)
4625 {
4626         int i;
4627
4628         for (i = 0; i < len; i++)
4629                 indirection_rqt[i] = i % num_channels;
4630 }
4631
4632 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4633 {
4634         int i;
4635
4636         /* The supported periods are organized in ascending order */
4637         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4638                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4639                         break;
4640
4641         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4642 }
4643
4644 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4645                             u16 num_channels)
4646 {
4647         enum mlx5e_traffic_types tt;
4648
4649         rss_params->hfunc = ETH_RSS_HASH_TOP;
4650         netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4651                             sizeof(rss_params->toeplitz_hash_key));
4652         mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4653                                       MLX5E_INDIR_RQT_SIZE, num_channels);
4654         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4655                 rss_params->rx_hash_fields[tt] =
4656                         tirc_default_config[tt].rx_hash_fields;
4657 }
4658
4659 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu)
4660 {
4661         struct mlx5e_rss_params *rss_params = &priv->rss_params;
4662         struct mlx5e_params *params = &priv->channels.params;
4663         struct mlx5_core_dev *mdev = priv->mdev;
4664         u8 rx_cq_period_mode;
4665
4666         priv->max_nch = mlx5e_calc_max_nch(priv, priv->profile);
4667
4668         params->sw_mtu = mtu;
4669         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4670         params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
4671                                      priv->max_nch);
4672         params->num_tc       = 1;
4673
4674         /* Set an initial non-zero value, so that mlx5e_select_queue won't
4675          * divide by zero if called before first activating channels.
4676          */
4677         priv->num_tc_x_num_ch = params->num_channels * params->num_tc;
4678
4679         /* SQ */
4680         params->log_sq_size = is_kdump_kernel() ?
4681                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4682                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4683         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4684
4685         /* XDP SQ */
4686         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4687
4688         /* set CQE compression */
4689         params->rx_cqe_compress_def = false;
4690         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4691             MLX5_CAP_GEN(mdev, vport_group_manager))
4692                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4693
4694         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4695         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4696
4697         /* RQ */
4698         mlx5e_build_rq_params(mdev, params);
4699
4700         /* HW LRO */
4701         if (MLX5_CAP_ETH(mdev, lro_cap) &&
4702             params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4703                 /* No XSK params: checking the availability of striding RQ in general. */
4704                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4705                         params->lro_en = !slow_pci_heuristic(mdev);
4706         }
4707         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4708
4709         /* CQ moderation params */
4710         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4711                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4712                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4713         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4714         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4715         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4716         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4717
4718         /* TX inline */
4719         mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
4720
4721         /* RSS */
4722         mlx5e_build_rss_params(rss_params, params->num_channels);
4723         params->tunneled_offload_en =
4724                 mlx5e_tunnel_inner_ft_supported(mdev);
4725
4726         /* AF_XDP */
4727         params->xsk = xsk;
4728
4729         /* Do not update netdev->features directly in here
4730          * on mlx5e_attach_netdev() we will call mlx5e_update_features()
4731          * To update netdev->features please modify mlx5e_fix_features()
4732          */
4733 }
4734
4735 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4736 {
4737         struct mlx5e_priv *priv = netdev_priv(netdev);
4738
4739         mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
4740         if (is_zero_ether_addr(netdev->dev_addr) &&
4741             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4742                 eth_hw_addr_random(netdev);
4743                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4744         }
4745 }
4746
4747 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table,
4748                                 unsigned int entry, struct udp_tunnel_info *ti)
4749 {
4750         struct mlx5e_priv *priv = netdev_priv(netdev);
4751
4752         return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port));
4753 }
4754
4755 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table,
4756                                   unsigned int entry, struct udp_tunnel_info *ti)
4757 {
4758         struct mlx5e_priv *priv = netdev_priv(netdev);
4759
4760         return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port));
4761 }
4762
4763 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv)
4764 {
4765         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4766                 return;
4767
4768         priv->nic_info.set_port = mlx5e_vxlan_set_port;
4769         priv->nic_info.unset_port = mlx5e_vxlan_unset_port;
4770         priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
4771                                 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN;
4772         priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN;
4773         /* Don't count the space hard-coded to the IANA port */
4774         priv->nic_info.tables[0].n_entries =
4775                 mlx5_vxlan_max_udp_ports(priv->mdev) - 1;
4776
4777         priv->netdev->udp_tunnel_nic_info = &priv->nic_info;
4778 }
4779
4780 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev)
4781 {
4782         int tt;
4783
4784         for (tt = 0; tt < MLX5E_NUM_TUNNEL_TT; tt++) {
4785                 if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5e_get_proto_by_tunnel_type(tt)))
4786                         return true;
4787         }
4788         return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev));
4789 }
4790
4791 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4792 {
4793         struct mlx5e_priv *priv = netdev_priv(netdev);
4794         struct mlx5_core_dev *mdev = priv->mdev;
4795         bool fcs_supported;
4796         bool fcs_enabled;
4797
4798         SET_NETDEV_DEV(netdev, mdev->device);
4799
4800         netdev->netdev_ops = &mlx5e_netdev_ops;
4801
4802         mlx5e_dcbnl_build_netdev(netdev);
4803
4804         netdev->watchdog_timeo    = 15 * HZ;
4805
4806         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4807
4808         netdev->vlan_features    |= NETIF_F_SG;
4809         netdev->vlan_features    |= NETIF_F_HW_CSUM;
4810         netdev->vlan_features    |= NETIF_F_GRO;
4811         netdev->vlan_features    |= NETIF_F_TSO;
4812         netdev->vlan_features    |= NETIF_F_TSO6;
4813         netdev->vlan_features    |= NETIF_F_RXCSUM;
4814         netdev->vlan_features    |= NETIF_F_RXHASH;
4815
4816         netdev->mpls_features    |= NETIF_F_SG;
4817         netdev->mpls_features    |= NETIF_F_HW_CSUM;
4818         netdev->mpls_features    |= NETIF_F_TSO;
4819         netdev->mpls_features    |= NETIF_F_TSO6;
4820
4821         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4822         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4823
4824         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4825             mlx5e_check_fragmented_striding_rq_cap(mdev))
4826                 netdev->vlan_features    |= NETIF_F_LRO;
4827
4828         netdev->hw_features       = netdev->vlan_features;
4829         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4830         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4831         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4832         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4833
4834         if (mlx5e_tunnel_any_tx_proto_supported(mdev)) {
4835                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4836                 netdev->hw_enc_features |= NETIF_F_TSO;
4837                 netdev->hw_enc_features |= NETIF_F_TSO6;
4838                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4839         }
4840
4841         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4842                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL;
4843                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
4844                 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL;
4845         }
4846
4847         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) {
4848                 netdev->hw_features     |= NETIF_F_GSO_GRE;
4849                 netdev->hw_enc_features |= NETIF_F_GSO_GRE;
4850                 netdev->gso_partial_features |= NETIF_F_GSO_GRE;
4851         }
4852
4853         if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) {
4854                 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4855                                        NETIF_F_GSO_IPXIP6;
4856                 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4857                                            NETIF_F_GSO_IPXIP6;
4858                 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4859                                                 NETIF_F_GSO_IPXIP6;
4860         }
4861
4862         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4863         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4864         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4865         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4866
4867         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4868
4869         if (fcs_supported)
4870                 netdev->hw_features |= NETIF_F_RXALL;
4871
4872         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4873                 netdev->hw_features |= NETIF_F_RXFCS;
4874
4875         if (mlx5_qos_is_supported(mdev))
4876                 netdev->hw_features |= NETIF_F_HW_TC;
4877
4878         netdev->features          = netdev->hw_features;
4879
4880         /* Defaults */
4881         if (fcs_enabled)
4882                 netdev->features  &= ~NETIF_F_RXALL;
4883         netdev->features  &= ~NETIF_F_LRO;
4884         netdev->features  &= ~NETIF_F_RXFCS;
4885
4886 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4887         if (FT_CAP(flow_modify_en) &&
4888             FT_CAP(modify_root) &&
4889             FT_CAP(identified_miss_table_mode) &&
4890             FT_CAP(flow_table_modify)) {
4891 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
4892                 netdev->hw_features      |= NETIF_F_HW_TC;
4893 #endif
4894 #ifdef CONFIG_MLX5_EN_ARFS
4895                 netdev->hw_features      |= NETIF_F_NTUPLE;
4896 #endif
4897         }
4898
4899         netdev->features         |= NETIF_F_HIGHDMA;
4900         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4901
4902         netdev->priv_flags       |= IFF_UNICAST_FLT;
4903
4904         mlx5e_set_netdev_dev_addr(netdev);
4905         mlx5e_ipsec_build_netdev(priv);
4906         mlx5e_tls_build_netdev(priv);
4907 }
4908
4909 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4910 {
4911         u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
4912         u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
4913         struct mlx5_core_dev *mdev = priv->mdev;
4914         int err;
4915
4916         MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
4917         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4918         if (!err)
4919                 priv->q_counter =
4920                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4921
4922         err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4923         if (!err)
4924                 priv->drop_rq_q_counter =
4925                         MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4926 }
4927
4928 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4929 {
4930         u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
4931
4932         MLX5_SET(dealloc_q_counter_in, in, opcode,
4933                  MLX5_CMD_OP_DEALLOC_Q_COUNTER);
4934         if (priv->q_counter) {
4935                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4936                          priv->q_counter);
4937                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4938         }
4939
4940         if (priv->drop_rq_q_counter) {
4941                 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4942                          priv->drop_rq_q_counter);
4943                 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4944         }
4945 }
4946
4947 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4948                           struct net_device *netdev)
4949 {
4950         struct mlx5e_priv *priv = netdev_priv(netdev);
4951         struct devlink_port *dl_port;
4952         int err;
4953
4954         mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu);
4955         mlx5e_vxlan_set_netdev_info(priv);
4956
4957         mlx5e_timestamp_init(priv);
4958
4959         err = mlx5e_ipsec_init(priv);
4960         if (err)
4961                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4962
4963         err = mlx5e_tls_init(priv);
4964         if (err)
4965                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4966
4967         dl_port = mlx5e_devlink_get_dl_port(priv);
4968         if (dl_port->registered)
4969                 mlx5e_health_create_reporters(priv);
4970
4971         return 0;
4972 }
4973
4974 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4975 {
4976         struct devlink_port *dl_port = mlx5e_devlink_get_dl_port(priv);
4977
4978         if (dl_port->registered)
4979                 mlx5e_health_destroy_reporters(priv);
4980         mlx5e_tls_cleanup(priv);
4981         mlx5e_ipsec_cleanup(priv);
4982 }
4983
4984 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4985 {
4986         struct mlx5_core_dev *mdev = priv->mdev;
4987         u16 max_nch = priv->max_nch;
4988         int err;
4989
4990         mlx5e_create_q_counters(priv);
4991
4992         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4993         if (err) {
4994                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4995                 goto err_destroy_q_counters;
4996         }
4997
4998         err = mlx5e_create_indirect_rqt(priv);
4999         if (err)
5000                 goto err_close_drop_rq;
5001
5002         err = mlx5e_create_direct_rqts(priv, priv->direct_tir, max_nch);
5003         if (err)
5004                 goto err_destroy_indirect_rqts;
5005
5006         err = mlx5e_create_indirect_tirs(priv, true);
5007         if (err)
5008                 goto err_destroy_direct_rqts;
5009
5010         err = mlx5e_create_direct_tirs(priv, priv->direct_tir, max_nch);
5011         if (err)
5012                 goto err_destroy_indirect_tirs;
5013
5014         err = mlx5e_create_direct_rqts(priv, priv->xsk_tir, max_nch);
5015         if (unlikely(err))
5016                 goto err_destroy_direct_tirs;
5017
5018         err = mlx5e_create_direct_tirs(priv, priv->xsk_tir, max_nch);
5019         if (unlikely(err))
5020                 goto err_destroy_xsk_rqts;
5021
5022         err = mlx5e_create_direct_rqts(priv, &priv->ptp_tir, 1);
5023         if (err)
5024                 goto err_destroy_xsk_tirs;
5025
5026         err = mlx5e_create_direct_tirs(priv, &priv->ptp_tir, 1);
5027         if (err)
5028                 goto err_destroy_ptp_rqt;
5029
5030         err = mlx5e_create_flow_steering(priv);
5031         if (err) {
5032                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5033                 goto err_destroy_ptp_direct_tir;
5034         }
5035
5036         err = mlx5e_tc_nic_init(priv);
5037         if (err)
5038                 goto err_destroy_flow_steering;
5039
5040         err = mlx5e_accel_init_rx(priv);
5041         if (err)
5042                 goto err_tc_nic_cleanup;
5043
5044 #ifdef CONFIG_MLX5_EN_ARFS
5045         priv->netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(priv->mdev);
5046 #endif
5047
5048         return 0;
5049
5050 err_tc_nic_cleanup:
5051         mlx5e_tc_nic_cleanup(priv);
5052 err_destroy_flow_steering:
5053         mlx5e_destroy_flow_steering(priv);
5054 err_destroy_ptp_direct_tir:
5055         mlx5e_destroy_direct_tirs(priv, &priv->ptp_tir, 1);
5056 err_destroy_ptp_rqt:
5057         mlx5e_destroy_direct_rqts(priv, &priv->ptp_tir, 1);
5058 err_destroy_xsk_tirs:
5059         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir, max_nch);
5060 err_destroy_xsk_rqts:
5061         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir, max_nch);
5062 err_destroy_direct_tirs:
5063         mlx5e_destroy_direct_tirs(priv, priv->direct_tir, max_nch);
5064 err_destroy_indirect_tirs:
5065         mlx5e_destroy_indirect_tirs(priv);
5066 err_destroy_direct_rqts:
5067         mlx5e_destroy_direct_rqts(priv, priv->direct_tir, max_nch);
5068 err_destroy_indirect_rqts:
5069         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5070 err_close_drop_rq:
5071         mlx5e_close_drop_rq(&priv->drop_rq);
5072 err_destroy_q_counters:
5073         mlx5e_destroy_q_counters(priv);
5074         return err;
5075 }
5076
5077 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5078 {
5079         u16 max_nch = priv->max_nch;
5080
5081         mlx5e_accel_cleanup_rx(priv);
5082         mlx5e_tc_nic_cleanup(priv);
5083         mlx5e_destroy_flow_steering(priv);
5084         mlx5e_destroy_direct_tirs(priv, &priv->ptp_tir, 1);
5085         mlx5e_destroy_direct_rqts(priv, &priv->ptp_tir, 1);
5086         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir, max_nch);
5087         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir, max_nch);
5088         mlx5e_destroy_direct_tirs(priv, priv->direct_tir, max_nch);
5089         mlx5e_destroy_indirect_tirs(priv);
5090         mlx5e_destroy_direct_rqts(priv, priv->direct_tir, max_nch);
5091         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5092         mlx5e_close_drop_rq(&priv->drop_rq);
5093         mlx5e_destroy_q_counters(priv);
5094 }
5095
5096 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5097 {
5098         int err;
5099
5100         err = mlx5e_create_tises(priv);
5101         if (err) {
5102                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5103                 return err;
5104         }
5105
5106         mlx5e_dcbnl_initialize(priv);
5107         return 0;
5108 }
5109
5110 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5111 {
5112         struct net_device *netdev = priv->netdev;
5113         struct mlx5_core_dev *mdev = priv->mdev;
5114
5115         mlx5e_init_l2_addr(priv);
5116
5117         /* Marking the link as currently not needed by the Driver */
5118         if (!netif_running(netdev))
5119                 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN);
5120
5121         mlx5e_set_netdev_mtu_boundaries(priv);
5122         mlx5e_set_dev_port_mtu(priv);
5123
5124         mlx5_lag_add_netdev(mdev, netdev);
5125
5126         mlx5e_enable_async_events(priv);
5127         mlx5e_enable_blocking_events(priv);
5128         if (mlx5e_monitor_counter_supported(priv))
5129                 mlx5e_monitor_counter_init(priv);
5130
5131         mlx5e_hv_vhca_stats_create(priv);
5132         if (netdev->reg_state != NETREG_REGISTERED)
5133                 return;
5134         mlx5e_dcbnl_init_app(priv);
5135
5136         mlx5e_nic_set_rx_mode(priv);
5137
5138         rtnl_lock();
5139         if (netif_running(netdev))
5140                 mlx5e_open(netdev);
5141         udp_tunnel_nic_reset_ntf(priv->netdev);
5142         netif_device_attach(netdev);
5143         rtnl_unlock();
5144 }
5145
5146 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5147 {
5148         struct mlx5_core_dev *mdev = priv->mdev;
5149
5150         if (priv->netdev->reg_state == NETREG_REGISTERED)
5151                 mlx5e_dcbnl_delete_app(priv);
5152
5153         rtnl_lock();
5154         if (netif_running(priv->netdev))
5155                 mlx5e_close(priv->netdev);
5156         netif_device_detach(priv->netdev);
5157         rtnl_unlock();
5158
5159         mlx5e_nic_set_rx_mode(priv);
5160
5161         mlx5e_hv_vhca_stats_destroy(priv);
5162         if (mlx5e_monitor_counter_supported(priv))
5163                 mlx5e_monitor_counter_cleanup(priv);
5164
5165         mlx5e_disable_blocking_events(priv);
5166         if (priv->en_trap) {
5167                 mlx5e_deactivate_trap(priv);
5168                 mlx5e_close_trap(priv->en_trap);
5169                 priv->en_trap = NULL;
5170         }
5171         mlx5e_disable_async_events(priv);
5172         mlx5_lag_remove_netdev(mdev, priv->netdev);
5173         mlx5_vxlan_reset_to_default(mdev->vxlan);
5174 }
5175
5176 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5177 {
5178         return mlx5e_refresh_tirs(priv, false, false);
5179 }
5180
5181 static const struct mlx5e_profile mlx5e_nic_profile = {
5182         .init              = mlx5e_nic_init,
5183         .cleanup           = mlx5e_nic_cleanup,
5184         .init_rx           = mlx5e_init_nic_rx,
5185         .cleanup_rx        = mlx5e_cleanup_nic_rx,
5186         .init_tx           = mlx5e_init_nic_tx,
5187         .cleanup_tx        = mlx5e_cleanup_nic_tx,
5188         .enable            = mlx5e_nic_enable,
5189         .disable           = mlx5e_nic_disable,
5190         .update_rx         = mlx5e_update_nic_rx,
5191         .update_stats      = mlx5e_stats_update_ndo_stats,
5192         .update_carrier    = mlx5e_update_carrier,
5193         .rx_handlers       = &mlx5e_rx_handlers_nic,
5194         .max_tc            = MLX5E_MAX_NUM_TC,
5195         .rq_groups         = MLX5E_NUM_RQ_GROUPS(XSK),
5196         .stats_grps        = mlx5e_nic_stats_grps,
5197         .stats_grps_num    = mlx5e_nic_stats_grps_num,
5198         .rx_ptp_support    = true,
5199 };
5200
5201 /* mlx5e generic netdev management API (move to en_common.c) */
5202 int mlx5e_priv_init(struct mlx5e_priv *priv,
5203                     struct net_device *netdev,
5204                     struct mlx5_core_dev *mdev)
5205 {
5206         /* priv init */
5207         priv->mdev        = mdev;
5208         priv->netdev      = netdev;
5209         priv->msglevel    = MLX5E_MSG_LEVEL;
5210         priv->max_opened_tc = 1;
5211
5212         if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
5213                 return -ENOMEM;
5214
5215         mutex_init(&priv->state_lock);
5216         hash_init(priv->htb.qos_tc2node);
5217         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5218         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5219         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5220         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5221
5222         priv->wq = create_singlethread_workqueue("mlx5e");
5223         if (!priv->wq)
5224                 goto err_free_cpumask;
5225
5226         return 0;
5227
5228 err_free_cpumask:
5229         free_cpumask_var(priv->scratchpad.cpumask);
5230
5231         return -ENOMEM;
5232 }
5233
5234 void mlx5e_priv_cleanup(struct mlx5e_priv *priv)
5235 {
5236         int i;
5237
5238         /* bail if change profile failed and also rollback failed */
5239         if (!priv->mdev)
5240                 return;
5241
5242         destroy_workqueue(priv->wq);
5243         free_cpumask_var(priv->scratchpad.cpumask);
5244
5245         for (i = 0; i < priv->htb.max_qos_sqs; i++)
5246                 kfree(priv->htb.qos_sq_stats[i]);
5247         kvfree(priv->htb.qos_sq_stats);
5248
5249         memset(priv, 0, sizeof(*priv));
5250 }
5251
5252 struct net_device *
5253 mlx5e_create_netdev(struct mlx5_core_dev *mdev, unsigned int txqs, unsigned int rxqs)
5254 {
5255         struct net_device *netdev;
5256         int err;
5257
5258         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs);
5259         if (!netdev) {
5260                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5261                 return NULL;
5262         }
5263
5264         err = mlx5e_priv_init(netdev_priv(netdev), netdev, mdev);
5265         if (err) {
5266                 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5267                 goto err_free_netdev;
5268         }
5269
5270         netif_carrier_off(netdev);
5271         dev_net_set(netdev, mlx5_core_net(mdev));
5272
5273         return netdev;
5274
5275 err_free_netdev:
5276         free_netdev(netdev);
5277
5278         return NULL;
5279 }
5280
5281 static void mlx5e_update_features(struct net_device *netdev)
5282 {
5283         if (netdev->reg_state != NETREG_REGISTERED)
5284                 return; /* features will be updated on netdev registration */
5285
5286         rtnl_lock();
5287         netdev_update_features(netdev);
5288         rtnl_unlock();
5289 }
5290
5291 static void mlx5e_reset_channels(struct net_device *netdev)
5292 {
5293         netdev_reset_tc(netdev);
5294 }
5295
5296 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5297 {
5298         const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
5299         const struct mlx5e_profile *profile = priv->profile;
5300         int max_nch;
5301         int err;
5302
5303         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5304
5305         /* max number of channels may have changed */
5306         max_nch = mlx5e_get_max_num_channels(priv->mdev);
5307         if (priv->channels.params.num_channels > max_nch) {
5308                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5309                 /* Reducing the number of channels - RXFH has to be reset, and
5310                  * mlx5e_num_channels_changed below will build the RQT.
5311                  */
5312                 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
5313                 priv->channels.params.num_channels = max_nch;
5314         }
5315         /* 1. Set the real number of queues in the kernel the first time.
5316          * 2. Set our default XPS cpumask.
5317          * 3. Build the RQT.
5318          *
5319          * rtnl_lock is required by netif_set_real_num_*_queues in case the
5320          * netdev has been registered by this point (if this function was called
5321          * in the reload or resume flow).
5322          */
5323         if (take_rtnl)
5324                 rtnl_lock();
5325         err = mlx5e_num_channels_changed(priv);
5326         if (take_rtnl)
5327                 rtnl_unlock();
5328         if (err)
5329                 goto out;
5330
5331         err = profile->init_tx(priv);
5332         if (err)
5333                 goto out;
5334
5335         err = profile->init_rx(priv);
5336         if (err)
5337                 goto err_cleanup_tx;
5338
5339         if (profile->enable)
5340                 profile->enable(priv);
5341
5342         mlx5e_update_features(priv->netdev);
5343
5344         return 0;
5345
5346 err_cleanup_tx:
5347         profile->cleanup_tx(priv);
5348
5349 out:
5350         mlx5e_reset_channels(priv->netdev);
5351         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5352         cancel_work_sync(&priv->update_stats_work);
5353         return err;
5354 }
5355
5356 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5357 {
5358         const struct mlx5e_profile *profile = priv->profile;
5359
5360         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5361
5362         if (profile->disable)
5363                 profile->disable(priv);
5364         flush_workqueue(priv->wq);
5365
5366         profile->cleanup_rx(priv);
5367         profile->cleanup_tx(priv);
5368         mlx5e_reset_channels(priv->netdev);
5369         cancel_work_sync(&priv->update_stats_work);
5370 }
5371
5372 static int
5373 mlx5e_netdev_attach_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
5374                             const struct mlx5e_profile *new_profile, void *new_ppriv)
5375 {
5376         struct mlx5e_priv *priv = netdev_priv(netdev);
5377         int err;
5378
5379         err = mlx5e_priv_init(priv, netdev, mdev);
5380         if (err) {
5381                 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5382                 return err;
5383         }
5384         netif_carrier_off(netdev);
5385         priv->profile = new_profile;
5386         priv->ppriv = new_ppriv;
5387         err = new_profile->init(priv->mdev, priv->netdev);
5388         if (err)
5389                 goto priv_cleanup;
5390         err = mlx5e_attach_netdev(priv);
5391         if (err)
5392                 goto profile_cleanup;
5393         return err;
5394
5395 profile_cleanup:
5396         new_profile->cleanup(priv);
5397 priv_cleanup:
5398         mlx5e_priv_cleanup(priv);
5399         return err;
5400 }
5401
5402 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
5403                                 const struct mlx5e_profile *new_profile, void *new_ppriv)
5404 {
5405         unsigned int new_max_nch = mlx5e_calc_max_nch(priv, new_profile);
5406         const struct mlx5e_profile *orig_profile = priv->profile;
5407         struct net_device *netdev = priv->netdev;
5408         struct mlx5_core_dev *mdev = priv->mdev;
5409         void *orig_ppriv = priv->ppriv;
5410         int err, rollback_err;
5411
5412         /* sanity */
5413         if (new_max_nch != priv->max_nch) {
5414                 netdev_warn(netdev, "%s: Replacing profile with different max channels\n",
5415                             __func__);
5416                 return -EINVAL;
5417         }
5418
5419         /* cleanup old profile */
5420         mlx5e_detach_netdev(priv);
5421         priv->profile->cleanup(priv);
5422         mlx5e_priv_cleanup(priv);
5423
5424         err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile, new_ppriv);
5425         if (err) { /* roll back to original profile */
5426                 netdev_warn(netdev, "%s: new profile init failed, %d\n", __func__, err);
5427                 goto rollback;
5428         }
5429
5430         return 0;
5431
5432 rollback:
5433         rollback_err = mlx5e_netdev_attach_profile(netdev, mdev, orig_profile, orig_ppriv);
5434         if (rollback_err)
5435                 netdev_err(netdev, "%s: failed to rollback to orig profile, %d\n",
5436                            __func__, rollback_err);
5437         return err;
5438 }
5439
5440 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv)
5441 {
5442         mlx5e_netdev_change_profile(priv, &mlx5e_nic_profile, NULL);
5443 }
5444
5445 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5446 {
5447         struct net_device *netdev = priv->netdev;
5448
5449         mlx5e_priv_cleanup(priv);
5450         free_netdev(netdev);
5451 }
5452
5453 static int mlx5e_resume(struct auxiliary_device *adev)
5454 {
5455         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5456         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5457         struct net_device *netdev = priv->netdev;
5458         struct mlx5_core_dev *mdev = edev->mdev;
5459         int err;
5460
5461         if (netif_device_present(netdev))
5462                 return 0;
5463
5464         err = mlx5e_create_mdev_resources(mdev);
5465         if (err)
5466                 return err;
5467
5468         err = mlx5e_attach_netdev(priv);
5469         if (err) {
5470                 mlx5e_destroy_mdev_resources(mdev);
5471                 return err;
5472         }
5473
5474         return 0;
5475 }
5476
5477 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)
5478 {
5479         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5480         struct net_device *netdev = priv->netdev;
5481         struct mlx5_core_dev *mdev = priv->mdev;
5482
5483         if (!netif_device_present(netdev))
5484                 return -ENODEV;
5485
5486         mlx5e_detach_netdev(priv);
5487         mlx5e_destroy_mdev_resources(mdev);
5488         return 0;
5489 }
5490
5491 static int mlx5e_probe(struct auxiliary_device *adev,
5492                        const struct auxiliary_device_id *id)
5493 {
5494         struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5495         const struct mlx5e_profile *profile = &mlx5e_nic_profile;
5496         struct mlx5_core_dev *mdev = edev->mdev;
5497         struct net_device *netdev;
5498         pm_message_t state = {};
5499         unsigned int txqs, rxqs, ptp_txqs = 0;
5500         struct mlx5e_priv *priv;
5501         int qos_sqs = 0;
5502         int err;
5503         int nch;
5504
5505         if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
5506                 ptp_txqs = profile->max_tc;
5507
5508         if (mlx5_qos_is_supported(mdev))
5509                 qos_sqs = mlx5e_qos_max_leaf_nodes(mdev);
5510
5511         nch = mlx5e_get_max_num_channels(mdev);
5512         txqs = nch * profile->max_tc + ptp_txqs + qos_sqs;
5513         rxqs = nch * profile->rq_groups;
5514         netdev = mlx5e_create_netdev(mdev, txqs, rxqs);
5515         if (!netdev) {
5516                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5517                 return -ENOMEM;
5518         }
5519
5520         mlx5e_build_nic_netdev(netdev);
5521
5522         priv = netdev_priv(netdev);
5523         dev_set_drvdata(&adev->dev, priv);
5524
5525         priv->profile = profile;
5526         priv->ppriv = NULL;
5527
5528         err = mlx5e_devlink_port_register(priv);
5529         if (err) {
5530                 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
5531                 goto err_destroy_netdev;
5532         }
5533
5534         err = profile->init(mdev, netdev);
5535         if (err) {
5536                 mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err);
5537                 goto err_devlink_cleanup;
5538         }
5539
5540         err = mlx5e_resume(adev);
5541         if (err) {
5542                 mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err);
5543                 goto err_profile_cleanup;
5544         }
5545
5546         err = register_netdev(netdev);
5547         if (err) {
5548                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5549                 goto err_resume;
5550         }
5551
5552         mlx5e_devlink_port_type_eth_set(priv);
5553
5554         mlx5e_dcbnl_init_app(priv);
5555         mlx5_uplink_netdev_set(mdev, netdev);
5556         return 0;
5557
5558 err_resume:
5559         mlx5e_suspend(adev, state);
5560 err_profile_cleanup:
5561         profile->cleanup(priv);
5562 err_devlink_cleanup:
5563         mlx5e_devlink_port_unregister(priv);
5564 err_destroy_netdev:
5565         mlx5e_destroy_netdev(priv);
5566         return err;
5567 }
5568
5569 static void mlx5e_remove(struct auxiliary_device *adev)
5570 {
5571         struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev);
5572         pm_message_t state = {};
5573
5574         mlx5e_dcbnl_delete_app(priv);
5575         unregister_netdev(priv->netdev);
5576         mlx5e_suspend(adev, state);
5577         priv->profile->cleanup(priv);
5578         mlx5e_devlink_port_unregister(priv);
5579         mlx5e_destroy_netdev(priv);
5580 }
5581
5582 static const struct auxiliary_device_id mlx5e_id_table[] = {
5583         { .name = MLX5_ADEV_NAME ".eth", },
5584         {},
5585 };
5586
5587 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table);
5588
5589 static struct auxiliary_driver mlx5e_driver = {
5590         .name = "eth",
5591         .probe = mlx5e_probe,
5592         .remove = mlx5e_remove,
5593         .suspend = mlx5e_suspend,
5594         .resume = mlx5e_resume,
5595         .id_table = mlx5e_id_table,
5596 };
5597
5598 int mlx5e_init(void)
5599 {
5600         int ret;
5601
5602         mlx5e_ipsec_build_inverse_table();
5603         mlx5e_build_ptys2ethtool_map();
5604         ret = auxiliary_driver_register(&mlx5e_driver);
5605         if (ret)
5606                 return ret;
5607
5608         ret = mlx5e_rep_init();
5609         if (ret)
5610                 auxiliary_driver_unregister(&mlx5e_driver);
5611         return ret;
5612 }
5613
5614 void mlx5e_cleanup(void)
5615 {
5616         mlx5e_rep_cleanup();
5617         auxiliary_driver_unregister(&mlx5e_driver);
5618 }