2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <net/geneve.h>
38 #include <linux/bpf.h>
39 #include <linux/if_bridge.h>
40 #include <linux/filter.h>
41 #include <net/page_pool.h>
42 #include <net/xdp_sock_drv.h>
48 #include "en_accel/ipsec.h"
49 #include "en_accel/en_accel.h"
50 #include "en_accel/ktls.h"
51 #include "lib/vxlan.h"
52 #include "lib/clock.h"
56 #include "en/monitor_stats.h"
57 #include "en/health.h"
58 #include "en/params.h"
59 #include "en/xsk/pool.h"
60 #include "en/xsk/setup.h"
61 #include "en/xsk/rx.h"
62 #include "en/xsk/tx.h"
63 #include "en/hv_vhca_stats.h"
64 #include "en/devlink.h"
70 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
72 bool striding_rq_umr, inline_umr;
75 striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) && MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
76 MLX5_CAP_ETH(mdev, reg_umr_sq);
77 max_wqe_sz_cap = mlx5e_get_max_sq_wqebbs(mdev) * MLX5_SEND_WQE_BB;
78 inline_umr = max_wqe_sz_cap >= MLX5E_UMR_WQE_INLINE_SZ;
82 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
83 (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
89 void mlx5e_update_carrier(struct mlx5e_priv *priv)
91 struct mlx5_core_dev *mdev = priv->mdev;
95 port_state = mlx5_query_vport_state(mdev,
96 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
99 up = port_state == VPORT_STATE_UP;
100 if (up == netif_carrier_ok(priv->netdev))
101 netif_carrier_event(priv->netdev);
103 netdev_info(priv->netdev, "Link up\n");
104 netif_carrier_on(priv->netdev);
106 netdev_info(priv->netdev, "Link down\n");
107 netif_carrier_off(priv->netdev);
111 static void mlx5e_update_carrier_work(struct work_struct *work)
113 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
114 update_carrier_work);
116 mutex_lock(&priv->state_lock);
117 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
118 if (priv->profile->update_carrier)
119 priv->profile->update_carrier(priv);
120 mutex_unlock(&priv->state_lock);
123 static void mlx5e_update_stats_work(struct work_struct *work)
125 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
128 mutex_lock(&priv->state_lock);
129 priv->profile->update_stats(priv);
130 mutex_unlock(&priv->state_lock);
133 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
135 if (!priv->profile->update_stats)
138 if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
141 queue_work(priv->wq, &priv->update_stats_work);
144 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
146 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
147 struct mlx5_eqe *eqe = data;
149 if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
152 switch (eqe->sub_type) {
153 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
154 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
155 queue_work(priv->wq, &priv->update_carrier_work);
164 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
166 priv->events_nb.notifier_call = async_event;
167 mlx5_notifier_register(priv->mdev, &priv->events_nb);
170 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
172 mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
175 static int blocking_event(struct notifier_block *nb, unsigned long event, void *data)
177 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb);
181 case MLX5_DRIVER_EVENT_TYPE_TRAP:
182 err = mlx5e_handle_trap_event(priv, data);
185 netdev_warn(priv->netdev, "Sync event: Unknown event %ld\n", event);
191 static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv)
193 priv->blocking_events_nb.notifier_call = blocking_event;
194 mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb);
197 static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv)
199 mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb);
202 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
203 struct mlx5e_icosq *sq,
204 struct mlx5e_umr_wqe *wqe)
206 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
207 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
208 u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
210 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
212 cseg->umr_mkey = rq->mkey_be;
214 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
215 ucseg->xlt_octowords =
216 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
217 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
220 static int mlx5e_rq_shampo_hd_alloc(struct mlx5e_rq *rq, int node)
222 rq->mpwqe.shampo = kvzalloc_node(sizeof(*rq->mpwqe.shampo),
224 if (!rq->mpwqe.shampo)
229 static void mlx5e_rq_shampo_hd_free(struct mlx5e_rq *rq)
231 kvfree(rq->mpwqe.shampo);
234 static int mlx5e_rq_shampo_hd_info_alloc(struct mlx5e_rq *rq, int node)
236 struct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo;
238 shampo->bitmap = bitmap_zalloc_node(shampo->hd_per_wq, GFP_KERNEL,
243 shampo->info = kvzalloc_node(array_size(shampo->hd_per_wq,
244 sizeof(*shampo->info)),
247 kvfree(shampo->bitmap);
253 static void mlx5e_rq_shampo_hd_info_free(struct mlx5e_rq *rq)
255 kvfree(rq->mpwqe.shampo->bitmap);
256 kvfree(rq->mpwqe.shampo->info);
259 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node)
261 int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
263 rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
264 sizeof(*rq->mpwqe.info)),
269 mlx5e_build_umr_wqe(rq, rq->icosq, &rq->mpwqe.umr_wqe);
274 static int mlx5e_create_umr_mtt_mkey(struct mlx5_core_dev *mdev,
275 u64 npages, u8 page_shift, u32 *umr_mkey,
276 dma_addr_t filler_addr)
278 struct mlx5_mtt *mtt;
285 inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + sizeof(*mtt) * npages;
287 in = kvzalloc(inlen, GFP_KERNEL);
291 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
293 MLX5_SET(mkc, mkc, free, 1);
294 MLX5_SET(mkc, mkc, umr_en, 1);
295 MLX5_SET(mkc, mkc, lw, 1);
296 MLX5_SET(mkc, mkc, lr, 1);
297 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
298 mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
299 MLX5_SET(mkc, mkc, qpn, 0xffffff);
300 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
301 MLX5_SET64(mkc, mkc, len, npages << page_shift);
302 MLX5_SET(mkc, mkc, translations_octword_size,
303 MLX5_MTT_OCTW(npages));
304 MLX5_SET(mkc, mkc, log_page_size, page_shift);
305 MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
306 MLX5_MTT_OCTW(npages));
308 /* Initialize the mkey with all MTTs pointing to a default
309 * page (filler_addr). When the channels are activated, UMR
310 * WQEs will redirect the RX WQEs to the actual memory from
311 * the RQ's pool, while the gaps (wqe_overflow) remain mapped
312 * to the default page.
314 mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
315 for (i = 0 ; i < npages ; i++)
316 mtt[i].ptag = cpu_to_be64(filler_addr);
318 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
324 static int mlx5e_create_umr_klm_mkey(struct mlx5_core_dev *mdev,
333 inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
335 in = kvzalloc(inlen, GFP_KERNEL);
339 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
341 MLX5_SET(mkc, mkc, free, 1);
342 MLX5_SET(mkc, mkc, umr_en, 1);
343 MLX5_SET(mkc, mkc, lw, 1);
344 MLX5_SET(mkc, mkc, lr, 1);
345 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_KLMS);
346 mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
347 MLX5_SET(mkc, mkc, qpn, 0xffffff);
348 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn);
349 MLX5_SET(mkc, mkc, translations_octword_size, nentries);
350 MLX5_SET(mkc, mkc, length64, 1);
351 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
357 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
359 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
361 return mlx5e_create_umr_mtt_mkey(mdev, num_mtts, PAGE_SHIFT,
362 &rq->umr_mkey, rq->wqe_overflow.addr);
365 static int mlx5e_create_rq_hd_umr_mkey(struct mlx5_core_dev *mdev,
368 u32 max_klm_size = BIT(MLX5_CAP_GEN(mdev, log_max_klm_list_size));
370 if (max_klm_size < rq->mpwqe.shampo->hd_per_wq) {
371 mlx5_core_err(mdev, "max klm list size 0x%x is smaller than shampo header buffer list size 0x%x\n",
372 max_klm_size, rq->mpwqe.shampo->hd_per_wq);
375 return mlx5e_create_umr_klm_mkey(mdev, rq->mpwqe.shampo->hd_per_wq,
376 &rq->mpwqe.shampo->mkey);
379 static u64 mlx5e_get_mpwqe_offset(u16 wqe_ix)
381 return MLX5E_REQUIRED_MTTS(wqe_ix) << PAGE_SHIFT;
384 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
386 struct mlx5e_wqe_frag_info next_frag = {};
387 struct mlx5e_wqe_frag_info *prev = NULL;
390 next_frag.di = &rq->wqe.di[0];
392 for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
393 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
394 struct mlx5e_wqe_frag_info *frag =
395 &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
398 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
399 if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
401 next_frag.offset = 0;
403 prev->last_in_page = true;
408 next_frag.offset += frag_info[f].frag_stride;
414 prev->last_in_page = true;
417 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node)
419 int len = wq_sz << rq->wqe.info.log_num_frags;
421 rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)), GFP_KERNEL, node);
425 mlx5e_init_frags_partition(rq);
430 void mlx5e_free_di_list(struct mlx5e_rq *rq)
435 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
437 struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
439 mlx5e_reporter_rq_cqe_err(rq);
442 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
444 rq->wqe_overflow.page = alloc_page(GFP_KERNEL);
445 if (!rq->wqe_overflow.page)
448 rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0,
449 PAGE_SIZE, rq->buff.map_dir);
450 if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) {
451 __free_page(rq->wqe_overflow.page);
457 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq)
459 dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE,
461 __free_page(rq->wqe_overflow.page);
464 static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
467 struct mlx5_core_dev *mdev = c->mdev;
470 rq->wq_type = params->rq_wq_type;
472 rq->netdev = c->netdev;
474 rq->tstamp = c->tstamp;
475 rq->clock = &mdev->clock;
476 rq->icosq = &c->icosq;
479 rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
480 rq->xdpsq = &c->rq_xdpsq;
481 rq->stats = &c->priv->channel_stats[c->ix]->rq;
482 rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev);
483 err = mlx5e_rq_set_handlers(rq, params, NULL);
487 return xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, 0);
490 static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *mdev,
491 struct mlx5e_params *params,
492 struct mlx5e_rq_param *rqp,
497 void *wqc = MLX5_ADDR_OF(rqc, rqp->rqc, wq);
501 if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
503 err = mlx5e_rq_shampo_hd_alloc(rq, node);
506 rq->mpwqe.shampo->hd_per_wq =
507 mlx5e_shampo_hd_per_wq(mdev, params, rqp);
508 err = mlx5e_create_rq_hd_umr_mkey(mdev, rq);
511 err = mlx5e_rq_shampo_hd_info_alloc(rq, node);
513 goto err_shampo_info;
514 rq->hw_gro_data = kvzalloc_node(sizeof(*rq->hw_gro_data), GFP_KERNEL, node);
515 if (!rq->hw_gro_data) {
517 goto err_hw_gro_data;
519 rq->mpwqe.shampo->key =
520 cpu_to_be32(rq->mpwqe.shampo->mkey);
521 rq->mpwqe.shampo->hd_per_wqe =
522 mlx5e_shampo_hd_per_wqe(mdev, params, rqp);
523 wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz));
524 *pool_size += (rq->mpwqe.shampo->hd_per_wqe * wq_size) /
525 MLX5E_SHAMPO_WQ_HEADER_PER_PAGE;
529 mlx5e_rq_shampo_hd_info_free(rq);
531 mlx5_core_destroy_mkey(mdev, rq->mpwqe.shampo->mkey);
533 mlx5e_rq_shampo_hd_free(rq);
538 static void mlx5e_rq_free_shampo(struct mlx5e_rq *rq)
540 if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
543 kvfree(rq->hw_gro_data);
544 mlx5e_rq_shampo_hd_info_free(rq);
545 mlx5_core_destroy_mkey(rq->mdev, rq->mpwqe.shampo->mkey);
546 mlx5e_rq_shampo_hd_free(rq);
549 static int mlx5e_alloc_rq(struct mlx5e_params *params,
550 struct mlx5e_xsk_param *xsk,
551 struct mlx5e_rq_param *rqp,
552 int node, struct mlx5e_rq *rq)
554 struct page_pool_params pp_params = { 0 };
555 struct mlx5_core_dev *mdev = rq->mdev;
556 void *rqc = rqp->rqc;
557 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
563 rqp->wq.db_numa_node = node;
564 INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
566 if (params->xdp_prog)
567 bpf_prog_inc(params->xdp_prog);
568 RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog);
570 rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
571 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
572 pool_size = 1 << params->log_rq_mtu_frames;
574 switch (rq->wq_type) {
575 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
576 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
579 goto err_rq_xdp_prog;
581 err = mlx5e_alloc_mpwqe_rq_drop_page(rq);
583 goto err_rq_wq_destroy;
585 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
587 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
589 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
590 mlx5e_mpwqe_get_log_rq_size(params, xsk);
592 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
593 rq->mpwqe.num_strides =
594 BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
595 rq->mpwqe.min_wqe_bulk = mlx5e_mpwqe_get_min_wqe_bulk(wq_sz);
597 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz);
599 err = mlx5e_create_rq_umr_mkey(mdev, rq);
601 goto err_rq_drop_page;
602 rq->mkey_be = cpu_to_be32(rq->umr_mkey);
604 err = mlx5e_rq_alloc_mpwqe_info(rq, node);
608 err = mlx5_rq_shampo_alloc(mdev, params, rqp, rq, &pool_size, node);
610 goto err_free_by_rq_type;
613 default: /* MLX5_WQ_TYPE_CYCLIC */
614 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
617 goto err_rq_xdp_prog;
619 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
621 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
623 rq->wqe.info = rqp->frags_info;
624 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride;
627 kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
628 (wq_sz << rq->wqe.info.log_num_frags)),
630 if (!rq->wqe.frags) {
632 goto err_rq_wq_destroy;
635 err = mlx5e_init_di_list(rq, wq_sz, node);
639 rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey);
643 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
644 MEM_TYPE_XSK_BUFF_POOL, NULL);
645 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq);
647 /* Create a page_pool and register it with rxq */
649 pp_params.flags = 0; /* No-internal DMA mapping in page_pool */
650 pp_params.pool_size = pool_size;
651 pp_params.nid = node;
652 pp_params.dev = rq->pdev;
653 pp_params.dma_dir = rq->buff.map_dir;
655 /* page_pool can be used even when there is no rq->xdp_prog,
656 * given page_pool does not handle DMA mapping there is no
657 * required state to clear. And page_pool gracefully handle
660 rq->page_pool = page_pool_create(&pp_params);
661 if (IS_ERR(rq->page_pool)) {
662 err = PTR_ERR(rq->page_pool);
663 rq->page_pool = NULL;
664 goto err_free_shampo;
666 if (xdp_rxq_info_is_reg(&rq->xdp_rxq))
667 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
668 MEM_TYPE_PAGE_POOL, rq->page_pool);
671 goto err_free_shampo;
673 for (i = 0; i < wq_sz; i++) {
674 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
675 struct mlx5e_rx_wqe_ll *wqe =
676 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
678 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
679 u64 dma_offset = mlx5e_get_mpwqe_offset(i);
680 u16 headroom = test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state) ?
681 0 : rq->buff.headroom;
683 wqe->data[0].addr = cpu_to_be64(dma_offset + headroom);
684 wqe->data[0].byte_count = cpu_to_be32(byte_count);
685 wqe->data[0].lkey = rq->mkey_be;
687 struct mlx5e_rx_wqe_cyc *wqe =
688 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
691 for (f = 0; f < rq->wqe.info.num_frags; f++) {
692 u32 frag_size = rq->wqe.info.arr[f].frag_size |
693 MLX5_HW_START_PADDING;
695 wqe->data[f].byte_count = cpu_to_be32(frag_size);
696 wqe->data[f].lkey = rq->mkey_be;
698 /* check if num_frags is not a pow of two */
699 if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
700 wqe->data[f].byte_count = 0;
701 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
702 wqe->data[f].addr = 0;
707 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
709 switch (params->rx_cq_moderation.cq_period_mode) {
710 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
711 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
713 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
715 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
718 rq->page_cache.head = 0;
719 rq->page_cache.tail = 0;
724 mlx5e_rq_free_shampo(rq);
726 switch (rq->wq_type) {
727 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
728 kvfree(rq->mpwqe.info);
730 mlx5_core_destroy_mkey(mdev, rq->umr_mkey);
732 mlx5e_free_mpwqe_rq_drop_page(rq);
734 default: /* MLX5_WQ_TYPE_CYCLIC */
735 mlx5e_free_di_list(rq);
737 kvfree(rq->wqe.frags);
740 mlx5_wq_destroy(&rq->wq_ctrl);
742 if (params->xdp_prog)
743 bpf_prog_put(params->xdp_prog);
748 static void mlx5e_free_rq(struct mlx5e_rq *rq)
750 struct bpf_prog *old_prog;
753 if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) {
754 old_prog = rcu_dereference_protected(rq->xdp_prog,
755 lockdep_is_held(&rq->priv->state_lock));
757 bpf_prog_put(old_prog);
760 switch (rq->wq_type) {
761 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
762 kvfree(rq->mpwqe.info);
763 mlx5_core_destroy_mkey(rq->mdev, rq->umr_mkey);
764 mlx5e_free_mpwqe_rq_drop_page(rq);
765 mlx5e_rq_free_shampo(rq);
767 default: /* MLX5_WQ_TYPE_CYCLIC */
768 kvfree(rq->wqe.frags);
769 mlx5e_free_di_list(rq);
772 for (i = rq->page_cache.head; i != rq->page_cache.tail;
773 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
774 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
776 /* With AF_XDP, page_cache is not used, so this loop is not
777 * entered, and it's safe to call mlx5e_page_release_dynamic
780 mlx5e_page_release_dynamic(rq, dma_info->page, false);
783 xdp_rxq_info_unreg(&rq->xdp_rxq);
784 page_pool_destroy(rq->page_pool);
785 mlx5_wq_destroy(&rq->wq_ctrl);
788 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
790 struct mlx5_core_dev *mdev = rq->mdev;
798 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
799 sizeof(u64) * rq->wq_ctrl.buf.npages;
800 in = kvzalloc(inlen, GFP_KERNEL);
804 ts_format = mlx5_is_real_time_rq(mdev) ?
805 MLX5_TIMESTAMP_FORMAT_REAL_TIME :
806 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
807 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
808 wq = MLX5_ADDR_OF(rqc, rqc, wq);
810 memcpy(rqc, param->rqc, sizeof(param->rqc));
812 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
813 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
814 MLX5_SET(rqc, rqc, ts_format, ts_format);
815 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
816 MLX5_ADAPTER_PAGE_SHIFT);
817 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
819 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {
820 MLX5_SET(wq, wq, log_headers_buffer_entry_num,
821 order_base_2(rq->mpwqe.shampo->hd_per_wq));
822 MLX5_SET(wq, wq, headers_mkey, rq->mpwqe.shampo->mkey);
825 mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
826 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
828 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
835 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
837 struct mlx5_core_dev *mdev = rq->mdev;
844 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
845 in = kvzalloc(inlen, GFP_KERNEL);
849 if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
850 mlx5e_rqwq_reset(rq);
852 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
854 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
855 MLX5_SET(rqc, rqc, state, next_state);
857 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
864 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
866 struct mlx5_core_dev *mdev = rq->mdev;
873 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
874 in = kvzalloc(inlen, GFP_KERNEL);
878 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
880 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
881 MLX5_SET64(modify_rq_in, in, modify_bitmask,
882 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
883 MLX5_SET(rqc, rqc, scatter_fcs, enable);
884 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
886 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
893 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
895 struct mlx5_core_dev *mdev = rq->mdev;
901 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
902 in = kvzalloc(inlen, GFP_KERNEL);
906 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
908 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
909 MLX5_SET64(modify_rq_in, in, modify_bitmask,
910 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
911 MLX5_SET(rqc, rqc, vsd, vsd);
912 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
914 err = mlx5_core_modify_rq(mdev, rq->rqn, in);
921 void mlx5e_destroy_rq(struct mlx5e_rq *rq)
923 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
926 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
928 unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
930 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
933 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
937 } while (time_before(jiffies, exp_time));
939 netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
940 rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
942 mlx5e_reporter_rx_timeout(rq);
946 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq)
948 struct mlx5_wq_ll *wq;
952 if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
958 /* Outstanding UMR WQEs (in progress) start at wq->head */
959 for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
960 rq->dealloc_wqe(rq, head);
961 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
964 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) {
967 len = (rq->mpwqe.shampo->pi - rq->mpwqe.shampo->ci) &
968 (rq->mpwqe.shampo->hd_per_wq - 1);
969 mlx5e_shampo_dealloc_hd(rq, len, rq->mpwqe.shampo->ci, false);
970 rq->mpwqe.shampo->pi = rq->mpwqe.shampo->ci;
973 rq->mpwqe.actual_wq_head = wq->head;
974 rq->mpwqe.umr_in_progress = 0;
975 rq->mpwqe.umr_completed = 0;
978 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
983 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
984 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
986 mlx5e_free_rx_in_progress_descs(rq);
988 while (!mlx5_wq_ll_is_empty(wq)) {
989 struct mlx5e_rx_wqe_ll *wqe;
991 wqe_ix_be = *wq->tail_next;
992 wqe_ix = be16_to_cpu(wqe_ix_be);
993 wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix);
994 rq->dealloc_wqe(rq, wqe_ix);
995 mlx5_wq_ll_pop(wq, wqe_ix_be,
996 &wqe->next.next_wqe_index);
999 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state))
1000 mlx5e_shampo_dealloc_hd(rq, rq->mpwqe.shampo->hd_per_wq,
1003 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1005 while (!mlx5_wq_cyc_is_empty(wq)) {
1006 wqe_ix = mlx5_wq_cyc_get_tail(wq);
1007 rq->dealloc_wqe(rq, wqe_ix);
1008 mlx5_wq_cyc_pop(wq);
1014 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
1015 struct mlx5e_xsk_param *xsk, int node,
1016 struct mlx5e_rq *rq)
1018 struct mlx5_core_dev *mdev = rq->mdev;
1021 if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO)
1022 __set_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state);
1024 err = mlx5e_alloc_rq(params, xsk, param, node, rq);
1028 err = mlx5e_create_rq(rq, param);
1032 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1034 goto err_destroy_rq;
1036 if (MLX5_CAP_ETH(mdev, cqe_checksum_full))
1037 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state);
1039 if (params->rx_dim_enabled)
1040 __set_bit(MLX5E_RQ_STATE_AM, &rq->state);
1042 /* We disable csum_complete when XDP is enabled since
1043 * XDP programs might manipulate packets which will render
1044 * skb->checksum incorrect.
1046 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || params->xdp_prog)
1047 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state);
1049 /* For CQE compression on striding RQ, use stride index provided by
1050 * HW if capability is supported.
1052 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) &&
1053 MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index))
1054 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state);
1059 mlx5e_destroy_rq(rq);
1066 void mlx5e_activate_rq(struct mlx5e_rq *rq)
1068 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
1070 mlx5e_trigger_irq(rq->icosq);
1073 napi_schedule(rq->cq.napi);
1078 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
1080 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
1081 synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */
1084 void mlx5e_close_rq(struct mlx5e_rq *rq)
1086 cancel_work_sync(&rq->dim.work);
1087 cancel_work_sync(&rq->recover_work);
1088 mlx5e_destroy_rq(rq);
1089 mlx5e_free_rx_descs(rq);
1093 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
1095 kvfree(sq->db.xdpi_fifo.xi);
1096 kvfree(sq->db.wqe_info);
1099 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
1101 struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
1102 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1103 int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1106 size = array_size(sizeof(*xdpi_fifo->xi), dsegs_per_wq);
1107 xdpi_fifo->xi = kvzalloc_node(size, GFP_KERNEL, numa);
1111 xdpi_fifo->pc = &sq->xdpi_fifo_pc;
1112 xdpi_fifo->cc = &sq->xdpi_fifo_cc;
1113 xdpi_fifo->mask = dsegs_per_wq - 1;
1118 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
1120 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1124 size = array_size(sizeof(*sq->db.wqe_info), wq_sz);
1125 sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1126 if (!sq->db.wqe_info)
1129 err = mlx5e_alloc_xdpsq_fifo(sq, numa);
1131 mlx5e_free_xdpsq_db(sq);
1138 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
1139 struct mlx5e_params *params,
1140 struct xsk_buff_pool *xsk_pool,
1141 struct mlx5e_sq_param *param,
1142 struct mlx5e_xdpsq *sq,
1145 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1146 struct mlx5_core_dev *mdev = c->mdev;
1147 struct mlx5_wq_cyc *wq = &sq->wq;
1151 sq->mkey_be = c->mkey_be;
1153 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
1154 sq->min_inline_mode = params->tx_min_inline_mode;
1155 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1156 sq->xsk_pool = xsk_pool;
1158 sq->stats = sq->xsk_pool ?
1159 &c->priv->channel_stats[c->ix]->xsksq :
1161 &c->priv->channel_stats[c->ix]->xdpsq :
1162 &c->priv->channel_stats[c->ix]->rq_xdpsq;
1163 sq->max_sq_wqebbs = mlx5e_get_max_sq_wqebbs(mdev);
1164 sq->stop_room = MLX5E_STOP_ROOM(sq->max_sq_wqebbs);
1165 sq->max_sq_mpw_wqebbs = mlx5e_get_sw_max_sq_mpw_wqebbs(sq->max_sq_wqebbs);
1167 param->wq.db_numa_node = cpu_to_node(c->cpu);
1168 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1171 wq->db = &wq->db[MLX5_SND_DBR];
1173 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1175 goto err_sq_wq_destroy;
1180 mlx5_wq_destroy(&sq->wq_ctrl);
1185 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1187 mlx5e_free_xdpsq_db(sq);
1188 mlx5_wq_destroy(&sq->wq_ctrl);
1191 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1193 kvfree(sq->db.wqe_info);
1196 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1198 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1201 size = array_size(wq_sz, sizeof(*sq->db.wqe_info));
1202 sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa);
1203 if (!sq->db.wqe_info)
1209 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1211 struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1214 mlx5e_reporter_icosq_cqe_err(sq);
1217 static void mlx5e_async_icosq_err_cqe_work(struct work_struct *recover_work)
1219 struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1222 /* Not implemented yet. */
1224 netdev_warn(sq->channel->netdev, "async_icosq recovery is not implemented\n");
1227 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1228 struct mlx5e_sq_param *param,
1229 struct mlx5e_icosq *sq,
1230 work_func_t recover_work_func)
1232 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1233 struct mlx5_core_dev *mdev = c->mdev;
1234 struct mlx5_wq_cyc *wq = &sq->wq;
1238 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
1239 sq->reserved_room = param->stop_room;
1240 sq->max_sq_wqebbs = mlx5e_get_max_sq_wqebbs(mdev);
1242 param->wq.db_numa_node = cpu_to_node(c->cpu);
1243 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1246 wq->db = &wq->db[MLX5_SND_DBR];
1248 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1250 goto err_sq_wq_destroy;
1252 INIT_WORK(&sq->recover_work, recover_work_func);
1257 mlx5_wq_destroy(&sq->wq_ctrl);
1262 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1264 mlx5e_free_icosq_db(sq);
1265 mlx5_wq_destroy(&sq->wq_ctrl);
1268 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1270 kvfree(sq->db.wqe_info);
1271 kvfree(sq->db.skb_fifo.fifo);
1272 kvfree(sq->db.dma_fifo);
1275 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1277 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1278 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1280 sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1281 sizeof(*sq->db.dma_fifo)),
1283 sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz,
1284 sizeof(*sq->db.skb_fifo.fifo)),
1286 sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1287 sizeof(*sq->db.wqe_info)),
1289 if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) {
1290 mlx5e_free_txqsq_db(sq);
1294 sq->dma_fifo_mask = df_sz - 1;
1296 sq->db.skb_fifo.pc = &sq->skb_fifo_pc;
1297 sq->db.skb_fifo.cc = &sq->skb_fifo_cc;
1298 sq->db.skb_fifo.mask = df_sz - 1;
1303 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1305 struct mlx5e_params *params,
1306 struct mlx5e_sq_param *param,
1307 struct mlx5e_txqsq *sq,
1310 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1311 struct mlx5_core_dev *mdev = c->mdev;
1312 struct mlx5_wq_cyc *wq = &sq->wq;
1316 sq->clock = &mdev->clock;
1317 sq->mkey_be = c->mkey_be;
1318 sq->netdev = c->netdev;
1322 sq->txq_ix = txq_ix;
1323 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map;
1324 sq->min_inline_mode = params->tx_min_inline_mode;
1325 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1326 sq->max_sq_wqebbs = mlx5e_get_max_sq_wqebbs(mdev);
1327 sq->max_sq_mpw_wqebbs = mlx5e_get_sw_max_sq_mpw_wqebbs(sq->max_sq_wqebbs);
1328 INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1329 if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1330 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1331 if (mlx5_ipsec_device_caps(c->priv->mdev))
1332 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1334 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state);
1335 sq->stop_room = param->stop_room;
1336 sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev);
1338 param->wq.db_numa_node = cpu_to_node(c->cpu);
1339 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1342 wq->db = &wq->db[MLX5_SND_DBR];
1344 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1346 goto err_sq_wq_destroy;
1348 INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1349 sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1354 mlx5_wq_destroy(&sq->wq_ctrl);
1359 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1361 mlx5e_free_txqsq_db(sq);
1362 mlx5_wq_destroy(&sq->wq_ctrl);
1365 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1366 struct mlx5e_sq_param *param,
1367 struct mlx5e_create_sq_param *csp,
1377 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1378 sizeof(u64) * csp->wq_ctrl->buf.npages;
1379 in = kvzalloc(inlen, GFP_KERNEL);
1383 ts_format = mlx5_is_real_time_sq(mdev) ?
1384 MLX5_TIMESTAMP_FORMAT_REAL_TIME :
1385 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING;
1386 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1387 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1389 memcpy(sqc, param->sqc, sizeof(param->sqc));
1390 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1391 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1392 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1393 MLX5_SET(sqc, sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn);
1394 MLX5_SET(sqc, sqc, ts_format, ts_format);
1397 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1398 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1400 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1401 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1403 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1404 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.hw_objs.bfreg.index);
1405 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1406 MLX5_ADAPTER_PAGE_SHIFT);
1407 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1409 mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1410 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1412 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1419 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1420 struct mlx5e_modify_sq_param *p)
1428 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1429 in = kvzalloc(inlen, GFP_KERNEL);
1433 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1435 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1436 MLX5_SET(sqc, sqc, state, p->next_state);
1437 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1439 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1441 if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) {
1443 MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id);
1445 MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask);
1447 err = mlx5_core_modify_sq(mdev, sqn, in);
1454 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1456 mlx5_core_destroy_sq(mdev, sqn);
1459 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1460 struct mlx5e_sq_param *param,
1461 struct mlx5e_create_sq_param *csp,
1462 u16 qos_queue_group_id,
1465 struct mlx5e_modify_sq_param msp = {0};
1468 err = mlx5e_create_sq(mdev, param, csp, sqn);
1472 msp.curr_state = MLX5_SQC_STATE_RST;
1473 msp.next_state = MLX5_SQC_STATE_RDY;
1474 if (qos_queue_group_id) {
1475 msp.qos_update = true;
1476 msp.qos_queue_group_id = qos_queue_group_id;
1478 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1480 mlx5e_destroy_sq(mdev, *sqn);
1485 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1486 struct mlx5e_txqsq *sq, u32 rate);
1488 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1489 struct mlx5e_params *params, struct mlx5e_sq_param *param,
1490 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id,
1491 struct mlx5e_sq_stats *sq_stats)
1493 struct mlx5e_create_sq_param csp = {};
1497 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1501 sq->stats = sq_stats;
1505 csp.cqn = sq->cq.mcq.cqn;
1506 csp.wq_ctrl = &sq->wq_ctrl;
1507 csp.min_inline_mode = sq->min_inline_mode;
1508 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn);
1510 goto err_free_txqsq;
1512 tx_rate = c->priv->tx_rates[sq->txq_ix];
1514 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1516 if (params->tx_dim_enabled)
1517 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1522 mlx5e_free_txqsq(sq);
1527 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1529 sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix);
1530 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1531 netdev_tx_reset_queue(sq->txq);
1532 netif_tx_start_queue(sq->txq);
1535 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1537 __netif_tx_lock_bh(txq);
1538 netif_tx_stop_queue(txq);
1539 __netif_tx_unlock_bh(txq);
1542 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1544 struct mlx5_wq_cyc *wq = &sq->wq;
1546 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1547 synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */
1549 mlx5e_tx_disable_queue(sq->txq);
1551 /* last doorbell out, godspeed .. */
1552 if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1553 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1554 struct mlx5e_tx_wqe *nop;
1556 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) {
1560 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1561 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1565 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1567 struct mlx5_core_dev *mdev = sq->mdev;
1568 struct mlx5_rate_limit rl = {0};
1570 cancel_work_sync(&sq->dim.work);
1571 cancel_work_sync(&sq->recover_work);
1572 mlx5e_destroy_sq(mdev, sq->sqn);
1573 if (sq->rate_limit) {
1574 rl.rate = sq->rate_limit;
1575 mlx5_rl_remove_rate(mdev, &rl);
1577 mlx5e_free_txqsq_descs(sq);
1578 mlx5e_free_txqsq(sq);
1581 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1583 struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1586 mlx5e_reporter_tx_err_cqe(sq);
1589 static int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1590 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq,
1591 work_func_t recover_work_func)
1593 struct mlx5e_create_sq_param csp = {};
1596 err = mlx5e_alloc_icosq(c, param, sq, recover_work_func);
1600 csp.cqn = sq->cq.mcq.cqn;
1601 csp.wq_ctrl = &sq->wq_ctrl;
1602 csp.min_inline_mode = params->tx_min_inline_mode;
1603 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1605 goto err_free_icosq;
1607 if (param->is_tls) {
1608 sq->ktls_resync = mlx5e_ktls_rx_resync_create_resp_list();
1609 if (IS_ERR(sq->ktls_resync)) {
1610 err = PTR_ERR(sq->ktls_resync);
1611 goto err_destroy_icosq;
1617 mlx5e_destroy_sq(c->mdev, sq->sqn);
1619 mlx5e_free_icosq(sq);
1624 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1626 set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1629 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1631 clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1632 synchronize_net(); /* Sync with NAPI. */
1635 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1637 struct mlx5e_channel *c = sq->channel;
1639 if (sq->ktls_resync)
1640 mlx5e_ktls_rx_resync_destroy_resp_list(sq->ktls_resync);
1641 mlx5e_destroy_sq(c->mdev, sq->sqn);
1642 mlx5e_free_icosq_descs(sq);
1643 mlx5e_free_icosq(sq);
1646 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1647 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1648 struct mlx5e_xdpsq *sq, bool is_redirect)
1650 struct mlx5e_create_sq_param csp = {};
1653 err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect);
1658 csp.tisn = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1659 csp.cqn = sq->cq.mcq.cqn;
1660 csp.wq_ctrl = &sq->wq_ctrl;
1661 csp.min_inline_mode = sq->min_inline_mode;
1662 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1664 /* Don't enable multi buffer on XDP_REDIRECT SQ, as it's not yet
1665 * supported by upstream, and there is no defined trigger to allow
1666 * transmitting redirected multi-buffer frames.
1668 if (param->is_xdp_mb && !is_redirect)
1669 set_bit(MLX5E_SQ_STATE_XDP_MULTIBUF, &sq->state);
1671 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn);
1673 goto err_free_xdpsq;
1675 mlx5e_set_xmit_fp(sq, param->is_mpw);
1677 if (!param->is_mpw && !test_bit(MLX5E_SQ_STATE_XDP_MULTIBUF, &sq->state)) {
1678 unsigned int ds_cnt = MLX5E_TX_WQE_EMPTY_DS_COUNT + 1;
1679 unsigned int inline_hdr_sz = 0;
1682 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1683 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1687 /* Pre initialize fixed WQE fields */
1688 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1689 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1690 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1691 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1692 struct mlx5_wqe_data_seg *dseg;
1694 sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) {
1699 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1700 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1702 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1703 dseg->lkey = sq->mkey_be;
1710 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1711 mlx5e_free_xdpsq(sq);
1716 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1718 struct mlx5e_channel *c = sq->channel;
1720 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1721 synchronize_net(); /* Sync with NAPI. */
1723 mlx5e_destroy_sq(c->mdev, sq->sqn);
1724 mlx5e_free_xdpsq_descs(sq);
1725 mlx5e_free_xdpsq(sq);
1728 static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv,
1729 struct mlx5e_cq_param *param,
1730 struct mlx5e_cq *cq)
1732 struct mlx5_core_dev *mdev = priv->mdev;
1733 struct mlx5_core_cq *mcq = &cq->mcq;
1737 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1743 mcq->set_ci_db = cq->wq_ctrl.db.db;
1744 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1745 *mcq->set_ci_db = 0;
1747 mcq->vector = param->eq_ix;
1748 mcq->comp = mlx5e_completion_event;
1749 mcq->event = mlx5e_cq_error_event;
1751 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1752 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1758 cq->netdev = priv->netdev;
1764 static int mlx5e_alloc_cq(struct mlx5e_priv *priv,
1765 struct mlx5e_cq_param *param,
1766 struct mlx5e_create_cq_param *ccp,
1767 struct mlx5e_cq *cq)
1771 param->wq.buf_numa_node = ccp->node;
1772 param->wq.db_numa_node = ccp->node;
1773 param->eq_ix = ccp->ix;
1775 err = mlx5e_alloc_cq_common(priv, param, cq);
1777 cq->napi = ccp->napi;
1778 cq->ch_stats = ccp->ch_stats;
1783 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1785 mlx5_wq_destroy(&cq->wq_ctrl);
1788 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1790 u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1791 struct mlx5_core_dev *mdev = cq->mdev;
1792 struct mlx5_core_cq *mcq = &cq->mcq;
1800 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn);
1804 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1805 sizeof(u64) * cq->wq_ctrl.buf.npages;
1806 in = kvzalloc(inlen, GFP_KERNEL);
1810 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1812 memcpy(cqc, param->cqc, sizeof(param->cqc));
1814 mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1815 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1817 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1818 MLX5_SET(cqc, cqc, c_eqn_or_apu_element, eqn);
1819 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1820 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1821 MLX5_ADAPTER_PAGE_SHIFT);
1822 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1824 err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1836 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1838 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1841 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
1842 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1843 struct mlx5e_cq *cq)
1845 struct mlx5_core_dev *mdev = priv->mdev;
1848 err = mlx5e_alloc_cq(priv, param, ccp, cq);
1852 err = mlx5e_create_cq(cq, param);
1856 if (MLX5_CAP_GEN(mdev, cq_moderation))
1857 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1866 void mlx5e_close_cq(struct mlx5e_cq *cq)
1868 mlx5e_destroy_cq(cq);
1872 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1873 struct mlx5e_params *params,
1874 struct mlx5e_create_cq_param *ccp,
1875 struct mlx5e_channel_param *cparam)
1880 for (tc = 0; tc < c->num_tc; tc++) {
1881 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->txq_sq.cqp,
1882 ccp, &c->sq[tc].cq);
1884 goto err_close_tx_cqs;
1890 for (tc--; tc >= 0; tc--)
1891 mlx5e_close_cq(&c->sq[tc].cq);
1896 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1900 for (tc = 0; tc < c->num_tc; tc++)
1901 mlx5e_close_cq(&c->sq[tc].cq);
1904 static int mlx5e_mqprio_txq_to_tc(struct netdev_tc_txq *tc_to_txq, unsigned int txq)
1908 for (tc = 0; tc < TC_MAX_QUEUE; tc++)
1909 if (txq - tc_to_txq[tc].offset < tc_to_txq[tc].count)
1912 WARN(1, "Unexpected TCs configuration. No match found for txq %u", txq);
1916 static int mlx5e_txq_get_qos_node_hw_id(struct mlx5e_params *params, int txq_ix,
1921 if (params->mqprio.mode != TC_MQPRIO_MODE_CHANNEL ||
1922 !params->mqprio.channel.rl) {
1927 tc = mlx5e_mqprio_txq_to_tc(params->mqprio.tc_to_txq, txq_ix);
1931 return mlx5e_mqprio_rl_get_node_hw_id(params->mqprio.channel.rl, tc, hw_id);
1934 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1935 struct mlx5e_params *params,
1936 struct mlx5e_channel_param *cparam)
1940 for (tc = 0; tc < mlx5e_get_dcb_num_tc(params); tc++) {
1941 int txq_ix = c->ix + tc * params->num_channels;
1942 u32 qos_queue_group_id;
1944 err = mlx5e_txq_get_qos_node_hw_id(params, txq_ix, &qos_queue_group_id);
1948 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1949 params, &cparam->txq_sq, &c->sq[tc], tc,
1951 &c->priv->channel_stats[c->ix]->sq[tc]);
1959 for (tc--; tc >= 0; tc--)
1960 mlx5e_close_txqsq(&c->sq[tc]);
1965 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1969 for (tc = 0; tc < c->num_tc; tc++)
1970 mlx5e_close_txqsq(&c->sq[tc]);
1973 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1974 struct mlx5e_txqsq *sq, u32 rate)
1976 struct mlx5e_priv *priv = netdev_priv(dev);
1977 struct mlx5_core_dev *mdev = priv->mdev;
1978 struct mlx5e_modify_sq_param msp = {0};
1979 struct mlx5_rate_limit rl = {0};
1983 if (rate == sq->rate_limit)
1987 if (sq->rate_limit) {
1988 rl.rate = sq->rate_limit;
1989 /* remove current rl index to free space to next ones */
1990 mlx5_rl_remove_rate(mdev, &rl);
1997 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1999 netdev_err(dev, "Failed configuring rate %u: %d\n",
2005 msp.curr_state = MLX5_SQC_STATE_RDY;
2006 msp.next_state = MLX5_SQC_STATE_RDY;
2007 msp.rl_index = rl_index;
2008 msp.rl_update = true;
2009 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
2011 netdev_err(dev, "Failed configuring rate %u: %d\n",
2013 /* remove the rate from the table */
2015 mlx5_rl_remove_rate(mdev, &rl);
2019 sq->rate_limit = rate;
2023 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
2025 struct mlx5e_priv *priv = netdev_priv(dev);
2026 struct mlx5_core_dev *mdev = priv->mdev;
2027 struct mlx5e_txqsq *sq = priv->txq2sq[index];
2030 if (!mlx5_rl_is_supported(mdev)) {
2031 netdev_err(dev, "Rate limiting is not supported on this device\n");
2035 /* rate is given in Mb/sec, HW config is in Kb/sec */
2038 /* Check whether rate in valid range, 0 is always valid */
2039 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
2040 netdev_err(dev, "TX rate %u, is not in range\n", rate);
2044 mutex_lock(&priv->state_lock);
2045 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
2046 err = mlx5e_set_sq_maxrate(dev, sq, rate);
2048 priv->tx_rates[index] = rate;
2049 mutex_unlock(&priv->state_lock);
2054 static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
2055 struct mlx5e_rq_param *rq_params)
2059 err = mlx5e_init_rxq_rq(c, params, &c->rq);
2063 return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), &c->rq);
2066 static int mlx5e_open_queues(struct mlx5e_channel *c,
2067 struct mlx5e_params *params,
2068 struct mlx5e_channel_param *cparam)
2070 struct dim_cq_moder icocq_moder = {0, 0};
2071 struct mlx5e_create_cq_param ccp;
2074 mlx5e_build_create_cq_param(&ccp, c);
2076 err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->async_icosq.cqp, &ccp,
2077 &c->async_icosq.cq);
2081 err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->icosq.cqp, &ccp,
2084 goto err_close_async_icosq_cq;
2086 err = mlx5e_open_tx_cqs(c, params, &ccp, cparam);
2088 goto err_close_icosq_cq;
2090 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp,
2093 goto err_close_tx_cqs;
2095 err = mlx5e_open_cq(c->priv, params->rx_cq_moderation, &cparam->rq.cqp, &ccp,
2098 goto err_close_xdp_tx_cqs;
2100 err = c->xdp ? mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp,
2101 &ccp, &c->rq_xdpsq.cq) : 0;
2103 goto err_close_rx_cq;
2105 spin_lock_init(&c->async_icosq_lock);
2107 err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq,
2108 mlx5e_async_icosq_err_cqe_work);
2110 goto err_close_xdpsq_cq;
2112 mutex_init(&c->icosq_recovery_lock);
2114 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq,
2115 mlx5e_icosq_err_cqe_work);
2117 goto err_close_async_icosq;
2119 err = mlx5e_open_sqs(c, params, cparam);
2121 goto err_close_icosq;
2123 err = mlx5e_open_rxq_rq(c, params, &cparam->rq);
2128 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
2129 &c->rq_xdpsq, false);
2134 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
2136 goto err_close_xdp_sq;
2142 mlx5e_close_xdpsq(&c->rq_xdpsq);
2145 mlx5e_close_rq(&c->rq);
2151 mlx5e_close_icosq(&c->icosq);
2153 err_close_async_icosq:
2154 mlx5e_close_icosq(&c->async_icosq);
2158 mlx5e_close_cq(&c->rq_xdpsq.cq);
2161 mlx5e_close_cq(&c->rq.cq);
2163 err_close_xdp_tx_cqs:
2164 mlx5e_close_cq(&c->xdpsq.cq);
2167 mlx5e_close_tx_cqs(c);
2170 mlx5e_close_cq(&c->icosq.cq);
2172 err_close_async_icosq_cq:
2173 mlx5e_close_cq(&c->async_icosq.cq);
2178 static void mlx5e_close_queues(struct mlx5e_channel *c)
2180 mlx5e_close_xdpsq(&c->xdpsq);
2182 mlx5e_close_xdpsq(&c->rq_xdpsq);
2183 /* The same ICOSQ is used for UMRs for both RQ and XSKRQ. */
2184 cancel_work_sync(&c->icosq.recover_work);
2185 mlx5e_close_rq(&c->rq);
2187 mlx5e_close_icosq(&c->icosq);
2188 mutex_destroy(&c->icosq_recovery_lock);
2189 mlx5e_close_icosq(&c->async_icosq);
2191 mlx5e_close_cq(&c->rq_xdpsq.cq);
2192 mlx5e_close_cq(&c->rq.cq);
2193 mlx5e_close_cq(&c->xdpsq.cq);
2194 mlx5e_close_tx_cqs(c);
2195 mlx5e_close_cq(&c->icosq.cq);
2196 mlx5e_close_cq(&c->async_icosq.cq);
2199 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
2201 u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
2203 return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
2206 static int mlx5e_channel_stats_alloc(struct mlx5e_priv *priv, int ix, int cpu)
2208 if (ix > priv->stats_nch) {
2209 netdev_warn(priv->netdev, "Unexpected channel stats index %d > %d\n", ix,
2214 if (priv->channel_stats[ix])
2217 /* Asymmetric dynamic memory allocation.
2218 * Freed in mlx5e_priv_arrays_free, not on channel closure.
2220 mlx5e_dbg(DRV, priv, "Creating channel stats %d\n", ix);
2221 priv->channel_stats[ix] = kvzalloc_node(sizeof(**priv->channel_stats),
2222 GFP_KERNEL, cpu_to_node(cpu));
2223 if (!priv->channel_stats[ix])
2230 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
2231 struct mlx5e_params *params,
2232 struct mlx5e_channel_param *cparam,
2233 struct xsk_buff_pool *xsk_pool,
2234 struct mlx5e_channel **cp)
2236 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
2237 struct net_device *netdev = priv->netdev;
2238 struct mlx5e_xsk_param xsk;
2239 struct mlx5e_channel *c;
2243 err = mlx5_vector2irqn(priv->mdev, ix, &irq);
2247 err = mlx5e_channel_stats_alloc(priv, ix, cpu);
2251 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
2256 c->mdev = priv->mdev;
2257 c->tstamp = &priv->tstamp;
2260 c->pdev = mlx5_core_dma_dev(priv->mdev);
2261 c->netdev = priv->netdev;
2262 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey);
2263 c->num_tc = mlx5e_get_dcb_num_tc(params);
2264 c->xdp = !!params->xdp_prog;
2265 c->stats = &priv->channel_stats[ix]->ch;
2266 c->aff_mask = irq_get_effective_affinity_mask(irq);
2267 c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
2269 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
2271 err = mlx5e_open_queues(c, params, cparam);
2276 mlx5e_build_xsk_param(xsk_pool, &xsk);
2277 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c);
2279 goto err_close_queues;
2287 mlx5e_close_queues(c);
2290 netif_napi_del(&c->napi);
2297 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2301 napi_enable(&c->napi);
2303 for (tc = 0; tc < c->num_tc; tc++)
2304 mlx5e_activate_txqsq(&c->sq[tc]);
2305 mlx5e_activate_icosq(&c->icosq);
2306 mlx5e_activate_icosq(&c->async_icosq);
2307 mlx5e_activate_rq(&c->rq);
2309 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2310 mlx5e_activate_xsk(c);
2313 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2317 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2318 mlx5e_deactivate_xsk(c);
2320 mlx5e_deactivate_rq(&c->rq);
2321 mlx5e_deactivate_icosq(&c->async_icosq);
2322 mlx5e_deactivate_icosq(&c->icosq);
2323 for (tc = 0; tc < c->num_tc; tc++)
2324 mlx5e_deactivate_txqsq(&c->sq[tc]);
2325 mlx5e_qos_deactivate_queues(c);
2327 napi_disable(&c->napi);
2330 static void mlx5e_close_channel(struct mlx5e_channel *c)
2332 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2334 mlx5e_close_queues(c);
2335 mlx5e_qos_close_queues(c);
2336 netif_napi_del(&c->napi);
2341 int mlx5e_open_channels(struct mlx5e_priv *priv,
2342 struct mlx5e_channels *chs)
2344 struct mlx5e_channel_param *cparam;
2348 chs->num = chs->params.num_channels;
2350 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2351 cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2352 if (!chs->c || !cparam)
2355 err = mlx5e_build_channel_param(priv->mdev, &chs->params, priv->q_counter, cparam);
2359 for (i = 0; i < chs->num; i++) {
2360 struct xsk_buff_pool *xsk_pool = NULL;
2362 if (chs->params.xdp_prog)
2363 xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i);
2365 err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]);
2367 goto err_close_channels;
2370 if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) {
2371 err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp);
2373 goto err_close_channels;
2376 err = mlx5e_qos_open_queues(priv, chs);
2380 mlx5e_health_channels_update(priv);
2386 mlx5e_ptp_close(chs->ptp);
2389 for (i--; i >= 0; i--)
2390 mlx5e_close_channel(chs->c[i]);
2399 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2403 for (i = 0; i < chs->num; i++)
2404 mlx5e_activate_channel(chs->c[i]);
2407 mlx5e_ptp_activate_channel(chs->ptp);
2410 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2412 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2417 for (i = 0; i < chs->num; i++) {
2418 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2420 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2422 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2423 * doesn't provide any Fill Ring entries at the setup stage.
2427 return err ? -ETIMEDOUT : 0;
2430 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2435 mlx5e_ptp_deactivate_channel(chs->ptp);
2437 for (i = 0; i < chs->num; i++)
2438 mlx5e_deactivate_channel(chs->c[i]);
2441 void mlx5e_close_channels(struct mlx5e_channels *chs)
2446 mlx5e_ptp_close(chs->ptp);
2449 for (i = 0; i < chs->num; i++)
2450 mlx5e_close_channel(chs->c[i]);
2456 static int mlx5e_modify_tirs_packet_merge(struct mlx5e_priv *priv)
2458 struct mlx5e_rx_res *res = priv->rx_res;
2460 return mlx5e_rx_res_packet_merge_set_param(res, &priv->channels.params.packet_merge);
2463 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_packet_merge);
2465 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2466 struct mlx5e_params *params, u16 mtu)
2468 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2471 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2475 /* Update vport context MTU */
2476 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2480 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2481 struct mlx5e_params *params, u16 *mtu)
2486 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2487 if (err || !hw_mtu) /* fallback to port oper mtu */
2488 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2490 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2493 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2495 struct mlx5e_params *params = &priv->channels.params;
2496 struct net_device *netdev = priv->netdev;
2497 struct mlx5_core_dev *mdev = priv->mdev;
2501 err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2505 mlx5e_query_mtu(mdev, params, &mtu);
2506 if (mtu != params->sw_mtu)
2507 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2508 __func__, mtu, params->sw_mtu);
2510 params->sw_mtu = mtu;
2514 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu);
2516 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2518 struct mlx5e_params *params = &priv->channels.params;
2519 struct net_device *netdev = priv->netdev;
2520 struct mlx5_core_dev *mdev = priv->mdev;
2523 /* MTU range: 68 - hw-specific max */
2524 netdev->min_mtu = ETH_MIN_MTU;
2526 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2527 netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2531 static int mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc,
2532 struct netdev_tc_txq *tc_to_txq)
2536 netdev_reset_tc(netdev);
2541 err = netdev_set_num_tc(netdev, ntc);
2543 netdev_WARN(netdev, "netdev_set_num_tc failed (%d), ntc = %d\n", err, ntc);
2547 for (tc = 0; tc < ntc; tc++) {
2550 count = tc_to_txq[tc].count;
2551 offset = tc_to_txq[tc].offset;
2552 netdev_set_tc_queue(netdev, tc, count, offset);
2558 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv)
2560 int qos_queues, nch, ntc, num_txqs, err;
2562 qos_queues = mlx5e_qos_cur_leaf_nodes(priv);
2564 nch = priv->channels.params.num_channels;
2565 ntc = mlx5e_get_dcb_num_tc(&priv->channels.params);
2566 num_txqs = nch * ntc + qos_queues;
2567 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS))
2570 mlx5e_dbg(DRV, priv, "Setting num_txqs %d\n", num_txqs);
2571 err = netif_set_real_num_tx_queues(priv->netdev, num_txqs);
2573 netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err);
2578 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv)
2580 struct netdev_tc_txq old_tc_to_txq[TC_MAX_QUEUE], *tc_to_txq;
2581 struct net_device *netdev = priv->netdev;
2582 int old_num_txqs, old_ntc;
2583 int num_rxqs, nch, ntc;
2587 old_num_txqs = netdev->real_num_tx_queues;
2588 old_ntc = netdev->num_tc ? : 1;
2589 for (i = 0; i < ARRAY_SIZE(old_tc_to_txq); i++)
2590 old_tc_to_txq[i] = netdev->tc_to_txq[i];
2592 nch = priv->channels.params.num_channels;
2593 ntc = priv->channels.params.mqprio.num_tc;
2594 num_rxqs = nch * priv->profile->rq_groups;
2595 tc_to_txq = priv->channels.params.mqprio.tc_to_txq;
2597 err = mlx5e_netdev_set_tcs(netdev, nch, ntc, tc_to_txq);
2600 err = mlx5e_update_tx_netdev_queues(priv);
2603 err = netif_set_real_num_rx_queues(netdev, num_rxqs);
2605 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err);
2608 if (priv->mqprio_rl != priv->channels.params.mqprio.channel.rl) {
2609 if (priv->mqprio_rl) {
2610 mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
2611 mlx5e_mqprio_rl_free(priv->mqprio_rl);
2613 priv->mqprio_rl = priv->channels.params.mqprio.channel.rl;
2619 /* netif_set_real_num_rx_queues could fail only when nch increased. Only
2620 * one of nch and ntc is changed in this function. That means, the call
2621 * to netif_set_real_num_tx_queues below should not fail, because it
2622 * decreases the number of TX queues.
2624 WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs));
2627 WARN_ON_ONCE(mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc,
2633 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_update_netdev_queues);
2635 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv,
2636 struct mlx5e_params *params)
2638 struct mlx5_core_dev *mdev = priv->mdev;
2639 int num_comp_vectors, ix, irq;
2641 num_comp_vectors = mlx5_comp_vectors_count(mdev);
2643 for (ix = 0; ix < params->num_channels; ix++) {
2644 cpumask_clear(priv->scratchpad.cpumask);
2646 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) {
2647 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq));
2649 cpumask_set_cpu(cpu, priv->scratchpad.cpumask);
2652 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix);
2656 static int mlx5e_num_channels_changed(struct mlx5e_priv *priv)
2658 u16 count = priv->channels.params.num_channels;
2661 err = mlx5e_update_netdev_queues(priv);
2665 mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params);
2667 /* This function may be called on attach, before priv->rx_res is created. */
2668 if (!netif_is_rxfh_configured(priv->netdev) && priv->rx_res)
2669 mlx5e_rx_res_rss_set_indir_uniform(priv->rx_res, count);
2674 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed);
2676 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2678 int i, ch, tc, num_tc;
2680 ch = priv->channels.num;
2681 num_tc = mlx5e_get_dcb_num_tc(&priv->channels.params);
2683 for (i = 0; i < ch; i++) {
2684 for (tc = 0; tc < num_tc; tc++) {
2685 struct mlx5e_channel *c = priv->channels.c[i];
2686 struct mlx5e_txqsq *sq = &c->sq[tc];
2688 priv->txq2sq[sq->txq_ix] = sq;
2692 if (!priv->channels.ptp)
2695 if (!test_bit(MLX5E_PTP_STATE_TX, priv->channels.ptp->state))
2698 for (tc = 0; tc < num_tc; tc++) {
2699 struct mlx5e_ptp *c = priv->channels.ptp;
2700 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq;
2702 priv->txq2sq[sq->txq_ix] = sq;
2706 /* Make the change to txq2sq visible before the queue is started.
2707 * As mlx5e_xmit runs under a spinlock, there is an implicit ACQUIRE,
2708 * which pairs with this barrier.
2713 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2715 mlx5e_build_txq_maps(priv);
2716 mlx5e_activate_channels(&priv->channels);
2717 mlx5e_qos_activate_queues(priv);
2718 mlx5e_xdp_tx_enable(priv);
2720 /* dev_watchdog() wants all TX queues to be started when the carrier is
2721 * OK, including the ones in range real_num_tx_queues..num_tx_queues-1.
2722 * Make it happy to avoid TX timeout false alarms.
2724 netif_tx_start_all_queues(priv->netdev);
2726 if (mlx5e_is_vport_rep(priv))
2727 mlx5e_add_sqs_fwd_rules(priv);
2729 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2732 mlx5e_rx_res_channels_activate(priv->rx_res, &priv->channels);
2735 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2738 mlx5e_rx_res_channels_deactivate(priv->rx_res);
2740 if (mlx5e_is_vport_rep(priv))
2741 mlx5e_remove_sqs_fwd_rules(priv);
2743 /* The results of ndo_select_queue are unreliable, while netdev config
2744 * is being changed (real_num_tx_queues, num_tc). Stop all queues to
2745 * prevent ndo_start_xmit from being called, so that it can assume that
2746 * the selected queue is always valid.
2748 netif_tx_disable(priv->netdev);
2750 mlx5e_xdp_tx_disable(priv);
2751 mlx5e_deactivate_channels(&priv->channels);
2754 static int mlx5e_switch_priv_params(struct mlx5e_priv *priv,
2755 struct mlx5e_params *new_params,
2756 mlx5e_fp_preactivate preactivate,
2759 struct mlx5e_params old_params;
2761 old_params = priv->channels.params;
2762 priv->channels.params = *new_params;
2767 err = preactivate(priv, context);
2769 priv->channels.params = old_params;
2777 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2778 struct mlx5e_channels *new_chs,
2779 mlx5e_fp_preactivate preactivate,
2782 struct net_device *netdev = priv->netdev;
2783 struct mlx5e_channels old_chs;
2787 carrier_ok = netif_carrier_ok(netdev);
2788 netif_carrier_off(netdev);
2790 mlx5e_deactivate_priv_channels(priv);
2792 old_chs = priv->channels;
2793 priv->channels = *new_chs;
2795 /* New channels are ready to roll, call the preactivate hook if needed
2796 * to modify HW settings or update kernel parameters.
2799 err = preactivate(priv, context);
2801 priv->channels = old_chs;
2806 mlx5e_close_channels(&old_chs);
2807 priv->profile->update_rx(priv);
2809 mlx5e_selq_apply(&priv->selq);
2811 mlx5e_activate_priv_channels(priv);
2813 /* return carrier back if needed */
2815 netif_carrier_on(netdev);
2820 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
2821 struct mlx5e_params *params,
2822 mlx5e_fp_preactivate preactivate,
2823 void *context, bool reset)
2825 struct mlx5e_channels new_chs = {};
2828 reset &= test_bit(MLX5E_STATE_OPENED, &priv->state);
2830 return mlx5e_switch_priv_params(priv, params, preactivate, context);
2832 new_chs.params = *params;
2834 mlx5e_selq_prepare(&priv->selq, &new_chs.params, !!priv->htb.maj_id);
2836 err = mlx5e_open_channels(priv, &new_chs);
2838 goto err_cancel_selq;
2840 err = mlx5e_switch_priv_channels(priv, &new_chs, preactivate, context);
2847 mlx5e_close_channels(&new_chs);
2850 mlx5e_selq_cancel(&priv->selq);
2854 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2856 return mlx5e_safe_switch_params(priv, &priv->channels.params, NULL, NULL, true);
2859 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2861 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
2862 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2865 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev,
2866 enum mlx5_port_status state)
2868 struct mlx5_eswitch *esw = mdev->priv.eswitch;
2869 int vport_admin_state;
2871 mlx5_set_port_admin_status(mdev, state);
2873 if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS ||
2874 !MLX5_CAP_GEN(mdev, uplink_follow))
2877 if (state == MLX5_PORT_UP)
2878 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO;
2880 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN;
2882 mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state);
2885 int mlx5e_open_locked(struct net_device *netdev)
2887 struct mlx5e_priv *priv = netdev_priv(netdev);
2890 mlx5e_selq_prepare(&priv->selq, &priv->channels.params, !!priv->htb.maj_id);
2892 set_bit(MLX5E_STATE_OPENED, &priv->state);
2894 err = mlx5e_open_channels(priv, &priv->channels);
2896 goto err_clear_state_opened_flag;
2898 priv->profile->update_rx(priv);
2899 mlx5e_selq_apply(&priv->selq);
2900 mlx5e_activate_priv_channels(priv);
2901 mlx5e_apply_traps(priv, true);
2902 if (priv->profile->update_carrier)
2903 priv->profile->update_carrier(priv);
2905 mlx5e_queue_update_stats(priv);
2908 err_clear_state_opened_flag:
2909 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2910 mlx5e_selq_cancel(&priv->selq);
2914 int mlx5e_open(struct net_device *netdev)
2916 struct mlx5e_priv *priv = netdev_priv(netdev);
2919 mutex_lock(&priv->state_lock);
2920 err = mlx5e_open_locked(netdev);
2922 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP);
2923 mutex_unlock(&priv->state_lock);
2928 int mlx5e_close_locked(struct net_device *netdev)
2930 struct mlx5e_priv *priv = netdev_priv(netdev);
2932 /* May already be CLOSED in case a previous configuration operation
2933 * (e.g RX/TX queue size change) that involves close&open failed.
2935 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2938 mlx5e_apply_traps(priv, false);
2939 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2941 netif_carrier_off(priv->netdev);
2942 mlx5e_deactivate_priv_channels(priv);
2943 mlx5e_close_channels(&priv->channels);
2948 int mlx5e_close(struct net_device *netdev)
2950 struct mlx5e_priv *priv = netdev_priv(netdev);
2953 if (!netif_device_present(netdev))
2956 mutex_lock(&priv->state_lock);
2957 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN);
2958 err = mlx5e_close_locked(netdev);
2959 mutex_unlock(&priv->state_lock);
2964 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq)
2966 mlx5_wq_destroy(&rq->wq_ctrl);
2969 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2970 struct mlx5e_rq *rq,
2971 struct mlx5e_rq_param *param)
2973 void *rqc = param->rqc;
2974 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2977 param->wq.db_numa_node = param->wq.buf_numa_node;
2979 err = mlx5_wq_cyc_create(mdev, ¶m->wq, rqc_wq, &rq->wqe.wq,
2984 /* Mark as unused given "Drop-RQ" packets never reach XDP */
2985 xdp_rxq_info_unused(&rq->xdp_rxq);
2992 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv,
2993 struct mlx5e_cq *cq,
2994 struct mlx5e_cq_param *param)
2996 struct mlx5_core_dev *mdev = priv->mdev;
2998 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
2999 param->wq.db_numa_node = dev_to_node(mlx5_core_dma_dev(mdev));
3001 return mlx5e_alloc_cq_common(priv, param, cq);
3004 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3005 struct mlx5e_rq *drop_rq)
3007 struct mlx5_core_dev *mdev = priv->mdev;
3008 struct mlx5e_cq_param cq_param = {};
3009 struct mlx5e_rq_param rq_param = {};
3010 struct mlx5e_cq *cq = &drop_rq->cq;
3013 mlx5e_build_drop_rq_param(mdev, priv->drop_rq_q_counter, &rq_param);
3015 err = mlx5e_alloc_drop_cq(priv, cq, &cq_param);
3019 err = mlx5e_create_cq(cq, &cq_param);
3023 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3025 goto err_destroy_cq;
3027 err = mlx5e_create_rq(drop_rq, &rq_param);
3031 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3033 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3038 mlx5e_free_drop_rq(drop_rq);
3041 mlx5e_destroy_cq(cq);
3049 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3051 mlx5e_destroy_rq(drop_rq);
3052 mlx5e_free_drop_rq(drop_rq);
3053 mlx5e_destroy_cq(&drop_rq->cq);
3054 mlx5e_free_cq(&drop_rq->cq);
3057 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3059 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3061 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn);
3063 if (MLX5_GET(tisc, tisc, tls_en))
3064 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.hw_objs.pdn);
3066 if (mlx5_lag_is_lacp_owner(mdev))
3067 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3069 return mlx5_core_create_tis(mdev, in, tisn);
3072 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3074 mlx5_core_destroy_tis(mdev, tisn);
3077 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3081 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3082 for (tc = 0; tc < priv->profile->max_tc; tc++)
3083 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3086 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3088 return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3091 int mlx5e_create_tises(struct mlx5e_priv *priv)
3096 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3097 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3098 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3101 tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3103 MLX5_SET(tisc, tisc, prio, tc << 1);
3105 if (mlx5e_lag_should_assign_affinity(priv->mdev))
3106 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3108 err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3110 goto err_close_tises;
3117 for (; i >= 0; i--) {
3118 for (tc--; tc >= 0; tc--)
3119 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3120 tc = priv->profile->max_tc;
3126 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3128 mlx5e_destroy_tises(priv);
3131 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3136 for (i = 0; i < chs->num; i++) {
3137 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3145 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3150 for (i = 0; i < chs->num; i++) {
3151 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3155 if (chs->ptp && test_bit(MLX5E_PTP_STATE_RX, chs->ptp->state))
3156 return mlx5e_modify_rq_vsd(&chs->ptp->rq, vsd);
3161 static void mlx5e_mqprio_build_default_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
3166 memset(tc_to_txq, 0, sizeof(*tc_to_txq) * TC_MAX_QUEUE);
3168 /* Map netdev TCs to offset 0.
3169 * We have our own UP to TXQ mapping for DCB mode of QoS
3171 for (tc = 0; tc < ntc; tc++) {
3172 tc_to_txq[tc] = (struct netdev_tc_txq) {
3179 static void mlx5e_mqprio_build_tc_to_txq(struct netdev_tc_txq *tc_to_txq,
3180 struct tc_mqprio_qopt *qopt)
3184 for (tc = 0; tc < TC_MAX_QUEUE; tc++) {
3185 tc_to_txq[tc] = (struct netdev_tc_txq) {
3186 .count = qopt->count[tc],
3187 .offset = qopt->offset[tc],
3192 static void mlx5e_params_mqprio_dcb_set(struct mlx5e_params *params, u8 num_tc)
3194 params->mqprio.mode = TC_MQPRIO_MODE_DCB;
3195 params->mqprio.num_tc = num_tc;
3196 params->mqprio.channel.rl = NULL;
3197 mlx5e_mqprio_build_default_tc_to_txq(params->mqprio.tc_to_txq, num_tc,
3198 params->num_channels);
3201 static void mlx5e_params_mqprio_channel_set(struct mlx5e_params *params,
3202 struct tc_mqprio_qopt *qopt,
3203 struct mlx5e_mqprio_rl *rl)
3205 params->mqprio.mode = TC_MQPRIO_MODE_CHANNEL;
3206 params->mqprio.num_tc = qopt->num_tc;
3207 params->mqprio.channel.rl = rl;
3208 mlx5e_mqprio_build_tc_to_txq(params->mqprio.tc_to_txq, qopt);
3211 static void mlx5e_params_mqprio_reset(struct mlx5e_params *params)
3213 mlx5e_params_mqprio_dcb_set(params, 1);
3216 static int mlx5e_setup_tc_mqprio_dcb(struct mlx5e_priv *priv,
3217 struct tc_mqprio_qopt *mqprio)
3219 struct mlx5e_params new_params;
3220 u8 tc = mqprio->num_tc;
3223 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3225 if (tc && tc != MLX5E_MAX_NUM_TC)
3228 new_params = priv->channels.params;
3229 mlx5e_params_mqprio_dcb_set(&new_params, tc ? tc : 1);
3231 err = mlx5e_safe_switch_params(priv, &new_params,
3232 mlx5e_num_channels_changed_ctx, NULL, true);
3234 priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3235 mlx5e_get_dcb_num_tc(&priv->channels.params));
3239 static int mlx5e_mqprio_channel_validate(struct mlx5e_priv *priv,
3240 struct tc_mqprio_qopt_offload *mqprio)
3242 struct net_device *netdev = priv->netdev;
3243 struct mlx5e_ptp *ptp_channel;
3247 ptp_channel = priv->channels.ptp;
3248 if (ptp_channel && test_bit(MLX5E_PTP_STATE_TX, ptp_channel->state)) {
3250 "Cannot activate MQPRIO mode channel since it conflicts with TX port TS\n");
3254 if (mqprio->qopt.offset[0] != 0 || mqprio->qopt.num_tc < 1 ||
3255 mqprio->qopt.num_tc > MLX5E_MAX_NUM_MQPRIO_CH_TC)
3258 for (i = 0; i < mqprio->qopt.num_tc; i++) {
3259 if (!mqprio->qopt.count[i]) {
3260 netdev_err(netdev, "Zero size for queue-group (%d) is not supported\n", i);
3263 if (mqprio->min_rate[i]) {
3264 netdev_err(netdev, "Min tx rate is not supported\n");
3268 if (mqprio->max_rate[i]) {
3271 err = mlx5e_qos_bytes_rate_check(priv->mdev, mqprio->max_rate[i]);
3276 if (mqprio->qopt.offset[i] != agg_count) {
3277 netdev_err(netdev, "Discontinuous queues config is not supported\n");
3280 agg_count += mqprio->qopt.count[i];
3283 if (priv->channels.params.num_channels != agg_count) {
3284 netdev_err(netdev, "Num of queues (%d) does not match available (%d)\n",
3285 agg_count, priv->channels.params.num_channels);
3292 static bool mlx5e_mqprio_rate_limit(struct tc_mqprio_qopt_offload *mqprio)
3296 for (tc = 0; tc < mqprio->qopt.num_tc; tc++)
3297 if (mqprio->max_rate[tc])
3302 static int mlx5e_setup_tc_mqprio_channel(struct mlx5e_priv *priv,
3303 struct tc_mqprio_qopt_offload *mqprio)
3305 mlx5e_fp_preactivate preactivate;
3306 struct mlx5e_params new_params;
3307 struct mlx5e_mqprio_rl *rl;
3311 err = mlx5e_mqprio_channel_validate(priv, mqprio);
3316 if (mlx5e_mqprio_rate_limit(mqprio)) {
3317 rl = mlx5e_mqprio_rl_alloc();
3320 err = mlx5e_mqprio_rl_init(rl, priv->mdev, mqprio->qopt.num_tc,
3323 mlx5e_mqprio_rl_free(rl);
3328 new_params = priv->channels.params;
3329 mlx5e_params_mqprio_channel_set(&new_params, &mqprio->qopt, rl);
3331 nch_changed = mlx5e_get_dcb_num_tc(&priv->channels.params) > 1;
3332 preactivate = nch_changed ? mlx5e_num_channels_changed_ctx :
3333 mlx5e_update_netdev_queues_ctx;
3334 err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, true);
3336 mlx5e_mqprio_rl_cleanup(rl);
3337 mlx5e_mqprio_rl_free(rl);
3343 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3344 struct tc_mqprio_qopt_offload *mqprio)
3346 /* MQPRIO is another toplevel qdisc that can't be attached
3347 * simultaneously with the offloaded HTB.
3349 if (WARN_ON(priv->htb.maj_id))
3352 switch (mqprio->mode) {
3353 case TC_MQPRIO_MODE_DCB:
3354 return mlx5e_setup_tc_mqprio_dcb(priv, &mqprio->qopt);
3355 case TC_MQPRIO_MODE_CHANNEL:
3356 return mlx5e_setup_tc_mqprio_channel(priv, mqprio);
3362 static int mlx5e_setup_tc_htb(struct mlx5e_priv *priv, struct tc_htb_qopt_offload *htb)
3366 switch (htb->command) {
3368 return mlx5e_htb_root_add(priv, htb->parent_classid, htb->classid,
3370 case TC_HTB_DESTROY:
3371 return mlx5e_htb_root_del(priv);
3372 case TC_HTB_LEAF_ALLOC_QUEUE:
3373 res = mlx5e_htb_leaf_alloc_queue(priv, htb->classid, htb->parent_classid,
3374 htb->rate, htb->ceil, htb->extack);
3379 case TC_HTB_LEAF_TO_INNER:
3380 return mlx5e_htb_leaf_to_inner(priv, htb->parent_classid, htb->classid,
3381 htb->rate, htb->ceil, htb->extack);
3382 case TC_HTB_LEAF_DEL:
3383 return mlx5e_htb_leaf_del(priv, &htb->classid, htb->extack);
3384 case TC_HTB_LEAF_DEL_LAST:
3385 case TC_HTB_LEAF_DEL_LAST_FORCE:
3386 return mlx5e_htb_leaf_del_last(priv, htb->classid,
3387 htb->command == TC_HTB_LEAF_DEL_LAST_FORCE,
3389 case TC_HTB_NODE_MODIFY:
3390 return mlx5e_htb_node_modify(priv, htb->classid, htb->rate, htb->ceil,
3392 case TC_HTB_LEAF_QUERY_QUEUE:
3393 res = mlx5e_get_txq_by_classid(priv, htb->classid);
3403 static LIST_HEAD(mlx5e_block_cb_list);
3405 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3408 struct mlx5e_priv *priv = netdev_priv(dev);
3409 bool tc_unbind = false;
3412 if (type == TC_SETUP_BLOCK &&
3413 ((struct flow_block_offload *)type_data)->command == FLOW_BLOCK_UNBIND)
3416 if (!netif_device_present(dev) && !tc_unbind)
3420 case TC_SETUP_BLOCK: {
3421 struct flow_block_offload *f = type_data;
3423 f->unlocked_driver_cb = true;
3424 return flow_block_cb_setup_simple(type_data,
3425 &mlx5e_block_cb_list,
3426 mlx5e_setup_tc_block_cb,
3429 case TC_SETUP_QDISC_MQPRIO:
3430 mutex_lock(&priv->state_lock);
3431 err = mlx5e_setup_tc_mqprio(priv, type_data);
3432 mutex_unlock(&priv->state_lock);
3434 case TC_SETUP_QDISC_HTB:
3435 mutex_lock(&priv->state_lock);
3436 err = mlx5e_setup_tc_htb(priv, type_data);
3437 mutex_unlock(&priv->state_lock);
3444 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3448 for (i = 0; i < priv->stats_nch; i++) {
3449 struct mlx5e_channel_stats *channel_stats = priv->channel_stats[i];
3450 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3451 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3454 s->rx_packets += rq_stats->packets + xskrq_stats->packets;
3455 s->rx_bytes += rq_stats->bytes + xskrq_stats->bytes;
3456 s->multicast += rq_stats->mcast_packets + xskrq_stats->mcast_packets;
3458 for (j = 0; j < priv->max_opened_tc; j++) {
3459 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3461 s->tx_packets += sq_stats->packets;
3462 s->tx_bytes += sq_stats->bytes;
3463 s->tx_dropped += sq_stats->dropped;
3466 if (priv->tx_ptp_opened) {
3467 for (i = 0; i < priv->max_opened_tc; i++) {
3468 struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[i];
3470 s->tx_packets += sq_stats->packets;
3471 s->tx_bytes += sq_stats->bytes;
3472 s->tx_dropped += sq_stats->dropped;
3475 if (priv->rx_ptp_opened) {
3476 struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq;
3478 s->rx_packets += rq_stats->packets;
3479 s->rx_bytes += rq_stats->bytes;
3480 s->multicast += rq_stats->mcast_packets;
3485 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3487 struct mlx5e_priv *priv = netdev_priv(dev);
3488 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3490 if (!netif_device_present(dev))
3493 /* In switchdev mode, monitor counters doesn't monitor
3494 * rx/tx stats of 802_3. The update stats mechanism
3495 * should keep the 802_3 layout counters updated
3497 if (!mlx5e_monitor_counter_supported(priv) ||
3498 mlx5e_is_uplink_rep(priv)) {
3499 /* update HW stats in background for next time */
3500 mlx5e_queue_update_stats(priv);
3503 if (mlx5e_is_uplink_rep(priv)) {
3504 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3506 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3507 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3508 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3509 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3511 /* vport multicast also counts packets that are dropped due to steering
3512 * or rx out of buffer
3514 stats->multicast = VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3516 mlx5e_fold_sw_stats64(priv, stats);
3519 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3521 stats->rx_length_errors =
3522 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3523 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3524 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3525 stats->rx_crc_errors =
3526 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3527 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3528 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3529 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3530 stats->rx_frame_errors;
3531 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3534 static void mlx5e_nic_set_rx_mode(struct mlx5e_priv *priv)
3536 if (mlx5e_is_uplink_rep(priv))
3537 return; /* no rx mode for uplink rep */
3539 queue_work(priv->wq, &priv->set_rx_mode_work);
3542 static void mlx5e_set_rx_mode(struct net_device *dev)
3544 struct mlx5e_priv *priv = netdev_priv(dev);
3546 mlx5e_nic_set_rx_mode(priv);
3549 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3551 struct mlx5e_priv *priv = netdev_priv(netdev);
3552 struct sockaddr *saddr = addr;
3554 if (!is_valid_ether_addr(saddr->sa_data))
3555 return -EADDRNOTAVAIL;
3557 netif_addr_lock_bh(netdev);
3558 eth_hw_addr_set(netdev, saddr->sa_data);
3559 netif_addr_unlock_bh(netdev);
3561 mlx5e_nic_set_rx_mode(priv);
3566 #define MLX5E_SET_FEATURE(features, feature, enable) \
3569 *features |= feature; \
3571 *features &= ~feature; \
3574 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3576 static int set_feature_lro(struct net_device *netdev, bool enable)
3578 struct mlx5e_priv *priv = netdev_priv(netdev);
3579 struct mlx5_core_dev *mdev = priv->mdev;
3580 struct mlx5e_params *cur_params;
3581 struct mlx5e_params new_params;
3585 mutex_lock(&priv->state_lock);
3587 if (enable && priv->xsk.refcnt) {
3588 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n",
3594 cur_params = &priv->channels.params;
3595 if (enable && !MLX5E_GET_PFLAG(cur_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3596 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3601 new_params = *cur_params;
3604 new_params.packet_merge.type = MLX5E_PACKET_MERGE_LRO;
3605 else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)
3606 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE;
3610 if (!(cur_params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO &&
3611 new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)) {
3612 if (cur_params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3613 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) ==
3614 mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_params, NULL))
3619 err = mlx5e_safe_switch_params(priv, &new_params,
3620 mlx5e_modify_tirs_packet_merge_ctx, NULL, reset);
3622 mutex_unlock(&priv->state_lock);
3626 static int set_feature_hw_gro(struct net_device *netdev, bool enable)
3628 struct mlx5e_priv *priv = netdev_priv(netdev);
3629 struct mlx5e_params new_params;
3633 mutex_lock(&priv->state_lock);
3634 new_params = priv->channels.params;
3637 new_params.packet_merge.type = MLX5E_PACKET_MERGE_SHAMPO;
3638 new_params.packet_merge.shampo.match_criteria_type =
3639 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED;
3640 new_params.packet_merge.shampo.alignment_granularity =
3641 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE;
3642 } else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) {
3643 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE;
3648 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
3650 mutex_unlock(&priv->state_lock);
3654 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3656 struct mlx5e_priv *priv = netdev_priv(netdev);
3659 mlx5e_enable_cvlan_filter(priv);
3661 mlx5e_disable_cvlan_filter(priv);
3666 static int set_feature_hw_tc(struct net_device *netdev, bool enable)
3668 struct mlx5e_priv *priv = netdev_priv(netdev);
3670 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
3671 if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3673 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3678 if (!enable && priv->htb.maj_id) {
3679 netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n");
3686 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3688 struct mlx5e_priv *priv = netdev_priv(netdev);
3689 struct mlx5_core_dev *mdev = priv->mdev;
3691 return mlx5_set_port_fcs(mdev, !enable);
3694 static int mlx5e_set_rx_port_ts(struct mlx5_core_dev *mdev, bool enable)
3696 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {};
3697 bool supported, curr_state;
3700 if (!MLX5_CAP_GEN(mdev, ports_check))
3703 err = mlx5_query_ports_check(mdev, in, sizeof(in));
3707 supported = MLX5_GET(pcmr_reg, in, rx_ts_over_crc_cap);
3708 curr_state = MLX5_GET(pcmr_reg, in, rx_ts_over_crc);
3710 if (!supported || enable == curr_state)
3713 MLX5_SET(pcmr_reg, in, local_port, 1);
3714 MLX5_SET(pcmr_reg, in, rx_ts_over_crc, enable);
3716 return mlx5_set_ports_check(mdev, in, sizeof(in));
3719 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3721 struct mlx5e_priv *priv = netdev_priv(netdev);
3722 struct mlx5e_channels *chs = &priv->channels;
3723 struct mlx5_core_dev *mdev = priv->mdev;
3726 mutex_lock(&priv->state_lock);
3729 err = mlx5e_set_rx_port_ts(mdev, false);
3733 chs->params.scatter_fcs_en = true;
3734 err = mlx5e_modify_channels_scatter_fcs(chs, true);
3736 chs->params.scatter_fcs_en = false;
3737 mlx5e_set_rx_port_ts(mdev, true);
3740 chs->params.scatter_fcs_en = false;
3741 err = mlx5e_modify_channels_scatter_fcs(chs, false);
3743 chs->params.scatter_fcs_en = true;
3746 err = mlx5e_set_rx_port_ts(mdev, true);
3748 mlx5_core_warn(mdev, "Failed to set RX port timestamp %d\n", err);
3754 mutex_unlock(&priv->state_lock);
3758 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3760 struct mlx5e_priv *priv = netdev_priv(netdev);
3763 mutex_lock(&priv->state_lock);
3765 priv->channels.params.vlan_strip_disable = !enable;
3766 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3769 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3771 priv->channels.params.vlan_strip_disable = enable;
3774 mutex_unlock(&priv->state_lock);
3779 #ifdef CONFIG_MLX5_EN_ARFS
3780 static int set_feature_arfs(struct net_device *netdev, bool enable)
3782 struct mlx5e_priv *priv = netdev_priv(netdev);
3786 err = mlx5e_arfs_enable(priv);
3788 err = mlx5e_arfs_disable(priv);
3794 static int mlx5e_handle_feature(struct net_device *netdev,
3795 netdev_features_t *features,
3796 netdev_features_t feature,
3797 mlx5e_feature_handler feature_handler)
3799 netdev_features_t changes = *features ^ netdev->features;
3800 bool enable = !!(*features & feature);
3803 if (!(changes & feature))
3806 err = feature_handler(netdev, enable);
3808 MLX5E_SET_FEATURE(features, feature, !enable);
3809 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3810 enable ? "Enable" : "Disable", &feature, err);
3817 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3819 netdev_features_t oper_features = features;
3822 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3823 mlx5e_handle_feature(netdev, &oper_features, feature, handler)
3825 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3826 err |= MLX5E_HANDLE_FEATURE(NETIF_F_GRO_HW, set_feature_hw_gro);
3827 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3828 set_feature_cvlan_filter);
3829 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc);
3830 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3831 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3832 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3833 #ifdef CONFIG_MLX5_EN_ARFS
3834 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3836 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx);
3839 netdev->features = oper_features;
3846 static netdev_features_t mlx5e_fix_uplink_rep_features(struct net_device *netdev,
3847 netdev_features_t features)
3849 features &= ~NETIF_F_HW_TLS_RX;
3850 if (netdev->features & NETIF_F_HW_TLS_RX)
3851 netdev_warn(netdev, "Disabling hw_tls_rx, not supported in switchdev mode\n");
3853 features &= ~NETIF_F_HW_TLS_TX;
3854 if (netdev->features & NETIF_F_HW_TLS_TX)
3855 netdev_warn(netdev, "Disabling hw_tls_tx, not supported in switchdev mode\n");
3857 features &= ~NETIF_F_NTUPLE;
3858 if (netdev->features & NETIF_F_NTUPLE)
3859 netdev_warn(netdev, "Disabling ntuple, not supported in switchdev mode\n");
3864 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3865 netdev_features_t features)
3867 struct mlx5e_priv *priv = netdev_priv(netdev);
3868 struct mlx5e_params *params;
3870 mutex_lock(&priv->state_lock);
3871 params = &priv->channels.params;
3872 if (!priv->fs.vlan ||
3873 !bitmap_empty(mlx5e_vlan_get_active_svlans(priv->fs.vlan), VLAN_N_VID)) {
3874 /* HW strips the outer C-tag header, this is a problem
3875 * for S-tag traffic.
3877 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3878 if (!params->vlan_strip_disable)
3879 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3882 if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3883 if (features & NETIF_F_LRO) {
3884 netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3885 features &= ~NETIF_F_LRO;
3887 if (features & NETIF_F_GRO_HW) {
3888 netdev_warn(netdev, "Disabling HW-GRO, not supported in legacy RQ\n");
3889 features &= ~NETIF_F_GRO_HW;
3893 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3894 features &= ~NETIF_F_RXHASH;
3895 if (netdev->features & NETIF_F_RXHASH)
3896 netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3898 if (features & NETIF_F_GRO_HW) {
3899 netdev_warn(netdev, "Disabling HW-GRO, not supported when CQE compress is active\n");
3900 features &= ~NETIF_F_GRO_HW;
3904 if (mlx5e_is_uplink_rep(priv))
3905 features = mlx5e_fix_uplink_rep_features(netdev, features);
3907 mutex_unlock(&priv->state_lock);
3912 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3913 struct mlx5e_channels *chs,
3914 struct mlx5e_params *new_params,
3915 struct mlx5_core_dev *mdev)
3919 for (ix = 0; ix < chs->params.num_channels; ix++) {
3920 struct xsk_buff_pool *xsk_pool =
3921 mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix);
3922 struct mlx5e_xsk_param xsk;
3927 mlx5e_build_xsk_param(xsk_pool, &xsk);
3929 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3930 u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3931 int max_mtu_frame, max_mtu_page, max_mtu;
3933 /* Two criteria must be met:
3934 * 1. HW MTU + all headrooms <= XSK frame size.
3935 * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3937 max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3938 max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3939 max_mtu = min(max_mtu_frame, max_mtu_page);
3941 netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u. Try MTU <= %d\n",
3942 new_params->sw_mtu, ix, max_mtu);
3950 static bool mlx5e_params_validate_xdp(struct net_device *netdev, struct mlx5e_params *params)
3954 /* No XSK params: AF_XDP can't be enabled yet at the point of setting
3957 is_linear = mlx5e_rx_is_linear_skb(params, NULL);
3959 if (!is_linear && params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3960 netdev_warn(netdev, "XDP is not allowed with striding RQ and MTU(%d) > %d\n",
3962 mlx5e_xdp_max_mtu(params, NULL));
3965 if (!is_linear && !params->xdp_prog->aux->xdp_has_frags) {
3966 netdev_warn(netdev, "MTU(%d) > %d, too big for an XDP program not aware of multi buffer\n",
3968 mlx5e_xdp_max_mtu(params, NULL));
3975 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3976 mlx5e_fp_preactivate preactivate)
3978 struct mlx5e_priv *priv = netdev_priv(netdev);
3979 struct mlx5e_params new_params;
3980 struct mlx5e_params *params;
3984 mutex_lock(&priv->state_lock);
3986 params = &priv->channels.params;
3988 new_params = *params;
3989 new_params.sw_mtu = new_mtu;
3990 err = mlx5e_validate_params(priv->mdev, &new_params);
3994 if (new_params.xdp_prog && !mlx5e_params_validate_xdp(netdev, &new_params)) {
3999 if (priv->xsk.refcnt &&
4000 !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
4001 &new_params, priv->mdev)) {
4006 if (params->packet_merge.type == MLX5E_PACKET_MERGE_LRO)
4009 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4010 bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, params, NULL);
4011 bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
4013 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
4014 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_params, NULL);
4016 /* Always reset in linear mode - hw_mtu is used in data path.
4017 * Check that the mode was non-linear and didn't change.
4018 * If XSK is active, XSK RQs are linear.
4020 if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt &&
4025 err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, reset);
4028 netdev->mtu = params->sw_mtu;
4029 mutex_unlock(&priv->state_lock);
4033 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
4035 return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx);
4038 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx)
4040 bool set = *(bool *)ctx;
4042 return mlx5e_ptp_rx_manage_fs(priv, set);
4045 static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter)
4047 bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4051 /* Reset CQE compression to Admin default */
4052 return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def, false);
4054 if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4057 /* Disable CQE compression */
4058 netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
4059 err = mlx5e_modify_rx_cqe_compression_locked(priv, false, true);
4061 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
4066 static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx)
4068 struct mlx5e_params new_params;
4070 if (ptp_rx == priv->channels.params.ptp_rx)
4073 new_params = priv->channels.params;
4074 new_params.ptp_rx = ptp_rx;
4075 return mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,
4076 &new_params.ptp_rx, true);
4079 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
4081 struct hwtstamp_config config;
4082 bool rx_cqe_compress_def;
4086 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
4087 (mlx5_clock_get_ptp_index(priv->mdev) == -1))
4090 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4093 /* TX HW timestamp */
4094 switch (config.tx_type) {
4095 case HWTSTAMP_TX_OFF:
4096 case HWTSTAMP_TX_ON:
4102 mutex_lock(&priv->state_lock);
4103 rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;
4105 /* RX HW timestamp */
4106 switch (config.rx_filter) {
4107 case HWTSTAMP_FILTER_NONE:
4110 case HWTSTAMP_FILTER_ALL:
4111 case HWTSTAMP_FILTER_SOME:
4112 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4113 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4114 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4115 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4116 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4117 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4118 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4119 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4120 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4121 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4122 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4123 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4124 case HWTSTAMP_FILTER_NTP_ALL:
4125 config.rx_filter = HWTSTAMP_FILTER_ALL;
4126 /* ptp_rx is set if both HW TS is set and CQE
4127 * compression is set
4129 ptp_rx = rx_cqe_compress_def;
4136 if (!mlx5e_profile_feature_cap(priv->profile, PTP_RX))
4137 err = mlx5e_hwstamp_config_no_ptp_rx(priv,
4138 config.rx_filter != HWTSTAMP_FILTER_NONE);
4140 err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx);
4144 memcpy(&priv->tstamp, &config, sizeof(config));
4145 mutex_unlock(&priv->state_lock);
4147 /* might need to fix some features */
4148 netdev_update_features(priv->netdev);
4150 return copy_to_user(ifr->ifr_data, &config,
4151 sizeof(config)) ? -EFAULT : 0;
4153 mutex_unlock(&priv->state_lock);
4157 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4159 struct hwtstamp_config *cfg = &priv->tstamp;
4161 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4164 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4167 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4169 struct mlx5e_priv *priv = netdev_priv(dev);
4173 return mlx5e_hwstamp_set(priv, ifr);
4175 return mlx5e_hwstamp_get(priv, ifr);
4181 #ifdef CONFIG_MLX5_ESWITCH
4182 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4184 struct mlx5e_priv *priv = netdev_priv(dev);
4185 struct mlx5_core_dev *mdev = priv->mdev;
4187 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4190 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4193 struct mlx5e_priv *priv = netdev_priv(dev);
4194 struct mlx5_core_dev *mdev = priv->mdev;
4196 if (vlan_proto != htons(ETH_P_8021Q))
4197 return -EPROTONOSUPPORT;
4199 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4203 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4205 struct mlx5e_priv *priv = netdev_priv(dev);
4206 struct mlx5_core_dev *mdev = priv->mdev;
4208 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4211 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4213 struct mlx5e_priv *priv = netdev_priv(dev);
4214 struct mlx5_core_dev *mdev = priv->mdev;
4216 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4219 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4222 struct mlx5e_priv *priv = netdev_priv(dev);
4223 struct mlx5_core_dev *mdev = priv->mdev;
4225 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4226 max_tx_rate, min_tx_rate);
4229 static int mlx5_vport_link2ifla(u8 esw_link)
4232 case MLX5_VPORT_ADMIN_STATE_DOWN:
4233 return IFLA_VF_LINK_STATE_DISABLE;
4234 case MLX5_VPORT_ADMIN_STATE_UP:
4235 return IFLA_VF_LINK_STATE_ENABLE;
4237 return IFLA_VF_LINK_STATE_AUTO;
4240 static int mlx5_ifla_link2vport(u8 ifla_link)
4242 switch (ifla_link) {
4243 case IFLA_VF_LINK_STATE_DISABLE:
4244 return MLX5_VPORT_ADMIN_STATE_DOWN;
4245 case IFLA_VF_LINK_STATE_ENABLE:
4246 return MLX5_VPORT_ADMIN_STATE_UP;
4248 return MLX5_VPORT_ADMIN_STATE_AUTO;
4251 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4254 struct mlx5e_priv *priv = netdev_priv(dev);
4255 struct mlx5_core_dev *mdev = priv->mdev;
4257 if (mlx5e_is_uplink_rep(priv))
4260 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4261 mlx5_ifla_link2vport(link_state));
4264 int mlx5e_get_vf_config(struct net_device *dev,
4265 int vf, struct ifla_vf_info *ivi)
4267 struct mlx5e_priv *priv = netdev_priv(dev);
4268 struct mlx5_core_dev *mdev = priv->mdev;
4271 if (!netif_device_present(dev))
4274 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4277 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4281 int mlx5e_get_vf_stats(struct net_device *dev,
4282 int vf, struct ifla_vf_stats *vf_stats)
4284 struct mlx5e_priv *priv = netdev_priv(dev);
4285 struct mlx5_core_dev *mdev = priv->mdev;
4287 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4292 mlx5e_has_offload_stats(const struct net_device *dev, int attr_id)
4294 struct mlx5e_priv *priv = netdev_priv(dev);
4296 if (!netif_device_present(dev))
4299 if (!mlx5e_is_uplink_rep(priv))
4302 return mlx5e_rep_has_offload_stats(dev, attr_id);
4306 mlx5e_get_offload_stats(int attr_id, const struct net_device *dev,
4309 struct mlx5e_priv *priv = netdev_priv(dev);
4311 if (!mlx5e_is_uplink_rep(priv))
4314 return mlx5e_rep_get_offload_stats(attr_id, dev, sp);
4318 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type)
4320 switch (proto_type) {
4322 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre);
4325 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) ||
4326 MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx));
4332 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev,
4333 struct sk_buff *skb)
4335 switch (skb->inner_protocol) {
4336 case htons(ETH_P_IP):
4337 case htons(ETH_P_IPV6):
4338 case htons(ETH_P_TEB):
4340 case htons(ETH_P_MPLS_UC):
4341 case htons(ETH_P_MPLS_MC):
4342 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre);
4347 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4348 struct sk_buff *skb,
4349 netdev_features_t features)
4351 unsigned int offset = 0;
4352 struct udphdr *udph;
4356 switch (vlan_get_protocol(skb)) {
4357 case htons(ETH_P_IP):
4358 proto = ip_hdr(skb)->protocol;
4360 case htons(ETH_P_IPV6):
4361 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4369 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb))
4374 if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP))
4378 udph = udp_hdr(skb);
4379 port = be16_to_cpu(udph->dest);
4381 /* Verify if UDP port is being offloaded by HW */
4382 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4385 #if IS_ENABLED(CONFIG_GENEVE)
4386 /* Support Geneve offload for default UDP port */
4387 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4391 #ifdef CONFIG_MLX5_EN_IPSEC
4393 return mlx5e_ipsec_feature_check(skb, features);
4398 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4399 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4402 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4403 struct net_device *netdev,
4404 netdev_features_t features)
4406 struct mlx5e_priv *priv = netdev_priv(netdev);
4408 features = vlan_features_check(skb, features);
4409 features = vxlan_features_check(skb, features);
4411 /* Validate if the tunneled packet is being offloaded by HW */
4412 if (skb->encapsulation &&
4413 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4414 return mlx5e_tunnel_features_check(priv, skb, features);
4419 static void mlx5e_tx_timeout_work(struct work_struct *work)
4421 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4423 struct net_device *netdev = priv->netdev;
4427 mutex_lock(&priv->state_lock);
4429 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4432 for (i = 0; i < netdev->real_num_tx_queues; i++) {
4433 struct netdev_queue *dev_queue =
4434 netdev_get_tx_queue(netdev, i);
4435 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4437 if (!netif_xmit_stopped(dev_queue))
4440 if (mlx5e_reporter_tx_timeout(sq))
4441 /* break if tried to reopened channels */
4446 mutex_unlock(&priv->state_lock);
4450 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4452 struct mlx5e_priv *priv = netdev_priv(dev);
4454 netdev_err(dev, "TX timeout detected\n");
4455 queue_work(priv->wq, &priv->tx_timeout_work);
4458 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4460 struct net_device *netdev = priv->netdev;
4461 struct mlx5e_params new_params;
4463 if (priv->channels.params.packet_merge.type != MLX5E_PACKET_MERGE_NONE) {
4464 netdev_warn(netdev, "can't set XDP while HW-GRO/LRO is on, disable them first\n");
4468 new_params = priv->channels.params;
4469 new_params.xdp_prog = prog;
4471 if (!mlx5e_params_validate_xdp(netdev, &new_params))
4477 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog)
4479 struct bpf_prog *old_prog;
4481 old_prog = rcu_replace_pointer(rq->xdp_prog, prog,
4482 lockdep_is_held(&rq->priv->state_lock));
4484 bpf_prog_put(old_prog);
4487 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4489 struct mlx5e_priv *priv = netdev_priv(netdev);
4490 struct mlx5e_params new_params;
4491 struct bpf_prog *old_prog;
4496 mutex_lock(&priv->state_lock);
4499 err = mlx5e_xdp_allowed(priv, prog);
4504 /* no need for full reset when exchanging programs */
4505 reset = (!priv->channels.params.xdp_prog || !prog);
4507 new_params = priv->channels.params;
4508 new_params.xdp_prog = prog;
4510 mlx5e_set_rq_type(priv->mdev, &new_params);
4511 old_prog = priv->channels.params.xdp_prog;
4513 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
4518 bpf_prog_put(old_prog);
4520 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4523 /* exchanging programs w/o reset, we update ref counts on behalf
4524 * of the channels RQs here.
4526 bpf_prog_add(prog, priv->channels.num);
4527 for (i = 0; i < priv->channels.num; i++) {
4528 struct mlx5e_channel *c = priv->channels.c[i];
4530 mlx5e_rq_replace_xdp_prog(&c->rq, prog);
4531 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) {
4533 mlx5e_rq_replace_xdp_prog(&c->xskrq, prog);
4538 mutex_unlock(&priv->state_lock);
4542 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4544 switch (xdp->command) {
4545 case XDP_SETUP_PROG:
4546 return mlx5e_xdp_set(dev, xdp->prog);
4547 case XDP_SETUP_XSK_POOL:
4548 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool,
4555 #ifdef CONFIG_MLX5_ESWITCH
4556 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4557 struct net_device *dev, u32 filter_mask,
4560 struct mlx5e_priv *priv = netdev_priv(dev);
4561 struct mlx5_core_dev *mdev = priv->mdev;
4565 err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4568 mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4569 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4571 0, 0, nlflags, filter_mask, NULL);
4574 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4575 u16 flags, struct netlink_ext_ack *extack)
4577 struct mlx5e_priv *priv = netdev_priv(dev);
4578 struct mlx5_core_dev *mdev = priv->mdev;
4579 struct nlattr *attr, *br_spec;
4580 u16 mode = BRIDGE_MODE_UNDEF;
4584 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4588 nla_for_each_nested(attr, br_spec, rem) {
4589 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4592 if (nla_len(attr) < sizeof(mode))
4595 mode = nla_get_u16(attr);
4596 if (mode > BRIDGE_MODE_VEPA)
4602 if (mode == BRIDGE_MODE_UNDEF)
4605 setting = (mode == BRIDGE_MODE_VEPA) ? 1 : 0;
4606 return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4610 const struct net_device_ops mlx5e_netdev_ops = {
4611 .ndo_open = mlx5e_open,
4612 .ndo_stop = mlx5e_close,
4613 .ndo_start_xmit = mlx5e_xmit,
4614 .ndo_setup_tc = mlx5e_setup_tc,
4615 .ndo_select_queue = mlx5e_select_queue,
4616 .ndo_get_stats64 = mlx5e_get_stats,
4617 .ndo_set_rx_mode = mlx5e_set_rx_mode,
4618 .ndo_set_mac_address = mlx5e_set_mac,
4619 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
4620 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
4621 .ndo_set_features = mlx5e_set_features,
4622 .ndo_fix_features = mlx5e_fix_features,
4623 .ndo_change_mtu = mlx5e_change_nic_mtu,
4624 .ndo_eth_ioctl = mlx5e_ioctl,
4625 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
4626 .ndo_features_check = mlx5e_features_check,
4627 .ndo_tx_timeout = mlx5e_tx_timeout,
4628 .ndo_bpf = mlx5e_xdp,
4629 .ndo_xdp_xmit = mlx5e_xdp_xmit,
4630 .ndo_xsk_wakeup = mlx5e_xsk_wakeup,
4631 #ifdef CONFIG_MLX5_EN_ARFS
4632 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
4634 #ifdef CONFIG_MLX5_ESWITCH
4635 .ndo_bridge_setlink = mlx5e_bridge_setlink,
4636 .ndo_bridge_getlink = mlx5e_bridge_getlink,
4638 /* SRIOV E-Switch NDOs */
4639 .ndo_set_vf_mac = mlx5e_set_vf_mac,
4640 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
4641 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
4642 .ndo_set_vf_trust = mlx5e_set_vf_trust,
4643 .ndo_set_vf_rate = mlx5e_set_vf_rate,
4644 .ndo_get_vf_config = mlx5e_get_vf_config,
4645 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
4646 .ndo_get_vf_stats = mlx5e_get_vf_stats,
4647 .ndo_has_offload_stats = mlx5e_has_offload_stats,
4648 .ndo_get_offload_stats = mlx5e_get_offload_stats,
4650 .ndo_get_devlink_port = mlx5e_get_devlink_port,
4653 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4657 /* The supported periods are organized in ascending order */
4658 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4659 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4662 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4665 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu)
4667 struct mlx5e_params *params = &priv->channels.params;
4668 struct mlx5_core_dev *mdev = priv->mdev;
4669 u8 rx_cq_period_mode;
4671 params->sw_mtu = mtu;
4672 params->hard_mtu = MLX5E_ETH_HARD_MTU;
4673 params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
4675 mlx5e_params_mqprio_reset(params);
4678 params->log_sq_size = is_kdump_kernel() ?
4679 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4680 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4681 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4684 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev));
4686 /* set CQE compression */
4687 params->rx_cqe_compress_def = false;
4688 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4689 MLX5_CAP_GEN(mdev, vport_group_manager))
4690 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4692 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4693 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4696 mlx5e_build_rq_params(mdev, params);
4699 if (MLX5_CAP_ETH(mdev, lro_cap) &&
4700 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4701 /* No XSK params: checking the availability of striding RQ in general. */
4702 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4703 params->packet_merge.type = slow_pci_heuristic(mdev) ?
4704 MLX5E_PACKET_MERGE_NONE : MLX5E_PACKET_MERGE_LRO;
4706 params->packet_merge.timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4708 /* CQ moderation params */
4709 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4710 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4711 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4712 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4713 params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4714 mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4715 mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4718 mlx5_query_min_inline(mdev, ¶ms->tx_min_inline_mode);
4720 params->tunneled_offload_en = mlx5_tunnel_inner_ft_supported(mdev);
4725 /* Do not update netdev->features directly in here
4726 * on mlx5e_attach_netdev() we will call mlx5e_update_features()
4727 * To update netdev->features please modify mlx5e_fix_features()
4731 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4733 struct mlx5e_priv *priv = netdev_priv(netdev);
4736 mlx5_query_mac_address(priv->mdev, addr);
4737 if (is_zero_ether_addr(addr) &&
4738 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4739 eth_hw_addr_random(netdev);
4740 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4744 eth_hw_addr_set(netdev, addr);
4747 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table,
4748 unsigned int entry, struct udp_tunnel_info *ti)
4750 struct mlx5e_priv *priv = netdev_priv(netdev);
4752 return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port));
4755 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table,
4756 unsigned int entry, struct udp_tunnel_info *ti)
4758 struct mlx5e_priv *priv = netdev_priv(netdev);
4760 return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port));
4763 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv)
4765 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4768 priv->nic_info.set_port = mlx5e_vxlan_set_port;
4769 priv->nic_info.unset_port = mlx5e_vxlan_unset_port;
4770 priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
4771 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN;
4772 priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN;
4773 /* Don't count the space hard-coded to the IANA port */
4774 priv->nic_info.tables[0].n_entries =
4775 mlx5_vxlan_max_udp_ports(priv->mdev) - 1;
4777 priv->netdev->udp_tunnel_nic_info = &priv->nic_info;
4780 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev)
4784 for (tt = 0; tt < MLX5_NUM_TUNNEL_TT; tt++) {
4785 if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5_get_proto_by_tunnel_type(tt)))
4788 return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev));
4791 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4793 struct mlx5e_priv *priv = netdev_priv(netdev);
4794 struct mlx5_core_dev *mdev = priv->mdev;
4798 SET_NETDEV_DEV(netdev, mdev->device);
4800 netdev->netdev_ops = &mlx5e_netdev_ops;
4802 mlx5e_dcbnl_build_netdev(netdev);
4804 netdev->watchdog_timeo = 15 * HZ;
4806 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4808 netdev->vlan_features |= NETIF_F_SG;
4809 netdev->vlan_features |= NETIF_F_HW_CSUM;
4810 netdev->vlan_features |= NETIF_F_GRO;
4811 netdev->vlan_features |= NETIF_F_TSO;
4812 netdev->vlan_features |= NETIF_F_TSO6;
4813 netdev->vlan_features |= NETIF_F_RXCSUM;
4814 netdev->vlan_features |= NETIF_F_RXHASH;
4816 netdev->mpls_features |= NETIF_F_SG;
4817 netdev->mpls_features |= NETIF_F_HW_CSUM;
4818 netdev->mpls_features |= NETIF_F_TSO;
4819 netdev->mpls_features |= NETIF_F_TSO6;
4821 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX;
4822 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX;
4824 /* Tunneled LRO is not supported in the driver, and the same RQs are
4825 * shared between inner and outer TIRs, so the driver can't disable LRO
4826 * for inner TIRs while having it enabled for outer TIRs. Due to this,
4827 * block LRO altogether if the firmware declares tunneled LRO support.
4829 if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4830 !MLX5_CAP_ETH(mdev, tunnel_lro_vxlan) &&
4831 !MLX5_CAP_ETH(mdev, tunnel_lro_gre) &&
4832 mlx5e_check_fragmented_striding_rq_cap(mdev))
4833 netdev->vlan_features |= NETIF_F_LRO;
4835 netdev->hw_features = netdev->vlan_features;
4836 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
4837 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4838 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4839 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
4841 if (!!MLX5_CAP_GEN(mdev, shampo) &&
4842 mlx5e_check_fragmented_striding_rq_cap(mdev))
4843 netdev->hw_features |= NETIF_F_GRO_HW;
4845 if (mlx5e_tunnel_any_tx_proto_supported(mdev)) {
4846 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4847 netdev->hw_enc_features |= NETIF_F_TSO;
4848 netdev->hw_enc_features |= NETIF_F_TSO6;
4849 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4852 if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4853 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4854 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4855 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4856 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4857 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4858 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL |
4859 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4862 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) {
4863 netdev->hw_features |= NETIF_F_GSO_GRE |
4864 NETIF_F_GSO_GRE_CSUM;
4865 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4866 NETIF_F_GSO_GRE_CSUM;
4867 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4868 NETIF_F_GSO_GRE_CSUM;
4871 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) {
4872 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4874 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4876 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4880 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
4881 netdev->gso_partial_features |= NETIF_F_GSO_UDP_L4;
4882 netdev->hw_features |= NETIF_F_GSO_UDP_L4;
4883 netdev->features |= NETIF_F_GSO_UDP_L4;
4885 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4888 netdev->hw_features |= NETIF_F_RXALL;
4890 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4891 netdev->hw_features |= NETIF_F_RXFCS;
4893 if (mlx5_qos_is_supported(mdev))
4894 netdev->hw_features |= NETIF_F_HW_TC;
4896 netdev->features = netdev->hw_features;
4900 netdev->features &= ~NETIF_F_RXALL;
4901 netdev->features &= ~NETIF_F_LRO;
4902 netdev->features &= ~NETIF_F_GRO_HW;
4903 netdev->features &= ~NETIF_F_RXFCS;
4905 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4906 if (FT_CAP(flow_modify_en) &&
4907 FT_CAP(modify_root) &&
4908 FT_CAP(identified_miss_table_mode) &&
4909 FT_CAP(flow_table_modify)) {
4910 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
4911 netdev->hw_features |= NETIF_F_HW_TC;
4913 #ifdef CONFIG_MLX5_EN_ARFS
4914 netdev->hw_features |= NETIF_F_NTUPLE;
4918 netdev->features |= NETIF_F_HIGHDMA;
4919 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
4921 netdev->priv_flags |= IFF_UNICAST_FLT;
4923 mlx5e_set_netdev_dev_addr(netdev);
4924 mlx5e_ipsec_build_netdev(priv);
4925 mlx5e_ktls_build_netdev(priv);
4928 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4930 u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {};
4931 u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {};
4932 struct mlx5_core_dev *mdev = priv->mdev;
4935 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
4936 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4939 MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4941 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out);
4943 priv->drop_rq_q_counter =
4944 MLX5_GET(alloc_q_counter_out, out, counter_set_id);
4947 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4949 u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {};
4951 MLX5_SET(dealloc_q_counter_in, in, opcode,
4952 MLX5_CMD_OP_DEALLOC_Q_COUNTER);
4953 if (priv->q_counter) {
4954 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4956 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4959 if (priv->drop_rq_q_counter) {
4960 MLX5_SET(dealloc_q_counter_in, in, counter_set_id,
4961 priv->drop_rq_q_counter);
4962 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in);
4966 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4967 struct net_device *netdev)
4969 struct mlx5e_priv *priv = netdev_priv(netdev);
4972 mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu);
4973 mlx5e_vxlan_set_netdev_info(priv);
4975 mlx5e_timestamp_init(priv);
4977 err = mlx5e_fs_init(priv);
4979 mlx5_core_err(mdev, "FS initialization failed, %d\n", err);
4983 err = mlx5e_ipsec_init(priv);
4985 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4987 err = mlx5e_ktls_init(priv);
4989 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4991 mlx5e_health_create_reporters(priv);
4995 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4997 mlx5e_health_destroy_reporters(priv);
4998 mlx5e_ktls_cleanup(priv);
4999 mlx5e_ipsec_cleanup(priv);
5000 mlx5e_fs_cleanup(priv);
5003 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
5005 struct mlx5_core_dev *mdev = priv->mdev;
5006 enum mlx5e_rx_res_features features;
5009 priv->rx_res = mlx5e_rx_res_alloc();
5013 mlx5e_create_q_counters(priv);
5015 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
5017 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5018 goto err_destroy_q_counters;
5021 features = MLX5E_RX_RES_FEATURE_XSK | MLX5E_RX_RES_FEATURE_PTP;
5022 if (priv->channels.params.tunneled_offload_en)
5023 features |= MLX5E_RX_RES_FEATURE_INNER_FT;
5024 err = mlx5e_rx_res_init(priv->rx_res, priv->mdev, features,
5025 priv->max_nch, priv->drop_rq.rqn,
5026 &priv->channels.params.packet_merge,
5027 priv->channels.params.num_channels);
5029 goto err_close_drop_rq;
5031 err = mlx5e_create_flow_steering(priv);
5033 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5034 goto err_destroy_rx_res;
5037 err = mlx5e_tc_nic_init(priv);
5039 goto err_destroy_flow_steering;
5041 err = mlx5e_accel_init_rx(priv);
5043 goto err_tc_nic_cleanup;
5045 #ifdef CONFIG_MLX5_EN_ARFS
5046 priv->netdev->rx_cpu_rmap = mlx5_eq_table_get_rmap(priv->mdev);
5052 mlx5e_tc_nic_cleanup(priv);
5053 err_destroy_flow_steering:
5054 mlx5e_destroy_flow_steering(priv);
5056 mlx5e_rx_res_destroy(priv->rx_res);
5058 mlx5e_close_drop_rq(&priv->drop_rq);
5059 err_destroy_q_counters:
5060 mlx5e_destroy_q_counters(priv);
5061 mlx5e_rx_res_free(priv->rx_res);
5062 priv->rx_res = NULL;
5066 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5068 mlx5e_accel_cleanup_rx(priv);
5069 mlx5e_tc_nic_cleanup(priv);
5070 mlx5e_destroy_flow_steering(priv);
5071 mlx5e_rx_res_destroy(priv->rx_res);
5072 mlx5e_close_drop_rq(&priv->drop_rq);
5073 mlx5e_destroy_q_counters(priv);
5074 mlx5e_rx_res_free(priv->rx_res);
5075 priv->rx_res = NULL;
5078 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5082 err = mlx5e_create_tises(priv);
5084 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5088 mlx5e_dcbnl_initialize(priv);
5092 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5094 struct net_device *netdev = priv->netdev;
5095 struct mlx5_core_dev *mdev = priv->mdev;
5097 mlx5e_init_l2_addr(priv);
5099 /* Marking the link as currently not needed by the Driver */
5100 if (!netif_running(netdev))
5101 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN);
5103 mlx5e_set_netdev_mtu_boundaries(priv);
5104 mlx5e_set_dev_port_mtu(priv);
5106 mlx5_lag_add_netdev(mdev, netdev);
5108 mlx5e_enable_async_events(priv);
5109 mlx5e_enable_blocking_events(priv);
5110 if (mlx5e_monitor_counter_supported(priv))
5111 mlx5e_monitor_counter_init(priv);
5113 mlx5e_hv_vhca_stats_create(priv);
5114 if (netdev->reg_state != NETREG_REGISTERED)
5116 mlx5e_dcbnl_init_app(priv);
5118 mlx5e_nic_set_rx_mode(priv);
5121 if (netif_running(netdev))
5123 udp_tunnel_nic_reset_ntf(priv->netdev);
5124 netif_device_attach(netdev);
5128 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5130 struct mlx5_core_dev *mdev = priv->mdev;
5132 if (priv->netdev->reg_state == NETREG_REGISTERED)
5133 mlx5e_dcbnl_delete_app(priv);
5136 if (netif_running(priv->netdev))
5137 mlx5e_close(priv->netdev);
5138 netif_device_detach(priv->netdev);
5141 mlx5e_nic_set_rx_mode(priv);
5143 mlx5e_hv_vhca_stats_destroy(priv);
5144 if (mlx5e_monitor_counter_supported(priv))
5145 mlx5e_monitor_counter_cleanup(priv);
5147 mlx5e_disable_blocking_events(priv);
5148 if (priv->en_trap) {
5149 mlx5e_deactivate_trap(priv);
5150 mlx5e_close_trap(priv->en_trap);
5151 priv->en_trap = NULL;
5153 mlx5e_disable_async_events(priv);
5154 mlx5_lag_remove_netdev(mdev, priv->netdev);
5155 mlx5_vxlan_reset_to_default(mdev->vxlan);
5158 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5160 return mlx5e_refresh_tirs(priv, false, false);
5163 static const struct mlx5e_profile mlx5e_nic_profile = {
5164 .init = mlx5e_nic_init,
5165 .cleanup = mlx5e_nic_cleanup,
5166 .init_rx = mlx5e_init_nic_rx,
5167 .cleanup_rx = mlx5e_cleanup_nic_rx,
5168 .init_tx = mlx5e_init_nic_tx,
5169 .cleanup_tx = mlx5e_cleanup_nic_tx,
5170 .enable = mlx5e_nic_enable,
5171 .disable = mlx5e_nic_disable,
5172 .update_rx = mlx5e_update_nic_rx,
5173 .update_stats = mlx5e_stats_update_ndo_stats,
5174 .update_carrier = mlx5e_update_carrier,
5175 .rx_handlers = &mlx5e_rx_handlers_nic,
5176 .max_tc = MLX5E_MAX_NUM_TC,
5177 .rq_groups = MLX5E_NUM_RQ_GROUPS(XSK),
5178 .stats_grps = mlx5e_nic_stats_grps,
5179 .stats_grps_num = mlx5e_nic_stats_grps_num,
5180 .features = BIT(MLX5E_PROFILE_FEATURE_PTP_RX) |
5181 BIT(MLX5E_PROFILE_FEATURE_PTP_TX) |
5182 BIT(MLX5E_PROFILE_FEATURE_QOS_HTB),
5185 static int mlx5e_profile_max_num_channels(struct mlx5_core_dev *mdev,
5186 const struct mlx5e_profile *profile)
5190 nch = mlx5e_get_max_num_channels(mdev);
5192 if (profile->max_nch_limit)
5193 nch = min_t(int, nch, profile->max_nch_limit(mdev));
5198 mlx5e_calc_max_nch(struct mlx5_core_dev *mdev, struct net_device *netdev,
5199 const struct mlx5e_profile *profile)
5202 unsigned int max_nch, tmp;
5204 /* core resources */
5205 max_nch = mlx5e_profile_max_num_channels(mdev, profile);
5207 /* netdev rx queues */
5208 tmp = netdev->num_rx_queues / max_t(u8, profile->rq_groups, 1);
5209 max_nch = min_t(unsigned int, max_nch, tmp);
5211 /* netdev tx queues */
5212 tmp = netdev->num_tx_queues;
5213 if (mlx5_qos_is_supported(mdev))
5214 tmp -= mlx5e_qos_max_leaf_nodes(mdev);
5215 if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn))
5216 tmp -= profile->max_tc;
5217 tmp = tmp / profile->max_tc;
5218 max_nch = min_t(unsigned int, max_nch, tmp);
5223 /* mlx5e generic netdev management API (move to en_common.c) */
5224 int mlx5e_priv_init(struct mlx5e_priv *priv,
5225 const struct mlx5e_profile *profile,
5226 struct net_device *netdev,
5227 struct mlx5_core_dev *mdev)
5229 int nch, num_txqs, node;
5232 num_txqs = netdev->num_tx_queues;
5233 nch = mlx5e_calc_max_nch(mdev, netdev, profile);
5234 node = dev_to_node(mlx5_core_dma_dev(mdev));
5238 priv->netdev = netdev;
5239 priv->msglevel = MLX5E_MSG_LEVEL;
5240 priv->max_nch = nch;
5241 priv->max_opened_tc = 1;
5243 if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL))
5246 mutex_init(&priv->state_lock);
5248 err = mlx5e_selq_init(&priv->selq, &priv->state_lock);
5250 goto err_free_cpumask;
5252 hash_init(priv->htb.qos_tc2node);
5253 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5254 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5255 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5256 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5258 priv->wq = create_singlethread_workqueue("mlx5e");
5262 priv->txq2sq = kcalloc_node(num_txqs, sizeof(*priv->txq2sq), GFP_KERNEL, node);
5264 goto err_destroy_workqueue;
5266 priv->tx_rates = kcalloc_node(num_txqs, sizeof(*priv->tx_rates), GFP_KERNEL, node);
5267 if (!priv->tx_rates)
5268 goto err_free_txq2sq;
5270 priv->channel_stats =
5271 kcalloc_node(nch, sizeof(*priv->channel_stats), GFP_KERNEL, node);
5272 if (!priv->channel_stats)
5273 goto err_free_tx_rates;
5278 kfree(priv->tx_rates);
5280 kfree(priv->txq2sq);
5281 err_destroy_workqueue:
5282 destroy_workqueue(priv->wq);
5284 mlx5e_selq_cleanup(&priv->selq);
5286 free_cpumask_var(priv->scratchpad.cpumask);
5290 void mlx5e_priv_cleanup(struct mlx5e_priv *priv)
5294 /* bail if change profile failed and also rollback failed */
5298 for (i = 0; i < priv->stats_nch; i++)
5299 kvfree(priv->channel_stats[i]);
5300 kfree(priv->channel_stats);
5301 kfree(priv->tx_rates);
5302 kfree(priv->txq2sq);
5303 destroy_workqueue(priv->wq);
5304 mutex_lock(&priv->state_lock);
5305 mlx5e_selq_cleanup(&priv->selq);
5306 mutex_unlock(&priv->state_lock);
5307 free_cpumask_var(priv->scratchpad.cpumask);
5309 for (i = 0; i < priv->htb.max_qos_sqs; i++)
5310 kfree(priv->htb.qos_sq_stats[i]);
5311 kvfree(priv->htb.qos_sq_stats);
5313 if (priv->mqprio_rl) {
5314 mlx5e_mqprio_rl_cleanup(priv->mqprio_rl);
5315 mlx5e_mqprio_rl_free(priv->mqprio_rl);
5318 memset(priv, 0, sizeof(*priv));
5321 static unsigned int mlx5e_get_max_num_txqs(struct mlx5_core_dev *mdev,
5322 const struct mlx5e_profile *profile)
5324 unsigned int nch, ptp_txqs, qos_txqs;
5326 nch = mlx5e_profile_max_num_channels(mdev, profile);
5328 ptp_txqs = MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn) &&
5329 mlx5e_profile_feature_cap(profile, PTP_TX) ?
5330 profile->max_tc : 0;
5332 qos_txqs = mlx5_qos_is_supported(mdev) &&
5333 mlx5e_profile_feature_cap(profile, QOS_HTB) ?
5334 mlx5e_qos_max_leaf_nodes(mdev) : 0;
5336 return nch * profile->max_tc + ptp_txqs + qos_txqs;
5339 static unsigned int mlx5e_get_max_num_rxqs(struct mlx5_core_dev *mdev,
5340 const struct mlx5e_profile *profile)
5344 nch = mlx5e_profile_max_num_channels(mdev, profile);
5346 return nch * profile->rq_groups;
5350 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile)
5352 struct net_device *netdev;
5353 unsigned int txqs, rxqs;
5356 txqs = mlx5e_get_max_num_txqs(mdev, profile);
5357 rxqs = mlx5e_get_max_num_rxqs(mdev, profile);
5359 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs);
5361 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5365 err = mlx5e_priv_init(netdev_priv(netdev), profile, netdev, mdev);
5367 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5368 goto err_free_netdev;
5371 netif_carrier_off(netdev);
5372 netif_tx_disable(netdev);
5373 dev_net_set(netdev, mlx5_core_net(mdev));
5378 free_netdev(netdev);
5383 static void mlx5e_update_features(struct net_device *netdev)
5385 if (netdev->reg_state != NETREG_REGISTERED)
5386 return; /* features will be updated on netdev registration */
5389 netdev_update_features(netdev);
5393 static void mlx5e_reset_channels(struct net_device *netdev)
5395 netdev_reset_tc(netdev);
5398 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5400 const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED;
5401 const struct mlx5e_profile *profile = priv->profile;
5405 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5407 /* max number of channels may have changed */
5408 max_nch = mlx5e_calc_max_nch(priv->mdev, priv->netdev, profile);
5409 if (priv->channels.params.num_channels > max_nch) {
5410 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5411 /* Reducing the number of channels - RXFH has to be reset, and
5412 * mlx5e_num_channels_changed below will build the RQT.
5414 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED;
5415 priv->channels.params.num_channels = max_nch;
5416 if (priv->channels.params.mqprio.mode == TC_MQPRIO_MODE_CHANNEL) {
5417 mlx5_core_warn(priv->mdev, "MLX5E: Disabling MQPRIO channel mode\n");
5418 mlx5e_params_mqprio_reset(&priv->channels.params);
5421 if (max_nch != priv->max_nch) {
5422 mlx5_core_warn(priv->mdev,
5423 "MLX5E: Updating max number of channels from %u to %u\n",
5424 priv->max_nch, max_nch);
5425 priv->max_nch = max_nch;
5428 /* 1. Set the real number of queues in the kernel the first time.
5429 * 2. Set our default XPS cpumask.
5432 * rtnl_lock is required by netif_set_real_num_*_queues in case the
5433 * netdev has been registered by this point (if this function was called
5434 * in the reload or resume flow).
5438 err = mlx5e_num_channels_changed(priv);
5444 err = profile->init_tx(priv);
5448 err = profile->init_rx(priv);
5450 goto err_cleanup_tx;
5452 if (profile->enable)
5453 profile->enable(priv);
5455 mlx5e_update_features(priv->netdev);
5460 profile->cleanup_tx(priv);
5463 mlx5e_reset_channels(priv->netdev);
5464 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5465 cancel_work_sync(&priv->update_stats_work);
5469 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5471 const struct mlx5e_profile *profile = priv->profile;
5473 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5475 if (profile->disable)
5476 profile->disable(priv);
5477 flush_workqueue(priv->wq);
5479 profile->cleanup_rx(priv);
5480 profile->cleanup_tx(priv);
5481 mlx5e_reset_channels(priv->netdev);
5482 cancel_work_sync(&priv->update_stats_work);
5486 mlx5e_netdev_attach_profile(struct net_device *netdev, struct mlx5_core_dev *mdev,
5487 const struct mlx5e_profile *new_profile, void *new_ppriv)
5489 struct mlx5e_priv *priv = netdev_priv(netdev);
5492 err = mlx5e_priv_init(priv, new_profile, netdev, mdev);
5494 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err);
5497 netif_carrier_off(netdev);
5498 priv->profile = new_profile;
5499 priv->ppriv = new_ppriv;
5500 err = new_profile->init(priv->mdev, priv->netdev);
5503 err = mlx5e_attach_netdev(priv);
5505 goto profile_cleanup;
5509 new_profile->cleanup(priv);
5511 mlx5e_priv_cleanup(priv);
5515 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
5516 const struct mlx5e_profile *new_profile, void *new_ppriv)
5518 const struct mlx5e_profile *orig_profile = priv->profile;
5519 struct net_device *netdev = priv->netdev;
5520 struct mlx5_core_dev *mdev = priv->mdev;
5521 void *orig_ppriv = priv->ppriv;
5522 int err, rollback_err;
5524 /* cleanup old profile */
5525 mlx5e_detach_netdev(priv);
5526 priv->profile->cleanup(priv);
5527 mlx5e_priv_cleanup(priv);
5529 err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile, new_ppriv);
5530 if (err) { /* roll back to original profile */
5531 netdev_warn(netdev, "%s: new profile init failed, %d\n", __func__, err);
5538 rollback_err = mlx5e_netdev_attach_profile(netdev, mdev, orig_profile, orig_ppriv);
5540 netdev_err(netdev, "%s: failed to rollback to orig profile, %d\n",
5541 __func__, rollback_err);
5545 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv)
5547 mlx5e_netdev_change_profile(priv, &mlx5e_nic_profile, NULL);
5550 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5552 struct net_device *netdev = priv->netdev;
5554 mlx5e_priv_cleanup(priv);
5555 free_netdev(netdev);
5558 static int mlx5e_resume(struct auxiliary_device *adev)
5560 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5561 struct mlx5e_priv *priv = auxiliary_get_drvdata(adev);
5562 struct net_device *netdev = priv->netdev;
5563 struct mlx5_core_dev *mdev = edev->mdev;
5566 if (netif_device_present(netdev))
5569 err = mlx5e_create_mdev_resources(mdev);
5573 err = mlx5e_attach_netdev(priv);
5575 mlx5e_destroy_mdev_resources(mdev);
5582 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state)
5584 struct mlx5e_priv *priv = auxiliary_get_drvdata(adev);
5585 struct net_device *netdev = priv->netdev;
5586 struct mlx5_core_dev *mdev = priv->mdev;
5588 if (!netif_device_present(netdev))
5591 mlx5e_detach_netdev(priv);
5592 mlx5e_destroy_mdev_resources(mdev);
5596 static int mlx5e_probe(struct auxiliary_device *adev,
5597 const struct auxiliary_device_id *id)
5599 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev);
5600 const struct mlx5e_profile *profile = &mlx5e_nic_profile;
5601 struct mlx5_core_dev *mdev = edev->mdev;
5602 struct net_device *netdev;
5603 pm_message_t state = {};
5604 struct mlx5e_priv *priv;
5607 netdev = mlx5e_create_netdev(mdev, profile);
5609 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5613 mlx5e_build_nic_netdev(netdev);
5615 priv = netdev_priv(netdev);
5616 auxiliary_set_drvdata(adev, priv);
5618 priv->profile = profile;
5621 err = mlx5e_devlink_port_register(priv);
5623 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err);
5624 goto err_destroy_netdev;
5627 err = profile->init(mdev, netdev);
5629 mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err);
5630 goto err_devlink_cleanup;
5633 err = mlx5e_resume(adev);
5635 mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err);
5636 goto err_profile_cleanup;
5639 err = register_netdev(netdev);
5641 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5645 mlx5e_devlink_port_type_eth_set(priv);
5647 mlx5e_dcbnl_init_app(priv);
5648 mlx5_uplink_netdev_set(mdev, netdev);
5652 mlx5e_suspend(adev, state);
5653 err_profile_cleanup:
5654 profile->cleanup(priv);
5655 err_devlink_cleanup:
5656 mlx5e_devlink_port_unregister(priv);
5658 mlx5e_destroy_netdev(priv);
5662 static void mlx5e_remove(struct auxiliary_device *adev)
5664 struct mlx5e_priv *priv = auxiliary_get_drvdata(adev);
5665 pm_message_t state = {};
5667 mlx5e_dcbnl_delete_app(priv);
5668 unregister_netdev(priv->netdev);
5669 mlx5e_suspend(adev, state);
5670 priv->profile->cleanup(priv);
5671 mlx5e_devlink_port_unregister(priv);
5672 mlx5e_destroy_netdev(priv);
5675 static const struct auxiliary_device_id mlx5e_id_table[] = {
5676 { .name = MLX5_ADEV_NAME ".eth", },
5680 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table);
5682 static struct auxiliary_driver mlx5e_driver = {
5684 .probe = mlx5e_probe,
5685 .remove = mlx5e_remove,
5686 .suspend = mlx5e_suspend,
5687 .resume = mlx5e_resume,
5688 .id_table = mlx5e_id_table,
5691 int mlx5e_init(void)
5695 mlx5e_build_ptys2ethtool_map();
5696 ret = auxiliary_driver_register(&mlx5e_driver);
5700 ret = mlx5e_rep_init();
5702 auxiliary_driver_unregister(&mlx5e_driver);
5706 void mlx5e_cleanup(void)
5708 mlx5e_rep_cleanup();
5709 auxiliary_driver_unregister(&mlx5e_driver);