1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell OcteonTx2 CGX driver
4 * Copyright (C) 2018 Marvell International Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
15 #include "cgx_fw_if.h"
19 #define PCI_DEVID_OCTEONTX2_CGX 0xA059
22 #define PCI_CFG_REG_BAR_NUM 0
24 #define CGX_ID_MASK 0x7
25 #define MAX_LMAC_PER_CGX 4
26 #define MAX_DMAC_ENTRIES_PER_CGX 32
27 #define CGX_FIFO_LEN 65536 /* 64K for both Rx & Tx */
28 #define CGX_OFFSET(x) ((x) * MAX_LMAC_PER_CGX)
31 #define CGXX_CMRX_CFG 0x00
32 #define CMR_P2X_SEL_MASK GENMASK_ULL(61, 59)
33 #define CMR_P2X_SEL_SHIFT 59ULL
34 #define CMR_P2X_SEL_NIX0 1ULL
35 #define CMR_P2X_SEL_NIX1 2ULL
36 #define CMR_EN BIT_ULL(55)
37 #define DATA_PKT_TX_EN BIT_ULL(53)
38 #define DATA_PKT_RX_EN BIT_ULL(54)
39 #define CGX_LMAC_TYPE_SHIFT 40
40 #define CGX_LMAC_TYPE_MASK 0xF
41 #define CGXX_CMRX_INT 0x040
42 #define FW_CGX_INT BIT_ULL(1)
43 #define CGXX_CMRX_INT_ENA_W1S 0x058
44 #define CGXX_CMRX_RX_ID_MAP 0x060
45 #define CGXX_CMRX_RX_STAT0 0x070
46 #define CGXX_CMRX_RX_LMACS 0x128
47 #define CGXX_CMRX_RX_DMAC_CTL0 (0x1F8 + mac_ops->csr_offset)
48 #define CGX_DMAC_CTL0_CAM_ENABLE BIT_ULL(3)
49 #define CGX_DMAC_CAM_ACCEPT BIT_ULL(3)
50 #define CGX_DMAC_MCAST_MODE_CAM BIT_ULL(2)
51 #define CGX_DMAC_MCAST_MODE BIT_ULL(1)
52 #define CGX_DMAC_BCAST_MODE BIT_ULL(0)
53 #define CGXX_CMRX_RX_DMAC_CAM0 (0x200 + mac_ops->csr_offset)
54 #define CGX_DMAC_CAM_ADDR_ENABLE BIT_ULL(48)
55 #define CGX_DMAC_CAM_ENTRY_LMACID GENMASK_ULL(50, 49)
56 #define CGXX_CMRX_RX_DMAC_CAM1 0x400
57 #define CGX_RX_DMAC_ADR_MASK GENMASK_ULL(47, 0)
58 #define CGXX_CMRX_TX_STAT0 0x700
59 #define CGXX_SCRATCH0_REG 0x1050
60 #define CGXX_SCRATCH1_REG 0x1058
61 #define CGX_CONST 0x2000
62 #define CGX_CONST_RXFIFO_SIZE GENMASK_ULL(23, 0)
63 #define CGXX_SPUX_CONTROL1 0x10000
64 #define CGXX_SPUX_LNX_FEC_CORR_BLOCKS 0x10700
65 #define CGXX_SPUX_LNX_FEC_UNCORR_BLOCKS 0x10800
66 #define CGXX_SPUX_RSFEC_CORR 0x10088
67 #define CGXX_SPUX_RSFEC_UNCORR 0x10090
69 #define CGXX_SPUX_CONTROL1_LBK BIT_ULL(14)
70 #define CGXX_GMP_PCS_MRX_CTL 0x30000
71 #define CGXX_GMP_PCS_MRX_CTL_LBK BIT_ULL(14)
73 #define CGXX_SMUX_RX_FRM_CTL 0x20020
74 #define CGX_SMUX_RX_FRM_CTL_CTL_BCK BIT_ULL(3)
75 #define CGX_SMUX_RX_FRM_CTL_PTP_MODE BIT_ULL(12)
76 #define CGXX_GMP_GMI_RXX_FRM_CTL 0x38028
77 #define CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK BIT_ULL(3)
78 #define CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE BIT_ULL(12)
79 #define CGXX_SMUX_TX_CTL 0x20178
80 #define CGXX_SMUX_TX_PAUSE_PKT_TIME 0x20110
81 #define CGXX_SMUX_TX_PAUSE_PKT_INTERVAL 0x20120
82 #define CGXX_GMP_GMI_TX_PAUSE_PKT_TIME 0x38230
83 #define CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL 0x38248
84 #define CGX_SMUX_TX_CTL_L2P_BP_CONV BIT_ULL(7)
85 #define CGXX_CMR_RX_OVR_BP 0x130
86 #define CGX_CMR_RX_OVR_BP_EN(X) BIT_ULL(((X) + 8))
87 #define CGX_CMR_RX_OVR_BP_BP(X) BIT_ULL(((X) + 4))
89 #define CGX_COMMAND_REG CGXX_SCRATCH1_REG
90 #define CGX_EVENT_REG CGXX_SCRATCH0_REG
91 #define CGX_CMD_TIMEOUT 2200 /* msecs */
92 #define DEFAULT_PAUSE_TIME 0x7FF
94 #define CGX_LMAC_FWI 0
96 enum cgx_nix_stat_type {
107 LMAC_MODE_QSGMII = 6,
110 LMAC_MODE_100G_R = 9,
111 LMAC_MODE_USXGMII = 10,
115 struct cgx_link_event {
116 struct cgx_link_user_info link_uinfo;
122 * struct cgx_event_cb
123 * @notify_link_chg: callback for link change notification
124 * @data: data passed to callback function
126 struct cgx_event_cb {
127 int (*notify_link_chg)(struct cgx_link_event *event, void *data);
131 extern struct pci_driver cgx_driver;
133 int cgx_get_cgxcnt_max(void);
134 int cgx_get_cgxid(void *cgxd);
135 int cgx_get_lmac_cnt(void *cgxd);
136 void *cgx_get_pdata(int cgx_id);
137 int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind);
138 int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id);
139 int cgx_lmac_evh_unregister(void *cgxd, int lmac_id);
140 int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat);
141 int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat);
142 int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable);
143 int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable);
144 int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr);
145 int cgx_lmac_addr_reset(u8 cgx_id, u8 lmac_id);
146 u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id);
147 int cgx_lmac_addr_add(u8 cgx_id, u8 lmac_id, u8 *mac_addr);
148 int cgx_lmac_addr_del(u8 cgx_id, u8 lmac_id, u8 index);
149 int cgx_lmac_addr_max_entries_get(u8 cgx_id, u8 lmac_id);
150 void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable);
151 void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable);
152 int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable);
153 int cgx_get_link_info(void *cgxd, int lmac_id,
154 struct cgx_link_user_info *linfo);
155 int cgx_lmac_linkup_start(void *cgxd);
156 int cgx_get_fwdata_base(u64 *base);
157 int cgx_lmac_get_pause_frm(void *cgxd, int lmac_id,
158 u8 *tx_pause, u8 *rx_pause);
159 int cgx_lmac_set_pause_frm(void *cgxd, int lmac_id,
160 u8 tx_pause, u8 rx_pause);
161 void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable);
162 u8 cgx_lmac_get_p2x(int cgx_id, int lmac_id);
163 int cgx_set_fec(u64 fec, int cgx_id, int lmac_id);
164 int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp);
165 int cgx_get_phy_fec_stats(void *cgxd, int lmac_id);
166 int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args,
167 int cgx_id, int lmac_id);
168 u64 cgx_features_get(void *cgxd);
169 struct mac_ops *get_mac_ops(void *cgxd);
170 int cgx_get_nr_lmacs(void *cgxd);
171 u8 cgx_get_lmacid(void *cgxd, u8 lmac_index);
172 unsigned long cgx_get_lmac_bmap(void *cgxd);
173 void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val);
174 u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset);
175 int cgx_lmac_addr_update(u8 cgx_id, u8 lmac_id, u8 *mac_addr, u8 index);
176 u64 cgx_read_dmac_ctrl(void *cgxd, int lmac_id);
177 u64 cgx_read_dmac_entry(void *cgxd, int index);