1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018 Intel Corporation */
4 #include <linux/module.h>
5 #include <linux/types.h>
6 #include <linux/if_vlan.h>
11 #include <linux/pm_runtime.h>
12 #include <net/pkt_sched.h>
13 #include <linux/bpf_trace.h>
22 #define DRV_SUMMARY "Intel(R) 2.5G Ethernet Linux Driver"
24 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
26 #define IGC_XDP_PASS 0
27 #define IGC_XDP_CONSUMED BIT(0)
28 #define IGC_XDP_TX BIT(1)
29 #define IGC_XDP_REDIRECT BIT(2)
31 static int debug = -1;
33 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
34 MODULE_DESCRIPTION(DRV_SUMMARY);
35 MODULE_LICENSE("GPL v2");
36 module_param(debug, int, 0);
37 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
39 char igc_driver_name[] = "igc";
40 static const char igc_driver_string[] = DRV_SUMMARY;
41 static const char igc_copyright[] =
42 "Copyright(c) 2018 Intel Corporation.";
44 static const struct igc_info *igc_info_tbl[] = {
45 [board_base] = &igc_base_info,
48 static const struct pci_device_id igc_pci_tbl[] = {
49 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_LM), board_base },
50 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_V), board_base },
51 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_I), board_base },
52 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I220_V), board_base },
53 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_K), board_base },
54 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_K2), board_base },
55 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_K), board_base },
56 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_LMVP), board_base },
57 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_IT), board_base },
58 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_LM), board_base },
59 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_V), board_base },
60 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_IT), board_base },
61 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I221_V), board_base },
62 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_BLANK_NVM), board_base },
63 { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_BLANK_NVM), board_base },
64 /* required last entry */
68 MODULE_DEVICE_TABLE(pci, igc_pci_tbl);
77 void igc_reset(struct igc_adapter *adapter)
79 struct net_device *dev = adapter->netdev;
80 struct igc_hw *hw = &adapter->hw;
81 struct igc_fc_info *fc = &hw->fc;
84 /* Repartition PBA for greater than 9k MTU if required */
87 /* flow control settings
88 * The high water mark must be low enough to fit one full frame
89 * after transmitting the pause frame. As such we must have enough
90 * space to allow for us to complete our current transmit and then
91 * receive the frame that is in progress from the link partner.
93 * - the full Rx FIFO size minus one full Tx plus one full Rx frame
95 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
97 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
98 fc->low_water = fc->high_water - 16;
99 fc->pause_time = 0xFFFF;
101 fc->current_mode = fc->requested_mode;
103 hw->mac.ops.reset_hw(hw);
105 if (hw->mac.ops.init_hw(hw))
106 netdev_err(dev, "Error on hardware initialization\n");
108 /* Re-establish EEE setting */
109 igc_set_eee_i225(hw, true, true, true);
111 if (!netif_running(adapter->netdev))
112 igc_power_down_phy_copper_base(&adapter->hw);
114 /* Re-enable PTP, where applicable. */
115 igc_ptp_reset(adapter);
117 /* Re-enable TSN offloading, where applicable. */
118 igc_tsn_offload_apply(adapter);
120 igc_get_phy_info(hw);
124 * igc_power_up_link - Power up the phy link
125 * @adapter: address of board private structure
127 static void igc_power_up_link(struct igc_adapter *adapter)
129 igc_reset_phy(&adapter->hw);
131 igc_power_up_phy_copper(&adapter->hw);
133 igc_setup_link(&adapter->hw);
137 * igc_release_hw_control - release control of the h/w to f/w
138 * @adapter: address of board private structure
140 * igc_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
141 * For ASF and Pass Through versions of f/w this means that the
142 * driver is no longer loaded.
144 static void igc_release_hw_control(struct igc_adapter *adapter)
146 struct igc_hw *hw = &adapter->hw;
149 /* Let firmware take over control of h/w */
150 ctrl_ext = rd32(IGC_CTRL_EXT);
152 ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD);
156 * igc_get_hw_control - get control of the h/w from f/w
157 * @adapter: address of board private structure
159 * igc_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
160 * For ASF and Pass Through versions of f/w this means that
161 * the driver is loaded.
163 static void igc_get_hw_control(struct igc_adapter *adapter)
165 struct igc_hw *hw = &adapter->hw;
168 /* Let firmware know the driver has taken over */
169 ctrl_ext = rd32(IGC_CTRL_EXT);
171 ctrl_ext | IGC_CTRL_EXT_DRV_LOAD);
175 * igc_clean_tx_ring - Free Tx Buffers
176 * @tx_ring: ring to be cleaned
178 static void igc_clean_tx_ring(struct igc_ring *tx_ring)
180 u16 i = tx_ring->next_to_clean;
181 struct igc_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
183 while (i != tx_ring->next_to_use) {
184 union igc_adv_tx_desc *eop_desc, *tx_desc;
186 if (tx_buffer->tx_flags & IGC_TX_FLAGS_XDP)
187 xdp_return_frame(tx_buffer->xdpf);
189 dev_kfree_skb_any(tx_buffer->skb);
191 /* unmap skb header data */
192 dma_unmap_single(tx_ring->dev,
193 dma_unmap_addr(tx_buffer, dma),
194 dma_unmap_len(tx_buffer, len),
197 /* check for eop_desc to determine the end of the packet */
198 eop_desc = tx_buffer->next_to_watch;
199 tx_desc = IGC_TX_DESC(tx_ring, i);
201 /* unmap remaining buffers */
202 while (tx_desc != eop_desc) {
206 if (unlikely(i == tx_ring->count)) {
208 tx_buffer = tx_ring->tx_buffer_info;
209 tx_desc = IGC_TX_DESC(tx_ring, 0);
212 /* unmap any remaining paged data */
213 if (dma_unmap_len(tx_buffer, len))
214 dma_unmap_page(tx_ring->dev,
215 dma_unmap_addr(tx_buffer, dma),
216 dma_unmap_len(tx_buffer, len),
220 /* move us one more past the eop_desc for start of next pkt */
223 if (unlikely(i == tx_ring->count)) {
225 tx_buffer = tx_ring->tx_buffer_info;
229 /* reset BQL for queue */
230 netdev_tx_reset_queue(txring_txq(tx_ring));
232 /* reset next_to_use and next_to_clean */
233 tx_ring->next_to_use = 0;
234 tx_ring->next_to_clean = 0;
238 * igc_free_tx_resources - Free Tx Resources per Queue
239 * @tx_ring: Tx descriptor ring for a specific queue
241 * Free all transmit software resources
243 void igc_free_tx_resources(struct igc_ring *tx_ring)
245 igc_clean_tx_ring(tx_ring);
247 vfree(tx_ring->tx_buffer_info);
248 tx_ring->tx_buffer_info = NULL;
250 /* if not set, then don't free */
254 dma_free_coherent(tx_ring->dev, tx_ring->size,
255 tx_ring->desc, tx_ring->dma);
257 tx_ring->desc = NULL;
261 * igc_free_all_tx_resources - Free Tx Resources for All Queues
262 * @adapter: board private structure
264 * Free all transmit software resources
266 static void igc_free_all_tx_resources(struct igc_adapter *adapter)
270 for (i = 0; i < adapter->num_tx_queues; i++)
271 igc_free_tx_resources(adapter->tx_ring[i]);
275 * igc_clean_all_tx_rings - Free Tx Buffers for all queues
276 * @adapter: board private structure
278 static void igc_clean_all_tx_rings(struct igc_adapter *adapter)
282 for (i = 0; i < adapter->num_tx_queues; i++)
283 if (adapter->tx_ring[i])
284 igc_clean_tx_ring(adapter->tx_ring[i]);
288 * igc_setup_tx_resources - allocate Tx resources (Descriptors)
289 * @tx_ring: tx descriptor ring (for a specific queue) to setup
291 * Return 0 on success, negative on failure
293 int igc_setup_tx_resources(struct igc_ring *tx_ring)
295 struct net_device *ndev = tx_ring->netdev;
296 struct device *dev = tx_ring->dev;
299 size = sizeof(struct igc_tx_buffer) * tx_ring->count;
300 tx_ring->tx_buffer_info = vzalloc(size);
301 if (!tx_ring->tx_buffer_info)
304 /* round up to nearest 4K */
305 tx_ring->size = tx_ring->count * sizeof(union igc_adv_tx_desc);
306 tx_ring->size = ALIGN(tx_ring->size, 4096);
308 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
309 &tx_ring->dma, GFP_KERNEL);
314 tx_ring->next_to_use = 0;
315 tx_ring->next_to_clean = 0;
320 vfree(tx_ring->tx_buffer_info);
321 netdev_err(ndev, "Unable to allocate memory for Tx descriptor ring\n");
326 * igc_setup_all_tx_resources - wrapper to allocate Tx resources for all queues
327 * @adapter: board private structure
329 * Return 0 on success, negative on failure
331 static int igc_setup_all_tx_resources(struct igc_adapter *adapter)
333 struct net_device *dev = adapter->netdev;
336 for (i = 0; i < adapter->num_tx_queues; i++) {
337 err = igc_setup_tx_resources(adapter->tx_ring[i]);
339 netdev_err(dev, "Error on Tx queue %u setup\n", i);
340 for (i--; i >= 0; i--)
341 igc_free_tx_resources(adapter->tx_ring[i]);
350 * igc_clean_rx_ring - Free Rx Buffers per Queue
351 * @rx_ring: ring to free buffers from
353 static void igc_clean_rx_ring(struct igc_ring *rx_ring)
355 u16 i = rx_ring->next_to_clean;
357 dev_kfree_skb(rx_ring->skb);
360 /* Free all the Rx ring sk_buffs */
361 while (i != rx_ring->next_to_alloc) {
362 struct igc_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
364 /* Invalidate cache lines that may have been written to by
365 * device so that we avoid corrupting memory.
367 dma_sync_single_range_for_cpu(rx_ring->dev,
369 buffer_info->page_offset,
370 igc_rx_bufsz(rx_ring),
373 /* free resources associated with mapping */
374 dma_unmap_page_attrs(rx_ring->dev,
376 igc_rx_pg_size(rx_ring),
379 __page_frag_cache_drain(buffer_info->page,
380 buffer_info->pagecnt_bias);
383 if (i == rx_ring->count)
387 clear_ring_uses_large_buffer(rx_ring);
389 rx_ring->next_to_alloc = 0;
390 rx_ring->next_to_clean = 0;
391 rx_ring->next_to_use = 0;
395 * igc_clean_all_rx_rings - Free Rx Buffers for all queues
396 * @adapter: board private structure
398 static void igc_clean_all_rx_rings(struct igc_adapter *adapter)
402 for (i = 0; i < adapter->num_rx_queues; i++)
403 if (adapter->rx_ring[i])
404 igc_clean_rx_ring(adapter->rx_ring[i]);
408 * igc_free_rx_resources - Free Rx Resources
409 * @rx_ring: ring to clean the resources from
411 * Free all receive software resources
413 void igc_free_rx_resources(struct igc_ring *rx_ring)
415 igc_clean_rx_ring(rx_ring);
417 igc_xdp_unregister_rxq_info(rx_ring);
419 vfree(rx_ring->rx_buffer_info);
420 rx_ring->rx_buffer_info = NULL;
422 /* if not set, then don't free */
426 dma_free_coherent(rx_ring->dev, rx_ring->size,
427 rx_ring->desc, rx_ring->dma);
429 rx_ring->desc = NULL;
433 * igc_free_all_rx_resources - Free Rx Resources for All Queues
434 * @adapter: board private structure
436 * Free all receive software resources
438 static void igc_free_all_rx_resources(struct igc_adapter *adapter)
442 for (i = 0; i < adapter->num_rx_queues; i++)
443 igc_free_rx_resources(adapter->rx_ring[i]);
447 * igc_setup_rx_resources - allocate Rx resources (Descriptors)
448 * @rx_ring: rx descriptor ring (for a specific queue) to setup
450 * Returns 0 on success, negative on failure
452 int igc_setup_rx_resources(struct igc_ring *rx_ring)
454 struct net_device *ndev = rx_ring->netdev;
455 struct device *dev = rx_ring->dev;
456 int size, desc_len, res;
458 res = igc_xdp_register_rxq_info(rx_ring);
462 size = sizeof(struct igc_rx_buffer) * rx_ring->count;
463 rx_ring->rx_buffer_info = vzalloc(size);
464 if (!rx_ring->rx_buffer_info)
467 desc_len = sizeof(union igc_adv_rx_desc);
469 /* Round up to nearest 4K */
470 rx_ring->size = rx_ring->count * desc_len;
471 rx_ring->size = ALIGN(rx_ring->size, 4096);
473 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
474 &rx_ring->dma, GFP_KERNEL);
479 rx_ring->next_to_alloc = 0;
480 rx_ring->next_to_clean = 0;
481 rx_ring->next_to_use = 0;
486 igc_xdp_unregister_rxq_info(rx_ring);
487 vfree(rx_ring->rx_buffer_info);
488 rx_ring->rx_buffer_info = NULL;
489 netdev_err(ndev, "Unable to allocate memory for Rx descriptor ring\n");
494 * igc_setup_all_rx_resources - wrapper to allocate Rx resources
495 * (Descriptors) for all queues
496 * @adapter: board private structure
498 * Return 0 on success, negative on failure
500 static int igc_setup_all_rx_resources(struct igc_adapter *adapter)
502 struct net_device *dev = adapter->netdev;
505 for (i = 0; i < adapter->num_rx_queues; i++) {
506 err = igc_setup_rx_resources(adapter->rx_ring[i]);
508 netdev_err(dev, "Error on Rx queue %u setup\n", i);
509 for (i--; i >= 0; i--)
510 igc_free_rx_resources(adapter->rx_ring[i]);
518 static bool igc_xdp_is_enabled(struct igc_adapter *adapter)
520 return !!adapter->xdp_prog;
524 * igc_configure_rx_ring - Configure a receive ring after Reset
525 * @adapter: board private structure
526 * @ring: receive ring to be configured
528 * Configure the Rx unit of the MAC after a reset.
530 static void igc_configure_rx_ring(struct igc_adapter *adapter,
531 struct igc_ring *ring)
533 struct igc_hw *hw = &adapter->hw;
534 union igc_adv_rx_desc *rx_desc;
535 int reg_idx = ring->reg_idx;
536 u32 srrctl = 0, rxdctl = 0;
537 u64 rdba = ring->dma;
539 if (igc_xdp_is_enabled(adapter))
540 set_ring_uses_large_buffer(ring);
542 /* disable the queue */
543 wr32(IGC_RXDCTL(reg_idx), 0);
545 /* Set DMA base address registers */
546 wr32(IGC_RDBAL(reg_idx),
547 rdba & 0x00000000ffffffffULL);
548 wr32(IGC_RDBAH(reg_idx), rdba >> 32);
549 wr32(IGC_RDLEN(reg_idx),
550 ring->count * sizeof(union igc_adv_rx_desc));
552 /* initialize head and tail */
553 ring->tail = adapter->io_addr + IGC_RDT(reg_idx);
554 wr32(IGC_RDH(reg_idx), 0);
555 writel(0, ring->tail);
557 /* reset next-to- use/clean to place SW in sync with hardware */
558 ring->next_to_clean = 0;
559 ring->next_to_use = 0;
561 /* set descriptor configuration */
562 srrctl = IGC_RX_HDR_LEN << IGC_SRRCTL_BSIZEHDRSIZE_SHIFT;
563 if (ring_uses_large_buffer(ring))
564 srrctl |= IGC_RXBUFFER_3072 >> IGC_SRRCTL_BSIZEPKT_SHIFT;
566 srrctl |= IGC_RXBUFFER_2048 >> IGC_SRRCTL_BSIZEPKT_SHIFT;
567 srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF;
569 wr32(IGC_SRRCTL(reg_idx), srrctl);
571 rxdctl |= IGC_RX_PTHRESH;
572 rxdctl |= IGC_RX_HTHRESH << 8;
573 rxdctl |= IGC_RX_WTHRESH << 16;
575 /* initialize rx_buffer_info */
576 memset(ring->rx_buffer_info, 0,
577 sizeof(struct igc_rx_buffer) * ring->count);
579 /* initialize Rx descriptor 0 */
580 rx_desc = IGC_RX_DESC(ring, 0);
581 rx_desc->wb.upper.length = 0;
583 /* enable receive descriptor fetching */
584 rxdctl |= IGC_RXDCTL_QUEUE_ENABLE;
586 wr32(IGC_RXDCTL(reg_idx), rxdctl);
590 * igc_configure_rx - Configure receive Unit after Reset
591 * @adapter: board private structure
593 * Configure the Rx unit of the MAC after a reset.
595 static void igc_configure_rx(struct igc_adapter *adapter)
599 /* Setup the HW Rx Head and Tail Descriptor Pointers and
600 * the Base and Length of the Rx Descriptor Ring
602 for (i = 0; i < adapter->num_rx_queues; i++)
603 igc_configure_rx_ring(adapter, adapter->rx_ring[i]);
607 * igc_configure_tx_ring - Configure transmit ring after Reset
608 * @adapter: board private structure
609 * @ring: tx ring to configure
611 * Configure a transmit ring after a reset.
613 static void igc_configure_tx_ring(struct igc_adapter *adapter,
614 struct igc_ring *ring)
616 struct igc_hw *hw = &adapter->hw;
617 int reg_idx = ring->reg_idx;
618 u64 tdba = ring->dma;
621 /* disable the queue */
622 wr32(IGC_TXDCTL(reg_idx), 0);
626 wr32(IGC_TDLEN(reg_idx),
627 ring->count * sizeof(union igc_adv_tx_desc));
628 wr32(IGC_TDBAL(reg_idx),
629 tdba & 0x00000000ffffffffULL);
630 wr32(IGC_TDBAH(reg_idx), tdba >> 32);
632 ring->tail = adapter->io_addr + IGC_TDT(reg_idx);
633 wr32(IGC_TDH(reg_idx), 0);
634 writel(0, ring->tail);
636 txdctl |= IGC_TX_PTHRESH;
637 txdctl |= IGC_TX_HTHRESH << 8;
638 txdctl |= IGC_TX_WTHRESH << 16;
640 txdctl |= IGC_TXDCTL_QUEUE_ENABLE;
641 wr32(IGC_TXDCTL(reg_idx), txdctl);
645 * igc_configure_tx - Configure transmit Unit after Reset
646 * @adapter: board private structure
648 * Configure the Tx unit of the MAC after a reset.
650 static void igc_configure_tx(struct igc_adapter *adapter)
654 for (i = 0; i < adapter->num_tx_queues; i++)
655 igc_configure_tx_ring(adapter, adapter->tx_ring[i]);
659 * igc_setup_mrqc - configure the multiple receive queue control registers
660 * @adapter: Board private structure
662 static void igc_setup_mrqc(struct igc_adapter *adapter)
664 struct igc_hw *hw = &adapter->hw;
665 u32 j, num_rx_queues;
669 netdev_rss_key_fill(rss_key, sizeof(rss_key));
670 for (j = 0; j < 10; j++)
671 wr32(IGC_RSSRK(j), rss_key[j]);
673 num_rx_queues = adapter->rss_queues;
675 if (adapter->rss_indir_tbl_init != num_rx_queues) {
676 for (j = 0; j < IGC_RETA_SIZE; j++)
677 adapter->rss_indir_tbl[j] =
678 (j * num_rx_queues) / IGC_RETA_SIZE;
679 adapter->rss_indir_tbl_init = num_rx_queues;
681 igc_write_rss_indir_tbl(adapter);
683 /* Disable raw packet checksumming so that RSS hash is placed in
684 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
685 * offloads as they are enabled by default
687 rxcsum = rd32(IGC_RXCSUM);
688 rxcsum |= IGC_RXCSUM_PCSD;
690 /* Enable Receive Checksum Offload for SCTP */
691 rxcsum |= IGC_RXCSUM_CRCOFL;
693 /* Don't need to set TUOFL or IPOFL, they default to 1 */
694 wr32(IGC_RXCSUM, rxcsum);
696 /* Generate RSS hash based on packet types, TCP/UDP
697 * port numbers and/or IPv4/v6 src and dst addresses
699 mrqc = IGC_MRQC_RSS_FIELD_IPV4 |
700 IGC_MRQC_RSS_FIELD_IPV4_TCP |
701 IGC_MRQC_RSS_FIELD_IPV6 |
702 IGC_MRQC_RSS_FIELD_IPV6_TCP |
703 IGC_MRQC_RSS_FIELD_IPV6_TCP_EX;
705 if (adapter->flags & IGC_FLAG_RSS_FIELD_IPV4_UDP)
706 mrqc |= IGC_MRQC_RSS_FIELD_IPV4_UDP;
707 if (adapter->flags & IGC_FLAG_RSS_FIELD_IPV6_UDP)
708 mrqc |= IGC_MRQC_RSS_FIELD_IPV6_UDP;
710 mrqc |= IGC_MRQC_ENABLE_RSS_MQ;
712 wr32(IGC_MRQC, mrqc);
716 * igc_setup_rctl - configure the receive control registers
717 * @adapter: Board private structure
719 static void igc_setup_rctl(struct igc_adapter *adapter)
721 struct igc_hw *hw = &adapter->hw;
724 rctl = rd32(IGC_RCTL);
726 rctl &= ~(3 << IGC_RCTL_MO_SHIFT);
727 rctl &= ~(IGC_RCTL_LBM_TCVR | IGC_RCTL_LBM_MAC);
729 rctl |= IGC_RCTL_EN | IGC_RCTL_BAM | IGC_RCTL_RDMTS_HALF |
730 (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT);
732 /* enable stripping of CRC. Newer features require
733 * that the HW strips the CRC.
735 rctl |= IGC_RCTL_SECRC;
737 /* disable store bad packets and clear size bits. */
738 rctl &= ~(IGC_RCTL_SBP | IGC_RCTL_SZ_256);
740 /* enable LPE to allow for reception of jumbo frames */
741 rctl |= IGC_RCTL_LPE;
743 /* disable queue 0 to prevent tail write w/o re-config */
744 wr32(IGC_RXDCTL(0), 0);
746 /* This is useful for sniffing bad packets. */
747 if (adapter->netdev->features & NETIF_F_RXALL) {
748 /* UPE and MPE will be handled by normal PROMISC logic
751 rctl |= (IGC_RCTL_SBP | /* Receive bad packets */
752 IGC_RCTL_BAM | /* RX All Bcast Pkts */
753 IGC_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
755 rctl &= ~(IGC_RCTL_DPF | /* Allow filtered pause */
756 IGC_RCTL_CFIEN); /* Disable VLAN CFIEN Filter */
759 wr32(IGC_RCTL, rctl);
763 * igc_setup_tctl - configure the transmit control registers
764 * @adapter: Board private structure
766 static void igc_setup_tctl(struct igc_adapter *adapter)
768 struct igc_hw *hw = &adapter->hw;
771 /* disable queue 0 which icould be enabled by default */
772 wr32(IGC_TXDCTL(0), 0);
774 /* Program the Transmit Control Register */
775 tctl = rd32(IGC_TCTL);
776 tctl &= ~IGC_TCTL_CT;
777 tctl |= IGC_TCTL_PSP | IGC_TCTL_RTLC |
778 (IGC_COLLISION_THRESHOLD << IGC_CT_SHIFT);
780 /* Enable transmits */
783 wr32(IGC_TCTL, tctl);
787 * igc_set_mac_filter_hw() - Set MAC address filter in hardware
788 * @adapter: Pointer to adapter where the filter should be set
789 * @index: Filter index
790 * @type: MAC address filter type (source or destination)
792 * @queue: If non-negative, queue assignment feature is enabled and frames
793 * matching the filter are enqueued onto 'queue'. Otherwise, queue
794 * assignment is disabled.
796 static void igc_set_mac_filter_hw(struct igc_adapter *adapter, int index,
797 enum igc_mac_filter_type type,
798 const u8 *addr, int queue)
800 struct net_device *dev = adapter->netdev;
801 struct igc_hw *hw = &adapter->hw;
804 if (WARN_ON(index >= hw->mac.rar_entry_count))
807 ral = le32_to_cpup((__le32 *)(addr));
808 rah = le16_to_cpup((__le16 *)(addr + 4));
810 if (type == IGC_MAC_FILTER_TYPE_SRC) {
811 rah &= ~IGC_RAH_ASEL_MASK;
812 rah |= IGC_RAH_ASEL_SRC_ADDR;
816 rah &= ~IGC_RAH_QSEL_MASK;
817 rah |= (queue << IGC_RAH_QSEL_SHIFT);
818 rah |= IGC_RAH_QSEL_ENABLE;
823 wr32(IGC_RAL(index), ral);
824 wr32(IGC_RAH(index), rah);
826 netdev_dbg(dev, "MAC address filter set in HW: index %d", index);
830 * igc_clear_mac_filter_hw() - Clear MAC address filter in hardware
831 * @adapter: Pointer to adapter where the filter should be cleared
832 * @index: Filter index
834 static void igc_clear_mac_filter_hw(struct igc_adapter *adapter, int index)
836 struct net_device *dev = adapter->netdev;
837 struct igc_hw *hw = &adapter->hw;
839 if (WARN_ON(index >= hw->mac.rar_entry_count))
842 wr32(IGC_RAL(index), 0);
843 wr32(IGC_RAH(index), 0);
845 netdev_dbg(dev, "MAC address filter cleared in HW: index %d", index);
848 /* Set default MAC address for the PF in the first RAR entry */
849 static void igc_set_default_mac_filter(struct igc_adapter *adapter)
851 struct net_device *dev = adapter->netdev;
852 u8 *addr = adapter->hw.mac.addr;
854 netdev_dbg(dev, "Set default MAC address filter: address %pM", addr);
856 igc_set_mac_filter_hw(adapter, 0, IGC_MAC_FILTER_TYPE_DST, addr, -1);
860 * igc_set_mac - Change the Ethernet Address of the NIC
861 * @netdev: network interface device structure
862 * @p: pointer to an address structure
864 * Returns 0 on success, negative on failure
866 static int igc_set_mac(struct net_device *netdev, void *p)
868 struct igc_adapter *adapter = netdev_priv(netdev);
869 struct igc_hw *hw = &adapter->hw;
870 struct sockaddr *addr = p;
872 if (!is_valid_ether_addr(addr->sa_data))
873 return -EADDRNOTAVAIL;
875 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
876 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
878 /* set the correct pool for the new PF MAC address in entry 0 */
879 igc_set_default_mac_filter(adapter);
885 * igc_write_mc_addr_list - write multicast addresses to MTA
886 * @netdev: network interface device structure
888 * Writes multicast address list to the MTA hash table.
889 * Returns: -ENOMEM on failure
890 * 0 on no addresses written
891 * X on writing X addresses to MTA
893 static int igc_write_mc_addr_list(struct net_device *netdev)
895 struct igc_adapter *adapter = netdev_priv(netdev);
896 struct igc_hw *hw = &adapter->hw;
897 struct netdev_hw_addr *ha;
901 if (netdev_mc_empty(netdev)) {
902 /* nothing to program, so clear mc list */
903 igc_update_mc_addr_list(hw, NULL, 0);
907 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC);
911 /* The shared function expects a packed array of only addresses. */
913 netdev_for_each_mc_addr(ha, netdev)
914 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
916 igc_update_mc_addr_list(hw, mta_list, i);
919 return netdev_mc_count(netdev);
922 static __le32 igc_tx_launchtime(struct igc_adapter *adapter, ktime_t txtime)
924 ktime_t cycle_time = adapter->cycle_time;
925 ktime_t base_time = adapter->base_time;
928 /* FIXME: when using ETF together with taprio, we may have a
929 * case where 'delta' is larger than the cycle_time, this may
930 * cause problems if we don't read the current value of
931 * IGC_BASET, as the value writen into the launchtime
932 * descriptor field may be misinterpreted.
934 div_s64_rem(ktime_sub_ns(txtime, base_time), cycle_time, &launchtime);
936 return cpu_to_le32(launchtime);
939 static void igc_tx_ctxtdesc(struct igc_ring *tx_ring,
940 struct igc_tx_buffer *first,
941 u32 vlan_macip_lens, u32 type_tucmd,
944 struct igc_adv_tx_context_desc *context_desc;
945 u16 i = tx_ring->next_to_use;
947 context_desc = IGC_TX_CTXTDESC(tx_ring, i);
950 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
952 /* set bits to identify this as an advanced context descriptor */
953 type_tucmd |= IGC_TXD_CMD_DEXT | IGC_ADVTXD_DTYP_CTXT;
955 /* For i225, context index must be unique per ring. */
956 if (test_bit(IGC_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
957 mss_l4len_idx |= tx_ring->reg_idx << 4;
959 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
960 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
961 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
963 /* We assume there is always a valid Tx time available. Invalid times
964 * should have been handled by the upper layers.
966 if (tx_ring->launchtime_enable) {
967 struct igc_adapter *adapter = netdev_priv(tx_ring->netdev);
968 ktime_t txtime = first->skb->tstamp;
970 skb_txtime_consumed(first->skb);
971 context_desc->launch_time = igc_tx_launchtime(adapter,
974 context_desc->launch_time = 0;
978 static void igc_tx_csum(struct igc_ring *tx_ring, struct igc_tx_buffer *first)
980 struct sk_buff *skb = first->skb;
981 u32 vlan_macip_lens = 0;
984 if (skb->ip_summed != CHECKSUM_PARTIAL) {
986 if (!(first->tx_flags & IGC_TX_FLAGS_VLAN) &&
987 !tx_ring->launchtime_enable)
992 switch (skb->csum_offset) {
993 case offsetof(struct tcphdr, check):
994 type_tucmd = IGC_ADVTXD_TUCMD_L4T_TCP;
996 case offsetof(struct udphdr, check):
998 case offsetof(struct sctphdr, checksum):
999 /* validate that this is actually an SCTP request */
1000 if (skb_csum_is_sctp(skb)) {
1001 type_tucmd = IGC_ADVTXD_TUCMD_L4T_SCTP;
1006 skb_checksum_help(skb);
1010 /* update TX checksum flag */
1011 first->tx_flags |= IGC_TX_FLAGS_CSUM;
1012 vlan_macip_lens = skb_checksum_start_offset(skb) -
1013 skb_network_offset(skb);
1015 vlan_macip_lens |= skb_network_offset(skb) << IGC_ADVTXD_MACLEN_SHIFT;
1016 vlan_macip_lens |= first->tx_flags & IGC_TX_FLAGS_VLAN_MASK;
1018 igc_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0);
1021 static int __igc_maybe_stop_tx(struct igc_ring *tx_ring, const u16 size)
1023 struct net_device *netdev = tx_ring->netdev;
1025 netif_stop_subqueue(netdev, tx_ring->queue_index);
1027 /* memory barriier comment */
1030 /* We need to check again in a case another CPU has just
1031 * made room available.
1033 if (igc_desc_unused(tx_ring) < size)
1037 netif_wake_subqueue(netdev, tx_ring->queue_index);
1039 u64_stats_update_begin(&tx_ring->tx_syncp2);
1040 tx_ring->tx_stats.restart_queue2++;
1041 u64_stats_update_end(&tx_ring->tx_syncp2);
1046 static inline int igc_maybe_stop_tx(struct igc_ring *tx_ring, const u16 size)
1048 if (igc_desc_unused(tx_ring) >= size)
1050 return __igc_maybe_stop_tx(tx_ring, size);
1053 #define IGC_SET_FLAG(_input, _flag, _result) \
1054 (((_flag) <= (_result)) ? \
1055 ((u32)((_input) & (_flag)) * ((_result) / (_flag))) : \
1056 ((u32)((_input) & (_flag)) / ((_flag) / (_result))))
1058 static u32 igc_tx_cmd_type(u32 tx_flags)
1060 /* set type for advanced descriptor with frame checksum insertion */
1061 u32 cmd_type = IGC_ADVTXD_DTYP_DATA |
1062 IGC_ADVTXD_DCMD_DEXT |
1063 IGC_ADVTXD_DCMD_IFCS;
1065 /* set segmentation bits for TSO */
1066 cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSO,
1067 (IGC_ADVTXD_DCMD_TSE));
1069 /* set timestamp bit if present */
1070 cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSTAMP,
1071 (IGC_ADVTXD_MAC_TSTAMP));
1076 static void igc_tx_olinfo_status(struct igc_ring *tx_ring,
1077 union igc_adv_tx_desc *tx_desc,
1078 u32 tx_flags, unsigned int paylen)
1080 u32 olinfo_status = paylen << IGC_ADVTXD_PAYLEN_SHIFT;
1082 /* insert L4 checksum */
1083 olinfo_status |= (tx_flags & IGC_TX_FLAGS_CSUM) *
1084 ((IGC_TXD_POPTS_TXSM << 8) /
1087 /* insert IPv4 checksum */
1088 olinfo_status |= (tx_flags & IGC_TX_FLAGS_IPV4) *
1089 (((IGC_TXD_POPTS_IXSM << 8)) /
1092 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
1095 static int igc_tx_map(struct igc_ring *tx_ring,
1096 struct igc_tx_buffer *first,
1099 struct sk_buff *skb = first->skb;
1100 struct igc_tx_buffer *tx_buffer;
1101 union igc_adv_tx_desc *tx_desc;
1102 u32 tx_flags = first->tx_flags;
1104 u16 i = tx_ring->next_to_use;
1105 unsigned int data_len, size;
1107 u32 cmd_type = igc_tx_cmd_type(tx_flags);
1109 tx_desc = IGC_TX_DESC(tx_ring, i);
1111 igc_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
1113 size = skb_headlen(skb);
1114 data_len = skb->data_len;
1116 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1120 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1121 if (dma_mapping_error(tx_ring->dev, dma))
1124 /* record length, and DMA address */
1125 dma_unmap_len_set(tx_buffer, len, size);
1126 dma_unmap_addr_set(tx_buffer, dma, dma);
1128 tx_desc->read.buffer_addr = cpu_to_le64(dma);
1130 while (unlikely(size > IGC_MAX_DATA_PER_TXD)) {
1131 tx_desc->read.cmd_type_len =
1132 cpu_to_le32(cmd_type ^ IGC_MAX_DATA_PER_TXD);
1136 if (i == tx_ring->count) {
1137 tx_desc = IGC_TX_DESC(tx_ring, 0);
1140 tx_desc->read.olinfo_status = 0;
1142 dma += IGC_MAX_DATA_PER_TXD;
1143 size -= IGC_MAX_DATA_PER_TXD;
1145 tx_desc->read.buffer_addr = cpu_to_le64(dma);
1148 if (likely(!data_len))
1151 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
1155 if (i == tx_ring->count) {
1156 tx_desc = IGC_TX_DESC(tx_ring, 0);
1159 tx_desc->read.olinfo_status = 0;
1161 size = skb_frag_size(frag);
1164 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
1165 size, DMA_TO_DEVICE);
1167 tx_buffer = &tx_ring->tx_buffer_info[i];
1170 /* write last descriptor with RS and EOP bits */
1171 cmd_type |= size | IGC_TXD_DCMD;
1172 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
1174 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
1176 /* set the timestamp */
1177 first->time_stamp = jiffies;
1179 skb_tx_timestamp(skb);
1181 /* Force memory writes to complete before letting h/w know there
1182 * are new descriptors to fetch. (Only applicable for weak-ordered
1183 * memory model archs, such as IA-64).
1185 * We also need this memory barrier to make certain all of the
1186 * status bits have been updated before next_to_watch is written.
1190 /* set next_to_watch value indicating a packet is present */
1191 first->next_to_watch = tx_desc;
1194 if (i == tx_ring->count)
1197 tx_ring->next_to_use = i;
1199 /* Make sure there is space in the ring for the next send. */
1200 igc_maybe_stop_tx(tx_ring, DESC_NEEDED);
1202 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
1203 writel(i, tx_ring->tail);
1208 netdev_err(tx_ring->netdev, "TX DMA map failed\n");
1209 tx_buffer = &tx_ring->tx_buffer_info[i];
1211 /* clear dma mappings for failed tx_buffer_info map */
1212 while (tx_buffer != first) {
1213 if (dma_unmap_len(tx_buffer, len))
1214 dma_unmap_page(tx_ring->dev,
1215 dma_unmap_addr(tx_buffer, dma),
1216 dma_unmap_len(tx_buffer, len),
1218 dma_unmap_len_set(tx_buffer, len, 0);
1221 i += tx_ring->count;
1222 tx_buffer = &tx_ring->tx_buffer_info[i];
1225 if (dma_unmap_len(tx_buffer, len))
1226 dma_unmap_single(tx_ring->dev,
1227 dma_unmap_addr(tx_buffer, dma),
1228 dma_unmap_len(tx_buffer, len),
1230 dma_unmap_len_set(tx_buffer, len, 0);
1232 dev_kfree_skb_any(tx_buffer->skb);
1233 tx_buffer->skb = NULL;
1235 tx_ring->next_to_use = i;
1240 static int igc_tso(struct igc_ring *tx_ring,
1241 struct igc_tx_buffer *first,
1244 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
1245 struct sk_buff *skb = first->skb;
1256 u32 paylen, l4_offset;
1259 if (skb->ip_summed != CHECKSUM_PARTIAL)
1262 if (!skb_is_gso(skb))
1265 err = skb_cow_head(skb, 0);
1269 ip.hdr = skb_network_header(skb);
1270 l4.hdr = skb_checksum_start(skb);
1272 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
1273 type_tucmd = IGC_ADVTXD_TUCMD_L4T_TCP;
1275 /* initialize outer IP header fields */
1276 if (ip.v4->version == 4) {
1277 unsigned char *csum_start = skb_checksum_start(skb);
1278 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
1280 /* IP header will have to cancel out any data that
1281 * is not a part of the outer IP header
1283 ip.v4->check = csum_fold(csum_partial(trans_start,
1284 csum_start - trans_start,
1286 type_tucmd |= IGC_ADVTXD_TUCMD_IPV4;
1289 first->tx_flags |= IGC_TX_FLAGS_TSO |
1293 ip.v6->payload_len = 0;
1294 first->tx_flags |= IGC_TX_FLAGS_TSO |
1298 /* determine offset of inner transport header */
1299 l4_offset = l4.hdr - skb->data;
1301 /* remove payload length from inner checksum */
1302 paylen = skb->len - l4_offset;
1303 if (type_tucmd & IGC_ADVTXD_TUCMD_L4T_TCP) {
1304 /* compute length of segmentation header */
1305 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
1306 csum_replace_by_diff(&l4.tcp->check,
1307 (__force __wsum)htonl(paylen));
1309 /* compute length of segmentation header */
1310 *hdr_len = sizeof(*l4.udp) + l4_offset;
1311 csum_replace_by_diff(&l4.udp->check,
1312 (__force __wsum)htonl(paylen));
1315 /* update gso size and bytecount with header size */
1316 first->gso_segs = skb_shinfo(skb)->gso_segs;
1317 first->bytecount += (first->gso_segs - 1) * *hdr_len;
1320 mss_l4len_idx = (*hdr_len - l4_offset) << IGC_ADVTXD_L4LEN_SHIFT;
1321 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IGC_ADVTXD_MSS_SHIFT;
1323 /* VLAN MACLEN IPLEN */
1324 vlan_macip_lens = l4.hdr - ip.hdr;
1325 vlan_macip_lens |= (ip.hdr - skb->data) << IGC_ADVTXD_MACLEN_SHIFT;
1326 vlan_macip_lens |= first->tx_flags & IGC_TX_FLAGS_VLAN_MASK;
1328 igc_tx_ctxtdesc(tx_ring, first, vlan_macip_lens,
1329 type_tucmd, mss_l4len_idx);
1334 static netdev_tx_t igc_xmit_frame_ring(struct sk_buff *skb,
1335 struct igc_ring *tx_ring)
1337 u16 count = TXD_USE_COUNT(skb_headlen(skb));
1338 __be16 protocol = vlan_get_protocol(skb);
1339 struct igc_tx_buffer *first;
1345 /* need: 1 descriptor per page * PAGE_SIZE/IGC_MAX_DATA_PER_TXD,
1346 * + 1 desc for skb_headlen/IGC_MAX_DATA_PER_TXD,
1347 * + 2 desc gap to keep tail from touching head,
1348 * + 1 desc for context descriptor,
1349 * otherwise try next time
1351 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1352 count += TXD_USE_COUNT(skb_frag_size(
1353 &skb_shinfo(skb)->frags[f]));
1355 if (igc_maybe_stop_tx(tx_ring, count + 3)) {
1356 /* this is a hard error */
1357 return NETDEV_TX_BUSY;
1360 /* record the location of the first descriptor for this packet */
1361 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
1363 first->bytecount = skb->len;
1364 first->gso_segs = 1;
1366 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
1367 struct igc_adapter *adapter = netdev_priv(tx_ring->netdev);
1369 /* FIXME: add support for retrieving timestamps from
1370 * the other timer registers before skipping the
1371 * timestamping request.
1373 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON &&
1374 !test_and_set_bit_lock(__IGC_PTP_TX_IN_PROGRESS,
1376 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1377 tx_flags |= IGC_TX_FLAGS_TSTAMP;
1379 adapter->ptp_tx_skb = skb_get(skb);
1380 adapter->ptp_tx_start = jiffies;
1382 adapter->tx_hwtstamp_skipped++;
1386 /* record initial flags and protocol */
1387 first->tx_flags = tx_flags;
1388 first->protocol = protocol;
1390 tso = igc_tso(tx_ring, first, &hdr_len);
1394 igc_tx_csum(tx_ring, first);
1396 igc_tx_map(tx_ring, first, hdr_len);
1398 return NETDEV_TX_OK;
1401 dev_kfree_skb_any(first->skb);
1404 return NETDEV_TX_OK;
1407 static inline struct igc_ring *igc_tx_queue_mapping(struct igc_adapter *adapter,
1408 struct sk_buff *skb)
1410 unsigned int r_idx = skb->queue_mapping;
1412 if (r_idx >= adapter->num_tx_queues)
1413 r_idx = r_idx % adapter->num_tx_queues;
1415 return adapter->tx_ring[r_idx];
1418 static netdev_tx_t igc_xmit_frame(struct sk_buff *skb,
1419 struct net_device *netdev)
1421 struct igc_adapter *adapter = netdev_priv(netdev);
1423 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1424 * in order to meet this minimum size requirement.
1426 if (skb->len < 17) {
1427 if (skb_padto(skb, 17))
1428 return NETDEV_TX_OK;
1432 return igc_xmit_frame_ring(skb, igc_tx_queue_mapping(adapter, skb));
1435 static void igc_rx_checksum(struct igc_ring *ring,
1436 union igc_adv_rx_desc *rx_desc,
1437 struct sk_buff *skb)
1439 skb_checksum_none_assert(skb);
1441 /* Ignore Checksum bit is set */
1442 if (igc_test_staterr(rx_desc, IGC_RXD_STAT_IXSM))
1445 /* Rx checksum disabled via ethtool */
1446 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1449 /* TCP/UDP checksum error bit is set */
1450 if (igc_test_staterr(rx_desc,
1451 IGC_RXDEXT_STATERR_L4E |
1452 IGC_RXDEXT_STATERR_IPE)) {
1453 /* work around errata with sctp packets where the TCPE aka
1454 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
1455 * packets (aka let the stack check the crc32c)
1457 if (!(skb->len == 60 &&
1458 test_bit(IGC_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
1459 u64_stats_update_begin(&ring->rx_syncp);
1460 ring->rx_stats.csum_err++;
1461 u64_stats_update_end(&ring->rx_syncp);
1463 /* let the stack verify checksum errors */
1466 /* It must be a TCP or UDP packet with a valid checksum */
1467 if (igc_test_staterr(rx_desc, IGC_RXD_STAT_TCPCS |
1468 IGC_RXD_STAT_UDPCS))
1469 skb->ip_summed = CHECKSUM_UNNECESSARY;
1471 netdev_dbg(ring->netdev, "cksum success: bits %08X\n",
1472 le32_to_cpu(rx_desc->wb.upper.status_error));
1475 static inline void igc_rx_hash(struct igc_ring *ring,
1476 union igc_adv_rx_desc *rx_desc,
1477 struct sk_buff *skb)
1479 if (ring->netdev->features & NETIF_F_RXHASH)
1481 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1486 * igc_process_skb_fields - Populate skb header fields from Rx descriptor
1487 * @rx_ring: rx descriptor ring packet is being transacted on
1488 * @rx_desc: pointer to the EOP Rx descriptor
1489 * @skb: pointer to current skb being populated
1491 * This function checks the ring, descriptor, and packet information in order
1492 * to populate the hash, checksum, VLAN, protocol, and other fields within the
1495 static void igc_process_skb_fields(struct igc_ring *rx_ring,
1496 union igc_adv_rx_desc *rx_desc,
1497 struct sk_buff *skb)
1499 igc_rx_hash(rx_ring, rx_desc, skb);
1501 igc_rx_checksum(rx_ring, rx_desc, skb);
1503 skb_record_rx_queue(skb, rx_ring->queue_index);
1505 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1508 static struct igc_rx_buffer *igc_get_rx_buffer(struct igc_ring *rx_ring,
1509 const unsigned int size,
1510 int *rx_buffer_pgcnt)
1512 struct igc_rx_buffer *rx_buffer;
1514 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1516 #if (PAGE_SIZE < 8192)
1517 page_count(rx_buffer->page);
1521 prefetchw(rx_buffer->page);
1523 /* we are reusing so sync this buffer for CPU use */
1524 dma_sync_single_range_for_cpu(rx_ring->dev,
1526 rx_buffer->page_offset,
1530 rx_buffer->pagecnt_bias--;
1535 static void igc_rx_buffer_flip(struct igc_rx_buffer *buffer,
1536 unsigned int truesize)
1538 #if (PAGE_SIZE < 8192)
1539 buffer->page_offset ^= truesize;
1541 buffer->page_offset += truesize;
1545 static unsigned int igc_get_rx_frame_truesize(struct igc_ring *ring,
1548 unsigned int truesize;
1550 #if (PAGE_SIZE < 8192)
1551 truesize = igc_rx_pg_size(ring) / 2;
1553 truesize = ring_uses_build_skb(ring) ?
1554 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
1555 SKB_DATA_ALIGN(IGC_SKB_PAD + size) :
1556 SKB_DATA_ALIGN(size);
1562 * igc_add_rx_frag - Add contents of Rx buffer to sk_buff
1563 * @rx_ring: rx descriptor ring to transact packets on
1564 * @rx_buffer: buffer containing page to add
1565 * @skb: sk_buff to place the data into
1566 * @size: size of buffer to be added
1568 * This function will add the data contained in rx_buffer->page to the skb.
1570 static void igc_add_rx_frag(struct igc_ring *rx_ring,
1571 struct igc_rx_buffer *rx_buffer,
1572 struct sk_buff *skb,
1575 unsigned int truesize;
1577 #if (PAGE_SIZE < 8192)
1578 truesize = igc_rx_pg_size(rx_ring) / 2;
1580 truesize = ring_uses_build_skb(rx_ring) ?
1581 SKB_DATA_ALIGN(IGC_SKB_PAD + size) :
1582 SKB_DATA_ALIGN(size);
1584 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
1585 rx_buffer->page_offset, size, truesize);
1587 igc_rx_buffer_flip(rx_buffer, truesize);
1590 static struct sk_buff *igc_build_skb(struct igc_ring *rx_ring,
1591 struct igc_rx_buffer *rx_buffer,
1592 union igc_adv_rx_desc *rx_desc,
1595 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset;
1596 unsigned int truesize = igc_get_rx_frame_truesize(rx_ring, size);
1597 struct sk_buff *skb;
1599 /* prefetch first cache line of first page */
1602 /* build an skb around the page buffer */
1603 skb = build_skb(va - IGC_SKB_PAD, truesize);
1607 /* update pointers within the skb to store the data */
1608 skb_reserve(skb, IGC_SKB_PAD);
1609 __skb_put(skb, size);
1611 igc_rx_buffer_flip(rx_buffer, truesize);
1615 static struct sk_buff *igc_construct_skb(struct igc_ring *rx_ring,
1616 struct igc_rx_buffer *rx_buffer,
1617 struct xdp_buff *xdp,
1620 unsigned int size = xdp->data_end - xdp->data;
1621 unsigned int truesize = igc_get_rx_frame_truesize(rx_ring, size);
1622 void *va = xdp->data;
1623 unsigned int headlen;
1624 struct sk_buff *skb;
1626 /* prefetch first cache line of first page */
1629 /* allocate a skb to store the frags */
1630 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGC_RX_HDR_LEN);
1635 skb_hwtstamps(skb)->hwtstamp = timestamp;
1637 /* Determine available headroom for copy */
1639 if (headlen > IGC_RX_HDR_LEN)
1640 headlen = eth_get_headlen(skb->dev, va, IGC_RX_HDR_LEN);
1642 /* align pull length to size of long to optimize memcpy performance */
1643 memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long)));
1645 /* update all of the pointers */
1648 skb_add_rx_frag(skb, 0, rx_buffer->page,
1649 (va + headlen) - page_address(rx_buffer->page),
1651 igc_rx_buffer_flip(rx_buffer, truesize);
1653 rx_buffer->pagecnt_bias++;
1660 * igc_reuse_rx_page - page flip buffer and store it back on the ring
1661 * @rx_ring: rx descriptor ring to store buffers on
1662 * @old_buff: donor buffer to have page reused
1664 * Synchronizes page for reuse by the adapter
1666 static void igc_reuse_rx_page(struct igc_ring *rx_ring,
1667 struct igc_rx_buffer *old_buff)
1669 u16 nta = rx_ring->next_to_alloc;
1670 struct igc_rx_buffer *new_buff;
1672 new_buff = &rx_ring->rx_buffer_info[nta];
1674 /* update, and store next to alloc */
1676 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1678 /* Transfer page from old buffer to new buffer.
1679 * Move each member individually to avoid possible store
1680 * forwarding stalls.
1682 new_buff->dma = old_buff->dma;
1683 new_buff->page = old_buff->page;
1684 new_buff->page_offset = old_buff->page_offset;
1685 new_buff->pagecnt_bias = old_buff->pagecnt_bias;
1688 static bool igc_can_reuse_rx_page(struct igc_rx_buffer *rx_buffer,
1689 int rx_buffer_pgcnt)
1691 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
1692 struct page *page = rx_buffer->page;
1694 /* avoid re-using remote and pfmemalloc pages */
1695 if (!dev_page_is_reusable(page))
1698 #if (PAGE_SIZE < 8192)
1699 /* if we are only owner of page we can reuse it */
1700 if (unlikely((rx_buffer_pgcnt - pagecnt_bias) > 1))
1703 #define IGC_LAST_OFFSET \
1704 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGC_RXBUFFER_2048)
1706 if (rx_buffer->page_offset > IGC_LAST_OFFSET)
1710 /* If we have drained the page fragment pool we need to update
1711 * the pagecnt_bias and page count so that we fully restock the
1712 * number of references the driver holds.
1714 if (unlikely(pagecnt_bias == 1)) {
1715 page_ref_add(page, USHRT_MAX - 1);
1716 rx_buffer->pagecnt_bias = USHRT_MAX;
1723 * igc_is_non_eop - process handling of non-EOP buffers
1724 * @rx_ring: Rx ring being processed
1725 * @rx_desc: Rx descriptor for current buffer
1727 * This function updates next to clean. If the buffer is an EOP buffer
1728 * this function exits returning false, otherwise it will place the
1729 * sk_buff in the next buffer to be chained and return true indicating
1730 * that this is in fact a non-EOP buffer.
1732 static bool igc_is_non_eop(struct igc_ring *rx_ring,
1733 union igc_adv_rx_desc *rx_desc)
1735 u32 ntc = rx_ring->next_to_clean + 1;
1737 /* fetch, update, and store next to clean */
1738 ntc = (ntc < rx_ring->count) ? ntc : 0;
1739 rx_ring->next_to_clean = ntc;
1741 prefetch(IGC_RX_DESC(rx_ring, ntc));
1743 if (likely(igc_test_staterr(rx_desc, IGC_RXD_STAT_EOP)))
1750 * igc_cleanup_headers - Correct corrupted or empty headers
1751 * @rx_ring: rx descriptor ring packet is being transacted on
1752 * @rx_desc: pointer to the EOP Rx descriptor
1753 * @skb: pointer to current skb being fixed
1755 * Address the case where we are pulling data in on pages only
1756 * and as such no data is present in the skb header.
1758 * In addition if skb is not at least 60 bytes we need to pad it so that
1759 * it is large enough to qualify as a valid Ethernet frame.
1761 * Returns true if an error was encountered and skb was freed.
1763 static bool igc_cleanup_headers(struct igc_ring *rx_ring,
1764 union igc_adv_rx_desc *rx_desc,
1765 struct sk_buff *skb)
1767 /* XDP packets use error pointer so abort at this point */
1771 if (unlikely(igc_test_staterr(rx_desc, IGC_RXDEXT_STATERR_RXE))) {
1772 struct net_device *netdev = rx_ring->netdev;
1774 if (!(netdev->features & NETIF_F_RXALL)) {
1775 dev_kfree_skb_any(skb);
1780 /* if eth_skb_pad returns an error the skb was freed */
1781 if (eth_skb_pad(skb))
1787 static void igc_put_rx_buffer(struct igc_ring *rx_ring,
1788 struct igc_rx_buffer *rx_buffer,
1789 int rx_buffer_pgcnt)
1791 if (igc_can_reuse_rx_page(rx_buffer, rx_buffer_pgcnt)) {
1792 /* hand second half of page back to the ring */
1793 igc_reuse_rx_page(rx_ring, rx_buffer);
1795 /* We are not reusing the buffer so unmap it and free
1796 * any references we are holding to it
1798 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
1799 igc_rx_pg_size(rx_ring), DMA_FROM_DEVICE,
1801 __page_frag_cache_drain(rx_buffer->page,
1802 rx_buffer->pagecnt_bias);
1805 /* clear contents of rx_buffer */
1806 rx_buffer->page = NULL;
1809 static inline unsigned int igc_rx_offset(struct igc_ring *rx_ring)
1811 struct igc_adapter *adapter = rx_ring->q_vector->adapter;
1813 if (ring_uses_build_skb(rx_ring))
1815 if (igc_xdp_is_enabled(adapter))
1816 return XDP_PACKET_HEADROOM;
1821 static bool igc_alloc_mapped_page(struct igc_ring *rx_ring,
1822 struct igc_rx_buffer *bi)
1824 struct page *page = bi->page;
1827 /* since we are recycling buffers we should seldom need to alloc */
1831 /* alloc new page for storage */
1832 page = dev_alloc_pages(igc_rx_pg_order(rx_ring));
1833 if (unlikely(!page)) {
1834 rx_ring->rx_stats.alloc_failed++;
1838 /* map page for use */
1839 dma = dma_map_page_attrs(rx_ring->dev, page, 0,
1840 igc_rx_pg_size(rx_ring),
1844 /* if mapping failed free memory back to system since
1845 * there isn't much point in holding memory we can't use
1847 if (dma_mapping_error(rx_ring->dev, dma)) {
1850 rx_ring->rx_stats.alloc_failed++;
1856 bi->page_offset = igc_rx_offset(rx_ring);
1857 page_ref_add(page, USHRT_MAX - 1);
1858 bi->pagecnt_bias = USHRT_MAX;
1864 * igc_alloc_rx_buffers - Replace used receive buffers; packet split
1865 * @rx_ring: rx descriptor ring
1866 * @cleaned_count: number of buffers to clean
1868 static void igc_alloc_rx_buffers(struct igc_ring *rx_ring, u16 cleaned_count)
1870 union igc_adv_rx_desc *rx_desc;
1871 u16 i = rx_ring->next_to_use;
1872 struct igc_rx_buffer *bi;
1879 rx_desc = IGC_RX_DESC(rx_ring, i);
1880 bi = &rx_ring->rx_buffer_info[i];
1881 i -= rx_ring->count;
1883 bufsz = igc_rx_bufsz(rx_ring);
1886 if (!igc_alloc_mapped_page(rx_ring, bi))
1889 /* sync the buffer for use by the device */
1890 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
1891 bi->page_offset, bufsz,
1894 /* Refresh the desc even if buffer_addrs didn't change
1895 * because each write-back erases this info.
1897 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1903 rx_desc = IGC_RX_DESC(rx_ring, 0);
1904 bi = rx_ring->rx_buffer_info;
1905 i -= rx_ring->count;
1908 /* clear the length for the next_to_use descriptor */
1909 rx_desc->wb.upper.length = 0;
1912 } while (cleaned_count);
1914 i += rx_ring->count;
1916 if (rx_ring->next_to_use != i) {
1917 /* record the next descriptor to use */
1918 rx_ring->next_to_use = i;
1920 /* update next to alloc since we have filled the ring */
1921 rx_ring->next_to_alloc = i;
1923 /* Force memory writes to complete before letting h/w
1924 * know there are new descriptors to fetch. (Only
1925 * applicable for weak-ordered memory model archs,
1929 writel(i, rx_ring->tail);
1933 static int igc_xdp_init_tx_buffer(struct igc_tx_buffer *buffer,
1934 struct xdp_frame *xdpf,
1935 struct igc_ring *ring)
1939 dma = dma_map_single(ring->dev, xdpf->data, xdpf->len, DMA_TO_DEVICE);
1940 if (dma_mapping_error(ring->dev, dma)) {
1941 netdev_err_once(ring->netdev, "Failed to map DMA for TX\n");
1945 buffer->xdpf = xdpf;
1946 buffer->tx_flags = IGC_TX_FLAGS_XDP;
1947 buffer->protocol = 0;
1948 buffer->bytecount = xdpf->len;
1949 buffer->gso_segs = 1;
1950 buffer->time_stamp = jiffies;
1951 dma_unmap_len_set(buffer, len, xdpf->len);
1952 dma_unmap_addr_set(buffer, dma, dma);
1956 /* This function requires __netif_tx_lock is held by the caller. */
1957 static int igc_xdp_init_tx_descriptor(struct igc_ring *ring,
1958 struct xdp_frame *xdpf)
1960 struct igc_tx_buffer *buffer;
1961 union igc_adv_tx_desc *desc;
1962 u32 cmd_type, olinfo_status;
1965 if (!igc_desc_unused(ring))
1968 buffer = &ring->tx_buffer_info[ring->next_to_use];
1969 err = igc_xdp_init_tx_buffer(buffer, xdpf, ring);
1973 cmd_type = IGC_ADVTXD_DTYP_DATA | IGC_ADVTXD_DCMD_DEXT |
1974 IGC_ADVTXD_DCMD_IFCS | IGC_TXD_DCMD |
1976 olinfo_status = buffer->bytecount << IGC_ADVTXD_PAYLEN_SHIFT;
1978 desc = IGC_TX_DESC(ring, ring->next_to_use);
1979 desc->read.cmd_type_len = cpu_to_le32(cmd_type);
1980 desc->read.olinfo_status = cpu_to_le32(olinfo_status);
1981 desc->read.buffer_addr = cpu_to_le64(dma_unmap_addr(buffer, dma));
1983 netdev_tx_sent_queue(txring_txq(ring), buffer->bytecount);
1985 buffer->next_to_watch = desc;
1987 ring->next_to_use++;
1988 if (ring->next_to_use == ring->count)
1989 ring->next_to_use = 0;
1994 static struct igc_ring *igc_xdp_get_tx_ring(struct igc_adapter *adapter,
1999 if (unlikely(index < 0))
2002 while (index >= adapter->num_tx_queues)
2003 index -= adapter->num_tx_queues;
2005 return adapter->tx_ring[index];
2008 static int igc_xdp_xmit_back(struct igc_adapter *adapter, struct xdp_buff *xdp)
2010 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
2011 int cpu = smp_processor_id();
2012 struct netdev_queue *nq;
2013 struct igc_ring *ring;
2016 if (unlikely(!xdpf))
2019 ring = igc_xdp_get_tx_ring(adapter, cpu);
2020 nq = txring_txq(ring);
2022 __netif_tx_lock(nq, cpu);
2023 res = igc_xdp_init_tx_descriptor(ring, xdpf);
2024 __netif_tx_unlock(nq);
2028 static struct sk_buff *igc_xdp_run_prog(struct igc_adapter *adapter,
2029 struct xdp_buff *xdp)
2031 struct bpf_prog *prog;
2037 prog = READ_ONCE(adapter->xdp_prog);
2043 act = bpf_prog_run_xdp(prog, xdp);
2049 if (igc_xdp_xmit_back(adapter, xdp) < 0)
2050 res = IGC_XDP_CONSUMED;
2055 if (xdp_do_redirect(adapter->netdev, xdp, prog) < 0)
2056 res = IGC_XDP_CONSUMED;
2058 res = IGC_XDP_REDIRECT;
2061 bpf_warn_invalid_xdp_action(act);
2064 trace_xdp_exception(adapter->netdev, prog, act);
2067 res = IGC_XDP_CONSUMED;
2073 return ERR_PTR(-res);
2076 /* This function assumes __netif_tx_lock is held by the caller. */
2077 static void igc_flush_tx_descriptors(struct igc_ring *ring)
2079 /* Once tail pointer is updated, hardware can fetch the descriptors
2080 * any time so we issue a write membar here to ensure all memory
2081 * writes are complete before the tail pointer is updated.
2084 writel(ring->next_to_use, ring->tail);
2087 static void igc_finalize_xdp(struct igc_adapter *adapter, int status)
2089 int cpu = smp_processor_id();
2090 struct netdev_queue *nq;
2091 struct igc_ring *ring;
2093 if (status & IGC_XDP_TX) {
2094 ring = igc_xdp_get_tx_ring(adapter, cpu);
2095 nq = txring_txq(ring);
2097 __netif_tx_lock(nq, cpu);
2098 igc_flush_tx_descriptors(ring);
2099 __netif_tx_unlock(nq);
2102 if (status & IGC_XDP_REDIRECT)
2106 static int igc_clean_rx_irq(struct igc_q_vector *q_vector, const int budget)
2108 unsigned int total_bytes = 0, total_packets = 0;
2109 struct igc_adapter *adapter = q_vector->adapter;
2110 struct igc_ring *rx_ring = q_vector->rx.ring;
2111 struct sk_buff *skb = rx_ring->skb;
2112 u16 cleaned_count = igc_desc_unused(rx_ring);
2113 int xdp_status = 0, rx_buffer_pgcnt;
2115 while (likely(total_packets < budget)) {
2116 union igc_adv_rx_desc *rx_desc;
2117 struct igc_rx_buffer *rx_buffer;
2118 unsigned int size, truesize;
2119 ktime_t timestamp = 0;
2120 struct xdp_buff xdp;
2124 /* return some buffers to hardware, one at a time is too slow */
2125 if (cleaned_count >= IGC_RX_BUFFER_WRITE) {
2126 igc_alloc_rx_buffers(rx_ring, cleaned_count);
2130 rx_desc = IGC_RX_DESC(rx_ring, rx_ring->next_to_clean);
2131 size = le16_to_cpu(rx_desc->wb.upper.length);
2135 /* This memory barrier is needed to keep us from reading
2136 * any other fields out of the rx_desc until we know the
2137 * descriptor has been written back
2141 rx_buffer = igc_get_rx_buffer(rx_ring, size, &rx_buffer_pgcnt);
2142 truesize = igc_get_rx_frame_truesize(rx_ring, size);
2144 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset;
2146 if (igc_test_staterr(rx_desc, IGC_RXDADV_STAT_TSIP)) {
2147 timestamp = igc_ptp_rx_pktstamp(q_vector->adapter,
2149 pkt_offset = IGC_TS_HDR_LEN;
2150 size -= IGC_TS_HDR_LEN;
2154 xdp.data = pktbuf + pkt_offset;
2155 xdp.data_end = xdp.data + size;
2156 xdp.data_hard_start = pktbuf - igc_rx_offset(rx_ring);
2157 xdp_set_data_meta_invalid(&xdp);
2158 xdp.frame_sz = truesize;
2159 xdp.rxq = &rx_ring->xdp_rxq;
2161 skb = igc_xdp_run_prog(adapter, &xdp);
2165 unsigned int xdp_res = -PTR_ERR(skb);
2168 case IGC_XDP_CONSUMED:
2169 rx_buffer->pagecnt_bias++;
2172 case IGC_XDP_REDIRECT:
2173 igc_rx_buffer_flip(rx_buffer, truesize);
2174 xdp_status |= xdp_res;
2179 total_bytes += size;
2181 igc_add_rx_frag(rx_ring, rx_buffer, skb, size);
2182 else if (ring_uses_build_skb(rx_ring))
2183 skb = igc_build_skb(rx_ring, rx_buffer, rx_desc, size);
2185 skb = igc_construct_skb(rx_ring, rx_buffer, &xdp,
2188 /* exit if we failed to retrieve a buffer */
2190 rx_ring->rx_stats.alloc_failed++;
2191 rx_buffer->pagecnt_bias++;
2195 igc_put_rx_buffer(rx_ring, rx_buffer, rx_buffer_pgcnt);
2198 /* fetch next buffer in frame if non-eop */
2199 if (igc_is_non_eop(rx_ring, rx_desc))
2202 /* verify the packet layout is correct */
2203 if (igc_cleanup_headers(rx_ring, rx_desc, skb)) {
2208 /* probably a little skewed due to removing CRC */
2209 total_bytes += skb->len;
2211 /* populate checksum, VLAN, and protocol */
2212 igc_process_skb_fields(rx_ring, rx_desc, skb);
2214 napi_gro_receive(&q_vector->napi, skb);
2216 /* reset skb pointer */
2219 /* update budget accounting */
2224 igc_finalize_xdp(adapter, xdp_status);
2226 /* place incomplete frames back on ring for completion */
2229 u64_stats_update_begin(&rx_ring->rx_syncp);
2230 rx_ring->rx_stats.packets += total_packets;
2231 rx_ring->rx_stats.bytes += total_bytes;
2232 u64_stats_update_end(&rx_ring->rx_syncp);
2233 q_vector->rx.total_packets += total_packets;
2234 q_vector->rx.total_bytes += total_bytes;
2237 igc_alloc_rx_buffers(rx_ring, cleaned_count);
2239 return total_packets;
2243 * igc_clean_tx_irq - Reclaim resources after transmit completes
2244 * @q_vector: pointer to q_vector containing needed info
2245 * @napi_budget: Used to determine if we are in netpoll
2247 * returns true if ring is completely cleaned
2249 static bool igc_clean_tx_irq(struct igc_q_vector *q_vector, int napi_budget)
2251 struct igc_adapter *adapter = q_vector->adapter;
2252 unsigned int total_bytes = 0, total_packets = 0;
2253 unsigned int budget = q_vector->tx.work_limit;
2254 struct igc_ring *tx_ring = q_vector->tx.ring;
2255 unsigned int i = tx_ring->next_to_clean;
2256 struct igc_tx_buffer *tx_buffer;
2257 union igc_adv_tx_desc *tx_desc;
2259 if (test_bit(__IGC_DOWN, &adapter->state))
2262 tx_buffer = &tx_ring->tx_buffer_info[i];
2263 tx_desc = IGC_TX_DESC(tx_ring, i);
2264 i -= tx_ring->count;
2267 union igc_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
2269 /* if next_to_watch is not set then there is no work pending */
2273 /* prevent any other reads prior to eop_desc */
2276 /* if DD is not set pending work has not been completed */
2277 if (!(eop_desc->wb.status & cpu_to_le32(IGC_TXD_STAT_DD)))
2280 /* clear next_to_watch to prevent false hangs */
2281 tx_buffer->next_to_watch = NULL;
2283 /* update the statistics for this packet */
2284 total_bytes += tx_buffer->bytecount;
2285 total_packets += tx_buffer->gso_segs;
2287 if (tx_buffer->tx_flags & IGC_TX_FLAGS_XDP)
2288 xdp_return_frame(tx_buffer->xdpf);
2290 napi_consume_skb(tx_buffer->skb, napi_budget);
2292 /* unmap skb header data */
2293 dma_unmap_single(tx_ring->dev,
2294 dma_unmap_addr(tx_buffer, dma),
2295 dma_unmap_len(tx_buffer, len),
2298 /* clear tx_buffer data */
2299 dma_unmap_len_set(tx_buffer, len, 0);
2301 /* clear last DMA location and unmap remaining buffers */
2302 while (tx_desc != eop_desc) {
2307 i -= tx_ring->count;
2308 tx_buffer = tx_ring->tx_buffer_info;
2309 tx_desc = IGC_TX_DESC(tx_ring, 0);
2312 /* unmap any remaining paged data */
2313 if (dma_unmap_len(tx_buffer, len)) {
2314 dma_unmap_page(tx_ring->dev,
2315 dma_unmap_addr(tx_buffer, dma),
2316 dma_unmap_len(tx_buffer, len),
2318 dma_unmap_len_set(tx_buffer, len, 0);
2322 /* move us one more past the eop_desc for start of next pkt */
2327 i -= tx_ring->count;
2328 tx_buffer = tx_ring->tx_buffer_info;
2329 tx_desc = IGC_TX_DESC(tx_ring, 0);
2332 /* issue prefetch for next Tx descriptor */
2335 /* update budget accounting */
2337 } while (likely(budget));
2339 netdev_tx_completed_queue(txring_txq(tx_ring),
2340 total_packets, total_bytes);
2342 i += tx_ring->count;
2343 tx_ring->next_to_clean = i;
2344 u64_stats_update_begin(&tx_ring->tx_syncp);
2345 tx_ring->tx_stats.bytes += total_bytes;
2346 tx_ring->tx_stats.packets += total_packets;
2347 u64_stats_update_end(&tx_ring->tx_syncp);
2348 q_vector->tx.total_bytes += total_bytes;
2349 q_vector->tx.total_packets += total_packets;
2351 if (test_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
2352 struct igc_hw *hw = &adapter->hw;
2354 /* Detect a transmit hang in hardware, this serializes the
2355 * check with the clearing of time_stamp and movement of i
2357 clear_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
2358 if (tx_buffer->next_to_watch &&
2359 time_after(jiffies, tx_buffer->time_stamp +
2360 (adapter->tx_timeout_factor * HZ)) &&
2361 !(rd32(IGC_STATUS) & IGC_STATUS_TXOFF)) {
2362 /* detected Tx unit hang */
2363 netdev_err(tx_ring->netdev,
2364 "Detected Tx Unit Hang\n"
2368 " next_to_use <%x>\n"
2369 " next_to_clean <%x>\n"
2370 "buffer_info[next_to_clean]\n"
2371 " time_stamp <%lx>\n"
2372 " next_to_watch <%p>\n"
2374 " desc.status <%x>\n",
2375 tx_ring->queue_index,
2376 rd32(IGC_TDH(tx_ring->reg_idx)),
2377 readl(tx_ring->tail),
2378 tx_ring->next_to_use,
2379 tx_ring->next_to_clean,
2380 tx_buffer->time_stamp,
2381 tx_buffer->next_to_watch,
2383 tx_buffer->next_to_watch->wb.status);
2384 netif_stop_subqueue(tx_ring->netdev,
2385 tx_ring->queue_index);
2387 /* we are about to reset, no point in enabling stuff */
2392 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
2393 if (unlikely(total_packets &&
2394 netif_carrier_ok(tx_ring->netdev) &&
2395 igc_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
2396 /* Make sure that anybody stopping the queue after this
2397 * sees the new next_to_clean.
2400 if (__netif_subqueue_stopped(tx_ring->netdev,
2401 tx_ring->queue_index) &&
2402 !(test_bit(__IGC_DOWN, &adapter->state))) {
2403 netif_wake_subqueue(tx_ring->netdev,
2404 tx_ring->queue_index);
2406 u64_stats_update_begin(&tx_ring->tx_syncp);
2407 tx_ring->tx_stats.restart_queue++;
2408 u64_stats_update_end(&tx_ring->tx_syncp);
2415 static int igc_find_mac_filter(struct igc_adapter *adapter,
2416 enum igc_mac_filter_type type, const u8 *addr)
2418 struct igc_hw *hw = &adapter->hw;
2419 int max_entries = hw->mac.rar_entry_count;
2423 for (i = 0; i < max_entries; i++) {
2424 ral = rd32(IGC_RAL(i));
2425 rah = rd32(IGC_RAH(i));
2427 if (!(rah & IGC_RAH_AV))
2429 if (!!(rah & IGC_RAH_ASEL_SRC_ADDR) != type)
2431 if ((rah & IGC_RAH_RAH_MASK) !=
2432 le16_to_cpup((__le16 *)(addr + 4)))
2434 if (ral != le32_to_cpup((__le32 *)(addr)))
2443 static int igc_get_avail_mac_filter_slot(struct igc_adapter *adapter)
2445 struct igc_hw *hw = &adapter->hw;
2446 int max_entries = hw->mac.rar_entry_count;
2450 for (i = 0; i < max_entries; i++) {
2451 rah = rd32(IGC_RAH(i));
2453 if (!(rah & IGC_RAH_AV))
2461 * igc_add_mac_filter() - Add MAC address filter
2462 * @adapter: Pointer to adapter where the filter should be added
2463 * @type: MAC address filter type (source or destination)
2464 * @addr: MAC address
2465 * @queue: If non-negative, queue assignment feature is enabled and frames
2466 * matching the filter are enqueued onto 'queue'. Otherwise, queue
2467 * assignment is disabled.
2469 * Return: 0 in case of success, negative errno code otherwise.
2471 static int igc_add_mac_filter(struct igc_adapter *adapter,
2472 enum igc_mac_filter_type type, const u8 *addr,
2475 struct net_device *dev = adapter->netdev;
2478 index = igc_find_mac_filter(adapter, type, addr);
2482 index = igc_get_avail_mac_filter_slot(adapter);
2486 netdev_dbg(dev, "Add MAC address filter: index %d type %s address %pM queue %d\n",
2487 index, type == IGC_MAC_FILTER_TYPE_DST ? "dst" : "src",
2491 igc_set_mac_filter_hw(adapter, index, type, addr, queue);
2496 * igc_del_mac_filter() - Delete MAC address filter
2497 * @adapter: Pointer to adapter where the filter should be deleted from
2498 * @type: MAC address filter type (source or destination)
2499 * @addr: MAC address
2501 static void igc_del_mac_filter(struct igc_adapter *adapter,
2502 enum igc_mac_filter_type type, const u8 *addr)
2504 struct net_device *dev = adapter->netdev;
2507 index = igc_find_mac_filter(adapter, type, addr);
2512 /* If this is the default filter, we don't actually delete it.
2513 * We just reset to its default value i.e. disable queue
2516 netdev_dbg(dev, "Disable default MAC filter queue assignment");
2518 igc_set_mac_filter_hw(adapter, 0, type, addr, -1);
2520 netdev_dbg(dev, "Delete MAC address filter: index %d type %s address %pM\n",
2522 type == IGC_MAC_FILTER_TYPE_DST ? "dst" : "src",
2525 igc_clear_mac_filter_hw(adapter, index);
2530 * igc_add_vlan_prio_filter() - Add VLAN priority filter
2531 * @adapter: Pointer to adapter where the filter should be added
2532 * @prio: VLAN priority value
2533 * @queue: Queue number which matching frames are assigned to
2535 * Return: 0 in case of success, negative errno code otherwise.
2537 static int igc_add_vlan_prio_filter(struct igc_adapter *adapter, int prio,
2540 struct net_device *dev = adapter->netdev;
2541 struct igc_hw *hw = &adapter->hw;
2544 vlanpqf = rd32(IGC_VLANPQF);
2546 if (vlanpqf & IGC_VLANPQF_VALID(prio)) {
2547 netdev_dbg(dev, "VLAN priority filter already in use\n");
2551 vlanpqf |= IGC_VLANPQF_QSEL(prio, queue);
2552 vlanpqf |= IGC_VLANPQF_VALID(prio);
2554 wr32(IGC_VLANPQF, vlanpqf);
2556 netdev_dbg(dev, "Add VLAN priority filter: prio %d queue %d\n",
2562 * igc_del_vlan_prio_filter() - Delete VLAN priority filter
2563 * @adapter: Pointer to adapter where the filter should be deleted from
2564 * @prio: VLAN priority value
2566 static void igc_del_vlan_prio_filter(struct igc_adapter *adapter, int prio)
2568 struct igc_hw *hw = &adapter->hw;
2571 vlanpqf = rd32(IGC_VLANPQF);
2573 vlanpqf &= ~IGC_VLANPQF_VALID(prio);
2574 vlanpqf &= ~IGC_VLANPQF_QSEL(prio, IGC_VLANPQF_QUEUE_MASK);
2576 wr32(IGC_VLANPQF, vlanpqf);
2578 netdev_dbg(adapter->netdev, "Delete VLAN priority filter: prio %d\n",
2582 static int igc_get_avail_etype_filter_slot(struct igc_adapter *adapter)
2584 struct igc_hw *hw = &adapter->hw;
2587 for (i = 0; i < MAX_ETYPE_FILTER; i++) {
2588 u32 etqf = rd32(IGC_ETQF(i));
2590 if (!(etqf & IGC_ETQF_FILTER_ENABLE))
2598 * igc_add_etype_filter() - Add ethertype filter
2599 * @adapter: Pointer to adapter where the filter should be added
2600 * @etype: Ethertype value
2601 * @queue: If non-negative, queue assignment feature is enabled and frames
2602 * matching the filter are enqueued onto 'queue'. Otherwise, queue
2603 * assignment is disabled.
2605 * Return: 0 in case of success, negative errno code otherwise.
2607 static int igc_add_etype_filter(struct igc_adapter *adapter, u16 etype,
2610 struct igc_hw *hw = &adapter->hw;
2614 index = igc_get_avail_etype_filter_slot(adapter);
2618 etqf = rd32(IGC_ETQF(index));
2620 etqf &= ~IGC_ETQF_ETYPE_MASK;
2624 etqf &= ~IGC_ETQF_QUEUE_MASK;
2625 etqf |= (queue << IGC_ETQF_QUEUE_SHIFT);
2626 etqf |= IGC_ETQF_QUEUE_ENABLE;
2629 etqf |= IGC_ETQF_FILTER_ENABLE;
2631 wr32(IGC_ETQF(index), etqf);
2633 netdev_dbg(adapter->netdev, "Add ethertype filter: etype %04x queue %d\n",
2638 static int igc_find_etype_filter(struct igc_adapter *adapter, u16 etype)
2640 struct igc_hw *hw = &adapter->hw;
2643 for (i = 0; i < MAX_ETYPE_FILTER; i++) {
2644 u32 etqf = rd32(IGC_ETQF(i));
2646 if ((etqf & IGC_ETQF_ETYPE_MASK) == etype)
2654 * igc_del_etype_filter() - Delete ethertype filter
2655 * @adapter: Pointer to adapter where the filter should be deleted from
2656 * @etype: Ethertype value
2658 static void igc_del_etype_filter(struct igc_adapter *adapter, u16 etype)
2660 struct igc_hw *hw = &adapter->hw;
2663 index = igc_find_etype_filter(adapter, etype);
2667 wr32(IGC_ETQF(index), 0);
2669 netdev_dbg(adapter->netdev, "Delete ethertype filter: etype %04x\n",
2673 static int igc_enable_nfc_rule(struct igc_adapter *adapter,
2674 const struct igc_nfc_rule *rule)
2678 if (rule->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE) {
2679 err = igc_add_etype_filter(adapter, rule->filter.etype,
2685 if (rule->filter.match_flags & IGC_FILTER_FLAG_SRC_MAC_ADDR) {
2686 err = igc_add_mac_filter(adapter, IGC_MAC_FILTER_TYPE_SRC,
2687 rule->filter.src_addr, rule->action);
2692 if (rule->filter.match_flags & IGC_FILTER_FLAG_DST_MAC_ADDR) {
2693 err = igc_add_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST,
2694 rule->filter.dst_addr, rule->action);
2699 if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI) {
2700 int prio = (rule->filter.vlan_tci & VLAN_PRIO_MASK) >>
2703 err = igc_add_vlan_prio_filter(adapter, prio, rule->action);
2711 static void igc_disable_nfc_rule(struct igc_adapter *adapter,
2712 const struct igc_nfc_rule *rule)
2714 if (rule->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE)
2715 igc_del_etype_filter(adapter, rule->filter.etype);
2717 if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI) {
2718 int prio = (rule->filter.vlan_tci & VLAN_PRIO_MASK) >>
2721 igc_del_vlan_prio_filter(adapter, prio);
2724 if (rule->filter.match_flags & IGC_FILTER_FLAG_SRC_MAC_ADDR)
2725 igc_del_mac_filter(adapter, IGC_MAC_FILTER_TYPE_SRC,
2726 rule->filter.src_addr);
2728 if (rule->filter.match_flags & IGC_FILTER_FLAG_DST_MAC_ADDR)
2729 igc_del_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST,
2730 rule->filter.dst_addr);
2734 * igc_get_nfc_rule() - Get NFC rule
2735 * @adapter: Pointer to adapter
2736 * @location: Rule location
2738 * Context: Expects adapter->nfc_rule_lock to be held by caller.
2740 * Return: Pointer to NFC rule at @location. If not found, NULL.
2742 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter,
2745 struct igc_nfc_rule *rule;
2747 list_for_each_entry(rule, &adapter->nfc_rule_list, list) {
2748 if (rule->location == location)
2750 if (rule->location > location)
2758 * igc_del_nfc_rule() - Delete NFC rule
2759 * @adapter: Pointer to adapter
2760 * @rule: Pointer to rule to be deleted
2762 * Disable NFC rule in hardware and delete it from adapter.
2764 * Context: Expects adapter->nfc_rule_lock to be held by caller.
2766 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule)
2768 igc_disable_nfc_rule(adapter, rule);
2770 list_del(&rule->list);
2771 adapter->nfc_rule_count--;
2776 static void igc_flush_nfc_rules(struct igc_adapter *adapter)
2778 struct igc_nfc_rule *rule, *tmp;
2780 mutex_lock(&adapter->nfc_rule_lock);
2782 list_for_each_entry_safe(rule, tmp, &adapter->nfc_rule_list, list)
2783 igc_del_nfc_rule(adapter, rule);
2785 mutex_unlock(&adapter->nfc_rule_lock);
2789 * igc_add_nfc_rule() - Add NFC rule
2790 * @adapter: Pointer to adapter
2791 * @rule: Pointer to rule to be added
2793 * Enable NFC rule in hardware and add it to adapter.
2795 * Context: Expects adapter->nfc_rule_lock to be held by caller.
2797 * Return: 0 on success, negative errno on failure.
2799 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule)
2801 struct igc_nfc_rule *pred, *cur;
2804 err = igc_enable_nfc_rule(adapter, rule);
2809 list_for_each_entry(cur, &adapter->nfc_rule_list, list) {
2810 if (cur->location >= rule->location)
2815 list_add(&rule->list, pred ? &pred->list : &adapter->nfc_rule_list);
2816 adapter->nfc_rule_count++;
2820 static void igc_restore_nfc_rules(struct igc_adapter *adapter)
2822 struct igc_nfc_rule *rule;
2824 mutex_lock(&adapter->nfc_rule_lock);
2826 list_for_each_entry_reverse(rule, &adapter->nfc_rule_list, list)
2827 igc_enable_nfc_rule(adapter, rule);
2829 mutex_unlock(&adapter->nfc_rule_lock);
2832 static int igc_uc_sync(struct net_device *netdev, const unsigned char *addr)
2834 struct igc_adapter *adapter = netdev_priv(netdev);
2836 return igc_add_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST, addr, -1);
2839 static int igc_uc_unsync(struct net_device *netdev, const unsigned char *addr)
2841 struct igc_adapter *adapter = netdev_priv(netdev);
2843 igc_del_mac_filter(adapter, IGC_MAC_FILTER_TYPE_DST, addr);
2848 * igc_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
2849 * @netdev: network interface device structure
2851 * The set_rx_mode entry point is called whenever the unicast or multicast
2852 * address lists or the network interface flags are updated. This routine is
2853 * responsible for configuring the hardware for proper unicast, multicast,
2854 * promiscuous mode, and all-multi behavior.
2856 static void igc_set_rx_mode(struct net_device *netdev)
2858 struct igc_adapter *adapter = netdev_priv(netdev);
2859 struct igc_hw *hw = &adapter->hw;
2860 u32 rctl = 0, rlpml = MAX_JUMBO_FRAME_SIZE;
2863 /* Check for Promiscuous and All Multicast modes */
2864 if (netdev->flags & IFF_PROMISC) {
2865 rctl |= IGC_RCTL_UPE | IGC_RCTL_MPE;
2867 if (netdev->flags & IFF_ALLMULTI) {
2868 rctl |= IGC_RCTL_MPE;
2870 /* Write addresses to the MTA, if the attempt fails
2871 * then we should just turn on promiscuous mode so
2872 * that we can at least receive multicast traffic
2874 count = igc_write_mc_addr_list(netdev);
2876 rctl |= IGC_RCTL_MPE;
2880 /* Write addresses to available RAR registers, if there is not
2881 * sufficient space to store all the addresses then enable
2882 * unicast promiscuous mode
2884 if (__dev_uc_sync(netdev, igc_uc_sync, igc_uc_unsync))
2885 rctl |= IGC_RCTL_UPE;
2887 /* update state of unicast and multicast */
2888 rctl |= rd32(IGC_RCTL) & ~(IGC_RCTL_UPE | IGC_RCTL_MPE);
2889 wr32(IGC_RCTL, rctl);
2891 #if (PAGE_SIZE < 8192)
2892 if (adapter->max_frame_size <= IGC_MAX_FRAME_BUILD_SKB)
2893 rlpml = IGC_MAX_FRAME_BUILD_SKB;
2895 wr32(IGC_RLPML, rlpml);
2899 * igc_configure - configure the hardware for RX and TX
2900 * @adapter: private board structure
2902 static void igc_configure(struct igc_adapter *adapter)
2904 struct net_device *netdev = adapter->netdev;
2907 igc_get_hw_control(adapter);
2908 igc_set_rx_mode(netdev);
2910 igc_setup_tctl(adapter);
2911 igc_setup_mrqc(adapter);
2912 igc_setup_rctl(adapter);
2914 igc_set_default_mac_filter(adapter);
2915 igc_restore_nfc_rules(adapter);
2917 igc_configure_tx(adapter);
2918 igc_configure_rx(adapter);
2920 igc_rx_fifo_flush_base(&adapter->hw);
2922 /* call igc_desc_unused which always leaves
2923 * at least 1 descriptor unused to make sure
2924 * next_to_use != next_to_clean
2926 for (i = 0; i < adapter->num_rx_queues; i++) {
2927 struct igc_ring *ring = adapter->rx_ring[i];
2929 igc_alloc_rx_buffers(ring, igc_desc_unused(ring));
2934 * igc_write_ivar - configure ivar for given MSI-X vector
2935 * @hw: pointer to the HW structure
2936 * @msix_vector: vector number we are allocating to a given ring
2937 * @index: row index of IVAR register to write within IVAR table
2938 * @offset: column offset of in IVAR, should be multiple of 8
2940 * The IVAR table consists of 2 columns,
2941 * each containing an cause allocation for an Rx and Tx ring, and a
2942 * variable number of rows depending on the number of queues supported.
2944 static void igc_write_ivar(struct igc_hw *hw, int msix_vector,
2945 int index, int offset)
2947 u32 ivar = array_rd32(IGC_IVAR0, index);
2949 /* clear any bits that are currently set */
2950 ivar &= ~((u32)0xFF << offset);
2952 /* write vector and valid bit */
2953 ivar |= (msix_vector | IGC_IVAR_VALID) << offset;
2955 array_wr32(IGC_IVAR0, index, ivar);
2958 static void igc_assign_vector(struct igc_q_vector *q_vector, int msix_vector)
2960 struct igc_adapter *adapter = q_vector->adapter;
2961 struct igc_hw *hw = &adapter->hw;
2962 int rx_queue = IGC_N0_QUEUE;
2963 int tx_queue = IGC_N0_QUEUE;
2965 if (q_vector->rx.ring)
2966 rx_queue = q_vector->rx.ring->reg_idx;
2967 if (q_vector->tx.ring)
2968 tx_queue = q_vector->tx.ring->reg_idx;
2970 switch (hw->mac.type) {
2972 if (rx_queue > IGC_N0_QUEUE)
2973 igc_write_ivar(hw, msix_vector,
2975 (rx_queue & 0x1) << 4);
2976 if (tx_queue > IGC_N0_QUEUE)
2977 igc_write_ivar(hw, msix_vector,
2979 ((tx_queue & 0x1) << 4) + 8);
2980 q_vector->eims_value = BIT(msix_vector);
2983 WARN_ONCE(hw->mac.type != igc_i225, "Wrong MAC type\n");
2987 /* add q_vector eims value to global eims_enable_mask */
2988 adapter->eims_enable_mask |= q_vector->eims_value;
2990 /* configure q_vector to set itr on first interrupt */
2991 q_vector->set_itr = 1;
2995 * igc_configure_msix - Configure MSI-X hardware
2996 * @adapter: Pointer to adapter structure
2998 * igc_configure_msix sets up the hardware to properly
2999 * generate MSI-X interrupts.
3001 static void igc_configure_msix(struct igc_adapter *adapter)
3003 struct igc_hw *hw = &adapter->hw;
3007 adapter->eims_enable_mask = 0;
3009 /* set vector for other causes, i.e. link changes */
3010 switch (hw->mac.type) {
3012 /* Turn on MSI-X capability first, or our settings
3013 * won't stick. And it will take days to debug.
3015 wr32(IGC_GPIE, IGC_GPIE_MSIX_MODE |
3016 IGC_GPIE_PBA | IGC_GPIE_EIAME |
3019 /* enable msix_other interrupt */
3020 adapter->eims_other = BIT(vector);
3021 tmp = (vector++ | IGC_IVAR_VALID) << 8;
3023 wr32(IGC_IVAR_MISC, tmp);
3026 /* do nothing, since nothing else supports MSI-X */
3028 } /* switch (hw->mac.type) */
3030 adapter->eims_enable_mask |= adapter->eims_other;
3032 for (i = 0; i < adapter->num_q_vectors; i++)
3033 igc_assign_vector(adapter->q_vector[i], vector++);
3039 * igc_irq_enable - Enable default interrupt generation settings
3040 * @adapter: board private structure
3042 static void igc_irq_enable(struct igc_adapter *adapter)
3044 struct igc_hw *hw = &adapter->hw;
3046 if (adapter->msix_entries) {
3047 u32 ims = IGC_IMS_LSC | IGC_IMS_DOUTSYNC | IGC_IMS_DRSTA;
3048 u32 regval = rd32(IGC_EIAC);
3050 wr32(IGC_EIAC, regval | adapter->eims_enable_mask);
3051 regval = rd32(IGC_EIAM);
3052 wr32(IGC_EIAM, regval | adapter->eims_enable_mask);
3053 wr32(IGC_EIMS, adapter->eims_enable_mask);
3056 wr32(IGC_IMS, IMS_ENABLE_MASK | IGC_IMS_DRSTA);
3057 wr32(IGC_IAM, IMS_ENABLE_MASK | IGC_IMS_DRSTA);
3062 * igc_irq_disable - Mask off interrupt generation on the NIC
3063 * @adapter: board private structure
3065 static void igc_irq_disable(struct igc_adapter *adapter)
3067 struct igc_hw *hw = &adapter->hw;
3069 if (adapter->msix_entries) {
3070 u32 regval = rd32(IGC_EIAM);
3072 wr32(IGC_EIAM, regval & ~adapter->eims_enable_mask);
3073 wr32(IGC_EIMC, adapter->eims_enable_mask);
3074 regval = rd32(IGC_EIAC);
3075 wr32(IGC_EIAC, regval & ~adapter->eims_enable_mask);
3082 if (adapter->msix_entries) {
3085 synchronize_irq(adapter->msix_entries[vector++].vector);
3087 for (i = 0; i < adapter->num_q_vectors; i++)
3088 synchronize_irq(adapter->msix_entries[vector++].vector);
3090 synchronize_irq(adapter->pdev->irq);
3094 void igc_set_flag_queue_pairs(struct igc_adapter *adapter,
3095 const u32 max_rss_queues)
3097 /* Determine if we need to pair queues. */
3098 /* If rss_queues > half of max_rss_queues, pair the queues in
3099 * order to conserve interrupts due to limited supply.
3101 if (adapter->rss_queues > (max_rss_queues / 2))
3102 adapter->flags |= IGC_FLAG_QUEUE_PAIRS;
3104 adapter->flags &= ~IGC_FLAG_QUEUE_PAIRS;
3107 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter)
3109 return IGC_MAX_RX_QUEUES;
3112 static void igc_init_queue_configuration(struct igc_adapter *adapter)
3116 max_rss_queues = igc_get_max_rss_queues(adapter);
3117 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
3119 igc_set_flag_queue_pairs(adapter, max_rss_queues);
3123 * igc_reset_q_vector - Reset config for interrupt vector
3124 * @adapter: board private structure to initialize
3125 * @v_idx: Index of vector to be reset
3127 * If NAPI is enabled it will delete any references to the
3128 * NAPI struct. This is preparation for igc_free_q_vector.
3130 static void igc_reset_q_vector(struct igc_adapter *adapter, int v_idx)
3132 struct igc_q_vector *q_vector = adapter->q_vector[v_idx];
3134 /* if we're coming from igc_set_interrupt_capability, the vectors are
3140 if (q_vector->tx.ring)
3141 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
3143 if (q_vector->rx.ring)
3144 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
3146 netif_napi_del(&q_vector->napi);
3150 * igc_free_q_vector - Free memory allocated for specific interrupt vector
3151 * @adapter: board private structure to initialize
3152 * @v_idx: Index of vector to be freed
3154 * This function frees the memory allocated to the q_vector.
3156 static void igc_free_q_vector(struct igc_adapter *adapter, int v_idx)
3158 struct igc_q_vector *q_vector = adapter->q_vector[v_idx];
3160 adapter->q_vector[v_idx] = NULL;
3162 /* igc_get_stats64() might access the rings on this vector,
3163 * we must wait a grace period before freeing it.
3166 kfree_rcu(q_vector, rcu);
3170 * igc_free_q_vectors - Free memory allocated for interrupt vectors
3171 * @adapter: board private structure to initialize
3173 * This function frees the memory allocated to the q_vectors. In addition if
3174 * NAPI is enabled it will delete any references to the NAPI struct prior
3175 * to freeing the q_vector.
3177 static void igc_free_q_vectors(struct igc_adapter *adapter)
3179 int v_idx = adapter->num_q_vectors;
3181 adapter->num_tx_queues = 0;
3182 adapter->num_rx_queues = 0;
3183 adapter->num_q_vectors = 0;
3186 igc_reset_q_vector(adapter, v_idx);
3187 igc_free_q_vector(adapter, v_idx);
3192 * igc_update_itr - update the dynamic ITR value based on statistics
3193 * @q_vector: pointer to q_vector
3194 * @ring_container: ring info to update the itr for
3196 * Stores a new ITR value based on packets and byte
3197 * counts during the last interrupt. The advantage of per interrupt
3198 * computation is faster updates and more accurate ITR for the current
3199 * traffic pattern. Constants in this function were computed
3200 * based on theoretical maximum wire speed and thresholds were set based
3201 * on testing data as well as attempting to minimize response time
3202 * while increasing bulk throughput.
3203 * NOTE: These calculations are only valid when operating in a single-
3204 * queue environment.
3206 static void igc_update_itr(struct igc_q_vector *q_vector,
3207 struct igc_ring_container *ring_container)
3209 unsigned int packets = ring_container->total_packets;
3210 unsigned int bytes = ring_container->total_bytes;
3211 u8 itrval = ring_container->itr;
3213 /* no packets, exit with status unchanged */
3218 case lowest_latency:
3219 /* handle TSO and jumbo frames */
3220 if (bytes / packets > 8000)
3221 itrval = bulk_latency;
3222 else if ((packets < 5) && (bytes > 512))
3223 itrval = low_latency;
3225 case low_latency: /* 50 usec aka 20000 ints/s */
3226 if (bytes > 10000) {
3227 /* this if handles the TSO accounting */
3228 if (bytes / packets > 8000)
3229 itrval = bulk_latency;
3230 else if ((packets < 10) || ((bytes / packets) > 1200))
3231 itrval = bulk_latency;
3232 else if ((packets > 35))
3233 itrval = lowest_latency;
3234 } else if (bytes / packets > 2000) {
3235 itrval = bulk_latency;
3236 } else if (packets <= 2 && bytes < 512) {
3237 itrval = lowest_latency;
3240 case bulk_latency: /* 250 usec aka 4000 ints/s */
3241 if (bytes > 25000) {
3243 itrval = low_latency;
3244 } else if (bytes < 1500) {
3245 itrval = low_latency;
3250 /* clear work counters since we have the values we need */
3251 ring_container->total_bytes = 0;
3252 ring_container->total_packets = 0;
3254 /* write updated itr to ring container */
3255 ring_container->itr = itrval;
3258 static void igc_set_itr(struct igc_q_vector *q_vector)
3260 struct igc_adapter *adapter = q_vector->adapter;
3261 u32 new_itr = q_vector->itr_val;
3264 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3265 switch (adapter->link_speed) {
3269 new_itr = IGC_4K_ITR;
3275 igc_update_itr(q_vector, &q_vector->tx);
3276 igc_update_itr(q_vector, &q_vector->rx);
3278 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
3280 /* conservative mode (itr 3) eliminates the lowest_latency setting */
3281 if (current_itr == lowest_latency &&
3282 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3283 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
3284 current_itr = low_latency;
3286 switch (current_itr) {
3287 /* counts and packets in update_itr are dependent on these numbers */
3288 case lowest_latency:
3289 new_itr = IGC_70K_ITR; /* 70,000 ints/sec */
3292 new_itr = IGC_20K_ITR; /* 20,000 ints/sec */
3295 new_itr = IGC_4K_ITR; /* 4,000 ints/sec */
3302 if (new_itr != q_vector->itr_val) {
3303 /* this attempts to bias the interrupt rate towards Bulk
3304 * by adding intermediate steps when interrupt rate is
3307 new_itr = new_itr > q_vector->itr_val ?
3308 max((new_itr * q_vector->itr_val) /
3309 (new_itr + (q_vector->itr_val >> 2)),
3311 /* Don't write the value here; it resets the adapter's
3312 * internal timer, and causes us to delay far longer than
3313 * we should between interrupts. Instead, we write the ITR
3314 * value at the beginning of the next interrupt so the timing
3315 * ends up being correct.
3317 q_vector->itr_val = new_itr;
3318 q_vector->set_itr = 1;
3322 static void igc_reset_interrupt_capability(struct igc_adapter *adapter)
3324 int v_idx = adapter->num_q_vectors;
3326 if (adapter->msix_entries) {
3327 pci_disable_msix(adapter->pdev);
3328 kfree(adapter->msix_entries);
3329 adapter->msix_entries = NULL;
3330 } else if (adapter->flags & IGC_FLAG_HAS_MSI) {
3331 pci_disable_msi(adapter->pdev);
3335 igc_reset_q_vector(adapter, v_idx);
3339 * igc_set_interrupt_capability - set MSI or MSI-X if supported
3340 * @adapter: Pointer to adapter structure
3341 * @msix: boolean value for MSI-X capability
3343 * Attempt to configure interrupts using the best available
3344 * capabilities of the hardware and kernel.
3346 static void igc_set_interrupt_capability(struct igc_adapter *adapter,
3354 adapter->flags |= IGC_FLAG_HAS_MSIX;
3356 /* Number of supported queues. */
3357 adapter->num_rx_queues = adapter->rss_queues;
3359 adapter->num_tx_queues = adapter->rss_queues;
3361 /* start with one vector for every Rx queue */
3362 numvecs = adapter->num_rx_queues;
3364 /* if Tx handler is separate add 1 for every Tx queue */
3365 if (!(adapter->flags & IGC_FLAG_QUEUE_PAIRS))
3366 numvecs += adapter->num_tx_queues;
3368 /* store the number of vectors reserved for queues */
3369 adapter->num_q_vectors = numvecs;
3371 /* add 1 vector for link status interrupts */
3374 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
3377 if (!adapter->msix_entries)
3380 /* populate entry values */
3381 for (i = 0; i < numvecs; i++)
3382 adapter->msix_entries[i].entry = i;
3384 err = pci_enable_msix_range(adapter->pdev,
3385 adapter->msix_entries,
3391 kfree(adapter->msix_entries);
3392 adapter->msix_entries = NULL;
3394 igc_reset_interrupt_capability(adapter);
3397 adapter->flags &= ~IGC_FLAG_HAS_MSIX;
3399 adapter->rss_queues = 1;
3400 adapter->flags |= IGC_FLAG_QUEUE_PAIRS;
3401 adapter->num_rx_queues = 1;
3402 adapter->num_tx_queues = 1;
3403 adapter->num_q_vectors = 1;
3404 if (!pci_enable_msi(adapter->pdev))
3405 adapter->flags |= IGC_FLAG_HAS_MSI;
3409 * igc_update_ring_itr - update the dynamic ITR value based on packet size
3410 * @q_vector: pointer to q_vector
3412 * Stores a new ITR value based on strictly on packet size. This
3413 * algorithm is less sophisticated than that used in igc_update_itr,
3414 * due to the difficulty of synchronizing statistics across multiple
3415 * receive rings. The divisors and thresholds used by this function
3416 * were determined based on theoretical maximum wire speed and testing
3417 * data, in order to minimize response time while increasing bulk
3419 * NOTE: This function is called only when operating in a multiqueue
3420 * receive environment.
3422 static void igc_update_ring_itr(struct igc_q_vector *q_vector)
3424 struct igc_adapter *adapter = q_vector->adapter;
3425 int new_val = q_vector->itr_val;
3426 int avg_wire_size = 0;
3427 unsigned int packets;
3429 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3430 * ints/sec - ITR timer value of 120 ticks.
3432 switch (adapter->link_speed) {
3435 new_val = IGC_4K_ITR;
3441 packets = q_vector->rx.total_packets;
3443 avg_wire_size = q_vector->rx.total_bytes / packets;
3445 packets = q_vector->tx.total_packets;
3447 avg_wire_size = max_t(u32, avg_wire_size,
3448 q_vector->tx.total_bytes / packets);
3450 /* if avg_wire_size isn't set no work was done */
3454 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3455 avg_wire_size += 24;
3457 /* Don't starve jumbo frames */
3458 avg_wire_size = min(avg_wire_size, 3000);
3460 /* Give a little boost to mid-size frames */
3461 if (avg_wire_size > 300 && avg_wire_size < 1200)
3462 new_val = avg_wire_size / 3;
3464 new_val = avg_wire_size / 2;
3466 /* conservative mode (itr 3) eliminates the lowest_latency setting */
3467 if (new_val < IGC_20K_ITR &&
3468 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3469 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
3470 new_val = IGC_20K_ITR;
3473 if (new_val != q_vector->itr_val) {
3474 q_vector->itr_val = new_val;
3475 q_vector->set_itr = 1;
3478 q_vector->rx.total_bytes = 0;
3479 q_vector->rx.total_packets = 0;
3480 q_vector->tx.total_bytes = 0;
3481 q_vector->tx.total_packets = 0;
3484 static void igc_ring_irq_enable(struct igc_q_vector *q_vector)
3486 struct igc_adapter *adapter = q_vector->adapter;
3487 struct igc_hw *hw = &adapter->hw;
3489 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
3490 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
3491 if (adapter->num_q_vectors == 1)
3492 igc_set_itr(q_vector);
3494 igc_update_ring_itr(q_vector);
3497 if (!test_bit(__IGC_DOWN, &adapter->state)) {
3498 if (adapter->msix_entries)
3499 wr32(IGC_EIMS, q_vector->eims_value);
3501 igc_irq_enable(adapter);
3505 static void igc_add_ring(struct igc_ring *ring,
3506 struct igc_ring_container *head)
3513 * igc_cache_ring_register - Descriptor ring to register mapping
3514 * @adapter: board private structure to initialize
3516 * Once we know the feature-set enabled for the device, we'll cache
3517 * the register offset the descriptor ring is assigned to.
3519 static void igc_cache_ring_register(struct igc_adapter *adapter)
3523 switch (adapter->hw.mac.type) {
3526 for (; i < adapter->num_rx_queues; i++)
3527 adapter->rx_ring[i]->reg_idx = i;
3528 for (; j < adapter->num_tx_queues; j++)
3529 adapter->tx_ring[j]->reg_idx = j;
3535 * igc_poll - NAPI Rx polling callback
3536 * @napi: napi polling structure
3537 * @budget: count of how many packets we should handle
3539 static int igc_poll(struct napi_struct *napi, int budget)
3541 struct igc_q_vector *q_vector = container_of(napi,
3542 struct igc_q_vector,
3544 bool clean_complete = true;
3547 if (q_vector->tx.ring)
3548 clean_complete = igc_clean_tx_irq(q_vector, budget);
3550 if (q_vector->rx.ring) {
3551 int cleaned = igc_clean_rx_irq(q_vector, budget);
3553 work_done += cleaned;
3554 if (cleaned >= budget)
3555 clean_complete = false;
3558 /* If all work not completed, return budget and keep polling */
3559 if (!clean_complete)
3562 /* Exit the polling mode, but don't re-enable interrupts if stack might
3563 * poll us due to busy-polling
3565 if (likely(napi_complete_done(napi, work_done)))
3566 igc_ring_irq_enable(q_vector);
3568 return min(work_done, budget - 1);
3572 * igc_alloc_q_vector - Allocate memory for a single interrupt vector
3573 * @adapter: board private structure to initialize
3574 * @v_count: q_vectors allocated on adapter, used for ring interleaving
3575 * @v_idx: index of vector in adapter struct
3576 * @txr_count: total number of Tx rings to allocate
3577 * @txr_idx: index of first Tx ring to allocate
3578 * @rxr_count: total number of Rx rings to allocate
3579 * @rxr_idx: index of first Rx ring to allocate
3581 * We allocate one q_vector. If allocation fails we return -ENOMEM.
3583 static int igc_alloc_q_vector(struct igc_adapter *adapter,
3584 unsigned int v_count, unsigned int v_idx,
3585 unsigned int txr_count, unsigned int txr_idx,
3586 unsigned int rxr_count, unsigned int rxr_idx)
3588 struct igc_q_vector *q_vector;
3589 struct igc_ring *ring;
3592 /* igc only supports 1 Tx and/or 1 Rx queue per vector */
3593 if (txr_count > 1 || rxr_count > 1)
3596 ring_count = txr_count + rxr_count;
3598 /* allocate q_vector and rings */
3599 q_vector = adapter->q_vector[v_idx];
3601 q_vector = kzalloc(struct_size(q_vector, ring, ring_count),
3604 memset(q_vector, 0, struct_size(q_vector, ring, ring_count));
3608 /* initialize NAPI */
3609 netif_napi_add(adapter->netdev, &q_vector->napi,
3612 /* tie q_vector and adapter together */
3613 adapter->q_vector[v_idx] = q_vector;
3614 q_vector->adapter = adapter;
3616 /* initialize work limits */
3617 q_vector->tx.work_limit = adapter->tx_work_limit;
3619 /* initialize ITR configuration */
3620 q_vector->itr_register = adapter->io_addr + IGC_EITR(0);
3621 q_vector->itr_val = IGC_START_ITR;
3623 /* initialize pointer to rings */
3624 ring = q_vector->ring;
3626 /* initialize ITR */
3628 /* rx or rx/tx vector */
3629 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
3630 q_vector->itr_val = adapter->rx_itr_setting;
3632 /* tx only vector */
3633 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
3634 q_vector->itr_val = adapter->tx_itr_setting;
3638 /* assign generic ring traits */
3639 ring->dev = &adapter->pdev->dev;
3640 ring->netdev = adapter->netdev;
3642 /* configure backlink on ring */
3643 ring->q_vector = q_vector;
3645 /* update q_vector Tx values */
3646 igc_add_ring(ring, &q_vector->tx);
3648 /* apply Tx specific ring traits */
3649 ring->count = adapter->tx_ring_count;
3650 ring->queue_index = txr_idx;
3652 /* assign ring to adapter */
3653 adapter->tx_ring[txr_idx] = ring;
3655 /* push pointer to next ring */
3660 /* assign generic ring traits */
3661 ring->dev = &adapter->pdev->dev;
3662 ring->netdev = adapter->netdev;
3664 /* configure backlink on ring */
3665 ring->q_vector = q_vector;
3667 /* update q_vector Rx values */
3668 igc_add_ring(ring, &q_vector->rx);
3670 /* apply Rx specific ring traits */
3671 ring->count = adapter->rx_ring_count;
3672 ring->queue_index = rxr_idx;
3674 /* assign ring to adapter */
3675 adapter->rx_ring[rxr_idx] = ring;
3682 * igc_alloc_q_vectors - Allocate memory for interrupt vectors
3683 * @adapter: board private structure to initialize
3685 * We allocate one q_vector per queue interrupt. If allocation fails we
3688 static int igc_alloc_q_vectors(struct igc_adapter *adapter)
3690 int rxr_remaining = adapter->num_rx_queues;
3691 int txr_remaining = adapter->num_tx_queues;
3692 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
3693 int q_vectors = adapter->num_q_vectors;
3696 if (q_vectors >= (rxr_remaining + txr_remaining)) {
3697 for (; rxr_remaining; v_idx++) {
3698 err = igc_alloc_q_vector(adapter, q_vectors, v_idx,
3704 /* update counts and index */
3710 for (; v_idx < q_vectors; v_idx++) {
3711 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
3712 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
3714 err = igc_alloc_q_vector(adapter, q_vectors, v_idx,
3715 tqpv, txr_idx, rqpv, rxr_idx);
3720 /* update counts and index */
3721 rxr_remaining -= rqpv;
3722 txr_remaining -= tqpv;
3730 adapter->num_tx_queues = 0;
3731 adapter->num_rx_queues = 0;
3732 adapter->num_q_vectors = 0;
3735 igc_free_q_vector(adapter, v_idx);
3741 * igc_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
3742 * @adapter: Pointer to adapter structure
3743 * @msix: boolean for MSI-X capability
3745 * This function initializes the interrupts and allocates all of the queues.
3747 static int igc_init_interrupt_scheme(struct igc_adapter *adapter, bool msix)
3749 struct net_device *dev = adapter->netdev;
3752 igc_set_interrupt_capability(adapter, msix);
3754 err = igc_alloc_q_vectors(adapter);
3756 netdev_err(dev, "Unable to allocate memory for vectors\n");
3757 goto err_alloc_q_vectors;
3760 igc_cache_ring_register(adapter);
3764 err_alloc_q_vectors:
3765 igc_reset_interrupt_capability(adapter);
3770 * igc_sw_init - Initialize general software structures (struct igc_adapter)
3771 * @adapter: board private structure to initialize
3773 * igc_sw_init initializes the Adapter private data structure.
3774 * Fields are initialized based on PCI device information and
3775 * OS network device settings (MTU size).
3777 static int igc_sw_init(struct igc_adapter *adapter)
3779 struct net_device *netdev = adapter->netdev;
3780 struct pci_dev *pdev = adapter->pdev;
3781 struct igc_hw *hw = &adapter->hw;
3783 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
3785 /* set default ring sizes */
3786 adapter->tx_ring_count = IGC_DEFAULT_TXD;
3787 adapter->rx_ring_count = IGC_DEFAULT_RXD;
3789 /* set default ITR values */
3790 adapter->rx_itr_setting = IGC_DEFAULT_ITR;
3791 adapter->tx_itr_setting = IGC_DEFAULT_ITR;
3793 /* set default work limits */
3794 adapter->tx_work_limit = IGC_DEFAULT_TX_WORK;
3796 /* adjust max frame to be at least the size of a standard frame */
3797 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
3799 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
3801 mutex_init(&adapter->nfc_rule_lock);
3802 INIT_LIST_HEAD(&adapter->nfc_rule_list);
3803 adapter->nfc_rule_count = 0;
3805 spin_lock_init(&adapter->stats64_lock);
3806 /* Assume MSI-X interrupts, will be checked during IRQ allocation */
3807 adapter->flags |= IGC_FLAG_HAS_MSIX;
3809 igc_init_queue_configuration(adapter);
3811 /* This call may decrease the number of queues */
3812 if (igc_init_interrupt_scheme(adapter, true)) {
3813 netdev_err(netdev, "Unable to allocate memory for queues\n");
3817 /* Explicitly disable IRQ since the NIC can be in any state. */
3818 igc_irq_disable(adapter);
3820 set_bit(__IGC_DOWN, &adapter->state);
3826 * igc_up - Open the interface and prepare it to handle traffic
3827 * @adapter: board private structure
3829 void igc_up(struct igc_adapter *adapter)
3831 struct igc_hw *hw = &adapter->hw;
3834 /* hardware has been reset, we need to reload some things */
3835 igc_configure(adapter);
3837 clear_bit(__IGC_DOWN, &adapter->state);
3839 for (i = 0; i < adapter->num_q_vectors; i++)
3840 napi_enable(&adapter->q_vector[i]->napi);
3842 if (adapter->msix_entries)
3843 igc_configure_msix(adapter);
3845 igc_assign_vector(adapter->q_vector[0], 0);
3847 /* Clear any pending interrupts. */
3849 igc_irq_enable(adapter);
3851 netif_tx_start_all_queues(adapter->netdev);
3853 /* start the watchdog. */
3854 hw->mac.get_link_status = true;
3855 schedule_work(&adapter->watchdog_task);
3859 * igc_update_stats - Update the board statistics counters
3860 * @adapter: board private structure
3862 void igc_update_stats(struct igc_adapter *adapter)
3864 struct rtnl_link_stats64 *net_stats = &adapter->stats64;
3865 struct pci_dev *pdev = adapter->pdev;
3866 struct igc_hw *hw = &adapter->hw;
3867 u64 _bytes, _packets;
3873 /* Prevent stats update while adapter is being reset, or if the pci
3874 * connection is down.
3876 if (adapter->link_speed == 0)
3878 if (pci_channel_offline(pdev))
3885 for (i = 0; i < adapter->num_rx_queues; i++) {
3886 struct igc_ring *ring = adapter->rx_ring[i];
3887 u32 rqdpc = rd32(IGC_RQDPC(i));
3889 if (hw->mac.type >= igc_i225)
3890 wr32(IGC_RQDPC(i), 0);
3893 ring->rx_stats.drops += rqdpc;
3894 net_stats->rx_fifo_errors += rqdpc;
3898 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
3899 _bytes = ring->rx_stats.bytes;
3900 _packets = ring->rx_stats.packets;
3901 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
3903 packets += _packets;
3906 net_stats->rx_bytes = bytes;
3907 net_stats->rx_packets = packets;
3911 for (i = 0; i < adapter->num_tx_queues; i++) {
3912 struct igc_ring *ring = adapter->tx_ring[i];
3915 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
3916 _bytes = ring->tx_stats.bytes;
3917 _packets = ring->tx_stats.packets;
3918 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
3920 packets += _packets;
3922 net_stats->tx_bytes = bytes;
3923 net_stats->tx_packets = packets;
3926 /* read stats registers */
3927 adapter->stats.crcerrs += rd32(IGC_CRCERRS);
3928 adapter->stats.gprc += rd32(IGC_GPRC);
3929 adapter->stats.gorc += rd32(IGC_GORCL);
3930 rd32(IGC_GORCH); /* clear GORCL */
3931 adapter->stats.bprc += rd32(IGC_BPRC);
3932 adapter->stats.mprc += rd32(IGC_MPRC);
3933 adapter->stats.roc += rd32(IGC_ROC);
3935 adapter->stats.prc64 += rd32(IGC_PRC64);
3936 adapter->stats.prc127 += rd32(IGC_PRC127);
3937 adapter->stats.prc255 += rd32(IGC_PRC255);
3938 adapter->stats.prc511 += rd32(IGC_PRC511);
3939 adapter->stats.prc1023 += rd32(IGC_PRC1023);
3940 adapter->stats.prc1522 += rd32(IGC_PRC1522);
3941 adapter->stats.tlpic += rd32(IGC_TLPIC);
3942 adapter->stats.rlpic += rd32(IGC_RLPIC);
3943 adapter->stats.hgptc += rd32(IGC_HGPTC);
3945 mpc = rd32(IGC_MPC);
3946 adapter->stats.mpc += mpc;
3947 net_stats->rx_fifo_errors += mpc;
3948 adapter->stats.scc += rd32(IGC_SCC);
3949 adapter->stats.ecol += rd32(IGC_ECOL);
3950 adapter->stats.mcc += rd32(IGC_MCC);
3951 adapter->stats.latecol += rd32(IGC_LATECOL);
3952 adapter->stats.dc += rd32(IGC_DC);
3953 adapter->stats.rlec += rd32(IGC_RLEC);
3954 adapter->stats.xonrxc += rd32(IGC_XONRXC);
3955 adapter->stats.xontxc += rd32(IGC_XONTXC);
3956 adapter->stats.xoffrxc += rd32(IGC_XOFFRXC);
3957 adapter->stats.xofftxc += rd32(IGC_XOFFTXC);
3958 adapter->stats.fcruc += rd32(IGC_FCRUC);
3959 adapter->stats.gptc += rd32(IGC_GPTC);
3960 adapter->stats.gotc += rd32(IGC_GOTCL);
3961 rd32(IGC_GOTCH); /* clear GOTCL */
3962 adapter->stats.rnbc += rd32(IGC_RNBC);
3963 adapter->stats.ruc += rd32(IGC_RUC);
3964 adapter->stats.rfc += rd32(IGC_RFC);
3965 adapter->stats.rjc += rd32(IGC_RJC);
3966 adapter->stats.tor += rd32(IGC_TORH);
3967 adapter->stats.tot += rd32(IGC_TOTH);
3968 adapter->stats.tpr += rd32(IGC_TPR);
3970 adapter->stats.ptc64 += rd32(IGC_PTC64);
3971 adapter->stats.ptc127 += rd32(IGC_PTC127);
3972 adapter->stats.ptc255 += rd32(IGC_PTC255);
3973 adapter->stats.ptc511 += rd32(IGC_PTC511);
3974 adapter->stats.ptc1023 += rd32(IGC_PTC1023);
3975 adapter->stats.ptc1522 += rd32(IGC_PTC1522);
3977 adapter->stats.mptc += rd32(IGC_MPTC);
3978 adapter->stats.bptc += rd32(IGC_BPTC);
3980 adapter->stats.tpt += rd32(IGC_TPT);
3981 adapter->stats.colc += rd32(IGC_COLC);
3982 adapter->stats.colc += rd32(IGC_RERC);
3984 adapter->stats.algnerrc += rd32(IGC_ALGNERRC);
3986 adapter->stats.tsctc += rd32(IGC_TSCTC);
3988 adapter->stats.iac += rd32(IGC_IAC);
3990 /* Fill out the OS statistics structure */
3991 net_stats->multicast = adapter->stats.mprc;
3992 net_stats->collisions = adapter->stats.colc;
3996 /* RLEC on some newer hardware can be incorrect so build
3997 * our own version based on RUC and ROC
3999 net_stats->rx_errors = adapter->stats.rxerrc +
4000 adapter->stats.crcerrs + adapter->stats.algnerrc +
4001 adapter->stats.ruc + adapter->stats.roc +
4002 adapter->stats.cexterr;
4003 net_stats->rx_length_errors = adapter->stats.ruc +
4005 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4006 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4007 net_stats->rx_missed_errors = adapter->stats.mpc;
4010 net_stats->tx_errors = adapter->stats.ecol +
4011 adapter->stats.latecol;
4012 net_stats->tx_aborted_errors = adapter->stats.ecol;
4013 net_stats->tx_window_errors = adapter->stats.latecol;
4014 net_stats->tx_carrier_errors = adapter->stats.tncrs;
4016 /* Tx Dropped needs to be maintained elsewhere */
4018 /* Management Stats */
4019 adapter->stats.mgptc += rd32(IGC_MGTPTC);
4020 adapter->stats.mgprc += rd32(IGC_MGTPRC);
4021 adapter->stats.mgpdc += rd32(IGC_MGTPDC);
4025 * igc_down - Close the interface
4026 * @adapter: board private structure
4028 void igc_down(struct igc_adapter *adapter)
4030 struct net_device *netdev = adapter->netdev;
4031 struct igc_hw *hw = &adapter->hw;
4035 set_bit(__IGC_DOWN, &adapter->state);
4037 igc_ptp_suspend(adapter);
4039 /* disable receives in the hardware */
4040 rctl = rd32(IGC_RCTL);
4041 wr32(IGC_RCTL, rctl & ~IGC_RCTL_EN);
4042 /* flush and sleep below */
4044 /* set trans_start so we don't get spurious watchdogs during reset */
4045 netif_trans_update(netdev);
4047 netif_carrier_off(netdev);
4048 netif_tx_stop_all_queues(netdev);
4050 /* disable transmits in the hardware */
4051 tctl = rd32(IGC_TCTL);
4052 tctl &= ~IGC_TCTL_EN;
4053 wr32(IGC_TCTL, tctl);
4054 /* flush both disables and wait for them to finish */
4056 usleep_range(10000, 20000);
4058 igc_irq_disable(adapter);
4060 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE;
4062 for (i = 0; i < adapter->num_q_vectors; i++) {
4063 if (adapter->q_vector[i]) {
4064 napi_synchronize(&adapter->q_vector[i]->napi);
4065 napi_disable(&adapter->q_vector[i]->napi);
4069 del_timer_sync(&adapter->watchdog_timer);
4070 del_timer_sync(&adapter->phy_info_timer);
4072 /* record the stats before reset*/
4073 spin_lock(&adapter->stats64_lock);
4074 igc_update_stats(adapter);
4075 spin_unlock(&adapter->stats64_lock);
4077 adapter->link_speed = 0;
4078 adapter->link_duplex = 0;
4080 if (!pci_channel_offline(adapter->pdev))
4083 /* clear VLAN promisc flag so VFTA will be updated if necessary */
4084 adapter->flags &= ~IGC_FLAG_VLAN_PROMISC;
4086 igc_clean_all_tx_rings(adapter);
4087 igc_clean_all_rx_rings(adapter);
4090 void igc_reinit_locked(struct igc_adapter *adapter)
4092 while (test_and_set_bit(__IGC_RESETTING, &adapter->state))
4093 usleep_range(1000, 2000);
4096 clear_bit(__IGC_RESETTING, &adapter->state);
4099 static void igc_reset_task(struct work_struct *work)
4101 struct igc_adapter *adapter;
4103 adapter = container_of(work, struct igc_adapter, reset_task);
4106 /* If we're already down or resetting, just bail */
4107 if (test_bit(__IGC_DOWN, &adapter->state) ||
4108 test_bit(__IGC_RESETTING, &adapter->state)) {
4113 igc_rings_dump(adapter);
4114 igc_regs_dump(adapter);
4115 netdev_err(adapter->netdev, "Reset adapter\n");
4116 igc_reinit_locked(adapter);
4121 * igc_change_mtu - Change the Maximum Transfer Unit
4122 * @netdev: network interface device structure
4123 * @new_mtu: new value for maximum frame size
4125 * Returns 0 on success, negative on failure
4127 static int igc_change_mtu(struct net_device *netdev, int new_mtu)
4129 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4130 struct igc_adapter *adapter = netdev_priv(netdev);
4132 if (igc_xdp_is_enabled(adapter) && new_mtu > ETH_DATA_LEN) {
4133 netdev_dbg(netdev, "Jumbo frames not supported with XDP");
4137 /* adjust max frame to be at least the size of a standard frame */
4138 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
4139 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
4141 while (test_and_set_bit(__IGC_RESETTING, &adapter->state))
4142 usleep_range(1000, 2000);
4144 /* igc_down has a dependency on max_frame_size */
4145 adapter->max_frame_size = max_frame;
4147 if (netif_running(netdev))
4150 netdev_dbg(netdev, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
4151 netdev->mtu = new_mtu;
4153 if (netif_running(netdev))
4158 clear_bit(__IGC_RESETTING, &adapter->state);
4164 * igc_get_stats64 - Get System Network Statistics
4165 * @netdev: network interface device structure
4166 * @stats: rtnl_link_stats64 pointer
4168 * Returns the address of the device statistics structure.
4169 * The statistics are updated here and also from the timer callback.
4171 static void igc_get_stats64(struct net_device *netdev,
4172 struct rtnl_link_stats64 *stats)
4174 struct igc_adapter *adapter = netdev_priv(netdev);
4176 spin_lock(&adapter->stats64_lock);
4177 if (!test_bit(__IGC_RESETTING, &adapter->state))
4178 igc_update_stats(adapter);
4179 memcpy(stats, &adapter->stats64, sizeof(*stats));
4180 spin_unlock(&adapter->stats64_lock);
4183 static netdev_features_t igc_fix_features(struct net_device *netdev,
4184 netdev_features_t features)
4186 /* Since there is no support for separate Rx/Tx vlan accel
4187 * enable/disable make sure Tx flag is always in same state as Rx.
4189 if (features & NETIF_F_HW_VLAN_CTAG_RX)
4190 features |= NETIF_F_HW_VLAN_CTAG_TX;
4192 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
4197 static int igc_set_features(struct net_device *netdev,
4198 netdev_features_t features)
4200 netdev_features_t changed = netdev->features ^ features;
4201 struct igc_adapter *adapter = netdev_priv(netdev);
4203 /* Add VLAN support */
4204 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
4207 if (!(features & NETIF_F_NTUPLE))
4208 igc_flush_nfc_rules(adapter);
4210 netdev->features = features;
4212 if (netif_running(netdev))
4213 igc_reinit_locked(adapter);
4220 static netdev_features_t
4221 igc_features_check(struct sk_buff *skb, struct net_device *dev,
4222 netdev_features_t features)
4224 unsigned int network_hdr_len, mac_hdr_len;
4226 /* Make certain the headers can be described by a context descriptor */
4227 mac_hdr_len = skb_network_header(skb) - skb->data;
4228 if (unlikely(mac_hdr_len > IGC_MAX_MAC_HDR_LEN))
4229 return features & ~(NETIF_F_HW_CSUM |
4231 NETIF_F_HW_VLAN_CTAG_TX |
4235 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
4236 if (unlikely(network_hdr_len > IGC_MAX_NETWORK_HDR_LEN))
4237 return features & ~(NETIF_F_HW_CSUM |
4242 /* We can only support IPv4 TSO in tunnels if we can mangle the
4243 * inner IP ID field, so strip TSO if MANGLEID is not supported.
4245 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
4246 features &= ~NETIF_F_TSO;
4251 static void igc_tsync_interrupt(struct igc_adapter *adapter)
4253 u32 ack, tsauxc, sec, nsec, tsicr;
4254 struct igc_hw *hw = &adapter->hw;
4255 struct ptp_clock_event event;
4256 struct timespec64 ts;
4258 tsicr = rd32(IGC_TSICR);
4261 if (tsicr & IGC_TSICR_SYS_WRAP) {
4262 event.type = PTP_CLOCK_PPS;
4263 if (adapter->ptp_caps.pps)
4264 ptp_clock_event(adapter->ptp_clock, &event);
4265 ack |= IGC_TSICR_SYS_WRAP;
4268 if (tsicr & IGC_TSICR_TXTS) {
4269 /* retrieve hardware timestamp */
4270 schedule_work(&adapter->ptp_tx_work);
4271 ack |= IGC_TSICR_TXTS;
4274 if (tsicr & IGC_TSICR_TT0) {
4275 spin_lock(&adapter->tmreg_lock);
4276 ts = timespec64_add(adapter->perout[0].start,
4277 adapter->perout[0].period);
4278 wr32(IGC_TRGTTIML0, ts.tv_nsec | IGC_TT_IO_TIMER_SEL_SYSTIM0);
4279 wr32(IGC_TRGTTIMH0, (u32)ts.tv_sec);
4280 tsauxc = rd32(IGC_TSAUXC);
4281 tsauxc |= IGC_TSAUXC_EN_TT0;
4282 wr32(IGC_TSAUXC, tsauxc);
4283 adapter->perout[0].start = ts;
4284 spin_unlock(&adapter->tmreg_lock);
4285 ack |= IGC_TSICR_TT0;
4288 if (tsicr & IGC_TSICR_TT1) {
4289 spin_lock(&adapter->tmreg_lock);
4290 ts = timespec64_add(adapter->perout[1].start,
4291 adapter->perout[1].period);
4292 wr32(IGC_TRGTTIML1, ts.tv_nsec | IGC_TT_IO_TIMER_SEL_SYSTIM0);
4293 wr32(IGC_TRGTTIMH1, (u32)ts.tv_sec);
4294 tsauxc = rd32(IGC_TSAUXC);
4295 tsauxc |= IGC_TSAUXC_EN_TT1;
4296 wr32(IGC_TSAUXC, tsauxc);
4297 adapter->perout[1].start = ts;
4298 spin_unlock(&adapter->tmreg_lock);
4299 ack |= IGC_TSICR_TT1;
4302 if (tsicr & IGC_TSICR_AUTT0) {
4303 nsec = rd32(IGC_AUXSTMPL0);
4304 sec = rd32(IGC_AUXSTMPH0);
4305 event.type = PTP_CLOCK_EXTTS;
4307 event.timestamp = sec * NSEC_PER_SEC + nsec;
4308 ptp_clock_event(adapter->ptp_clock, &event);
4309 ack |= IGC_TSICR_AUTT0;
4312 if (tsicr & IGC_TSICR_AUTT1) {
4313 nsec = rd32(IGC_AUXSTMPL1);
4314 sec = rd32(IGC_AUXSTMPH1);
4315 event.type = PTP_CLOCK_EXTTS;
4317 event.timestamp = sec * NSEC_PER_SEC + nsec;
4318 ptp_clock_event(adapter->ptp_clock, &event);
4319 ack |= IGC_TSICR_AUTT1;
4322 /* acknowledge the interrupts */
4323 wr32(IGC_TSICR, ack);
4327 * igc_msix_other - msix other interrupt handler
4328 * @irq: interrupt number
4329 * @data: pointer to a q_vector
4331 static irqreturn_t igc_msix_other(int irq, void *data)
4333 struct igc_adapter *adapter = data;
4334 struct igc_hw *hw = &adapter->hw;
4335 u32 icr = rd32(IGC_ICR);
4337 /* reading ICR causes bit 31 of EICR to be cleared */
4338 if (icr & IGC_ICR_DRSTA)
4339 schedule_work(&adapter->reset_task);
4341 if (icr & IGC_ICR_DOUTSYNC) {
4342 /* HW is reporting DMA is out of sync */
4343 adapter->stats.doosync++;
4346 if (icr & IGC_ICR_LSC) {
4347 hw->mac.get_link_status = true;
4348 /* guard against interrupt when we're going down */
4349 if (!test_bit(__IGC_DOWN, &adapter->state))
4350 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4353 if (icr & IGC_ICR_TS)
4354 igc_tsync_interrupt(adapter);
4356 wr32(IGC_EIMS, adapter->eims_other);
4361 static void igc_write_itr(struct igc_q_vector *q_vector)
4363 u32 itr_val = q_vector->itr_val & IGC_QVECTOR_MASK;
4365 if (!q_vector->set_itr)
4369 itr_val = IGC_ITR_VAL_MASK;
4371 itr_val |= IGC_EITR_CNT_IGNR;
4373 writel(itr_val, q_vector->itr_register);
4374 q_vector->set_itr = 0;
4377 static irqreturn_t igc_msix_ring(int irq, void *data)
4379 struct igc_q_vector *q_vector = data;
4381 /* Write the ITR value calculated from the previous interrupt. */
4382 igc_write_itr(q_vector);
4384 napi_schedule(&q_vector->napi);
4390 * igc_request_msix - Initialize MSI-X interrupts
4391 * @adapter: Pointer to adapter structure
4393 * igc_request_msix allocates MSI-X vectors and requests interrupts from the
4396 static int igc_request_msix(struct igc_adapter *adapter)
4398 int i = 0, err = 0, vector = 0, free_vector = 0;
4399 struct net_device *netdev = adapter->netdev;
4401 err = request_irq(adapter->msix_entries[vector].vector,
4402 &igc_msix_other, 0, netdev->name, adapter);
4406 for (i = 0; i < adapter->num_q_vectors; i++) {
4407 struct igc_q_vector *q_vector = adapter->q_vector[i];
4411 q_vector->itr_register = adapter->io_addr + IGC_EITR(vector);
4413 if (q_vector->rx.ring && q_vector->tx.ring)
4414 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
4415 q_vector->rx.ring->queue_index);
4416 else if (q_vector->tx.ring)
4417 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
4418 q_vector->tx.ring->queue_index);
4419 else if (q_vector->rx.ring)
4420 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
4421 q_vector->rx.ring->queue_index);
4423 sprintf(q_vector->name, "%s-unused", netdev->name);
4425 err = request_irq(adapter->msix_entries[vector].vector,
4426 igc_msix_ring, 0, q_vector->name,
4432 igc_configure_msix(adapter);
4436 /* free already assigned IRQs */
4437 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
4440 for (i = 0; i < vector; i++) {
4441 free_irq(adapter->msix_entries[free_vector++].vector,
4442 adapter->q_vector[i]);
4449 * igc_clear_interrupt_scheme - reset the device to a state of no interrupts
4450 * @adapter: Pointer to adapter structure
4452 * This function resets the device so that it has 0 rx queues, tx queues, and
4453 * MSI-X interrupts allocated.
4455 static void igc_clear_interrupt_scheme(struct igc_adapter *adapter)
4457 igc_free_q_vectors(adapter);
4458 igc_reset_interrupt_capability(adapter);
4461 /* Need to wait a few seconds after link up to get diagnostic information from
4464 static void igc_update_phy_info(struct timer_list *t)
4466 struct igc_adapter *adapter = from_timer(adapter, t, phy_info_timer);
4468 igc_get_phy_info(&adapter->hw);
4472 * igc_has_link - check shared code for link and determine up/down
4473 * @adapter: pointer to driver private info
4475 bool igc_has_link(struct igc_adapter *adapter)
4477 struct igc_hw *hw = &adapter->hw;
4478 bool link_active = false;
4480 /* get_link_status is set on LSC (link status) interrupt or
4481 * rx sequence error interrupt. get_link_status will stay
4482 * false until the igc_check_for_link establishes link
4483 * for copper adapters ONLY
4485 switch (hw->phy.media_type) {
4486 case igc_media_type_copper:
4487 if (!hw->mac.get_link_status)
4489 hw->mac.ops.check_for_link(hw);
4490 link_active = !hw->mac.get_link_status;
4493 case igc_media_type_unknown:
4497 if (hw->mac.type == igc_i225 &&
4498 hw->phy.id == I225_I_PHY_ID) {
4499 if (!netif_carrier_ok(adapter->netdev)) {
4500 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE;
4501 } else if (!(adapter->flags & IGC_FLAG_NEED_LINK_UPDATE)) {
4502 adapter->flags |= IGC_FLAG_NEED_LINK_UPDATE;
4503 adapter->link_check_timeout = jiffies;
4511 * igc_watchdog - Timer Call-back
4512 * @t: timer for the watchdog
4514 static void igc_watchdog(struct timer_list *t)
4516 struct igc_adapter *adapter = from_timer(adapter, t, watchdog_timer);
4517 /* Do the rest outside of interrupt context */
4518 schedule_work(&adapter->watchdog_task);
4521 static void igc_watchdog_task(struct work_struct *work)
4523 struct igc_adapter *adapter = container_of(work,
4526 struct net_device *netdev = adapter->netdev;
4527 struct igc_hw *hw = &adapter->hw;
4528 struct igc_phy_info *phy = &hw->phy;
4529 u16 phy_data, retry_count = 20;
4533 link = igc_has_link(adapter);
4535 if (adapter->flags & IGC_FLAG_NEED_LINK_UPDATE) {
4536 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4537 adapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE;
4543 /* Cancel scheduled suspend requests. */
4544 pm_runtime_resume(netdev->dev.parent);
4546 if (!netif_carrier_ok(netdev)) {
4549 hw->mac.ops.get_speed_and_duplex(hw,
4550 &adapter->link_speed,
4551 &adapter->link_duplex);
4553 ctrl = rd32(IGC_CTRL);
4554 /* Link status message must follow this format */
4556 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4557 adapter->link_speed,
4558 adapter->link_duplex == FULL_DUPLEX ?
4560 (ctrl & IGC_CTRL_TFCE) &&
4561 (ctrl & IGC_CTRL_RFCE) ? "RX/TX" :
4562 (ctrl & IGC_CTRL_RFCE) ? "RX" :
4563 (ctrl & IGC_CTRL_TFCE) ? "TX" : "None");
4565 /* disable EEE if enabled */
4566 if ((adapter->flags & IGC_FLAG_EEE) &&
4567 adapter->link_duplex == HALF_DUPLEX) {
4569 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex\n");
4570 adapter->hw.dev_spec._base.eee_enable = false;
4571 adapter->flags &= ~IGC_FLAG_EEE;
4574 /* check if SmartSpeed worked */
4575 igc_check_downshift(hw);
4576 if (phy->speed_downgraded)
4577 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4579 /* adjust timeout factor according to speed/duplex */
4580 adapter->tx_timeout_factor = 1;
4581 switch (adapter->link_speed) {
4583 adapter->tx_timeout_factor = 14;
4586 /* maybe add some timeout factor ? */
4590 if (adapter->link_speed != SPEED_1000)
4593 /* wait for Remote receiver status OK */
4595 if (!igc_read_phy_reg(hw, PHY_1000T_STATUS,
4597 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&
4601 goto retry_read_status;
4602 } else if (!retry_count) {
4603 netdev_err(netdev, "exceed max 2 second\n");
4606 netdev_err(netdev, "read 1000Base-T Status Reg\n");
4609 netif_carrier_on(netdev);
4611 /* link state has changed, schedule phy info update */
4612 if (!test_bit(__IGC_DOWN, &adapter->state))
4613 mod_timer(&adapter->phy_info_timer,
4614 round_jiffies(jiffies + 2 * HZ));
4617 if (netif_carrier_ok(netdev)) {
4618 adapter->link_speed = 0;
4619 adapter->link_duplex = 0;
4621 /* Links status message must follow this format */
4622 netdev_info(netdev, "NIC Link is Down\n");
4623 netif_carrier_off(netdev);
4625 /* link state has changed, schedule phy info update */
4626 if (!test_bit(__IGC_DOWN, &adapter->state))
4627 mod_timer(&adapter->phy_info_timer,
4628 round_jiffies(jiffies + 2 * HZ));
4630 /* link is down, time to check for alternate media */
4631 if (adapter->flags & IGC_FLAG_MAS_ENABLE) {
4632 if (adapter->flags & IGC_FLAG_MEDIA_RESET) {
4633 schedule_work(&adapter->reset_task);
4634 /* return immediately */
4638 pm_schedule_suspend(netdev->dev.parent,
4641 /* also check for alternate media here */
4642 } else if (!netif_carrier_ok(netdev) &&
4643 (adapter->flags & IGC_FLAG_MAS_ENABLE)) {
4644 if (adapter->flags & IGC_FLAG_MEDIA_RESET) {
4645 schedule_work(&adapter->reset_task);
4646 /* return immediately */
4652 spin_lock(&adapter->stats64_lock);
4653 igc_update_stats(adapter);
4654 spin_unlock(&adapter->stats64_lock);
4656 for (i = 0; i < adapter->num_tx_queues; i++) {
4657 struct igc_ring *tx_ring = adapter->tx_ring[i];
4659 if (!netif_carrier_ok(netdev)) {
4660 /* We've lost link, so the controller stops DMA,
4661 * but we've got queued Tx work that's never going
4662 * to get done, so reset controller to flush Tx.
4663 * (Do the reset outside of interrupt context).
4665 if (igc_desc_unused(tx_ring) + 1 < tx_ring->count) {
4666 adapter->tx_timeout_count++;
4667 schedule_work(&adapter->reset_task);
4668 /* return immediately since reset is imminent */
4673 /* Force detection of hung controller every watchdog period */
4674 set_bit(IGC_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
4677 /* Cause software interrupt to ensure Rx ring is cleaned */
4678 if (adapter->flags & IGC_FLAG_HAS_MSIX) {
4681 for (i = 0; i < adapter->num_q_vectors; i++)
4682 eics |= adapter->q_vector[i]->eims_value;
4683 wr32(IGC_EICS, eics);
4685 wr32(IGC_ICS, IGC_ICS_RXDMT0);
4688 igc_ptp_tx_hang(adapter);
4690 /* Reset the timer */
4691 if (!test_bit(__IGC_DOWN, &adapter->state)) {
4692 if (adapter->flags & IGC_FLAG_NEED_LINK_UPDATE)
4693 mod_timer(&adapter->watchdog_timer,
4694 round_jiffies(jiffies + HZ));
4696 mod_timer(&adapter->watchdog_timer,
4697 round_jiffies(jiffies + 2 * HZ));
4702 * igc_intr_msi - Interrupt Handler
4703 * @irq: interrupt number
4704 * @data: pointer to a network interface device structure
4706 static irqreturn_t igc_intr_msi(int irq, void *data)
4708 struct igc_adapter *adapter = data;
4709 struct igc_q_vector *q_vector = adapter->q_vector[0];
4710 struct igc_hw *hw = &adapter->hw;
4711 /* read ICR disables interrupts using IAM */
4712 u32 icr = rd32(IGC_ICR);
4714 igc_write_itr(q_vector);
4716 if (icr & IGC_ICR_DRSTA)
4717 schedule_work(&adapter->reset_task);
4719 if (icr & IGC_ICR_DOUTSYNC) {
4720 /* HW is reporting DMA is out of sync */
4721 adapter->stats.doosync++;
4724 if (icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) {
4725 hw->mac.get_link_status = true;
4726 if (!test_bit(__IGC_DOWN, &adapter->state))
4727 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4730 napi_schedule(&q_vector->napi);
4736 * igc_intr - Legacy Interrupt Handler
4737 * @irq: interrupt number
4738 * @data: pointer to a network interface device structure
4740 static irqreturn_t igc_intr(int irq, void *data)
4742 struct igc_adapter *adapter = data;
4743 struct igc_q_vector *q_vector = adapter->q_vector[0];
4744 struct igc_hw *hw = &adapter->hw;
4745 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4746 * need for the IMC write
4748 u32 icr = rd32(IGC_ICR);
4750 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4751 * not set, then the adapter didn't send an interrupt
4753 if (!(icr & IGC_ICR_INT_ASSERTED))
4756 igc_write_itr(q_vector);
4758 if (icr & IGC_ICR_DRSTA)
4759 schedule_work(&adapter->reset_task);
4761 if (icr & IGC_ICR_DOUTSYNC) {
4762 /* HW is reporting DMA is out of sync */
4763 adapter->stats.doosync++;
4766 if (icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) {
4767 hw->mac.get_link_status = true;
4768 /* guard against interrupt when we're going down */
4769 if (!test_bit(__IGC_DOWN, &adapter->state))
4770 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4773 napi_schedule(&q_vector->napi);
4778 static void igc_free_irq(struct igc_adapter *adapter)
4780 if (adapter->msix_entries) {
4783 free_irq(adapter->msix_entries[vector++].vector, adapter);
4785 for (i = 0; i < adapter->num_q_vectors; i++)
4786 free_irq(adapter->msix_entries[vector++].vector,
4787 adapter->q_vector[i]);
4789 free_irq(adapter->pdev->irq, adapter);
4794 * igc_request_irq - initialize interrupts
4795 * @adapter: Pointer to adapter structure
4797 * Attempts to configure interrupts using the best available
4798 * capabilities of the hardware and kernel.
4800 static int igc_request_irq(struct igc_adapter *adapter)
4802 struct net_device *netdev = adapter->netdev;
4803 struct pci_dev *pdev = adapter->pdev;
4806 if (adapter->flags & IGC_FLAG_HAS_MSIX) {
4807 err = igc_request_msix(adapter);
4810 /* fall back to MSI */
4811 igc_free_all_tx_resources(adapter);
4812 igc_free_all_rx_resources(adapter);
4814 igc_clear_interrupt_scheme(adapter);
4815 err = igc_init_interrupt_scheme(adapter, false);
4818 igc_setup_all_tx_resources(adapter);
4819 igc_setup_all_rx_resources(adapter);
4820 igc_configure(adapter);
4823 igc_assign_vector(adapter->q_vector[0], 0);
4825 if (adapter->flags & IGC_FLAG_HAS_MSI) {
4826 err = request_irq(pdev->irq, &igc_intr_msi, 0,
4827 netdev->name, adapter);
4831 /* fall back to legacy interrupts */
4832 igc_reset_interrupt_capability(adapter);
4833 adapter->flags &= ~IGC_FLAG_HAS_MSI;
4836 err = request_irq(pdev->irq, &igc_intr, IRQF_SHARED,
4837 netdev->name, adapter);
4840 netdev_err(netdev, "Error %d getting interrupt\n", err);
4847 * __igc_open - Called when a network interface is made active
4848 * @netdev: network interface device structure
4849 * @resuming: boolean indicating if the device is resuming
4851 * Returns 0 on success, negative value on failure
4853 * The open entry point is called when a network interface is made
4854 * active by the system (IFF_UP). At this point all resources needed
4855 * for transmit and receive operations are allocated, the interrupt
4856 * handler is registered with the OS, the watchdog timer is started,
4857 * and the stack is notified that the interface is ready.
4859 static int __igc_open(struct net_device *netdev, bool resuming)
4861 struct igc_adapter *adapter = netdev_priv(netdev);
4862 struct pci_dev *pdev = adapter->pdev;
4863 struct igc_hw *hw = &adapter->hw;
4867 /* disallow open during test */
4869 if (test_bit(__IGC_TESTING, &adapter->state)) {
4875 pm_runtime_get_sync(&pdev->dev);
4877 netif_carrier_off(netdev);
4879 /* allocate transmit descriptors */
4880 err = igc_setup_all_tx_resources(adapter);
4884 /* allocate receive descriptors */
4885 err = igc_setup_all_rx_resources(adapter);
4889 igc_power_up_link(adapter);
4891 igc_configure(adapter);
4893 err = igc_request_irq(adapter);
4897 /* Notify the stack of the actual queue counts. */
4898 err = netif_set_real_num_tx_queues(netdev, adapter->num_tx_queues);
4900 goto err_set_queues;
4902 err = netif_set_real_num_rx_queues(netdev, adapter->num_rx_queues);
4904 goto err_set_queues;
4906 clear_bit(__IGC_DOWN, &adapter->state);
4908 for (i = 0; i < adapter->num_q_vectors; i++)
4909 napi_enable(&adapter->q_vector[i]->napi);
4911 /* Clear any pending interrupts. */
4913 igc_irq_enable(adapter);
4916 pm_runtime_put(&pdev->dev);
4918 netif_tx_start_all_queues(netdev);
4920 /* start the watchdog. */
4921 hw->mac.get_link_status = true;
4922 schedule_work(&adapter->watchdog_task);
4927 igc_free_irq(adapter);
4929 igc_release_hw_control(adapter);
4930 igc_power_down_phy_copper_base(&adapter->hw);
4931 igc_free_all_rx_resources(adapter);
4933 igc_free_all_tx_resources(adapter);
4937 pm_runtime_put(&pdev->dev);
4942 int igc_open(struct net_device *netdev)
4944 return __igc_open(netdev, false);
4948 * __igc_close - Disables a network interface
4949 * @netdev: network interface device structure
4950 * @suspending: boolean indicating the device is suspending
4952 * Returns 0, this is not allowed to fail
4954 * The close entry point is called when an interface is de-activated
4955 * by the OS. The hardware is still under the driver's control, but
4956 * needs to be disabled. A global MAC reset is issued to stop the
4957 * hardware, and all transmit and receive resources are freed.
4959 static int __igc_close(struct net_device *netdev, bool suspending)
4961 struct igc_adapter *adapter = netdev_priv(netdev);
4962 struct pci_dev *pdev = adapter->pdev;
4964 WARN_ON(test_bit(__IGC_RESETTING, &adapter->state));
4967 pm_runtime_get_sync(&pdev->dev);
4971 igc_release_hw_control(adapter);
4973 igc_free_irq(adapter);
4975 igc_free_all_tx_resources(adapter);
4976 igc_free_all_rx_resources(adapter);
4979 pm_runtime_put_sync(&pdev->dev);
4984 int igc_close(struct net_device *netdev)
4986 if (netif_device_present(netdev) || netdev->dismantle)
4987 return __igc_close(netdev, false);
4992 * igc_ioctl - Access the hwtstamp interface
4993 * @netdev: network interface device structure
4994 * @ifr: interface request data
4995 * @cmd: ioctl command
4997 static int igc_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5001 return igc_ptp_get_ts_config(netdev, ifr);
5003 return igc_ptp_set_ts_config(netdev, ifr);
5009 static int igc_save_launchtime_params(struct igc_adapter *adapter, int queue,
5012 struct igc_ring *ring;
5015 if (queue < 0 || queue >= adapter->num_tx_queues)
5018 ring = adapter->tx_ring[queue];
5019 ring->launchtime_enable = enable;
5021 if (adapter->base_time)
5024 adapter->cycle_time = NSEC_PER_SEC;
5026 for (i = 0; i < adapter->num_tx_queues; i++) {
5027 ring = adapter->tx_ring[i];
5028 ring->start_time = 0;
5029 ring->end_time = NSEC_PER_SEC;
5035 static bool is_base_time_past(ktime_t base_time, const struct timespec64 *now)
5037 struct timespec64 b;
5039 b = ktime_to_timespec64(base_time);
5041 return timespec64_compare(now, &b) > 0;
5044 static bool validate_schedule(struct igc_adapter *adapter,
5045 const struct tc_taprio_qopt_offload *qopt)
5047 int queue_uses[IGC_MAX_TX_QUEUES] = { };
5048 struct timespec64 now;
5051 if (qopt->cycle_time_extension)
5054 igc_ptp_read(adapter, &now);
5056 /* If we program the controller's BASET registers with a time
5057 * in the future, it will hold all the packets until that
5058 * time, causing a lot of TX Hangs, so to avoid that, we
5059 * reject schedules that would start in the future.
5061 if (!is_base_time_past(qopt->base_time, &now))
5064 for (n = 0; n < qopt->num_entries; n++) {
5065 const struct tc_taprio_sched_entry *e;
5068 e = &qopt->entries[n];
5070 /* i225 only supports "global" frame preemption
5073 if (e->command != TC_TAPRIO_CMD_SET_GATES)
5076 for (i = 0; i < IGC_MAX_TX_QUEUES; i++) {
5077 if (e->gate_mask & BIT(i))
5080 if (queue_uses[i] > 1)
5088 static int igc_tsn_enable_launchtime(struct igc_adapter *adapter,
5089 struct tc_etf_qopt_offload *qopt)
5091 struct igc_hw *hw = &adapter->hw;
5094 if (hw->mac.type != igc_i225)
5097 err = igc_save_launchtime_params(adapter, qopt->queue, qopt->enable);
5101 return igc_tsn_offload_apply(adapter);
5104 static int igc_save_qbv_schedule(struct igc_adapter *adapter,
5105 struct tc_taprio_qopt_offload *qopt)
5107 u32 start_time = 0, end_time = 0;
5110 if (!qopt->enable) {
5111 adapter->base_time = 0;
5115 if (adapter->base_time)
5118 if (!validate_schedule(adapter, qopt))
5121 adapter->cycle_time = qopt->cycle_time;
5122 adapter->base_time = qopt->base_time;
5124 /* FIXME: be a little smarter about cases when the gate for a
5125 * queue stays open for more than one entry.
5127 for (n = 0; n < qopt->num_entries; n++) {
5128 struct tc_taprio_sched_entry *e = &qopt->entries[n];
5131 end_time += e->interval;
5133 for (i = 0; i < IGC_MAX_TX_QUEUES; i++) {
5134 struct igc_ring *ring = adapter->tx_ring[i];
5136 if (!(e->gate_mask & BIT(i)))
5139 ring->start_time = start_time;
5140 ring->end_time = end_time;
5143 start_time += e->interval;
5149 static int igc_tsn_enable_qbv_scheduling(struct igc_adapter *adapter,
5150 struct tc_taprio_qopt_offload *qopt)
5152 struct igc_hw *hw = &adapter->hw;
5155 if (hw->mac.type != igc_i225)
5158 err = igc_save_qbv_schedule(adapter, qopt);
5162 return igc_tsn_offload_apply(adapter);
5165 static int igc_setup_tc(struct net_device *dev, enum tc_setup_type type,
5168 struct igc_adapter *adapter = netdev_priv(dev);
5171 case TC_SETUP_QDISC_TAPRIO:
5172 return igc_tsn_enable_qbv_scheduling(adapter, type_data);
5174 case TC_SETUP_QDISC_ETF:
5175 return igc_tsn_enable_launchtime(adapter, type_data);
5182 static int igc_bpf(struct net_device *dev, struct netdev_bpf *bpf)
5184 struct igc_adapter *adapter = netdev_priv(dev);
5186 switch (bpf->command) {
5187 case XDP_SETUP_PROG:
5188 return igc_xdp_set_prog(adapter, bpf->prog, bpf->extack);
5194 static int igc_xdp_xmit(struct net_device *dev, int num_frames,
5195 struct xdp_frame **frames, u32 flags)
5197 struct igc_adapter *adapter = netdev_priv(dev);
5198 int cpu = smp_processor_id();
5199 struct netdev_queue *nq;
5200 struct igc_ring *ring;
5203 if (unlikely(test_bit(__IGC_DOWN, &adapter->state)))
5206 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
5209 ring = igc_xdp_get_tx_ring(adapter, cpu);
5210 nq = txring_txq(ring);
5212 __netif_tx_lock(nq, cpu);
5215 for (i = 0; i < num_frames; i++) {
5217 struct xdp_frame *xdpf = frames[i];
5219 err = igc_xdp_init_tx_descriptor(ring, xdpf);
5221 xdp_return_frame_rx_napi(xdpf);
5226 if (flags & XDP_XMIT_FLUSH)
5227 igc_flush_tx_descriptors(ring);
5229 __netif_tx_unlock(nq);
5231 return num_frames - drops;
5234 static const struct net_device_ops igc_netdev_ops = {
5235 .ndo_open = igc_open,
5236 .ndo_stop = igc_close,
5237 .ndo_start_xmit = igc_xmit_frame,
5238 .ndo_set_rx_mode = igc_set_rx_mode,
5239 .ndo_set_mac_address = igc_set_mac,
5240 .ndo_change_mtu = igc_change_mtu,
5241 .ndo_get_stats64 = igc_get_stats64,
5242 .ndo_fix_features = igc_fix_features,
5243 .ndo_set_features = igc_set_features,
5244 .ndo_features_check = igc_features_check,
5245 .ndo_do_ioctl = igc_ioctl,
5246 .ndo_setup_tc = igc_setup_tc,
5248 .ndo_xdp_xmit = igc_xdp_xmit,
5251 /* PCIe configuration access */
5252 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value)
5254 struct igc_adapter *adapter = hw->back;
5256 pci_read_config_word(adapter->pdev, reg, value);
5259 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value)
5261 struct igc_adapter *adapter = hw->back;
5263 pci_write_config_word(adapter->pdev, reg, *value);
5266 s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value)
5268 struct igc_adapter *adapter = hw->back;
5270 if (!pci_is_pcie(adapter->pdev))
5271 return -IGC_ERR_CONFIG;
5273 pcie_capability_read_word(adapter->pdev, reg, value);
5278 s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value)
5280 struct igc_adapter *adapter = hw->back;
5282 if (!pci_is_pcie(adapter->pdev))
5283 return -IGC_ERR_CONFIG;
5285 pcie_capability_write_word(adapter->pdev, reg, *value);
5290 u32 igc_rd32(struct igc_hw *hw, u32 reg)
5292 struct igc_adapter *igc = container_of(hw, struct igc_adapter, hw);
5293 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr);
5296 value = readl(&hw_addr[reg]);
5298 /* reads should not return all F's */
5299 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
5300 struct net_device *netdev = igc->netdev;
5303 netif_device_detach(netdev);
5304 netdev_err(netdev, "PCIe link lost, device now detached\n");
5305 WARN(pci_device_is_present(igc->pdev),
5306 "igc: Failed to read reg 0x%x!\n", reg);
5312 int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx)
5314 struct igc_mac_info *mac = &adapter->hw.mac;
5316 mac->autoneg = false;
5318 /* Make sure dplx is at most 1 bit and lsb of speed is not set
5319 * for the switch() below to work
5321 if ((spd & 1) || (dplx & ~1))
5324 switch (spd + dplx) {
5325 case SPEED_10 + DUPLEX_HALF:
5326 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5328 case SPEED_10 + DUPLEX_FULL:
5329 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5331 case SPEED_100 + DUPLEX_HALF:
5332 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5334 case SPEED_100 + DUPLEX_FULL:
5335 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5337 case SPEED_1000 + DUPLEX_FULL:
5338 mac->autoneg = true;
5339 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5341 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5343 case SPEED_2500 + DUPLEX_FULL:
5344 mac->autoneg = true;
5345 adapter->hw.phy.autoneg_advertised = ADVERTISE_2500_FULL;
5347 case SPEED_2500 + DUPLEX_HALF: /* not supported */
5352 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
5353 adapter->hw.phy.mdix = AUTO_ALL_MODES;
5358 netdev_err(adapter->netdev, "Unsupported Speed/Duplex configuration\n");
5363 * igc_probe - Device Initialization Routine
5364 * @pdev: PCI device information struct
5365 * @ent: entry in igc_pci_tbl
5367 * Returns 0 on success, negative on failure
5369 * igc_probe initializes an adapter identified by a pci_dev structure.
5370 * The OS initialization, configuring the adapter private structure,
5371 * and a hardware reset occur.
5373 static int igc_probe(struct pci_dev *pdev,
5374 const struct pci_device_id *ent)
5376 struct igc_adapter *adapter;
5377 struct net_device *netdev;
5379 const struct igc_info *ei = igc_info_tbl[ent->driver_data];
5380 int err, pci_using_dac;
5382 err = pci_enable_device_mem(pdev);
5387 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
5391 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
5394 "No usable DMA configuration, aborting\n");
5399 err = pci_request_mem_regions(pdev, igc_driver_name);
5403 pci_enable_pcie_error_reporting(pdev);
5405 pci_set_master(pdev);
5408 netdev = alloc_etherdev_mq(sizeof(struct igc_adapter),
5412 goto err_alloc_etherdev;
5414 SET_NETDEV_DEV(netdev, &pdev->dev);
5416 pci_set_drvdata(pdev, netdev);
5417 adapter = netdev_priv(netdev);
5418 adapter->netdev = netdev;
5419 adapter->pdev = pdev;
5422 adapter->port_num = hw->bus.func;
5423 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
5425 err = pci_save_state(pdev);
5430 adapter->io_addr = ioremap(pci_resource_start(pdev, 0),
5431 pci_resource_len(pdev, 0));
5432 if (!adapter->io_addr)
5435 /* hw->hw_addr can be zeroed, so use adapter->io_addr for unmap */
5436 hw->hw_addr = adapter->io_addr;
5438 netdev->netdev_ops = &igc_netdev_ops;
5439 igc_ethtool_set_ops(netdev);
5440 netdev->watchdog_timeo = 5 * HZ;
5442 netdev->mem_start = pci_resource_start(pdev, 0);
5443 netdev->mem_end = pci_resource_end(pdev, 0);
5445 /* PCI config space info */
5446 hw->vendor_id = pdev->vendor;
5447 hw->device_id = pdev->device;
5448 hw->revision_id = pdev->revision;
5449 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5450 hw->subsystem_device_id = pdev->subsystem_device;
5452 /* Copy the default MAC and PHY function pointers */
5453 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
5454 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
5456 /* Initialize skew-specific constants */
5457 err = ei->get_invariants(hw);
5461 /* Add supported features to the features list*/
5462 netdev->features |= NETIF_F_SG;
5463 netdev->features |= NETIF_F_TSO;
5464 netdev->features |= NETIF_F_TSO6;
5465 netdev->features |= NETIF_F_TSO_ECN;
5466 netdev->features |= NETIF_F_RXCSUM;
5467 netdev->features |= NETIF_F_HW_CSUM;
5468 netdev->features |= NETIF_F_SCTP_CRC;
5469 netdev->features |= NETIF_F_HW_TC;
5471 #define IGC_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
5472 NETIF_F_GSO_GRE_CSUM | \
5473 NETIF_F_GSO_IPXIP4 | \
5474 NETIF_F_GSO_IPXIP6 | \
5475 NETIF_F_GSO_UDP_TUNNEL | \
5476 NETIF_F_GSO_UDP_TUNNEL_CSUM)
5478 netdev->gso_partial_features = IGC_GSO_PARTIAL_FEATURES;
5479 netdev->features |= NETIF_F_GSO_PARTIAL | IGC_GSO_PARTIAL_FEATURES;
5481 /* setup the private structure */
5482 err = igc_sw_init(adapter);
5486 /* copy netdev features into list of user selectable features */
5487 netdev->hw_features |= NETIF_F_NTUPLE;
5488 netdev->hw_features |= netdev->features;
5491 netdev->features |= NETIF_F_HIGHDMA;
5493 /* MTU range: 68 - 9216 */
5494 netdev->min_mtu = ETH_MIN_MTU;
5495 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE;
5497 /* before reading the NVM, reset the controller to put the device in a
5498 * known good starting state
5500 hw->mac.ops.reset_hw(hw);
5502 if (igc_get_flash_presence_i225(hw)) {
5503 if (hw->nvm.ops.validate(hw) < 0) {
5504 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
5510 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) {
5511 /* copy the MAC address out of the NVM */
5512 if (hw->mac.ops.read_mac_addr(hw))
5513 dev_err(&pdev->dev, "NVM Read Error\n");
5516 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
5518 if (!is_valid_ether_addr(netdev->dev_addr)) {
5519 dev_err(&pdev->dev, "Invalid MAC Address\n");
5524 /* configure RXPBSIZE and TXPBSIZE */
5525 wr32(IGC_RXPBS, I225_RXPBSIZE_DEFAULT);
5526 wr32(IGC_TXPBS, I225_TXPBSIZE_DEFAULT);
5528 timer_setup(&adapter->watchdog_timer, igc_watchdog, 0);
5529 timer_setup(&adapter->phy_info_timer, igc_update_phy_info, 0);
5531 INIT_WORK(&adapter->reset_task, igc_reset_task);
5532 INIT_WORK(&adapter->watchdog_task, igc_watchdog_task);
5534 /* Initialize link properties that are user-changeable */
5535 adapter->fc_autoneg = true;
5536 hw->mac.autoneg = true;
5537 hw->phy.autoneg_advertised = 0xaf;
5539 hw->fc.requested_mode = igc_fc_default;
5540 hw->fc.current_mode = igc_fc_default;
5542 /* By default, support wake on port A */
5543 adapter->flags |= IGC_FLAG_WOL_SUPPORTED;
5545 /* initialize the wol settings based on the eeprom settings */
5546 if (adapter->flags & IGC_FLAG_WOL_SUPPORTED)
5547 adapter->wol |= IGC_WUFC_MAG;
5549 device_set_wakeup_enable(&adapter->pdev->dev,
5550 adapter->flags & IGC_FLAG_WOL_SUPPORTED);
5552 igc_ptp_init(adapter);
5554 /* reset the hardware with the new settings */
5557 /* let the f/w know that the h/w is now under the control of the
5560 igc_get_hw_control(adapter);
5562 strncpy(netdev->name, "eth%d", IFNAMSIZ);
5563 err = register_netdev(netdev);
5567 /* carrier off reporting is important to ethtool even BEFORE open */
5568 netif_carrier_off(netdev);
5570 /* Check if Media Autosense is enabled */
5573 /* print pcie link status and MAC address */
5574 pcie_print_link_status(pdev);
5575 netdev_info(netdev, "MAC: %pM\n", netdev->dev_addr);
5577 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
5578 /* Disable EEE for internal PHY devices */
5579 hw->dev_spec._base.eee_enable = false;
5580 adapter->flags &= ~IGC_FLAG_EEE;
5581 igc_set_eee_i225(hw, false, false, false);
5583 pm_runtime_put_noidle(&pdev->dev);
5588 igc_release_hw_control(adapter);
5590 if (!igc_check_reset_block(hw))
5593 igc_clear_interrupt_scheme(adapter);
5594 iounmap(adapter->io_addr);
5596 free_netdev(netdev);
5598 pci_release_mem_regions(pdev);
5601 pci_disable_device(pdev);
5606 * igc_remove - Device Removal Routine
5607 * @pdev: PCI device information struct
5609 * igc_remove is called by the PCI subsystem to alert the driver
5610 * that it should release a PCI device. This could be caused by a
5611 * Hot-Plug event, or because the driver is going to be removed from
5614 static void igc_remove(struct pci_dev *pdev)
5616 struct net_device *netdev = pci_get_drvdata(pdev);
5617 struct igc_adapter *adapter = netdev_priv(netdev);
5619 pm_runtime_get_noresume(&pdev->dev);
5621 igc_flush_nfc_rules(adapter);
5623 igc_ptp_stop(adapter);
5625 set_bit(__IGC_DOWN, &adapter->state);
5627 del_timer_sync(&adapter->watchdog_timer);
5628 del_timer_sync(&adapter->phy_info_timer);
5630 cancel_work_sync(&adapter->reset_task);
5631 cancel_work_sync(&adapter->watchdog_task);
5633 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5634 * would have already happened in close and is redundant.
5636 igc_release_hw_control(adapter);
5637 unregister_netdev(netdev);
5639 igc_clear_interrupt_scheme(adapter);
5640 pci_iounmap(pdev, adapter->io_addr);
5641 pci_release_mem_regions(pdev);
5643 free_netdev(netdev);
5645 pci_disable_pcie_error_reporting(pdev);
5647 pci_disable_device(pdev);
5650 static int __igc_shutdown(struct pci_dev *pdev, bool *enable_wake,
5653 struct net_device *netdev = pci_get_drvdata(pdev);
5654 struct igc_adapter *adapter = netdev_priv(netdev);
5655 u32 wufc = runtime ? IGC_WUFC_LNKC : adapter->wol;
5656 struct igc_hw *hw = &adapter->hw;
5657 u32 ctrl, rctl, status;
5661 netif_device_detach(netdev);
5663 if (netif_running(netdev))
5664 __igc_close(netdev, true);
5666 igc_ptp_suspend(adapter);
5668 igc_clear_interrupt_scheme(adapter);
5671 status = rd32(IGC_STATUS);
5672 if (status & IGC_STATUS_LU)
5673 wufc &= ~IGC_WUFC_LNKC;
5676 igc_setup_rctl(adapter);
5677 igc_set_rx_mode(netdev);
5679 /* turn on all-multi mode if wake on multicast is enabled */
5680 if (wufc & IGC_WUFC_MC) {
5681 rctl = rd32(IGC_RCTL);
5682 rctl |= IGC_RCTL_MPE;
5683 wr32(IGC_RCTL, rctl);
5686 ctrl = rd32(IGC_CTRL);
5687 ctrl |= IGC_CTRL_ADVD3WUC;
5688 wr32(IGC_CTRL, ctrl);
5690 /* Allow time for pending master requests to run */
5691 igc_disable_pcie_master(hw);
5693 wr32(IGC_WUC, IGC_WUC_PME_EN);
5694 wr32(IGC_WUFC, wufc);
5700 wake = wufc || adapter->en_mng_pt;
5702 igc_power_down_phy_copper_base(&adapter->hw);
5704 igc_power_up_link(adapter);
5707 *enable_wake = wake;
5709 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5710 * would have already happened in close and is redundant.
5712 igc_release_hw_control(adapter);
5714 pci_disable_device(pdev);
5720 static int __maybe_unused igc_runtime_suspend(struct device *dev)
5722 return __igc_shutdown(to_pci_dev(dev), NULL, 1);
5725 static void igc_deliver_wake_packet(struct net_device *netdev)
5727 struct igc_adapter *adapter = netdev_priv(netdev);
5728 struct igc_hw *hw = &adapter->hw;
5729 struct sk_buff *skb;
5732 wupl = rd32(IGC_WUPL) & IGC_WUPL_MASK;
5734 /* WUPM stores only the first 128 bytes of the wake packet.
5735 * Read the packet only if we have the whole thing.
5737 if (wupl == 0 || wupl > IGC_WUPM_BYTES)
5740 skb = netdev_alloc_skb_ip_align(netdev, IGC_WUPM_BYTES);
5746 /* Ensure reads are 32-bit aligned */
5747 wupl = roundup(wupl, 4);
5749 memcpy_fromio(skb->data, hw->hw_addr + IGC_WUPM_REG(0), wupl);
5751 skb->protocol = eth_type_trans(skb, netdev);
5755 static int __maybe_unused igc_resume(struct device *dev)
5757 struct pci_dev *pdev = to_pci_dev(dev);
5758 struct net_device *netdev = pci_get_drvdata(pdev);
5759 struct igc_adapter *adapter = netdev_priv(netdev);
5760 struct igc_hw *hw = &adapter->hw;
5763 pci_set_power_state(pdev, PCI_D0);
5764 pci_restore_state(pdev);
5765 pci_save_state(pdev);
5767 if (!pci_device_is_present(pdev))
5769 err = pci_enable_device_mem(pdev);
5771 netdev_err(netdev, "Cannot enable PCI device from suspend\n");
5774 pci_set_master(pdev);
5776 pci_enable_wake(pdev, PCI_D3hot, 0);
5777 pci_enable_wake(pdev, PCI_D3cold, 0);
5779 if (igc_init_interrupt_scheme(adapter, true)) {
5780 netdev_err(netdev, "Unable to allocate memory for queues\n");
5786 /* let the f/w know that the h/w is now under the control of the
5789 igc_get_hw_control(adapter);
5791 val = rd32(IGC_WUS);
5792 if (val & WAKE_PKT_WUS)
5793 igc_deliver_wake_packet(netdev);
5798 if (!err && netif_running(netdev))
5799 err = __igc_open(netdev, true);
5802 netif_device_attach(netdev);
5808 static int __maybe_unused igc_runtime_resume(struct device *dev)
5810 return igc_resume(dev);
5813 static int __maybe_unused igc_suspend(struct device *dev)
5815 return __igc_shutdown(to_pci_dev(dev), NULL, 0);
5818 static int __maybe_unused igc_runtime_idle(struct device *dev)
5820 struct net_device *netdev = dev_get_drvdata(dev);
5821 struct igc_adapter *adapter = netdev_priv(netdev);
5823 if (!igc_has_link(adapter))
5824 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
5828 #endif /* CONFIG_PM */
5830 static void igc_shutdown(struct pci_dev *pdev)
5834 __igc_shutdown(pdev, &wake, 0);
5836 if (system_state == SYSTEM_POWER_OFF) {
5837 pci_wake_from_d3(pdev, wake);
5838 pci_set_power_state(pdev, PCI_D3hot);
5843 * igc_io_error_detected - called when PCI error is detected
5844 * @pdev: Pointer to PCI device
5845 * @state: The current PCI connection state
5847 * This function is called after a PCI bus error affecting
5848 * this device has been detected.
5850 static pci_ers_result_t igc_io_error_detected(struct pci_dev *pdev,
5851 pci_channel_state_t state)
5853 struct net_device *netdev = pci_get_drvdata(pdev);
5854 struct igc_adapter *adapter = netdev_priv(netdev);
5856 netif_device_detach(netdev);
5858 if (state == pci_channel_io_perm_failure)
5859 return PCI_ERS_RESULT_DISCONNECT;
5861 if (netif_running(netdev))
5863 pci_disable_device(pdev);
5865 /* Request a slot reset. */
5866 return PCI_ERS_RESULT_NEED_RESET;
5870 * igc_io_slot_reset - called after the PCI bus has been reset.
5871 * @pdev: Pointer to PCI device
5873 * Restart the card from scratch, as if from a cold-boot. Implementation
5874 * resembles the first-half of the igc_resume routine.
5876 static pci_ers_result_t igc_io_slot_reset(struct pci_dev *pdev)
5878 struct net_device *netdev = pci_get_drvdata(pdev);
5879 struct igc_adapter *adapter = netdev_priv(netdev);
5880 struct igc_hw *hw = &adapter->hw;
5881 pci_ers_result_t result;
5883 if (pci_enable_device_mem(pdev)) {
5884 netdev_err(netdev, "Could not re-enable PCI device after reset\n");
5885 result = PCI_ERS_RESULT_DISCONNECT;
5887 pci_set_master(pdev);
5888 pci_restore_state(pdev);
5889 pci_save_state(pdev);
5891 pci_enable_wake(pdev, PCI_D3hot, 0);
5892 pci_enable_wake(pdev, PCI_D3cold, 0);
5894 /* In case of PCI error, adapter loses its HW address
5895 * so we should re-assign it here.
5897 hw->hw_addr = adapter->io_addr;
5901 result = PCI_ERS_RESULT_RECOVERED;
5908 * igc_io_resume - called when traffic can start to flow again.
5909 * @pdev: Pointer to PCI device
5911 * This callback is called when the error recovery driver tells us that
5912 * its OK to resume normal operation. Implementation resembles the
5913 * second-half of the igc_resume routine.
5915 static void igc_io_resume(struct pci_dev *pdev)
5917 struct net_device *netdev = pci_get_drvdata(pdev);
5918 struct igc_adapter *adapter = netdev_priv(netdev);
5921 if (netif_running(netdev)) {
5922 if (igc_open(netdev)) {
5923 netdev_err(netdev, "igc_open failed after reset\n");
5928 netif_device_attach(netdev);
5930 /* let the f/w know that the h/w is now under the control of the
5933 igc_get_hw_control(adapter);
5937 static const struct pci_error_handlers igc_err_handler = {
5938 .error_detected = igc_io_error_detected,
5939 .slot_reset = igc_io_slot_reset,
5940 .resume = igc_io_resume,
5944 static const struct dev_pm_ops igc_pm_ops = {
5945 SET_SYSTEM_SLEEP_PM_OPS(igc_suspend, igc_resume)
5946 SET_RUNTIME_PM_OPS(igc_runtime_suspend, igc_runtime_resume,
5951 static struct pci_driver igc_driver = {
5952 .name = igc_driver_name,
5953 .id_table = igc_pci_tbl,
5955 .remove = igc_remove,
5957 .driver.pm = &igc_pm_ops,
5959 .shutdown = igc_shutdown,
5960 .err_handler = &igc_err_handler,
5964 * igc_reinit_queues - return error
5965 * @adapter: pointer to adapter structure
5967 int igc_reinit_queues(struct igc_adapter *adapter)
5969 struct net_device *netdev = adapter->netdev;
5972 if (netif_running(netdev))
5975 igc_reset_interrupt_capability(adapter);
5977 if (igc_init_interrupt_scheme(adapter, true)) {
5978 netdev_err(netdev, "Unable to allocate memory for queues\n");
5982 if (netif_running(netdev))
5983 err = igc_open(netdev);
5989 * igc_get_hw_dev - return device
5990 * @hw: pointer to hardware structure
5992 * used by hardware layer to print debugging information
5994 struct net_device *igc_get_hw_dev(struct igc_hw *hw)
5996 struct igc_adapter *adapter = hw->back;
5998 return adapter->netdev;
6002 * igc_init_module - Driver Registration Routine
6004 * igc_init_module is the first routine called when the driver is
6005 * loaded. All it does is register with the PCI subsystem.
6007 static int __init igc_init_module(void)
6011 pr_info("%s\n", igc_driver_string);
6012 pr_info("%s\n", igc_copyright);
6014 ret = pci_register_driver(&igc_driver);
6018 module_init(igc_init_module);
6021 * igc_exit_module - Driver Exit Cleanup Routine
6023 * igc_exit_module is called just before the driver is removed
6026 static void __exit igc_exit_module(void)
6028 pci_unregister_driver(&igc_driver);
6031 module_exit(igc_exit_module);