drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #include <linux/etherdevice.h>
   5 #include <linux/iopoll.h>
   6 #include <net/rtnetlink.h>
   7 #include "hclgevf_cmd.h"
   8 #include "hclgevf_main.h"
   9 #include "hclge_mbx.h"
  10 #include "hnae3.h"
  11 #include "hclgevf_devlink.h"
  12
  13 #define HCLGEVF_NAME    "hclgevf"
  14
  15 #define HCLGEVF_RESET_MAX_FAIL_CNT      5
  16
  17 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev);
  18 static void hclgevf_task_schedule(struct hclgevf_dev *hdev,
  19                                   unsigned long delay);
  20
  21 static struct hnae3_ae_algo ae_algovf;
  22
  23 static struct workqueue_struct *hclgevf_wq;
  24
  25 static const struct pci_device_id ae_algovf_pci_tbl[] = {
  26         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},
  27         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
  28          HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
  29         /* required last entry */
  30         {0, }
  31 };
  32
  33 static const u8 hclgevf_hash_key[] = {
  34         0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
  35         0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
  36         0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
  37         0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
  38         0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA
  39 };
  40
  41 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl);
  42
  43 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG,
  44                                          HCLGEVF_CMDQ_TX_ADDR_H_REG,
  45                                          HCLGEVF_CMDQ_TX_DEPTH_REG,
  46                                          HCLGEVF_CMDQ_TX_TAIL_REG,
  47                                          HCLGEVF_CMDQ_TX_HEAD_REG,
  48                                          HCLGEVF_CMDQ_RX_ADDR_L_REG,
  49                                          HCLGEVF_CMDQ_RX_ADDR_H_REG,
  50                                          HCLGEVF_CMDQ_RX_DEPTH_REG,
  51                                          HCLGEVF_CMDQ_RX_TAIL_REG,
  52                                          HCLGEVF_CMDQ_RX_HEAD_REG,
  53                                          HCLGEVF_VECTOR0_CMDQ_SRC_REG,
  54                                          HCLGEVF_VECTOR0_CMDQ_STATE_REG,
  55                                          HCLGEVF_CMDQ_INTR_EN_REG,
  56                                          HCLGEVF_CMDQ_INTR_GEN_REG};
  57
  58 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE,
  59                                            HCLGEVF_RST_ING,
  60                                            HCLGEVF_GRO_EN_REG};
  61
  62 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG,
  63                                          HCLGEVF_RING_RX_ADDR_H_REG,
  64                                          HCLGEVF_RING_RX_BD_NUM_REG,
  65                                          HCLGEVF_RING_RX_BD_LENGTH_REG,
  66                                          HCLGEVF_RING_RX_MERGE_EN_REG,
  67                                          HCLGEVF_RING_RX_TAIL_REG,
  68                                          HCLGEVF_RING_RX_HEAD_REG,
  69                                          HCLGEVF_RING_RX_FBD_NUM_REG,
  70                                          HCLGEVF_RING_RX_OFFSET_REG,
  71                                          HCLGEVF_RING_RX_FBD_OFFSET_REG,
  72                                          HCLGEVF_RING_RX_STASH_REG,
  73                                          HCLGEVF_RING_RX_BD_ERR_REG,
  74                                          HCLGEVF_RING_TX_ADDR_L_REG,
  75                                          HCLGEVF_RING_TX_ADDR_H_REG,
  76                                          HCLGEVF_RING_TX_BD_NUM_REG,
  77                                          HCLGEVF_RING_TX_PRIORITY_REG,
  78                                          HCLGEVF_RING_TX_TC_REG,
  79                                          HCLGEVF_RING_TX_MERGE_EN_REG,
  80                                          HCLGEVF_RING_TX_TAIL_REG,
  81                                          HCLGEVF_RING_TX_HEAD_REG,
  82                                          HCLGEVF_RING_TX_FBD_NUM_REG,
  83                                          HCLGEVF_RING_TX_OFFSET_REG,
  84                                          HCLGEVF_RING_TX_EBD_NUM_REG,
  85                                          HCLGEVF_RING_TX_EBD_OFFSET_REG,
  86                                          HCLGEVF_RING_TX_BD_ERR_REG,
  87                                          HCLGEVF_RING_EN_REG};
  88
  89 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG,
  90                                              HCLGEVF_TQP_INTR_GL0_REG,
  91                                              HCLGEVF_TQP_INTR_GL1_REG,
  92                                              HCLGEVF_TQP_INTR_GL2_REG,
  93                                              HCLGEVF_TQP_INTR_RL_REG};
  94
  95 static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle)
  96 {
  97         if (!handle->client)
  98                 return container_of(handle, struct hclgevf_dev, nic);
  99         else if (handle->client->type == HNAE3_CLIENT_ROCE)
 100                 return container_of(handle, struct hclgevf_dev, roce);
 101         else
 102                 return container_of(handle, struct hclgevf_dev, nic);
 103 }
 104
 105 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle)
 106 {
 107         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 108         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 109         struct hclgevf_desc desc;
 110         struct hclgevf_tqp *tqp;
 111         int status;
 112         int i;
 113
 114         for (i = 0; i < kinfo->num_tqps; i++) {
 115                 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
 116                 hclgevf_cmd_setup_basic_desc(&desc,
 117                                              HCLGEVF_OPC_QUERY_RX_STATUS,
 118                                              true);
 119
 120                 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
 121                 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
 122                 if (status) {
 123                         dev_err(&hdev->pdev->dev,
 124                                 "Query tqp stat fail, status = %d,queue = %d\n",
 125                                 status, i);
 126                         return status;
 127                 }
 128                 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
 129                         le32_to_cpu(desc.data[1]);
 130
 131                 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS,
 132                                              true);
 133
 134                 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
 135                 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
 136                 if (status) {
 137                         dev_err(&hdev->pdev->dev,
 138                                 "Query tqp stat fail, status = %d,queue = %d\n",
 139                                 status, i);
 140                         return status;
 141                 }
 142                 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
 143                         le32_to_cpu(desc.data[1]);
 144         }
 145
 146         return 0;
 147 }
 148
 149 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
 150 {
 151         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 152         struct hclgevf_tqp *tqp;
 153         u64 *buff = data;
 154         int i;
 155
 156         for (i = 0; i < kinfo->num_tqps; i++) {
 157                 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
 158                 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
 159         }
 160         for (i = 0; i < kinfo->num_tqps; i++) {
 161                 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
 162                 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
 163         }
 164
 165         return buff;
 166 }
 167
 168 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset)
 169 {
 170         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 171
 172         return kinfo->num_tqps * 2;
 173 }
 174
 175 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
 176 {
 177         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 178         u8 *buff = data;
 179         int i;
 180
 181         for (i = 0; i < kinfo->num_tqps; i++) {
 182                 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i],
 183                                                        struct hclgevf_tqp, q);
 184                 snprintf(buff, ETH_GSTRING_LEN, "txq%u_pktnum_rcd",
 185                          tqp->index);
 186                 buff += ETH_GSTRING_LEN;
 187         }
 188
 189         for (i = 0; i < kinfo->num_tqps; i++) {
 190                 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i],
 191                                                        struct hclgevf_tqp, q);
 192                 snprintf(buff, ETH_GSTRING_LEN, "rxq%u_pktnum_rcd",
 193                          tqp->index);
 194                 buff += ETH_GSTRING_LEN;
 195         }
 196
 197         return buff;
 198 }
 199
 200 static void hclgevf_update_stats(struct hnae3_handle *handle,
 201                                  struct net_device_stats *net_stats)
 202 {
 203         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 204         int status;
 205
 206         status = hclgevf_tqps_update_stats(handle);
 207         if (status)
 208                 dev_err(&hdev->pdev->dev,
 209                         "VF update of TQPS stats fail, status = %d.\n",
 210                         status);
 211 }
 212
 213 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset)
 214 {
 215         if (strset == ETH_SS_TEST)
 216                 return -EOPNOTSUPP;
 217         else if (strset == ETH_SS_STATS)
 218                 return hclgevf_tqps_get_sset_count(handle, strset);
 219
 220         return 0;
 221 }
 222
 223 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset,
 224                                 u8 *data)
 225 {
 226         u8 *p = (char *)data;
 227
 228         if (strset == ETH_SS_STATS)
 229                 p = hclgevf_tqps_get_strings(handle, p);
 230 }
 231
 232 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data)
 233 {
 234         hclgevf_tqps_get_stats(handle, data);
 235 }
 236
 237 static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code,
 238                                    u8 subcode)
 239 {
 240         if (msg) {
 241                 memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg));
 242                 msg->code = code;
 243                 msg->subcode = subcode;
 244         }
 245 }
 246
 247 static int hclgevf_get_basic_info(struct hclgevf_dev *hdev)
 248 {
 249         struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
 250         u8 resp_msg[HCLGE_MBX_MAX_RESP_DATA_SIZE];
 251         struct hclge_basic_info *basic_info;
 252         struct hclge_vf_to_pf_msg send_msg;
 253         unsigned long caps;
 254         int status;
 255
 256         hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_BASIC_INFO, 0);
 257         status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
 258                                       sizeof(resp_msg));
 259         if (status) {
 260                 dev_err(&hdev->pdev->dev,
 261                         "failed to get basic info from pf, ret = %d", status);
 262                 return status;
 263         }
 264
 265         basic_info = (struct hclge_basic_info *)resp_msg;
 266
 267         hdev->hw_tc_map = basic_info->hw_tc_map;
 268         hdev->mbx_api_version = basic_info->mbx_api_version;
 269         caps = basic_info->pf_caps;
 270         if (test_bit(HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B, &caps))
 271                 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps);
 272
 273         return 0;
 274 }
 275
 276 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev)
 277 {
 278         struct hnae3_handle *nic = &hdev->nic;
 279         struct hclge_vf_to_pf_msg send_msg;
 280         u8 resp_msg;
 281         int ret;
 282
 283         hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
 284                                HCLGE_MBX_GET_PORT_BASE_VLAN_STATE);
 285         ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg,
 286                                    sizeof(u8));
 287         if (ret) {
 288                 dev_err(&hdev->pdev->dev,
 289                         "VF request to get port based vlan state failed %d",
 290                         ret);
 291                 return ret;
 292         }
 293
 294         nic->port_base_vlan_state = resp_msg;
 295
 296         return 0;
 297 }
 298
 299 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev)
 300 {
 301 #define HCLGEVF_TQPS_RSS_INFO_LEN       6
 302 #define HCLGEVF_TQPS_ALLOC_OFFSET       0
 303 #define HCLGEVF_TQPS_RSS_SIZE_OFFSET    2
 304 #define HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET       4
 305
 306         u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN];
 307         struct hclge_vf_to_pf_msg send_msg;
 308         int status;
 309
 310         hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0);
 311         status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
 312                                       HCLGEVF_TQPS_RSS_INFO_LEN);
 313         if (status) {
 314                 dev_err(&hdev->pdev->dev,
 315                         "VF request to get tqp info from PF failed %d",
 316                         status);
 317                 return status;
 318         }
 319
 320         memcpy(&hdev->num_tqps, &resp_msg[HCLGEVF_TQPS_ALLOC_OFFSET],
 321                sizeof(u16));
 322         memcpy(&hdev->rss_size_max, &resp_msg[HCLGEVF_TQPS_RSS_SIZE_OFFSET],
 323                sizeof(u16));
 324         memcpy(&hdev->rx_buf_len, &resp_msg[HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET],
 325                sizeof(u16));
 326
 327         return 0;
 328 }
 329
 330 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev)
 331 {
 332 #define HCLGEVF_TQPS_DEPTH_INFO_LEN     4
 333 #define HCLGEVF_TQPS_NUM_TX_DESC_OFFSET 0
 334 #define HCLGEVF_TQPS_NUM_RX_DESC_OFFSET 2
 335
 336         u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN];
 337         struct hclge_vf_to_pf_msg send_msg;
 338         int ret;
 339
 340         hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0);
 341         ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
 342                                    HCLGEVF_TQPS_DEPTH_INFO_LEN);
 343         if (ret) {
 344                 dev_err(&hdev->pdev->dev,
 345                         "VF request to get tqp depth info from PF failed %d",
 346                         ret);
 347                 return ret;
 348         }
 349
 350         memcpy(&hdev->num_tx_desc, &resp_msg[HCLGEVF_TQPS_NUM_TX_DESC_OFFSET],
 351                sizeof(u16));
 352         memcpy(&hdev->num_rx_desc, &resp_msg[HCLGEVF_TQPS_NUM_RX_DESC_OFFSET],
 353                sizeof(u16));
 354
 355         return 0;
 356 }
 357
 358 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id)
 359 {
 360         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 361         struct hclge_vf_to_pf_msg send_msg;
 362         u16 qid_in_pf = 0;
 363         u8 resp_data[2];
 364         int ret;
 365
 366         hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0);
 367         memcpy(send_msg.data, &queue_id, sizeof(queue_id));
 368         ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data,
 369                                    sizeof(resp_data));
 370         if (!ret)
 371                 qid_in_pf = *(u16 *)resp_data;
 372
 373         return qid_in_pf;
 374 }
 375
 376 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev)
 377 {
 378         struct hclge_vf_to_pf_msg send_msg;
 379         u8 resp_msg[2];
 380         int ret;
 381
 382         hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0);
 383         ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
 384                                    sizeof(resp_msg));
 385         if (ret) {
 386                 dev_err(&hdev->pdev->dev,
 387                         "VF request to get the pf port media type failed %d",
 388                         ret);
 389                 return ret;
 390         }
 391
 392         hdev->hw.mac.media_type = resp_msg[0];
 393         hdev->hw.mac.module_type = resp_msg[1];
 394
 395         return 0;
 396 }
 397
 398 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev)
 399 {
 400         struct hclgevf_tqp *tqp;
 401         int i;
 402
 403         hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
 404                                   sizeof(struct hclgevf_tqp), GFP_KERNEL);
 405         if (!hdev->htqp)
 406                 return -ENOMEM;
 407
 408         tqp = hdev->htqp;
 409
 410         for (i = 0; i < hdev->num_tqps; i++) {
 411                 tqp->dev = &hdev->pdev->dev;
 412                 tqp->index = i;
 413
 414                 tqp->q.ae_algo = &ae_algovf;
 415                 tqp->q.buf_size = hdev->rx_buf_len;
 416                 tqp->q.tx_desc_num = hdev->num_tx_desc;
 417                 tqp->q.rx_desc_num = hdev->num_rx_desc;
 418
 419                 /* need an extended offset to configure queues >=
 420                  * HCLGEVF_TQP_MAX_SIZE_DEV_V2.
 421                  */
 422                 if (i < HCLGEVF_TQP_MAX_SIZE_DEV_V2)
 423                         tqp->q.io_base = hdev->hw.io_base +
 424                                          HCLGEVF_TQP_REG_OFFSET +
 425                                          i * HCLGEVF_TQP_REG_SIZE;
 426                 else
 427                         tqp->q.io_base = hdev->hw.io_base +
 428                                          HCLGEVF_TQP_REG_OFFSET +
 429                                          HCLGEVF_TQP_EXT_REG_OFFSET +
 430                                          (i - HCLGEVF_TQP_MAX_SIZE_DEV_V2) *
 431                                          HCLGEVF_TQP_REG_SIZE;
 432
 433                 tqp++;
 434         }
 435
 436         return 0;
 437 }
 438
 439 static int hclgevf_knic_setup(struct hclgevf_dev *hdev)
 440 {
 441         struct hnae3_handle *nic = &hdev->nic;
 442         struct hnae3_knic_private_info *kinfo;
 443         u16 new_tqps = hdev->num_tqps;
 444         unsigned int i;
 445         u8 num_tc = 0;
 446
 447         kinfo = &nic->kinfo;
 448         kinfo->num_tx_desc = hdev->num_tx_desc;
 449         kinfo->num_rx_desc = hdev->num_rx_desc;
 450         kinfo->rx_buf_len = hdev->rx_buf_len;
 451         for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++)
 452                 if (hdev->hw_tc_map & BIT(i))
 453                         num_tc++;
 454
 455         num_tc = num_tc ? num_tc : 1;
 456         kinfo->tc_info.num_tc = num_tc;
 457         kinfo->rss_size = min_t(u16, hdev->rss_size_max, new_tqps / num_tc);
 458         new_tqps = kinfo->rss_size * num_tc;
 459         kinfo->num_tqps = min(new_tqps, hdev->num_tqps);
 460
 461         kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
 462                                   sizeof(struct hnae3_queue *), GFP_KERNEL);
 463         if (!kinfo->tqp)
 464                 return -ENOMEM;
 465
 466         for (i = 0; i < kinfo->num_tqps; i++) {
 467                 hdev->htqp[i].q.handle = &hdev->nic;
 468                 hdev->htqp[i].q.tqp_index = i;
 469                 kinfo->tqp[i] = &hdev->htqp[i].q;
 470         }
 471
 472         /* after init the max rss_size and tqps, adjust the default tqp numbers
 473          * and rss size with the actual vector numbers
 474          */
 475         kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps);
 476         kinfo->rss_size = min_t(u16, kinfo->num_tqps / num_tc,
 477                                 kinfo->rss_size);
 478
 479         return 0;
 480 }
 481
 482 static void hclgevf_request_link_info(struct hclgevf_dev *hdev)
 483 {
 484         struct hclge_vf_to_pf_msg send_msg;
 485         int status;
 486
 487         hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0);
 488         status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
 489         if (status)
 490                 dev_err(&hdev->pdev->dev,
 491                         "VF failed to fetch link status(%d) from PF", status);
 492 }
 493
 494 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state)
 495 {
 496         struct hnae3_handle *rhandle = &hdev->roce;
 497         struct hnae3_handle *handle = &hdev->nic;
 498         struct hnae3_client *rclient;
 499         struct hnae3_client *client;
 500
 501         if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state))
 502                 return;
 503
 504         client = handle->client;
 505         rclient = hdev->roce_client;
 506
 507         link_state =
 508                 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state;
 509         if (link_state != hdev->hw.mac.link) {
 510                 hdev->hw.mac.link = link_state;
 511                 client->ops->link_status_change(handle, !!link_state);
 512                 if (rclient && rclient->ops->link_status_change)
 513                         rclient->ops->link_status_change(rhandle, !!link_state);
 514         }
 515
 516         clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state);
 517 }
 518
 519 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev)
 520 {
 521 #define HCLGEVF_ADVERTISING     0
 522 #define HCLGEVF_SUPPORTED       1
 523
 524         struct hclge_vf_to_pf_msg send_msg;
 525
 526         hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0);
 527         send_msg.data[0] = HCLGEVF_ADVERTISING;
 528         hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
 529         send_msg.data[0] = HCLGEVF_SUPPORTED;
 530         hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
 531 }
 532
 533 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev)
 534 {
 535         struct hnae3_handle *nic = &hdev->nic;
 536         int ret;
 537
 538         nic->ae_algo = &ae_algovf;
 539         nic->pdev = hdev->pdev;
 540         nic->numa_node_mask = hdev->numa_node_mask;
 541         nic->flags |= HNAE3_SUPPORT_VF;
 542         nic->kinfo.io_base = hdev->hw.io_base;
 543
 544         ret = hclgevf_knic_setup(hdev);
 545         if (ret)
 546                 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n",
 547                         ret);
 548         return ret;
 549 }
 550
 551 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id)
 552 {
 553         if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) {
 554                 dev_warn(&hdev->pdev->dev,
 555                          "vector(vector_id %d) has been freed.\n", vector_id);
 556                 return;
 557         }
 558
 559         hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT;
 560         hdev->num_msi_left += 1;
 561         hdev->num_msi_used -= 1;
 562 }
 563
 564 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num,
 565                               struct hnae3_vector_info *vector_info)
 566 {
 567         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 568         struct hnae3_vector_info *vector = vector_info;
 569         int alloc = 0;
 570         int i, j;
 571
 572         vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num);
 573         vector_num = min(hdev->num_msi_left, vector_num);
 574
 575         for (j = 0; j < vector_num; j++) {
 576                 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) {
 577                         if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) {
 578                                 vector->vector = pci_irq_vector(hdev->pdev, i);
 579                                 vector->io_addr = hdev->hw.io_base +
 580                                         HCLGEVF_VECTOR_REG_BASE +
 581                                         (i - 1) * HCLGEVF_VECTOR_REG_OFFSET;
 582                                 hdev->vector_status[i] = 0;
 583                                 hdev->vector_irq[i] = vector->vector;
 584
 585                                 vector++;
 586                                 alloc++;
 587
 588                                 break;
 589                         }
 590                 }
 591         }
 592         hdev->num_msi_left -= alloc;
 593         hdev->num_msi_used += alloc;
 594
 595         return alloc;
 596 }
 597
 598 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector)
 599 {
 600         int i;
 601
 602         for (i = 0; i < hdev->num_msi; i++)
 603                 if (vector == hdev->vector_irq[i])
 604                         return i;
 605
 606         return -EINVAL;
 607 }
 608
 609 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev,
 610                                     const u8 hfunc, const u8 *key)
 611 {
 612         struct hclgevf_rss_config_cmd *req;
 613         unsigned int key_offset = 0;
 614         struct hclgevf_desc desc;
 615         int key_counts;
 616         int key_size;
 617         int ret;
 618
 619         key_counts = HCLGEVF_RSS_KEY_SIZE;
 620         req = (struct hclgevf_rss_config_cmd *)desc.data;
 621
 622         while (key_counts) {
 623                 hclgevf_cmd_setup_basic_desc(&desc,
 624                                              HCLGEVF_OPC_RSS_GENERIC_CONFIG,
 625                                              false);
 626
 627                 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK);
 628                 req->hash_config |=
 629                         (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B);
 630
 631                 key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts);
 632                 memcpy(req->hash_key,
 633                        key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size);
 634
 635                 key_counts -= key_size;
 636                 key_offset++;
 637                 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
 638                 if (ret) {
 639                         dev_err(&hdev->pdev->dev,
 640                                 "Configure RSS config fail, status = %d\n",
 641                                 ret);
 642                         return ret;
 643                 }
 644         }
 645
 646         return 0;
 647 }
 648
 649 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle)
 650 {
 651         return HCLGEVF_RSS_KEY_SIZE;
 652 }
 653
 654 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev)
 655 {
 656         const u8 *indir = hdev->rss_cfg.rss_indirection_tbl;
 657         struct hclgevf_rss_indirection_table_cmd *req;
 658         struct hclgevf_desc desc;
 659         int rss_cfg_tbl_num;
 660         int status;
 661         int i, j;
 662
 663         req = (struct hclgevf_rss_indirection_table_cmd *)desc.data;
 664         rss_cfg_tbl_num = hdev->ae_dev->dev_specs.rss_ind_tbl_size /
 665                           HCLGEVF_RSS_CFG_TBL_SIZE;
 666
 667         for (i = 0; i < rss_cfg_tbl_num; i++) {
 668                 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE,
 669                                              false);
 670                 req->start_table_index =
 671                         cpu_to_le16(i * HCLGEVF_RSS_CFG_TBL_SIZE);
 672                 req->rss_set_bitmap = cpu_to_le16(HCLGEVF_RSS_SET_BITMAP_MSK);
 673                 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++)
 674                         req->rss_result[j] =
 675                                 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j];
 676
 677                 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
 678                 if (status) {
 679                         dev_err(&hdev->pdev->dev,
 680                                 "VF failed(=%d) to set RSS indirection table\n",
 681                                 status);
 682                         return status;
 683                 }
 684         }
 685
 686         return 0;
 687 }
 688
 689 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev,  u16 rss_size)
 690 {
 691         struct hclgevf_rss_tc_mode_cmd *req;
 692         u16 tc_offset[HCLGEVF_MAX_TC_NUM];
 693         u16 tc_valid[HCLGEVF_MAX_TC_NUM];
 694         u16 tc_size[HCLGEVF_MAX_TC_NUM];
 695         struct hclgevf_desc desc;
 696         u16 roundup_size;
 697         unsigned int i;
 698         int status;
 699
 700         req = (struct hclgevf_rss_tc_mode_cmd *)desc.data;
 701
 702         roundup_size = roundup_pow_of_two(rss_size);
 703         roundup_size = ilog2(roundup_size);
 704
 705         for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
 706                 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i));
 707                 tc_size[i] = roundup_size;
 708                 tc_offset[i] = rss_size * i;
 709         }
 710
 711         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false);
 712         for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
 713                 u16 mode = 0;
 714
 715                 hnae3_set_bit(mode, HCLGEVF_RSS_TC_VALID_B,
 716                               (tc_valid[i] & 0x1));
 717                 hnae3_set_field(mode, HCLGEVF_RSS_TC_SIZE_M,
 718                                 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]);
 719                 hnae3_set_bit(mode, HCLGEVF_RSS_TC_SIZE_MSB_B,
 720                               tc_size[i] >> HCLGEVF_RSS_TC_SIZE_MSB_OFFSET &
 721                               0x1);
 722                 hnae3_set_field(mode, HCLGEVF_RSS_TC_OFFSET_M,
 723                                 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]);
 724
 725                 req->rss_tc_mode[i] = cpu_to_le16(mode);
 726         }
 727         status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
 728         if (status)
 729                 dev_err(&hdev->pdev->dev,
 730                         "VF failed(=%d) to set rss tc mode\n", status);
 731
 732         return status;
 733 }
 734
 735 /* for revision 0x20, vf shared the same rss config with pf */
 736 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev)
 737 {
 738 #define HCLGEVF_RSS_MBX_RESP_LEN        8
 739         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
 740         u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN];
 741         struct hclge_vf_to_pf_msg send_msg;
 742         u16 msg_num, hash_key_index;
 743         u8 index;
 744         int ret;
 745
 746         hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0);
 747         msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) /
 748                         HCLGEVF_RSS_MBX_RESP_LEN;
 749         for (index = 0; index < msg_num; index++) {
 750                 send_msg.data[0] = index;
 751                 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
 752                                            HCLGEVF_RSS_MBX_RESP_LEN);
 753                 if (ret) {
 754                         dev_err(&hdev->pdev->dev,
 755                                 "VF get rss hash key from PF failed, ret=%d",
 756                                 ret);
 757                         return ret;
 758                 }
 759
 760                 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index;
 761                 if (index == msg_num - 1)
 762                         memcpy(&rss_cfg->rss_hash_key[hash_key_index],
 763                                &resp_msg[0],
 764                                HCLGEVF_RSS_KEY_SIZE - hash_key_index);
 765                 else
 766                         memcpy(&rss_cfg->rss_hash_key[hash_key_index],
 767                                &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN);
 768         }
 769
 770         return 0;
 771 }
 772
 773 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key,
 774                            u8 *hfunc)
 775 {
 776         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 777         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
 778         int i, ret;
 779
 780         if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
 781                 /* Get hash algorithm */
 782                 if (hfunc) {
 783                         switch (rss_cfg->hash_algo) {
 784                         case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ:
 785                                 *hfunc = ETH_RSS_HASH_TOP;
 786                                 break;
 787                         case HCLGEVF_RSS_HASH_ALGO_SIMPLE:
 788                                 *hfunc = ETH_RSS_HASH_XOR;
 789                                 break;
 790                         default:
 791                                 *hfunc = ETH_RSS_HASH_UNKNOWN;
 792                                 break;
 793                         }
 794                 }
 795
 796                 /* Get the RSS Key required by the user */
 797                 if (key)
 798                         memcpy(key, rss_cfg->rss_hash_key,
 799                                HCLGEVF_RSS_KEY_SIZE);
 800         } else {
 801                 if (hfunc)
 802                         *hfunc = ETH_RSS_HASH_TOP;
 803                 if (key) {
 804                         ret = hclgevf_get_rss_hash_key(hdev);
 805                         if (ret)
 806                                 return ret;
 807                         memcpy(key, rss_cfg->rss_hash_key,
 808                                HCLGEVF_RSS_KEY_SIZE);
 809                 }
 810         }
 811
 812         if (indir)
 813                 for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++)
 814                         indir[i] = rss_cfg->rss_indirection_tbl[i];
 815
 816         return 0;
 817 }
 818
 819 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir,
 820                            const u8 *key, const u8 hfunc)
 821 {
 822         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 823         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
 824         int ret, i;
 825
 826         if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
 827                 /* Set the RSS Hash Key if specififed by the user */
 828                 if (key) {
 829                         switch (hfunc) {
 830                         case ETH_RSS_HASH_TOP:
 831                                 rss_cfg->hash_algo =
 832                                         HCLGEVF_RSS_HASH_ALGO_TOEPLITZ;
 833                                 break;
 834                         case ETH_RSS_HASH_XOR:
 835                                 rss_cfg->hash_algo =
 836                                         HCLGEVF_RSS_HASH_ALGO_SIMPLE;
 837                                 break;
 838                         case ETH_RSS_HASH_NO_CHANGE:
 839                                 break;
 840                         default:
 841                                 return -EINVAL;
 842                         }
 843
 844                         ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo,
 845                                                        key);
 846                         if (ret)
 847                                 return ret;
 848
 849                         /* Update the shadow RSS key with user specified qids */
 850                         memcpy(rss_cfg->rss_hash_key, key,
 851                                HCLGEVF_RSS_KEY_SIZE);
 852                 }
 853         }
 854
 855         /* update the shadow RSS table with user specified qids */
 856         for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++)
 857                 rss_cfg->rss_indirection_tbl[i] = indir[i];
 858
 859         /* update the hardware */
 860         return hclgevf_set_rss_indir_table(hdev);
 861 }
 862
 863 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
 864 {
 865         u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0;
 866
 867         if (nfc->data & RXH_L4_B_2_3)
 868                 hash_sets |= HCLGEVF_D_PORT_BIT;
 869         else
 870                 hash_sets &= ~HCLGEVF_D_PORT_BIT;
 871
 872         if (nfc->data & RXH_IP_SRC)
 873                 hash_sets |= HCLGEVF_S_IP_BIT;
 874         else
 875                 hash_sets &= ~HCLGEVF_S_IP_BIT;
 876
 877         if (nfc->data & RXH_IP_DST)
 878                 hash_sets |= HCLGEVF_D_IP_BIT;
 879         else
 880                 hash_sets &= ~HCLGEVF_D_IP_BIT;
 881
 882         if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
 883                 hash_sets |= HCLGEVF_V_TAG_BIT;
 884
 885         return hash_sets;
 886 }
 887
 888 static int hclgevf_init_rss_tuple_cmd(struct hnae3_handle *handle,
 889                                       struct ethtool_rxnfc *nfc,
 890                                       struct hclgevf_rss_input_tuple_cmd *req)
 891 {
 892         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 893         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
 894         u8 tuple_sets;
 895
 896         req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
 897         req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en;
 898         req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
 899         req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en;
 900         req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
 901         req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en;
 902         req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
 903         req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en;
 904
 905         tuple_sets = hclgevf_get_rss_hash_bits(nfc);
 906         switch (nfc->flow_type) {
 907         case TCP_V4_FLOW:
 908                 req->ipv4_tcp_en = tuple_sets;
 909                 break;
 910         case TCP_V6_FLOW:
 911                 req->ipv6_tcp_en = tuple_sets;
 912                 break;
 913         case UDP_V4_FLOW:
 914                 req->ipv4_udp_en = tuple_sets;
 915                 break;
 916         case UDP_V6_FLOW:
 917                 req->ipv6_udp_en = tuple_sets;
 918                 break;
 919         case SCTP_V4_FLOW:
 920                 req->ipv4_sctp_en = tuple_sets;
 921                 break;
 922         case SCTP_V6_FLOW:
 923                 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 &&
 924                     (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)))
 925                         return -EINVAL;
 926
 927                 req->ipv6_sctp_en = tuple_sets;
 928                 break;
 929         case IPV4_FLOW:
 930                 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
 931                 break;
 932         case IPV6_FLOW:
 933                 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
 934                 break;
 935         default:
 936                 return -EINVAL;
 937         }
 938
 939         return 0;
 940 }
 941
 942 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle,
 943                                  struct ethtool_rxnfc *nfc)
 944 {
 945         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 946         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
 947         struct hclgevf_rss_input_tuple_cmd *req;
 948         struct hclgevf_desc desc;
 949         int ret;
 950
 951         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
 952                 return -EOPNOTSUPP;
 953
 954         if (nfc->data &
 955             ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3))
 956                 return -EINVAL;
 957
 958         req = (struct hclgevf_rss_input_tuple_cmd *)desc.data;
 959         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false);
 960
 961         ret = hclgevf_init_rss_tuple_cmd(handle, nfc, req);
 962         if (ret) {
 963                 dev_err(&hdev->pdev->dev,
 964                         "failed to init rss tuple cmd, ret = %d\n", ret);
 965                 return ret;
 966         }
 967
 968         ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
 969         if (ret) {
 970                 dev_err(&hdev->pdev->dev,
 971                         "Set rss tuple fail, status = %d\n", ret);
 972                 return ret;
 973         }
 974
 975         rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
 976         rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
 977         rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
 978         rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
 979         rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
 980         rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
 981         rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
 982         rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
 983         return 0;
 984 }
 985
 986 static int hclgevf_get_rss_tuple_by_flow_type(struct hclgevf_dev *hdev,
 987                                               int flow_type, u8 *tuple_sets)
 988 {
 989         switch (flow_type) {
 990         case TCP_V4_FLOW:
 991                 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_tcp_en;
 992                 break;
 993         case UDP_V4_FLOW:
 994                 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_udp_en;
 995                 break;
 996         case TCP_V6_FLOW:
 997                 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_tcp_en;
 998                 break;
 999         case UDP_V6_FLOW:
1000                 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_udp_en;
1001                 break;
1002         case SCTP_V4_FLOW:
1003                 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_sctp_en;
1004                 break;
1005         case SCTP_V6_FLOW:
1006                 *tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_sctp_en;
1007                 break;
1008         case IPV4_FLOW:
1009         case IPV6_FLOW:
1010                 *tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT;
1011                 break;
1012         default:
1013                 return -EINVAL;
1014         }
1015
1016         return 0;
1017 }
1018
1019 static u64 hclgevf_convert_rss_tuple(u8 tuple_sets)
1020 {
1021         u64 tuple_data = 0;
1022
1023         if (tuple_sets & HCLGEVF_D_PORT_BIT)
1024                 tuple_data |= RXH_L4_B_2_3;
1025         if (tuple_sets & HCLGEVF_S_PORT_BIT)
1026                 tuple_data |= RXH_L4_B_0_1;
1027         if (tuple_sets & HCLGEVF_D_IP_BIT)
1028                 tuple_data |= RXH_IP_DST;
1029         if (tuple_sets & HCLGEVF_S_IP_BIT)
1030                 tuple_data |= RXH_IP_SRC;
1031
1032         return tuple_data;
1033 }
1034
1035 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle,
1036                                  struct ethtool_rxnfc *nfc)
1037 {
1038         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1039         u8 tuple_sets;
1040         int ret;
1041
1042         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
1043                 return -EOPNOTSUPP;
1044
1045         nfc->data = 0;
1046
1047         ret = hclgevf_get_rss_tuple_by_flow_type(hdev, nfc->flow_type,
1048                                                  &tuple_sets);
1049         if (ret || !tuple_sets)
1050                 return ret;
1051
1052         nfc->data = hclgevf_convert_rss_tuple(tuple_sets);
1053
1054         return 0;
1055 }
1056
1057 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev,
1058                                        struct hclgevf_rss_cfg *rss_cfg)
1059 {
1060         struct hclgevf_rss_input_tuple_cmd *req;
1061         struct hclgevf_desc desc;
1062         int ret;
1063
1064         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false);
1065
1066         req = (struct hclgevf_rss_input_tuple_cmd *)desc.data;
1067
1068         req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
1069         req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en;
1070         req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
1071         req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en;
1072         req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
1073         req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en;
1074         req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
1075         req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en;
1076
1077         ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
1078         if (ret)
1079                 dev_err(&hdev->pdev->dev,
1080                         "Configure rss input fail, status = %d\n", ret);
1081         return ret;
1082 }
1083
1084 static int hclgevf_get_tc_size(struct hnae3_handle *handle)
1085 {
1086         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1087         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
1088
1089         return rss_cfg->rss_size;
1090 }
1091
1092 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en,
1093                                        int vector_id,
1094                                        struct hnae3_ring_chain_node *ring_chain)
1095 {
1096         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1097         struct hclge_vf_to_pf_msg send_msg;
1098         struct hnae3_ring_chain_node *node;
1099         int status;
1100         int i = 0;
1101
1102         memset(&send_msg, 0, sizeof(send_msg));
1103         send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR :
1104                 HCLGE_MBX_UNMAP_RING_TO_VECTOR;
1105         send_msg.vector_id = vector_id;
1106
1107         for (node = ring_chain; node; node = node->next) {
1108                 send_msg.param[i].ring_type =
1109                                 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B);
1110
1111                 send_msg.param[i].tqp_index = node->tqp_index;
1112                 send_msg.param[i].int_gl_index =
1113                                         hnae3_get_field(node->int_gl_idx,
1114                                                         HNAE3_RING_GL_IDX_M,
1115                                                         HNAE3_RING_GL_IDX_S);
1116
1117                 i++;
1118                 if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) {
1119                         send_msg.ring_num = i;
1120
1121                         status = hclgevf_send_mbx_msg(hdev, &send_msg, false,
1122                                                       NULL, 0);
1123                         if (status) {
1124                                 dev_err(&hdev->pdev->dev,
1125                                         "Map TQP fail, status is %d.\n",
1126                                         status);
1127                                 return status;
1128                         }
1129                         i = 0;
1130                 }
1131         }
1132
1133         return 0;
1134 }
1135
1136 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector,
1137                                       struct hnae3_ring_chain_node *ring_chain)
1138 {
1139         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1140         int vector_id;
1141
1142         vector_id = hclgevf_get_vector_index(hdev, vector);
1143         if (vector_id < 0) {
1144                 dev_err(&handle->pdev->dev,
1145                         "Get vector index fail. ret =%d\n", vector_id);
1146                 return vector_id;
1147         }
1148
1149         return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain);
1150 }
1151
1152 static int hclgevf_unmap_ring_from_vector(
1153                                 struct hnae3_handle *handle,
1154                                 int vector,
1155                                 struct hnae3_ring_chain_node *ring_chain)
1156 {
1157         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1158         int ret, vector_id;
1159
1160         if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
1161                 return 0;
1162
1163         vector_id = hclgevf_get_vector_index(hdev, vector);
1164         if (vector_id < 0) {
1165                 dev_err(&handle->pdev->dev,
1166                         "Get vector index fail. ret =%d\n", vector_id);
1167                 return vector_id;
1168         }
1169
1170         ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain);
1171         if (ret)
1172                 dev_err(&handle->pdev->dev,
1173                         "Unmap ring from vector fail. vector=%d, ret =%d\n",
1174                         vector_id,
1175                         ret);
1176
1177         return ret;
1178 }
1179
1180 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector)
1181 {
1182         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1183         int vector_id;
1184
1185         vector_id = hclgevf_get_vector_index(hdev, vector);
1186         if (vector_id < 0) {
1187                 dev_err(&handle->pdev->dev,
1188                         "hclgevf_put_vector get vector index fail. ret =%d\n",
1189                         vector_id);
1190                 return vector_id;
1191         }
1192
1193         hclgevf_free_vector(hdev, vector_id);
1194
1195         return 0;
1196 }
1197
1198 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev,
1199                                         bool en_uc_pmc, bool en_mc_pmc,
1200                                         bool en_bc_pmc)
1201 {
1202         struct hnae3_handle *handle = &hdev->nic;
1203         struct hclge_vf_to_pf_msg send_msg;
1204         int ret;
1205
1206         memset(&send_msg, 0, sizeof(send_msg));
1207         send_msg.code = HCLGE_MBX_SET_PROMISC_MODE;
1208         send_msg.en_bc = en_bc_pmc ? 1 : 0;
1209         send_msg.en_uc = en_uc_pmc ? 1 : 0;
1210         send_msg.en_mc = en_mc_pmc ? 1 : 0;
1211         send_msg.en_limit_promisc = test_bit(HNAE3_PFLAG_LIMIT_PROMISC,
1212                                              &handle->priv_flags) ? 1 : 0;
1213
1214         ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
1215         if (ret)
1216                 dev_err(&hdev->pdev->dev,
1217                         "Set promisc mode fail, status is %d.\n", ret);
1218
1219         return ret;
1220 }
1221
1222 static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
1223                                     bool en_mc_pmc)
1224 {
1225         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1226         bool en_bc_pmc;
1227
1228         en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2;
1229
1230         return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc,
1231                                             en_bc_pmc);
1232 }
1233
1234 static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle)
1235 {
1236         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1237
1238         set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);
1239         hclgevf_task_schedule(hdev, 0);
1240 }
1241
1242 static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev)
1243 {
1244         struct hnae3_handle *handle = &hdev->nic;
1245         bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE;
1246         bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE;
1247         int ret;
1248
1249         if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) {
1250                 ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc);
1251                 if (!ret)
1252                         clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);
1253         }
1254 }
1255
1256 static int hclgevf_tqp_enable_cmd_send(struct hclgevf_dev *hdev, u16 tqp_id,
1257                                        u16 stream_id, bool enable)
1258 {
1259         struct hclgevf_cfg_com_tqp_queue_cmd *req;
1260         struct hclgevf_desc desc;
1261
1262         req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data;
1263
1264         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE,
1265                                      false);
1266         req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK);
1267         req->stream_id = cpu_to_le16(stream_id);
1268         if (enable)
1269                 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B;
1270
1271         return hclgevf_cmd_send(&hdev->hw, &desc, 1);
1272 }
1273
1274 static int hclgevf_tqp_enable(struct hnae3_handle *handle, bool enable)
1275 {
1276         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1277         int ret;
1278         u16 i;
1279
1280         for (i = 0; i < handle->kinfo.num_tqps; i++) {
1281                 ret = hclgevf_tqp_enable_cmd_send(hdev, i, 0, enable);
1282                 if (ret)
1283                         return ret;
1284         }
1285
1286         return 0;
1287 }
1288
1289 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle)
1290 {
1291         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
1292         struct hclgevf_tqp *tqp;
1293         int i;
1294
1295         for (i = 0; i < kinfo->num_tqps; i++) {
1296                 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
1297                 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
1298         }
1299 }
1300
1301 static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p)
1302 {
1303         struct hclge_vf_to_pf_msg send_msg;
1304         u8 host_mac[ETH_ALEN];
1305         int status;
1306
1307         hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0);
1308         status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac,
1309                                       ETH_ALEN);
1310         if (status) {
1311                 dev_err(&hdev->pdev->dev,
1312                         "fail to get VF MAC from host %d", status);
1313                 return status;
1314         }
1315
1316         ether_addr_copy(p, host_mac);
1317
1318         return 0;
1319 }
1320
1321 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p)
1322 {
1323         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1324         u8 host_mac_addr[ETH_ALEN];
1325
1326         if (hclgevf_get_host_mac_addr(hdev, host_mac_addr))
1327                 return;
1328
1329         hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr);
1330         if (hdev->has_pf_mac)
1331                 ether_addr_copy(p, host_mac_addr);
1332         else
1333                 ether_addr_copy(p, hdev->hw.mac.mac_addr);
1334 }
1335
1336 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p,
1337                                 bool is_first)
1338 {
1339         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1340         u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr;
1341         struct hclge_vf_to_pf_msg send_msg;
1342         u8 *new_mac_addr = (u8 *)p;
1343         int status;
1344
1345         hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0);
1346         send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY;
1347         ether_addr_copy(send_msg.data, new_mac_addr);
1348         if (is_first && !hdev->has_pf_mac)
1349                 eth_zero_addr(&send_msg.data[ETH_ALEN]);
1350         else
1351                 ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr);
1352         status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1353         if (!status)
1354                 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr);
1355
1356         return status;
1357 }
1358
1359 static struct hclgevf_mac_addr_node *
1360 hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr)
1361 {
1362         struct hclgevf_mac_addr_node *mac_node, *tmp;
1363
1364         list_for_each_entry_safe(mac_node, tmp, list, node)
1365                 if (ether_addr_equal(mac_addr, mac_node->mac_addr))
1366                         return mac_node;
1367
1368         return NULL;
1369 }
1370
1371 static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node,
1372                                     enum HCLGEVF_MAC_NODE_STATE state)
1373 {
1374         switch (state) {
1375         /* from set_rx_mode or tmp_add_list */
1376         case HCLGEVF_MAC_TO_ADD:
1377                 if (mac_node->state == HCLGEVF_MAC_TO_DEL)
1378                         mac_node->state = HCLGEVF_MAC_ACTIVE;
1379                 break;
1380         /* only from set_rx_mode */
1381         case HCLGEVF_MAC_TO_DEL:
1382                 if (mac_node->state == HCLGEVF_MAC_TO_ADD) {
1383                         list_del(&mac_node->node);
1384                         kfree(mac_node);
1385                 } else {
1386                         mac_node->state = HCLGEVF_MAC_TO_DEL;
1387                 }
1388                 break;
1389         /* only from tmp_add_list, the mac_node->state won't be
1390          * HCLGEVF_MAC_ACTIVE
1391          */
1392         case HCLGEVF_MAC_ACTIVE:
1393                 if (mac_node->state == HCLGEVF_MAC_TO_ADD)
1394                         mac_node->state = HCLGEVF_MAC_ACTIVE;
1395                 break;
1396         }
1397 }
1398
1399 static int hclgevf_update_mac_list(struct hnae3_handle *handle,
1400                                    enum HCLGEVF_MAC_NODE_STATE state,
1401                                    enum HCLGEVF_MAC_ADDR_TYPE mac_type,
1402                                    const unsigned char *addr)
1403 {
1404         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1405         struct hclgevf_mac_addr_node *mac_node;
1406         struct list_head *list;
1407
1408         list = (mac_type == HCLGEVF_MAC_ADDR_UC) ?
1409                &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list;
1410
1411         spin_lock_bh(&hdev->mac_table.mac_list_lock);
1412
1413         /* if the mac addr is already in the mac list, no need to add a new
1414          * one into it, just check the mac addr state, convert it to a new
1415          * new state, or just remove it, or do nothing.
1416          */
1417         mac_node = hclgevf_find_mac_node(list, addr);
1418         if (mac_node) {
1419                 hclgevf_update_mac_node(mac_node, state);
1420                 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1421                 return 0;
1422         }
1423         /* if this address is never added, unnecessary to delete */
1424         if (state == HCLGEVF_MAC_TO_DEL) {
1425                 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1426                 return -ENOENT;
1427         }
1428
1429         mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC);
1430         if (!mac_node) {
1431                 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1432                 return -ENOMEM;
1433         }
1434
1435         mac_node->state = state;
1436         ether_addr_copy(mac_node->mac_addr, addr);
1437         list_add_tail(&mac_node->node, list);
1438
1439         spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1440         return 0;
1441 }
1442
1443 static int hclgevf_add_uc_addr(struct hnae3_handle *handle,
1444                                const unsigned char *addr)
1445 {
1446         return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD,
1447                                        HCLGEVF_MAC_ADDR_UC, addr);
1448 }
1449
1450 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle,
1451                               const unsigned char *addr)
1452 {
1453         return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL,
1454                                        HCLGEVF_MAC_ADDR_UC, addr);
1455 }
1456
1457 static int hclgevf_add_mc_addr(struct hnae3_handle *handle,
1458                                const unsigned char *addr)
1459 {
1460         return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD,
1461                                        HCLGEVF_MAC_ADDR_MC, addr);
1462 }
1463
1464 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle,
1465                               const unsigned char *addr)
1466 {
1467         return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL,
1468                                        HCLGEVF_MAC_ADDR_MC, addr);
1469 }
1470
1471 static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev,
1472                                     struct hclgevf_mac_addr_node *mac_node,
1473                                     enum HCLGEVF_MAC_ADDR_TYPE mac_type)
1474 {
1475         struct hclge_vf_to_pf_msg send_msg;
1476         u8 code, subcode;
1477
1478         if (mac_type == HCLGEVF_MAC_ADDR_UC) {
1479                 code = HCLGE_MBX_SET_UNICAST;
1480                 if (mac_node->state == HCLGEVF_MAC_TO_ADD)
1481                         subcode = HCLGE_MBX_MAC_VLAN_UC_ADD;
1482                 else
1483                         subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE;
1484         } else {
1485                 code = HCLGE_MBX_SET_MULTICAST;
1486                 if (mac_node->state == HCLGEVF_MAC_TO_ADD)
1487                         subcode = HCLGE_MBX_MAC_VLAN_MC_ADD;
1488                 else
1489                         subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE;
1490         }
1491
1492         hclgevf_build_send_msg(&send_msg, code, subcode);
1493         ether_addr_copy(send_msg.data, mac_node->mac_addr);
1494         return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
1495 }
1496
1497 static void hclgevf_config_mac_list(struct hclgevf_dev *hdev,
1498                                     struct list_head *list,
1499                                     enum HCLGEVF_MAC_ADDR_TYPE mac_type)
1500 {
1501         struct hclgevf_mac_addr_node *mac_node, *tmp;
1502         int ret;
1503
1504         list_for_each_entry_safe(mac_node, tmp, list, node) {
1505                 ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type);
1506                 if  (ret) {
1507                         dev_err(&hdev->pdev->dev,
1508                                 "failed to configure mac %pM, state = %d, ret = %d\n",
1509                                 mac_node->mac_addr, mac_node->state, ret);
1510                         return;
1511                 }
1512                 if (mac_node->state == HCLGEVF_MAC_TO_ADD) {
1513                         mac_node->state = HCLGEVF_MAC_ACTIVE;
1514                 } else {
1515                         list_del(&mac_node->node);
1516                         kfree(mac_node);
1517                 }
1518         }
1519 }
1520
1521 static void hclgevf_sync_from_add_list(struct list_head *add_list,
1522                                        struct list_head *mac_list)
1523 {
1524         struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;
1525
1526         list_for_each_entry_safe(mac_node, tmp, add_list, node) {
1527                 /* if the mac address from tmp_add_list is not in the
1528                  * uc/mc_mac_list, it means have received a TO_DEL request
1529                  * during the time window of sending mac config request to PF
1530                  * If mac_node state is ACTIVE, then change its state to TO_DEL,
1531                  * then it will be removed at next time. If is TO_ADD, it means
1532                  * send TO_ADD request failed, so just remove the mac node.
1533                  */
1534                 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr);
1535                 if (new_node) {
1536                         hclgevf_update_mac_node(new_node, mac_node->state);
1537                         list_del(&mac_node->node);
1538                         kfree(mac_node);
1539                 } else if (mac_node->state == HCLGEVF_MAC_ACTIVE) {
1540                         mac_node->state = HCLGEVF_MAC_TO_DEL;
1541                         list_move_tail(&mac_node->node, mac_list);
1542                 } else {
1543                         list_del(&mac_node->node);
1544                         kfree(mac_node);
1545                 }
1546         }
1547 }
1548
1549 static void hclgevf_sync_from_del_list(struct list_head *del_list,
1550                                        struct list_head *mac_list)
1551 {
1552         struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;
1553
1554         list_for_each_entry_safe(mac_node, tmp, del_list, node) {
1555                 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr);
1556                 if (new_node) {
1557                         /* If the mac addr is exist in the mac list, it means
1558                          * received a new request TO_ADD during the time window
1559                          * of sending mac addr configurrequest to PF, so just
1560                          * change the mac state to ACTIVE.
1561                          */
1562                         new_node->state = HCLGEVF_MAC_ACTIVE;
1563                         list_del(&mac_node->node);
1564                         kfree(mac_node);
1565                 } else {
1566                         list_move_tail(&mac_node->node, mac_list);
1567                 }
1568         }
1569 }
1570
1571 static void hclgevf_clear_list(struct list_head *list)
1572 {
1573         struct hclgevf_mac_addr_node *mac_node, *tmp;
1574
1575         list_for_each_entry_safe(mac_node, tmp, list, node) {
1576                 list_del(&mac_node->node);
1577                 kfree(mac_node);
1578         }
1579 }
1580
1581 static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev,
1582                                   enum HCLGEVF_MAC_ADDR_TYPE mac_type)
1583 {
1584         struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;
1585         struct list_head tmp_add_list, tmp_del_list;
1586         struct list_head *list;
1587
1588         INIT_LIST_HEAD(&tmp_add_list);
1589         INIT_LIST_HEAD(&tmp_del_list);
1590
1591         /* move the mac addr to the tmp_add_list and tmp_del_list, then
1592          * we can add/delete these mac addr outside the spin lock
1593          */
1594         list = (mac_type == HCLGEVF_MAC_ADDR_UC) ?
1595                 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list;
1596
1597         spin_lock_bh(&hdev->mac_table.mac_list_lock);
1598
1599         list_for_each_entry_safe(mac_node, tmp, list, node) {
1600                 switch (mac_node->state) {
1601                 case HCLGEVF_MAC_TO_DEL:
1602                         list_move_tail(&mac_node->node, &tmp_del_list);
1603                         break;
1604                 case HCLGEVF_MAC_TO_ADD:
1605                         new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC);
1606                         if (!new_node)
1607                                 goto stop_traverse;
1608
1609                         ether_addr_copy(new_node->mac_addr, mac_node->mac_addr);
1610                         new_node->state = mac_node->state;
1611                         list_add_tail(&new_node->node, &tmp_add_list);
1612                         break;
1613                 default:
1614                         break;
1615                 }
1616         }
1617
1618 stop_traverse:
1619         spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1620
1621         /* delete first, in order to get max mac table space for adding */
1622         hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type);
1623         hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type);
1624
1625         /* if some mac addresses were added/deleted fail, move back to the
1626          * mac_list, and retry at next time.
1627          */
1628         spin_lock_bh(&hdev->mac_table.mac_list_lock);
1629
1630         hclgevf_sync_from_del_list(&tmp_del_list, list);
1631         hclgevf_sync_from_add_list(&tmp_add_list, list);
1632
1633         spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1634 }
1635
1636 static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev)
1637 {
1638         hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC);
1639         hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC);
1640 }
1641
1642 static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev)
1643 {
1644         spin_lock_bh(&hdev->mac_table.mac_list_lock);
1645
1646         hclgevf_clear_list(&hdev->mac_table.uc_mac_list);
1647         hclgevf_clear_list(&hdev->mac_table.mc_mac_list);
1648
1649         spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1650 }
1651
1652 static int hclgevf_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
1653 {
1654         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1655         struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
1656         struct hclge_vf_to_pf_msg send_msg;
1657
1658         if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
1659                 return -EOPNOTSUPP;
1660
1661         hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
1662                                HCLGE_MBX_ENABLE_VLAN_FILTER);
1663         send_msg.data[0] = enable ? 1 : 0;
1664
1665         return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1666 }
1667
1668 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle,
1669                                    __be16 proto, u16 vlan_id,
1670                                    bool is_kill)
1671 {
1672 #define HCLGEVF_VLAN_MBX_IS_KILL_OFFSET 0
1673 #define HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET 1
1674 #define HCLGEVF_VLAN_MBX_PROTO_OFFSET   3
1675
1676         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1677         struct hclge_vf_to_pf_msg send_msg;
1678         int ret;
1679
1680         if (vlan_id > HCLGEVF_MAX_VLAN_ID)
1681                 return -EINVAL;
1682
1683         if (proto != htons(ETH_P_8021Q))
1684                 return -EPROTONOSUPPORT;
1685
1686         /* When device is resetting or reset failed, firmware is unable to
1687          * handle mailbox. Just record the vlan id, and remove it after
1688          * reset finished.
1689          */
1690         if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||
1691              test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) {
1692                 set_bit(vlan_id, hdev->vlan_del_fail_bmap);
1693                 return -EBUSY;
1694         }
1695
1696         hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
1697                                HCLGE_MBX_VLAN_FILTER);
1698         send_msg.data[HCLGEVF_VLAN_MBX_IS_KILL_OFFSET] = is_kill;
1699         memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET], &vlan_id,
1700                sizeof(vlan_id));
1701         memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_PROTO_OFFSET], &proto,
1702                sizeof(proto));
1703         /* when remove hw vlan filter failed, record the vlan id,
1704          * and try to remove it from hw later, to be consistence
1705          * with stack.
1706          */
1707         ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1708         if (is_kill && ret)
1709                 set_bit(vlan_id, hdev->vlan_del_fail_bmap);
1710
1711         return ret;
1712 }
1713
1714 static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev)
1715 {
1716 #define HCLGEVF_MAX_SYNC_COUNT  60
1717         struct hnae3_handle *handle = &hdev->nic;
1718         int ret, sync_cnt = 0;
1719         u16 vlan_id;
1720
1721         vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID);
1722         while (vlan_id != VLAN_N_VID) {
1723                 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q),
1724                                               vlan_id, true);
1725                 if (ret)
1726                         return;
1727
1728                 clear_bit(vlan_id, hdev->vlan_del_fail_bmap);
1729                 sync_cnt++;
1730                 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT)
1731                         return;
1732
1733                 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID);
1734         }
1735 }
1736
1737 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
1738 {
1739         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1740         struct hclge_vf_to_pf_msg send_msg;
1741
1742         hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
1743                                HCLGE_MBX_VLAN_RX_OFF_CFG);
1744         send_msg.data[0] = enable ? 1 : 0;
1745         return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
1746 }
1747
1748 static int hclgevf_reset_tqp(struct hnae3_handle *handle)
1749 {
1750 #define HCLGEVF_RESET_ALL_QUEUE_DONE    1U
1751         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1752         struct hclge_vf_to_pf_msg send_msg;
1753         u8 return_status = 0;
1754         int ret;
1755         u16 i;
1756
1757         /* disable vf queue before send queue reset msg to PF */
1758         ret = hclgevf_tqp_enable(handle, false);
1759         if (ret) {
1760                 dev_err(&hdev->pdev->dev, "failed to disable tqp, ret = %d\n",
1761                         ret);
1762                 return ret;
1763         }
1764
1765         hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0);
1766
1767         ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &return_status,
1768                                    sizeof(return_status));
1769         if (ret || return_status == HCLGEVF_RESET_ALL_QUEUE_DONE)
1770                 return ret;
1771
1772         for (i = 1; i < handle->kinfo.num_tqps; i++) {
1773                 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0);
1774                 memcpy(send_msg.data, &i, sizeof(i));
1775                 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1776                 if (ret)
1777                         return ret;
1778         }
1779
1780         return 0;
1781 }
1782
1783 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu)
1784 {
1785         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1786         struct hclge_vf_to_pf_msg send_msg;
1787
1788         hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0);
1789         memcpy(send_msg.data, &new_mtu, sizeof(new_mtu));
1790         return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1791 }
1792
1793 static int hclgevf_notify_client(struct hclgevf_dev *hdev,
1794                                  enum hnae3_reset_notify_type type)
1795 {
1796         struct hnae3_client *client = hdev->nic_client;
1797         struct hnae3_handle *handle = &hdev->nic;
1798         int ret;
1799
1800         if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) ||
1801             !client)
1802                 return 0;
1803
1804         if (!client->ops->reset_notify)
1805                 return -EOPNOTSUPP;
1806
1807         ret = client->ops->reset_notify(handle, type);
1808         if (ret)
1809                 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n",
1810                         type, ret);
1811
1812         return ret;
1813 }
1814
1815 static int hclgevf_notify_roce_client(struct hclgevf_dev *hdev,
1816                                       enum hnae3_reset_notify_type type)
1817 {
1818         struct hnae3_client *client = hdev->roce_client;
1819         struct hnae3_handle *handle = &hdev->roce;
1820         int ret;
1821
1822         if (!test_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state) || !client)
1823                 return 0;
1824
1825         if (!client->ops->reset_notify)
1826                 return -EOPNOTSUPP;
1827
1828         ret = client->ops->reset_notify(handle, type);
1829         if (ret)
1830                 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)",
1831                         type, ret);
1832         return ret;
1833 }
1834
1835 static int hclgevf_reset_wait(struct hclgevf_dev *hdev)
1836 {
1837 #define HCLGEVF_RESET_WAIT_US   20000
1838 #define HCLGEVF_RESET_WAIT_CNT  2000
1839 #define HCLGEVF_RESET_WAIT_TIMEOUT_US   \
1840         (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT)
1841
1842         u32 val;
1843         int ret;
1844
1845         if (hdev->reset_type == HNAE3_VF_RESET)
1846                 ret = readl_poll_timeout(hdev->hw.io_base +
1847                                          HCLGEVF_VF_RST_ING, val,
1848                                          !(val & HCLGEVF_VF_RST_ING_BIT),
1849                                          HCLGEVF_RESET_WAIT_US,
1850                                          HCLGEVF_RESET_WAIT_TIMEOUT_US);
1851         else
1852                 ret = readl_poll_timeout(hdev->hw.io_base +
1853                                          HCLGEVF_RST_ING, val,
1854                                          !(val & HCLGEVF_RST_ING_BITS),
1855                                          HCLGEVF_RESET_WAIT_US,
1856                                          HCLGEVF_RESET_WAIT_TIMEOUT_US);
1857
1858         /* hardware completion status should be available by this time */
1859         if (ret) {
1860                 dev_err(&hdev->pdev->dev,
1861                         "couldn't get reset done status from h/w, timeout!\n");
1862                 return ret;
1863         }
1864
1865         /* we will wait a bit more to let reset of the stack to complete. This
1866          * might happen in case reset assertion was made by PF. Yes, this also
1867          * means we might end up waiting bit more even for VF reset.
1868          */
1869         msleep(5000);
1870
1871         return 0;
1872 }
1873
1874 static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable)
1875 {
1876         u32 reg_val;
1877
1878         reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG);
1879         if (enable)
1880                 reg_val |= HCLGEVF_NIC_SW_RST_RDY;
1881         else
1882                 reg_val &= ~HCLGEVF_NIC_SW_RST_RDY;
1883
1884         hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG,
1885                           reg_val);
1886 }
1887
1888 static int hclgevf_reset_stack(struct hclgevf_dev *hdev)
1889 {
1890         int ret;
1891
1892         /* uninitialize the nic client */
1893         ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT);
1894         if (ret)
1895                 return ret;
1896
1897         /* re-initialize the hclge device */
1898         ret = hclgevf_reset_hdev(hdev);
1899         if (ret) {
1900                 dev_err(&hdev->pdev->dev,
1901                         "hclge device re-init failed, VF is disabled!\n");
1902                 return ret;
1903         }
1904
1905         /* bring up the nic client again */
1906         ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT);
1907         if (ret)
1908                 return ret;
1909
1910         /* clear handshake status with IMP */
1911         hclgevf_reset_handshake(hdev, false);
1912
1913         /* bring up the nic to enable TX/RX again */
1914         return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
1915 }
1916
1917 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev)
1918 {
1919 #define HCLGEVF_RESET_SYNC_TIME 100
1920
1921         if (hdev->reset_type == HNAE3_VF_FUNC_RESET) {
1922                 struct hclge_vf_to_pf_msg send_msg;
1923                 int ret;
1924
1925                 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0);
1926                 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1927                 if (ret) {
1928                         dev_err(&hdev->pdev->dev,
1929                                 "failed to assert VF reset, ret = %d\n", ret);
1930                         return ret;
1931                 }
1932                 hdev->rst_stats.vf_func_rst_cnt++;
1933         }
1934
1935         set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
1936         /* inform hardware that preparatory work is done */
1937         msleep(HCLGEVF_RESET_SYNC_TIME);
1938         hclgevf_reset_handshake(hdev, true);
1939         dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done\n",
1940                  hdev->reset_type);
1941
1942         return 0;
1943 }
1944
1945 static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev)
1946 {
1947         dev_info(&hdev->pdev->dev, "VF function reset count: %u\n",
1948                  hdev->rst_stats.vf_func_rst_cnt);
1949         dev_info(&hdev->pdev->dev, "FLR reset count: %u\n",
1950                  hdev->rst_stats.flr_rst_cnt);
1951         dev_info(&hdev->pdev->dev, "VF reset count: %u\n",
1952                  hdev->rst_stats.vf_rst_cnt);
1953         dev_info(&hdev->pdev->dev, "reset done count: %u\n",
1954                  hdev->rst_stats.rst_done_cnt);
1955         dev_info(&hdev->pdev->dev, "HW reset done count: %u\n",
1956                  hdev->rst_stats.hw_rst_done_cnt);
1957         dev_info(&hdev->pdev->dev, "reset count: %u\n",
1958                  hdev->rst_stats.rst_cnt);
1959         dev_info(&hdev->pdev->dev, "reset fail count: %u\n",
1960                  hdev->rst_stats.rst_fail_cnt);
1961         dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n",
1962                  hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE));
1963         dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n",
1964                  hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STATE_REG));
1965         dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n",
1966                  hclgevf_read_dev(&hdev->hw, HCLGEVF_CMDQ_TX_DEPTH_REG));
1967         dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n",
1968                  hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING));
1969         dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state);
1970 }
1971
1972 static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev)
1973 {
1974         /* recover handshake status with IMP when reset fail */
1975         hclgevf_reset_handshake(hdev, true);
1976         hdev->rst_stats.rst_fail_cnt++;
1977         dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n",
1978                 hdev->rst_stats.rst_fail_cnt);
1979
1980         if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT)
1981                 set_bit(hdev->reset_type, &hdev->reset_pending);
1982
1983         if (hclgevf_is_reset_pending(hdev)) {
1984                 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
1985                 hclgevf_reset_task_schedule(hdev);
1986         } else {
1987                 set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
1988                 hclgevf_dump_rst_info(hdev);
1989         }
1990 }
1991
1992 static int hclgevf_reset_prepare(struct hclgevf_dev *hdev)
1993 {
1994         int ret;
1995
1996         hdev->rst_stats.rst_cnt++;
1997
1998         /* perform reset of the stack & ae device for a client */
1999         ret = hclgevf_notify_roce_client(hdev, HNAE3_DOWN_CLIENT);
2000         if (ret)
2001                 return ret;
2002
2003         rtnl_lock();
2004         /* bring down the nic to stop any ongoing TX/RX */
2005         ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);
2006         rtnl_unlock();
2007         if (ret)
2008                 return ret;
2009
2010         return hclgevf_reset_prepare_wait(hdev);
2011 }
2012
2013 static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev)
2014 {
2015         int ret;
2016
2017         hdev->rst_stats.hw_rst_done_cnt++;
2018         ret = hclgevf_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT);
2019         if (ret)
2020                 return ret;
2021
2022         rtnl_lock();
2023         /* now, re-initialize the nic client and ae device */
2024         ret = hclgevf_reset_stack(hdev);
2025         rtnl_unlock();
2026         if (ret) {
2027                 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n");
2028                 return ret;
2029         }
2030
2031         ret = hclgevf_notify_roce_client(hdev, HNAE3_INIT_CLIENT);
2032         /* ignore RoCE notify error if it fails HCLGEVF_RESET_MAX_FAIL_CNT - 1
2033          * times
2034          */
2035         if (ret &&
2036             hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT - 1)
2037                 return ret;
2038
2039         ret = hclgevf_notify_roce_client(hdev, HNAE3_UP_CLIENT);
2040         if (ret)
2041                 return ret;
2042
2043         hdev->last_reset_time = jiffies;
2044         hdev->rst_stats.rst_done_cnt++;
2045         hdev->rst_stats.rst_fail_cnt = 0;
2046         clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
2047
2048         return 0;
2049 }
2050
2051 static void hclgevf_reset(struct hclgevf_dev *hdev)
2052 {
2053         if (hclgevf_reset_prepare(hdev))
2054                 goto err_reset;
2055
2056         /* check if VF could successfully fetch the hardware reset completion
2057          * status from the hardware
2058          */
2059         if (hclgevf_reset_wait(hdev)) {
2060                 /* can't do much in this situation, will disable VF */
2061                 dev_err(&hdev->pdev->dev,
2062                         "failed to fetch H/W reset completion status\n");
2063                 goto err_reset;
2064         }
2065
2066         if (hclgevf_reset_rebuild(hdev))
2067                 goto err_reset;
2068
2069         return;
2070
2071 err_reset:
2072         hclgevf_reset_err_handle(hdev);
2073 }
2074
2075 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev,
2076                                                      unsigned long *addr)
2077 {
2078         enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2079
2080         /* return the highest priority reset level amongst all */
2081         if (test_bit(HNAE3_VF_RESET, addr)) {
2082                 rst_level = HNAE3_VF_RESET;
2083                 clear_bit(HNAE3_VF_RESET, addr);
2084                 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr);
2085                 clear_bit(HNAE3_VF_FUNC_RESET, addr);
2086         } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) {
2087                 rst_level = HNAE3_VF_FULL_RESET;
2088                 clear_bit(HNAE3_VF_FULL_RESET, addr);
2089                 clear_bit(HNAE3_VF_FUNC_RESET, addr);
2090         } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) {
2091                 rst_level = HNAE3_VF_PF_FUNC_RESET;
2092                 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr);
2093                 clear_bit(HNAE3_VF_FUNC_RESET, addr);
2094         } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) {
2095                 rst_level = HNAE3_VF_FUNC_RESET;
2096                 clear_bit(HNAE3_VF_FUNC_RESET, addr);
2097         } else if (test_bit(HNAE3_FLR_RESET, addr)) {
2098                 rst_level = HNAE3_FLR_RESET;
2099                 clear_bit(HNAE3_FLR_RESET, addr);
2100         }
2101
2102         return rst_level;
2103 }
2104
2105 static void hclgevf_reset_event(struct pci_dev *pdev,
2106                                 struct hnae3_handle *handle)
2107 {
2108         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2109         struct hclgevf_dev *hdev = ae_dev->priv;
2110
2111         dev_info(&hdev->pdev->dev, "received reset request from VF enet\n");
2112
2113         if (hdev->default_reset_request)
2114                 hdev->reset_level =
2115                         hclgevf_get_reset_level(hdev,
2116                                                 &hdev->default_reset_request);
2117         else
2118                 hdev->reset_level = HNAE3_VF_FUNC_RESET;
2119
2120         /* reset of this VF requested */
2121         set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state);
2122         hclgevf_reset_task_schedule(hdev);
2123
2124         hdev->last_reset_time = jiffies;
2125 }
2126
2127 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
2128                                           enum hnae3_reset_type rst_type)
2129 {
2130         struct hclgevf_dev *hdev = ae_dev->priv;
2131
2132         set_bit(rst_type, &hdev->default_reset_request);
2133 }
2134
2135 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en)
2136 {
2137         writel(en ? 1 : 0, vector->addr);
2138 }
2139
2140 static void hclgevf_reset_prepare_general(struct hnae3_ae_dev *ae_dev,
2141                                           enum hnae3_reset_type rst_type)
2142 {
2143 #define HCLGEVF_RESET_RETRY_WAIT_MS     500
2144 #define HCLGEVF_RESET_RETRY_CNT         5
2145
2146         struct hclgevf_dev *hdev = ae_dev->priv;
2147         int retry_cnt = 0;
2148         int ret;
2149
2150 retry:
2151         down(&hdev->reset_sem);
2152         set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2153         hdev->reset_type = rst_type;
2154         ret = hclgevf_reset_prepare(hdev);
2155         if (ret) {
2156                 dev_err(&hdev->pdev->dev, "fail to prepare to reset, ret=%d\n",
2157                         ret);
2158                 if (hdev->reset_pending ||
2159                     retry_cnt++ < HCLGEVF_RESET_RETRY_CNT) {
2160                         dev_err(&hdev->pdev->dev,
2161                                 "reset_pending:0x%lx, retry_cnt:%d\n",
2162                                 hdev->reset_pending, retry_cnt);
2163                         clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2164                         up(&hdev->reset_sem);
2165                         msleep(HCLGEVF_RESET_RETRY_WAIT_MS);
2166                         goto retry;
2167                 }
2168         }
2169
2170         /* disable misc vector before reset done */
2171         hclgevf_enable_vector(&hdev->misc_vector, false);
2172
2173         if (hdev->reset_type == HNAE3_FLR_RESET)
2174                 hdev->rst_stats.flr_rst_cnt++;
2175 }
2176
2177 static void hclgevf_reset_done(struct hnae3_ae_dev *ae_dev)
2178 {
2179         struct hclgevf_dev *hdev = ae_dev->priv;
2180         int ret;
2181
2182         hclgevf_enable_vector(&hdev->misc_vector, true);
2183
2184         ret = hclgevf_reset_rebuild(hdev);
2185         if (ret)
2186                 dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n",
2187                          ret);
2188
2189         hdev->reset_type = HNAE3_NONE_RESET;
2190         clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2191         up(&hdev->reset_sem);
2192 }
2193
2194 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle)
2195 {
2196         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2197
2198         return hdev->fw_version;
2199 }
2200
2201 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev)
2202 {
2203         struct hclgevf_misc_vector *vector = &hdev->misc_vector;
2204
2205         vector->vector_irq = pci_irq_vector(hdev->pdev,
2206                                             HCLGEVF_MISC_VECTOR_NUM);
2207         vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE;
2208         /* vector status always valid for Vector 0 */
2209         hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0;
2210         hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq;
2211
2212         hdev->num_msi_left -= 1;
2213         hdev->num_msi_used += 1;
2214 }
2215
2216 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev)
2217 {
2218         if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&
2219             !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED,
2220                               &hdev->state))
2221                 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0);
2222 }
2223
2224 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev)
2225 {
2226         if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&
2227             !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED,
2228                               &hdev->state))
2229                 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0);
2230 }
2231
2232 static void hclgevf_task_schedule(struct hclgevf_dev *hdev,
2233                                   unsigned long delay)
2234 {
2235         if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&
2236             !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state))
2237                 mod_delayed_work(hclgevf_wq, &hdev->service_task, delay);
2238 }
2239
2240 static void hclgevf_reset_service_task(struct hclgevf_dev *hdev)
2241 {
2242 #define HCLGEVF_MAX_RESET_ATTEMPTS_CNT  3
2243
2244         if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state))
2245                 return;
2246
2247         down(&hdev->reset_sem);
2248         set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2249
2250         if (test_and_clear_bit(HCLGEVF_RESET_PENDING,
2251                                &hdev->reset_state)) {
2252                 /* PF has intimated that it is about to reset the hardware.
2253                  * We now have to poll & check if hardware has actually
2254                  * completed the reset sequence. On hardware reset completion,
2255                  * VF needs to reset the client and ae device.
2256                  */
2257                 hdev->reset_attempts = 0;
2258
2259                 hdev->last_reset_time = jiffies;
2260                 while ((hdev->reset_type =
2261                         hclgevf_get_reset_level(hdev, &hdev->reset_pending))
2262                        != HNAE3_NONE_RESET)
2263                         hclgevf_reset(hdev);
2264         } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED,
2265                                       &hdev->reset_state)) {
2266                 /* we could be here when either of below happens:
2267                  * 1. reset was initiated due to watchdog timeout caused by
2268                  *    a. IMP was earlier reset and our TX got choked down and
2269                  *       which resulted in watchdog reacting and inducing VF
2270                  *       reset. This also means our cmdq would be unreliable.
2271                  *    b. problem in TX due to other lower layer(example link
2272                  *       layer not functioning properly etc.)
2273                  * 2. VF reset might have been initiated due to some config
2274                  *    change.
2275                  *
2276                  * NOTE: Theres no clear way to detect above cases than to react
2277                  * to the response of PF for this reset request. PF will ack the
2278                  * 1b and 2. cases but we will not get any intimation about 1a
2279                  * from PF as cmdq would be in unreliable state i.e. mailbox
2280                  * communication between PF and VF would be broken.
2281                  *
2282                  * if we are never geting into pending state it means either:
2283                  * 1. PF is not receiving our request which could be due to IMP
2284                  *    reset
2285                  * 2. PF is screwed
2286                  * We cannot do much for 2. but to check first we can try reset
2287                  * our PCIe + stack and see if it alleviates the problem.
2288                  */
2289                 if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) {
2290                         /* prepare for full reset of stack + pcie interface */
2291                         set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending);
2292
2293                         /* "defer" schedule the reset task again */
2294                         set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
2295                 } else {
2296                         hdev->reset_attempts++;
2297
2298                         set_bit(hdev->reset_level, &hdev->reset_pending);
2299                         set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
2300                 }
2301                 hclgevf_reset_task_schedule(hdev);
2302         }
2303
2304         hdev->reset_type = HNAE3_NONE_RESET;
2305         clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2306         up(&hdev->reset_sem);
2307 }
2308
2309 static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev)
2310 {
2311         if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state))
2312                 return;
2313
2314         if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state))
2315                 return;
2316
2317         hclgevf_mbx_async_handler(hdev);
2318
2319         clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
2320 }
2321
2322 static void hclgevf_keep_alive(struct hclgevf_dev *hdev)
2323 {
2324         struct hclge_vf_to_pf_msg send_msg;
2325         int ret;
2326
2327         if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state))
2328                 return;
2329
2330         hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0);
2331         ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
2332         if (ret)
2333                 dev_err(&hdev->pdev->dev,
2334                         "VF sends keep alive cmd failed(=%d)\n", ret);
2335 }
2336
2337 static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev)
2338 {
2339         unsigned long delta = round_jiffies_relative(HZ);
2340         struct hnae3_handle *handle = &hdev->nic;
2341
2342         if (test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state))
2343                 return;
2344
2345         if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) {
2346                 delta = jiffies - hdev->last_serv_processed;
2347
2348                 if (delta < round_jiffies_relative(HZ)) {
2349                         delta = round_jiffies_relative(HZ) - delta;
2350                         goto out;
2351                 }
2352         }
2353
2354         hdev->serv_processed_cnt++;
2355         if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL))
2356                 hclgevf_keep_alive(hdev);
2357
2358         if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) {
2359                 hdev->last_serv_processed = jiffies;
2360                 goto out;
2361         }
2362
2363         if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL))
2364                 hclgevf_tqps_update_stats(handle);
2365
2366         /* VF does not need to request link status when this bit is set, because
2367          * PF will push its link status to VFs when link status changed.
2368          */
2369         if (!test_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state))
2370                 hclgevf_request_link_info(hdev);
2371
2372         hclgevf_update_link_mode(hdev);
2373
2374         hclgevf_sync_vlan_filter(hdev);
2375
2376         hclgevf_sync_mac_table(hdev);
2377
2378         hclgevf_sync_promisc_mode(hdev);
2379
2380         hdev->last_serv_processed = jiffies;
2381
2382 out:
2383         hclgevf_task_schedule(hdev, delta);
2384 }
2385
2386 static void hclgevf_service_task(struct work_struct *work)
2387 {
2388         struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev,
2389                                                 service_task.work);
2390
2391         hclgevf_reset_service_task(hdev);
2392         hclgevf_mailbox_service_task(hdev);
2393         hclgevf_periodic_service_task(hdev);
2394
2395         /* Handle reset and mbx again in case periodical task delays the
2396          * handling by calling hclgevf_task_schedule() in
2397          * hclgevf_periodic_service_task()
2398          */
2399         hclgevf_reset_service_task(hdev);
2400         hclgevf_mailbox_service_task(hdev);
2401 }
2402
2403 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr)
2404 {
2405         hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr);
2406 }
2407
2408 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev,
2409                                                       u32 *clearval)
2410 {
2411         u32 val, cmdq_stat_reg, rst_ing_reg;
2412
2413         /* fetch the events from their corresponding regs */
2414         cmdq_stat_reg = hclgevf_read_dev(&hdev->hw,
2415                                          HCLGEVF_VECTOR0_CMDQ_STATE_REG);
2416         if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
2417                 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
2418                 dev_info(&hdev->pdev->dev,
2419                          "receive reset interrupt 0x%x!\n", rst_ing_reg);
2420                 set_bit(HNAE3_VF_RESET, &hdev->reset_pending);
2421                 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
2422                 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
2423                 *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B);
2424                 hdev->rst_stats.vf_rst_cnt++;
2425                 /* set up VF hardware reset status, its PF will clear
2426                  * this status when PF has initialized done.
2427                  */
2428                 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING);
2429                 hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING,
2430                                   val | HCLGEVF_VF_RST_ING_BIT);
2431                 return HCLGEVF_VECTOR0_EVENT_RST;
2432         }
2433
2434         /* check for vector0 mailbox(=CMDQ RX) event source */
2435         if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
2436                 /* for revision 0x21, clearing interrupt is writing bit 0
2437                  * to the clear register, writing bit 1 means to keep the
2438                  * old value.
2439                  * for revision 0x20, the clear register is a read & write
2440                  * register, so we should just write 0 to the bit we are
2441                  * handling, and keep other bits as cmdq_stat_reg.
2442                  */
2443                 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
2444                         *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
2445                 else
2446                         *clearval = cmdq_stat_reg &
2447                                     ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
2448
2449                 return HCLGEVF_VECTOR0_EVENT_MBX;
2450         }
2451
2452         /* print other vector0 event source */
2453         dev_info(&hdev->pdev->dev,
2454                  "vector 0 interrupt from unknown source, cmdq_src = %#x\n",
2455                  cmdq_stat_reg);
2456
2457         return HCLGEVF_VECTOR0_EVENT_OTHER;
2458 }
2459
2460 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data)
2461 {
2462         enum hclgevf_evt_cause event_cause;
2463         struct hclgevf_dev *hdev = data;
2464         u32 clearval;
2465
2466         hclgevf_enable_vector(&hdev->misc_vector, false);
2467         event_cause = hclgevf_check_evt_cause(hdev, &clearval);
2468
2469         switch (event_cause) {
2470         case HCLGEVF_VECTOR0_EVENT_RST:
2471                 hclgevf_reset_task_schedule(hdev);
2472                 break;
2473         case HCLGEVF_VECTOR0_EVENT_MBX:
2474                 hclgevf_mbx_handler(hdev);
2475                 break;
2476         default:
2477                 break;
2478         }
2479
2480         if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) {
2481                 hclgevf_clear_event_cause(hdev, clearval);
2482                 hclgevf_enable_vector(&hdev->misc_vector, true);
2483         }
2484
2485         return IRQ_HANDLED;
2486 }
2487
2488 static int hclgevf_configure(struct hclgevf_dev *hdev)
2489 {
2490         int ret;
2491
2492         hdev->gro_en = true;
2493
2494         ret = hclgevf_get_basic_info(hdev);
2495         if (ret)
2496                 return ret;
2497
2498         /* get current port based vlan state from PF */
2499         ret = hclgevf_get_port_base_vlan_filter_state(hdev);
2500         if (ret)
2501                 return ret;
2502
2503         /* get queue configuration from PF */
2504         ret = hclgevf_get_queue_info(hdev);
2505         if (ret)
2506                 return ret;
2507
2508         /* get queue depth info from PF */
2509         ret = hclgevf_get_queue_depth(hdev);
2510         if (ret)
2511                 return ret;
2512
2513         return hclgevf_get_pf_media_type(hdev);
2514 }
2515
2516 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev)
2517 {
2518         struct pci_dev *pdev = ae_dev->pdev;
2519         struct hclgevf_dev *hdev;
2520
2521         hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
2522         if (!hdev)
2523                 return -ENOMEM;
2524
2525         hdev->pdev = pdev;
2526         hdev->ae_dev = ae_dev;
2527         ae_dev->priv = hdev;
2528
2529         return 0;
2530 }
2531
2532 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev)
2533 {
2534         struct hnae3_handle *roce = &hdev->roce;
2535         struct hnae3_handle *nic = &hdev->nic;
2536
2537         roce->rinfo.num_vectors = hdev->num_roce_msix;
2538
2539         if (hdev->num_msi_left < roce->rinfo.num_vectors ||
2540             hdev->num_msi_left == 0)
2541                 return -EINVAL;
2542
2543         roce->rinfo.base_vector = hdev->roce_base_vector;
2544
2545         roce->rinfo.netdev = nic->kinfo.netdev;
2546         roce->rinfo.roce_io_base = hdev->hw.io_base;
2547         roce->rinfo.roce_mem_base = hdev->hw.mem_base;
2548
2549         roce->pdev = nic->pdev;
2550         roce->ae_algo = nic->ae_algo;
2551         roce->numa_node_mask = nic->numa_node_mask;
2552
2553         return 0;
2554 }
2555
2556 static int hclgevf_config_gro(struct hclgevf_dev *hdev)
2557 {
2558         struct hclgevf_cfg_gro_status_cmd *req;
2559         struct hclgevf_desc desc;
2560         int ret;
2561
2562         if (!hnae3_dev_gro_supported(hdev))
2563                 return 0;
2564
2565         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG,
2566                                      false);
2567         req = (struct hclgevf_cfg_gro_status_cmd *)desc.data;
2568
2569         req->gro_en = hdev->gro_en ? 1 : 0;
2570
2571         ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
2572         if (ret)
2573                 dev_err(&hdev->pdev->dev,
2574                         "VF GRO hardware config cmd failed, ret = %d.\n", ret);
2575
2576         return ret;
2577 }
2578
2579 static int hclgevf_rss_init_cfg(struct hclgevf_dev *hdev)
2580 {
2581         u16 rss_ind_tbl_size = hdev->ae_dev->dev_specs.rss_ind_tbl_size;
2582         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
2583         struct hclgevf_rss_tuple_cfg *tuple_sets;
2584         u32 i;
2585
2586         rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ;
2587         rss_cfg->rss_size = hdev->nic.kinfo.rss_size;
2588         tuple_sets = &rss_cfg->rss_tuple_sets;
2589         if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
2590                 u8 *rss_ind_tbl;
2591
2592                 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE;
2593
2594                 rss_ind_tbl = devm_kcalloc(&hdev->pdev->dev, rss_ind_tbl_size,
2595                                            sizeof(*rss_ind_tbl), GFP_KERNEL);
2596                 if (!rss_ind_tbl)
2597                         return -ENOMEM;
2598
2599                 rss_cfg->rss_indirection_tbl = rss_ind_tbl;
2600                 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key,
2601                        HCLGEVF_RSS_KEY_SIZE);
2602
2603                 tuple_sets->ipv4_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2604                 tuple_sets->ipv4_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2605                 tuple_sets->ipv4_sctp_en = HCLGEVF_RSS_INPUT_TUPLE_SCTP;
2606                 tuple_sets->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2607                 tuple_sets->ipv6_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2608                 tuple_sets->ipv6_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2609                 tuple_sets->ipv6_sctp_en =
2610                         hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 ?
2611                                         HCLGEVF_RSS_INPUT_TUPLE_SCTP_NO_PORT :
2612                                         HCLGEVF_RSS_INPUT_TUPLE_SCTP;
2613                 tuple_sets->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2614         }
2615
2616         /* Initialize RSS indirect table */
2617         for (i = 0; i < rss_ind_tbl_size; i++)
2618                 rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size;
2619
2620         return 0;
2621 }
2622
2623 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev)
2624 {
2625         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
2626         int ret;
2627
2628         if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
2629                 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo,
2630                                                rss_cfg->rss_hash_key);
2631                 if (ret)
2632                         return ret;
2633
2634                 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg);
2635                 if (ret)
2636                         return ret;
2637         }
2638
2639         ret = hclgevf_set_rss_indir_table(hdev);
2640         if (ret)
2641                 return ret;
2642
2643         return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size);
2644 }
2645
2646 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev)
2647 {
2648         struct hnae3_handle *nic = &hdev->nic;
2649         int ret;
2650
2651         ret = hclgevf_en_hw_strip_rxvtag(nic, true);
2652         if (ret) {
2653                 dev_err(&hdev->pdev->dev,
2654                         "failed to enable rx vlan offload, ret = %d\n", ret);
2655                 return ret;
2656         }
2657
2658         return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0,
2659                                        false);
2660 }
2661
2662 static void hclgevf_flush_link_update(struct hclgevf_dev *hdev)
2663 {
2664 #define HCLGEVF_FLUSH_LINK_TIMEOUT      100000
2665
2666         unsigned long last = hdev->serv_processed_cnt;
2667         int i = 0;
2668
2669         while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) &&
2670                i++ < HCLGEVF_FLUSH_LINK_TIMEOUT &&
2671                last == hdev->serv_processed_cnt)
2672                 usleep_range(1, 1);
2673 }
2674
2675 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable)
2676 {
2677         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2678
2679         if (enable) {
2680                 hclgevf_task_schedule(hdev, 0);
2681         } else {
2682                 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2683
2684                 /* flush memory to make sure DOWN is seen by service task */
2685                 smp_mb__before_atomic();
2686                 hclgevf_flush_link_update(hdev);
2687         }
2688 }
2689
2690 static int hclgevf_ae_start(struct hnae3_handle *handle)
2691 {
2692         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2693
2694         clear_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2695         clear_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS, &hdev->state);
2696
2697         hclgevf_reset_tqp_stats(handle);
2698
2699         hclgevf_request_link_info(hdev);
2700
2701         hclgevf_update_link_mode(hdev);
2702
2703         return 0;
2704 }
2705
2706 static void hclgevf_ae_stop(struct hnae3_handle *handle)
2707 {
2708         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2709
2710         set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2711
2712         if (hdev->reset_type != HNAE3_VF_RESET)
2713                 hclgevf_reset_tqp(handle);
2714
2715         hclgevf_reset_tqp_stats(handle);
2716         hclgevf_update_link_status(hdev, 0);
2717 }
2718
2719 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive)
2720 {
2721 #define HCLGEVF_STATE_ALIVE     1
2722 #define HCLGEVF_STATE_NOT_ALIVE 0
2723
2724         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2725         struct hclge_vf_to_pf_msg send_msg;
2726
2727         hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0);
2728         send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE :
2729                                 HCLGEVF_STATE_NOT_ALIVE;
2730         return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
2731 }
2732
2733 static int hclgevf_client_start(struct hnae3_handle *handle)
2734 {
2735         return hclgevf_set_alive(handle, true);
2736 }
2737
2738 static void hclgevf_client_stop(struct hnae3_handle *handle)
2739 {
2740         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2741         int ret;
2742
2743         ret = hclgevf_set_alive(handle, false);
2744         if (ret)
2745                 dev_warn(&hdev->pdev->dev,
2746                          "%s failed %d\n", __func__, ret);
2747 }
2748
2749 static void hclgevf_state_init(struct hclgevf_dev *hdev)
2750 {
2751         clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
2752         clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
2753         clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
2754
2755         INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task);
2756
2757         mutex_init(&hdev->mbx_resp.mbx_mutex);
2758         sema_init(&hdev->reset_sem, 1);
2759
2760         spin_lock_init(&hdev->mac_table.mac_list_lock);
2761         INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list);
2762         INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list);
2763
2764         /* bring the device down */
2765         set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2766 }
2767
2768 static void hclgevf_state_uninit(struct hclgevf_dev *hdev)
2769 {
2770         set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2771         set_bit(HCLGEVF_STATE_REMOVING, &hdev->state);
2772
2773         if (hdev->service_task.work.func)
2774                 cancel_delayed_work_sync(&hdev->service_task);
2775
2776         mutex_destroy(&hdev->mbx_resp.mbx_mutex);
2777 }
2778
2779 static int hclgevf_init_msi(struct hclgevf_dev *hdev)
2780 {
2781         struct pci_dev *pdev = hdev->pdev;
2782         int vectors;
2783         int i;
2784
2785         if (hnae3_dev_roce_supported(hdev))
2786                 vectors = pci_alloc_irq_vectors(pdev,
2787                                                 hdev->roce_base_msix_offset + 1,
2788                                                 hdev->num_msi,
2789                                                 PCI_IRQ_MSIX);
2790         else
2791                 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM,
2792                                                 hdev->num_msi,
2793                                                 PCI_IRQ_MSI | PCI_IRQ_MSIX);
2794
2795         if (vectors < 0) {
2796                 dev_err(&pdev->dev,
2797                         "failed(%d) to allocate MSI/MSI-X vectors\n",
2798                         vectors);
2799                 return vectors;
2800         }
2801         if (vectors < hdev->num_msi)
2802                 dev_warn(&hdev->pdev->dev,
2803                          "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2804                          hdev->num_msi, vectors);
2805
2806         hdev->num_msi = vectors;
2807         hdev->num_msi_left = vectors;
2808
2809         hdev->base_msi_vector = pdev->irq;
2810         hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset;
2811
2812         hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2813                                            sizeof(u16), GFP_KERNEL);
2814         if (!hdev->vector_status) {
2815                 pci_free_irq_vectors(pdev);
2816                 return -ENOMEM;
2817         }
2818
2819         for (i = 0; i < hdev->num_msi; i++)
2820                 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT;
2821
2822         hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2823                                         sizeof(int), GFP_KERNEL);
2824         if (!hdev->vector_irq) {
2825                 devm_kfree(&pdev->dev, hdev->vector_status);
2826                 pci_free_irq_vectors(pdev);
2827                 return -ENOMEM;
2828         }
2829
2830         return 0;
2831 }
2832
2833 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev)
2834 {
2835         struct pci_dev *pdev = hdev->pdev;
2836
2837         devm_kfree(&pdev->dev, hdev->vector_status);
2838         devm_kfree(&pdev->dev, hdev->vector_irq);
2839         pci_free_irq_vectors(pdev);
2840 }
2841
2842 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev)
2843 {
2844         int ret;
2845
2846         hclgevf_get_misc_vector(hdev);
2847
2848         snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s",
2849                  HCLGEVF_NAME, pci_name(hdev->pdev));
2850         ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle,
2851                           0, hdev->misc_vector.name, hdev);
2852         if (ret) {
2853                 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n",
2854                         hdev->misc_vector.vector_irq);
2855                 return ret;
2856         }
2857
2858         hclgevf_clear_event_cause(hdev, 0);
2859
2860         /* enable misc. vector(vector 0) */
2861         hclgevf_enable_vector(&hdev->misc_vector, true);
2862
2863         return ret;
2864 }
2865
2866 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev)
2867 {
2868         /* disable misc vector(vector 0) */
2869         hclgevf_enable_vector(&hdev->misc_vector, false);
2870         synchronize_irq(hdev->misc_vector.vector_irq);
2871         free_irq(hdev->misc_vector.vector_irq, hdev);
2872         hclgevf_free_vector(hdev, 0);
2873 }
2874
2875 static void hclgevf_info_show(struct hclgevf_dev *hdev)
2876 {
2877         struct device *dev = &hdev->pdev->dev;
2878
2879         dev_info(dev, "VF info begin:\n");
2880
2881         dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps);
2882         dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc);
2883         dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc);
2884         dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport);
2885         dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map);
2886         dev_info(dev, "PF media type of this VF: %u\n",
2887                  hdev->hw.mac.media_type);
2888
2889         dev_info(dev, "VF info end.\n");
2890 }
2891
2892 static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev,
2893                                             struct hnae3_client *client)
2894 {
2895         struct hclgevf_dev *hdev = ae_dev->priv;
2896         int rst_cnt = hdev->rst_stats.rst_cnt;
2897         int ret;
2898
2899         ret = client->ops->init_instance(&hdev->nic);
2900         if (ret)
2901                 return ret;
2902
2903         set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);
2904         if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||
2905             rst_cnt != hdev->rst_stats.rst_cnt) {
2906                 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);
2907
2908                 client->ops->uninit_instance(&hdev->nic, 0);
2909                 return -EBUSY;
2910         }
2911
2912         hnae3_set_client_init_flag(client, ae_dev, 1);
2913
2914         if (netif_msg_drv(&hdev->nic))
2915                 hclgevf_info_show(hdev);
2916
2917         return 0;
2918 }
2919
2920 static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev,
2921                                              struct hnae3_client *client)
2922 {
2923         struct hclgevf_dev *hdev = ae_dev->priv;
2924         int ret;
2925
2926         if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client ||
2927             !hdev->nic_client)
2928                 return 0;
2929
2930         ret = hclgevf_init_roce_base_info(hdev);
2931         if (ret)
2932                 return ret;
2933
2934         ret = client->ops->init_instance(&hdev->roce);
2935         if (ret)
2936                 return ret;
2937
2938         set_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state);
2939         hnae3_set_client_init_flag(client, ae_dev, 1);
2940
2941         return 0;
2942 }
2943
2944 static int hclgevf_init_client_instance(struct hnae3_client *client,
2945                                         struct hnae3_ae_dev *ae_dev)
2946 {
2947         struct hclgevf_dev *hdev = ae_dev->priv;
2948         int ret;
2949
2950         switch (client->type) {
2951         case HNAE3_CLIENT_KNIC:
2952                 hdev->nic_client = client;
2953                 hdev->nic.client = client;
2954
2955                 ret = hclgevf_init_nic_client_instance(ae_dev, client);
2956                 if (ret)
2957                         goto clear_nic;
2958
2959                 ret = hclgevf_init_roce_client_instance(ae_dev,
2960                                                         hdev->roce_client);
2961                 if (ret)
2962                         goto clear_roce;
2963
2964                 break;
2965         case HNAE3_CLIENT_ROCE:
2966                 if (hnae3_dev_roce_supported(hdev)) {
2967                         hdev->roce_client = client;
2968                         hdev->roce.client = client;
2969                 }
2970
2971                 ret = hclgevf_init_roce_client_instance(ae_dev, client);
2972                 if (ret)
2973                         goto clear_roce;
2974
2975                 break;
2976         default:
2977                 return -EINVAL;
2978         }
2979
2980         return 0;
2981
2982 clear_nic:
2983         hdev->nic_client = NULL;
2984         hdev->nic.client = NULL;
2985         return ret;
2986 clear_roce:
2987         hdev->roce_client = NULL;
2988         hdev->roce.client = NULL;
2989         return ret;
2990 }
2991
2992 static void hclgevf_uninit_client_instance(struct hnae3_client *client,
2993                                            struct hnae3_ae_dev *ae_dev)
2994 {
2995         struct hclgevf_dev *hdev = ae_dev->priv;
2996
2997         /* un-init roce, if it exists */
2998         if (hdev->roce_client) {
2999                 clear_bit(HCLGEVF_STATE_ROCE_REGISTERED, &hdev->state);
3000                 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0);
3001                 hdev->roce_client = NULL;
3002                 hdev->roce.client = NULL;
3003         }
3004
3005         /* un-init nic/unic, if this was not called by roce client */
3006         if (client->ops->uninit_instance && hdev->nic_client &&
3007             client->type != HNAE3_CLIENT_ROCE) {
3008                 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);
3009
3010                 client->ops->uninit_instance(&hdev->nic, 0);
3011                 hdev->nic_client = NULL;
3012                 hdev->nic.client = NULL;
3013         }
3014 }
3015
3016 static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev)
3017 {
3018 #define HCLGEVF_MEM_BAR         4
3019
3020         struct pci_dev *pdev = hdev->pdev;
3021         struct hclgevf_hw *hw = &hdev->hw;
3022
3023         /* for device does not have device memory, return directly */
3024         if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR)))
3025                 return 0;
3026
3027         hw->mem_base = devm_ioremap_wc(&pdev->dev,
3028                                        pci_resource_start(pdev,
3029                                                           HCLGEVF_MEM_BAR),
3030                                        pci_resource_len(pdev, HCLGEVF_MEM_BAR));
3031         if (!hw->mem_base) {
3032                 dev_err(&pdev->dev, "failed to map device memory\n");
3033                 return -EFAULT;
3034         }
3035
3036         return 0;
3037 }
3038
3039 static int hclgevf_pci_init(struct hclgevf_dev *hdev)
3040 {
3041         struct pci_dev *pdev = hdev->pdev;
3042         struct hclgevf_hw *hw;
3043         int ret;
3044
3045         ret = pci_enable_device(pdev);
3046         if (ret) {
3047                 dev_err(&pdev->dev, "failed to enable PCI device\n");
3048                 return ret;
3049         }
3050
3051         ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3052         if (ret) {
3053                 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting");
3054                 goto err_disable_device;
3055         }
3056
3057         ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME);
3058         if (ret) {
3059                 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
3060                 goto err_disable_device;
3061         }
3062
3063         pci_set_master(pdev);
3064         hw = &hdev->hw;
3065         hw->hdev = hdev;
3066         hw->io_base = pci_iomap(pdev, 2, 0);
3067         if (!hw->io_base) {
3068                 dev_err(&pdev->dev, "can't map configuration register space\n");
3069                 ret = -ENOMEM;
3070                 goto err_clr_master;
3071         }
3072
3073         ret = hclgevf_dev_mem_map(hdev);
3074         if (ret)
3075                 goto err_unmap_io_base;
3076
3077         return 0;
3078
3079 err_unmap_io_base:
3080         pci_iounmap(pdev, hdev->hw.io_base);
3081 err_clr_master:
3082         pci_clear_master(pdev);
3083         pci_release_regions(pdev);
3084 err_disable_device:
3085         pci_disable_device(pdev);
3086
3087         return ret;
3088 }
3089
3090 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev)
3091 {
3092         struct pci_dev *pdev = hdev->pdev;
3093
3094         if (hdev->hw.mem_base)
3095                 devm_iounmap(&pdev->dev, hdev->hw.mem_base);
3096
3097         pci_iounmap(pdev, hdev->hw.io_base);
3098         pci_clear_master(pdev);
3099         pci_release_regions(pdev);
3100         pci_disable_device(pdev);
3101 }
3102
3103 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev)
3104 {
3105         struct hclgevf_query_res_cmd *req;
3106         struct hclgevf_desc desc;
3107         int ret;
3108
3109         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true);
3110         ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
3111         if (ret) {
3112                 dev_err(&hdev->pdev->dev,
3113                         "query vf resource failed, ret = %d.\n", ret);
3114                 return ret;
3115         }
3116
3117         req = (struct hclgevf_query_res_cmd *)desc.data;
3118
3119         if (hnae3_dev_roce_supported(hdev)) {
3120                 hdev->roce_base_msix_offset =
3121                 hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee),
3122                                 HCLGEVF_MSIX_OFT_ROCEE_M,
3123                                 HCLGEVF_MSIX_OFT_ROCEE_S);
3124                 hdev->num_roce_msix =
3125                 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number),
3126                                 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
3127
3128                 /* nic's msix numbers is always equals to the roce's. */
3129                 hdev->num_nic_msix = hdev->num_roce_msix;
3130
3131                 /* VF should have NIC vectors and Roce vectors, NIC vectors
3132                  * are queued before Roce vectors. The offset is fixed to 64.
3133                  */
3134                 hdev->num_msi = hdev->num_roce_msix +
3135                                 hdev->roce_base_msix_offset;
3136         } else {
3137                 hdev->num_msi =
3138                 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number),
3139                                 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
3140
3141                 hdev->num_nic_msix = hdev->num_msi;
3142         }
3143
3144         if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) {
3145                 dev_err(&hdev->pdev->dev,
3146                         "Just %u msi resources, not enough for vf(min:2).\n",
3147                         hdev->num_nic_msix);
3148                 return -EINVAL;
3149         }
3150
3151         return 0;
3152 }
3153
3154 static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev)
3155 {
3156 #define HCLGEVF_MAX_NON_TSO_BD_NUM                      8U
3157
3158         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
3159
3160         ae_dev->dev_specs.max_non_tso_bd_num =
3161                                         HCLGEVF_MAX_NON_TSO_BD_NUM;
3162         ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE;
3163         ae_dev->dev_specs.rss_key_size = HCLGEVF_RSS_KEY_SIZE;
3164         ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL;
3165         ae_dev->dev_specs.max_frm_size = HCLGEVF_MAC_MAX_FRAME;
3166 }
3167
3168 static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev,
3169                                     struct hclgevf_desc *desc)
3170 {
3171         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
3172         struct hclgevf_dev_specs_0_cmd *req0;
3173         struct hclgevf_dev_specs_1_cmd *req1;
3174
3175         req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data;
3176         req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data;
3177
3178         ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num;
3179         ae_dev->dev_specs.rss_ind_tbl_size =
3180                                         le16_to_cpu(req0->rss_ind_tbl_size);
3181         ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max);
3182         ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size);
3183         ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl);
3184         ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size);
3185 }
3186
3187 static void hclgevf_check_dev_specs(struct hclgevf_dev *hdev)
3188 {
3189         struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs;
3190
3191         if (!dev_specs->max_non_tso_bd_num)
3192                 dev_specs->max_non_tso_bd_num = HCLGEVF_MAX_NON_TSO_BD_NUM;
3193         if (!dev_specs->rss_ind_tbl_size)
3194                 dev_specs->rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE;
3195         if (!dev_specs->rss_key_size)
3196                 dev_specs->rss_key_size = HCLGEVF_RSS_KEY_SIZE;
3197         if (!dev_specs->max_int_gl)
3198                 dev_specs->max_int_gl = HCLGEVF_DEF_MAX_INT_GL;
3199         if (!dev_specs->max_frm_size)
3200                 dev_specs->max_frm_size = HCLGEVF_MAC_MAX_FRAME;
3201 }
3202
3203 static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev)
3204 {
3205         struct hclgevf_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM];
3206         int ret;
3207         int i;
3208
3209         /* set default specifications as devices lower than version V3 do not
3210          * support querying specifications from firmware.
3211          */
3212         if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) {
3213                 hclgevf_set_default_dev_specs(hdev);
3214                 return 0;
3215         }
3216
3217         for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3218                 hclgevf_cmd_setup_basic_desc(&desc[i],
3219                                              HCLGEVF_OPC_QUERY_DEV_SPECS, true);
3220                 desc[i].flag |= cpu_to_le16(HCLGEVF_CMD_FLAG_NEXT);
3221         }
3222         hclgevf_cmd_setup_basic_desc(&desc[i], HCLGEVF_OPC_QUERY_DEV_SPECS,
3223                                      true);
3224
3225         ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM);
3226         if (ret)
3227                 return ret;
3228
3229         hclgevf_parse_dev_specs(hdev, desc);
3230         hclgevf_check_dev_specs(hdev);
3231
3232         return 0;
3233 }
3234
3235 static int hclgevf_pci_reset(struct hclgevf_dev *hdev)
3236 {
3237         struct pci_dev *pdev = hdev->pdev;
3238         int ret = 0;
3239
3240         if (hdev->reset_type == HNAE3_VF_FULL_RESET &&
3241             test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
3242                 hclgevf_misc_irq_uninit(hdev);
3243                 hclgevf_uninit_msi(hdev);
3244                 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
3245         }
3246
3247         if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
3248                 pci_set_master(pdev);
3249                 ret = hclgevf_init_msi(hdev);
3250                 if (ret) {
3251                         dev_err(&pdev->dev,
3252                                 "failed(%d) to init MSI/MSI-X\n", ret);
3253                         return ret;
3254                 }
3255
3256                 ret = hclgevf_misc_irq_init(hdev);
3257                 if (ret) {
3258                         hclgevf_uninit_msi(hdev);
3259                         dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n",
3260                                 ret);
3261                         return ret;
3262                 }
3263
3264                 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
3265         }
3266
3267         return ret;
3268 }
3269
3270 static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev)
3271 {
3272         struct hclge_vf_to_pf_msg send_msg;
3273
3274         hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL,
3275                                HCLGE_MBX_VPORT_LIST_CLEAR);
3276         return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
3277 }
3278
3279 static void hclgevf_init_rxd_adv_layout(struct hclgevf_dev *hdev)
3280 {
3281         if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev))
3282                 hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 1);
3283 }
3284
3285 static void hclgevf_uninit_rxd_adv_layout(struct hclgevf_dev *hdev)
3286 {
3287         if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev))
3288                 hclgevf_write_dev(&hdev->hw, HCLGEVF_RXD_ADV_LAYOUT_EN_REG, 0);
3289 }
3290
3291 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev)
3292 {
3293         struct pci_dev *pdev = hdev->pdev;
3294         int ret;
3295
3296         ret = hclgevf_pci_reset(hdev);
3297         if (ret) {
3298                 dev_err(&pdev->dev, "pci reset failed %d\n", ret);
3299                 return ret;
3300         }
3301
3302         ret = hclgevf_cmd_init(hdev);
3303         if (ret) {
3304                 dev_err(&pdev->dev, "cmd failed %d\n", ret);
3305                 return ret;
3306         }
3307
3308         ret = hclgevf_rss_init_hw(hdev);
3309         if (ret) {
3310                 dev_err(&hdev->pdev->dev,
3311                         "failed(%d) to initialize RSS\n", ret);
3312                 return ret;
3313         }
3314
3315         ret = hclgevf_config_gro(hdev);
3316         if (ret)
3317                 return ret;
3318
3319         ret = hclgevf_init_vlan_config(hdev);
3320         if (ret) {
3321                 dev_err(&hdev->pdev->dev,
3322                         "failed(%d) to initialize VLAN config\n", ret);
3323                 return ret;
3324         }
3325
3326         set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);
3327
3328         hclgevf_init_rxd_adv_layout(hdev);
3329
3330         dev_info(&hdev->pdev->dev, "Reset done\n");
3331
3332         return 0;
3333 }
3334
3335 static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
3336 {
3337         struct pci_dev *pdev = hdev->pdev;
3338         int ret;
3339
3340         ret = hclgevf_pci_init(hdev);
3341         if (ret)
3342                 return ret;
3343
3344         ret = hclgevf_devlink_init(hdev);
3345         if (ret)
3346                 goto err_devlink_init;
3347
3348         ret = hclgevf_cmd_queue_init(hdev);
3349         if (ret)
3350                 goto err_cmd_queue_init;
3351
3352         ret = hclgevf_cmd_init(hdev);
3353         if (ret)
3354                 goto err_cmd_init;
3355
3356         /* Get vf resource */
3357         ret = hclgevf_query_vf_resource(hdev);
3358         if (ret)
3359                 goto err_cmd_init;
3360
3361         ret = hclgevf_query_dev_specs(hdev);
3362         if (ret) {
3363                 dev_err(&pdev->dev,
3364                         "failed to query dev specifications, ret = %d\n", ret);
3365                 goto err_cmd_init;
3366         }
3367
3368         ret = hclgevf_init_msi(hdev);
3369         if (ret) {
3370                 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret);
3371                 goto err_cmd_init;
3372         }
3373
3374         hclgevf_state_init(hdev);
3375         hdev->reset_level = HNAE3_VF_FUNC_RESET;
3376         hdev->reset_type = HNAE3_NONE_RESET;
3377
3378         ret = hclgevf_misc_irq_init(hdev);
3379         if (ret)
3380                 goto err_misc_irq_init;
3381
3382         set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
3383
3384         ret = hclgevf_configure(hdev);
3385         if (ret) {
3386                 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret);
3387                 goto err_config;
3388         }
3389
3390         ret = hclgevf_alloc_tqps(hdev);
3391         if (ret) {
3392                 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret);
3393                 goto err_config;
3394         }
3395
3396         ret = hclgevf_set_handle_info(hdev);
3397         if (ret)
3398                 goto err_config;
3399
3400         ret = hclgevf_config_gro(hdev);
3401         if (ret)
3402                 goto err_config;
3403
3404         /* Initialize RSS for this VF */
3405         ret = hclgevf_rss_init_cfg(hdev);
3406         if (ret) {
3407                 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret);
3408                 goto err_config;
3409         }
3410
3411         ret = hclgevf_rss_init_hw(hdev);
3412         if (ret) {
3413                 dev_err(&hdev->pdev->dev,
3414                         "failed(%d) to initialize RSS\n", ret);
3415                 goto err_config;
3416         }
3417
3418         /* ensure vf tbl list as empty before init*/
3419         ret = hclgevf_clear_vport_list(hdev);
3420         if (ret) {
3421                 dev_err(&pdev->dev,
3422                         "failed to clear tbl list configuration, ret = %d.\n",
3423                         ret);
3424                 goto err_config;
3425         }
3426
3427         ret = hclgevf_init_vlan_config(hdev);
3428         if (ret) {
3429                 dev_err(&hdev->pdev->dev,
3430                         "failed(%d) to initialize VLAN config\n", ret);
3431                 goto err_config;
3432         }
3433
3434         hclgevf_init_rxd_adv_layout(hdev);
3435
3436         hdev->last_reset_time = jiffies;
3437         dev_info(&hdev->pdev->dev, "finished initializing %s driver\n",
3438                  HCLGEVF_DRIVER_NAME);
3439
3440         hclgevf_task_schedule(hdev, round_jiffies_relative(HZ));
3441
3442         return 0;
3443
3444 err_config:
3445         hclgevf_misc_irq_uninit(hdev);
3446 err_misc_irq_init:
3447         hclgevf_state_uninit(hdev);
3448         hclgevf_uninit_msi(hdev);
3449 err_cmd_init:
3450         hclgevf_cmd_uninit(hdev);
3451 err_cmd_queue_init:
3452         hclgevf_devlink_uninit(hdev);
3453 err_devlink_init:
3454         hclgevf_pci_uninit(hdev);
3455         clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
3456         return ret;
3457 }
3458
3459 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev)
3460 {
3461         struct hclge_vf_to_pf_msg send_msg;
3462
3463         hclgevf_state_uninit(hdev);
3464         hclgevf_uninit_rxd_adv_layout(hdev);
3465
3466         hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0);
3467         hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
3468
3469         if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
3470                 hclgevf_misc_irq_uninit(hdev);
3471                 hclgevf_uninit_msi(hdev);
3472         }
3473
3474         hclgevf_cmd_uninit(hdev);
3475         hclgevf_devlink_uninit(hdev);
3476         hclgevf_pci_uninit(hdev);
3477         hclgevf_uninit_mac_list(hdev);
3478 }
3479
3480 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev)
3481 {
3482         struct pci_dev *pdev = ae_dev->pdev;
3483         int ret;
3484
3485         ret = hclgevf_alloc_hdev(ae_dev);
3486         if (ret) {
3487                 dev_err(&pdev->dev, "hclge device allocation failed\n");
3488                 return ret;
3489         }
3490
3491         ret = hclgevf_init_hdev(ae_dev->priv);
3492         if (ret) {
3493                 dev_err(&pdev->dev, "hclge device initialization failed\n");
3494                 return ret;
3495         }
3496
3497         return 0;
3498 }
3499
3500 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
3501 {
3502         struct hclgevf_dev *hdev = ae_dev->priv;
3503
3504         hclgevf_uninit_hdev(hdev);
3505         ae_dev->priv = NULL;
3506 }
3507
3508 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev)
3509 {
3510         struct hnae3_handle *nic = &hdev->nic;
3511         struct hnae3_knic_private_info *kinfo = &nic->kinfo;
3512
3513         return min_t(u32, hdev->rss_size_max,
3514                      hdev->num_tqps / kinfo->tc_info.num_tc);
3515 }
3516
3517 /**
3518  * hclgevf_get_channels - Get the current channels enabled and max supported.
3519  * @handle: hardware information for network interface
3520  * @ch: ethtool channels structure
3521  *
3522  * We don't support separate tx and rx queues as channels. The other count
3523  * represents how many queues are being used for control. max_combined counts
3524  * how many queue pairs we can support. They may not be mapped 1 to 1 with
3525  * q_vectors since we support a lot more queue pairs than q_vectors.
3526  **/
3527 static void hclgevf_get_channels(struct hnae3_handle *handle,
3528                                  struct ethtool_channels *ch)
3529 {
3530         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3531
3532         ch->max_combined = hclgevf_get_max_channels(hdev);
3533         ch->other_count = 0;
3534         ch->max_other = 0;
3535         ch->combined_count = handle->kinfo.rss_size;
3536 }
3537
3538 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle,
3539                                           u16 *alloc_tqps, u16 *max_rss_size)
3540 {
3541         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3542
3543         *alloc_tqps = hdev->num_tqps;
3544         *max_rss_size = hdev->rss_size_max;
3545 }
3546
3547 static void hclgevf_update_rss_size(struct hnae3_handle *handle,
3548                                     u32 new_tqps_num)
3549 {
3550         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3551         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3552         u16 max_rss_size;
3553
3554         kinfo->req_rss_size = new_tqps_num;
3555
3556         max_rss_size = min_t(u16, hdev->rss_size_max,
3557                              hdev->num_tqps / kinfo->tc_info.num_tc);
3558
3559         /* Use the user's configuration when it is not larger than
3560          * max_rss_size, otherwise, use the maximum specification value.
3561          */
3562         if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size &&
3563             kinfo->req_rss_size <= max_rss_size)
3564                 kinfo->rss_size = kinfo->req_rss_size;
3565         else if (kinfo->rss_size > max_rss_size ||
3566                  (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size))
3567                 kinfo->rss_size = max_rss_size;
3568
3569         kinfo->num_tqps = kinfo->tc_info.num_tc * kinfo->rss_size;
3570 }
3571
3572 static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num,
3573                                 bool rxfh_configured)
3574 {
3575         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3576         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3577         u16 cur_rss_size = kinfo->rss_size;
3578         u16 cur_tqps = kinfo->num_tqps;
3579         u32 *rss_indir;
3580         unsigned int i;
3581         int ret;
3582
3583         hclgevf_update_rss_size(handle, new_tqps_num);
3584
3585         ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size);
3586         if (ret)
3587                 return ret;
3588
3589         /* RSS indirection table has been configured by user */
3590         if (rxfh_configured)
3591                 goto out;
3592
3593         /* Reinitializes the rss indirect table according to the new RSS size */
3594         rss_indir = kcalloc(hdev->ae_dev->dev_specs.rss_ind_tbl_size,
3595                             sizeof(u32), GFP_KERNEL);
3596         if (!rss_indir)
3597                 return -ENOMEM;
3598
3599         for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++)
3600                 rss_indir[i] = i % kinfo->rss_size;
3601
3602         hdev->rss_cfg.rss_size = kinfo->rss_size;
3603
3604         ret = hclgevf_set_rss(handle, rss_indir, NULL, 0);
3605         if (ret)
3606                 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
3607                         ret);
3608
3609         kfree(rss_indir);
3610
3611 out:
3612         if (!ret)
3613                 dev_info(&hdev->pdev->dev,
3614                          "Channels changed, rss_size from %u to %u, tqps from %u to %u",
3615                          cur_rss_size, kinfo->rss_size,
3616                          cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc);
3617
3618         return ret;
3619 }
3620
3621 static int hclgevf_get_status(struct hnae3_handle *handle)
3622 {
3623         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3624
3625         return hdev->hw.mac.link;
3626 }
3627
3628 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle,
3629                                             u8 *auto_neg, u32 *speed,
3630                                             u8 *duplex)
3631 {
3632         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3633
3634         if (speed)
3635                 *speed = hdev->hw.mac.speed;
3636         if (duplex)
3637                 *duplex = hdev->hw.mac.duplex;
3638         if (auto_neg)
3639                 *auto_neg = AUTONEG_DISABLE;
3640 }
3641
3642 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
3643                                  u8 duplex)
3644 {
3645         hdev->hw.mac.speed = speed;
3646         hdev->hw.mac.duplex = duplex;
3647 }
3648
3649 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable)
3650 {
3651         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3652         bool gro_en_old = hdev->gro_en;
3653         int ret;
3654
3655         hdev->gro_en = enable;
3656         ret = hclgevf_config_gro(hdev);
3657         if (ret)
3658                 hdev->gro_en = gro_en_old;
3659
3660         return ret;
3661 }
3662
3663 static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type,
3664                                    u8 *module_type)
3665 {
3666         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3667
3668         if (media_type)
3669                 *media_type = hdev->hw.mac.media_type;
3670
3671         if (module_type)
3672                 *module_type = hdev->hw.mac.module_type;
3673 }
3674
3675 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle)
3676 {
3677         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3678
3679         return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
3680 }
3681
3682 static bool hclgevf_get_cmdq_stat(struct hnae3_handle *handle)
3683 {
3684         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3685
3686         return test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
3687 }
3688
3689 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle)
3690 {
3691         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3692
3693         return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
3694 }
3695
3696 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle)
3697 {
3698         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3699
3700         return hdev->rst_stats.hw_rst_done_cnt;
3701 }
3702
3703 static void hclgevf_get_link_mode(struct hnae3_handle *handle,
3704                                   unsigned long *supported,
3705                                   unsigned long *advertising)
3706 {
3707         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3708
3709         *supported = hdev->hw.mac.supported;
3710         *advertising = hdev->hw.mac.advertising;
3711 }
3712
3713 #define MAX_SEPARATE_NUM        4
3714 #define SEPARATOR_VALUE         0xFDFCFBFA
3715 #define REG_NUM_PER_LINE        4
3716 #define REG_LEN_PER_LINE        (REG_NUM_PER_LINE * sizeof(u32))
3717
3718 static int hclgevf_get_regs_len(struct hnae3_handle *handle)
3719 {
3720         int cmdq_lines, common_lines, ring_lines, tqp_intr_lines;
3721         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3722
3723         cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1;
3724         common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1;
3725         ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1;
3726         tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1;
3727
3728         return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps +
3729                 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE;
3730 }
3731
3732 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version,
3733                              void *data)
3734 {
3735         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3736         int i, j, reg_um, separator_num;
3737         u32 *reg = data;
3738
3739         *version = hdev->fw_version;
3740
3741         /* fetching per-VF registers values from VF PCIe register space */
3742         reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32);
3743         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
3744         for (i = 0; i < reg_um; i++)
3745                 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]);
3746         for (i = 0; i < separator_num; i++)
3747                 *reg++ = SEPARATOR_VALUE;
3748
3749         reg_um = sizeof(common_reg_addr_list) / sizeof(u32);
3750         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
3751         for (i = 0; i < reg_um; i++)
3752                 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]);
3753         for (i = 0; i < separator_num; i++)
3754                 *reg++ = SEPARATOR_VALUE;
3755
3756         reg_um = sizeof(ring_reg_addr_list) / sizeof(u32);
3757         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
3758         for (j = 0; j < hdev->num_tqps; j++) {
3759                 for (i = 0; i < reg_um; i++)
3760                         *reg++ = hclgevf_read_dev(&hdev->hw,
3761                                                   ring_reg_addr_list[i] +
3762                                                   0x200 * j);
3763                 for (i = 0; i < separator_num; i++)
3764                         *reg++ = SEPARATOR_VALUE;
3765         }
3766
3767         reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32);
3768         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
3769         for (j = 0; j < hdev->num_msi_used - 1; j++) {
3770                 for (i = 0; i < reg_um; i++)
3771                         *reg++ = hclgevf_read_dev(&hdev->hw,
3772                                                   tqp_intr_reg_addr_list[i] +
3773                                                   4 * j);
3774                 for (i = 0; i < separator_num; i++)
3775                         *reg++ = SEPARATOR_VALUE;
3776         }
3777 }
3778
3779 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state,
3780                                         u8 *port_base_vlan_info, u8 data_size)
3781 {
3782         struct hnae3_handle *nic = &hdev->nic;
3783         struct hclge_vf_to_pf_msg send_msg;
3784         int ret;
3785
3786         rtnl_lock();
3787
3788         if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||
3789             test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) {
3790                 dev_warn(&hdev->pdev->dev,
3791                          "is resetting when updating port based vlan info\n");
3792                 rtnl_unlock();
3793                 return;
3794         }
3795
3796         ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);
3797         if (ret) {
3798                 rtnl_unlock();
3799                 return;
3800         }
3801
3802         /* send msg to PF and wait update port based vlan info */
3803         hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
3804                                HCLGE_MBX_PORT_BASE_VLAN_CFG);
3805         memcpy(send_msg.data, port_base_vlan_info, data_size);
3806         ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
3807         if (!ret) {
3808                 if (state == HNAE3_PORT_BASE_VLAN_DISABLE)
3809                         nic->port_base_vlan_state = state;
3810                 else
3811                         nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE;
3812         }
3813
3814         hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
3815         rtnl_unlock();
3816 }
3817
3818 static const struct hnae3_ae_ops hclgevf_ops = {
3819         .init_ae_dev = hclgevf_init_ae_dev,
3820         .uninit_ae_dev = hclgevf_uninit_ae_dev,
3821         .reset_prepare = hclgevf_reset_prepare_general,
3822         .reset_done = hclgevf_reset_done,
3823         .init_client_instance = hclgevf_init_client_instance,
3824         .uninit_client_instance = hclgevf_uninit_client_instance,
3825         .start = hclgevf_ae_start,
3826         .stop = hclgevf_ae_stop,
3827         .client_start = hclgevf_client_start,
3828         .client_stop = hclgevf_client_stop,
3829         .map_ring_to_vector = hclgevf_map_ring_to_vector,
3830         .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector,
3831         .get_vector = hclgevf_get_vector,
3832         .put_vector = hclgevf_put_vector,
3833         .reset_queue = hclgevf_reset_tqp,
3834         .get_mac_addr = hclgevf_get_mac_addr,
3835         .set_mac_addr = hclgevf_set_mac_addr,
3836         .add_uc_addr = hclgevf_add_uc_addr,
3837         .rm_uc_addr = hclgevf_rm_uc_addr,
3838         .add_mc_addr = hclgevf_add_mc_addr,
3839         .rm_mc_addr = hclgevf_rm_mc_addr,
3840         .get_stats = hclgevf_get_stats,
3841         .update_stats = hclgevf_update_stats,
3842         .get_strings = hclgevf_get_strings,
3843         .get_sset_count = hclgevf_get_sset_count,
3844         .get_rss_key_size = hclgevf_get_rss_key_size,
3845         .get_rss = hclgevf_get_rss,
3846         .set_rss = hclgevf_set_rss,
3847         .get_rss_tuple = hclgevf_get_rss_tuple,
3848         .set_rss_tuple = hclgevf_set_rss_tuple,
3849         .get_tc_size = hclgevf_get_tc_size,
3850         .get_fw_version = hclgevf_get_fw_version,
3851         .set_vlan_filter = hclgevf_set_vlan_filter,
3852         .enable_vlan_filter = hclgevf_enable_vlan_filter,
3853         .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag,
3854         .reset_event = hclgevf_reset_event,
3855         .set_default_reset_request = hclgevf_set_def_reset_request,
3856         .set_channels = hclgevf_set_channels,
3857         .get_channels = hclgevf_get_channels,
3858         .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info,
3859         .get_regs_len = hclgevf_get_regs_len,
3860         .get_regs = hclgevf_get_regs,
3861         .get_status = hclgevf_get_status,
3862         .get_ksettings_an_result = hclgevf_get_ksettings_an_result,
3863         .get_media_type = hclgevf_get_media_type,
3864         .get_hw_reset_stat = hclgevf_get_hw_reset_stat,
3865         .ae_dev_resetting = hclgevf_ae_dev_resetting,
3866         .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt,
3867         .set_gro_en = hclgevf_gro_en,
3868         .set_mtu = hclgevf_set_mtu,
3869         .get_global_queue_id = hclgevf_get_qid_global,
3870         .set_timer_task = hclgevf_set_timer_task,
3871         .get_link_mode = hclgevf_get_link_mode,
3872         .set_promisc_mode = hclgevf_set_promisc_mode,
3873         .request_update_promisc_mode = hclgevf_request_update_promisc_mode,
3874         .get_cmdq_stat = hclgevf_get_cmdq_stat,
3875 };
3876
3877 static struct hnae3_ae_algo ae_algovf = {
3878         .ops = &hclgevf_ops,
3879         .pdev_id_table = ae_algovf_pci_tbl,
3880 };
3881
3882 static int hclgevf_init(void)
3883 {
3884         pr_info("%s is initializing\n", HCLGEVF_NAME);
3885
3886         hclgevf_wq = alloc_workqueue("%s", 0, 0, HCLGEVF_NAME);
3887         if (!hclgevf_wq) {
3888                 pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME);
3889                 return -ENOMEM;
3890         }
3891
3892         hnae3_register_ae_algo(&ae_algovf);
3893
3894         return 0;
3895 }
3896
3897 static void hclgevf_exit(void)
3898 {
3899         hnae3_unregister_ae_algo(&ae_algovf);
3900         destroy_workqueue(hclgevf_wq);
3901 }
3902 module_init(hclgevf_init);
3903 module_exit(hclgevf_exit);
3904
3905 MODULE_LICENSE("GPL");
3906 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
3907 MODULE_DESCRIPTION("HCLGEVF Driver");
3908 MODULE_VERSION(HCLGEVF_MOD_VERSION);