drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #include <linux/device.h>
   5 #include <linux/dma-direction.h>
   6 #include <linux/dma-mapping.h>
   7 #include <linux/err.h>
   8 #include <linux/pci.h>
   9 #include <linux/slab.h>
  10 #include "hclgevf_cmd.h"
  11 #include "hclgevf_main.h"
  12 #include "hnae3.h"
  13
  14 #define hclgevf_is_csq(ring) ((ring)->flag & HCLGEVF_TYPE_CSQ)
  15 #define hclgevf_ring_to_dma_dir(ring) (hclgevf_is_csq(ring) ? \
  16                                         DMA_TO_DEVICE : DMA_FROM_DEVICE)
  17 #define cmq_ring_to_dev(ring)   (&(ring)->dev->pdev->dev)
  18
  19 static int hclgevf_ring_space(struct hclgevf_cmq_ring *ring)
  20 {
  21         int ntc = ring->next_to_clean;
  22         int ntu = ring->next_to_use;
  23         int used;
  24
  25         used = (ntu - ntc + ring->desc_num) % ring->desc_num;
  26
  27         return ring->desc_num - used - 1;
  28 }
  29
  30 static int hclgevf_cmd_csq_clean(struct hclgevf_hw *hw)
  31 {
  32         struct hclgevf_cmq_ring *csq = &hw->cmq.csq;
  33         u16 ntc = csq->next_to_clean;
  34         struct hclgevf_desc *desc;
  35         int clean = 0;
  36         u32 head;
  37
  38         desc = &csq->desc[ntc];
  39         head = hclgevf_read_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG);
  40         while (head != ntc) {
  41                 memset(desc, 0, sizeof(*desc));
  42                 ntc++;
  43                 if (ntc == csq->desc_num)
  44                         ntc = 0;
  45                 desc = &csq->desc[ntc];
  46                 clean++;
  47         }
  48         csq->next_to_clean = ntc;
  49
  50         return clean;
  51 }
  52
  53 static bool hclgevf_cmd_csq_done(struct hclgevf_hw *hw)
  54 {
  55         u32 head;
  56
  57         head = hclgevf_read_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG);
  58
  59         return head == hw->cmq.csq.next_to_use;
  60 }
  61
  62 static bool hclgevf_is_special_opcode(u16 opcode)
  63 {
  64         u16 spec_opcode[] = {0x30, 0x31, 0x32};
  65         int i;
  66
  67         for (i = 0; i < ARRAY_SIZE(spec_opcode); i++) {
  68                 if (spec_opcode[i] == opcode)
  69                         return true;
  70         }
  71
  72         return false;
  73 }
  74
  75 static void hclgevf_cmd_config_regs(struct hclgevf_cmq_ring *ring)
  76 {
  77         struct hclgevf_dev *hdev = ring->dev;
  78         struct hclgevf_hw *hw = &hdev->hw;
  79         u32 reg_val;
  80
  81         if (ring->flag == HCLGEVF_TYPE_CSQ) {
  82                 reg_val = (u32)ring->desc_dma_addr;
  83                 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_L_REG, reg_val);
  84                 reg_val = (u32)((ring->desc_dma_addr >> 31) >> 1);
  85                 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_H_REG, reg_val);
  86
  87                 reg_val = (ring->desc_num >> HCLGEVF_NIC_CMQ_DESC_NUM_S);
  88                 reg_val |= HCLGEVF_NIC_CMQ_ENABLE;
  89                 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_DEPTH_REG, reg_val);
  90
  91                 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG, 0);
  92                 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_TAIL_REG, 0);
  93         } else {
  94                 reg_val = (u32)ring->desc_dma_addr;
  95                 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_L_REG, reg_val);
  96                 reg_val = (u32)((ring->desc_dma_addr >> 31) >> 1);
  97                 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_H_REG, reg_val);
  98
  99                 reg_val = (ring->desc_num >> HCLGEVF_NIC_CMQ_DESC_NUM_S);
 100                 reg_val |= HCLGEVF_NIC_CMQ_ENABLE;
 101                 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_DEPTH_REG, reg_val);
 102
 103                 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_HEAD_REG, 0);
 104                 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_TAIL_REG, 0);
 105         }
 106 }
 107
 108 static void hclgevf_cmd_init_regs(struct hclgevf_hw *hw)
 109 {
 110         hclgevf_cmd_config_regs(&hw->cmq.csq);
 111         hclgevf_cmd_config_regs(&hw->cmq.crq);
 112 }
 113
 114 static int hclgevf_alloc_cmd_desc(struct hclgevf_cmq_ring *ring)
 115 {
 116         int size = ring->desc_num * sizeof(struct hclgevf_desc);
 117
 118         ring->desc = dma_zalloc_coherent(cmq_ring_to_dev(ring),
 119                                          size, &ring->desc_dma_addr,
 120                                          GFP_KERNEL);
 121         if (!ring->desc)
 122                 return -ENOMEM;
 123
 124         return 0;
 125 }
 126
 127 static void hclgevf_free_cmd_desc(struct hclgevf_cmq_ring *ring)
 128 {
 129         int size  = ring->desc_num * sizeof(struct hclgevf_desc);
 130
 131         if (ring->desc) {
 132                 dma_free_coherent(cmq_ring_to_dev(ring), size,
 133                                   ring->desc, ring->desc_dma_addr);
 134                 ring->desc = NULL;
 135         }
 136 }
 137
 138 static int hclgevf_alloc_cmd_queue(struct hclgevf_dev *hdev, int ring_type)
 139 {
 140         struct hclgevf_hw *hw = &hdev->hw;
 141         struct hclgevf_cmq_ring *ring =
 142                 (ring_type == HCLGEVF_TYPE_CSQ) ? &hw->cmq.csq : &hw->cmq.crq;
 143         int ret;
 144
 145         ring->dev = hdev;
 146         ring->flag = ring_type;
 147
 148         /* allocate CSQ/CRQ descriptor */
 149         ret = hclgevf_alloc_cmd_desc(ring);
 150         if (ret)
 151                 dev_err(&hdev->pdev->dev, "failed(%d) to alloc %s desc\n", ret,
 152                         (ring_type == HCLGEVF_TYPE_CSQ) ? "CSQ" : "CRQ");
 153
 154         return ret;
 155 }
 156
 157 void hclgevf_cmd_setup_basic_desc(struct hclgevf_desc *desc,
 158                                   enum hclgevf_opcode_type opcode, bool is_read)
 159 {
 160         memset(desc, 0, sizeof(struct hclgevf_desc));
 161         desc->opcode = cpu_to_le16(opcode);
 162         desc->flag = cpu_to_le16(HCLGEVF_CMD_FLAG_NO_INTR |
 163                                  HCLGEVF_CMD_FLAG_IN);
 164         if (is_read)
 165                 desc->flag |= cpu_to_le16(HCLGEVF_CMD_FLAG_WR);
 166         else
 167                 desc->flag &= cpu_to_le16(~HCLGEVF_CMD_FLAG_WR);
 168 }
 169
 170 /* hclgevf_cmd_send - send command to command queue
 171  * @hw: pointer to the hw struct
 172  * @desc: prefilled descriptor for describing the command
 173  * @num : the number of descriptors to be sent
 174  *
 175  * This is the main send command for command queue, it
 176  * sends the queue, cleans the queue, etc
 177  */
 178 int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclgevf_desc *desc, int num)
 179 {
 180         struct hclgevf_dev *hdev = (struct hclgevf_dev *)hw->hdev;
 181         struct hclgevf_desc *desc_to_use;
 182         bool complete = false;
 183         u32 timeout = 0;
 184         int handle = 0;
 185         int status = 0;
 186         u16 retval;
 187         u16 opcode;
 188         int ntc;
 189
 190         spin_lock_bh(&hw->cmq.csq.lock);
 191
 192         if (num > hclgevf_ring_space(&hw->cmq.csq) ||
 193             test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) {
 194                 spin_unlock_bh(&hw->cmq.csq.lock);
 195                 return -EBUSY;
 196         }
 197
 198         /* Record the location of desc in the ring for this time
 199          * which will be use for hardware to write back
 200          */
 201         ntc = hw->cmq.csq.next_to_use;
 202         opcode = le16_to_cpu(desc[0].opcode);
 203         while (handle < num) {
 204                 desc_to_use = &hw->cmq.csq.desc[hw->cmq.csq.next_to_use];
 205                 *desc_to_use = desc[handle];
 206                 (hw->cmq.csq.next_to_use)++;
 207                 if (hw->cmq.csq.next_to_use == hw->cmq.csq.desc_num)
 208                         hw->cmq.csq.next_to_use = 0;
 209                 handle++;
 210         }
 211
 212         /* Write to hardware */
 213         hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_TAIL_REG,
 214                           hw->cmq.csq.next_to_use);
 215
 216         /* If the command is sync, wait for the firmware to write back,
 217          * if multi descriptors to be sent, use the first one to check
 218          */
 219         if (HCLGEVF_SEND_SYNC(le16_to_cpu(desc->flag))) {
 220                 do {
 221                         if (hclgevf_cmd_csq_done(hw))
 222                                 break;
 223                         udelay(1);
 224                         timeout++;
 225                 } while (timeout < hw->cmq.tx_timeout);
 226         }
 227
 228         if (hclgevf_cmd_csq_done(hw)) {
 229                 complete = true;
 230                 handle = 0;
 231
 232                 while (handle < num) {
 233                         /* Get the result of hardware write back */
 234                         desc_to_use = &hw->cmq.csq.desc[ntc];
 235                         desc[handle] = *desc_to_use;
 236
 237                         if (likely(!hclgevf_is_special_opcode(opcode)))
 238                                 retval = le16_to_cpu(desc[handle].retval);
 239                         else
 240                                 retval = le16_to_cpu(desc[0].retval);
 241
 242                         if ((enum hclgevf_cmd_return_status)retval ==
 243                             HCLGEVF_CMD_EXEC_SUCCESS)
 244                                 status = 0;
 245                         else
 246                                 status = -EIO;
 247                         hw->cmq.last_status = (enum hclgevf_cmd_status)retval;
 248                         ntc++;
 249                         handle++;
 250                         if (ntc == hw->cmq.csq.desc_num)
 251                                 ntc = 0;
 252                 }
 253         }
 254
 255         if (!complete)
 256                 status = -EAGAIN;
 257
 258         /* Clean the command send queue */
 259         handle = hclgevf_cmd_csq_clean(hw);
 260         if (handle != num) {
 261                 dev_warn(&hdev->pdev->dev,
 262                          "cleaned %d, need to clean %d\n", handle, num);
 263         }
 264
 265         spin_unlock_bh(&hw->cmq.csq.lock);
 266
 267         return status;
 268 }
 269
 270 static int  hclgevf_cmd_query_firmware_version(struct hclgevf_hw *hw,
 271                                                u32 *version)
 272 {
 273         struct hclgevf_query_version_cmd *resp;
 274         struct hclgevf_desc desc;
 275         int status;
 276
 277         resp = (struct hclgevf_query_version_cmd *)desc.data;
 278
 279         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_FW_VER, 1);
 280         status = hclgevf_cmd_send(hw, &desc, 1);
 281         if (!status)
 282                 *version = le32_to_cpu(resp->firmware);
 283
 284         return status;
 285 }
 286
 287 int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev)
 288 {
 289         int ret;
 290
 291         /* Setup the lock for command queue */
 292         spin_lock_init(&hdev->hw.cmq.csq.lock);
 293         spin_lock_init(&hdev->hw.cmq.crq.lock);
 294
 295         hdev->hw.cmq.tx_timeout = HCLGEVF_CMDQ_TX_TIMEOUT;
 296         hdev->hw.cmq.csq.desc_num = HCLGEVF_NIC_CMQ_DESC_NUM;
 297         hdev->hw.cmq.crq.desc_num = HCLGEVF_NIC_CMQ_DESC_NUM;
 298
 299         ret = hclgevf_alloc_cmd_queue(hdev, HCLGEVF_TYPE_CSQ);
 300         if (ret) {
 301                 dev_err(&hdev->pdev->dev,
 302                         "CSQ ring setup error %d\n", ret);
 303                 return ret;
 304         }
 305
 306         ret = hclgevf_alloc_cmd_queue(hdev, HCLGEVF_TYPE_CRQ);
 307         if (ret) {
 308                 dev_err(&hdev->pdev->dev,
 309                         "CRQ ring setup error %d\n", ret);
 310                 goto err_csq;
 311         }
 312
 313         return 0;
 314 err_csq:
 315         hclgevf_free_cmd_desc(&hdev->hw.cmq.csq);
 316         return ret;
 317 }
 318
 319 int hclgevf_cmd_init(struct hclgevf_dev *hdev)
 320 {
 321         u32 version;
 322         int ret;
 323
 324         spin_lock_bh(&hdev->hw.cmq.csq.lock);
 325         spin_lock_bh(&hdev->hw.cmq.crq.lock);
 326
 327         /* initialize the pointers of async rx queue of mailbox */
 328         hdev->arq.hdev = hdev;
 329         hdev->arq.head = 0;
 330         hdev->arq.tail = 0;
 331         hdev->arq.count = 0;
 332         hdev->hw.cmq.csq.next_to_clean = 0;
 333         hdev->hw.cmq.csq.next_to_use = 0;
 334         hdev->hw.cmq.crq.next_to_clean = 0;
 335         hdev->hw.cmq.crq.next_to_use = 0;
 336
 337         hclgevf_cmd_init_regs(&hdev->hw);
 338
 339         spin_unlock_bh(&hdev->hw.cmq.crq.lock);
 340         spin_unlock_bh(&hdev->hw.cmq.csq.lock);
 341
 342         clear_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
 343
 344         /* Check if there is new reset pending, because the higher level
 345          * reset may happen when lower level reset is being processed.
 346          */
 347         if (hclgevf_is_reset_pending(hdev)) {
 348                 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
 349                 return -EBUSY;
 350         }
 351
 352         /* get firmware version */
 353         ret = hclgevf_cmd_query_firmware_version(&hdev->hw, &version);
 354         if (ret) {
 355                 dev_err(&hdev->pdev->dev,
 356                         "failed(%d) to query firmware version\n", ret);
 357                 return ret;
 358         }
 359         hdev->fw_version = version;
 360
 361         dev_info(&hdev->pdev->dev, "The firmware version is %08x\n", version);
 362
 363         return 0;
 364 }
 365
 366 void hclgevf_cmd_uninit(struct hclgevf_dev *hdev)
 367 {
 368         hclgevf_free_cmd_desc(&hdev->hw.cmq.csq);
 369         hclgevf_free_cmd_desc(&hdev->hw.cmq.crq);
 370 }