drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #include "hclge_main.h"
   5 #include "hclge_dcb.h"
   6 #include "hclge_tm.h"
   7 #include "hnae3.h"
   8
   9 #define BW_PERCENT      100
  10
  11 static int hclge_ieee_ets_to_tm_info(struct hclge_dev *hdev,
  12                                      struct ieee_ets *ets)
  13 {
  14         u8 i;
  15
  16         for (i = 0; i < HNAE3_MAX_TC; i++) {
  17                 switch (ets->tc_tsa[i]) {
  18                 case IEEE_8021QAZ_TSA_STRICT:
  19                         hdev->tm_info.tc_info[i].tc_sch_mode =
  20                                 HCLGE_SCH_MODE_SP;
  21                         hdev->tm_info.pg_info[0].tc_dwrr[i] = 0;
  22                         break;
  23                 case IEEE_8021QAZ_TSA_ETS:
  24                         hdev->tm_info.tc_info[i].tc_sch_mode =
  25                                 HCLGE_SCH_MODE_DWRR;
  26                         hdev->tm_info.pg_info[0].tc_dwrr[i] =
  27                                 ets->tc_tx_bw[i];
  28                         break;
  29                 default:
  30                         /* Hardware only supports SP (strict priority)
  31                          * or ETS (enhanced transmission selection)
  32                          * algorithms, if we receive some other value
  33                          * from dcbnl, then throw an error.
  34                          */
  35                         return -EINVAL;
  36                 }
  37         }
  38
  39         hclge_tm_prio_tc_info_update(hdev, ets->prio_tc);
  40
  41         return 0;
  42 }
  43
  44 static void hclge_tm_info_to_ieee_ets(struct hclge_dev *hdev,
  45                                       struct ieee_ets *ets)
  46 {
  47         u32 i;
  48
  49         memset(ets, 0, sizeof(*ets));
  50         ets->willing = 1;
  51         ets->ets_cap = hdev->tc_max;
  52
  53         for (i = 0; i < HNAE3_MAX_TC; i++) {
  54                 ets->prio_tc[i] = hdev->tm_info.prio_tc[i];
  55                 ets->tc_tx_bw[i] = hdev->tm_info.pg_info[0].tc_dwrr[i];
  56
  57                 if (hdev->tm_info.tc_info[i].tc_sch_mode ==
  58                     HCLGE_SCH_MODE_SP)
  59                         ets->tc_tsa[i] = IEEE_8021QAZ_TSA_STRICT;
  60                 else
  61                         ets->tc_tsa[i] = IEEE_8021QAZ_TSA_ETS;
  62         }
  63 }
  64
  65 /* IEEE std */
  66 static int hclge_ieee_getets(struct hnae3_handle *h, struct ieee_ets *ets)
  67 {
  68         struct hclge_vport *vport = hclge_get_vport(h);
  69         struct hclge_dev *hdev = vport->back;
  70
  71         hclge_tm_info_to_ieee_ets(hdev, ets);
  72
  73         return 0;
  74 }
  75
  76 static int hclge_dcb_common_validate(struct hclge_dev *hdev, u8 num_tc,
  77                                      u8 *prio_tc)
  78 {
  79         int i;
  80
  81         if (num_tc > hdev->tc_max) {
  82                 dev_err(&hdev->pdev->dev,
  83                         "tc num checking failed, %u > tc_max(%u)\n",
  84                         num_tc, hdev->tc_max);
  85                 return -EINVAL;
  86         }
  87
  88         for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
  89                 if (prio_tc[i] >= num_tc) {
  90                         dev_err(&hdev->pdev->dev,
  91                                 "prio_tc[%d] checking failed, %u >= num_tc(%u)\n",
  92                                 i, prio_tc[i], num_tc);
  93                         return -EINVAL;
  94                 }
  95         }
  96
  97         if (num_tc > hdev->vport[0].alloc_tqps) {
  98                 dev_err(&hdev->pdev->dev,
  99                         "allocated tqp checking failed, %u > tqp(%u)\n",
 100                         num_tc, hdev->vport[0].alloc_tqps);
 101                 return -EINVAL;
 102         }
 103
 104         return 0;
 105 }
 106
 107 static int hclge_ets_validate(struct hclge_dev *hdev, struct ieee_ets *ets,
 108                               u8 *tc, bool *changed)
 109 {
 110         bool has_ets_tc = false;
 111         u32 total_ets_bw = 0;
 112         u8 max_tc = 0;
 113         int ret;
 114         u8 i;
 115
 116         for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
 117                 if (ets->prio_tc[i] != hdev->tm_info.prio_tc[i])
 118                         *changed = true;
 119
 120                 if (ets->prio_tc[i] > max_tc)
 121                         max_tc = ets->prio_tc[i];
 122         }
 123
 124         ret = hclge_dcb_common_validate(hdev, max_tc + 1, ets->prio_tc);
 125         if (ret)
 126                 return ret;
 127
 128         for (i = 0; i < hdev->tc_max; i++) {
 129                 switch (ets->tc_tsa[i]) {
 130                 case IEEE_8021QAZ_TSA_STRICT:
 131                         if (hdev->tm_info.tc_info[i].tc_sch_mode !=
 132                                 HCLGE_SCH_MODE_SP)
 133                                 *changed = true;
 134                         break;
 135                 case IEEE_8021QAZ_TSA_ETS:
 136                         if (hdev->tm_info.tc_info[i].tc_sch_mode !=
 137                                 HCLGE_SCH_MODE_DWRR)
 138                                 *changed = true;
 139
 140                         total_ets_bw += ets->tc_tx_bw[i];
 141                         has_ets_tc = true;
 142                         break;
 143                 default:
 144                         return -EINVAL;
 145                 }
 146         }
 147
 148         if (has_ets_tc && total_ets_bw != BW_PERCENT)
 149                 return -EINVAL;
 150
 151         *tc = max_tc + 1;
 152         if (*tc != hdev->tm_info.num_tc)
 153                 *changed = true;
 154
 155         return 0;
 156 }
 157
 158 static int hclge_map_update(struct hclge_dev *hdev)
 159 {
 160         int ret;
 161
 162         ret = hclge_tm_schd_setup_hw(hdev);
 163         if (ret)
 164                 return ret;
 165
 166         ret = hclge_pause_setup_hw(hdev, false);
 167         if (ret)
 168                 return ret;
 169
 170         ret = hclge_buffer_alloc(hdev);
 171         if (ret)
 172                 return ret;
 173
 174         hclge_rss_indir_init_cfg(hdev);
 175
 176         return hclge_rss_init_hw(hdev);
 177 }
 178
 179 static int hclge_client_setup_tc(struct hclge_dev *hdev)
 180 {
 181         struct hclge_vport *vport = hdev->vport;
 182         struct hnae3_client *client;
 183         struct hnae3_handle *handle;
 184         int ret;
 185         u32 i;
 186
 187         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
 188                 handle = &vport[i].nic;
 189                 client = handle->client;
 190
 191                 if (!client || !client->ops || !client->ops->setup_tc)
 192                         continue;
 193
 194                 ret = client->ops->setup_tc(handle, hdev->tm_info.num_tc);
 195                 if (ret)
 196                         return ret;
 197         }
 198
 199         return 0;
 200 }
 201
 202 static int hclge_notify_down_uinit(struct hclge_dev *hdev)
 203 {
 204         int ret;
 205
 206         ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
 207         if (ret)
 208                 return ret;
 209
 210         return hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
 211 }
 212
 213 static int hclge_notify_init_up(struct hclge_dev *hdev)
 214 {
 215         int ret;
 216
 217         ret = hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
 218         if (ret)
 219                 return ret;
 220
 221         return hclge_notify_client(hdev, HNAE3_UP_CLIENT);
 222 }
 223
 224 static int hclge_ieee_setets(struct hnae3_handle *h, struct ieee_ets *ets)
 225 {
 226         struct hclge_vport *vport = hclge_get_vport(h);
 227         struct net_device *netdev = h->kinfo.netdev;
 228         struct hclge_dev *hdev = vport->back;
 229         bool map_changed = false;
 230         u8 num_tc = 0;
 231         int ret;
 232
 233         if (!(hdev->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) ||
 234             hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE)
 235                 return -EINVAL;
 236
 237         ret = hclge_ets_validate(hdev, ets, &num_tc, &map_changed);
 238         if (ret)
 239                 return ret;
 240
 241         if (map_changed) {
 242                 netif_dbg(h, drv, netdev, "set ets\n");
 243
 244                 ret = hclge_notify_down_uinit(hdev);
 245                 if (ret)
 246                         return ret;
 247         }
 248
 249         hclge_tm_schd_info_update(hdev, num_tc);
 250
 251         ret = hclge_ieee_ets_to_tm_info(hdev, ets);
 252         if (ret)
 253                 goto err_out;
 254
 255         if (map_changed) {
 256                 ret = hclge_map_update(hdev);
 257                 if (ret)
 258                         goto err_out;
 259
 260                 ret = hclge_client_setup_tc(hdev);
 261                 if (ret)
 262                         goto err_out;
 263
 264                 ret = hclge_notify_init_up(hdev);
 265                 if (ret)
 266                         return ret;
 267         }
 268
 269         return hclge_tm_dwrr_cfg(hdev);
 270
 271 err_out:
 272         if (!map_changed)
 273                 return ret;
 274
 275         hclge_notify_init_up(hdev);
 276
 277         return ret;
 278 }
 279
 280 static int hclge_ieee_getpfc(struct hnae3_handle *h, struct ieee_pfc *pfc)
 281 {
 282         u64 requests[HNAE3_MAX_TC], indications[HNAE3_MAX_TC];
 283         struct hclge_vport *vport = hclge_get_vport(h);
 284         struct hclge_dev *hdev = vport->back;
 285         u8 i, j, pfc_map, *prio_tc;
 286         int ret;
 287
 288         memset(pfc, 0, sizeof(*pfc));
 289         pfc->pfc_cap = hdev->pfc_max;
 290         prio_tc = hdev->tm_info.prio_tc;
 291         pfc_map = hdev->tm_info.hw_pfc_map;
 292
 293         /* Pfc setting is based on TC */
 294         for (i = 0; i < hdev->tm_info.num_tc; i++) {
 295                 for (j = 0; j < HNAE3_MAX_USER_PRIO; j++) {
 296                         if ((prio_tc[j] == i) && (pfc_map & BIT(i)))
 297                                 pfc->pfc_en |= BIT(j);
 298                 }
 299         }
 300
 301         ret = hclge_pfc_tx_stats_get(hdev, requests);
 302         if (ret)
 303                 return ret;
 304
 305         ret = hclge_pfc_rx_stats_get(hdev, indications);
 306         if (ret)
 307                 return ret;
 308
 309         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
 310                 pfc->requests[i] = requests[i];
 311                 pfc->indications[i] = indications[i];
 312         }
 313         return 0;
 314 }
 315
 316 static int hclge_ieee_setpfc(struct hnae3_handle *h, struct ieee_pfc *pfc)
 317 {
 318         struct hclge_vport *vport = hclge_get_vport(h);
 319         struct net_device *netdev = h->kinfo.netdev;
 320         struct hclge_dev *hdev = vport->back;
 321         u8 i, j, pfc_map, *prio_tc;
 322         int ret;
 323
 324         if (!(hdev->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) ||
 325             hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE)
 326                 return -EINVAL;
 327
 328         if (pfc->pfc_en == hdev->tm_info.pfc_en)
 329                 return 0;
 330
 331         prio_tc = hdev->tm_info.prio_tc;
 332         pfc_map = 0;
 333
 334         for (i = 0; i < hdev->tm_info.num_tc; i++) {
 335                 for (j = 0; j < HNAE3_MAX_USER_PRIO; j++) {
 336                         if ((prio_tc[j] == i) && (pfc->pfc_en & BIT(j))) {
 337                                 pfc_map |= BIT(i);
 338                                 break;
 339                         }
 340                 }
 341         }
 342
 343         hdev->tm_info.hw_pfc_map = pfc_map;
 344         hdev->tm_info.pfc_en = pfc->pfc_en;
 345
 346         netif_dbg(h, drv, netdev,
 347                   "set pfc: pfc_en=%x, pfc_map=%x, num_tc=%u\n",
 348                   pfc->pfc_en, pfc_map, hdev->tm_info.num_tc);
 349
 350         hclge_tm_pfc_info_update(hdev);
 351
 352         ret = hclge_pause_setup_hw(hdev, false);
 353         if (ret)
 354                 return ret;
 355
 356         ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
 357         if (ret)
 358                 return ret;
 359
 360         ret = hclge_buffer_alloc(hdev);
 361         if (ret) {
 362                 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
 363                 return ret;
 364         }
 365
 366         return hclge_notify_client(hdev, HNAE3_UP_CLIENT);
 367 }
 368
 369 /* DCBX configuration */
 370 static u8 hclge_getdcbx(struct hnae3_handle *h)
 371 {
 372         struct hclge_vport *vport = hclge_get_vport(h);
 373         struct hclge_dev *hdev = vport->back;
 374
 375         if (hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE)
 376                 return 0;
 377
 378         return hdev->dcbx_cap;
 379 }
 380
 381 static u8 hclge_setdcbx(struct hnae3_handle *h, u8 mode)
 382 {
 383         struct hclge_vport *vport = hclge_get_vport(h);
 384         struct net_device *netdev = h->kinfo.netdev;
 385         struct hclge_dev *hdev = vport->back;
 386
 387         netif_dbg(h, drv, netdev, "set dcbx: mode=%u\n", mode);
 388
 389         /* No support for LLD_MANAGED modes or CEE */
 390         if ((mode & DCB_CAP_DCBX_LLD_MANAGED) ||
 391             (mode & DCB_CAP_DCBX_VER_CEE) ||
 392             !(mode & DCB_CAP_DCBX_HOST))
 393                 return 1;
 394
 395         hdev->dcbx_cap = mode;
 396
 397         return 0;
 398 }
 399
 400 static int hclge_mqprio_qopt_check(struct hclge_dev *hdev,
 401                                    struct tc_mqprio_qopt_offload *mqprio_qopt)
 402 {
 403         u16 queue_sum = 0;
 404         int ret;
 405         int i;
 406
 407         if (!mqprio_qopt->qopt.num_tc) {
 408                 mqprio_qopt->qopt.num_tc = 1;
 409                 return 0;
 410         }
 411
 412         ret = hclge_dcb_common_validate(hdev, mqprio_qopt->qopt.num_tc,
 413                                         mqprio_qopt->qopt.prio_tc_map);
 414         if (ret)
 415                 return ret;
 416
 417         for (i = 0; i < mqprio_qopt->qopt.num_tc; i++) {
 418                 if (!is_power_of_2(mqprio_qopt->qopt.count[i])) {
 419                         dev_err(&hdev->pdev->dev,
 420                                 "qopt queue count must be power of 2\n");
 421                         return -EINVAL;
 422                 }
 423
 424                 if (mqprio_qopt->qopt.count[i] > hdev->rss_size_max) {
 425                         dev_err(&hdev->pdev->dev,
 426                                 "qopt queue count should be no more than %u\n",
 427                                 hdev->rss_size_max);
 428                         return -EINVAL;
 429                 }
 430
 431                 if (mqprio_qopt->qopt.offset[i] != queue_sum) {
 432                         dev_err(&hdev->pdev->dev,
 433                                 "qopt queue offset must start from 0, and being continuous\n");
 434                         return -EINVAL;
 435                 }
 436
 437                 if (mqprio_qopt->min_rate[i] || mqprio_qopt->max_rate[i]) {
 438                         dev_err(&hdev->pdev->dev,
 439                                 "qopt tx_rate is not supported\n");
 440                         return -EOPNOTSUPP;
 441                 }
 442
 443                 queue_sum = mqprio_qopt->qopt.offset[i];
 444                 queue_sum += mqprio_qopt->qopt.count[i];
 445         }
 446         if (hdev->vport[0].alloc_tqps < queue_sum) {
 447                 dev_err(&hdev->pdev->dev,
 448                         "qopt queue count sum should be less than %u\n",
 449                         hdev->vport[0].alloc_tqps);
 450                 return -EINVAL;
 451         }
 452
 453         return 0;
 454 }
 455
 456 static void hclge_sync_mqprio_qopt(struct hnae3_tc_info *tc_info,
 457                                    struct tc_mqprio_qopt_offload *mqprio_qopt)
 458 {
 459         int i;
 460
 461         memset(tc_info, 0, sizeof(*tc_info));
 462         tc_info->num_tc = mqprio_qopt->qopt.num_tc;
 463         memcpy(tc_info->prio_tc, mqprio_qopt->qopt.prio_tc_map,
 464                sizeof_field(struct hnae3_tc_info, prio_tc));
 465         memcpy(tc_info->tqp_count, mqprio_qopt->qopt.count,
 466                sizeof_field(struct hnae3_tc_info, tqp_count));
 467         memcpy(tc_info->tqp_offset, mqprio_qopt->qopt.offset,
 468                sizeof_field(struct hnae3_tc_info, tqp_offset));
 469
 470         for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
 471                 set_bit(tc_info->prio_tc[i], &tc_info->tc_en);
 472 }
 473
 474 static int hclge_config_tc(struct hclge_dev *hdev,
 475                            struct hnae3_tc_info *tc_info)
 476 {
 477         int i;
 478
 479         hclge_tm_schd_info_update(hdev, tc_info->num_tc);
 480         for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
 481                 hdev->tm_info.prio_tc[i] = tc_info->prio_tc[i];
 482
 483         return hclge_map_update(hdev);
 484 }
 485
 486 /* Set up TC for hardware offloaded mqprio in channel mode */
 487 static int hclge_setup_tc(struct hnae3_handle *h,
 488                           struct tc_mqprio_qopt_offload *mqprio_qopt)
 489 {
 490         struct hclge_vport *vport = hclge_get_vport(h);
 491         struct hnae3_knic_private_info *kinfo;
 492         struct hclge_dev *hdev = vport->back;
 493         struct hnae3_tc_info old_tc_info;
 494         u8 tc = mqprio_qopt->qopt.num_tc;
 495         int ret;
 496
 497         /* if client unregistered, it's not allowed to change
 498          * mqprio configuration, which may cause uninit ring
 499          * fail.
 500          */
 501         if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state))
 502                 return -EBUSY;
 503
 504         if (hdev->flag & HCLGE_FLAG_DCB_ENABLE)
 505                 return -EINVAL;
 506
 507         ret = hclge_mqprio_qopt_check(hdev, mqprio_qopt);
 508         if (ret) {
 509                 dev_err(&hdev->pdev->dev,
 510                         "failed to check mqprio qopt params, ret = %d\n", ret);
 511                 return ret;
 512         }
 513
 514         ret = hclge_notify_down_uinit(hdev);
 515         if (ret)
 516                 return ret;
 517
 518         kinfo = &vport->nic.kinfo;
 519         memcpy(&old_tc_info, &kinfo->tc_info, sizeof(old_tc_info));
 520         hclge_sync_mqprio_qopt(&kinfo->tc_info, mqprio_qopt);
 521         kinfo->tc_info.mqprio_active = tc > 0;
 522
 523         ret = hclge_config_tc(hdev, &kinfo->tc_info);
 524         if (ret)
 525                 goto err_out;
 526
 527         hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE;
 528
 529         if (tc > 1)
 530                 hdev->flag |= HCLGE_FLAG_MQPRIO_ENABLE;
 531         else
 532                 hdev->flag &= ~HCLGE_FLAG_MQPRIO_ENABLE;
 533
 534         return hclge_notify_init_up(hdev);
 535
 536 err_out:
 537         /* roll-back */
 538         memcpy(&kinfo->tc_info, &old_tc_info, sizeof(old_tc_info));
 539         if (hclge_config_tc(hdev, &kinfo->tc_info))
 540                 dev_err(&hdev->pdev->dev,
 541                         "failed to roll back tc configuration\n");
 542
 543         hclge_notify_init_up(hdev);
 544
 545         return ret;
 546 }
 547
 548 static const struct hnae3_dcb_ops hns3_dcb_ops = {
 549         .ieee_getets    = hclge_ieee_getets,
 550         .ieee_setets    = hclge_ieee_setets,
 551         .ieee_getpfc    = hclge_ieee_getpfc,
 552         .ieee_setpfc    = hclge_ieee_setpfc,
 553         .getdcbx        = hclge_getdcbx,
 554         .setdcbx        = hclge_setdcbx,
 555         .setup_tc       = hclge_setup_tc,
 556 };
 557
 558 void hclge_dcb_ops_set(struct hclge_dev *hdev)
 559 {
 560         struct hclge_vport *vport = hdev->vport;
 561         struct hnae3_knic_private_info *kinfo;
 562
 563         /* Hdev does not support DCB or vport is
 564          * not a pf, then dcb_ops is not set.
 565          */
 566         if (!hnae3_dev_dcb_supported(hdev) ||
 567             vport->vport_id != 0)
 568                 return;
 569
 570         kinfo = &vport->nic.kinfo;
 571         kinfo->dcb_ops = &hns3_dcb_ops;
 572         hdev->dcbx_cap = DCB_CAP_DCBX_VER_IEEE | DCB_CAP_DCBX_HOST;
 573 }