drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #ifndef __HCLGE_CMD_H
   5 #define __HCLGE_CMD_H
   6 #include <linux/types.h>
   7 #include <linux/io.h>
   8 #include <linux/etherdevice.h>
   9 #include "hnae3.h"
  10
  11 #define HCLGE_CMDQ_TX_TIMEOUT           30000
  12 #define HCLGE_DESC_DATA_LEN             6
  13
  14 struct hclge_dev;
  15 struct hclge_desc {
  16         __le16 opcode;
  17
  18 #define HCLGE_CMDQ_RX_INVLD_B           0
  19 #define HCLGE_CMDQ_RX_OUTVLD_B          1
  20
  21         __le16 flag;
  22         __le16 retval;
  23         __le16 rsv;
  24         __le32 data[HCLGE_DESC_DATA_LEN];
  25 };
  26
  27 struct hclge_cmq_ring {
  28         dma_addr_t desc_dma_addr;
  29         struct hclge_desc *desc;
  30         struct hclge_dev *dev;
  31         u32 head;
  32         u32 tail;
  33
  34         u16 buf_size;
  35         u16 desc_num;
  36         int next_to_use;
  37         int next_to_clean;
  38         u8 ring_type; /* cmq ring type */
  39         spinlock_t lock; /* Command queue lock */
  40 };
  41
  42 enum hclge_cmd_return_status {
  43         HCLGE_CMD_EXEC_SUCCESS  = 0,
  44         HCLGE_CMD_NO_AUTH       = 1,
  45         HCLGE_CMD_NOT_SUPPORTED = 2,
  46         HCLGE_CMD_QUEUE_FULL    = 3,
  47         HCLGE_CMD_NEXT_ERR      = 4,
  48         HCLGE_CMD_UNEXE_ERR     = 5,
  49         HCLGE_CMD_PARA_ERR      = 6,
  50         HCLGE_CMD_RESULT_ERR    = 7,
  51         HCLGE_CMD_TIMEOUT       = 8,
  52         HCLGE_CMD_HILINK_ERR    = 9,
  53         HCLGE_CMD_QUEUE_ILLEGAL = 10,
  54         HCLGE_CMD_INVALID       = 11,
  55 };
  56
  57 enum hclge_cmd_status {
  58         HCLGE_STATUS_SUCCESS    = 0,
  59         HCLGE_ERR_CSQ_FULL      = -1,
  60         HCLGE_ERR_CSQ_TIMEOUT   = -2,
  61         HCLGE_ERR_CSQ_ERROR     = -3,
  62 };
  63
  64 struct hclge_misc_vector {
  65         u8 __iomem *addr;
  66         int vector_irq;
  67         char name[HNAE3_INT_NAME_LEN];
  68 };
  69
  70 struct hclge_cmq {
  71         struct hclge_cmq_ring csq;
  72         struct hclge_cmq_ring crq;
  73         u16 tx_timeout;
  74         enum hclge_cmd_status last_status;
  75 };
  76
  77 #define HCLGE_CMD_FLAG_IN       BIT(0)
  78 #define HCLGE_CMD_FLAG_OUT      BIT(1)
  79 #define HCLGE_CMD_FLAG_NEXT     BIT(2)
  80 #define HCLGE_CMD_FLAG_WR       BIT(3)
  81 #define HCLGE_CMD_FLAG_NO_INTR  BIT(4)
  82 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5)
  83
  84 enum hclge_opcode_type {
  85         /* Generic commands */
  86         HCLGE_OPC_QUERY_FW_VER          = 0x0001,
  87         HCLGE_OPC_CFG_RST_TRIGGER       = 0x0020,
  88         HCLGE_OPC_GBL_RST_STATUS        = 0x0021,
  89         HCLGE_OPC_QUERY_FUNC_STATUS     = 0x0022,
  90         HCLGE_OPC_QUERY_PF_RSRC         = 0x0023,
  91         HCLGE_OPC_QUERY_VF_RSRC         = 0x0024,
  92         HCLGE_OPC_GET_CFG_PARAM         = 0x0025,
  93         HCLGE_OPC_PF_RST_DONE           = 0x0026,
  94         HCLGE_OPC_QUERY_VF_RST_RDY      = 0x0027,
  95
  96         HCLGE_OPC_STATS_64_BIT          = 0x0030,
  97         HCLGE_OPC_STATS_32_BIT          = 0x0031,
  98         HCLGE_OPC_STATS_MAC             = 0x0032,
  99         HCLGE_OPC_QUERY_MAC_REG_NUM     = 0x0033,
 100         HCLGE_OPC_STATS_MAC_ALL         = 0x0034,
 101
 102         HCLGE_OPC_QUERY_REG_NUM         = 0x0040,
 103         HCLGE_OPC_QUERY_32_BIT_REG      = 0x0041,
 104         HCLGE_OPC_QUERY_64_BIT_REG      = 0x0042,
 105         HCLGE_OPC_DFX_BD_NUM            = 0x0043,
 106         HCLGE_OPC_DFX_BIOS_COMMON_REG   = 0x0044,
 107         HCLGE_OPC_DFX_SSU_REG_0         = 0x0045,
 108         HCLGE_OPC_DFX_SSU_REG_1         = 0x0046,
 109         HCLGE_OPC_DFX_IGU_EGU_REG       = 0x0047,
 110         HCLGE_OPC_DFX_RPU_REG_0         = 0x0048,
 111         HCLGE_OPC_DFX_RPU_REG_1         = 0x0049,
 112         HCLGE_OPC_DFX_NCSI_REG          = 0x004A,
 113         HCLGE_OPC_DFX_RTC_REG           = 0x004B,
 114         HCLGE_OPC_DFX_PPP_REG           = 0x004C,
 115         HCLGE_OPC_DFX_RCB_REG           = 0x004D,
 116         HCLGE_OPC_DFX_TQP_REG           = 0x004E,
 117         HCLGE_OPC_DFX_SSU_REG_2         = 0x004F,
 118
 119         HCLGE_OPC_QUERY_DEV_SPECS       = 0x0050,
 120
 121         /* MAC command */
 122         HCLGE_OPC_CONFIG_MAC_MODE       = 0x0301,
 123         HCLGE_OPC_CONFIG_AN_MODE        = 0x0304,
 124         HCLGE_OPC_QUERY_LINK_STATUS     = 0x0307,
 125         HCLGE_OPC_CONFIG_MAX_FRM_SIZE   = 0x0308,
 126         HCLGE_OPC_CONFIG_SPEED_DUP      = 0x0309,
 127         HCLGE_OPC_QUERY_MAC_TNL_INT     = 0x0310,
 128         HCLGE_OPC_MAC_TNL_INT_EN        = 0x0311,
 129         HCLGE_OPC_CLEAR_MAC_TNL_INT     = 0x0312,
 130         HCLGE_OPC_COMMON_LOOPBACK       = 0x0315,
 131         HCLGE_OPC_CONFIG_FEC_MODE       = 0x031A,
 132
 133         /* PTP commands */
 134         HCLGE_OPC_PTP_INT_EN            = 0x0501,
 135         HCLGE_OPC_PTP_MODE_CFG          = 0x0507,
 136
 137         /* PFC/Pause commands */
 138         HCLGE_OPC_CFG_MAC_PAUSE_EN      = 0x0701,
 139         HCLGE_OPC_CFG_PFC_PAUSE_EN      = 0x0702,
 140         HCLGE_OPC_CFG_MAC_PARA          = 0x0703,
 141         HCLGE_OPC_CFG_PFC_PARA          = 0x0704,
 142         HCLGE_OPC_QUERY_MAC_TX_PKT_CNT  = 0x0705,
 143         HCLGE_OPC_QUERY_MAC_RX_PKT_CNT  = 0x0706,
 144         HCLGE_OPC_QUERY_PFC_TX_PKT_CNT  = 0x0707,
 145         HCLGE_OPC_QUERY_PFC_RX_PKT_CNT  = 0x0708,
 146         HCLGE_OPC_PRI_TO_TC_MAPPING     = 0x0709,
 147         HCLGE_OPC_QOS_MAP               = 0x070A,
 148
 149         /* ETS/scheduler commands */
 150         HCLGE_OPC_TM_PG_TO_PRI_LINK     = 0x0804,
 151         HCLGE_OPC_TM_QS_TO_PRI_LINK     = 0x0805,
 152         HCLGE_OPC_TM_NQ_TO_QS_LINK      = 0x0806,
 153         HCLGE_OPC_TM_RQ_TO_QS_LINK      = 0x0807,
 154         HCLGE_OPC_TM_PORT_WEIGHT        = 0x0808,
 155         HCLGE_OPC_TM_PG_WEIGHT          = 0x0809,
 156         HCLGE_OPC_TM_QS_WEIGHT          = 0x080A,
 157         HCLGE_OPC_TM_PRI_WEIGHT         = 0x080B,
 158         HCLGE_OPC_TM_PRI_C_SHAPPING     = 0x080C,
 159         HCLGE_OPC_TM_PRI_P_SHAPPING     = 0x080D,
 160         HCLGE_OPC_TM_PG_C_SHAPPING      = 0x080E,
 161         HCLGE_OPC_TM_PG_P_SHAPPING      = 0x080F,
 162         HCLGE_OPC_TM_PORT_SHAPPING      = 0x0810,
 163         HCLGE_OPC_TM_PG_SCH_MODE_CFG    = 0x0812,
 164         HCLGE_OPC_TM_PRI_SCH_MODE_CFG   = 0x0813,
 165         HCLGE_OPC_TM_QS_SCH_MODE_CFG    = 0x0814,
 166         HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
 167         HCLGE_OPC_TM_NODES              = 0x0816,
 168         HCLGE_OPC_ETS_TC_WEIGHT         = 0x0843,
 169         HCLGE_OPC_QSET_DFX_STS          = 0x0844,
 170         HCLGE_OPC_PRI_DFX_STS           = 0x0845,
 171         HCLGE_OPC_PG_DFX_STS            = 0x0846,
 172         HCLGE_OPC_PORT_DFX_STS          = 0x0847,
 173         HCLGE_OPC_SCH_NQ_CNT            = 0x0848,
 174         HCLGE_OPC_SCH_RQ_CNT            = 0x0849,
 175         HCLGE_OPC_TM_INTERNAL_STS       = 0x0850,
 176         HCLGE_OPC_TM_INTERNAL_CNT       = 0x0851,
 177         HCLGE_OPC_TM_INTERNAL_STS_1     = 0x0852,
 178
 179         /* Packet buffer allocate commands */
 180         HCLGE_OPC_TX_BUFF_ALLOC         = 0x0901,
 181         HCLGE_OPC_RX_PRIV_BUFF_ALLOC    = 0x0902,
 182         HCLGE_OPC_RX_PRIV_WL_ALLOC      = 0x0903,
 183         HCLGE_OPC_RX_COM_THRD_ALLOC     = 0x0904,
 184         HCLGE_OPC_RX_COM_WL_ALLOC       = 0x0905,
 185         HCLGE_OPC_RX_GBL_PKT_CNT        = 0x0906,
 186
 187         /* TQP management command */
 188         HCLGE_OPC_SET_TQP_MAP           = 0x0A01,
 189
 190         /* TQP commands */
 191         HCLGE_OPC_CFG_TX_QUEUE          = 0x0B01,
 192         HCLGE_OPC_QUERY_TX_POINTER      = 0x0B02,
 193         HCLGE_OPC_QUERY_TX_STATS        = 0x0B03,
 194         HCLGE_OPC_TQP_TX_QUEUE_TC       = 0x0B04,
 195         HCLGE_OPC_CFG_RX_QUEUE          = 0x0B11,
 196         HCLGE_OPC_QUERY_RX_POINTER      = 0x0B12,
 197         HCLGE_OPC_QUERY_RX_STATS        = 0x0B13,
 198         HCLGE_OPC_STASH_RX_QUEUE_LRO    = 0x0B16,
 199         HCLGE_OPC_CFG_RX_QUEUE_LRO      = 0x0B17,
 200         HCLGE_OPC_CFG_COM_TQP_QUEUE     = 0x0B20,
 201         HCLGE_OPC_RESET_TQP_QUEUE       = 0x0B22,
 202
 203         /* PPU commands */
 204         HCLGE_OPC_PPU_PF_OTHER_INT_DFX  = 0x0B4A,
 205
 206         /* TSO command */
 207         HCLGE_OPC_TSO_GENERIC_CONFIG    = 0x0C01,
 208         HCLGE_OPC_GRO_GENERIC_CONFIG    = 0x0C10,
 209
 210         /* RSS commands */
 211         HCLGE_OPC_RSS_GENERIC_CONFIG    = 0x0D01,
 212         HCLGE_OPC_RSS_INDIR_TABLE       = 0x0D07,
 213         HCLGE_OPC_RSS_TC_MODE           = 0x0D08,
 214         HCLGE_OPC_RSS_INPUT_TUPLE       = 0x0D02,
 215
 216         /* Promisuous mode command */
 217         HCLGE_OPC_CFG_PROMISC_MODE      = 0x0E01,
 218
 219         /* Vlan offload commands */
 220         HCLGE_OPC_VLAN_PORT_TX_CFG      = 0x0F01,
 221         HCLGE_OPC_VLAN_PORT_RX_CFG      = 0x0F02,
 222
 223         /* Interrupts commands */
 224         HCLGE_OPC_ADD_RING_TO_VECTOR    = 0x1503,
 225         HCLGE_OPC_DEL_RING_TO_VECTOR    = 0x1504,
 226
 227         /* MAC commands */
 228         HCLGE_OPC_MAC_VLAN_ADD              = 0x1000,
 229         HCLGE_OPC_MAC_VLAN_REMOVE           = 0x1001,
 230         HCLGE_OPC_MAC_VLAN_TYPE_ID          = 0x1002,
 231         HCLGE_OPC_MAC_VLAN_INSERT           = 0x1003,
 232         HCLGE_OPC_MAC_VLAN_ALLOCATE         = 0x1004,
 233         HCLGE_OPC_MAC_ETHTYPE_ADD           = 0x1010,
 234         HCLGE_OPC_MAC_ETHTYPE_REMOVE    = 0x1011,
 235
 236         /* MAC VLAN commands */
 237         HCLGE_OPC_MAC_VLAN_SWITCH_PARAM = 0x1033,
 238
 239         /* VLAN commands */
 240         HCLGE_OPC_VLAN_FILTER_CTRL          = 0x1100,
 241         HCLGE_OPC_VLAN_FILTER_PF_CFG    = 0x1101,
 242         HCLGE_OPC_VLAN_FILTER_VF_CFG    = 0x1102,
 243         HCLGE_OPC_PORT_VLAN_BYPASS      = 0x1103,
 244
 245         /* Flow Director commands */
 246         HCLGE_OPC_FD_MODE_CTRL          = 0x1200,
 247         HCLGE_OPC_FD_GET_ALLOCATION     = 0x1201,
 248         HCLGE_OPC_FD_KEY_CONFIG         = 0x1202,
 249         HCLGE_OPC_FD_TCAM_OP            = 0x1203,
 250         HCLGE_OPC_FD_AD_OP              = 0x1204,
 251         HCLGE_OPC_FD_CNT_OP             = 0x1205,
 252         HCLGE_OPC_FD_USER_DEF_OP        = 0x1207,
 253
 254         /* MDIO command */
 255         HCLGE_OPC_MDIO_CONFIG           = 0x1900,
 256
 257         /* QCN commands */
 258         HCLGE_OPC_QCN_MOD_CFG           = 0x1A01,
 259         HCLGE_OPC_QCN_GRP_TMPLT_CFG     = 0x1A02,
 260         HCLGE_OPC_QCN_SHAPPING_CFG      = 0x1A03,
 261         HCLGE_OPC_QCN_SHAPPING_BS_CFG   = 0x1A04,
 262         HCLGE_OPC_QCN_QSET_LINK_CFG     = 0x1A05,
 263         HCLGE_OPC_QCN_RP_STATUS_GET     = 0x1A06,
 264         HCLGE_OPC_QCN_AJUST_INIT        = 0x1A07,
 265         HCLGE_OPC_QCN_DFX_CNT_STATUS    = 0x1A08,
 266
 267         /* Mailbox command */
 268         HCLGEVF_OPC_MBX_PF_TO_VF        = 0x2000,
 269
 270         /* Led command */
 271         HCLGE_OPC_LED_STATUS_CFG        = 0xB000,
 272
 273         /* NCL config command */
 274         HCLGE_OPC_QUERY_NCL_CONFIG      = 0x7011,
 275
 276         /* IMP stats command */
 277         HCLGE_OPC_IMP_STATS_BD          = 0x7012,
 278         HCLGE_OPC_IMP_STATS_INFO                = 0x7013,
 279         HCLGE_OPC_IMP_COMPAT_CFG                = 0x701A,
 280
 281         /* SFP command */
 282         HCLGE_OPC_GET_SFP_EEPROM        = 0x7100,
 283         HCLGE_OPC_GET_SFP_EXIST         = 0x7101,
 284         HCLGE_OPC_GET_SFP_INFO          = 0x7104,
 285
 286         /* Error INT commands */
 287         HCLGE_MAC_COMMON_INT_EN         = 0x030E,
 288         HCLGE_TM_SCH_ECC_INT_EN         = 0x0829,
 289         HCLGE_SSU_ECC_INT_CMD           = 0x0989,
 290         HCLGE_SSU_COMMON_INT_CMD        = 0x098C,
 291         HCLGE_PPU_MPF_ECC_INT_CMD       = 0x0B40,
 292         HCLGE_PPU_MPF_OTHER_INT_CMD     = 0x0B41,
 293         HCLGE_PPU_PF_OTHER_INT_CMD      = 0x0B42,
 294         HCLGE_COMMON_ECC_INT_CFG        = 0x1505,
 295         HCLGE_QUERY_RAS_INT_STS_BD_NUM  = 0x1510,
 296         HCLGE_QUERY_CLEAR_MPF_RAS_INT   = 0x1511,
 297         HCLGE_QUERY_CLEAR_PF_RAS_INT    = 0x1512,
 298         HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
 299         HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT      = 0x1514,
 300         HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT       = 0x1515,
 301         HCLGE_QUERY_ALL_ERR_BD_NUM              = 0x1516,
 302         HCLGE_QUERY_ALL_ERR_INFO                = 0x1517,
 303         HCLGE_CONFIG_ROCEE_RAS_INT_EN   = 0x1580,
 304         HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581,
 305         HCLGE_ROCEE_PF_RAS_INT_CMD      = 0x1584,
 306         HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD      = 0x1585,
 307         HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD      = 0x1586,
 308         HCLGE_IGU_EGU_TNL_INT_EN        = 0x1803,
 309         HCLGE_IGU_COMMON_INT_EN         = 0x1806,
 310         HCLGE_TM_QCN_MEM_INT_CFG        = 0x1A14,
 311         HCLGE_PPP_CMD0_INT_CMD          = 0x2100,
 312         HCLGE_PPP_CMD1_INT_CMD          = 0x2101,
 313         HCLGE_MAC_ETHERTYPE_IDX_RD      = 0x2105,
 314         HCLGE_NCSI_INT_EN               = 0x2401,
 315
 316         /* PHY command */
 317         HCLGE_OPC_PHY_LINK_KSETTING     = 0x7025,
 318         HCLGE_OPC_PHY_REG               = 0x7026,
 319 };
 320
 321 #define HCLGE_TQP_REG_OFFSET            0x80000
 322 #define HCLGE_TQP_REG_SIZE              0x200
 323
 324 #define HCLGE_TQP_MAX_SIZE_DEV_V2       1024
 325 #define HCLGE_TQP_EXT_REG_OFFSET        0x100
 326
 327 #define HCLGE_RCB_INIT_QUERY_TIMEOUT    10
 328 #define HCLGE_RCB_INIT_FLAG_EN_B        0
 329 #define HCLGE_RCB_INIT_FLAG_FINI_B      8
 330 struct hclge_config_rcb_init_cmd {
 331         __le16 rcb_init_flag;
 332         u8 rsv[22];
 333 };
 334
 335 struct hclge_tqp_map_cmd {
 336         __le16 tqp_id;  /* Absolute tqp id for in this pf */
 337         u8 tqp_vf;      /* VF id */
 338 #define HCLGE_TQP_MAP_TYPE_PF           0
 339 #define HCLGE_TQP_MAP_TYPE_VF           1
 340 #define HCLGE_TQP_MAP_TYPE_B            0
 341 #define HCLGE_TQP_MAP_EN_B              1
 342         u8 tqp_flag;    /* Indicate it's pf or vf tqp */
 343         __le16 tqp_vid; /* Virtual id in this pf/vf */
 344         u8 rsv[18];
 345 };
 346
 347 #define HCLGE_VECTOR_ELEMENTS_PER_CMD   10
 348
 349 enum hclge_int_type {
 350         HCLGE_INT_TX,
 351         HCLGE_INT_RX,
 352         HCLGE_INT_EVENT,
 353 };
 354
 355 struct hclge_ctrl_vector_chain_cmd {
 356 #define HCLGE_VECTOR_ID_L_S     0
 357 #define HCLGE_VECTOR_ID_L_M     GENMASK(7, 0)
 358         u8 int_vector_id_l;
 359         u8 int_cause_num;
 360 #define HCLGE_INT_TYPE_S        0
 361 #define HCLGE_INT_TYPE_M        GENMASK(1, 0)
 362 #define HCLGE_TQP_ID_S          2
 363 #define HCLGE_TQP_ID_M          GENMASK(12, 2)
 364 #define HCLGE_INT_GL_IDX_S      13
 365 #define HCLGE_INT_GL_IDX_M      GENMASK(14, 13)
 366         __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];
 367         u8 vfid;
 368 #define HCLGE_VECTOR_ID_H_S     8
 369 #define HCLGE_VECTOR_ID_H_M     GENMASK(15, 8)
 370         u8 int_vector_id_h;
 371 };
 372
 373 #define HCLGE_MAX_TC_NUM                8
 374 #define HCLGE_TC0_PRI_BUF_EN_B  15 /* Bit 15 indicate enable or not */
 375 #define HCLGE_BUF_UNIT_S        7  /* Buf size is united by 128 bytes */
 376 struct hclge_tx_buff_alloc_cmd {
 377         __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM];
 378         u8 tx_buff_rsv[8];
 379 };
 380
 381 struct hclge_rx_priv_buff_cmd {
 382         __le16 buf_num[HCLGE_MAX_TC_NUM];
 383         __le16 shared_buf;
 384         u8 rsv[6];
 385 };
 386
 387 enum HCLGE_CAP_BITS {
 388         HCLGE_CAP_UDP_GSO_B,
 389         HCLGE_CAP_QB_B,
 390         HCLGE_CAP_FD_FORWARD_TC_B,
 391         HCLGE_CAP_PTP_B,
 392         HCLGE_CAP_INT_QL_B,
 393         HCLGE_CAP_HW_TX_CSUM_B,
 394         HCLGE_CAP_TX_PUSH_B,
 395         HCLGE_CAP_PHY_IMP_B,
 396         HCLGE_CAP_TQP_TXRX_INDEP_B,
 397         HCLGE_CAP_HW_PAD_B,
 398         HCLGE_CAP_STASH_B,
 399         HCLGE_CAP_UDP_TUNNEL_CSUM_B,
 400         HCLGE_CAP_RAS_IMP_B = 12,
 401         HCLGE_CAP_FEC_B = 13,
 402         HCLGE_CAP_PAUSE_B = 14,
 403         HCLGE_CAP_RXD_ADV_LAYOUT_B = 15,
 404         HCLGE_CAP_PORT_VLAN_BYPASS_B = 17,
 405 };
 406
 407 enum HCLGE_API_CAP_BITS {
 408         HCLGE_API_CAP_FLEX_RSS_TBL_B,
 409 };
 410
 411 #define HCLGE_QUERY_CAP_LENGTH          3
 412 struct hclge_query_version_cmd {
 413         __le32 firmware;
 414         __le32 hardware;
 415         __le32 api_caps;
 416         __le32 caps[HCLGE_QUERY_CAP_LENGTH]; /* capabilities of device */
 417 };
 418
 419 #define HCLGE_RX_PRIV_EN_B      15
 420 #define HCLGE_TC_NUM_ONE_DESC   4
 421 struct hclge_priv_wl {
 422         __le16 high;
 423         __le16 low;
 424 };
 425
 426 struct hclge_rx_priv_wl_buf {
 427         struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC];
 428 };
 429
 430 struct hclge_rx_com_thrd {
 431         struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC];
 432 };
 433
 434 struct hclge_rx_com_wl {
 435         struct hclge_priv_wl com_wl;
 436 };
 437
 438 struct hclge_waterline {
 439         u32 low;
 440         u32 high;
 441 };
 442
 443 struct hclge_tc_thrd {
 444         u32 low;
 445         u32 high;
 446 };
 447
 448 struct hclge_priv_buf {
 449         struct hclge_waterline wl;      /* Waterline for low and high*/
 450         u32 buf_size;   /* TC private buffer size */
 451         u32 tx_buf_size;
 452         u32 enable;     /* Enable TC private buffer or not */
 453 };
 454
 455 struct hclge_shared_buf {
 456         struct hclge_waterline self;
 457         struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM];
 458         u32 buf_size;
 459 };
 460
 461 struct hclge_pkt_buf_alloc {
 462         struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM];
 463         struct hclge_shared_buf s_buf;
 464 };
 465
 466 #define HCLGE_RX_COM_WL_EN_B    15
 467 struct hclge_rx_com_wl_buf_cmd {
 468         __le16 high_wl;
 469         __le16 low_wl;
 470         u8 rsv[20];
 471 };
 472
 473 #define HCLGE_RX_PKT_EN_B       15
 474 struct hclge_rx_pkt_buf_cmd {
 475         __le16 high_pkt;
 476         __le16 low_pkt;
 477         u8 rsv[20];
 478 };
 479
 480 #define HCLGE_PF_STATE_DONE_B   0
 481 #define HCLGE_PF_STATE_MAIN_B   1
 482 #define HCLGE_PF_STATE_BOND_B   2
 483 #define HCLGE_PF_STATE_MAC_N_B  6
 484 #define HCLGE_PF_MAC_NUM_MASK   0x3
 485 #define HCLGE_PF_STATE_MAIN     BIT(HCLGE_PF_STATE_MAIN_B)
 486 #define HCLGE_PF_STATE_DONE     BIT(HCLGE_PF_STATE_DONE_B)
 487 #define HCLGE_VF_RST_STATUS_CMD 4
 488
 489 struct hclge_func_status_cmd {
 490         __le32  vf_rst_state[HCLGE_VF_RST_STATUS_CMD];
 491         u8 pf_state;
 492         u8 mac_id;
 493         u8 rsv1;
 494         u8 pf_cnt_in_mac;
 495         u8 pf_num;
 496         u8 vf_num;
 497         u8 rsv[2];
 498 };
 499
 500 struct hclge_pf_res_cmd {
 501         __le16 tqp_num;
 502         __le16 buf_size;
 503         __le16 msixcap_localid_ba_nic;
 504         __le16 msixcap_localid_number_nic;
 505         __le16 pf_intr_vector_number_roce;
 506         __le16 pf_own_fun_number;
 507         __le16 tx_buf_size;
 508         __le16 dv_buf_size;
 509         __le16 ext_tqp_num;
 510         u8 rsv[6];
 511 };
 512
 513 #define HCLGE_CFG_OFFSET_S      0
 514 #define HCLGE_CFG_OFFSET_M      GENMASK(19, 0)
 515 #define HCLGE_CFG_RD_LEN_S      24
 516 #define HCLGE_CFG_RD_LEN_M      GENMASK(27, 24)
 517 #define HCLGE_CFG_RD_LEN_BYTES  16
 518 #define HCLGE_CFG_RD_LEN_UNIT   4
 519
 520 #define HCLGE_CFG_TC_NUM_S      8
 521 #define HCLGE_CFG_TC_NUM_M      GENMASK(15, 8)
 522 #define HCLGE_CFG_TQP_DESC_N_S  16
 523 #define HCLGE_CFG_TQP_DESC_N_M  GENMASK(31, 16)
 524 #define HCLGE_CFG_PHY_ADDR_S    0
 525 #define HCLGE_CFG_PHY_ADDR_M    GENMASK(7, 0)
 526 #define HCLGE_CFG_MEDIA_TP_S    8
 527 #define HCLGE_CFG_MEDIA_TP_M    GENMASK(15, 8)
 528 #define HCLGE_CFG_RX_BUF_LEN_S  16
 529 #define HCLGE_CFG_RX_BUF_LEN_M  GENMASK(31, 16)
 530 #define HCLGE_CFG_MAC_ADDR_H_S  0
 531 #define HCLGE_CFG_MAC_ADDR_H_M  GENMASK(15, 0)
 532 #define HCLGE_CFG_DEFAULT_SPEED_S       16
 533 #define HCLGE_CFG_DEFAULT_SPEED_M       GENMASK(23, 16)
 534 #define HCLGE_CFG_RSS_SIZE_S    24
 535 #define HCLGE_CFG_RSS_SIZE_M    GENMASK(31, 24)
 536 #define HCLGE_CFG_SPEED_ABILITY_S       0
 537 #define HCLGE_CFG_SPEED_ABILITY_M       GENMASK(7, 0)
 538 #define HCLGE_CFG_SPEED_ABILITY_EXT_S   10
 539 #define HCLGE_CFG_SPEED_ABILITY_EXT_M   GENMASK(15, 10)
 540 #define HCLGE_CFG_VLAN_FLTR_CAP_S       8
 541 #define HCLGE_CFG_VLAN_FLTR_CAP_M       GENMASK(9, 8)
 542 #define HCLGE_CFG_UMV_TBL_SPACE_S       16
 543 #define HCLGE_CFG_UMV_TBL_SPACE_M       GENMASK(31, 16)
 544 #define HCLGE_CFG_PF_RSS_SIZE_S         0
 545 #define HCLGE_CFG_PF_RSS_SIZE_M         GENMASK(3, 0)
 546 #define HCLGE_CFG_TX_SPARE_BUF_SIZE_S   4
 547 #define HCLGE_CFG_TX_SPARE_BUF_SIZE_M   GENMASK(15, 4)
 548
 549 #define HCLGE_CFG_CMD_CNT               4
 550
 551 struct hclge_cfg_param_cmd {
 552         __le32 offset;
 553         __le32 rsv;
 554         __le32 param[HCLGE_CFG_CMD_CNT];
 555 };
 556
 557 #define HCLGE_MAC_MODE          0x0
 558 #define HCLGE_DESC_NUM          0x40
 559
 560 #define HCLGE_ALLOC_VALID_B     0
 561 struct hclge_vf_num_cmd {
 562         u8 alloc_valid;
 563         u8 rsv[23];
 564 };
 565
 566 #define HCLGE_RSS_DEFAULT_OUTPORT_B     4
 567 #define HCLGE_RSS_HASH_KEY_OFFSET_B     4
 568 #define HCLGE_RSS_HASH_KEY_NUM          16
 569 struct hclge_rss_config_cmd {
 570         u8 hash_config;
 571         u8 rsv[7];
 572         u8 hash_key[HCLGE_RSS_HASH_KEY_NUM];
 573 };
 574
 575 struct hclge_rss_input_tuple_cmd {
 576         u8 ipv4_tcp_en;
 577         u8 ipv4_udp_en;
 578         u8 ipv4_sctp_en;
 579         u8 ipv4_fragment_en;
 580         u8 ipv6_tcp_en;
 581         u8 ipv6_udp_en;
 582         u8 ipv6_sctp_en;
 583         u8 ipv6_fragment_en;
 584         u8 rsv[16];
 585 };
 586
 587 #define HCLGE_RSS_CFG_TBL_SIZE  16
 588 #define HCLGE_RSS_CFG_TBL_SIZE_H        4
 589 #define HCLGE_RSS_CFG_TBL_BW_H          2U
 590 #define HCLGE_RSS_CFG_TBL_BW_L          8U
 591
 592 struct hclge_rss_indirection_table_cmd {
 593         __le16 start_table_index;
 594         __le16 rss_set_bitmap;
 595         u8 rss_qid_h[HCLGE_RSS_CFG_TBL_SIZE_H];
 596         u8 rss_qid_l[HCLGE_RSS_CFG_TBL_SIZE];
 597 };
 598
 599 #define HCLGE_RSS_TC_OFFSET_S           0
 600 #define HCLGE_RSS_TC_OFFSET_M           GENMASK(10, 0)
 601 #define HCLGE_RSS_TC_SIZE_MSB_B         11
 602 #define HCLGE_RSS_TC_SIZE_S             12
 603 #define HCLGE_RSS_TC_SIZE_M             GENMASK(14, 12)
 604 #define HCLGE_RSS_TC_SIZE_MSB_OFFSET    3
 605 #define HCLGE_RSS_TC_VALID_B            15
 606 struct hclge_rss_tc_mode_cmd {
 607         __le16 rss_tc_mode[HCLGE_MAX_TC_NUM];
 608         u8 rsv[8];
 609 };
 610
 611 #define HCLGE_LINK_STATUS_UP_B  0
 612 #define HCLGE_LINK_STATUS_UP_M  BIT(HCLGE_LINK_STATUS_UP_B)
 613 struct hclge_link_status_cmd {
 614         u8 status;
 615         u8 rsv[23];
 616 };
 617
 618 /* for DEVICE_VERSION_V1/2, reference to promisc cmd byte8 */
 619 #define HCLGE_PROMISC_EN_UC     1
 620 #define HCLGE_PROMISC_EN_MC     2
 621 #define HCLGE_PROMISC_EN_BC     3
 622 #define HCLGE_PROMISC_TX_EN     4
 623 #define HCLGE_PROMISC_RX_EN     5
 624
 625 /* for DEVICE_VERSION_V3, reference to promisc cmd byte10 */
 626 #define HCLGE_PROMISC_UC_RX_EN  2
 627 #define HCLGE_PROMISC_MC_RX_EN  3
 628 #define HCLGE_PROMISC_BC_RX_EN  4
 629 #define HCLGE_PROMISC_UC_TX_EN  5
 630 #define HCLGE_PROMISC_MC_TX_EN  6
 631 #define HCLGE_PROMISC_BC_TX_EN  7
 632
 633 struct hclge_promisc_cfg_cmd {
 634         u8 promisc;
 635         u8 vf_id;
 636         u8 extend_promisc;
 637         u8 rsv0[21];
 638 };
 639
 640 enum hclge_promisc_type {
 641         HCLGE_UNICAST   = 1,
 642         HCLGE_MULTICAST = 2,
 643         HCLGE_BROADCAST = 3,
 644 };
 645
 646 #define HCLGE_MAC_TX_EN_B       6
 647 #define HCLGE_MAC_RX_EN_B       7
 648 #define HCLGE_MAC_PAD_TX_B      11
 649 #define HCLGE_MAC_PAD_RX_B      12
 650 #define HCLGE_MAC_1588_TX_B     13
 651 #define HCLGE_MAC_1588_RX_B     14
 652 #define HCLGE_MAC_APP_LP_B      15
 653 #define HCLGE_MAC_LINE_LP_B     16
 654 #define HCLGE_MAC_FCS_TX_B      17
 655 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B        18
 656 #define HCLGE_MAC_RX_FCS_STRIP_B        19
 657 #define HCLGE_MAC_RX_FCS_B      20
 658 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B            21
 659 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B        22
 660
 661 struct hclge_config_mac_mode_cmd {
 662         __le32 txrx_pad_fcs_loop_en;
 663         u8 rsv[20];
 664 };
 665
 666 struct hclge_pf_rst_sync_cmd {
 667 #define HCLGE_PF_RST_ALL_VF_RDY_B       0
 668         u8 all_vf_ready;
 669         u8 rsv[23];
 670 };
 671
 672 #define HCLGE_CFG_SPEED_S               0
 673 #define HCLGE_CFG_SPEED_M               GENMASK(5, 0)
 674
 675 #define HCLGE_CFG_DUPLEX_B              7
 676 #define HCLGE_CFG_DUPLEX_M              BIT(HCLGE_CFG_DUPLEX_B)
 677
 678 struct hclge_config_mac_speed_dup_cmd {
 679         u8 speed_dup;
 680
 681 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0
 682         u8 mac_change_fec_en;
 683         u8 rsv[22];
 684 };
 685
 686 #define HCLGE_TQP_ENABLE_B              0
 687
 688 #define HCLGE_MAC_CFG_AN_EN_B           0
 689 #define HCLGE_MAC_CFG_AN_INT_EN_B       1
 690 #define HCLGE_MAC_CFG_AN_INT_MSK_B      2
 691 #define HCLGE_MAC_CFG_AN_INT_CLR_B      3
 692 #define HCLGE_MAC_CFG_AN_RST_B          4
 693
 694 #define HCLGE_MAC_CFG_AN_EN     BIT(HCLGE_MAC_CFG_AN_EN_B)
 695
 696 struct hclge_config_auto_neg_cmd {
 697         __le32  cfg_an_cmd_flag;
 698         u8      rsv[20];
 699 };
 700
 701 struct hclge_sfp_info_cmd {
 702         __le32 speed;
 703         u8 query_type; /* 0: sfp speed, 1: active speed */
 704         u8 active_fec;
 705         u8 autoneg; /* autoneg state */
 706         u8 autoneg_ability; /* whether support autoneg */
 707         __le32 speed_ability; /* speed ability for current media */
 708         __le32 module_type;
 709         u8 rsv[8];
 710 };
 711
 712 #define HCLGE_MAC_CFG_FEC_AUTO_EN_B     0
 713 #define HCLGE_MAC_CFG_FEC_MODE_S        1
 714 #define HCLGE_MAC_CFG_FEC_MODE_M        GENMASK(3, 1)
 715 #define HCLGE_MAC_CFG_FEC_SET_DEF_B     0
 716 #define HCLGE_MAC_CFG_FEC_CLR_DEF_B     1
 717
 718 #define HCLGE_MAC_FEC_OFF               0
 719 #define HCLGE_MAC_FEC_BASER             1
 720 #define HCLGE_MAC_FEC_RS                2
 721 struct hclge_config_fec_cmd {
 722         u8 fec_mode;
 723         u8 default_config;
 724         u8 rsv[22];
 725 };
 726
 727 #define HCLGE_MAC_UPLINK_PORT           0x100
 728
 729 struct hclge_config_max_frm_size_cmd {
 730         __le16  max_frm_size;
 731         u8      min_frm_size;
 732         u8      rsv[21];
 733 };
 734
 735 enum hclge_mac_vlan_tbl_opcode {
 736         HCLGE_MAC_VLAN_ADD,     /* Add new or modify mac_vlan */
 737         HCLGE_MAC_VLAN_UPDATE,  /* Modify other fields of this table */
 738         HCLGE_MAC_VLAN_REMOVE,  /* Remove a entry through mac_vlan key */
 739         HCLGE_MAC_VLAN_LKUP,    /* Lookup a entry through mac_vlan key */
 740 };
 741
 742 enum hclge_mac_vlan_add_resp_code {
 743         HCLGE_ADD_UC_OVERFLOW = 2,      /* ADD failed for UC overflow */
 744         HCLGE_ADD_MC_OVERFLOW,          /* ADD failed for MC overflow */
 745 };
 746
 747 #define HCLGE_MAC_VLAN_BIT0_EN_B        0
 748 #define HCLGE_MAC_VLAN_BIT1_EN_B        1
 749 #define HCLGE_MAC_EPORT_SW_EN_B         12
 750 #define HCLGE_MAC_EPORT_TYPE_B          11
 751 #define HCLGE_MAC_EPORT_VFID_S          3
 752 #define HCLGE_MAC_EPORT_VFID_M          GENMASK(10, 3)
 753 #define HCLGE_MAC_EPORT_PFID_S          0
 754 #define HCLGE_MAC_EPORT_PFID_M          GENMASK(2, 0)
 755 struct hclge_mac_vlan_tbl_entry_cmd {
 756         u8      flags;
 757         u8      resp_code;
 758         __le16  vlan_tag;
 759         __le32  mac_addr_hi32;
 760         __le16  mac_addr_lo16;
 761         __le16  rsv1;
 762         u8      entry_type;
 763         u8      mc_mac_en;
 764         __le16  egress_port;
 765         __le16  egress_queue;
 766         u8      rsv2[6];
 767 };
 768
 769 #define HCLGE_UMV_SPC_ALC_B     0
 770 struct hclge_umv_spc_alc_cmd {
 771         u8 allocate;
 772         u8 rsv1[3];
 773         __le32 space_size;
 774         u8 rsv2[16];
 775 };
 776
 777 #define HCLGE_MAC_MGR_MASK_VLAN_B               BIT(0)
 778 #define HCLGE_MAC_MGR_MASK_MAC_B                BIT(1)
 779 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B          BIT(2)
 780
 781 struct hclge_mac_mgr_tbl_entry_cmd {
 782         u8      flags;
 783         u8      resp_code;
 784         __le16  vlan_tag;
 785         u8      mac_addr[ETH_ALEN];
 786         __le16  rsv1;
 787         __le16  ethter_type;
 788         __le16  egress_port;
 789         __le16  egress_queue;
 790         u8      sw_port_id_aware;
 791         u8      rsv2;
 792         u8      i_port_bitmap;
 793         u8      i_port_direction;
 794         u8      rsv3[2];
 795 };
 796
 797 struct hclge_vlan_filter_ctrl_cmd {
 798         u8 vlan_type;
 799         u8 vlan_fe;
 800         u8 rsv1[2];
 801         u8 vf_id;
 802         u8 rsv2[19];
 803 };
 804
 805 #define HCLGE_VLAN_ID_OFFSET_STEP       160
 806 #define HCLGE_VLAN_BYTE_SIZE            8
 807 #define HCLGE_VLAN_OFFSET_BITMAP \
 808         (HCLGE_VLAN_ID_OFFSET_STEP / HCLGE_VLAN_BYTE_SIZE)
 809
 810 struct hclge_vlan_filter_pf_cfg_cmd {
 811         u8 vlan_offset;
 812         u8 vlan_cfg;
 813         u8 rsv[2];
 814         u8 vlan_offset_bitmap[HCLGE_VLAN_OFFSET_BITMAP];
 815 };
 816
 817 #define HCLGE_MAX_VF_BYTES  16
 818
 819 struct hclge_vlan_filter_vf_cfg_cmd {
 820         __le16 vlan_id;
 821         u8  resp_code;
 822         u8  rsv;
 823         u8  vlan_cfg;
 824         u8  rsv1[3];
 825         u8  vf_bitmap[HCLGE_MAX_VF_BYTES];
 826 };
 827
 828 #define HCLGE_INGRESS_BYPASS_B          0
 829 struct hclge_port_vlan_filter_bypass_cmd {
 830         u8 bypass_state;
 831         u8 rsv1[3];
 832         u8 vf_id;
 833         u8 rsv2[19];
 834 };
 835
 836 #define HCLGE_SWITCH_ANTI_SPOOF_B       0U
 837 #define HCLGE_SWITCH_ALW_LPBK_B         1U
 838 #define HCLGE_SWITCH_ALW_LCL_LPBK_B     2U
 839 #define HCLGE_SWITCH_ALW_DST_OVRD_B     3U
 840 #define HCLGE_SWITCH_NO_MASK            0x0
 841 #define HCLGE_SWITCH_ANTI_SPOOF_MASK    0xFE
 842 #define HCLGE_SWITCH_ALW_LPBK_MASK      0xFD
 843 #define HCLGE_SWITCH_ALW_LCL_LPBK_MASK  0xFB
 844 #define HCLGE_SWITCH_LW_DST_OVRD_MASK   0xF7
 845
 846 struct hclge_mac_vlan_switch_cmd {
 847         u8 roce_sel;
 848         u8 rsv1[3];
 849         __le32 func_id;
 850         u8 switch_param;
 851         u8 rsv2[3];
 852         u8 param_mask;
 853         u8 rsv3[11];
 854 };
 855
 856 enum hclge_mac_vlan_cfg_sel {
 857         HCLGE_MAC_VLAN_NIC_SEL = 0,
 858         HCLGE_MAC_VLAN_ROCE_SEL,
 859 };
 860
 861 #define HCLGE_ACCEPT_TAG1_B             0
 862 #define HCLGE_ACCEPT_UNTAG1_B           1
 863 #define HCLGE_PORT_INS_TAG1_EN_B        2
 864 #define HCLGE_PORT_INS_TAG2_EN_B        3
 865 #define HCLGE_CFG_NIC_ROCE_SEL_B        4
 866 #define HCLGE_ACCEPT_TAG2_B             5
 867 #define HCLGE_ACCEPT_UNTAG2_B           6
 868 #define HCLGE_TAG_SHIFT_MODE_EN_B       7
 869 #define HCLGE_VF_NUM_PER_BYTE           8
 870
 871 struct hclge_vport_vtag_tx_cfg_cmd {
 872         u8 vport_vlan_cfg;
 873         u8 vf_offset;
 874         u8 rsv1[2];
 875         __le16 def_vlan_tag1;
 876         __le16 def_vlan_tag2;
 877         u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];
 878         u8 rsv2[8];
 879 };
 880
 881 #define HCLGE_REM_TAG1_EN_B             0
 882 #define HCLGE_REM_TAG2_EN_B             1
 883 #define HCLGE_SHOW_TAG1_EN_B            2
 884 #define HCLGE_SHOW_TAG2_EN_B            3
 885 #define HCLGE_DISCARD_TAG1_EN_B         5
 886 #define HCLGE_DISCARD_TAG2_EN_B         6
 887 struct hclge_vport_vtag_rx_cfg_cmd {
 888         u8 vport_vlan_cfg;
 889         u8 vf_offset;
 890         u8 rsv1[6];
 891         u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];
 892         u8 rsv2[8];
 893 };
 894
 895 struct hclge_tx_vlan_type_cfg_cmd {
 896         __le16 ot_vlan_type;
 897         __le16 in_vlan_type;
 898         u8 rsv[20];
 899 };
 900
 901 struct hclge_rx_vlan_type_cfg_cmd {
 902         __le16 ot_fst_vlan_type;
 903         __le16 ot_sec_vlan_type;
 904         __le16 in_fst_vlan_type;
 905         __le16 in_sec_vlan_type;
 906         u8 rsv[16];
 907 };
 908
 909 struct hclge_cfg_com_tqp_queue_cmd {
 910         __le16 tqp_id;
 911         __le16 stream_id;
 912         u8 enable;
 913         u8 rsv[19];
 914 };
 915
 916 struct hclge_cfg_tx_queue_pointer_cmd {
 917         __le16 tqp_id;
 918         __le16 tx_tail;
 919         __le16 tx_head;
 920         __le16 fbd_num;
 921         __le16 ring_offset;
 922         u8 rsv[14];
 923 };
 924
 925 #pragma pack(1)
 926 struct hclge_mac_ethertype_idx_rd_cmd {
 927         u8      flags;
 928         u8      resp_code;
 929         __le16  vlan_tag;
 930         u8      mac_addr[ETH_ALEN];
 931         __le16  index;
 932         __le16  ethter_type;
 933         __le16  egress_port;
 934         __le16  egress_queue;
 935         __le16  rev0;
 936         u8      i_port_bitmap;
 937         u8      i_port_direction;
 938         u8      rev1[2];
 939 };
 940
 941 #pragma pack()
 942
 943 #define HCLGE_TSO_MSS_MIN_S     0
 944 #define HCLGE_TSO_MSS_MIN_M     GENMASK(13, 0)
 945
 946 #define HCLGE_TSO_MSS_MAX_S     16
 947 #define HCLGE_TSO_MSS_MAX_M     GENMASK(29, 16)
 948
 949 struct hclge_cfg_tso_status_cmd {
 950         __le16 tso_mss_min;
 951         __le16 tso_mss_max;
 952         u8 rsv[20];
 953 };
 954
 955 #define HCLGE_GRO_EN_B          0
 956 struct hclge_cfg_gro_status_cmd {
 957         u8 gro_en;
 958         u8 rsv[23];
 959 };
 960
 961 #define HCLGE_TSO_MSS_MIN       256
 962 #define HCLGE_TSO_MSS_MAX       9668
 963
 964 #define HCLGE_TQP_RESET_B       0
 965 struct hclge_reset_tqp_queue_cmd {
 966         __le16 tqp_id;
 967         u8 reset_req;
 968         u8 ready_to_reset;
 969         u8 rsv[20];
 970 };
 971
 972 #define HCLGE_CFG_RESET_MAC_B           3
 973 #define HCLGE_CFG_RESET_FUNC_B          7
 974 #define HCLGE_CFG_RESET_RCB_B           1
 975 struct hclge_reset_cmd {
 976         u8 mac_func_reset;
 977         u8 fun_reset_vfid;
 978         u8 fun_reset_rcb;
 979         u8 rsv;
 980         __le16 fun_reset_rcb_vqid_start;
 981         __le16 fun_reset_rcb_vqid_num;
 982         u8 fun_reset_rcb_return_status;
 983         u8 rsv1[15];
 984 };
 985
 986 #define HCLGE_PF_RESET_DONE_BIT         BIT(0)
 987
 988 struct hclge_pf_rst_done_cmd {
 989         u8 pf_rst_done;
 990         u8 rsv[23];
 991 };
 992
 993 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B    BIT(0)
 994 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B  BIT(2)
 995 #define HCLGE_CMD_GE_PHY_INNER_LOOP_B           BIT(3)
 996 #define HCLGE_CMD_COMMON_LB_DONE_B              BIT(0)
 997 #define HCLGE_CMD_COMMON_LB_SUCCESS_B           BIT(1)
 998 struct hclge_common_lb_cmd {
 999         u8 mask;
1000         u8 enable;
1001         u8 result;
1002         u8 rsv[21];
1003 };
1004
1005 #define HCLGE_DEFAULT_TX_BUF            0x4000   /* 16k  bytes */
1006 #define HCLGE_TOTAL_PKT_BUF             0x108000 /* 1.03125M bytes */
1007 #define HCLGE_DEFAULT_DV                0xA000   /* 40k byte */
1008 #define HCLGE_DEFAULT_NON_DCB_DV        0x7800  /* 30K byte */
1009 #define HCLGE_NON_DCB_ADDITIONAL_BUF    0x1400  /* 5120 byte */
1010
1011 #define HCLGE_TYPE_CRQ                  0
1012 #define HCLGE_TYPE_CSQ                  1
1013 #define HCLGE_NIC_CSQ_BASEADDR_L_REG    0x27000
1014 #define HCLGE_NIC_CSQ_BASEADDR_H_REG    0x27004
1015 #define HCLGE_NIC_CSQ_DEPTH_REG         0x27008
1016 #define HCLGE_NIC_CSQ_TAIL_REG          0x27010
1017 #define HCLGE_NIC_CSQ_HEAD_REG          0x27014
1018 #define HCLGE_NIC_CRQ_BASEADDR_L_REG    0x27018
1019 #define HCLGE_NIC_CRQ_BASEADDR_H_REG    0x2701c
1020 #define HCLGE_NIC_CRQ_DEPTH_REG         0x27020
1021 #define HCLGE_NIC_CRQ_TAIL_REG          0x27024
1022 #define HCLGE_NIC_CRQ_HEAD_REG          0x27028
1023
1024 /* this bit indicates that the driver is ready for hardware reset */
1025 #define HCLGE_NIC_SW_RST_RDY_B          16
1026 #define HCLGE_NIC_SW_RST_RDY            BIT(HCLGE_NIC_SW_RST_RDY_B)
1027
1028 #define HCLGE_NIC_CMQ_DESC_NUM          1024
1029 #define HCLGE_NIC_CMQ_DESC_NUM_S        3
1030
1031 #define HCLGE_LED_LOCATE_STATE_S        0
1032 #define HCLGE_LED_LOCATE_STATE_M        GENMASK(1, 0)
1033
1034 struct hclge_set_led_state_cmd {
1035         u8 rsv1[3];
1036         u8 locate_led_config;
1037         u8 rsv2[20];
1038 };
1039
1040 struct hclge_get_fd_mode_cmd {
1041         u8 mode;
1042         u8 enable;
1043         u8 rsv[22];
1044 };
1045
1046 struct hclge_get_fd_allocation_cmd {
1047         __le32 stage1_entry_num;
1048         __le32 stage2_entry_num;
1049         __le16 stage1_counter_num;
1050         __le16 stage2_counter_num;
1051         u8 rsv[12];
1052 };
1053
1054 struct hclge_set_fd_key_config_cmd {
1055         u8 stage;
1056         u8 key_select;
1057         u8 inner_sipv6_word_en;
1058         u8 inner_dipv6_word_en;
1059         u8 outer_sipv6_word_en;
1060         u8 outer_dipv6_word_en;
1061         u8 rsv1[2];
1062         __le32 tuple_mask;
1063         __le32 meta_data_mask;
1064         u8 rsv2[8];
1065 };
1066
1067 #define HCLGE_FD_EPORT_SW_EN_B          0
1068 struct hclge_fd_tcam_config_1_cmd {
1069         u8 stage;
1070         u8 xy_sel;
1071         u8 port_info;
1072         u8 rsv1[1];
1073         __le32 index;
1074         u8 entry_vld;
1075         u8 rsv2[7];
1076         u8 tcam_data[8];
1077 };
1078
1079 struct hclge_fd_tcam_config_2_cmd {
1080         u8 tcam_data[24];
1081 };
1082
1083 struct hclge_fd_tcam_config_3_cmd {
1084         u8 tcam_data[20];
1085         u8 rsv[4];
1086 };
1087
1088 #define HCLGE_FD_AD_DROP_B              0
1089 #define HCLGE_FD_AD_DIRECT_QID_B        1
1090 #define HCLGE_FD_AD_QID_S               2
1091 #define HCLGE_FD_AD_QID_M               GENMASK(11, 2)
1092 #define HCLGE_FD_AD_USE_COUNTER_B       12
1093 #define HCLGE_FD_AD_COUNTER_NUM_S       13
1094 #define HCLGE_FD_AD_COUNTER_NUM_M       GENMASK(20, 13)
1095 #define HCLGE_FD_AD_NXT_STEP_B          20
1096 #define HCLGE_FD_AD_NXT_KEY_S           21
1097 #define HCLGE_FD_AD_NXT_KEY_M           GENMASK(25, 21)
1098 #define HCLGE_FD_AD_WR_RULE_ID_B        0
1099 #define HCLGE_FD_AD_RULE_ID_S           1
1100 #define HCLGE_FD_AD_RULE_ID_M           GENMASK(12, 1)
1101 #define HCLGE_FD_AD_TC_OVRD_B           16
1102 #define HCLGE_FD_AD_TC_SIZE_S           17
1103 #define HCLGE_FD_AD_TC_SIZE_M           GENMASK(20, 17)
1104
1105 struct hclge_fd_ad_config_cmd {
1106         u8 stage;
1107         u8 rsv1[3];
1108         __le32 index;
1109         __le64 ad_data;
1110         u8 rsv2[8];
1111 };
1112
1113 struct hclge_fd_ad_cnt_read_cmd {
1114         u8 rsv0[4];
1115         __le16 index;
1116         u8 rsv1[2];
1117         __le64 cnt;
1118         u8 rsv2[8];
1119 };
1120
1121 #define HCLGE_FD_USER_DEF_OFT_S         0
1122 #define HCLGE_FD_USER_DEF_OFT_M         GENMASK(14, 0)
1123 #define HCLGE_FD_USER_DEF_EN_B          15
1124 struct hclge_fd_user_def_cfg_cmd {
1125         __le16 ol2_cfg;
1126         __le16 l2_cfg;
1127         __le16 ol3_cfg;
1128         __le16 l3_cfg;
1129         __le16 ol4_cfg;
1130         __le16 l4_cfg;
1131         u8 rsv[12];
1132 };
1133
1134 struct hclge_get_imp_bd_cmd {
1135         __le32 bd_num;
1136         u8 rsv[20];
1137 };
1138
1139 struct hclge_query_ppu_pf_other_int_dfx_cmd {
1140         __le16 over_8bd_no_fe_qid;
1141         __le16 over_8bd_no_fe_vf_id;
1142         __le16 tso_mss_cmp_min_err_qid;
1143         __le16 tso_mss_cmp_min_err_vf_id;
1144         __le16 tso_mss_cmp_max_err_qid;
1145         __le16 tso_mss_cmp_max_err_vf_id;
1146         __le16 tx_rd_fbd_poison_qid;
1147         __le16 tx_rd_fbd_poison_vf_id;
1148         __le16 rx_rd_fbd_poison_qid;
1149         __le16 rx_rd_fbd_poison_vf_id;
1150         u8 rsv[4];
1151 };
1152
1153 #define HCLGE_LINK_EVENT_REPORT_EN_B    0
1154 #define HCLGE_NCSI_ERROR_REPORT_EN_B    1
1155 #define HCLGE_PHY_IMP_EN_B              2
1156 struct hclge_firmware_compat_cmd {
1157         __le32 compat;
1158         u8 rsv[20];
1159 };
1160
1161 #define HCLGE_SFP_INFO_CMD_NUM  6
1162 #define HCLGE_SFP_INFO_BD0_LEN  20
1163 #define HCLGE_SFP_INFO_BDX_LEN  24
1164 #define HCLGE_SFP_INFO_MAX_LEN \
1165         (HCLGE_SFP_INFO_BD0_LEN + \
1166         (HCLGE_SFP_INFO_CMD_NUM - 1) * HCLGE_SFP_INFO_BDX_LEN)
1167
1168 struct hclge_sfp_info_bd0_cmd {
1169         __le16 offset;
1170         __le16 read_len;
1171         u8 data[HCLGE_SFP_INFO_BD0_LEN];
1172 };
1173
1174 #define HCLGE_QUERY_DEV_SPECS_BD_NUM            4
1175
1176 struct hclge_dev_specs_0_cmd {
1177         __le32 rsv0;
1178         __le32 mac_entry_num;
1179         __le32 mng_entry_num;
1180         __le16 rss_ind_tbl_size;
1181         __le16 rss_key_size;
1182         __le16 int_ql_max;
1183         u8 max_non_tso_bd_num;
1184         u8 rsv1;
1185         __le32 max_tm_rate;
1186 };
1187
1188 #define HCLGE_DEF_MAX_INT_GL            0x1FE0U
1189
1190 struct hclge_dev_specs_1_cmd {
1191         __le16 max_frm_size;
1192         __le16 max_qset_num;
1193         __le16 max_int_gl;
1194         u8 rsv1[18];
1195 };
1196
1197 #define HCLGE_PHY_LINK_SETTING_BD_NUM           2
1198
1199 struct hclge_phy_link_ksetting_0_cmd {
1200         __le32 speed;
1201         u8 duplex;
1202         u8 autoneg;
1203         u8 eth_tp_mdix;
1204         u8 eth_tp_mdix_ctrl;
1205         u8 port;
1206         u8 transceiver;
1207         u8 phy_address;
1208         u8 rsv;
1209         __le32 supported;
1210         __le32 advertising;
1211         __le32 lp_advertising;
1212 };
1213
1214 struct hclge_phy_link_ksetting_1_cmd {
1215         u8 master_slave_cfg;
1216         u8 master_slave_state;
1217         u8 rsv[22];
1218 };
1219
1220 struct hclge_phy_reg_cmd {
1221         __le16 reg_addr;
1222         u8 rsv0[2];
1223         __le16 reg_val;
1224         u8 rsv1[18];
1225 };
1226
1227 int hclge_cmd_init(struct hclge_dev *hdev);
1228 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
1229 {
1230         writel(value, base + reg);
1231 }
1232
1233 #define hclge_write_dev(a, reg, value) \
1234         hclge_write_reg((a)->io_base, reg, value)
1235 #define hclge_read_dev(a, reg) \
1236         hclge_read_reg((a)->io_base, reg)
1237
1238 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg)
1239 {
1240         u8 __iomem *reg_addr = READ_ONCE(base);
1241
1242         return readl(reg_addr + reg);
1243 }
1244
1245 #define HCLGE_SEND_SYNC(flag) \
1246         ((flag) & HCLGE_CMD_FLAG_NO_INTR)
1247
1248 struct hclge_hw;
1249 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num);
1250 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
1251                                 enum hclge_opcode_type opcode, bool is_read);
1252 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
1253
1254 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw,
1255                                            struct hclge_desc *desc);
1256 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw,
1257                                           struct hclge_desc *desc);
1258
1259 void hclge_cmd_uninit(struct hclge_dev *hdev);
1260 int hclge_cmd_queue_init(struct hclge_dev *hdev);
1261 #endif