drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Copyright (c) 2018-2019 Hisilicon Limited. */
   3
   4 #include <linux/debugfs.h>
   5 #include <linux/device.h>
   6
   7 #include "hnae3.h"
   8 #include "hns3_debugfs.h"
   9 #include "hns3_enet.h"
  10
  11 static struct dentry *hns3_dbgfs_root;
  12
  13 static struct hns3_dbg_dentry_info hns3_dbg_dentry[] = {
  14         {
  15                 .name = "tm"
  16         },
  17         {
  18                 .name = "tx_bd_info"
  19         },
  20         {
  21                 .name = "rx_bd_info"
  22         },
  23         {
  24                 .name = "mac_list"
  25         },
  26         {
  27                 .name = "reg"
  28         },
  29         {
  30                 .name = "queue"
  31         },
  32         {
  33                 .name = "fd"
  34         },
  35         /* keep common at the bottom and add new directory above */
  36         {
  37                 .name = "common"
  38         },
  39 };
  40
  41 static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, unsigned int cmd);
  42 static int hns3_dbg_common_file_init(struct hnae3_handle *handle,
  43                                      unsigned int cmd);
  44
  45 static struct hns3_dbg_cmd_info hns3_dbg_cmd[] = {
  46         {
  47                 .name = "tm_nodes",
  48                 .cmd = HNAE3_DBG_CMD_TM_NODES,
  49                 .dentry = HNS3_DBG_DENTRY_TM,
  50                 .buf_len = HNS3_DBG_READ_LEN,
  51                 .init = hns3_dbg_common_file_init,
  52         },
  53         {
  54                 .name = "tm_priority",
  55                 .cmd = HNAE3_DBG_CMD_TM_PRI,
  56                 .dentry = HNS3_DBG_DENTRY_TM,
  57                 .buf_len = HNS3_DBG_READ_LEN,
  58                 .init = hns3_dbg_common_file_init,
  59         },
  60         {
  61                 .name = "tm_qset",
  62                 .cmd = HNAE3_DBG_CMD_TM_QSET,
  63                 .dentry = HNS3_DBG_DENTRY_TM,
  64                 .buf_len = HNS3_DBG_READ_LEN,
  65                 .init = hns3_dbg_common_file_init,
  66         },
  67         {
  68                 .name = "tm_map",
  69                 .cmd = HNAE3_DBG_CMD_TM_MAP,
  70                 .dentry = HNS3_DBG_DENTRY_TM,
  71                 .buf_len = HNS3_DBG_READ_LEN_1MB,
  72                 .init = hns3_dbg_common_file_init,
  73         },
  74         {
  75                 .name = "tm_pg",
  76                 .cmd = HNAE3_DBG_CMD_TM_PG,
  77                 .dentry = HNS3_DBG_DENTRY_TM,
  78                 .buf_len = HNS3_DBG_READ_LEN,
  79                 .init = hns3_dbg_common_file_init,
  80         },
  81         {
  82                 .name = "tm_port",
  83                 .cmd = HNAE3_DBG_CMD_TM_PORT,
  84                 .dentry = HNS3_DBG_DENTRY_TM,
  85                 .buf_len = HNS3_DBG_READ_LEN,
  86                 .init = hns3_dbg_common_file_init,
  87         },
  88         {
  89                 .name = "tc_sch_info",
  90                 .cmd = HNAE3_DBG_CMD_TC_SCH_INFO,
  91                 .dentry = HNS3_DBG_DENTRY_TM,
  92                 .buf_len = HNS3_DBG_READ_LEN,
  93                 .init = hns3_dbg_common_file_init,
  94         },
  95         {
  96                 .name = "qos_pause_cfg",
  97                 .cmd = HNAE3_DBG_CMD_QOS_PAUSE_CFG,
  98                 .dentry = HNS3_DBG_DENTRY_TM,
  99                 .buf_len = HNS3_DBG_READ_LEN,
 100                 .init = hns3_dbg_common_file_init,
 101         },
 102         {
 103                 .name = "qos_pri_map",
 104                 .cmd = HNAE3_DBG_CMD_QOS_PRI_MAP,
 105                 .dentry = HNS3_DBG_DENTRY_TM,
 106                 .buf_len = HNS3_DBG_READ_LEN,
 107                 .init = hns3_dbg_common_file_init,
 108         },
 109         {
 110                 .name = "qos_buf_cfg",
 111                 .cmd = HNAE3_DBG_CMD_QOS_BUF_CFG,
 112                 .dentry = HNS3_DBG_DENTRY_TM,
 113                 .buf_len = HNS3_DBG_READ_LEN,
 114                 .init = hns3_dbg_common_file_init,
 115         },
 116         {
 117                 .name = "dev_info",
 118                 .cmd = HNAE3_DBG_CMD_DEV_INFO,
 119                 .dentry = HNS3_DBG_DENTRY_COMMON,
 120                 .buf_len = HNS3_DBG_READ_LEN,
 121                 .init = hns3_dbg_common_file_init,
 122         },
 123         {
 124                 .name = "tx_bd_queue",
 125                 .cmd = HNAE3_DBG_CMD_TX_BD,
 126                 .dentry = HNS3_DBG_DENTRY_TX_BD,
 127                 .buf_len = HNS3_DBG_READ_LEN_4MB,
 128                 .init = hns3_dbg_bd_file_init,
 129         },
 130         {
 131                 .name = "rx_bd_queue",
 132                 .cmd = HNAE3_DBG_CMD_RX_BD,
 133                 .dentry = HNS3_DBG_DENTRY_RX_BD,
 134                 .buf_len = HNS3_DBG_READ_LEN_4MB,
 135                 .init = hns3_dbg_bd_file_init,
 136         },
 137         {
 138                 .name = "uc",
 139                 .cmd = HNAE3_DBG_CMD_MAC_UC,
 140                 .dentry = HNS3_DBG_DENTRY_MAC,
 141                 .buf_len = HNS3_DBG_READ_LEN,
 142                 .init = hns3_dbg_common_file_init,
 143         },
 144         {
 145                 .name = "mc",
 146                 .cmd = HNAE3_DBG_CMD_MAC_MC,
 147                 .dentry = HNS3_DBG_DENTRY_MAC,
 148                 .buf_len = HNS3_DBG_READ_LEN,
 149                 .init = hns3_dbg_common_file_init,
 150         },
 151         {
 152                 .name = "mng_tbl",
 153                 .cmd = HNAE3_DBG_CMD_MNG_TBL,
 154                 .dentry = HNS3_DBG_DENTRY_COMMON,
 155                 .buf_len = HNS3_DBG_READ_LEN,
 156                 .init = hns3_dbg_common_file_init,
 157         },
 158         {
 159                 .name = "loopback",
 160                 .cmd = HNAE3_DBG_CMD_LOOPBACK,
 161                 .dentry = HNS3_DBG_DENTRY_COMMON,
 162                 .buf_len = HNS3_DBG_READ_LEN,
 163                 .init = hns3_dbg_common_file_init,
 164         },
 165         {
 166                 .name = "interrupt_info",
 167                 .cmd = HNAE3_DBG_CMD_INTERRUPT_INFO,
 168                 .dentry = HNS3_DBG_DENTRY_COMMON,
 169                 .buf_len = HNS3_DBG_READ_LEN,
 170                 .init = hns3_dbg_common_file_init,
 171         },
 172         {
 173                 .name = "reset_info",
 174                 .cmd = HNAE3_DBG_CMD_RESET_INFO,
 175                 .dentry = HNS3_DBG_DENTRY_COMMON,
 176                 .buf_len = HNS3_DBG_READ_LEN,
 177                 .init = hns3_dbg_common_file_init,
 178         },
 179         {
 180                 .name = "imp_info",
 181                 .cmd = HNAE3_DBG_CMD_IMP_INFO,
 182                 .dentry = HNS3_DBG_DENTRY_COMMON,
 183                 .buf_len = HNS3_DBG_READ_LEN,
 184                 .init = hns3_dbg_common_file_init,
 185         },
 186         {
 187                 .name = "ncl_config",
 188                 .cmd = HNAE3_DBG_CMD_NCL_CONFIG,
 189                 .dentry = HNS3_DBG_DENTRY_COMMON,
 190                 .buf_len = HNS3_DBG_READ_LEN_128KB,
 191                 .init = hns3_dbg_common_file_init,
 192         },
 193         {
 194                 .name = "mac_tnl_status",
 195                 .cmd = HNAE3_DBG_CMD_MAC_TNL_STATUS,
 196                 .dentry = HNS3_DBG_DENTRY_COMMON,
 197                 .buf_len = HNS3_DBG_READ_LEN,
 198                 .init = hns3_dbg_common_file_init,
 199         },
 200         {
 201                 .name = "bios_common",
 202                 .cmd = HNAE3_DBG_CMD_REG_BIOS_COMMON,
 203                 .dentry = HNS3_DBG_DENTRY_REG,
 204                 .buf_len = HNS3_DBG_READ_LEN,
 205                 .init = hns3_dbg_common_file_init,
 206         },
 207         {
 208                 .name = "ssu",
 209                 .cmd = HNAE3_DBG_CMD_REG_SSU,
 210                 .dentry = HNS3_DBG_DENTRY_REG,
 211                 .buf_len = HNS3_DBG_READ_LEN,
 212                 .init = hns3_dbg_common_file_init,
 213         },
 214         {
 215                 .name = "igu_egu",
 216                 .cmd = HNAE3_DBG_CMD_REG_IGU_EGU,
 217                 .dentry = HNS3_DBG_DENTRY_REG,
 218                 .buf_len = HNS3_DBG_READ_LEN,
 219                 .init = hns3_dbg_common_file_init,
 220         },
 221         {
 222                 .name = "rpu",
 223                 .cmd = HNAE3_DBG_CMD_REG_RPU,
 224                 .dentry = HNS3_DBG_DENTRY_REG,
 225                 .buf_len = HNS3_DBG_READ_LEN,
 226                 .init = hns3_dbg_common_file_init,
 227         },
 228         {
 229                 .name = "ncsi",
 230                 .cmd = HNAE3_DBG_CMD_REG_NCSI,
 231                 .dentry = HNS3_DBG_DENTRY_REG,
 232                 .buf_len = HNS3_DBG_READ_LEN,
 233                 .init = hns3_dbg_common_file_init,
 234         },
 235         {
 236                 .name = "rtc",
 237                 .cmd = HNAE3_DBG_CMD_REG_RTC,
 238                 .dentry = HNS3_DBG_DENTRY_REG,
 239                 .buf_len = HNS3_DBG_READ_LEN,
 240                 .init = hns3_dbg_common_file_init,
 241         },
 242         {
 243                 .name = "ppp",
 244                 .cmd = HNAE3_DBG_CMD_REG_PPP,
 245                 .dentry = HNS3_DBG_DENTRY_REG,
 246                 .buf_len = HNS3_DBG_READ_LEN,
 247                 .init = hns3_dbg_common_file_init,
 248         },
 249         {
 250                 .name = "rcb",
 251                 .cmd = HNAE3_DBG_CMD_REG_RCB,
 252                 .dentry = HNS3_DBG_DENTRY_REG,
 253                 .buf_len = HNS3_DBG_READ_LEN,
 254                 .init = hns3_dbg_common_file_init,
 255         },
 256         {
 257                 .name = "tqp",
 258                 .cmd = HNAE3_DBG_CMD_REG_TQP,
 259                 .dentry = HNS3_DBG_DENTRY_REG,
 260                 .buf_len = HNS3_DBG_READ_LEN,
 261                 .init = hns3_dbg_common_file_init,
 262         },
 263         {
 264                 .name = "mac",
 265                 .cmd = HNAE3_DBG_CMD_REG_MAC,
 266                 .dentry = HNS3_DBG_DENTRY_REG,
 267                 .buf_len = HNS3_DBG_READ_LEN,
 268                 .init = hns3_dbg_common_file_init,
 269         },
 270         {
 271                 .name = "dcb",
 272                 .cmd = HNAE3_DBG_CMD_REG_DCB,
 273                 .dentry = HNS3_DBG_DENTRY_REG,
 274                 .buf_len = HNS3_DBG_READ_LEN,
 275                 .init = hns3_dbg_common_file_init,
 276         },
 277         {
 278                 .name = "queue_map",
 279                 .cmd = HNAE3_DBG_CMD_QUEUE_MAP,
 280                 .dentry = HNS3_DBG_DENTRY_QUEUE,
 281                 .buf_len = HNS3_DBG_READ_LEN,
 282                 .init = hns3_dbg_common_file_init,
 283         },
 284         {
 285                 .name = "rx_queue_info",
 286                 .cmd = HNAE3_DBG_CMD_RX_QUEUE_INFO,
 287                 .dentry = HNS3_DBG_DENTRY_QUEUE,
 288                 .buf_len = HNS3_DBG_READ_LEN_1MB,
 289                 .init = hns3_dbg_common_file_init,
 290         },
 291         {
 292                 .name = "tx_queue_info",
 293                 .cmd = HNAE3_DBG_CMD_TX_QUEUE_INFO,
 294                 .dentry = HNS3_DBG_DENTRY_QUEUE,
 295                 .buf_len = HNS3_DBG_READ_LEN_1MB,
 296                 .init = hns3_dbg_common_file_init,
 297         },
 298         {
 299                 .name = "fd_tcam",
 300                 .cmd = HNAE3_DBG_CMD_FD_TCAM,
 301                 .dentry = HNS3_DBG_DENTRY_FD,
 302                 .buf_len = HNS3_DBG_READ_LEN,
 303                 .init = hns3_dbg_common_file_init,
 304         },
 305         {
 306                 .name = "service_task_info",
 307                 .cmd = HNAE3_DBG_CMD_SERV_INFO,
 308                 .dentry = HNS3_DBG_DENTRY_COMMON,
 309                 .buf_len = HNS3_DBG_READ_LEN,
 310                 .init = hns3_dbg_common_file_init,
 311         },
 312         {
 313                 .name = "vlan_config",
 314                 .cmd = HNAE3_DBG_CMD_VLAN_CONFIG,
 315                 .dentry = HNS3_DBG_DENTRY_COMMON,
 316                 .buf_len = HNS3_DBG_READ_LEN,
 317                 .init = hns3_dbg_common_file_init,
 318         },
 319         {
 320                 .name = "ptp_info",
 321                 .cmd = HNAE3_DBG_CMD_PTP_INFO,
 322                 .dentry = HNS3_DBG_DENTRY_COMMON,
 323                 .buf_len = HNS3_DBG_READ_LEN,
 324                 .init = hns3_dbg_common_file_init,
 325         },
 326         {
 327                 .name = "fd_counter",
 328                 .cmd = HNAE3_DBG_CMD_FD_COUNTER,
 329                 .dentry = HNS3_DBG_DENTRY_FD,
 330                 .buf_len = HNS3_DBG_READ_LEN,
 331                 .init = hns3_dbg_common_file_init,
 332         },
 333         {
 334                 .name = "umv_info",
 335                 .cmd = HNAE3_DBG_CMD_UMV_INFO,
 336                 .dentry = HNS3_DBG_DENTRY_COMMON,
 337                 .buf_len = HNS3_DBG_READ_LEN,
 338                 .init = hns3_dbg_common_file_init,
 339         },
 340 };
 341
 342 static struct hns3_dbg_cap_info hns3_dbg_cap[] = {
 343         {
 344                 .name = "support FD",
 345                 .cap_bit = HNAE3_DEV_SUPPORT_FD_B,
 346         }, {
 347                 .name = "support GRO",
 348                 .cap_bit = HNAE3_DEV_SUPPORT_GRO_B,
 349         }, {
 350                 .name = "support FEC",
 351                 .cap_bit = HNAE3_DEV_SUPPORT_FEC_B,
 352         }, {
 353                 .name = "support UDP GSO",
 354                 .cap_bit = HNAE3_DEV_SUPPORT_UDP_GSO_B,
 355         }, {
 356                 .name = "support PTP",
 357                 .cap_bit = HNAE3_DEV_SUPPORT_PTP_B,
 358         }, {
 359                 .name = "support INT QL",
 360                 .cap_bit = HNAE3_DEV_SUPPORT_INT_QL_B,
 361         }, {
 362                 .name = "support HW TX csum",
 363                 .cap_bit = HNAE3_DEV_SUPPORT_HW_TX_CSUM_B,
 364         }, {
 365                 .name = "support UDP tunnel csum",
 366                 .cap_bit = HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B,
 367         }, {
 368                 .name = "support TX push",
 369                 .cap_bit = HNAE3_DEV_SUPPORT_TX_PUSH_B,
 370         }, {
 371                 .name = "support imp-controlled PHY",
 372                 .cap_bit = HNAE3_DEV_SUPPORT_PHY_IMP_B,
 373         }, {
 374                 .name = "support imp-controlled RAS",
 375                 .cap_bit = HNAE3_DEV_SUPPORT_RAS_IMP_B,
 376         }, {
 377                 .name = "support rxd advanced layout",
 378                 .cap_bit = HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,
 379         }, {
 380                 .name = "support port vlan bypass",
 381                 .cap_bit = HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B,
 382         }, {
 383                 .name = "support modify vlan filter state",
 384                 .cap_bit = HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B,
 385         }
 386 };
 387
 388 static void hns3_dbg_fill_content(char *content, u16 len,
 389                                   const struct hns3_dbg_item *items,
 390                                   const char **result, u16 size)
 391 {
 392         char *pos = content;
 393         u16 i;
 394
 395         memset(content, ' ', len);
 396         for (i = 0; i < size; i++) {
 397                 if (result)
 398                         strncpy(pos, result[i], strlen(result[i]));
 399                 else
 400                         strncpy(pos, items[i].name, strlen(items[i].name));
 401
 402                 pos += strlen(items[i].name) + items[i].interval;
 403         }
 404
 405         *pos++ = '\n';
 406         *pos++ = '\0';
 407 }
 408
 409 static const struct hns3_dbg_item tx_spare_info_items[] = {
 410         { "QUEUE_ID", 2 },
 411         { "COPYBREAK", 2 },
 412         { "LEN", 7 },
 413         { "NTU", 4 },
 414         { "NTC", 4 },
 415         { "LTC", 4 },
 416         { "DMA", 17 },
 417 };
 418
 419 static void hns3_dbg_tx_spare_info(struct hns3_enet_ring *ring, char *buf,
 420                                    int len, u32 ring_num, int *pos)
 421 {
 422         char data_str[ARRAY_SIZE(tx_spare_info_items)][HNS3_DBG_DATA_STR_LEN];
 423         struct hns3_tx_spare *tx_spare = ring->tx_spare;
 424         char *result[ARRAY_SIZE(tx_spare_info_items)];
 425         char content[HNS3_DBG_INFO_LEN];
 426         u32 i, j;
 427
 428         if (!tx_spare) {
 429                 *pos += scnprintf(buf + *pos, len - *pos,
 430                                   "tx spare buffer is not enabled\n");
 431                 return;
 432         }
 433
 434         for (i = 0; i < ARRAY_SIZE(tx_spare_info_items); i++)
 435                 result[i] = &data_str[i][0];
 436
 437         *pos += scnprintf(buf + *pos, len - *pos, "tx spare buffer info\n");
 438         hns3_dbg_fill_content(content, sizeof(content), tx_spare_info_items,
 439                               NULL, ARRAY_SIZE(tx_spare_info_items));
 440         *pos += scnprintf(buf + *pos, len - *pos, "%s", content);
 441
 442         for (i = 0; i < ring_num; i++) {
 443                 j = 0;
 444                 sprintf(result[j++], "%8u", i);
 445                 sprintf(result[j++], "%9u", ring->tx_copybreak);
 446                 sprintf(result[j++], "%3u", tx_spare->len);
 447                 sprintf(result[j++], "%3u", tx_spare->next_to_use);
 448                 sprintf(result[j++], "%3u", tx_spare->next_to_clean);
 449                 sprintf(result[j++], "%3u", tx_spare->last_to_clean);
 450                 sprintf(result[j++], "%pad", &tx_spare->dma);
 451                 hns3_dbg_fill_content(content, sizeof(content),
 452                                       tx_spare_info_items,
 453                                       (const char **)result,
 454                                       ARRAY_SIZE(tx_spare_info_items));
 455                 *pos += scnprintf(buf + *pos, len - *pos, "%s", content);
 456         }
 457 }
 458
 459 static const struct hns3_dbg_item rx_queue_info_items[] = {
 460         { "QUEUE_ID", 2 },
 461         { "BD_NUM", 2 },
 462         { "BD_LEN", 2 },
 463         { "TAIL", 2 },
 464         { "HEAD", 2 },
 465         { "FBDNUM", 2 },
 466         { "PKTNUM", 2 },
 467         { "COPYBREAK", 2 },
 468         { "RING_EN", 2 },
 469         { "RX_RING_EN", 2 },
 470         { "BASE_ADDR", 10 },
 471 };
 472
 473 static void hns3_dump_rx_queue_info(struct hns3_enet_ring *ring,
 474                                     struct hnae3_ae_dev *ae_dev, char **result,
 475                                     u32 index)
 476 {
 477         u32 base_add_l, base_add_h;
 478         u32 j = 0;
 479
 480         sprintf(result[j++], "%8u", index);
 481
 482         sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base +
 483                 HNS3_RING_RX_RING_BD_NUM_REG));
 484
 485         sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base +
 486                 HNS3_RING_RX_RING_BD_LEN_REG));
 487
 488         sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base +
 489                 HNS3_RING_RX_RING_TAIL_REG));
 490
 491         sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base +
 492                 HNS3_RING_RX_RING_HEAD_REG));
 493
 494         sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base +
 495                 HNS3_RING_RX_RING_FBDNUM_REG));
 496
 497         sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base +
 498                 HNS3_RING_RX_RING_PKTNUM_RECORD_REG));
 499         sprintf(result[j++], "%9u", ring->rx_copybreak);
 500
 501         sprintf(result[j++], "%7s", readl_relaxed(ring->tqp->io_base +
 502                 HNS3_RING_EN_REG) ? "on" : "off");
 503
 504         if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev))
 505                 sprintf(result[j++], "%10s", readl_relaxed(ring->tqp->io_base +
 506                         HNS3_RING_RX_EN_REG) ? "on" : "off");
 507         else
 508                 sprintf(result[j++], "%10s", "NA");
 509
 510         base_add_h = readl_relaxed(ring->tqp->io_base +
 511                                         HNS3_RING_RX_RING_BASEADDR_H_REG);
 512         base_add_l = readl_relaxed(ring->tqp->io_base +
 513                                         HNS3_RING_RX_RING_BASEADDR_L_REG);
 514         sprintf(result[j++], "0x%08x%08x", base_add_h, base_add_l);
 515 }
 516
 517 static int hns3_dbg_rx_queue_info(struct hnae3_handle *h,
 518                                   char *buf, int len)
 519 {
 520         char data_str[ARRAY_SIZE(rx_queue_info_items)][HNS3_DBG_DATA_STR_LEN];
 521         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
 522         char *result[ARRAY_SIZE(rx_queue_info_items)];
 523         struct hns3_nic_priv *priv = h->priv;
 524         char content[HNS3_DBG_INFO_LEN];
 525         struct hns3_enet_ring *ring;
 526         int pos = 0;
 527         u32 i;
 528
 529         if (!priv->ring) {
 530                 dev_err(&h->pdev->dev, "priv->ring is NULL\n");
 531                 return -EFAULT;
 532         }
 533
 534         for (i = 0; i < ARRAY_SIZE(rx_queue_info_items); i++)
 535                 result[i] = &data_str[i][0];
 536
 537         hns3_dbg_fill_content(content, sizeof(content), rx_queue_info_items,
 538                               NULL, ARRAY_SIZE(rx_queue_info_items));
 539         pos += scnprintf(buf + pos, len - pos, "%s", content);
 540         for (i = 0; i < h->kinfo.num_tqps; i++) {
 541                 /* Each cycle needs to determine whether the instance is reset,
 542                  * to prevent reference to invalid memory. And need to ensure
 543                  * that the following code is executed within 100ms.
 544                  */
 545                 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) ||
 546                     test_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
 547                         return -EPERM;
 548
 549                 ring = &priv->ring[(u32)(i + h->kinfo.num_tqps)];
 550                 hns3_dump_rx_queue_info(ring, ae_dev, result, i);
 551                 hns3_dbg_fill_content(content, sizeof(content),
 552                                       rx_queue_info_items,
 553                                       (const char **)result,
 554                                       ARRAY_SIZE(rx_queue_info_items));
 555                 pos += scnprintf(buf + pos, len - pos, "%s", content);
 556         }
 557
 558         return 0;
 559 }
 560
 561 static const struct hns3_dbg_item tx_queue_info_items[] = {
 562         { "QUEUE_ID", 2 },
 563         { "BD_NUM", 2 },
 564         { "TC", 2 },
 565         { "TAIL", 2 },
 566         { "HEAD", 2 },
 567         { "FBDNUM", 2 },
 568         { "OFFSET", 2 },
 569         { "PKTNUM", 2 },
 570         { "RING_EN", 2 },
 571         { "TX_RING_EN", 2 },
 572         { "BASE_ADDR", 10 },
 573 };
 574
 575 static void hns3_dump_tx_queue_info(struct hns3_enet_ring *ring,
 576                                     struct hnae3_ae_dev *ae_dev, char **result,
 577                                     u32 index)
 578 {
 579         u32 base_add_l, base_add_h;
 580         u32 j = 0;
 581
 582         sprintf(result[j++], "%8u", index);
 583         sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base +
 584                 HNS3_RING_TX_RING_BD_NUM_REG));
 585
 586         sprintf(result[j++], "%2u", readl_relaxed(ring->tqp->io_base +
 587                 HNS3_RING_TX_RING_TC_REG));
 588
 589         sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base +
 590                 HNS3_RING_TX_RING_TAIL_REG));
 591
 592         sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base +
 593                 HNS3_RING_TX_RING_HEAD_REG));
 594
 595         sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base +
 596                 HNS3_RING_TX_RING_FBDNUM_REG));
 597
 598         sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base +
 599                 HNS3_RING_TX_RING_OFFSET_REG));
 600
 601         sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base +
 602                 HNS3_RING_TX_RING_PKTNUM_RECORD_REG));
 603
 604         sprintf(result[j++], "%7s", readl_relaxed(ring->tqp->io_base +
 605                 HNS3_RING_EN_REG) ? "on" : "off");
 606
 607         if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev))
 608                 sprintf(result[j++], "%10s", readl_relaxed(ring->tqp->io_base +
 609                         HNS3_RING_TX_EN_REG) ? "on" : "off");
 610         else
 611                 sprintf(result[j++], "%10s", "NA");
 612
 613         base_add_h = readl_relaxed(ring->tqp->io_base +
 614                                         HNS3_RING_TX_RING_BASEADDR_H_REG);
 615         base_add_l = readl_relaxed(ring->tqp->io_base +
 616                                         HNS3_RING_TX_RING_BASEADDR_L_REG);
 617         sprintf(result[j++], "0x%08x%08x", base_add_h, base_add_l);
 618 }
 619
 620 static int hns3_dbg_tx_queue_info(struct hnae3_handle *h,
 621                                   char *buf, int len)
 622 {
 623         char data_str[ARRAY_SIZE(tx_queue_info_items)][HNS3_DBG_DATA_STR_LEN];
 624         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
 625         char *result[ARRAY_SIZE(tx_queue_info_items)];
 626         struct hns3_nic_priv *priv = h->priv;
 627         char content[HNS3_DBG_INFO_LEN];
 628         struct hns3_enet_ring *ring;
 629         int pos = 0;
 630         u32 i;
 631
 632         if (!priv->ring) {
 633                 dev_err(&h->pdev->dev, "priv->ring is NULL\n");
 634                 return -EFAULT;
 635         }
 636
 637         for (i = 0; i < ARRAY_SIZE(tx_queue_info_items); i++)
 638                 result[i] = &data_str[i][0];
 639
 640         hns3_dbg_fill_content(content, sizeof(content), tx_queue_info_items,
 641                               NULL, ARRAY_SIZE(tx_queue_info_items));
 642         pos += scnprintf(buf + pos, len - pos, "%s", content);
 643
 644         for (i = 0; i < h->kinfo.num_tqps; i++) {
 645                 /* Each cycle needs to determine whether the instance is reset,
 646                  * to prevent reference to invalid memory. And need to ensure
 647                  * that the following code is executed within 100ms.
 648                  */
 649                 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) ||
 650                     test_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
 651                         return -EPERM;
 652
 653                 ring = &priv->ring[i];
 654                 hns3_dump_tx_queue_info(ring, ae_dev, result, i);
 655                 hns3_dbg_fill_content(content, sizeof(content),
 656                                       tx_queue_info_items,
 657                                       (const char **)result,
 658                                       ARRAY_SIZE(tx_queue_info_items));
 659                 pos += scnprintf(buf + pos, len - pos, "%s", content);
 660         }
 661
 662         hns3_dbg_tx_spare_info(ring, buf, len, h->kinfo.num_tqps, &pos);
 663
 664         return 0;
 665 }
 666
 667 static const struct hns3_dbg_item queue_map_items[] = {
 668         { "local_queue_id", 2 },
 669         { "global_queue_id", 2 },
 670         { "vector_id", 2 },
 671 };
 672
 673 static int hns3_dbg_queue_map(struct hnae3_handle *h, char *buf, int len)
 674 {
 675         char data_str[ARRAY_SIZE(queue_map_items)][HNS3_DBG_DATA_STR_LEN];
 676         char *result[ARRAY_SIZE(queue_map_items)];
 677         struct hns3_nic_priv *priv = h->priv;
 678         char content[HNS3_DBG_INFO_LEN];
 679         int pos = 0;
 680         int j;
 681         u32 i;
 682
 683         if (!h->ae_algo->ops->get_global_queue_id)
 684                 return -EOPNOTSUPP;
 685
 686         for (i = 0; i < ARRAY_SIZE(queue_map_items); i++)
 687                 result[i] = &data_str[i][0];
 688
 689         hns3_dbg_fill_content(content, sizeof(content), queue_map_items,
 690                               NULL, ARRAY_SIZE(queue_map_items));
 691         pos += scnprintf(buf + pos, len - pos, "%s", content);
 692         for (i = 0; i < h->kinfo.num_tqps; i++) {
 693                 if (!priv->ring || !priv->ring[i].tqp_vector)
 694                         continue;
 695                 j = 0;
 696                 sprintf(result[j++], "%u", i);
 697                 sprintf(result[j++], "%u",
 698                         h->ae_algo->ops->get_global_queue_id(h, i));
 699                 sprintf(result[j++], "%u",
 700                         priv->ring[i].tqp_vector->vector_irq);
 701                 hns3_dbg_fill_content(content, sizeof(content), queue_map_items,
 702                                       (const char **)result,
 703                                       ARRAY_SIZE(queue_map_items));
 704                 pos += scnprintf(buf + pos, len - pos, "%s", content);
 705         }
 706
 707         return 0;
 708 }
 709
 710 static const struct hns3_dbg_item rx_bd_info_items[] = {
 711         { "BD_IDX", 3 },
 712         { "L234_INFO", 2 },
 713         { "PKT_LEN", 3 },
 714         { "SIZE", 4 },
 715         { "RSS_HASH", 4 },
 716         { "FD_ID", 2 },
 717         { "VLAN_TAG", 2 },
 718         { "O_DM_VLAN_ID_FB", 2 },
 719         { "OT_VLAN_TAG", 2 },
 720         { "BD_BASE_INFO", 2 },
 721         { "PTYPE", 2 },
 722         { "HW_CSUM", 2 },
 723 };
 724
 725 static void hns3_dump_rx_bd_info(struct hns3_nic_priv *priv,
 726                                  struct hns3_desc *desc, char **result, int idx)
 727 {
 728         unsigned int j = 0;
 729
 730         sprintf(result[j++], "%5d", idx);
 731         sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.l234_info));
 732         sprintf(result[j++], "%7u", le16_to_cpu(desc->rx.pkt_len));
 733         sprintf(result[j++], "%4u", le16_to_cpu(desc->rx.size));
 734         sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.rss_hash));
 735         sprintf(result[j++], "%5u", le16_to_cpu(desc->rx.fd_id));
 736         sprintf(result[j++], "%8u", le16_to_cpu(desc->rx.vlan_tag));
 737         sprintf(result[j++], "%15u", le16_to_cpu(desc->rx.o_dm_vlan_id_fb));
 738         sprintf(result[j++], "%11u", le16_to_cpu(desc->rx.ot_vlan_tag));
 739         sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.bd_base_info));
 740         if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
 741                 u32 ol_info = le32_to_cpu(desc->rx.ol_info);
 742
 743                 sprintf(result[j++], "%5lu", hnae3_get_field(ol_info,
 744                                                              HNS3_RXD_PTYPE_M,
 745                                                              HNS3_RXD_PTYPE_S));
 746                 sprintf(result[j++], "%7u", le16_to_cpu(desc->csum));
 747         } else {
 748                 sprintf(result[j++], "NA");
 749                 sprintf(result[j++], "NA");
 750         }
 751 }
 752
 753 static int hns3_dbg_rx_bd_info(struct hns3_dbg_data *d, char *buf, int len)
 754 {
 755         char data_str[ARRAY_SIZE(rx_bd_info_items)][HNS3_DBG_DATA_STR_LEN];
 756         struct hns3_nic_priv *priv = d->handle->priv;
 757         char *result[ARRAY_SIZE(rx_bd_info_items)];
 758         char content[HNS3_DBG_INFO_LEN];
 759         struct hns3_enet_ring *ring;
 760         struct hns3_desc *desc;
 761         unsigned int i;
 762         int pos = 0;
 763
 764         if (d->qid >= d->handle->kinfo.num_tqps) {
 765                 dev_err(&d->handle->pdev->dev,
 766                         "queue%u is not in use\n", d->qid);
 767                 return -EINVAL;
 768         }
 769
 770         for (i = 0; i < ARRAY_SIZE(rx_bd_info_items); i++)
 771                 result[i] = &data_str[i][0];
 772
 773         pos += scnprintf(buf + pos, len - pos,
 774                           "Queue %u rx bd info:\n", d->qid);
 775         hns3_dbg_fill_content(content, sizeof(content), rx_bd_info_items,
 776                               NULL, ARRAY_SIZE(rx_bd_info_items));
 777         pos += scnprintf(buf + pos, len - pos, "%s", content);
 778
 779         ring = &priv->ring[d->qid + d->handle->kinfo.num_tqps];
 780         for (i = 0; i < ring->desc_num; i++) {
 781                 desc = &ring->desc[i];
 782
 783                 hns3_dump_rx_bd_info(priv, desc, result, i);
 784                 hns3_dbg_fill_content(content, sizeof(content),
 785                                       rx_bd_info_items, (const char **)result,
 786                                       ARRAY_SIZE(rx_bd_info_items));
 787                 pos += scnprintf(buf + pos, len - pos, "%s", content);
 788         }
 789
 790         return 0;
 791 }
 792
 793 static const struct hns3_dbg_item tx_bd_info_items[] = {
 794         { "BD_IDX", 5 },
 795         { "ADDRESS", 2 },
 796         { "VLAN_TAG", 2 },
 797         { "SIZE", 2 },
 798         { "T_CS_VLAN_TSO", 2 },
 799         { "OT_VLAN_TAG", 3 },
 800         { "TV", 2 },
 801         { "OLT_VLAN_LEN", 2},
 802         { "PAYLEN_OL4CS", 2},
 803         { "BD_FE_SC_VLD", 2},
 804         { "MSS_HW_CSUM", 0},
 805 };
 806
 807 static void hns3_dump_tx_bd_info(struct hns3_nic_priv *priv,
 808                                  struct hns3_desc *desc, char **result, int idx)
 809 {
 810         unsigned int j = 0;
 811
 812         sprintf(result[j++], "%6d", idx);
 813         sprintf(result[j++], "%#llx", le64_to_cpu(desc->addr));
 814         sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.vlan_tag));
 815         sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.send_size));
 816         sprintf(result[j++], "%#x",
 817                 le32_to_cpu(desc->tx.type_cs_vlan_tso_len));
 818         sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.outer_vlan_tag));
 819         sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.tv));
 820         sprintf(result[j++], "%10u",
 821                 le32_to_cpu(desc->tx.ol_type_vlan_len_msec));
 822         sprintf(result[j++], "%#x", le32_to_cpu(desc->tx.paylen_ol4cs));
 823         sprintf(result[j++], "%#x", le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri));
 824         sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.mss_hw_csum));
 825 }
 826
 827 static int hns3_dbg_tx_bd_info(struct hns3_dbg_data *d, char *buf, int len)
 828 {
 829         char data_str[ARRAY_SIZE(tx_bd_info_items)][HNS3_DBG_DATA_STR_LEN];
 830         struct hns3_nic_priv *priv = d->handle->priv;
 831         char *result[ARRAY_SIZE(tx_bd_info_items)];
 832         char content[HNS3_DBG_INFO_LEN];
 833         struct hns3_enet_ring *ring;
 834         struct hns3_desc *desc;
 835         unsigned int i;
 836         int pos = 0;
 837
 838         if (d->qid >= d->handle->kinfo.num_tqps) {
 839                 dev_err(&d->handle->pdev->dev,
 840                         "queue%u is not in use\n", d->qid);
 841                 return -EINVAL;
 842         }
 843
 844         for (i = 0; i < ARRAY_SIZE(tx_bd_info_items); i++)
 845                 result[i] = &data_str[i][0];
 846
 847         pos += scnprintf(buf + pos, len - pos,
 848                           "Queue %u tx bd info:\n", d->qid);
 849         hns3_dbg_fill_content(content, sizeof(content), tx_bd_info_items,
 850                               NULL, ARRAY_SIZE(tx_bd_info_items));
 851         pos += scnprintf(buf + pos, len - pos, "%s", content);
 852
 853         ring = &priv->ring[d->qid];
 854         for (i = 0; i < ring->desc_num; i++) {
 855                 desc = &ring->desc[i];
 856
 857                 hns3_dump_tx_bd_info(priv, desc, result, i);
 858                 hns3_dbg_fill_content(content, sizeof(content),
 859                                       tx_bd_info_items, (const char **)result,
 860                                       ARRAY_SIZE(tx_bd_info_items));
 861                 pos += scnprintf(buf + pos, len - pos, "%s", content);
 862         }
 863
 864         return 0;
 865 }
 866
 867 static void
 868 hns3_dbg_dev_caps(struct hnae3_handle *h, char *buf, int len, int *pos)
 869 {
 870         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
 871         static const char * const str[] = {"no", "yes"};
 872         unsigned long *caps = ae_dev->caps;
 873         u32 i, state;
 874
 875         *pos += scnprintf(buf + *pos, len - *pos, "dev capability:\n");
 876
 877         for (i = 0; i < ARRAY_SIZE(hns3_dbg_cap); i++) {
 878                 state = test_bit(hns3_dbg_cap[i].cap_bit, caps);
 879                 *pos += scnprintf(buf + *pos, len - *pos, "%s: %s\n",
 880                                   hns3_dbg_cap[i].name, str[state]);
 881         }
 882
 883         *pos += scnprintf(buf + *pos, len - *pos, "\n");
 884 }
 885
 886 static void
 887 hns3_dbg_dev_specs(struct hnae3_handle *h, char *buf, int len, int *pos)
 888 {
 889         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
 890         struct hnae3_dev_specs *dev_specs = &ae_dev->dev_specs;
 891         struct hnae3_knic_private_info *kinfo = &h->kinfo;
 892
 893         *pos += scnprintf(buf + *pos, len - *pos, "dev_spec:\n");
 894         *pos += scnprintf(buf + *pos, len - *pos, "MAC entry num: %u\n",
 895                           dev_specs->mac_entry_num);
 896         *pos += scnprintf(buf + *pos, len - *pos, "MNG entry num: %u\n",
 897                           dev_specs->mng_entry_num);
 898         *pos += scnprintf(buf + *pos, len - *pos, "MAX non tso bd num: %u\n",
 899                           dev_specs->max_non_tso_bd_num);
 900         *pos += scnprintf(buf + *pos, len - *pos, "RSS ind tbl size: %u\n",
 901                           dev_specs->rss_ind_tbl_size);
 902         *pos += scnprintf(buf + *pos, len - *pos, "RSS key size: %u\n",
 903                           dev_specs->rss_key_size);
 904         *pos += scnprintf(buf + *pos, len - *pos, "RSS size: %u\n",
 905                           kinfo->rss_size);
 906         *pos += scnprintf(buf + *pos, len - *pos, "Allocated RSS size: %u\n",
 907                           kinfo->req_rss_size);
 908         *pos += scnprintf(buf + *pos, len - *pos,
 909                           "Task queue pairs numbers: %u\n",
 910                           kinfo->num_tqps);
 911         *pos += scnprintf(buf + *pos, len - *pos, "RX buffer length: %u\n",
 912                           kinfo->rx_buf_len);
 913         *pos += scnprintf(buf + *pos, len - *pos, "Desc num per TX queue: %u\n",
 914                           kinfo->num_tx_desc);
 915         *pos += scnprintf(buf + *pos, len - *pos, "Desc num per RX queue: %u\n",
 916                           kinfo->num_rx_desc);
 917         *pos += scnprintf(buf + *pos, len - *pos,
 918                           "Total number of enabled TCs: %u\n",
 919                           kinfo->tc_info.num_tc);
 920         *pos += scnprintf(buf + *pos, len - *pos, "MAX INT QL: %u\n",
 921                           dev_specs->int_ql_max);
 922         *pos += scnprintf(buf + *pos, len - *pos, "MAX INT GL: %u\n",
 923                           dev_specs->max_int_gl);
 924         *pos += scnprintf(buf + *pos, len - *pos, "MAX TM RATE: %u\n",
 925                           dev_specs->max_tm_rate);
 926         *pos += scnprintf(buf + *pos, len - *pos, "MAX QSET number: %u\n",
 927                           dev_specs->max_qset_num);
 928 }
 929
 930 static int hns3_dbg_dev_info(struct hnae3_handle *h, char *buf, int len)
 931 {
 932         int pos = 0;
 933
 934         hns3_dbg_dev_caps(h, buf, len, &pos);
 935
 936         hns3_dbg_dev_specs(h, buf, len, &pos);
 937
 938         return 0;
 939 }
 940
 941 static int hns3_dbg_get_cmd_index(struct hnae3_handle *handle,
 942                                   const unsigned char *name, u32 *index)
 943 {
 944         u32 i;
 945
 946         for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) {
 947                 if (!strncmp(name, hns3_dbg_cmd[i].name,
 948                              strlen(hns3_dbg_cmd[i].name))) {
 949                         *index = i;
 950                         return 0;
 951                 }
 952         }
 953
 954         dev_err(&handle->pdev->dev, "unknown command(%s)\n", name);
 955         return -EINVAL;
 956 }
 957
 958 static const struct hns3_dbg_func hns3_dbg_cmd_func[] = {
 959         {
 960                 .cmd = HNAE3_DBG_CMD_QUEUE_MAP,
 961                 .dbg_dump = hns3_dbg_queue_map,
 962         },
 963         {
 964                 .cmd = HNAE3_DBG_CMD_DEV_INFO,
 965                 .dbg_dump = hns3_dbg_dev_info,
 966         },
 967         {
 968                 .cmd = HNAE3_DBG_CMD_TX_BD,
 969                 .dbg_dump_bd = hns3_dbg_tx_bd_info,
 970         },
 971         {
 972                 .cmd = HNAE3_DBG_CMD_RX_BD,
 973                 .dbg_dump_bd = hns3_dbg_rx_bd_info,
 974         },
 975         {
 976                 .cmd = HNAE3_DBG_CMD_RX_QUEUE_INFO,
 977                 .dbg_dump = hns3_dbg_rx_queue_info,
 978         },
 979         {
 980                 .cmd = HNAE3_DBG_CMD_TX_QUEUE_INFO,
 981                 .dbg_dump = hns3_dbg_tx_queue_info,
 982         },
 983 };
 984
 985 static int hns3_dbg_read_cmd(struct hns3_dbg_data *dbg_data,
 986                              enum hnae3_dbg_cmd cmd, char *buf, int len)
 987 {
 988         const struct hnae3_ae_ops *ops = dbg_data->handle->ae_algo->ops;
 989         const struct hns3_dbg_func *cmd_func;
 990         u32 i;
 991
 992         for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd_func); i++) {
 993                 if (cmd == hns3_dbg_cmd_func[i].cmd) {
 994                         cmd_func = &hns3_dbg_cmd_func[i];
 995                         if (cmd_func->dbg_dump)
 996                                 return cmd_func->dbg_dump(dbg_data->handle, buf,
 997                                                           len);
 998                         else
 999                                 return cmd_func->dbg_dump_bd(dbg_data, buf,
1000                                                              len);
1001                 }
1002         }
1003
1004         if (!ops->dbg_read_cmd)
1005                 return -EOPNOTSUPP;
1006
1007         return ops->dbg_read_cmd(dbg_data->handle, cmd, buf, len);
1008 }
1009
1010 static ssize_t hns3_dbg_read(struct file *filp, char __user *buffer,
1011                              size_t count, loff_t *ppos)
1012 {
1013         struct hns3_dbg_data *dbg_data = filp->private_data;
1014         struct hnae3_handle *handle = dbg_data->handle;
1015         struct hns3_nic_priv *priv = handle->priv;
1016         ssize_t size = 0;
1017         char **save_buf;
1018         char *read_buf;
1019         u32 index;
1020         int ret;
1021
1022         ret = hns3_dbg_get_cmd_index(handle, filp->f_path.dentry->d_iname,
1023                                      &index);
1024         if (ret)
1025                 return ret;
1026
1027         save_buf = &hns3_dbg_cmd[index].buf;
1028
1029         if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) ||
1030             test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) {
1031                 ret = -EBUSY;
1032                 goto out;
1033         }
1034
1035         if (*save_buf) {
1036                 read_buf = *save_buf;
1037         } else {
1038                 read_buf = kvzalloc(hns3_dbg_cmd[index].buf_len, GFP_KERNEL);
1039                 if (!read_buf)
1040                         return -ENOMEM;
1041
1042                 /* save the buffer addr until the last read operation */
1043                 *save_buf = read_buf;
1044         }
1045
1046         /* get data ready for the first time to read */
1047         if (!*ppos) {
1048                 ret = hns3_dbg_read_cmd(dbg_data, hns3_dbg_cmd[index].cmd,
1049                                         read_buf, hns3_dbg_cmd[index].buf_len);
1050                 if (ret)
1051                         goto out;
1052         }
1053
1054         size = simple_read_from_buffer(buffer, count, ppos, read_buf,
1055                                        strlen(read_buf));
1056         if (size > 0)
1057                 return size;
1058
1059 out:
1060         /* free the buffer for the last read operation */
1061         if (*save_buf) {
1062                 kvfree(*save_buf);
1063                 *save_buf = NULL;
1064         }
1065
1066         return ret;
1067 }
1068
1069 static const struct file_operations hns3_dbg_fops = {
1070         .owner = THIS_MODULE,
1071         .open  = simple_open,
1072         .read  = hns3_dbg_read,
1073 };
1074
1075 static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, u32 cmd)
1076 {
1077         struct dentry *entry_dir;
1078         struct hns3_dbg_data *data;
1079         u16 max_queue_num;
1080         unsigned int i;
1081
1082         entry_dir = hns3_dbg_dentry[hns3_dbg_cmd[cmd].dentry].dentry;
1083         max_queue_num = hns3_get_max_available_channels(handle);
1084         data = devm_kzalloc(&handle->pdev->dev, max_queue_num * sizeof(*data),
1085                             GFP_KERNEL);
1086         if (!data)
1087                 return -ENOMEM;
1088
1089         for (i = 0; i < max_queue_num; i++) {
1090                 char name[HNS3_DBG_FILE_NAME_LEN];
1091
1092                 data[i].handle = handle;
1093                 data[i].qid = i;
1094                 sprintf(name, "%s%u", hns3_dbg_cmd[cmd].name, i);
1095                 debugfs_create_file(name, 0400, entry_dir, &data[i],
1096                                     &hns3_dbg_fops);
1097         }
1098
1099         return 0;
1100 }
1101
1102 static int
1103 hns3_dbg_common_file_init(struct hnae3_handle *handle, u32 cmd)
1104 {
1105         struct hns3_dbg_data *data;
1106         struct dentry *entry_dir;
1107
1108         data = devm_kzalloc(&handle->pdev->dev, sizeof(*data), GFP_KERNEL);
1109         if (!data)
1110                 return -ENOMEM;
1111
1112         data->handle = handle;
1113         entry_dir = hns3_dbg_dentry[hns3_dbg_cmd[cmd].dentry].dentry;
1114         debugfs_create_file(hns3_dbg_cmd[cmd].name, 0400, entry_dir,
1115                             data, &hns3_dbg_fops);
1116
1117         return 0;
1118 }
1119
1120 int hns3_dbg_init(struct hnae3_handle *handle)
1121 {
1122         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
1123         const char *name = pci_name(handle->pdev);
1124         int ret;
1125         u32 i;
1126
1127         hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry =
1128                                 debugfs_create_dir(name, hns3_dbgfs_root);
1129         handle->hnae3_dbgfs = hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry;
1130
1131         for (i = 0; i < HNS3_DBG_DENTRY_COMMON; i++)
1132                 hns3_dbg_dentry[i].dentry =
1133                         debugfs_create_dir(hns3_dbg_dentry[i].name,
1134                                            handle->hnae3_dbgfs);
1135
1136         for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) {
1137                 if ((hns3_dbg_cmd[i].cmd == HNAE3_DBG_CMD_TM_NODES &&
1138                      ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) ||
1139                     (hns3_dbg_cmd[i].cmd == HNAE3_DBG_CMD_PTP_INFO &&
1140                      !test_bit(HNAE3_DEV_SUPPORT_PTP_B, ae_dev->caps)))
1141                         continue;
1142
1143                 if (!hns3_dbg_cmd[i].init) {
1144                         dev_err(&handle->pdev->dev,
1145                                 "cmd %s lack of init func\n",
1146                                 hns3_dbg_cmd[i].name);
1147                         ret = -EINVAL;
1148                         goto out;
1149                 }
1150
1151                 ret = hns3_dbg_cmd[i].init(handle, i);
1152                 if (ret) {
1153                         dev_err(&handle->pdev->dev, "failed to init cmd %s\n",
1154                                 hns3_dbg_cmd[i].name);
1155                         goto out;
1156                 }
1157         }
1158
1159         return 0;
1160
1161 out:
1162         debugfs_remove_recursive(handle->hnae3_dbgfs);
1163         handle->hnae3_dbgfs = NULL;
1164         return ret;
1165 }
1166
1167 void hns3_dbg_uninit(struct hnae3_handle *handle)
1168 {
1169         u32 i;
1170
1171         for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++)
1172                 if (hns3_dbg_cmd[i].buf) {
1173                         kvfree(hns3_dbg_cmd[i].buf);
1174                         hns3_dbg_cmd[i].buf = NULL;
1175                 }
1176
1177         debugfs_remove_recursive(handle->hnae3_dbgfs);
1178         handle->hnae3_dbgfs = NULL;
1179 }
1180
1181 void hns3_dbg_register_debugfs(const char *debugfs_dir_name)
1182 {
1183         hns3_dbgfs_root = debugfs_create_dir(debugfs_dir_name, NULL);
1184 }
1185
1186 void hns3_dbg_unregister_debugfs(void)
1187 {
1188         debugfs_remove_recursive(hns3_dbgfs_root);
1189         hns3_dbgfs_root = NULL;
1190 }