1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* drivers/net/ethernet/freescale/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
13 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
14 * Copyright 2007 MontaVista Software, Inc.
16 * Gianfar: AKA Lambda Draconis, "Dragon"
24 * The driver is initialized through of_device. Configuration information
25 * is therefore conveyed through an OF-style device tree.
27 * The Gianfar Ethernet Controller uses a ring of buffer
28 * descriptors. The beginning is indicated by a register
29 * pointing to the physical address of the start of the ring.
30 * The end is determined by a "wrap" bit being set in the
31 * last descriptor of the ring.
33 * When a packet is received, the RXF bit in the
34 * IEVENT register is set, triggering an interrupt when the
35 * corresponding bit in the IMASK register is also set (if
36 * interrupt coalescing is active, then the interrupt may not
37 * happen immediately, but will wait until either a set number
38 * of frames or amount of time have passed). In NAPI, the
39 * interrupt handler will signal there is work to be done, and
40 * exit. This method will start at the last known empty
41 * descriptor, and process every subsequent descriptor until there
42 * are none left with data (NAPI will stop after a set number of
43 * packets to give time to other tasks, but will eventually
44 * process all the packets). The data arrives inside a
45 * pre-allocated skb, and so after the skb is passed up to the
46 * stack, a new skb must be allocated, and the address field in
47 * the buffer descriptor must be updated to indicate this new
50 * When the kernel requests that a packet be transmitted, the
51 * driver starts where it left off last time, and points the
52 * descriptor at the buffer which was passed in. The driver
53 * then informs the DMA engine that there are packets ready to
54 * be transmitted. Once the controller is finished transmitting
55 * the packet, an interrupt may be triggered (under the same
56 * conditions as for reception, but depending on the TXF bit).
57 * The driver then cleans up the buffer.
60 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
62 #include <linux/kernel.h>
63 #include <linux/string.h>
64 #include <linux/errno.h>
65 #include <linux/unistd.h>
66 #include <linux/slab.h>
67 #include <linux/interrupt.h>
68 #include <linux/delay.h>
69 #include <linux/netdevice.h>
70 #include <linux/etherdevice.h>
71 #include <linux/skbuff.h>
72 #include <linux/if_vlan.h>
73 #include <linux/spinlock.h>
75 #include <linux/of_address.h>
76 #include <linux/of_irq.h>
77 #include <linux/of_mdio.h>
78 #include <linux/of_platform.h>
80 #include <linux/tcp.h>
81 #include <linux/udp.h>
83 #include <linux/net_tstamp.h>
88 #include <asm/mpc85xx.h>
91 #include <linux/uaccess.h>
92 #include <linux/module.h>
93 #include <linux/dma-mapping.h>
94 #include <linux/crc32.h>
95 #include <linux/mii.h>
96 #include <linux/phy.h>
97 #include <linux/phy_fixed.h>
99 #include <linux/of_net.h>
103 #define TX_TIMEOUT (5*HZ)
105 MODULE_AUTHOR("Freescale Semiconductor, Inc");
106 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
107 MODULE_LICENSE("GPL");
109 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
114 bdp->bufPtr = cpu_to_be32(buf);
116 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
117 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
118 lstatus |= BD_LFLAG(RXBD_WRAP);
122 bdp->lstatus = cpu_to_be32(lstatus);
125 static void gfar_init_tx_rx_base(struct gfar_private *priv)
127 struct gfar __iomem *regs = priv->gfargrp[0].regs;
131 baddr = ®s->tbase0;
132 for (i = 0; i < priv->num_tx_queues; i++) {
133 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
137 baddr = ®s->rbase0;
138 for (i = 0; i < priv->num_rx_queues; i++) {
139 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
144 static void gfar_init_rqprm(struct gfar_private *priv)
146 struct gfar __iomem *regs = priv->gfargrp[0].regs;
150 baddr = ®s->rqprm0;
151 for (i = 0; i < priv->num_rx_queues; i++) {
152 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
153 (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
158 static void gfar_rx_offload_en(struct gfar_private *priv)
160 /* set this when rx hw offload (TOE) functions are being used */
161 priv->uses_rxfcb = 0;
163 if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
164 priv->uses_rxfcb = 1;
166 if (priv->hwts_rx_en || priv->rx_filer_enable)
167 priv->uses_rxfcb = 1;
170 static void gfar_mac_rx_config(struct gfar_private *priv)
172 struct gfar __iomem *regs = priv->gfargrp[0].regs;
175 if (priv->rx_filer_enable) {
176 rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
177 /* Program the RIR0 reg with the required distribution */
178 if (priv->poll_mode == GFAR_SQ_POLLING)
179 gfar_write(®s->rir0, DEFAULT_2RXQ_RIR0);
180 else /* GFAR_MQ_POLLING */
181 gfar_write(®s->rir0, DEFAULT_8RXQ_RIR0);
184 /* Restore PROMISC mode */
185 if (priv->ndev->flags & IFF_PROMISC)
188 if (priv->ndev->features & NETIF_F_RXCSUM)
189 rctrl |= RCTRL_CHECKSUMMING;
191 if (priv->extended_hash)
192 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
195 rctrl &= ~RCTRL_PAL_MASK;
196 rctrl |= RCTRL_PADDING(priv->padding);
199 /* Enable HW time stamping if requested from user space */
200 if (priv->hwts_rx_en)
201 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
203 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
204 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
206 /* Clear the LFC bit */
207 gfar_write(®s->rctrl, rctrl);
208 /* Init flow control threshold values */
209 gfar_init_rqprm(priv);
210 gfar_write(®s->ptv, DEFAULT_LFC_PTVVAL);
213 /* Init rctrl based on our settings */
214 gfar_write(®s->rctrl, rctrl);
217 static void gfar_mac_tx_config(struct gfar_private *priv)
219 struct gfar __iomem *regs = priv->gfargrp[0].regs;
222 if (priv->ndev->features & NETIF_F_IP_CSUM)
223 tctrl |= TCTRL_INIT_CSUM;
225 if (priv->prio_sched_en)
226 tctrl |= TCTRL_TXSCHED_PRIO;
228 tctrl |= TCTRL_TXSCHED_WRRS;
229 gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT);
230 gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT);
233 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
234 tctrl |= TCTRL_VLINS;
236 gfar_write(®s->tctrl, tctrl);
239 static void gfar_configure_coalescing(struct gfar_private *priv,
240 unsigned long tx_mask, unsigned long rx_mask)
242 struct gfar __iomem *regs = priv->gfargrp[0].regs;
245 if (priv->mode == MQ_MG_MODE) {
248 baddr = ®s->txic0;
249 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
250 gfar_write(baddr + i, 0);
251 if (likely(priv->tx_queue[i]->txcoalescing))
252 gfar_write(baddr + i, priv->tx_queue[i]->txic);
255 baddr = ®s->rxic0;
256 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
257 gfar_write(baddr + i, 0);
258 if (likely(priv->rx_queue[i]->rxcoalescing))
259 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
262 /* Backward compatible case -- even if we enable
263 * multiple queues, there's only single reg to program
265 gfar_write(®s->txic, 0);
266 if (likely(priv->tx_queue[0]->txcoalescing))
267 gfar_write(®s->txic, priv->tx_queue[0]->txic);
269 gfar_write(®s->rxic, 0);
270 if (unlikely(priv->rx_queue[0]->rxcoalescing))
271 gfar_write(®s->rxic, priv->rx_queue[0]->rxic);
275 static void gfar_configure_coalescing_all(struct gfar_private *priv)
277 gfar_configure_coalescing(priv, 0xFF, 0xFF);
280 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
282 struct gfar_private *priv = netdev_priv(dev);
283 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
284 unsigned long tx_packets = 0, tx_bytes = 0;
287 for (i = 0; i < priv->num_rx_queues; i++) {
288 rx_packets += priv->rx_queue[i]->stats.rx_packets;
289 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
290 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
293 dev->stats.rx_packets = rx_packets;
294 dev->stats.rx_bytes = rx_bytes;
295 dev->stats.rx_dropped = rx_dropped;
297 for (i = 0; i < priv->num_tx_queues; i++) {
298 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
299 tx_packets += priv->tx_queue[i]->stats.tx_packets;
302 dev->stats.tx_bytes = tx_bytes;
303 dev->stats.tx_packets = tx_packets;
308 /* Set the appropriate hash bit for the given addr */
309 /* The algorithm works like so:
310 * 1) Take the Destination Address (ie the multicast address), and
311 * do a CRC on it (little endian), and reverse the bits of the
313 * 2) Use the 8 most significant bits as a hash into a 256-entry
314 * table. The table is controlled through 8 32-bit registers:
315 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
316 * gaddr7. This means that the 3 most significant bits in the
317 * hash index which gaddr register to use, and the 5 other bits
318 * indicate which bit (assuming an IBM numbering scheme, which
319 * for PowerPC (tm) is usually the case) in the register holds
322 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
325 struct gfar_private *priv = netdev_priv(dev);
326 u32 result = ether_crc(ETH_ALEN, addr);
327 int width = priv->hash_width;
328 u8 whichbit = (result >> (32 - width)) & 0x1f;
329 u8 whichreg = result >> (32 - width + 5);
330 u32 value = (1 << (31-whichbit));
332 tempval = gfar_read(priv->hash_regs[whichreg]);
334 gfar_write(priv->hash_regs[whichreg], tempval);
337 /* There are multiple MAC Address register pairs on some controllers
338 * This function sets the numth pair to a given address
340 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
343 struct gfar_private *priv = netdev_priv(dev);
344 struct gfar __iomem *regs = priv->gfargrp[0].regs;
346 u32 __iomem *macptr = ®s->macstnaddr1;
350 /* For a station address of 0x12345678ABCD in transmission
351 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
352 * MACnADDR2 is set to 0x34120000.
354 tempval = (addr[5] << 24) | (addr[4] << 16) |
355 (addr[3] << 8) | addr[2];
357 gfar_write(macptr, tempval);
359 tempval = (addr[1] << 24) | (addr[0] << 16);
361 gfar_write(macptr+1, tempval);
364 static int gfar_set_mac_addr(struct net_device *dev, void *p)
366 eth_mac_addr(dev, p);
368 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
373 static void gfar_ints_disable(struct gfar_private *priv)
376 for (i = 0; i < priv->num_grps; i++) {
377 struct gfar __iomem *regs = priv->gfargrp[i].regs;
379 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
381 /* Initialize IMASK */
382 gfar_write(®s->imask, IMASK_INIT_CLEAR);
386 static void gfar_ints_enable(struct gfar_private *priv)
389 for (i = 0; i < priv->num_grps; i++) {
390 struct gfar __iomem *regs = priv->gfargrp[i].regs;
391 /* Unmask the interrupts we look for */
392 gfar_write(®s->imask, IMASK_DEFAULT);
396 static int gfar_alloc_tx_queues(struct gfar_private *priv)
400 for (i = 0; i < priv->num_tx_queues; i++) {
401 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
403 if (!priv->tx_queue[i])
406 priv->tx_queue[i]->tx_skbuff = NULL;
407 priv->tx_queue[i]->qindex = i;
408 priv->tx_queue[i]->dev = priv->ndev;
409 spin_lock_init(&(priv->tx_queue[i]->txlock));
414 static int gfar_alloc_rx_queues(struct gfar_private *priv)
418 for (i = 0; i < priv->num_rx_queues; i++) {
419 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
421 if (!priv->rx_queue[i])
424 priv->rx_queue[i]->qindex = i;
425 priv->rx_queue[i]->ndev = priv->ndev;
430 static void gfar_free_tx_queues(struct gfar_private *priv)
434 for (i = 0; i < priv->num_tx_queues; i++)
435 kfree(priv->tx_queue[i]);
438 static void gfar_free_rx_queues(struct gfar_private *priv)
442 for (i = 0; i < priv->num_rx_queues; i++)
443 kfree(priv->rx_queue[i]);
446 static void unmap_group_regs(struct gfar_private *priv)
450 for (i = 0; i < MAXGROUPS; i++)
451 if (priv->gfargrp[i].regs)
452 iounmap(priv->gfargrp[i].regs);
455 static void free_gfar_dev(struct gfar_private *priv)
459 for (i = 0; i < priv->num_grps; i++)
460 for (j = 0; j < GFAR_NUM_IRQS; j++) {
461 kfree(priv->gfargrp[i].irqinfo[j]);
462 priv->gfargrp[i].irqinfo[j] = NULL;
465 free_netdev(priv->ndev);
468 static void disable_napi(struct gfar_private *priv)
472 for (i = 0; i < priv->num_grps; i++) {
473 napi_disable(&priv->gfargrp[i].napi_rx);
474 napi_disable(&priv->gfargrp[i].napi_tx);
478 static void enable_napi(struct gfar_private *priv)
482 for (i = 0; i < priv->num_grps; i++) {
483 napi_enable(&priv->gfargrp[i].napi_rx);
484 napi_enable(&priv->gfargrp[i].napi_tx);
488 static int gfar_parse_group(struct device_node *np,
489 struct gfar_private *priv, const char *model)
491 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
494 for (i = 0; i < GFAR_NUM_IRQS; i++) {
495 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
497 if (!grp->irqinfo[i])
501 grp->regs = of_iomap(np, 0);
505 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
507 /* If we aren't the FEC we have multiple interrupts */
508 if (model && strcasecmp(model, "FEC")) {
509 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
510 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
511 if (!gfar_irq(grp, TX)->irq ||
512 !gfar_irq(grp, RX)->irq ||
513 !gfar_irq(grp, ER)->irq)
518 spin_lock_init(&grp->grplock);
519 if (priv->mode == MQ_MG_MODE) {
520 u32 rxq_mask, txq_mask;
523 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
524 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
526 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
528 grp->rx_bit_map = rxq_mask ?
529 rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
532 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
534 grp->tx_bit_map = txq_mask ?
535 txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
538 if (priv->poll_mode == GFAR_SQ_POLLING) {
539 /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
540 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
541 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
544 grp->rx_bit_map = 0xFF;
545 grp->tx_bit_map = 0xFF;
548 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
549 * right to left, so we need to revert the 8 bits to get the q index
551 grp->rx_bit_map = bitrev8(grp->rx_bit_map);
552 grp->tx_bit_map = bitrev8(grp->tx_bit_map);
554 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
555 * also assign queues to groups
557 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
559 grp->rx_queue = priv->rx_queue[i];
560 grp->num_rx_queues++;
561 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
562 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
563 priv->rx_queue[i]->grp = grp;
566 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
568 grp->tx_queue = priv->tx_queue[i];
569 grp->num_tx_queues++;
570 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
571 priv->tqueue |= (TQUEUE_EN0 >> i);
572 priv->tx_queue[i]->grp = grp;
580 static int gfar_of_group_count(struct device_node *np)
582 struct device_node *child;
585 for_each_available_child_of_node(np, child)
586 if (of_node_name_eq(child, "queue-group"))
592 /* Reads the controller's registers to determine what interface
593 * connects it to the PHY.
595 static phy_interface_t gfar_get_interface(struct net_device *dev)
597 struct gfar_private *priv = netdev_priv(dev);
598 struct gfar __iomem *regs = priv->gfargrp[0].regs;
601 ecntrl = gfar_read(®s->ecntrl);
603 if (ecntrl & ECNTRL_SGMII_MODE)
604 return PHY_INTERFACE_MODE_SGMII;
606 if (ecntrl & ECNTRL_TBI_MODE) {
607 if (ecntrl & ECNTRL_REDUCED_MODE)
608 return PHY_INTERFACE_MODE_RTBI;
610 return PHY_INTERFACE_MODE_TBI;
613 if (ecntrl & ECNTRL_REDUCED_MODE) {
614 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
615 return PHY_INTERFACE_MODE_RMII;
618 phy_interface_t interface = priv->interface;
620 /* This isn't autodetected right now, so it must
621 * be set by the device tree or platform code.
623 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
624 return PHY_INTERFACE_MODE_RGMII_ID;
626 return PHY_INTERFACE_MODE_RGMII;
630 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
631 return PHY_INTERFACE_MODE_GMII;
633 return PHY_INTERFACE_MODE_MII;
636 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
639 const void *mac_addr;
641 phy_interface_t interface;
642 struct net_device *dev = NULL;
643 struct gfar_private *priv = NULL;
644 struct device_node *np = ofdev->dev.of_node;
645 struct device_node *child = NULL;
648 unsigned int num_tx_qs, num_rx_qs;
649 unsigned short mode, poll_mode;
654 if (of_device_is_compatible(np, "fsl,etsec2")) {
656 poll_mode = GFAR_SQ_POLLING;
659 poll_mode = GFAR_SQ_POLLING;
662 if (mode == SQ_SG_MODE) {
665 } else { /* MQ_MG_MODE */
666 /* get the actual number of supported groups */
667 unsigned int num_grps = gfar_of_group_count(np);
669 if (num_grps == 0 || num_grps > MAXGROUPS) {
670 dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
672 pr_err("Cannot do alloc_etherdev, aborting\n");
676 if (poll_mode == GFAR_SQ_POLLING) {
677 num_tx_qs = num_grps; /* one txq per int group */
678 num_rx_qs = num_grps; /* one rxq per int group */
679 } else { /* GFAR_MQ_POLLING */
680 u32 tx_queues, rx_queues;
683 /* parse the num of HW tx and rx queues */
684 ret = of_property_read_u32(np, "fsl,num_tx_queues",
686 num_tx_qs = ret ? 1 : tx_queues;
688 ret = of_property_read_u32(np, "fsl,num_rx_queues",
690 num_rx_qs = ret ? 1 : rx_queues;
694 if (num_tx_qs > MAX_TX_QS) {
695 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
696 num_tx_qs, MAX_TX_QS);
697 pr_err("Cannot do alloc_etherdev, aborting\n");
701 if (num_rx_qs > MAX_RX_QS) {
702 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
703 num_rx_qs, MAX_RX_QS);
704 pr_err("Cannot do alloc_etherdev, aborting\n");
708 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
713 priv = netdev_priv(dev);
717 priv->poll_mode = poll_mode;
719 priv->num_tx_queues = num_tx_qs;
720 netif_set_real_num_rx_queues(dev, num_rx_qs);
721 priv->num_rx_queues = num_rx_qs;
723 err = gfar_alloc_tx_queues(priv);
725 goto tx_alloc_failed;
727 err = gfar_alloc_rx_queues(priv);
729 goto rx_alloc_failed;
731 err = of_property_read_string(np, "model", &model);
733 pr_err("Device model property missing, aborting\n");
734 goto rx_alloc_failed;
737 /* Init Rx queue filer rule set linked list */
738 INIT_LIST_HEAD(&priv->rx_list.list);
739 priv->rx_list.count = 0;
740 mutex_init(&priv->rx_queue_access);
742 for (i = 0; i < MAXGROUPS; i++)
743 priv->gfargrp[i].regs = NULL;
745 /* Parse and initialize group specific information */
746 if (priv->mode == MQ_MG_MODE) {
747 for_each_available_child_of_node(np, child) {
748 if (!of_node_name_eq(child, "queue-group"))
751 err = gfar_parse_group(child, priv, model);
757 } else { /* SQ_SG_MODE */
758 err = gfar_parse_group(np, priv, model);
763 if (of_property_read_bool(np, "bd-stash")) {
764 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
765 priv->bd_stash_en = 1;
768 err = of_property_read_u32(np, "rx-stash-len", &stash_len);
771 priv->rx_stash_size = stash_len;
773 err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
776 priv->rx_stash_index = stash_idx;
778 if (stash_len || stash_idx)
779 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
781 mac_addr = of_get_mac_address(np);
783 if (!IS_ERR(mac_addr)) {
784 ether_addr_copy(dev->dev_addr, mac_addr);
786 eth_hw_addr_random(dev);
787 dev_info(&ofdev->dev, "Using random MAC address: %pM\n", dev->dev_addr);
790 if (model && !strcasecmp(model, "TSEC"))
791 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
792 FSL_GIANFAR_DEV_HAS_COALESCE |
793 FSL_GIANFAR_DEV_HAS_RMON |
794 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
796 if (model && !strcasecmp(model, "eTSEC"))
797 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
798 FSL_GIANFAR_DEV_HAS_COALESCE |
799 FSL_GIANFAR_DEV_HAS_RMON |
800 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
801 FSL_GIANFAR_DEV_HAS_CSUM |
802 FSL_GIANFAR_DEV_HAS_VLAN |
803 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
804 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
805 FSL_GIANFAR_DEV_HAS_TIMER |
806 FSL_GIANFAR_DEV_HAS_RX_FILER;
808 /* Use PHY connection type from the DT node if one is specified there.
809 * rgmii-id really needs to be specified. Other types can be
810 * detected by hardware
812 err = of_get_phy_mode(np, &interface);
814 priv->interface = interface;
816 priv->interface = gfar_get_interface(dev);
818 if (of_find_property(np, "fsl,magic-packet", NULL))
819 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
821 if (of_get_property(np, "fsl,wake-on-filer", NULL))
822 priv->device_flags |= FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER;
824 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
826 /* In the case of a fixed PHY, the DT node associated
827 * to the PHY is the Ethernet MAC DT node.
829 if (!priv->phy_node && of_phy_is_fixed_link(np)) {
830 err = of_phy_register_fixed_link(np);
834 priv->phy_node = of_node_get(np);
837 /* Find the TBI PHY. If it's not there, we don't support SGMII */
838 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
843 unmap_group_regs(priv);
845 gfar_free_rx_queues(priv);
847 gfar_free_tx_queues(priv);
852 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
855 u32 rqfpr = FPR_FILER_MASK;
859 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
860 priv->ftp_rqfpr[rqfar] = rqfpr;
861 priv->ftp_rqfcr[rqfar] = rqfcr;
862 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
865 rqfcr = RQFCR_CMP_NOMATCH;
866 priv->ftp_rqfpr[rqfar] = rqfpr;
867 priv->ftp_rqfcr[rqfar] = rqfcr;
868 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
871 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
873 priv->ftp_rqfcr[rqfar] = rqfcr;
874 priv->ftp_rqfpr[rqfar] = rqfpr;
875 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
878 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
880 priv->ftp_rqfcr[rqfar] = rqfcr;
881 priv->ftp_rqfpr[rqfar] = rqfpr;
882 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
887 static void gfar_init_filer_table(struct gfar_private *priv)
890 u32 rqfar = MAX_FILER_IDX;
892 u32 rqfpr = FPR_FILER_MASK;
895 rqfcr = RQFCR_CMP_MATCH;
896 priv->ftp_rqfcr[rqfar] = rqfcr;
897 priv->ftp_rqfpr[rqfar] = rqfpr;
898 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
900 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
901 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
902 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
903 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
904 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
905 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
907 /* cur_filer_idx indicated the first non-masked rule */
908 priv->cur_filer_idx = rqfar;
910 /* Rest are masked rules */
911 rqfcr = RQFCR_CMP_NOMATCH;
912 for (i = 0; i < rqfar; i++) {
913 priv->ftp_rqfcr[i] = rqfcr;
914 priv->ftp_rqfpr[i] = rqfpr;
915 gfar_write_filer(priv, i, rqfcr, rqfpr);
920 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
922 unsigned int pvr = mfspr(SPRN_PVR);
923 unsigned int svr = mfspr(SPRN_SVR);
924 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
925 unsigned int rev = svr & 0xffff;
927 /* MPC8313 Rev 2.0 and higher; All MPC837x */
928 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
929 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
930 priv->errata |= GFAR_ERRATA_74;
932 /* MPC8313 and MPC837x all rev */
933 if ((pvr == 0x80850010 && mod == 0x80b0) ||
934 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
935 priv->errata |= GFAR_ERRATA_76;
937 /* MPC8313 Rev < 2.0 */
938 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
939 priv->errata |= GFAR_ERRATA_12;
942 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
944 unsigned int svr = mfspr(SPRN_SVR);
946 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
947 priv->errata |= GFAR_ERRATA_12;
948 /* P2020/P1010 Rev 1; MPC8548 Rev 2 */
949 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
950 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)) ||
951 ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) < 0x31)))
952 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
956 static void gfar_detect_errata(struct gfar_private *priv)
958 struct device *dev = &priv->ofdev->dev;
960 /* no plans to fix */
961 priv->errata |= GFAR_ERRATA_A002;
964 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
965 __gfar_detect_errata_85xx(priv);
966 else /* non-mpc85xx parts, i.e. e300 core based */
967 __gfar_detect_errata_83xx(priv);
971 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
975 static void gfar_init_addr_hash_table(struct gfar_private *priv)
977 struct gfar __iomem *regs = priv->gfargrp[0].regs;
979 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
980 priv->extended_hash = 1;
981 priv->hash_width = 9;
983 priv->hash_regs[0] = ®s->igaddr0;
984 priv->hash_regs[1] = ®s->igaddr1;
985 priv->hash_regs[2] = ®s->igaddr2;
986 priv->hash_regs[3] = ®s->igaddr3;
987 priv->hash_regs[4] = ®s->igaddr4;
988 priv->hash_regs[5] = ®s->igaddr5;
989 priv->hash_regs[6] = ®s->igaddr6;
990 priv->hash_regs[7] = ®s->igaddr7;
991 priv->hash_regs[8] = ®s->gaddr0;
992 priv->hash_regs[9] = ®s->gaddr1;
993 priv->hash_regs[10] = ®s->gaddr2;
994 priv->hash_regs[11] = ®s->gaddr3;
995 priv->hash_regs[12] = ®s->gaddr4;
996 priv->hash_regs[13] = ®s->gaddr5;
997 priv->hash_regs[14] = ®s->gaddr6;
998 priv->hash_regs[15] = ®s->gaddr7;
1001 priv->extended_hash = 0;
1002 priv->hash_width = 8;
1004 priv->hash_regs[0] = ®s->gaddr0;
1005 priv->hash_regs[1] = ®s->gaddr1;
1006 priv->hash_regs[2] = ®s->gaddr2;
1007 priv->hash_regs[3] = ®s->gaddr3;
1008 priv->hash_regs[4] = ®s->gaddr4;
1009 priv->hash_regs[5] = ®s->gaddr5;
1010 priv->hash_regs[6] = ®s->gaddr6;
1011 priv->hash_regs[7] = ®s->gaddr7;
1015 static int __gfar_is_rx_idle(struct gfar_private *priv)
1019 /* Normaly TSEC should not hang on GRS commands, so we should
1020 * actually wait for IEVENT_GRSC flag.
1022 if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1025 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1026 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1027 * and the Rx can be safely reset.
1029 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1031 if ((res & 0xffff) == (res >> 16))
1037 /* Halt the receive and transmit queues */
1038 static void gfar_halt_nodisable(struct gfar_private *priv)
1040 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1042 unsigned int timeout;
1045 gfar_ints_disable(priv);
1047 if (gfar_is_dma_stopped(priv))
1050 /* Stop the DMA, and wait for it to stop */
1051 tempval = gfar_read(®s->dmactrl);
1052 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1053 gfar_write(®s->dmactrl, tempval);
1057 while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1063 stopped = gfar_is_dma_stopped(priv);
1065 if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1066 !__gfar_is_rx_idle(priv))
1070 /* Halt the receive and transmit queues */
1071 static void gfar_halt(struct gfar_private *priv)
1073 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1076 /* Dissable the Rx/Tx hw queues */
1077 gfar_write(®s->rqueue, 0);
1078 gfar_write(®s->tqueue, 0);
1082 gfar_halt_nodisable(priv);
1084 /* Disable Rx/Tx DMA */
1085 tempval = gfar_read(®s->maccfg1);
1086 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1087 gfar_write(®s->maccfg1, tempval);
1090 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1092 struct txbd8 *txbdp;
1093 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1096 txbdp = tx_queue->tx_bd_base;
1098 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1099 if (!tx_queue->tx_skbuff[i])
1102 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1103 be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
1105 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1108 dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1109 be16_to_cpu(txbdp->length),
1113 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1114 tx_queue->tx_skbuff[i] = NULL;
1116 kfree(tx_queue->tx_skbuff);
1117 tx_queue->tx_skbuff = NULL;
1120 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1124 struct rxbd8 *rxbdp = rx_queue->rx_bd_base;
1126 dev_kfree_skb(rx_queue->skb);
1128 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1129 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[i];
1138 dma_unmap_page(rx_queue->dev, rxb->dma,
1139 PAGE_SIZE, DMA_FROM_DEVICE);
1140 __free_page(rxb->page);
1145 kfree(rx_queue->rx_buff);
1146 rx_queue->rx_buff = NULL;
1149 /* If there are any tx skbs or rx skbs still around, free them.
1150 * Then free tx_skbuff and rx_skbuff
1152 static void free_skb_resources(struct gfar_private *priv)
1154 struct gfar_priv_tx_q *tx_queue = NULL;
1155 struct gfar_priv_rx_q *rx_queue = NULL;
1158 /* Go through all the buffer descriptors and free their data buffers */
1159 for (i = 0; i < priv->num_tx_queues; i++) {
1160 struct netdev_queue *txq;
1162 tx_queue = priv->tx_queue[i];
1163 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1164 if (tx_queue->tx_skbuff)
1165 free_skb_tx_queue(tx_queue);
1166 netdev_tx_reset_queue(txq);
1169 for (i = 0; i < priv->num_rx_queues; i++) {
1170 rx_queue = priv->rx_queue[i];
1171 if (rx_queue->rx_buff)
1172 free_skb_rx_queue(rx_queue);
1175 dma_free_coherent(priv->dev,
1176 sizeof(struct txbd8) * priv->total_tx_ring_size +
1177 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1178 priv->tx_queue[0]->tx_bd_base,
1179 priv->tx_queue[0]->tx_bd_dma_base);
1182 void stop_gfar(struct net_device *dev)
1184 struct gfar_private *priv = netdev_priv(dev);
1186 netif_tx_stop_all_queues(dev);
1188 smp_mb__before_atomic();
1189 set_bit(GFAR_DOWN, &priv->state);
1190 smp_mb__after_atomic();
1194 /* disable ints and gracefully shut down Rx/Tx DMA */
1197 phy_stop(dev->phydev);
1199 free_skb_resources(priv);
1202 static void gfar_start(struct gfar_private *priv)
1204 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1208 /* Enable Rx/Tx hw queues */
1209 gfar_write(®s->rqueue, priv->rqueue);
1210 gfar_write(®s->tqueue, priv->tqueue);
1212 /* Initialize DMACTRL to have WWR and WOP */
1213 tempval = gfar_read(®s->dmactrl);
1214 tempval |= DMACTRL_INIT_SETTINGS;
1215 gfar_write(®s->dmactrl, tempval);
1217 /* Make sure we aren't stopped */
1218 tempval = gfar_read(®s->dmactrl);
1219 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1220 gfar_write(®s->dmactrl, tempval);
1222 for (i = 0; i < priv->num_grps; i++) {
1223 regs = priv->gfargrp[i].regs;
1224 /* Clear THLT/RHLT, so that the DMA starts polling now */
1225 gfar_write(®s->tstat, priv->gfargrp[i].tstat);
1226 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
1229 /* Enable Rx/Tx DMA */
1230 tempval = gfar_read(®s->maccfg1);
1231 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1232 gfar_write(®s->maccfg1, tempval);
1234 gfar_ints_enable(priv);
1236 netif_trans_update(priv->ndev); /* prevent tx timeout */
1239 static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb)
1244 page = dev_alloc_page();
1245 if (unlikely(!page))
1248 addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
1249 if (unlikely(dma_mapping_error(rxq->dev, addr))) {
1257 rxb->page_offset = 0;
1262 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue)
1264 struct gfar_private *priv = netdev_priv(rx_queue->ndev);
1265 struct gfar_extra_stats *estats = &priv->extra_stats;
1267 netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n");
1268 atomic64_inc(&estats->rx_alloc_err);
1271 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
1275 struct gfar_rx_buff *rxb;
1278 i = rx_queue->next_to_use;
1279 bdp = &rx_queue->rx_bd_base[i];
1280 rxb = &rx_queue->rx_buff[i];
1282 while (alloc_cnt--) {
1283 /* try reuse page */
1284 if (unlikely(!rxb->page)) {
1285 if (unlikely(!gfar_new_page(rx_queue, rxb))) {
1286 gfar_rx_alloc_err(rx_queue);
1291 /* Setup the new RxBD */
1292 gfar_init_rxbdp(rx_queue, bdp,
1293 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT);
1295 /* Update to the next pointer */
1299 if (unlikely(++i == rx_queue->rx_ring_size)) {
1301 bdp = rx_queue->rx_bd_base;
1302 rxb = rx_queue->rx_buff;
1306 rx_queue->next_to_use = i;
1307 rx_queue->next_to_alloc = i;
1310 static void gfar_init_bds(struct net_device *ndev)
1312 struct gfar_private *priv = netdev_priv(ndev);
1313 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1314 struct gfar_priv_tx_q *tx_queue = NULL;
1315 struct gfar_priv_rx_q *rx_queue = NULL;
1316 struct txbd8 *txbdp;
1317 u32 __iomem *rfbptr;
1320 for (i = 0; i < priv->num_tx_queues; i++) {
1321 tx_queue = priv->tx_queue[i];
1322 /* Initialize some variables in our dev structure */
1323 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
1324 tx_queue->dirty_tx = tx_queue->tx_bd_base;
1325 tx_queue->cur_tx = tx_queue->tx_bd_base;
1326 tx_queue->skb_curtx = 0;
1327 tx_queue->skb_dirtytx = 0;
1329 /* Initialize Transmit Descriptor Ring */
1330 txbdp = tx_queue->tx_bd_base;
1331 for (j = 0; j < tx_queue->tx_ring_size; j++) {
1337 /* Set the last descriptor in the ring to indicate wrap */
1339 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
1343 rfbptr = ®s->rfbptr0;
1344 for (i = 0; i < priv->num_rx_queues; i++) {
1345 rx_queue = priv->rx_queue[i];
1347 rx_queue->next_to_clean = 0;
1348 rx_queue->next_to_use = 0;
1349 rx_queue->next_to_alloc = 0;
1351 /* make sure next_to_clean != next_to_use after this
1352 * by leaving at least 1 unused descriptor
1354 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue));
1356 rx_queue->rfbptr = rfbptr;
1361 static int gfar_alloc_skb_resources(struct net_device *ndev)
1366 struct gfar_private *priv = netdev_priv(ndev);
1367 struct device *dev = priv->dev;
1368 struct gfar_priv_tx_q *tx_queue = NULL;
1369 struct gfar_priv_rx_q *rx_queue = NULL;
1371 priv->total_tx_ring_size = 0;
1372 for (i = 0; i < priv->num_tx_queues; i++)
1373 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
1375 priv->total_rx_ring_size = 0;
1376 for (i = 0; i < priv->num_rx_queues; i++)
1377 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
1379 /* Allocate memory for the buffer descriptors */
1380 vaddr = dma_alloc_coherent(dev,
1381 (priv->total_tx_ring_size *
1382 sizeof(struct txbd8)) +
1383 (priv->total_rx_ring_size *
1384 sizeof(struct rxbd8)),
1389 for (i = 0; i < priv->num_tx_queues; i++) {
1390 tx_queue = priv->tx_queue[i];
1391 tx_queue->tx_bd_base = vaddr;
1392 tx_queue->tx_bd_dma_base = addr;
1393 tx_queue->dev = ndev;
1394 /* enet DMA only understands physical addresses */
1395 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
1396 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
1399 /* Start the rx descriptor ring where the tx ring leaves off */
1400 for (i = 0; i < priv->num_rx_queues; i++) {
1401 rx_queue = priv->rx_queue[i];
1402 rx_queue->rx_bd_base = vaddr;
1403 rx_queue->rx_bd_dma_base = addr;
1404 rx_queue->ndev = ndev;
1405 rx_queue->dev = dev;
1406 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
1407 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
1410 /* Setup the skbuff rings */
1411 for (i = 0; i < priv->num_tx_queues; i++) {
1412 tx_queue = priv->tx_queue[i];
1413 tx_queue->tx_skbuff =
1414 kmalloc_array(tx_queue->tx_ring_size,
1415 sizeof(*tx_queue->tx_skbuff),
1417 if (!tx_queue->tx_skbuff)
1420 for (j = 0; j < tx_queue->tx_ring_size; j++)
1421 tx_queue->tx_skbuff[j] = NULL;
1424 for (i = 0; i < priv->num_rx_queues; i++) {
1425 rx_queue = priv->rx_queue[i];
1426 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size,
1427 sizeof(*rx_queue->rx_buff),
1429 if (!rx_queue->rx_buff)
1433 gfar_init_bds(ndev);
1438 free_skb_resources(priv);
1442 /* Bring the controller up and running */
1443 int startup_gfar(struct net_device *ndev)
1445 struct gfar_private *priv = netdev_priv(ndev);
1448 gfar_mac_reset(priv);
1450 err = gfar_alloc_skb_resources(ndev);
1454 gfar_init_tx_rx_base(priv);
1456 smp_mb__before_atomic();
1457 clear_bit(GFAR_DOWN, &priv->state);
1458 smp_mb__after_atomic();
1460 /* Start Rx/Tx DMA and enable the interrupts */
1463 /* force link state update after mac reset */
1466 priv->oldduplex = -1;
1468 phy_start(ndev->phydev);
1472 netif_tx_wake_all_queues(ndev);
1477 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
1479 struct net_device *ndev = priv->ndev;
1480 struct phy_device *phydev = ndev->phydev;
1483 if (!phydev->duplex)
1486 if (!priv->pause_aneg_en) {
1487 if (priv->tx_pause_en)
1488 val |= MACCFG1_TX_FLOW;
1489 if (priv->rx_pause_en)
1490 val |= MACCFG1_RX_FLOW;
1492 u16 lcl_adv, rmt_adv;
1494 /* get link partner capabilities */
1497 rmt_adv = LPA_PAUSE_CAP;
1498 if (phydev->asym_pause)
1499 rmt_adv |= LPA_PAUSE_ASYM;
1501 lcl_adv = linkmode_adv_to_lcl_adv_t(phydev->advertising);
1502 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1503 if (flowctrl & FLOW_CTRL_TX)
1504 val |= MACCFG1_TX_FLOW;
1505 if (flowctrl & FLOW_CTRL_RX)
1506 val |= MACCFG1_RX_FLOW;
1512 static noinline void gfar_update_link_state(struct gfar_private *priv)
1514 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1515 struct net_device *ndev = priv->ndev;
1516 struct phy_device *phydev = ndev->phydev;
1517 struct gfar_priv_rx_q *rx_queue = NULL;
1520 if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
1524 u32 tempval1 = gfar_read(®s->maccfg1);
1525 u32 tempval = gfar_read(®s->maccfg2);
1526 u32 ecntrl = gfar_read(®s->ecntrl);
1527 u32 tx_flow_oldval = (tempval1 & MACCFG1_TX_FLOW);
1529 if (phydev->duplex != priv->oldduplex) {
1530 if (!(phydev->duplex))
1531 tempval &= ~(MACCFG2_FULL_DUPLEX);
1533 tempval |= MACCFG2_FULL_DUPLEX;
1535 priv->oldduplex = phydev->duplex;
1538 if (phydev->speed != priv->oldspeed) {
1539 switch (phydev->speed) {
1542 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1544 ecntrl &= ~(ECNTRL_R100);
1549 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1551 /* Reduced mode distinguishes
1552 * between 10 and 100
1554 if (phydev->speed == SPEED_100)
1555 ecntrl |= ECNTRL_R100;
1557 ecntrl &= ~(ECNTRL_R100);
1560 netif_warn(priv, link, priv->ndev,
1561 "Ack! Speed (%d) is not 10/100/1000!\n",
1566 priv->oldspeed = phydev->speed;
1569 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1570 tempval1 |= gfar_get_flowctrl_cfg(priv);
1572 /* Turn last free buffer recording on */
1573 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
1574 for (i = 0; i < priv->num_rx_queues; i++) {
1577 rx_queue = priv->rx_queue[i];
1578 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
1579 gfar_write(rx_queue->rfbptr, bdp_dma);
1582 priv->tx_actual_en = 1;
1585 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
1586 priv->tx_actual_en = 0;
1588 gfar_write(®s->maccfg1, tempval1);
1589 gfar_write(®s->maccfg2, tempval);
1590 gfar_write(®s->ecntrl, ecntrl);
1595 } else if (priv->oldlink) {
1598 priv->oldduplex = -1;
1601 if (netif_msg_link(priv))
1602 phy_print_status(phydev);
1605 /* Called every time the controller might need to be made
1606 * aware of new link state. The PHY code conveys this
1607 * information through variables in the phydev structure, and this
1608 * function converts those variables into the appropriate
1609 * register values, and can bring down the device if needed.
1611 static void adjust_link(struct net_device *dev)
1613 struct gfar_private *priv = netdev_priv(dev);
1614 struct phy_device *phydev = dev->phydev;
1616 if (unlikely(phydev->link != priv->oldlink ||
1617 (phydev->link && (phydev->duplex != priv->oldduplex ||
1618 phydev->speed != priv->oldspeed))))
1619 gfar_update_link_state(priv);
1622 /* Initialize TBI PHY interface for communicating with the
1623 * SERDES lynx PHY on the chip. We communicate with this PHY
1624 * through the MDIO bus on each controller, treating it as a
1625 * "normal" PHY at the address found in the TBIPA register. We assume
1626 * that the TBIPA register is valid. Either the MDIO bus code will set
1627 * it to a value that doesn't conflict with other PHYs on the bus, or the
1628 * value doesn't matter, as there are no other PHYs on the bus.
1630 static void gfar_configure_serdes(struct net_device *dev)
1632 struct gfar_private *priv = netdev_priv(dev);
1633 struct phy_device *tbiphy;
1635 if (!priv->tbi_node) {
1636 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1637 "device tree specify a tbi-handle\n");
1641 tbiphy = of_phy_find_device(priv->tbi_node);
1643 dev_err(&dev->dev, "error: Could not get TBI device\n");
1647 /* If the link is already up, we must already be ok, and don't need to
1648 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1649 * everything for us? Resetting it takes the link down and requires
1650 * several seconds for it to come back.
1652 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) {
1653 put_device(&tbiphy->mdio.dev);
1657 /* Single clk mode, mii mode off(for serdes communication) */
1658 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1660 phy_write(tbiphy, MII_ADVERTISE,
1661 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1662 ADVERTISE_1000XPSE_ASYM);
1664 phy_write(tbiphy, MII_BMCR,
1665 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1668 put_device(&tbiphy->mdio.dev);
1671 /* Initializes driver's PHY state, and attaches to the PHY.
1672 * Returns 0 on success.
1674 static int init_phy(struct net_device *dev)
1676 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1677 struct gfar_private *priv = netdev_priv(dev);
1678 phy_interface_t interface = priv->interface;
1679 struct phy_device *phydev;
1680 struct ethtool_eee edata;
1682 linkmode_set_bit_array(phy_10_100_features_array,
1683 ARRAY_SIZE(phy_10_100_features_array),
1685 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mask);
1686 linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, mask);
1687 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1688 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mask);
1692 priv->oldduplex = -1;
1694 phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1697 dev_err(&dev->dev, "could not attach to PHY\n");
1701 if (interface == PHY_INTERFACE_MODE_SGMII)
1702 gfar_configure_serdes(dev);
1704 /* Remove any features not supported by the controller */
1705 linkmode_and(phydev->supported, phydev->supported, mask);
1706 linkmode_copy(phydev->advertising, phydev->supported);
1708 /* Add support for flow control */
1709 phy_support_asym_pause(phydev);
1711 /* disable EEE autoneg, EEE not supported by eTSEC */
1712 memset(&edata, 0, sizeof(struct ethtool_eee));
1713 phy_ethtool_set_eee(phydev, &edata);
1718 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1720 struct txfcb *fcb = skb_push(skb, GMAC_FCB_LEN);
1722 memset(fcb, 0, GMAC_FCB_LEN);
1727 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
1730 /* If we're here, it's a IP packet with a TCP or UDP
1731 * payload. We set it to checksum, using a pseudo-header
1734 u8 flags = TXFCB_DEFAULT;
1736 /* Tell the controller what the protocol is
1737 * And provide the already calculated phcs
1739 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1741 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
1743 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
1745 /* l3os is the distance between the start of the
1746 * frame (skb->data) and the start of the IP hdr.
1747 * l4os is the distance between the start of the
1748 * l3 hdr and the l4 hdr
1750 fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
1751 fcb->l4os = skb_network_header_len(skb);
1756 static inline void gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1758 fcb->flags |= TXFCB_VLN;
1759 fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
1762 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1763 struct txbd8 *base, int ring_size)
1765 struct txbd8 *new_bd = bdp + stride;
1767 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1770 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1773 return skip_txbd(bdp, 1, base, ring_size);
1776 /* eTSEC12: csum generation not supported for some fcb offsets */
1777 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
1778 unsigned long fcb_addr)
1780 return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
1781 (fcb_addr % 0x20) > 0x18);
1784 /* eTSEC76: csum generation for frames larger than 2500 may
1785 * cause excess delays before start of transmission
1787 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
1790 return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
1794 /* This is called by the kernel when a frame is ready for transmission.
1795 * It is pointed to by the dev->hard_start_xmit function pointer
1797 static netdev_tx_t gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1799 struct gfar_private *priv = netdev_priv(dev);
1800 struct gfar_priv_tx_q *tx_queue = NULL;
1801 struct netdev_queue *txq;
1802 struct gfar __iomem *regs = NULL;
1803 struct txfcb *fcb = NULL;
1804 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
1808 int do_tstamp, do_csum, do_vlan;
1810 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
1812 rq = skb->queue_mapping;
1813 tx_queue = priv->tx_queue[rq];
1814 txq = netdev_get_tx_queue(dev, rq);
1815 base = tx_queue->tx_bd_base;
1816 regs = tx_queue->grp->regs;
1818 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
1819 do_vlan = skb_vlan_tag_present(skb);
1820 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1823 if (do_csum || do_vlan)
1824 fcb_len = GMAC_FCB_LEN;
1826 /* check if time stamp should be generated */
1827 if (unlikely(do_tstamp))
1828 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
1830 /* make space for additional header when fcb is needed */
1832 if (unlikely(skb_cow_head(skb, fcb_len))) {
1833 dev->stats.tx_errors++;
1834 dev_kfree_skb_any(skb);
1835 return NETDEV_TX_OK;
1839 /* total number of fragments in the SKB */
1840 nr_frags = skb_shinfo(skb)->nr_frags;
1842 /* calculate the required number of TxBDs for this skb */
1843 if (unlikely(do_tstamp))
1844 nr_txbds = nr_frags + 2;
1846 nr_txbds = nr_frags + 1;
1848 /* check if there is space to queue this packet */
1849 if (nr_txbds > tx_queue->num_txbdfree) {
1850 /* no space, stop the queue */
1851 netif_tx_stop_queue(txq);
1852 dev->stats.tx_fifo_errors++;
1853 return NETDEV_TX_BUSY;
1856 /* Update transmit stats */
1857 bytes_sent = skb->len;
1858 tx_queue->stats.tx_bytes += bytes_sent;
1859 /* keep Tx bytes on wire for BQL accounting */
1860 GFAR_CB(skb)->bytes_sent = bytes_sent;
1861 tx_queue->stats.tx_packets++;
1863 txbdp = txbdp_start = tx_queue->cur_tx;
1864 lstatus = be32_to_cpu(txbdp->lstatus);
1866 /* Add TxPAL between FCB and frame if required */
1867 if (unlikely(do_tstamp)) {
1868 skb_push(skb, GMAC_TXPAL_LEN);
1869 memset(skb->data, 0, GMAC_TXPAL_LEN);
1872 /* Add TxFCB if required */
1874 fcb = gfar_add_fcb(skb);
1875 lstatus |= BD_LFLAG(TXBD_TOE);
1878 /* Set up checksumming */
1880 gfar_tx_checksum(skb, fcb, fcb_len);
1882 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
1883 unlikely(gfar_csum_errata_76(priv, skb->len))) {
1884 __skb_pull(skb, GMAC_FCB_LEN);
1885 skb_checksum_help(skb);
1886 if (do_vlan || do_tstamp) {
1887 /* put back a new fcb for vlan/tstamp TOE */
1888 fcb = gfar_add_fcb(skb);
1890 /* Tx TOE not used */
1891 lstatus &= ~(BD_LFLAG(TXBD_TOE));
1898 gfar_tx_vlan(skb, fcb);
1900 bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
1902 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
1905 txbdp_start->bufPtr = cpu_to_be32(bufaddr);
1907 /* Time stamp insertion requires one additional TxBD */
1908 if (unlikely(do_tstamp))
1909 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
1910 tx_queue->tx_ring_size);
1912 if (likely(!nr_frags)) {
1913 if (likely(!do_tstamp))
1914 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1916 u32 lstatus_start = lstatus;
1918 /* Place the fragment addresses and lengths into the TxBDs */
1919 frag = &skb_shinfo(skb)->frags[0];
1920 for (i = 0; i < nr_frags; i++, frag++) {
1923 /* Point at the next BD, wrapping as needed */
1924 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
1926 size = skb_frag_size(frag);
1928 lstatus = be32_to_cpu(txbdp->lstatus) | size |
1929 BD_LFLAG(TXBD_READY);
1931 /* Handle the last BD specially */
1932 if (i == nr_frags - 1)
1933 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1935 bufaddr = skb_frag_dma_map(priv->dev, frag, 0,
1936 size, DMA_TO_DEVICE);
1937 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
1940 /* set the TxBD length and buffer pointer */
1941 txbdp->bufPtr = cpu_to_be32(bufaddr);
1942 txbdp->lstatus = cpu_to_be32(lstatus);
1945 lstatus = lstatus_start;
1948 /* If time stamping is requested one additional TxBD must be set up. The
1949 * first TxBD points to the FCB and must have a data length of
1950 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
1951 * the full frame length.
1953 if (unlikely(do_tstamp)) {
1954 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
1956 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
1959 lstatus_ts |= BD_LFLAG(TXBD_READY) |
1960 (skb_headlen(skb) - fcb_len);
1962 lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1964 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
1965 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
1966 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
1968 /* Setup tx hardware time stamping */
1969 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1972 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1975 netdev_tx_sent_queue(txq, bytes_sent);
1979 txbdp_start->lstatus = cpu_to_be32(lstatus);
1981 gfar_wmb(); /* force lstatus write before tx_skbuff */
1983 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
1985 /* Update the current skb pointer to the next entry we will use
1986 * (wrapping if necessary)
1988 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
1989 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
1991 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
1993 /* We can work in parallel with gfar_clean_tx_ring(), except
1994 * when modifying num_txbdfree. Note that we didn't grab the lock
1995 * when we were reading the num_txbdfree and checking for available
1996 * space, that's because outside of this function it can only grow.
1998 spin_lock_bh(&tx_queue->txlock);
1999 /* reduce TxBD free count */
2000 tx_queue->num_txbdfree -= (nr_txbds);
2001 spin_unlock_bh(&tx_queue->txlock);
2003 /* If the next BD still needs to be cleaned up, then the bds
2004 * are full. We need to tell the kernel to stop sending us stuff.
2006 if (!tx_queue->num_txbdfree) {
2007 netif_tx_stop_queue(txq);
2009 dev->stats.tx_fifo_errors++;
2012 /* Tell the DMA to go go go */
2013 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2015 return NETDEV_TX_OK;
2018 txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2020 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2021 for (i = 0; i < nr_frags; i++) {
2022 lstatus = be32_to_cpu(txbdp->lstatus);
2023 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2026 lstatus &= ~BD_LFLAG(TXBD_READY);
2027 txbdp->lstatus = cpu_to_be32(lstatus);
2028 bufaddr = be32_to_cpu(txbdp->bufPtr);
2029 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
2031 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2034 dev_kfree_skb_any(skb);
2035 return NETDEV_TX_OK;
2038 /* Changes the mac address if the controller is not running. */
2039 static int gfar_set_mac_address(struct net_device *dev)
2041 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2046 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2048 struct gfar_private *priv = netdev_priv(dev);
2050 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2053 if (dev->flags & IFF_UP)
2058 if (dev->flags & IFF_UP)
2061 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2066 static void reset_gfar(struct net_device *ndev)
2068 struct gfar_private *priv = netdev_priv(ndev);
2070 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2076 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2079 /* gfar_reset_task gets scheduled when a packet has not been
2080 * transmitted after a set amount of time.
2081 * For now, assume that clearing out all the structures, and
2082 * starting over will fix the problem.
2084 static void gfar_reset_task(struct work_struct *work)
2086 struct gfar_private *priv = container_of(work, struct gfar_private,
2088 reset_gfar(priv->ndev);
2091 static void gfar_timeout(struct net_device *dev, unsigned int txqueue)
2093 struct gfar_private *priv = netdev_priv(dev);
2095 dev->stats.tx_errors++;
2096 schedule_work(&priv->reset_task);
2099 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
2101 struct hwtstamp_config config;
2102 struct gfar_private *priv = netdev_priv(netdev);
2104 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2107 /* reserved for future extensions */
2111 switch (config.tx_type) {
2112 case HWTSTAMP_TX_OFF:
2113 priv->hwts_tx_en = 0;
2115 case HWTSTAMP_TX_ON:
2116 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
2118 priv->hwts_tx_en = 1;
2124 switch (config.rx_filter) {
2125 case HWTSTAMP_FILTER_NONE:
2126 if (priv->hwts_rx_en) {
2127 priv->hwts_rx_en = 0;
2132 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
2134 if (!priv->hwts_rx_en) {
2135 priv->hwts_rx_en = 1;
2138 config.rx_filter = HWTSTAMP_FILTER_ALL;
2142 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
2146 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
2148 struct hwtstamp_config config;
2149 struct gfar_private *priv = netdev_priv(netdev);
2152 config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
2153 config.rx_filter = (priv->hwts_rx_en ?
2154 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
2156 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
2160 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2162 struct phy_device *phydev = dev->phydev;
2164 if (!netif_running(dev))
2167 if (cmd == SIOCSHWTSTAMP)
2168 return gfar_hwtstamp_set(dev, rq);
2169 if (cmd == SIOCGHWTSTAMP)
2170 return gfar_hwtstamp_get(dev, rq);
2175 return phy_mii_ioctl(phydev, rq, cmd);
2178 /* Interrupt Handler for Transmit complete */
2179 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2181 struct net_device *dev = tx_queue->dev;
2182 struct netdev_queue *txq;
2183 struct gfar_private *priv = netdev_priv(dev);
2184 struct txbd8 *bdp, *next = NULL;
2185 struct txbd8 *lbdp = NULL;
2186 struct txbd8 *base = tx_queue->tx_bd_base;
2187 struct sk_buff *skb;
2189 int tx_ring_size = tx_queue->tx_ring_size;
2190 int frags = 0, nr_txbds = 0;
2193 int tqi = tx_queue->qindex;
2194 unsigned int bytes_sent = 0;
2198 txq = netdev_get_tx_queue(dev, tqi);
2199 bdp = tx_queue->dirty_tx;
2200 skb_dirtytx = tx_queue->skb_dirtytx;
2202 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2205 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2208 frags = skb_shinfo(skb)->nr_frags;
2210 /* When time stamping, one additional TxBD must be freed.
2211 * Also, we need to dma_unmap_single() the TxPAL.
2213 if (unlikely(do_tstamp))
2214 nr_txbds = frags + 2;
2216 nr_txbds = frags + 1;
2218 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2220 lstatus = be32_to_cpu(lbdp->lstatus);
2222 /* Only clean completed frames */
2223 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2224 (lstatus & BD_LENGTH_MASK))
2227 if (unlikely(do_tstamp)) {
2228 next = next_txbd(bdp, base, tx_ring_size);
2229 buflen = be16_to_cpu(next->length) +
2230 GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2232 buflen = be16_to_cpu(bdp->length);
2234 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2235 buflen, DMA_TO_DEVICE);
2237 if (unlikely(do_tstamp)) {
2238 struct skb_shared_hwtstamps shhwtstamps;
2239 u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) &
2242 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2243 shhwtstamps.hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
2244 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2245 skb_tstamp_tx(skb, &shhwtstamps);
2246 gfar_clear_txbd_status(bdp);
2250 gfar_clear_txbd_status(bdp);
2251 bdp = next_txbd(bdp, base, tx_ring_size);
2253 for (i = 0; i < frags; i++) {
2254 dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2255 be16_to_cpu(bdp->length),
2257 gfar_clear_txbd_status(bdp);
2258 bdp = next_txbd(bdp, base, tx_ring_size);
2261 bytes_sent += GFAR_CB(skb)->bytes_sent;
2263 dev_kfree_skb_any(skb);
2265 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2267 skb_dirtytx = (skb_dirtytx + 1) &
2268 TX_RING_MOD_MASK(tx_ring_size);
2271 spin_lock(&tx_queue->txlock);
2272 tx_queue->num_txbdfree += nr_txbds;
2273 spin_unlock(&tx_queue->txlock);
2276 /* If we freed a buffer, we can restart transmission, if necessary */
2277 if (tx_queue->num_txbdfree &&
2278 netif_tx_queue_stopped(txq) &&
2279 !(test_bit(GFAR_DOWN, &priv->state)))
2280 netif_wake_subqueue(priv->ndev, tqi);
2282 /* Update dirty indicators */
2283 tx_queue->skb_dirtytx = skb_dirtytx;
2284 tx_queue->dirty_tx = bdp;
2286 netdev_tx_completed_queue(txq, howmany, bytes_sent);
2289 static void count_errors(u32 lstatus, struct net_device *ndev)
2291 struct gfar_private *priv = netdev_priv(ndev);
2292 struct net_device_stats *stats = &ndev->stats;
2293 struct gfar_extra_stats *estats = &priv->extra_stats;
2295 /* If the packet was truncated, none of the other errors matter */
2296 if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) {
2297 stats->rx_length_errors++;
2299 atomic64_inc(&estats->rx_trunc);
2303 /* Count the errors, if there were any */
2304 if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) {
2305 stats->rx_length_errors++;
2307 if (lstatus & BD_LFLAG(RXBD_LARGE))
2308 atomic64_inc(&estats->rx_large);
2310 atomic64_inc(&estats->rx_short);
2312 if (lstatus & BD_LFLAG(RXBD_NONOCTET)) {
2313 stats->rx_frame_errors++;
2314 atomic64_inc(&estats->rx_nonoctet);
2316 if (lstatus & BD_LFLAG(RXBD_CRCERR)) {
2317 atomic64_inc(&estats->rx_crcerr);
2318 stats->rx_crc_errors++;
2320 if (lstatus & BD_LFLAG(RXBD_OVERRUN)) {
2321 atomic64_inc(&estats->rx_overrun);
2322 stats->rx_over_errors++;
2326 static irqreturn_t gfar_receive(int irq, void *grp_id)
2328 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2329 unsigned long flags;
2332 ievent = gfar_read(&grp->regs->ievent);
2334 if (unlikely(ievent & IEVENT_FGPI)) {
2335 gfar_write(&grp->regs->ievent, IEVENT_FGPI);
2339 if (likely(napi_schedule_prep(&grp->napi_rx))) {
2340 spin_lock_irqsave(&grp->grplock, flags);
2341 imask = gfar_read(&grp->regs->imask);
2342 imask &= IMASK_RX_DISABLED;
2343 gfar_write(&grp->regs->imask, imask);
2344 spin_unlock_irqrestore(&grp->grplock, flags);
2345 __napi_schedule(&grp->napi_rx);
2347 /* Clear IEVENT, so interrupts aren't called again
2348 * because of the packets that have already arrived.
2350 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2356 /* Interrupt Handler for Transmit complete */
2357 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2359 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2360 unsigned long flags;
2363 if (likely(napi_schedule_prep(&grp->napi_tx))) {
2364 spin_lock_irqsave(&grp->grplock, flags);
2365 imask = gfar_read(&grp->regs->imask);
2366 imask &= IMASK_TX_DISABLED;
2367 gfar_write(&grp->regs->imask, imask);
2368 spin_unlock_irqrestore(&grp->grplock, flags);
2369 __napi_schedule(&grp->napi_tx);
2371 /* Clear IEVENT, so interrupts aren't called again
2372 * because of the packets that have already arrived.
2374 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2380 static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus,
2381 struct sk_buff *skb, bool first)
2383 int size = lstatus & BD_LENGTH_MASK;
2384 struct page *page = rxb->page;
2386 if (likely(first)) {
2389 /* the last fragments' length contains the full frame length */
2390 if (lstatus & BD_LFLAG(RXBD_LAST))
2393 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
2394 rxb->page_offset + RXBUF_ALIGNMENT,
2395 size, GFAR_RXB_TRUESIZE);
2398 /* try reuse page */
2399 if (unlikely(page_count(page) != 1 || page_is_pfmemalloc(page)))
2402 /* change offset to the other half */
2403 rxb->page_offset ^= GFAR_RXB_TRUESIZE;
2410 static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq,
2411 struct gfar_rx_buff *old_rxb)
2413 struct gfar_rx_buff *new_rxb;
2414 u16 nta = rxq->next_to_alloc;
2416 new_rxb = &rxq->rx_buff[nta];
2418 /* find next buf that can reuse a page */
2420 rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0;
2422 /* copy page reference */
2423 *new_rxb = *old_rxb;
2425 /* sync for use by the device */
2426 dma_sync_single_range_for_device(rxq->dev, old_rxb->dma,
2427 old_rxb->page_offset,
2428 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2431 static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue,
2432 u32 lstatus, struct sk_buff *skb)
2434 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean];
2435 struct page *page = rxb->page;
2439 void *buff_addr = page_address(page) + rxb->page_offset;
2441 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE);
2442 if (unlikely(!skb)) {
2443 gfar_rx_alloc_err(rx_queue);
2446 skb_reserve(skb, RXBUF_ALIGNMENT);
2450 dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset,
2451 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2453 if (gfar_add_rx_frag(rxb, lstatus, skb, first)) {
2454 /* reuse the free half of the page */
2455 gfar_reuse_rx_page(rx_queue, rxb);
2457 /* page cannot be reused, unmap it */
2458 dma_unmap_page(rx_queue->dev, rxb->dma,
2459 PAGE_SIZE, DMA_FROM_DEVICE);
2462 /* clear rxb content */
2468 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2470 /* If valid headers were found, and valid sums
2471 * were verified, then we tell the kernel that no
2472 * checksumming is necessary. Otherwise, it is [FIXME]
2474 if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
2475 (RXFCB_CIP | RXFCB_CTU))
2476 skb->ip_summed = CHECKSUM_UNNECESSARY;
2478 skb_checksum_none_assert(skb);
2481 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2482 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb)
2484 struct gfar_private *priv = netdev_priv(ndev);
2485 struct rxfcb *fcb = NULL;
2487 /* fcb is at the beginning if exists */
2488 fcb = (struct rxfcb *)skb->data;
2490 /* Remove the FCB from the skb
2491 * Remove the padded bytes, if there are any
2493 if (priv->uses_rxfcb)
2494 skb_pull(skb, GMAC_FCB_LEN);
2496 /* Get receive timestamp from the skb */
2497 if (priv->hwts_rx_en) {
2498 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2499 u64 *ns = (u64 *) skb->data;
2501 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2502 shhwtstamps->hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
2506 skb_pull(skb, priv->padding);
2508 /* Trim off the FCS */
2509 pskb_trim(skb, skb->len - ETH_FCS_LEN);
2511 if (ndev->features & NETIF_F_RXCSUM)
2512 gfar_rx_checksum(skb, fcb);
2514 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
2515 * Even if vlan rx accel is disabled, on some chips
2516 * RXFCB_VLN is pseudo randomly set.
2518 if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2519 be16_to_cpu(fcb->flags) & RXFCB_VLN)
2520 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2521 be16_to_cpu(fcb->vlctl));
2524 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2525 * until the budget/quota has been reached. Returns the number
2528 static int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue,
2531 struct net_device *ndev = rx_queue->ndev;
2532 struct gfar_private *priv = netdev_priv(ndev);
2535 struct sk_buff *skb = rx_queue->skb;
2536 int cleaned_cnt = gfar_rxbd_unused(rx_queue);
2537 unsigned int total_bytes = 0, total_pkts = 0;
2539 /* Get the first full descriptor */
2540 i = rx_queue->next_to_clean;
2542 while (rx_work_limit--) {
2545 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) {
2546 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
2550 bdp = &rx_queue->rx_bd_base[i];
2551 lstatus = be32_to_cpu(bdp->lstatus);
2552 if (lstatus & BD_LFLAG(RXBD_EMPTY))
2555 /* order rx buffer descriptor reads */
2558 /* fetch next to clean buffer from the ring */
2559 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb);
2566 if (unlikely(++i == rx_queue->rx_ring_size))
2569 rx_queue->next_to_clean = i;
2571 /* fetch next buffer if not the last in frame */
2572 if (!(lstatus & BD_LFLAG(RXBD_LAST)))
2575 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) {
2576 count_errors(lstatus, ndev);
2578 /* discard faulty buffer */
2581 rx_queue->stats.rx_dropped++;
2585 gfar_process_frame(ndev, skb);
2587 /* Increment the number of packets */
2589 total_bytes += skb->len;
2591 skb_record_rx_queue(skb, rx_queue->qindex);
2593 skb->protocol = eth_type_trans(skb, ndev);
2595 /* Send the packet up the stack */
2596 napi_gro_receive(&rx_queue->grp->napi_rx, skb);
2601 /* Store incomplete frames for completion */
2602 rx_queue->skb = skb;
2604 rx_queue->stats.rx_packets += total_pkts;
2605 rx_queue->stats.rx_bytes += total_bytes;
2608 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
2610 /* Update Last Free RxBD pointer for LFC */
2611 if (unlikely(priv->tx_actual_en)) {
2612 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
2614 gfar_write(rx_queue->rfbptr, bdp_dma);
2620 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
2622 struct gfar_priv_grp *gfargrp =
2623 container_of(napi, struct gfar_priv_grp, napi_rx);
2624 struct gfar __iomem *regs = gfargrp->regs;
2625 struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
2628 /* Clear IEVENT, so interrupts aren't called again
2629 * because of the packets that have already arrived
2631 gfar_write(®s->ievent, IEVENT_RX_MASK);
2633 work_done = gfar_clean_rx_ring(rx_queue, budget);
2635 if (work_done < budget) {
2637 napi_complete_done(napi, work_done);
2638 /* Clear the halt bit in RSTAT */
2639 gfar_write(®s->rstat, gfargrp->rstat);
2641 spin_lock_irq(&gfargrp->grplock);
2642 imask = gfar_read(®s->imask);
2643 imask |= IMASK_RX_DEFAULT;
2644 gfar_write(®s->imask, imask);
2645 spin_unlock_irq(&gfargrp->grplock);
2651 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
2653 struct gfar_priv_grp *gfargrp =
2654 container_of(napi, struct gfar_priv_grp, napi_tx);
2655 struct gfar __iomem *regs = gfargrp->regs;
2656 struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
2659 /* Clear IEVENT, so interrupts aren't called again
2660 * because of the packets that have already arrived
2662 gfar_write(®s->ievent, IEVENT_TX_MASK);
2664 /* run Tx cleanup to completion */
2665 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
2666 gfar_clean_tx_ring(tx_queue);
2668 napi_complete(napi);
2670 spin_lock_irq(&gfargrp->grplock);
2671 imask = gfar_read(®s->imask);
2672 imask |= IMASK_TX_DEFAULT;
2673 gfar_write(®s->imask, imask);
2674 spin_unlock_irq(&gfargrp->grplock);
2679 static int gfar_poll_rx(struct napi_struct *napi, int budget)
2681 struct gfar_priv_grp *gfargrp =
2682 container_of(napi, struct gfar_priv_grp, napi_rx);
2683 struct gfar_private *priv = gfargrp->priv;
2684 struct gfar __iomem *regs = gfargrp->regs;
2685 struct gfar_priv_rx_q *rx_queue = NULL;
2686 int work_done = 0, work_done_per_q = 0;
2687 int i, budget_per_q = 0;
2688 unsigned long rstat_rxf;
2691 /* Clear IEVENT, so interrupts aren't called again
2692 * because of the packets that have already arrived
2694 gfar_write(®s->ievent, IEVENT_RX_MASK);
2696 rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK;
2698 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
2700 budget_per_q = budget/num_act_queues;
2702 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2703 /* skip queue if not active */
2704 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
2707 rx_queue = priv->rx_queue[i];
2709 gfar_clean_rx_ring(rx_queue, budget_per_q);
2710 work_done += work_done_per_q;
2712 /* finished processing this queue */
2713 if (work_done_per_q < budget_per_q) {
2714 /* clear active queue hw indication */
2715 gfar_write(®s->rstat,
2716 RSTAT_CLEAR_RXF0 >> i);
2719 if (!num_act_queues)
2724 if (!num_act_queues) {
2726 napi_complete_done(napi, work_done);
2728 /* Clear the halt bit in RSTAT */
2729 gfar_write(®s->rstat, gfargrp->rstat);
2731 spin_lock_irq(&gfargrp->grplock);
2732 imask = gfar_read(®s->imask);
2733 imask |= IMASK_RX_DEFAULT;
2734 gfar_write(®s->imask, imask);
2735 spin_unlock_irq(&gfargrp->grplock);
2741 static int gfar_poll_tx(struct napi_struct *napi, int budget)
2743 struct gfar_priv_grp *gfargrp =
2744 container_of(napi, struct gfar_priv_grp, napi_tx);
2745 struct gfar_private *priv = gfargrp->priv;
2746 struct gfar __iomem *regs = gfargrp->regs;
2747 struct gfar_priv_tx_q *tx_queue = NULL;
2748 int has_tx_work = 0;
2751 /* Clear IEVENT, so interrupts aren't called again
2752 * because of the packets that have already arrived
2754 gfar_write(®s->ievent, IEVENT_TX_MASK);
2756 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
2757 tx_queue = priv->tx_queue[i];
2758 /* run Tx cleanup to completion */
2759 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
2760 gfar_clean_tx_ring(tx_queue);
2767 napi_complete(napi);
2769 spin_lock_irq(&gfargrp->grplock);
2770 imask = gfar_read(®s->imask);
2771 imask |= IMASK_TX_DEFAULT;
2772 gfar_write(®s->imask, imask);
2773 spin_unlock_irq(&gfargrp->grplock);
2779 /* GFAR error interrupt handler */
2780 static irqreturn_t gfar_error(int irq, void *grp_id)
2782 struct gfar_priv_grp *gfargrp = grp_id;
2783 struct gfar __iomem *regs = gfargrp->regs;
2784 struct gfar_private *priv= gfargrp->priv;
2785 struct net_device *dev = priv->ndev;
2787 /* Save ievent for future reference */
2788 u32 events = gfar_read(®s->ievent);
2791 gfar_write(®s->ievent, events & IEVENT_ERR_MASK);
2793 /* Magic Packet is not an error. */
2794 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2795 (events & IEVENT_MAG))
2796 events &= ~IEVENT_MAG;
2799 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2801 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
2802 events, gfar_read(®s->imask));
2804 /* Update the error counters */
2805 if (events & IEVENT_TXE) {
2806 dev->stats.tx_errors++;
2808 if (events & IEVENT_LC)
2809 dev->stats.tx_window_errors++;
2810 if (events & IEVENT_CRL)
2811 dev->stats.tx_aborted_errors++;
2812 if (events & IEVENT_XFUN) {
2813 netif_dbg(priv, tx_err, dev,
2814 "TX FIFO underrun, packet dropped\n");
2815 dev->stats.tx_dropped++;
2816 atomic64_inc(&priv->extra_stats.tx_underrun);
2818 schedule_work(&priv->reset_task);
2820 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
2822 if (events & IEVENT_BSY) {
2823 dev->stats.rx_over_errors++;
2824 atomic64_inc(&priv->extra_stats.rx_bsy);
2826 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
2827 gfar_read(®s->rstat));
2829 if (events & IEVENT_BABR) {
2830 dev->stats.rx_errors++;
2831 atomic64_inc(&priv->extra_stats.rx_babr);
2833 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
2835 if (events & IEVENT_EBERR) {
2836 atomic64_inc(&priv->extra_stats.eberr);
2837 netif_dbg(priv, rx_err, dev, "bus error\n");
2839 if (events & IEVENT_RXC)
2840 netif_dbg(priv, rx_status, dev, "control frame\n");
2842 if (events & IEVENT_BABT) {
2843 atomic64_inc(&priv->extra_stats.tx_babt);
2844 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
2849 /* The interrupt handler for devices with one interrupt */
2850 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2852 struct gfar_priv_grp *gfargrp = grp_id;
2854 /* Save ievent for future reference */
2855 u32 events = gfar_read(&gfargrp->regs->ievent);
2857 /* Check for reception */
2858 if (events & IEVENT_RX_MASK)
2859 gfar_receive(irq, grp_id);
2861 /* Check for transmit completion */
2862 if (events & IEVENT_TX_MASK)
2863 gfar_transmit(irq, grp_id);
2865 /* Check for errors */
2866 if (events & IEVENT_ERR_MASK)
2867 gfar_error(irq, grp_id);
2872 #ifdef CONFIG_NET_POLL_CONTROLLER
2873 /* Polling 'interrupt' - used by things like netconsole to send skbs
2874 * without having to re-enable interrupts. It's not called while
2875 * the interrupt routine is executing.
2877 static void gfar_netpoll(struct net_device *dev)
2879 struct gfar_private *priv = netdev_priv(dev);
2882 /* If the device has multiple interrupts, run tx/rx */
2883 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2884 for (i = 0; i < priv->num_grps; i++) {
2885 struct gfar_priv_grp *grp = &priv->gfargrp[i];
2887 disable_irq(gfar_irq(grp, TX)->irq);
2888 disable_irq(gfar_irq(grp, RX)->irq);
2889 disable_irq(gfar_irq(grp, ER)->irq);
2890 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2891 enable_irq(gfar_irq(grp, ER)->irq);
2892 enable_irq(gfar_irq(grp, RX)->irq);
2893 enable_irq(gfar_irq(grp, TX)->irq);
2896 for (i = 0; i < priv->num_grps; i++) {
2897 struct gfar_priv_grp *grp = &priv->gfargrp[i];
2899 disable_irq(gfar_irq(grp, TX)->irq);
2900 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2901 enable_irq(gfar_irq(grp, TX)->irq);
2907 static void free_grp_irqs(struct gfar_priv_grp *grp)
2909 free_irq(gfar_irq(grp, TX)->irq, grp);
2910 free_irq(gfar_irq(grp, RX)->irq, grp);
2911 free_irq(gfar_irq(grp, ER)->irq, grp);
2914 static int register_grp_irqs(struct gfar_priv_grp *grp)
2916 struct gfar_private *priv = grp->priv;
2917 struct net_device *dev = priv->ndev;
2920 /* If the device has multiple interrupts, register for
2921 * them. Otherwise, only register for the one
2923 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2924 /* Install our interrupt handlers for Error,
2925 * Transmit, and Receive
2927 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2928 gfar_irq(grp, ER)->name, grp);
2930 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2931 gfar_irq(grp, ER)->irq);
2935 enable_irq_wake(gfar_irq(grp, ER)->irq);
2937 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2938 gfar_irq(grp, TX)->name, grp);
2940 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2941 gfar_irq(grp, TX)->irq);
2944 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2945 gfar_irq(grp, RX)->name, grp);
2947 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2948 gfar_irq(grp, RX)->irq);
2951 enable_irq_wake(gfar_irq(grp, RX)->irq);
2954 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2955 gfar_irq(grp, TX)->name, grp);
2957 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2958 gfar_irq(grp, TX)->irq);
2961 enable_irq_wake(gfar_irq(grp, TX)->irq);
2967 free_irq(gfar_irq(grp, TX)->irq, grp);
2969 free_irq(gfar_irq(grp, ER)->irq, grp);
2975 static void gfar_free_irq(struct gfar_private *priv)
2980 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2981 for (i = 0; i < priv->num_grps; i++)
2982 free_grp_irqs(&priv->gfargrp[i]);
2984 for (i = 0; i < priv->num_grps; i++)
2985 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2990 static int gfar_request_irq(struct gfar_private *priv)
2994 for (i = 0; i < priv->num_grps; i++) {
2995 err = register_grp_irqs(&priv->gfargrp[i]);
2997 for (j = 0; j < i; j++)
2998 free_grp_irqs(&priv->gfargrp[j]);
3006 /* Called when something needs to use the ethernet device
3007 * Returns 0 for success.
3009 static int gfar_enet_open(struct net_device *dev)
3011 struct gfar_private *priv = netdev_priv(dev);
3014 err = init_phy(dev);
3018 err = gfar_request_irq(priv);
3022 err = startup_gfar(dev);
3029 /* Stops the kernel queue, and halts the controller */
3030 static int gfar_close(struct net_device *dev)
3032 struct gfar_private *priv = netdev_priv(dev);
3034 cancel_work_sync(&priv->reset_task);
3037 /* Disconnect from the PHY */
3038 phy_disconnect(dev->phydev);
3040 gfar_free_irq(priv);
3045 /* Clears each of the exact match registers to zero, so they
3046 * don't interfere with normal reception
3048 static void gfar_clear_exact_match(struct net_device *dev)
3051 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3053 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3054 gfar_set_mac_for_addr(dev, idx, zero_arr);
3057 /* Update the hash table based on the current list of multicast
3058 * addresses we subscribe to. Also, change the promiscuity of
3059 * the device based on the flags (this function is called
3060 * whenever dev->flags is changed
3062 static void gfar_set_multi(struct net_device *dev)
3064 struct netdev_hw_addr *ha;
3065 struct gfar_private *priv = netdev_priv(dev);
3066 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3069 if (dev->flags & IFF_PROMISC) {
3070 /* Set RCTRL to PROM */
3071 tempval = gfar_read(®s->rctrl);
3072 tempval |= RCTRL_PROM;
3073 gfar_write(®s->rctrl, tempval);
3075 /* Set RCTRL to not PROM */
3076 tempval = gfar_read(®s->rctrl);
3077 tempval &= ~(RCTRL_PROM);
3078 gfar_write(®s->rctrl, tempval);
3081 if (dev->flags & IFF_ALLMULTI) {
3082 /* Set the hash to rx all multicast frames */
3083 gfar_write(®s->igaddr0, 0xffffffff);
3084 gfar_write(®s->igaddr1, 0xffffffff);
3085 gfar_write(®s->igaddr2, 0xffffffff);
3086 gfar_write(®s->igaddr3, 0xffffffff);
3087 gfar_write(®s->igaddr4, 0xffffffff);
3088 gfar_write(®s->igaddr5, 0xffffffff);
3089 gfar_write(®s->igaddr6, 0xffffffff);
3090 gfar_write(®s->igaddr7, 0xffffffff);
3091 gfar_write(®s->gaddr0, 0xffffffff);
3092 gfar_write(®s->gaddr1, 0xffffffff);
3093 gfar_write(®s->gaddr2, 0xffffffff);
3094 gfar_write(®s->gaddr3, 0xffffffff);
3095 gfar_write(®s->gaddr4, 0xffffffff);
3096 gfar_write(®s->gaddr5, 0xffffffff);
3097 gfar_write(®s->gaddr6, 0xffffffff);
3098 gfar_write(®s->gaddr7, 0xffffffff);
3103 /* zero out the hash */
3104 gfar_write(®s->igaddr0, 0x0);
3105 gfar_write(®s->igaddr1, 0x0);
3106 gfar_write(®s->igaddr2, 0x0);
3107 gfar_write(®s->igaddr3, 0x0);
3108 gfar_write(®s->igaddr4, 0x0);
3109 gfar_write(®s->igaddr5, 0x0);
3110 gfar_write(®s->igaddr6, 0x0);
3111 gfar_write(®s->igaddr7, 0x0);
3112 gfar_write(®s->gaddr0, 0x0);
3113 gfar_write(®s->gaddr1, 0x0);
3114 gfar_write(®s->gaddr2, 0x0);
3115 gfar_write(®s->gaddr3, 0x0);
3116 gfar_write(®s->gaddr4, 0x0);
3117 gfar_write(®s->gaddr5, 0x0);
3118 gfar_write(®s->gaddr6, 0x0);
3119 gfar_write(®s->gaddr7, 0x0);
3121 /* If we have extended hash tables, we need to
3122 * clear the exact match registers to prepare for
3125 if (priv->extended_hash) {
3126 em_num = GFAR_EM_NUM + 1;
3127 gfar_clear_exact_match(dev);
3134 if (netdev_mc_empty(dev))
3137 /* Parse the list, and set the appropriate bits */
3138 netdev_for_each_mc_addr(ha, dev) {
3140 gfar_set_mac_for_addr(dev, idx, ha->addr);
3143 gfar_set_hash_for_addr(dev, ha->addr);
3148 void gfar_mac_reset(struct gfar_private *priv)
3150 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3153 /* Reset MAC layer */
3154 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET);
3156 /* We need to delay at least 3 TX clocks */
3159 /* the soft reset bit is not self-resetting, so we need to
3160 * clear it before resuming normal operation
3162 gfar_write(®s->maccfg1, 0);
3166 gfar_rx_offload_en(priv);
3168 /* Initialize the max receive frame/buffer lengths */
3169 gfar_write(®s->maxfrm, GFAR_JUMBO_FRAME_SIZE);
3170 gfar_write(®s->mrblr, GFAR_RXB_SIZE);
3172 /* Initialize the Minimum Frame Length Register */
3173 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS);
3175 /* Initialize MACCFG2. */
3176 tempval = MACCFG2_INIT_SETTINGS;
3178 /* eTSEC74 erratum: Rx frames of length MAXFRM or MAXFRM-1
3179 * are marked as truncated. Avoid this by MACCFG2[Huge Frame]=1,
3180 * and by checking RxBD[LG] and discarding larger than MAXFRM.
3182 if (gfar_has_errata(priv, GFAR_ERRATA_74))
3183 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
3185 gfar_write(®s->maccfg2, tempval);
3187 /* Clear mac addr hash registers */
3188 gfar_write(®s->igaddr0, 0);
3189 gfar_write(®s->igaddr1, 0);
3190 gfar_write(®s->igaddr2, 0);
3191 gfar_write(®s->igaddr3, 0);
3192 gfar_write(®s->igaddr4, 0);
3193 gfar_write(®s->igaddr5, 0);
3194 gfar_write(®s->igaddr6, 0);
3195 gfar_write(®s->igaddr7, 0);
3197 gfar_write(®s->gaddr0, 0);
3198 gfar_write(®s->gaddr1, 0);
3199 gfar_write(®s->gaddr2, 0);
3200 gfar_write(®s->gaddr3, 0);
3201 gfar_write(®s->gaddr4, 0);
3202 gfar_write(®s->gaddr5, 0);
3203 gfar_write(®s->gaddr6, 0);
3204 gfar_write(®s->gaddr7, 0);
3206 if (priv->extended_hash)
3207 gfar_clear_exact_match(priv->ndev);
3209 gfar_mac_rx_config(priv);
3211 gfar_mac_tx_config(priv);
3213 gfar_set_mac_address(priv->ndev);
3215 gfar_set_multi(priv->ndev);
3217 /* clear ievent and imask before configuring coalescing */
3218 gfar_ints_disable(priv);
3220 /* Configure the coalescing support */
3221 gfar_configure_coalescing_all(priv);
3224 static void gfar_hw_init(struct gfar_private *priv)
3226 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3229 /* Stop the DMA engine now, in case it was running before
3230 * (The firmware could have used it, and left it running).
3234 gfar_mac_reset(priv);
3236 /* Zero out the rmon mib registers if it has them */
3237 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
3238 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
3240 /* Mask off the CAM interrupts */
3241 gfar_write(®s->rmon.cam1, 0xffffffff);
3242 gfar_write(®s->rmon.cam2, 0xffffffff);
3245 /* Initialize ECNTRL */
3246 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS);
3248 /* Set the extraction length and index */
3249 attrs = ATTRELI_EL(priv->rx_stash_size) |
3250 ATTRELI_EI(priv->rx_stash_index);
3252 gfar_write(®s->attreli, attrs);
3254 /* Start with defaults, and add stashing
3255 * depending on driver parameters
3257 attrs = ATTR_INIT_SETTINGS;
3259 if (priv->bd_stash_en)
3260 attrs |= ATTR_BDSTASH;
3262 if (priv->rx_stash_size != 0)
3263 attrs |= ATTR_BUFSTASH;
3265 gfar_write(®s->attr, attrs);
3268 gfar_write(®s->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
3269 gfar_write(®s->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
3270 gfar_write(®s->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
3272 /* Program the interrupt steering regs, only for MG devices */
3273 if (priv->num_grps > 1)
3274 gfar_write_isrg(priv);
3277 static const struct net_device_ops gfar_netdev_ops = {
3278 .ndo_open = gfar_enet_open,
3279 .ndo_start_xmit = gfar_start_xmit,
3280 .ndo_stop = gfar_close,
3281 .ndo_change_mtu = gfar_change_mtu,
3282 .ndo_set_features = gfar_set_features,
3283 .ndo_set_rx_mode = gfar_set_multi,
3284 .ndo_tx_timeout = gfar_timeout,
3285 .ndo_do_ioctl = gfar_ioctl,
3286 .ndo_get_stats = gfar_get_stats,
3287 .ndo_change_carrier = fixed_phy_change_carrier,
3288 .ndo_set_mac_address = gfar_set_mac_addr,
3289 .ndo_validate_addr = eth_validate_addr,
3290 #ifdef CONFIG_NET_POLL_CONTROLLER
3291 .ndo_poll_controller = gfar_netpoll,
3295 /* Set up the ethernet device structure, private data,
3296 * and anything else we need before we start
3298 static int gfar_probe(struct platform_device *ofdev)
3300 struct device_node *np = ofdev->dev.of_node;
3301 struct net_device *dev = NULL;
3302 struct gfar_private *priv = NULL;
3305 err = gfar_of_init(ofdev, &dev);
3310 priv = netdev_priv(dev);
3312 priv->ofdev = ofdev;
3313 priv->dev = &ofdev->dev;
3314 SET_NETDEV_DEV(dev, &ofdev->dev);
3316 INIT_WORK(&priv->reset_task, gfar_reset_task);
3318 platform_set_drvdata(ofdev, priv);
3320 gfar_detect_errata(priv);
3322 /* Set the dev->base_addr to the gfar reg region */
3323 dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
3325 /* Fill in the dev structure */
3326 dev->watchdog_timeo = TX_TIMEOUT;
3327 /* MTU range: 50 - 9586 */
3330 dev->max_mtu = GFAR_JUMBO_FRAME_SIZE - ETH_HLEN;
3331 dev->netdev_ops = &gfar_netdev_ops;
3332 dev->ethtool_ops = &gfar_ethtool_ops;
3334 /* Register for napi ...We are registering NAPI for each grp */
3335 for (i = 0; i < priv->num_grps; i++) {
3336 if (priv->poll_mode == GFAR_SQ_POLLING) {
3337 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
3338 gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
3339 netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
3340 gfar_poll_tx_sq, 2);
3342 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
3343 gfar_poll_rx, GFAR_DEV_WEIGHT);
3344 netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
3349 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
3350 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
3352 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
3353 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
3356 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
3357 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
3358 NETIF_F_HW_VLAN_CTAG_RX;
3359 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3362 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
3364 gfar_init_addr_hash_table(priv);
3366 /* Insert receive time stamps into padding alignment bytes, and
3367 * plus 2 bytes padding to ensure the cpu alignment.
3369 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
3370 priv->padding = 8 + DEFAULT_PADDING;
3372 if (dev->features & NETIF_F_IP_CSUM ||
3373 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
3374 dev->needed_headroom = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
3376 /* Initializing some of the rx/tx queue level parameters */
3377 for (i = 0; i < priv->num_tx_queues; i++) {
3378 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
3379 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
3380 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
3381 priv->tx_queue[i]->txic = DEFAULT_TXIC;
3384 for (i = 0; i < priv->num_rx_queues; i++) {
3385 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
3386 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
3387 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
3390 /* Always enable rx filer if available */
3391 priv->rx_filer_enable =
3392 (priv->device_flags & FSL_GIANFAR_DEV_HAS_RX_FILER) ? 1 : 0;
3393 /* Enable most messages by default */
3394 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
3395 /* use pritority h/w tx queue scheduling for single queue devices */
3396 if (priv->num_tx_queues == 1)
3397 priv->prio_sched_en = 1;
3399 set_bit(GFAR_DOWN, &priv->state);
3403 /* Carrier starts down, phylib will bring it up */
3404 netif_carrier_off(dev);
3406 err = register_netdev(dev);
3409 pr_err("%s: Cannot register net device, aborting\n", dev->name);
3413 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET)
3414 priv->wol_supported |= GFAR_WOL_MAGIC;
3416 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER) &&
3417 priv->rx_filer_enable)
3418 priv->wol_supported |= GFAR_WOL_FILER_UCAST;
3420 device_set_wakeup_capable(&ofdev->dev, priv->wol_supported);
3422 /* fill out IRQ number and name fields */
3423 for (i = 0; i < priv->num_grps; i++) {
3424 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3425 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3426 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
3427 dev->name, "_g", '0' + i, "_tx");
3428 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
3429 dev->name, "_g", '0' + i, "_rx");
3430 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
3431 dev->name, "_g", '0' + i, "_er");
3433 strcpy(gfar_irq(grp, TX)->name, dev->name);
3436 /* Initialize the filer table */
3437 gfar_init_filer_table(priv);
3439 /* Print out the device info */
3440 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
3442 /* Even more device info helps when determining which kernel
3443 * provided which set of benchmarks.
3445 netdev_info(dev, "Running with NAPI enabled\n");
3446 for (i = 0; i < priv->num_rx_queues; i++)
3447 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
3448 i, priv->rx_queue[i]->rx_ring_size);
3449 for (i = 0; i < priv->num_tx_queues; i++)
3450 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
3451 i, priv->tx_queue[i]->tx_ring_size);
3456 if (of_phy_is_fixed_link(np))
3457 of_phy_deregister_fixed_link(np);
3458 unmap_group_regs(priv);
3459 gfar_free_rx_queues(priv);
3460 gfar_free_tx_queues(priv);
3461 of_node_put(priv->phy_node);
3462 of_node_put(priv->tbi_node);
3463 free_gfar_dev(priv);
3467 static int gfar_remove(struct platform_device *ofdev)
3469 struct gfar_private *priv = platform_get_drvdata(ofdev);
3470 struct device_node *np = ofdev->dev.of_node;
3472 of_node_put(priv->phy_node);
3473 of_node_put(priv->tbi_node);
3475 unregister_netdev(priv->ndev);
3477 if (of_phy_is_fixed_link(np))
3478 of_phy_deregister_fixed_link(np);
3480 unmap_group_regs(priv);
3481 gfar_free_rx_queues(priv);
3482 gfar_free_tx_queues(priv);
3483 free_gfar_dev(priv);
3490 static void __gfar_filer_disable(struct gfar_private *priv)
3492 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3495 temp = gfar_read(®s->rctrl);
3496 temp &= ~(RCTRL_FILREN | RCTRL_PRSDEP_INIT);
3497 gfar_write(®s->rctrl, temp);
3500 static void __gfar_filer_enable(struct gfar_private *priv)
3502 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3505 temp = gfar_read(®s->rctrl);
3506 temp |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
3507 gfar_write(®s->rctrl, temp);
3510 /* Filer rules implementing wol capabilities */
3511 static void gfar_filer_config_wol(struct gfar_private *priv)
3516 __gfar_filer_disable(priv);
3518 /* clear the filer table, reject any packet by default */
3519 rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH;
3520 for (i = 0; i <= MAX_FILER_IDX; i++)
3521 gfar_write_filer(priv, i, rqfcr, 0);
3524 if (priv->wol_opts & GFAR_WOL_FILER_UCAST) {
3525 /* unicast packet, accept it */
3526 struct net_device *ndev = priv->ndev;
3527 /* get the default rx queue index */
3528 u8 qindex = (u8)priv->gfargrp[0].rx_queue->qindex;
3529 u32 dest_mac_addr = (ndev->dev_addr[0] << 16) |
3530 (ndev->dev_addr[1] << 8) |
3533 rqfcr = (qindex << 10) | RQFCR_AND |
3534 RQFCR_CMP_EXACT | RQFCR_PID_DAH;
3536 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
3538 dest_mac_addr = (ndev->dev_addr[3] << 16) |
3539 (ndev->dev_addr[4] << 8) |
3541 rqfcr = (qindex << 10) | RQFCR_GPI |
3542 RQFCR_CMP_EXACT | RQFCR_PID_DAL;
3543 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
3546 __gfar_filer_enable(priv);
3549 static void gfar_filer_restore_table(struct gfar_private *priv)
3554 __gfar_filer_disable(priv);
3556 for (i = 0; i <= MAX_FILER_IDX; i++) {
3557 rqfcr = priv->ftp_rqfcr[i];
3558 rqfpr = priv->ftp_rqfpr[i];
3559 gfar_write_filer(priv, i, rqfcr, rqfpr);
3562 __gfar_filer_enable(priv);
3565 /* gfar_start() for Rx only and with the FGPI filer interrupt enabled */
3566 static void gfar_start_wol_filer(struct gfar_private *priv)
3568 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3572 /* Enable Rx hw queues */
3573 gfar_write(®s->rqueue, priv->rqueue);
3575 /* Initialize DMACTRL to have WWR and WOP */
3576 tempval = gfar_read(®s->dmactrl);
3577 tempval |= DMACTRL_INIT_SETTINGS;
3578 gfar_write(®s->dmactrl, tempval);
3580 /* Make sure we aren't stopped */
3581 tempval = gfar_read(®s->dmactrl);
3582 tempval &= ~DMACTRL_GRS;
3583 gfar_write(®s->dmactrl, tempval);
3585 for (i = 0; i < priv->num_grps; i++) {
3586 regs = priv->gfargrp[i].regs;
3587 /* Clear RHLT, so that the DMA starts polling now */
3588 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
3589 /* enable the Filer General Purpose Interrupt */
3590 gfar_write(®s->imask, IMASK_FGPI);
3594 tempval = gfar_read(®s->maccfg1);
3595 tempval |= MACCFG1_RX_EN;
3596 gfar_write(®s->maccfg1, tempval);
3599 static int gfar_suspend(struct device *dev)
3601 struct gfar_private *priv = dev_get_drvdata(dev);
3602 struct net_device *ndev = priv->ndev;
3603 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3605 u16 wol = priv->wol_opts;
3607 if (!netif_running(ndev))
3611 netif_tx_lock(ndev);
3612 netif_device_detach(ndev);
3613 netif_tx_unlock(ndev);
3617 if (wol & GFAR_WOL_MAGIC) {
3618 /* Enable interrupt on Magic Packet */
3619 gfar_write(®s->imask, IMASK_MAG);
3621 /* Enable Magic Packet mode */
3622 tempval = gfar_read(®s->maccfg2);
3623 tempval |= MACCFG2_MPEN;
3624 gfar_write(®s->maccfg2, tempval);
3626 /* re-enable the Rx block */
3627 tempval = gfar_read(®s->maccfg1);
3628 tempval |= MACCFG1_RX_EN;
3629 gfar_write(®s->maccfg1, tempval);
3631 } else if (wol & GFAR_WOL_FILER_UCAST) {
3632 gfar_filer_config_wol(priv);
3633 gfar_start_wol_filer(priv);
3636 phy_stop(ndev->phydev);
3642 static int gfar_resume(struct device *dev)
3644 struct gfar_private *priv = dev_get_drvdata(dev);
3645 struct net_device *ndev = priv->ndev;
3646 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3648 u16 wol = priv->wol_opts;
3650 if (!netif_running(ndev))
3653 if (wol & GFAR_WOL_MAGIC) {
3654 /* Disable Magic Packet mode */
3655 tempval = gfar_read(®s->maccfg2);
3656 tempval &= ~MACCFG2_MPEN;
3657 gfar_write(®s->maccfg2, tempval);
3659 } else if (wol & GFAR_WOL_FILER_UCAST) {
3660 /* need to stop rx only, tx is already down */
3662 gfar_filer_restore_table(priv);
3665 phy_start(ndev->phydev);
3670 netif_device_attach(ndev);
3676 static int gfar_restore(struct device *dev)
3678 struct gfar_private *priv = dev_get_drvdata(dev);
3679 struct net_device *ndev = priv->ndev;
3681 if (!netif_running(ndev)) {
3682 netif_device_attach(ndev);
3687 gfar_init_bds(ndev);
3689 gfar_mac_reset(priv);
3691 gfar_init_tx_rx_base(priv);
3697 priv->oldduplex = -1;
3700 phy_start(ndev->phydev);
3702 netif_device_attach(ndev);
3708 static const struct dev_pm_ops gfar_pm_ops = {
3709 .suspend = gfar_suspend,
3710 .resume = gfar_resume,
3711 .freeze = gfar_suspend,
3712 .thaw = gfar_resume,
3713 .restore = gfar_restore,
3716 #define GFAR_PM_OPS (&gfar_pm_ops)
3720 #define GFAR_PM_OPS NULL
3724 static const struct of_device_id gfar_match[] =
3728 .compatible = "gianfar",
3731 .compatible = "fsl,etsec2",
3735 MODULE_DEVICE_TABLE(of, gfar_match);
3737 /* Structure for a device driver */
3738 static struct platform_driver gfar_driver = {
3740 .name = "fsl-gianfar",
3742 .of_match_table = gfar_match,
3744 .probe = gfar_probe,
3745 .remove = gfar_remove,
3748 module_platform_driver(gfar_driver);