drivers/net/ethernet/freescale/dpaa/dpaa_eth.c

   1 /* Copyright 2008 - 2016 Freescale Semiconductor Inc.
   2  *
   3  * Redistribution and use in source and binary forms, with or without
   4  * modification, are permitted provided that the following conditions are met:
   5  *     * Redistributions of source code must retain the above copyright
   6  *       notice, this list of conditions and the following disclaimer.
   7  *     * Redistributions in binary form must reproduce the above copyright
   8  *       notice, this list of conditions and the following disclaimer in the
   9  *       documentation and/or other materials provided with the distribution.
  10  *     * Neither the name of Freescale Semiconductor nor the
  11  *       names of its contributors may be used to endorse or promote products
  12  *       derived from this software without specific prior written permission.
  13  *
  14  * ALTERNATIVELY, this software may be distributed under the terms of the
  15  * GNU General Public License ("GPL") as published by the Free Software
  16  * Foundation, either version 2 of that License or (at your option) any
  17  * later version.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  20  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  21  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  22  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  23  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  25  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  26  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  32
  33 #include <linux/init.h>
  34 #include <linux/module.h>
  35 #include <linux/of_platform.h>
  36 #include <linux/of_mdio.h>
  37 #include <linux/of_net.h>
  38 #include <linux/io.h>
  39 #include <linux/if_arp.h>
  40 #include <linux/if_vlan.h>
  41 #include <linux/icmp.h>
  42 #include <linux/ip.h>
  43 #include <linux/ipv6.h>
  44 #include <linux/udp.h>
  45 #include <linux/tcp.h>
  46 #include <linux/net.h>
  47 #include <linux/skbuff.h>
  48 #include <linux/etherdevice.h>
  49 #include <linux/if_ether.h>
  50 #include <linux/highmem.h>
  51 #include <linux/percpu.h>
  52 #include <linux/dma-mapping.h>
  53 #include <linux/sort.h>
  54 #include <soc/fsl/bman.h>
  55 #include <soc/fsl/qman.h>
  56
  57 #include "fman.h"
  58 #include "fman_port.h"
  59 #include "mac.h"
  60 #include "dpaa_eth.h"
  61
  62 /* CREATE_TRACE_POINTS only needs to be defined once. Other dpaa files
  63  * using trace events only need to #include <trace/events/sched.h>
  64  */
  65 #define CREATE_TRACE_POINTS
  66 #include "dpaa_eth_trace.h"
  67
  68 static int debug = -1;
  69 module_param(debug, int, 0444);
  70 MODULE_PARM_DESC(debug, "Module/Driver verbosity level (0=none,...,16=all)");
  71
  72 static u16 tx_timeout = 1000;
  73 module_param(tx_timeout, ushort, 0444);
  74 MODULE_PARM_DESC(tx_timeout, "The Tx timeout in ms");
  75
  76 #define FM_FD_STAT_RX_ERRORS                                            \
  77         (FM_FD_ERR_DMA | FM_FD_ERR_PHYSICAL     | \
  78          FM_FD_ERR_SIZE | FM_FD_ERR_CLS_DISCARD | \
  79          FM_FD_ERR_EXTRACTION | FM_FD_ERR_NO_SCHEME     | \
  80          FM_FD_ERR_PRS_TIMEOUT | FM_FD_ERR_PRS_ILL_INSTRUCT | \
  81          FM_FD_ERR_PRS_HDR_ERR)
  82
  83 #define FM_FD_STAT_TX_ERRORS \
  84         (FM_FD_ERR_UNSUPPORTED_FORMAT | \
  85          FM_FD_ERR_LENGTH | FM_FD_ERR_DMA)
  86
  87 #define DPAA_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
  88                           NETIF_MSG_LINK | NETIF_MSG_IFUP | \
  89                           NETIF_MSG_IFDOWN)
  90
  91 #define DPAA_INGRESS_CS_THRESHOLD 0x10000000
  92 /* Ingress congestion threshold on FMan ports
  93  * The size in bytes of the ingress tail-drop threshold on FMan ports.
  94  * Traffic piling up above this value will be rejected by QMan and discarded
  95  * by FMan.
  96  */
  97
  98 /* Size in bytes of the FQ taildrop threshold */
  99 #define DPAA_FQ_TD 0x200000
 100
 101 #define DPAA_CS_THRESHOLD_1G 0x06000000
 102 /* Egress congestion threshold on 1G ports, range 0x1000 .. 0x10000000
 103  * The size in bytes of the egress Congestion State notification threshold on
 104  * 1G ports. The 1G dTSECs can quite easily be flooded by cores doing Tx in a
 105  * tight loop (e.g. by sending UDP datagrams at "while(1) speed"),
 106  * and the larger the frame size, the more acute the problem.
 107  * So we have to find a balance between these factors:
 108  * - avoiding the device staying congested for a prolonged time (risking
 109  *   the netdev watchdog to fire - see also the tx_timeout module param);
 110  * - affecting performance of protocols such as TCP, which otherwise
 111  *   behave well under the congestion notification mechanism;
 112  * - preventing the Tx cores from tightly-looping (as if the congestion
 113  *   threshold was too low to be effective);
 114  * - running out of memory if the CS threshold is set too high.
 115  */
 116
 117 #define DPAA_CS_THRESHOLD_10G 0x10000000
 118 /* The size in bytes of the egress Congestion State notification threshold on
 119  * 10G ports, range 0x1000 .. 0x10000000
 120  */
 121
 122 /* Largest value that the FQD's OAL field can hold */
 123 #define FSL_QMAN_MAX_OAL        127
 124
 125 /* Default alignment for start of data in an Rx FD */
 126 #define DPAA_FD_DATA_ALIGNMENT  16
 127
 128 /* Values for the L3R field of the FM Parse Results
 129  */
 130 /* L3 Type field: First IP Present IPv4 */
 131 #define FM_L3_PARSE_RESULT_IPV4 0x8000
 132 /* L3 Type field: First IP Present IPv6 */
 133 #define FM_L3_PARSE_RESULT_IPV6 0x4000
 134 /* Values for the L4R field of the FM Parse Results */
 135 /* L4 Type field: UDP */
 136 #define FM_L4_PARSE_RESULT_UDP  0x40
 137 /* L4 Type field: TCP */
 138 #define FM_L4_PARSE_RESULT_TCP  0x20
 139
 140 /* FD status field indicating whether the FM Parser has attempted to validate
 141  * the L4 csum of the frame.
 142  * Note that having this bit set doesn't necessarily imply that the checksum
 143  * is valid. One would have to check the parse results to find that out.
 144  */
 145 #define FM_FD_STAT_L4CV         0x00000004
 146
 147 #define DPAA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */
 148 #define DPAA_BUFF_RELEASE_MAX 8 /* maximum number of buffers released at once */
 149
 150 #define FSL_DPAA_BPID_INV               0xff
 151 #define FSL_DPAA_ETH_MAX_BUF_COUNT      128
 152 #define FSL_DPAA_ETH_REFILL_THRESHOLD   80
 153
 154 #define DPAA_TX_PRIV_DATA_SIZE  16
 155 #define DPAA_PARSE_RESULTS_SIZE sizeof(struct fman_prs_result)
 156 #define DPAA_TIME_STAMP_SIZE 8
 157 #define DPAA_HASH_RESULTS_SIZE 8
 158 #define DPAA_RX_PRIV_DATA_SIZE  (u16)(DPAA_TX_PRIV_DATA_SIZE + \
 159                                         dpaa_rx_extra_headroom)
 160
 161 #define DPAA_ETH_PCD_RXQ_NUM    128
 162
 163 #define DPAA_ENQUEUE_RETRIES    100000
 164
 165 enum port_type {RX, TX};
 166
 167 struct fm_port_fqs {
 168         struct dpaa_fq *tx_defq;
 169         struct dpaa_fq *tx_errq;
 170         struct dpaa_fq *rx_defq;
 171         struct dpaa_fq *rx_errq;
 172         struct dpaa_fq *rx_pcdq;
 173 };
 174
 175 /* All the dpa bps in use at any moment */
 176 static struct dpaa_bp *dpaa_bp_array[BM_MAX_NUM_OF_POOLS];
 177
 178 /* The raw buffer size must be cacheline aligned */
 179 #define DPAA_BP_RAW_SIZE 4096
 180 /* When using more than one buffer pool, the raw sizes are as follows:
 181  * 1 bp: 4KB
 182  * 2 bp: 2KB, 4KB
 183  * 3 bp: 1KB, 2KB, 4KB
 184  * 4 bp: 1KB, 2KB, 4KB, 8KB
 185  */
 186 static inline size_t bpool_buffer_raw_size(u8 index, u8 cnt)
 187 {
 188         size_t res = DPAA_BP_RAW_SIZE / 4;
 189         u8 i;
 190
 191         for (i = (cnt < 3) ? cnt : 3; i < 3 + index; i++)
 192                 res *= 2;
 193         return res;
 194 }
 195
 196 /* FMan-DMA requires 16-byte alignment for Rx buffers, but SKB_DATA_ALIGN is
 197  * even stronger (SMP_CACHE_BYTES-aligned), so we just get away with that,
 198  * via SKB_WITH_OVERHEAD(). We can't rely on netdev_alloc_frag() giving us
 199  * half-page-aligned buffers, so we reserve some more space for start-of-buffer
 200  * alignment.
 201  */
 202 #define dpaa_bp_size(raw_size) SKB_WITH_OVERHEAD((raw_size) - SMP_CACHE_BYTES)
 203
 204 static int dpaa_max_frm;
 205
 206 static int dpaa_rx_extra_headroom;
 207
 208 #define dpaa_get_max_mtu()      \
 209         (dpaa_max_frm - (VLAN_ETH_HLEN + ETH_FCS_LEN))
 210
 211 static int dpaa_netdev_init(struct net_device *net_dev,
 212                             const struct net_device_ops *dpaa_ops,
 213                             u16 tx_timeout)
 214 {
 215         struct dpaa_priv *priv = netdev_priv(net_dev);
 216         struct device *dev = net_dev->dev.parent;
 217         struct dpaa_percpu_priv *percpu_priv;
 218         const u8 *mac_addr;
 219         int i, err;
 220
 221         /* Although we access another CPU's private data here
 222          * we do it at initialization so it is safe
 223          */
 224         for_each_possible_cpu(i) {
 225                 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
 226                 percpu_priv->net_dev = net_dev;
 227         }
 228
 229         net_dev->netdev_ops = dpaa_ops;
 230         mac_addr = priv->mac_dev->addr;
 231
 232         net_dev->mem_start = priv->mac_dev->res->start;
 233         net_dev->mem_end = priv->mac_dev->res->end;
 234
 235         net_dev->min_mtu = ETH_MIN_MTU;
 236         net_dev->max_mtu = dpaa_get_max_mtu();
 237
 238         net_dev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
 239                                  NETIF_F_LLTX | NETIF_F_RXHASH);
 240
 241         net_dev->hw_features |= NETIF_F_SG | NETIF_F_HIGHDMA;
 242         /* The kernels enables GSO automatically, if we declare NETIF_F_SG.
 243          * For conformity, we'll still declare GSO explicitly.
 244          */
 245         net_dev->features |= NETIF_F_GSO;
 246         net_dev->features |= NETIF_F_RXCSUM;
 247
 248         net_dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
 249         /* we do not want shared skbs on TX */
 250         net_dev->priv_flags &= ~IFF_TX_SKB_SHARING;
 251
 252         net_dev->features |= net_dev->hw_features;
 253         net_dev->vlan_features = net_dev->features;
 254
 255         memcpy(net_dev->perm_addr, mac_addr, net_dev->addr_len);
 256         memcpy(net_dev->dev_addr, mac_addr, net_dev->addr_len);
 257
 258         net_dev->ethtool_ops = &dpaa_ethtool_ops;
 259
 260         net_dev->needed_headroom = priv->tx_headroom;
 261         net_dev->watchdog_timeo = msecs_to_jiffies(tx_timeout);
 262
 263         /* start without the RUNNING flag, phylib controls it later */
 264         netif_carrier_off(net_dev);
 265
 266         err = register_netdev(net_dev);
 267         if (err < 0) {
 268                 dev_err(dev, "register_netdev() = %d\n", err);
 269                 return err;
 270         }
 271
 272         return 0;
 273 }
 274
 275 static int dpaa_stop(struct net_device *net_dev)
 276 {
 277         struct mac_device *mac_dev;
 278         struct dpaa_priv *priv;
 279         int i, err, error;
 280
 281         priv = netdev_priv(net_dev);
 282         mac_dev = priv->mac_dev;
 283
 284         netif_tx_stop_all_queues(net_dev);
 285         /* Allow the Fman (Tx) port to process in-flight frames before we
 286          * try switching it off.
 287          */
 288         usleep_range(5000, 10000);
 289
 290         err = mac_dev->stop(mac_dev);
 291         if (err < 0)
 292                 netif_err(priv, ifdown, net_dev, "mac_dev->stop() = %d\n",
 293                           err);
 294
 295         for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) {
 296                 error = fman_port_disable(mac_dev->port[i]);
 297                 if (error)
 298                         err = error;
 299         }
 300
 301         if (net_dev->phydev)
 302                 phy_disconnect(net_dev->phydev);
 303         net_dev->phydev = NULL;
 304
 305         return err;
 306 }
 307
 308 static void dpaa_tx_timeout(struct net_device *net_dev)
 309 {
 310         struct dpaa_percpu_priv *percpu_priv;
 311         const struct dpaa_priv  *priv;
 312
 313         priv = netdev_priv(net_dev);
 314         percpu_priv = this_cpu_ptr(priv->percpu_priv);
 315
 316         netif_crit(priv, timer, net_dev, "Transmit timeout latency: %u ms\n",
 317                    jiffies_to_msecs(jiffies - dev_trans_start(net_dev)));
 318
 319         percpu_priv->stats.tx_errors++;
 320 }
 321
 322 /* Calculates the statistics for the given device by adding the statistics
 323  * collected by each CPU.
 324  */
 325 static void dpaa_get_stats64(struct net_device *net_dev,
 326                              struct rtnl_link_stats64 *s)
 327 {
 328         int numstats = sizeof(struct rtnl_link_stats64) / sizeof(u64);
 329         struct dpaa_priv *priv = netdev_priv(net_dev);
 330         struct dpaa_percpu_priv *percpu_priv;
 331         u64 *netstats = (u64 *)s;
 332         u64 *cpustats;
 333         int i, j;
 334
 335         for_each_possible_cpu(i) {
 336                 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
 337
 338                 cpustats = (u64 *)&percpu_priv->stats;
 339
 340                 /* add stats from all CPUs */
 341                 for (j = 0; j < numstats; j++)
 342                         netstats[j] += cpustats[j];
 343         }
 344 }
 345
 346 static int dpaa_setup_tc(struct net_device *net_dev, enum tc_setup_type type,
 347                          void *type_data)
 348 {
 349         struct dpaa_priv *priv = netdev_priv(net_dev);
 350         struct tc_mqprio_qopt *mqprio = type_data;
 351         u8 num_tc;
 352         int i;
 353
 354         if (type != TC_SETUP_QDISC_MQPRIO)
 355                 return -EOPNOTSUPP;
 356
 357         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
 358         num_tc = mqprio->num_tc;
 359
 360         if (num_tc == priv->num_tc)
 361                 return 0;
 362
 363         if (!num_tc) {
 364                 netdev_reset_tc(net_dev);
 365                 goto out;
 366         }
 367
 368         if (num_tc > DPAA_TC_NUM) {
 369                 netdev_err(net_dev, "Too many traffic classes: max %d supported.\n",
 370                            DPAA_TC_NUM);
 371                 return -EINVAL;
 372         }
 373
 374         netdev_set_num_tc(net_dev, num_tc);
 375
 376         for (i = 0; i < num_tc; i++)
 377                 netdev_set_tc_queue(net_dev, i, DPAA_TC_TXQ_NUM,
 378                                     i * DPAA_TC_TXQ_NUM);
 379
 380 out:
 381         priv->num_tc = num_tc ? : 1;
 382         netif_set_real_num_tx_queues(net_dev, priv->num_tc * DPAA_TC_TXQ_NUM);
 383         return 0;
 384 }
 385
 386 static struct mac_device *dpaa_mac_dev_get(struct platform_device *pdev)
 387 {
 388         struct dpaa_eth_data *eth_data;
 389         struct device *dpaa_dev;
 390         struct mac_device *mac_dev;
 391
 392         dpaa_dev = &pdev->dev;
 393         eth_data = dpaa_dev->platform_data;
 394         if (!eth_data) {
 395                 dev_err(dpaa_dev, "eth_data missing\n");
 396                 return ERR_PTR(-ENODEV);
 397         }
 398         mac_dev = eth_data->mac_dev;
 399         if (!mac_dev) {
 400                 dev_err(dpaa_dev, "mac_dev missing\n");
 401                 return ERR_PTR(-EINVAL);
 402         }
 403
 404         return mac_dev;
 405 }
 406
 407 static int dpaa_set_mac_address(struct net_device *net_dev, void *addr)
 408 {
 409         const struct dpaa_priv *priv;
 410         struct mac_device *mac_dev;
 411         struct sockaddr old_addr;
 412         int err;
 413
 414         priv = netdev_priv(net_dev);
 415
 416         memcpy(old_addr.sa_data, net_dev->dev_addr,  ETH_ALEN);
 417
 418         err = eth_mac_addr(net_dev, addr);
 419         if (err < 0) {
 420                 netif_err(priv, drv, net_dev, "eth_mac_addr() = %d\n", err);
 421                 return err;
 422         }
 423
 424         mac_dev = priv->mac_dev;
 425
 426         err = mac_dev->change_addr(mac_dev->fman_mac,
 427                                    (enet_addr_t *)net_dev->dev_addr);
 428         if (err < 0) {
 429                 netif_err(priv, drv, net_dev, "mac_dev->change_addr() = %d\n",
 430                           err);
 431                 /* reverting to previous address */
 432                 eth_mac_addr(net_dev, &old_addr);
 433
 434                 return err;
 435         }
 436
 437         return 0;
 438 }
 439
 440 static void dpaa_set_rx_mode(struct net_device *net_dev)
 441 {
 442         const struct dpaa_priv  *priv;
 443         int err;
 444
 445         priv = netdev_priv(net_dev);
 446
 447         if (!!(net_dev->flags & IFF_PROMISC) != priv->mac_dev->promisc) {
 448                 priv->mac_dev->promisc = !priv->mac_dev->promisc;
 449                 err = priv->mac_dev->set_promisc(priv->mac_dev->fman_mac,
 450                                                  priv->mac_dev->promisc);
 451                 if (err < 0)
 452                         netif_err(priv, drv, net_dev,
 453                                   "mac_dev->set_promisc() = %d\n",
 454                                   err);
 455         }
 456
 457         if (!!(net_dev->flags & IFF_ALLMULTI) != priv->mac_dev->allmulti) {
 458                 priv->mac_dev->allmulti = !priv->mac_dev->allmulti;
 459                 err = priv->mac_dev->set_allmulti(priv->mac_dev->fman_mac,
 460                                                   priv->mac_dev->allmulti);
 461                 if (err < 0)
 462                         netif_err(priv, drv, net_dev,
 463                                   "mac_dev->set_allmulti() = %d\n",
 464                                   err);
 465         }
 466
 467         err = priv->mac_dev->set_multi(net_dev, priv->mac_dev);
 468         if (err < 0)
 469                 netif_err(priv, drv, net_dev, "mac_dev->set_multi() = %d\n",
 470                           err);
 471 }
 472
 473 static struct dpaa_bp *dpaa_bpid2pool(int bpid)
 474 {
 475         if (WARN_ON(bpid < 0 || bpid >= BM_MAX_NUM_OF_POOLS))
 476                 return NULL;
 477
 478         return dpaa_bp_array[bpid];
 479 }
 480
 481 /* checks if this bpool is already allocated */
 482 static bool dpaa_bpid2pool_use(int bpid)
 483 {
 484         if (dpaa_bpid2pool(bpid)) {
 485                 atomic_inc(&dpaa_bp_array[bpid]->refs);
 486                 return true;
 487         }
 488
 489         return false;
 490 }
 491
 492 /* called only once per bpid by dpaa_bp_alloc_pool() */
 493 static void dpaa_bpid2pool_map(int bpid, struct dpaa_bp *dpaa_bp)
 494 {
 495         dpaa_bp_array[bpid] = dpaa_bp;
 496         atomic_set(&dpaa_bp->refs, 1);
 497 }
 498
 499 static int dpaa_bp_alloc_pool(struct dpaa_bp *dpaa_bp)
 500 {
 501         int err;
 502
 503         if (dpaa_bp->size == 0 || dpaa_bp->config_count == 0) {
 504                 pr_err("%s: Buffer pool is not properly initialized! Missing size or initial number of buffers\n",
 505                        __func__);
 506                 return -EINVAL;
 507         }
 508
 509         /* If the pool is already specified, we only create one per bpid */
 510         if (dpaa_bp->bpid != FSL_DPAA_BPID_INV &&
 511             dpaa_bpid2pool_use(dpaa_bp->bpid))
 512                 return 0;
 513
 514         if (dpaa_bp->bpid == FSL_DPAA_BPID_INV) {
 515                 dpaa_bp->pool = bman_new_pool();
 516                 if (!dpaa_bp->pool) {
 517                         pr_err("%s: bman_new_pool() failed\n",
 518                                __func__);
 519                         return -ENODEV;
 520                 }
 521
 522                 dpaa_bp->bpid = (u8)bman_get_bpid(dpaa_bp->pool);
 523         }
 524
 525         if (dpaa_bp->seed_cb) {
 526                 err = dpaa_bp->seed_cb(dpaa_bp);
 527                 if (err)
 528                         goto pool_seed_failed;
 529         }
 530
 531         dpaa_bpid2pool_map(dpaa_bp->bpid, dpaa_bp);
 532
 533         return 0;
 534
 535 pool_seed_failed:
 536         pr_err("%s: pool seeding failed\n", __func__);
 537         bman_free_pool(dpaa_bp->pool);
 538
 539         return err;
 540 }
 541
 542 /* remove and free all the buffers from the given buffer pool */
 543 static void dpaa_bp_drain(struct dpaa_bp *bp)
 544 {
 545         u8 num = 8;
 546         int ret;
 547
 548         do {
 549                 struct bm_buffer bmb[8];
 550                 int i;
 551
 552                 ret = bman_acquire(bp->pool, bmb, num);
 553                 if (ret < 0) {
 554                         if (num == 8) {
 555                                 /* we have less than 8 buffers left;
 556                                  * drain them one by one
 557                                  */
 558                                 num = 1;
 559                                 ret = 1;
 560                                 continue;
 561                         } else {
 562                                 /* Pool is fully drained */
 563                                 break;
 564                         }
 565                 }
 566
 567                 if (bp->free_buf_cb)
 568                         for (i = 0; i < num; i++)
 569                                 bp->free_buf_cb(bp, &bmb[i]);
 570         } while (ret > 0);
 571 }
 572
 573 static void dpaa_bp_free(struct dpaa_bp *dpaa_bp)
 574 {
 575         struct dpaa_bp *bp = dpaa_bpid2pool(dpaa_bp->bpid);
 576
 577         /* the mapping between bpid and dpaa_bp is done very late in the
 578          * allocation procedure; if something failed before the mapping, the bp
 579          * was not configured, therefore we don't need the below instructions
 580          */
 581         if (!bp)
 582                 return;
 583
 584         if (!atomic_dec_and_test(&bp->refs))
 585                 return;
 586
 587         if (bp->free_buf_cb)
 588                 dpaa_bp_drain(bp);
 589
 590         dpaa_bp_array[bp->bpid] = NULL;
 591         bman_free_pool(bp->pool);
 592 }
 593
 594 static void dpaa_bps_free(struct dpaa_priv *priv)
 595 {
 596         int i;
 597
 598         for (i = 0; i < DPAA_BPS_NUM; i++)
 599                 dpaa_bp_free(priv->dpaa_bps[i]);
 600 }
 601
 602 /* Use multiple WQs for FQ assignment:
 603  *      - Tx Confirmation queues go to WQ1.
 604  *      - Rx Error and Tx Error queues go to WQ5 (giving them a better chance
 605  *        to be scheduled, in case there are many more FQs in WQ6).
 606  *      - Rx Default goes to WQ6.
 607  *      - Tx queues go to different WQs depending on their priority. Equal
 608  *        chunks of NR_CPUS queues go to WQ6 (lowest priority), WQ2, WQ1 and
 609  *        WQ0 (highest priority).
 610  * This ensures that Tx-confirmed buffers are timely released. In particular,
 611  * it avoids congestion on the Tx Confirm FQs, which can pile up PFDRs if they
 612  * are greatly outnumbered by other FQs in the system, while
 613  * dequeue scheduling is round-robin.
 614  */
 615 static inline void dpaa_assign_wq(struct dpaa_fq *fq, int idx)
 616 {
 617         switch (fq->fq_type) {
 618         case FQ_TYPE_TX_CONFIRM:
 619         case FQ_TYPE_TX_CONF_MQ:
 620                 fq->wq = 1;
 621                 break;
 622         case FQ_TYPE_RX_ERROR:
 623         case FQ_TYPE_TX_ERROR:
 624                 fq->wq = 5;
 625                 break;
 626         case FQ_TYPE_RX_DEFAULT:
 627         case FQ_TYPE_RX_PCD:
 628                 fq->wq = 6;
 629                 break;
 630         case FQ_TYPE_TX:
 631                 switch (idx / DPAA_TC_TXQ_NUM) {
 632                 case 0:
 633                         /* Low priority (best effort) */
 634                         fq->wq = 6;
 635                         break;
 636                 case 1:
 637                         /* Medium priority */
 638                         fq->wq = 2;
 639                         break;
 640                 case 2:
 641                         /* High priority */
 642                         fq->wq = 1;
 643                         break;
 644                 case 3:
 645                         /* Very high priority */
 646                         fq->wq = 0;
 647                         break;
 648                 default:
 649                         WARN(1, "Too many TX FQs: more than %d!\n",
 650                              DPAA_ETH_TXQ_NUM);
 651                 }
 652                 break;
 653         default:
 654                 WARN(1, "Invalid FQ type %d for FQID %d!\n",
 655                      fq->fq_type, fq->fqid);
 656         }
 657 }
 658
 659 static struct dpaa_fq *dpaa_fq_alloc(struct device *dev,
 660                                      u32 start, u32 count,
 661                                      struct list_head *list,
 662                                      enum dpaa_fq_type fq_type)
 663 {
 664         struct dpaa_fq *dpaa_fq;
 665         int i;
 666
 667         dpaa_fq = devm_kcalloc(dev, count, sizeof(*dpaa_fq),
 668                                GFP_KERNEL);
 669         if (!dpaa_fq)
 670                 return NULL;
 671
 672         for (i = 0; i < count; i++) {
 673                 dpaa_fq[i].fq_type = fq_type;
 674                 dpaa_fq[i].fqid = start ? start + i : 0;
 675                 list_add_tail(&dpaa_fq[i].list, list);
 676         }
 677
 678         for (i = 0; i < count; i++)
 679                 dpaa_assign_wq(dpaa_fq + i, i);
 680
 681         return dpaa_fq;
 682 }
 683
 684 static int dpaa_alloc_all_fqs(struct device *dev, struct list_head *list,
 685                               struct fm_port_fqs *port_fqs)
 686 {
 687         struct dpaa_fq *dpaa_fq;
 688         u32 fq_base, fq_base_aligned, i;
 689
 690         dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_ERROR);
 691         if (!dpaa_fq)
 692                 goto fq_alloc_failed;
 693
 694         port_fqs->rx_errq = &dpaa_fq[0];
 695
 696         dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_DEFAULT);
 697         if (!dpaa_fq)
 698                 goto fq_alloc_failed;
 699
 700         port_fqs->rx_defq = &dpaa_fq[0];
 701
 702         /* the PCD FQIDs range needs to be aligned for correct operation */
 703         if (qman_alloc_fqid_range(&fq_base, 2 * DPAA_ETH_PCD_RXQ_NUM))
 704                 goto fq_alloc_failed;
 705
 706         fq_base_aligned = ALIGN(fq_base, DPAA_ETH_PCD_RXQ_NUM);
 707
 708         for (i = fq_base; i < fq_base_aligned; i++)
 709                 qman_release_fqid(i);
 710
 711         for (i = fq_base_aligned + DPAA_ETH_PCD_RXQ_NUM;
 712              i < (fq_base + 2 * DPAA_ETH_PCD_RXQ_NUM); i++)
 713                 qman_release_fqid(i);
 714
 715         dpaa_fq = dpaa_fq_alloc(dev, fq_base_aligned, DPAA_ETH_PCD_RXQ_NUM,
 716                                 list, FQ_TYPE_RX_PCD);
 717         if (!dpaa_fq)
 718                 goto fq_alloc_failed;
 719
 720         port_fqs->rx_pcdq = &dpaa_fq[0];
 721
 722         if (!dpaa_fq_alloc(dev, 0, DPAA_ETH_TXQ_NUM, list, FQ_TYPE_TX_CONF_MQ))
 723                 goto fq_alloc_failed;
 724
 725         dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_ERROR);
 726         if (!dpaa_fq)
 727                 goto fq_alloc_failed;
 728
 729         port_fqs->tx_errq = &dpaa_fq[0];
 730
 731         dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_CONFIRM);
 732         if (!dpaa_fq)
 733                 goto fq_alloc_failed;
 734
 735         port_fqs->tx_defq = &dpaa_fq[0];
 736
 737         if (!dpaa_fq_alloc(dev, 0, DPAA_ETH_TXQ_NUM, list, FQ_TYPE_TX))
 738                 goto fq_alloc_failed;
 739
 740         return 0;
 741
 742 fq_alloc_failed:
 743         dev_err(dev, "dpaa_fq_alloc() failed\n");
 744         return -ENOMEM;
 745 }
 746
 747 static u32 rx_pool_channel;
 748 static DEFINE_SPINLOCK(rx_pool_channel_init);
 749
 750 static int dpaa_get_channel(void)
 751 {
 752         spin_lock(&rx_pool_channel_init);
 753         if (!rx_pool_channel) {
 754                 u32 pool;
 755                 int ret;
 756
 757                 ret = qman_alloc_pool(&pool);
 758
 759                 if (!ret)
 760                         rx_pool_channel = pool;
 761         }
 762         spin_unlock(&rx_pool_channel_init);
 763         if (!rx_pool_channel)
 764                 return -ENOMEM;
 765         return rx_pool_channel;
 766 }
 767
 768 static void dpaa_release_channel(void)
 769 {
 770         qman_release_pool(rx_pool_channel);
 771 }
 772
 773 static void dpaa_eth_add_channel(u16 channel)
 774 {
 775         u32 pool = QM_SDQCR_CHANNELS_POOL_CONV(channel);
 776         const cpumask_t *cpus = qman_affine_cpus();
 777         struct qman_portal *portal;
 778         int cpu;
 779
 780         for_each_cpu(cpu, cpus) {
 781                 portal = qman_get_affine_portal(cpu);
 782                 qman_p_static_dequeue_add(portal, pool);
 783         }
 784 }
 785
 786 /* Congestion group state change notification callback.
 787  * Stops the device's egress queues while they are congested and
 788  * wakes them upon exiting congested state.
 789  * Also updates some CGR-related stats.
 790  */
 791 static void dpaa_eth_cgscn(struct qman_portal *qm, struct qman_cgr *cgr,
 792                            int congested)
 793 {
 794         struct dpaa_priv *priv = (struct dpaa_priv *)container_of(cgr,
 795                 struct dpaa_priv, cgr_data.cgr);
 796
 797         if (congested) {
 798                 priv->cgr_data.congestion_start_jiffies = jiffies;
 799                 netif_tx_stop_all_queues(priv->net_dev);
 800                 priv->cgr_data.cgr_congested_count++;
 801         } else {
 802                 priv->cgr_data.congested_jiffies +=
 803                         (jiffies - priv->cgr_data.congestion_start_jiffies);
 804                 netif_tx_wake_all_queues(priv->net_dev);
 805         }
 806 }
 807
 808 static int dpaa_eth_cgr_init(struct dpaa_priv *priv)
 809 {
 810         struct qm_mcc_initcgr initcgr;
 811         u32 cs_th;
 812         int err;
 813
 814         err = qman_alloc_cgrid(&priv->cgr_data.cgr.cgrid);
 815         if (err < 0) {
 816                 if (netif_msg_drv(priv))
 817                         pr_err("%s: Error %d allocating CGR ID\n",
 818                                __func__, err);
 819                 goto out_error;
 820         }
 821         priv->cgr_data.cgr.cb = dpaa_eth_cgscn;
 822
 823         /* Enable Congestion State Change Notifications and CS taildrop */
 824         memset(&initcgr, 0, sizeof(initcgr));
 825         initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES);
 826         initcgr.cgr.cscn_en = QM_CGR_EN;
 827
 828         /* Set different thresholds based on the MAC speed.
 829          * This may turn suboptimal if the MAC is reconfigured at a speed
 830          * lower than its max, e.g. if a dTSEC later negotiates a 100Mbps link.
 831          * In such cases, we ought to reconfigure the threshold, too.
 832          */
 833         if (priv->mac_dev->if_support & SUPPORTED_10000baseT_Full)
 834                 cs_th = DPAA_CS_THRESHOLD_10G;
 835         else
 836                 cs_th = DPAA_CS_THRESHOLD_1G;
 837         qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1);
 838
 839         initcgr.we_mask |= cpu_to_be16(QM_CGR_WE_CSTD_EN);
 840         initcgr.cgr.cstd_en = QM_CGR_EN;
 841
 842         err = qman_create_cgr(&priv->cgr_data.cgr, QMAN_CGR_FLAG_USE_INIT,
 843                               &initcgr);
 844         if (err < 0) {
 845                 if (netif_msg_drv(priv))
 846                         pr_err("%s: Error %d creating CGR with ID %d\n",
 847                                __func__, err, priv->cgr_data.cgr.cgrid);
 848                 qman_release_cgrid(priv->cgr_data.cgr.cgrid);
 849                 goto out_error;
 850         }
 851         if (netif_msg_drv(priv))
 852                 pr_debug("Created CGR %d for netdev with hwaddr %pM on QMan channel %d\n",
 853                          priv->cgr_data.cgr.cgrid, priv->mac_dev->addr,
 854                          priv->cgr_data.cgr.chan);
 855
 856 out_error:
 857         return err;
 858 }
 859
 860 static inline void dpaa_setup_ingress(const struct dpaa_priv *priv,
 861                                       struct dpaa_fq *fq,
 862                                       const struct qman_fq *template)
 863 {
 864         fq->fq_base = *template;
 865         fq->net_dev = priv->net_dev;
 866
 867         fq->flags = QMAN_FQ_FLAG_NO_ENQUEUE;
 868         fq->channel = priv->channel;
 869 }
 870
 871 static inline void dpaa_setup_egress(const struct dpaa_priv *priv,
 872                                      struct dpaa_fq *fq,
 873                                      struct fman_port *port,
 874                                      const struct qman_fq *template)
 875 {
 876         fq->fq_base = *template;
 877         fq->net_dev = priv->net_dev;
 878
 879         if (port) {
 880                 fq->flags = QMAN_FQ_FLAG_TO_DCPORTAL;
 881                 fq->channel = (u16)fman_port_get_qman_channel_id(port);
 882         } else {
 883                 fq->flags = QMAN_FQ_FLAG_NO_MODIFY;
 884         }
 885 }
 886
 887 static void dpaa_fq_setup(struct dpaa_priv *priv,
 888                           const struct dpaa_fq_cbs *fq_cbs,
 889                           struct fman_port *tx_port)
 890 {
 891         int egress_cnt = 0, conf_cnt = 0, num_portals = 0, portal_cnt = 0, cpu;
 892         const cpumask_t *affine_cpus = qman_affine_cpus();
 893         u16 channels[NR_CPUS];
 894         struct dpaa_fq *fq;
 895
 896         for_each_cpu(cpu, affine_cpus)
 897                 channels[num_portals++] = qman_affine_channel(cpu);
 898
 899         if (num_portals == 0)
 900                 dev_err(priv->net_dev->dev.parent,
 901                         "No Qman software (affine) channels found");
 902
 903         /* Initialize each FQ in the list */
 904         list_for_each_entry(fq, &priv->dpaa_fq_list, list) {
 905                 switch (fq->fq_type) {
 906                 case FQ_TYPE_RX_DEFAULT:
 907                         dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq);
 908                         break;
 909                 case FQ_TYPE_RX_ERROR:
 910                         dpaa_setup_ingress(priv, fq, &fq_cbs->rx_errq);
 911                         break;
 912                 case FQ_TYPE_RX_PCD:
 913                         if (!num_portals)
 914                                 continue;
 915                         dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq);
 916                         fq->channel = channels[portal_cnt++ % num_portals];
 917                         break;
 918                 case FQ_TYPE_TX:
 919                         dpaa_setup_egress(priv, fq, tx_port,
 920                                           &fq_cbs->egress_ern);
 921                         /* If we have more Tx queues than the number of cores,
 922                          * just ignore the extra ones.
 923                          */
 924                         if (egress_cnt < DPAA_ETH_TXQ_NUM)
 925                                 priv->egress_fqs[egress_cnt++] = &fq->fq_base;
 926                         break;
 927                 case FQ_TYPE_TX_CONF_MQ:
 928                         priv->conf_fqs[conf_cnt++] = &fq->fq_base;
 929                         /* fall through */
 930                 case FQ_TYPE_TX_CONFIRM:
 931                         dpaa_setup_ingress(priv, fq, &fq_cbs->tx_defq);
 932                         break;
 933                 case FQ_TYPE_TX_ERROR:
 934                         dpaa_setup_ingress(priv, fq, &fq_cbs->tx_errq);
 935                         break;
 936                 default:
 937                         dev_warn(priv->net_dev->dev.parent,
 938                                  "Unknown FQ type detected!\n");
 939                         break;
 940                 }
 941         }
 942
 943          /* Make sure all CPUs receive a corresponding Tx queue. */
 944         while (egress_cnt < DPAA_ETH_TXQ_NUM) {
 945                 list_for_each_entry(fq, &priv->dpaa_fq_list, list) {
 946                         if (fq->fq_type != FQ_TYPE_TX)
 947                                 continue;
 948                         priv->egress_fqs[egress_cnt++] = &fq->fq_base;
 949                         if (egress_cnt == DPAA_ETH_TXQ_NUM)
 950                                 break;
 951                 }
 952         }
 953 }
 954
 955 static inline int dpaa_tx_fq_to_id(const struct dpaa_priv *priv,
 956                                    struct qman_fq *tx_fq)
 957 {
 958         int i;
 959
 960         for (i = 0; i < DPAA_ETH_TXQ_NUM; i++)
 961                 if (priv->egress_fqs[i] == tx_fq)
 962                         return i;
 963
 964         return -EINVAL;
 965 }
 966
 967 static int dpaa_fq_init(struct dpaa_fq *dpaa_fq, bool td_enable)
 968 {
 969         const struct dpaa_priv  *priv;
 970         struct qman_fq *confq = NULL;
 971         struct qm_mcc_initfq initfq;
 972         struct device *dev;
 973         struct qman_fq *fq;
 974         int queue_id;
 975         int err;
 976
 977         priv = netdev_priv(dpaa_fq->net_dev);
 978         dev = dpaa_fq->net_dev->dev.parent;
 979
 980         if (dpaa_fq->fqid == 0)
 981                 dpaa_fq->flags |= QMAN_FQ_FLAG_DYNAMIC_FQID;
 982
 983         dpaa_fq->init = !(dpaa_fq->flags & QMAN_FQ_FLAG_NO_MODIFY);
 984
 985         err = qman_create_fq(dpaa_fq->fqid, dpaa_fq->flags, &dpaa_fq->fq_base);
 986         if (err) {
 987                 dev_err(dev, "qman_create_fq() failed\n");
 988                 return err;
 989         }
 990         fq = &dpaa_fq->fq_base;
 991
 992         if (dpaa_fq->init) {
 993                 memset(&initfq, 0, sizeof(initfq));
 994
 995                 initfq.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL);
 996                 /* Note: we may get to keep an empty FQ in cache */
 997                 initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_PREFERINCACHE);
 998
 999                 /* Try to reduce the number of portal interrupts for
1000                  * Tx Confirmation FQs.
1001                  */
1002                 if (dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM)
1003                         initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_AVOIDBLOCK);
1004
1005                 /* FQ placement */
1006                 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_DESTWQ);
1007
1008                 qm_fqd_set_destwq(&initfq.fqd, dpaa_fq->channel, dpaa_fq->wq);
1009
1010                 /* Put all egress queues in a congestion group of their own.
1011                  * Sensu stricto, the Tx confirmation queues are Rx FQs,
1012                  * rather than Tx - but they nonetheless account for the
1013                  * memory footprint on behalf of egress traffic. We therefore
1014                  * place them in the netdev's CGR, along with the Tx FQs.
1015                  */
1016                 if (dpaa_fq->fq_type == FQ_TYPE_TX ||
1017                     dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM ||
1018                     dpaa_fq->fq_type == FQ_TYPE_TX_CONF_MQ) {
1019                         initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID);
1020                         initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_CGE);
1021                         initfq.fqd.cgid = (u8)priv->cgr_data.cgr.cgrid;
1022                         /* Set a fixed overhead accounting, in an attempt to
1023                          * reduce the impact of fixed-size skb shells and the
1024                          * driver's needed headroom on system memory. This is
1025                          * especially the case when the egress traffic is
1026                          * composed of small datagrams.
1027                          * Unfortunately, QMan's OAL value is capped to an
1028                          * insufficient value, but even that is better than
1029                          * no overhead accounting at all.
1030                          */
1031                         initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC);
1032                         qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG);
1033                         qm_fqd_set_oal(&initfq.fqd,
1034                                        min(sizeof(struct sk_buff) +
1035                                        priv->tx_headroom,
1036                                        (size_t)FSL_QMAN_MAX_OAL));
1037                 }
1038
1039                 if (td_enable) {
1040                         initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_TDTHRESH);
1041                         qm_fqd_set_taildrop(&initfq.fqd, DPAA_FQ_TD, 1);
1042                         initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_TDE);
1043                 }
1044
1045                 if (dpaa_fq->fq_type == FQ_TYPE_TX) {
1046                         queue_id = dpaa_tx_fq_to_id(priv, &dpaa_fq->fq_base);
1047                         if (queue_id >= 0)
1048                                 confq = priv->conf_fqs[queue_id];
1049                         if (confq) {
1050                                 initfq.we_mask |=
1051                                         cpu_to_be16(QM_INITFQ_WE_CONTEXTA);
1052                         /* ContextA: OVOM=1(use contextA2 bits instead of ICAD)
1053                          *           A2V=1 (contextA A2 field is valid)
1054                          *           A0V=1 (contextA A0 field is valid)
1055                          *           B0V=1 (contextB field is valid)
1056                          * ContextA A2: EBD=1 (deallocate buffers inside FMan)
1057                          * ContextB B0(ASPID): 0 (absolute Virtual Storage ID)
1058                          */
1059                                 qm_fqd_context_a_set64(&initfq.fqd,
1060                                                        0x1e00000080000000ULL);
1061                         }
1062                 }
1063
1064                 /* Put all the ingress queues in our "ingress CGR". */
1065                 if (priv->use_ingress_cgr &&
1066                     (dpaa_fq->fq_type == FQ_TYPE_RX_DEFAULT ||
1067                      dpaa_fq->fq_type == FQ_TYPE_RX_ERROR ||
1068                      dpaa_fq->fq_type == FQ_TYPE_RX_PCD)) {
1069                         initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID);
1070                         initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_CGE);
1071                         initfq.fqd.cgid = (u8)priv->ingress_cgr.cgrid;
1072                         /* Set a fixed overhead accounting, just like for the
1073                          * egress CGR.
1074                          */
1075                         initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC);
1076                         qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG);
1077                         qm_fqd_set_oal(&initfq.fqd,
1078                                        min(sizeof(struct sk_buff) +
1079                                        priv->tx_headroom,
1080                                        (size_t)FSL_QMAN_MAX_OAL));
1081                 }
1082
1083                 /* Initialization common to all ingress queues */
1084                 if (dpaa_fq->flags & QMAN_FQ_FLAG_NO_ENQUEUE) {
1085                         initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CONTEXTA);
1086                         initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_HOLDACTIVE |
1087                                                 QM_FQCTRL_CTXASTASHING);
1088                         initfq.fqd.context_a.stashing.exclusive =
1089                                 QM_STASHING_EXCL_DATA | QM_STASHING_EXCL_CTX |
1090                                 QM_STASHING_EXCL_ANNOTATION;
1091                         qm_fqd_set_stashing(&initfq.fqd, 1, 2,
1092                                             DIV_ROUND_UP(sizeof(struct qman_fq),
1093                                                          64));
1094                 }
1095
1096                 err = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &initfq);
1097                 if (err < 0) {
1098                         dev_err(dev, "qman_init_fq(%u) = %d\n",
1099                                 qman_fq_fqid(fq), err);
1100                         qman_destroy_fq(fq);
1101                         return err;
1102                 }
1103         }
1104
1105         dpaa_fq->fqid = qman_fq_fqid(fq);
1106
1107         return 0;
1108 }
1109
1110 static int dpaa_fq_free_entry(struct device *dev, struct qman_fq *fq)
1111 {
1112         const struct dpaa_priv  *priv;
1113         struct dpaa_fq *dpaa_fq;
1114         int err, error;
1115
1116         err = 0;
1117
1118         dpaa_fq = container_of(fq, struct dpaa_fq, fq_base);
1119         priv = netdev_priv(dpaa_fq->net_dev);
1120
1121         if (dpaa_fq->init) {
1122                 err = qman_retire_fq(fq, NULL);
1123                 if (err < 0 && netif_msg_drv(priv))
1124                         dev_err(dev, "qman_retire_fq(%u) = %d\n",
1125                                 qman_fq_fqid(fq), err);
1126
1127                 error = qman_oos_fq(fq);
1128                 if (error < 0 && netif_msg_drv(priv)) {
1129                         dev_err(dev, "qman_oos_fq(%u) = %d\n",
1130                                 qman_fq_fqid(fq), error);
1131                         if (err >= 0)
1132                                 err = error;
1133                 }
1134         }
1135
1136         qman_destroy_fq(fq);
1137         list_del(&dpaa_fq->list);
1138
1139         return err;
1140 }
1141
1142 static int dpaa_fq_free(struct device *dev, struct list_head *list)
1143 {
1144         struct dpaa_fq *dpaa_fq, *tmp;
1145         int err, error;
1146
1147         err = 0;
1148         list_for_each_entry_safe(dpaa_fq, tmp, list, list) {
1149                 error = dpaa_fq_free_entry(dev, (struct qman_fq *)dpaa_fq);
1150                 if (error < 0 && err >= 0)
1151                         err = error;
1152         }
1153
1154         return err;
1155 }
1156
1157 static int dpaa_eth_init_tx_port(struct fman_port *port, struct dpaa_fq *errq,
1158                                  struct dpaa_fq *defq,
1159                                  struct dpaa_buffer_layout *buf_layout)
1160 {
1161         struct fman_buffer_prefix_content buf_prefix_content;
1162         struct fman_port_params params;
1163         int err;
1164
1165         memset(&params, 0, sizeof(params));
1166         memset(&buf_prefix_content, 0, sizeof(buf_prefix_content));
1167
1168         buf_prefix_content.priv_data_size = buf_layout->priv_data_size;
1169         buf_prefix_content.pass_prs_result = true;
1170         buf_prefix_content.pass_hash_result = true;
1171         buf_prefix_content.pass_time_stamp = false;
1172         buf_prefix_content.data_align = DPAA_FD_DATA_ALIGNMENT;
1173
1174         params.specific_params.non_rx_params.err_fqid = errq->fqid;
1175         params.specific_params.non_rx_params.dflt_fqid = defq->fqid;
1176
1177         err = fman_port_config(port, &params);
1178         if (err) {
1179                 pr_err("%s: fman_port_config failed\n", __func__);
1180                 return err;
1181         }
1182
1183         err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content);
1184         if (err) {
1185                 pr_err("%s: fman_port_cfg_buf_prefix_content failed\n",
1186                        __func__);
1187                 return err;
1188         }
1189
1190         err = fman_port_init(port);
1191         if (err)
1192                 pr_err("%s: fm_port_init failed\n", __func__);
1193
1194         return err;
1195 }
1196
1197 static int dpaa_eth_init_rx_port(struct fman_port *port, struct dpaa_bp **bps,
1198                                  size_t count, struct dpaa_fq *errq,
1199                                  struct dpaa_fq *defq, struct dpaa_fq *pcdq,
1200                                  struct dpaa_buffer_layout *buf_layout)
1201 {
1202         struct fman_buffer_prefix_content buf_prefix_content;
1203         struct fman_port_rx_params *rx_p;
1204         struct fman_port_params params;
1205         int i, err;
1206
1207         memset(&params, 0, sizeof(params));
1208         memset(&buf_prefix_content, 0, sizeof(buf_prefix_content));
1209
1210         buf_prefix_content.priv_data_size = buf_layout->priv_data_size;
1211         buf_prefix_content.pass_prs_result = true;
1212         buf_prefix_content.pass_hash_result = true;
1213         buf_prefix_content.pass_time_stamp = false;
1214         buf_prefix_content.data_align = DPAA_FD_DATA_ALIGNMENT;
1215
1216         rx_p = &params.specific_params.rx_params;
1217         rx_p->err_fqid = errq->fqid;
1218         rx_p->dflt_fqid = defq->fqid;
1219         if (pcdq) {
1220                 rx_p->pcd_base_fqid = pcdq->fqid;
1221                 rx_p->pcd_fqs_count = DPAA_ETH_PCD_RXQ_NUM;
1222         }
1223
1224         count = min(ARRAY_SIZE(rx_p->ext_buf_pools.ext_buf_pool), count);
1225         rx_p->ext_buf_pools.num_of_pools_used = (u8)count;
1226         for (i = 0; i < count; i++) {
1227                 rx_p->ext_buf_pools.ext_buf_pool[i].id =  bps[i]->bpid;
1228                 rx_p->ext_buf_pools.ext_buf_pool[i].size = (u16)bps[i]->size;
1229         }
1230
1231         err = fman_port_config(port, &params);
1232         if (err) {
1233                 pr_err("%s: fman_port_config failed\n", __func__);
1234                 return err;
1235         }
1236
1237         err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content);
1238         if (err) {
1239                 pr_err("%s: fman_port_cfg_buf_prefix_content failed\n",
1240                        __func__);
1241                 return err;
1242         }
1243
1244         err = fman_port_init(port);
1245         if (err)
1246                 pr_err("%s: fm_port_init failed\n", __func__);
1247
1248         return err;
1249 }
1250
1251 static int dpaa_eth_init_ports(struct mac_device *mac_dev,
1252                                struct dpaa_bp **bps, size_t count,
1253                                struct fm_port_fqs *port_fqs,
1254                                struct dpaa_buffer_layout *buf_layout,
1255                                struct device *dev)
1256 {
1257         struct fman_port *rxport = mac_dev->port[RX];
1258         struct fman_port *txport = mac_dev->port[TX];
1259         int err;
1260
1261         err = dpaa_eth_init_tx_port(txport, port_fqs->tx_errq,
1262                                     port_fqs->tx_defq, &buf_layout[TX]);
1263         if (err)
1264                 return err;
1265
1266         err = dpaa_eth_init_rx_port(rxport, bps, count, port_fqs->rx_errq,
1267                                     port_fqs->rx_defq, port_fqs->rx_pcdq,
1268                                     &buf_layout[RX]);
1269
1270         return err;
1271 }
1272
1273 static int dpaa_bman_release(const struct dpaa_bp *dpaa_bp,
1274                              struct bm_buffer *bmb, int cnt)
1275 {
1276         int err;
1277
1278         err = bman_release(dpaa_bp->pool, bmb, cnt);
1279         /* Should never occur, address anyway to avoid leaking the buffers */
1280         if (unlikely(WARN_ON(err)) && dpaa_bp->free_buf_cb)
1281                 while (cnt-- > 0)
1282                         dpaa_bp->free_buf_cb(dpaa_bp, &bmb[cnt]);
1283
1284         return cnt;
1285 }
1286
1287 static void dpaa_release_sgt_members(struct qm_sg_entry *sgt)
1288 {
1289         struct bm_buffer bmb[DPAA_BUFF_RELEASE_MAX];
1290         struct dpaa_bp *dpaa_bp;
1291         int i = 0, j;
1292
1293         memset(bmb, 0, sizeof(bmb));
1294
1295         do {
1296                 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1297                 if (!dpaa_bp)
1298                         return;
1299
1300                 j = 0;
1301                 do {
1302                         WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
1303
1304                         bm_buffer_set64(&bmb[j], qm_sg_entry_get64(&sgt[i]));
1305
1306                         j++; i++;
1307                 } while (j < ARRAY_SIZE(bmb) &&
1308                                 !qm_sg_entry_is_final(&sgt[i - 1]) &&
1309                                 sgt[i - 1].bpid == sgt[i].bpid);
1310
1311                 dpaa_bman_release(dpaa_bp, bmb, j);
1312         } while (!qm_sg_entry_is_final(&sgt[i - 1]));
1313 }
1314
1315 static void dpaa_fd_release(const struct net_device *net_dev,
1316                             const struct qm_fd *fd)
1317 {
1318         struct qm_sg_entry *sgt;
1319         struct dpaa_bp *dpaa_bp;
1320         struct bm_buffer bmb;
1321         dma_addr_t addr;
1322         void *vaddr;
1323
1324         bmb.data = 0;
1325         bm_buffer_set64(&bmb, qm_fd_addr(fd));
1326
1327         dpaa_bp = dpaa_bpid2pool(fd->bpid);
1328         if (!dpaa_bp)
1329                 return;
1330
1331         if (qm_fd_get_format(fd) == qm_fd_sg) {
1332                 vaddr = phys_to_virt(qm_fd_addr(fd));
1333                 sgt = vaddr + qm_fd_get_offset(fd);
1334
1335                 dma_unmap_single(dpaa_bp->dev, qm_fd_addr(fd), dpaa_bp->size,
1336                                  DMA_FROM_DEVICE);
1337
1338                 dpaa_release_sgt_members(sgt);
1339
1340                 addr = dma_map_single(dpaa_bp->dev, vaddr, dpaa_bp->size,
1341                                       DMA_FROM_DEVICE);
1342                 if (dma_mapping_error(dpaa_bp->dev, addr)) {
1343                         dev_err(dpaa_bp->dev, "DMA mapping failed");
1344                         return;
1345                 }
1346                 bm_buffer_set64(&bmb, addr);
1347         }
1348
1349         dpaa_bman_release(dpaa_bp, &bmb, 1);
1350 }
1351
1352 static void count_ern(struct dpaa_percpu_priv *percpu_priv,
1353                       const union qm_mr_entry *msg)
1354 {
1355         switch (msg->ern.rc & QM_MR_RC_MASK) {
1356         case QM_MR_RC_CGR_TAILDROP:
1357                 percpu_priv->ern_cnt.cg_tdrop++;
1358                 break;
1359         case QM_MR_RC_WRED:
1360                 percpu_priv->ern_cnt.wred++;
1361                 break;
1362         case QM_MR_RC_ERROR:
1363                 percpu_priv->ern_cnt.err_cond++;
1364                 break;
1365         case QM_MR_RC_ORPWINDOW_EARLY:
1366                 percpu_priv->ern_cnt.early_window++;
1367                 break;
1368         case QM_MR_RC_ORPWINDOW_LATE:
1369                 percpu_priv->ern_cnt.late_window++;
1370                 break;
1371         case QM_MR_RC_FQ_TAILDROP:
1372                 percpu_priv->ern_cnt.fq_tdrop++;
1373                 break;
1374         case QM_MR_RC_ORPWINDOW_RETIRED:
1375                 percpu_priv->ern_cnt.fq_retired++;
1376                 break;
1377         case QM_MR_RC_ORP_ZERO:
1378                 percpu_priv->ern_cnt.orp_zero++;
1379                 break;
1380         }
1381 }
1382
1383 /* Turn on HW checksum computation for this outgoing frame.
1384  * If the current protocol is not something we support in this regard
1385  * (or if the stack has already computed the SW checksum), we do nothing.
1386  *
1387  * Returns 0 if all goes well (or HW csum doesn't apply), and a negative value
1388  * otherwise.
1389  *
1390  * Note that this function may modify the fd->cmd field and the skb data buffer
1391  * (the Parse Results area).
1392  */
1393 static int dpaa_enable_tx_csum(struct dpaa_priv *priv,
1394                                struct sk_buff *skb,
1395                                struct qm_fd *fd,
1396                                char *parse_results)
1397 {
1398         struct fman_prs_result *parse_result;
1399         u16 ethertype = ntohs(skb->protocol);
1400         struct ipv6hdr *ipv6h = NULL;
1401         struct iphdr *iph;
1402         int retval = 0;
1403         u8 l4_proto;
1404
1405         if (skb->ip_summed != CHECKSUM_PARTIAL)
1406                 return 0;
1407
1408         /* Note: L3 csum seems to be already computed in sw, but we can't choose
1409          * L4 alone from the FM configuration anyway.
1410          */
1411
1412         /* Fill in some fields of the Parse Results array, so the FMan
1413          * can find them as if they came from the FMan Parser.
1414          */
1415         parse_result = (struct fman_prs_result *)parse_results;
1416
1417         /* If we're dealing with VLAN, get the real Ethernet type */
1418         if (ethertype == ETH_P_8021Q) {
1419                 /* We can't always assume the MAC header is set correctly
1420                  * by the stack, so reset to beginning of skb->data
1421                  */
1422                 skb_reset_mac_header(skb);
1423                 ethertype = ntohs(vlan_eth_hdr(skb)->h_vlan_encapsulated_proto);
1424         }
1425
1426         /* Fill in the relevant L3 parse result fields
1427          * and read the L4 protocol type
1428          */
1429         switch (ethertype) {
1430         case ETH_P_IP:
1431                 parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV4);
1432                 iph = ip_hdr(skb);
1433                 WARN_ON(!iph);
1434                 l4_proto = iph->protocol;
1435                 break;
1436         case ETH_P_IPV6:
1437                 parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV6);
1438                 ipv6h = ipv6_hdr(skb);
1439                 WARN_ON(!ipv6h);
1440                 l4_proto = ipv6h->nexthdr;
1441                 break;
1442         default:
1443                 /* We shouldn't even be here */
1444                 if (net_ratelimit())
1445                         netif_alert(priv, tx_err, priv->net_dev,
1446                                     "Can't compute HW csum for L3 proto 0x%x\n",
1447                                     ntohs(skb->protocol));
1448                 retval = -EIO;
1449                 goto return_error;
1450         }
1451
1452         /* Fill in the relevant L4 parse result fields */
1453         switch (l4_proto) {
1454         case IPPROTO_UDP:
1455                 parse_result->l4r = FM_L4_PARSE_RESULT_UDP;
1456                 break;
1457         case IPPROTO_TCP:
1458                 parse_result->l4r = FM_L4_PARSE_RESULT_TCP;
1459                 break;
1460         default:
1461                 if (net_ratelimit())
1462                         netif_alert(priv, tx_err, priv->net_dev,
1463                                     "Can't compute HW csum for L4 proto 0x%x\n",
1464                                     l4_proto);
1465                 retval = -EIO;
1466                 goto return_error;
1467         }
1468
1469         /* At index 0 is IPOffset_1 as defined in the Parse Results */
1470         parse_result->ip_off[0] = (u8)skb_network_offset(skb);
1471         parse_result->l4_off = (u8)skb_transport_offset(skb);
1472
1473         /* Enable L3 (and L4, if TCP or UDP) HW checksum. */
1474         fd->cmd |= cpu_to_be32(FM_FD_CMD_RPD | FM_FD_CMD_DTC);
1475
1476         /* On P1023 and similar platforms fd->cmd interpretation could
1477          * be disabled by setting CONTEXT_A bit ICMD; currently this bit
1478          * is not set so we do not need to check; in the future, if/when
1479          * using context_a we need to check this bit
1480          */
1481
1482 return_error:
1483         return retval;
1484 }
1485
1486 static int dpaa_bp_add_8_bufs(const struct dpaa_bp *dpaa_bp)
1487 {
1488         struct device *dev = dpaa_bp->dev;
1489         struct bm_buffer bmb[8];
1490         dma_addr_t addr;
1491         void *new_buf;
1492         u8 i;
1493
1494         for (i = 0; i < 8; i++) {
1495                 new_buf = netdev_alloc_frag(dpaa_bp->raw_size);
1496                 if (unlikely(!new_buf)) {
1497                         dev_err(dev, "netdev_alloc_frag() failed, size %zu\n",
1498                                 dpaa_bp->raw_size);
1499                         goto release_previous_buffs;
1500                 }
1501                 new_buf = PTR_ALIGN(new_buf, SMP_CACHE_BYTES);
1502
1503                 addr = dma_map_single(dev, new_buf,
1504                                       dpaa_bp->size, DMA_FROM_DEVICE);
1505                 if (unlikely(dma_mapping_error(dev, addr))) {
1506                         dev_err(dpaa_bp->dev, "DMA map failed");
1507                         goto release_previous_buffs;
1508                 }
1509
1510                 bmb[i].data = 0;
1511                 bm_buffer_set64(&bmb[i], addr);
1512         }
1513
1514 release_bufs:
1515         return dpaa_bman_release(dpaa_bp, bmb, i);
1516
1517 release_previous_buffs:
1518         WARN_ONCE(1, "dpaa_eth: failed to add buffers on Rx\n");
1519
1520         bm_buffer_set64(&bmb[i], 0);
1521         /* Avoid releasing a completely null buffer; bman_release() requires
1522          * at least one buffer.
1523          */
1524         if (likely(i))
1525                 goto release_bufs;
1526
1527         return 0;
1528 }
1529
1530 static int dpaa_bp_seed(struct dpaa_bp *dpaa_bp)
1531 {
1532         int i;
1533
1534         /* Give each CPU an allotment of "config_count" buffers */
1535         for_each_possible_cpu(i) {
1536                 int *count_ptr = per_cpu_ptr(dpaa_bp->percpu_count, i);
1537                 int j;
1538
1539                 /* Although we access another CPU's counters here
1540                  * we do it at boot time so it is safe
1541                  */
1542                 for (j = 0; j < dpaa_bp->config_count; j += 8)
1543                         *count_ptr += dpaa_bp_add_8_bufs(dpaa_bp);
1544         }
1545         return 0;
1546 }
1547
1548 /* Add buffers/(pages) for Rx processing whenever bpool count falls below
1549  * REFILL_THRESHOLD.
1550  */
1551 static int dpaa_eth_refill_bpool(struct dpaa_bp *dpaa_bp, int *countptr)
1552 {
1553         int count = *countptr;
1554         int new_bufs;
1555
1556         if (unlikely(count < FSL_DPAA_ETH_REFILL_THRESHOLD)) {
1557                 do {
1558                         new_bufs = dpaa_bp_add_8_bufs(dpaa_bp);
1559                         if (unlikely(!new_bufs)) {
1560                                 /* Avoid looping forever if we've temporarily
1561                                  * run out of memory. We'll try again at the
1562                                  * next NAPI cycle.
1563                                  */
1564                                 break;
1565                         }
1566                         count += new_bufs;
1567                 } while (count < FSL_DPAA_ETH_MAX_BUF_COUNT);
1568
1569                 *countptr = count;
1570                 if (unlikely(count < FSL_DPAA_ETH_MAX_BUF_COUNT))
1571                         return -ENOMEM;
1572         }
1573
1574         return 0;
1575 }
1576
1577 static int dpaa_eth_refill_bpools(struct dpaa_priv *priv)
1578 {
1579         struct dpaa_bp *dpaa_bp;
1580         int *countptr;
1581         int res, i;
1582
1583         for (i = 0; i < DPAA_BPS_NUM; i++) {
1584                 dpaa_bp = priv->dpaa_bps[i];
1585                 if (!dpaa_bp)
1586                         return -EINVAL;
1587                 countptr = this_cpu_ptr(dpaa_bp->percpu_count);
1588                 res  = dpaa_eth_refill_bpool(dpaa_bp, countptr);
1589                 if (res)
1590                         return res;
1591         }
1592         return 0;
1593 }
1594
1595 /* Cleanup function for outgoing frame descriptors that were built on Tx path,
1596  * either contiguous frames or scatter/gather ones.
1597  * Skb freeing is not handled here.
1598  *
1599  * This function may be called on error paths in the Tx function, so guard
1600  * against cases when not all fd relevant fields were filled in.
1601  *
1602  * Return the skb backpointer, since for S/G frames the buffer containing it
1603  * gets freed here.
1604  */
1605 static struct sk_buff *dpaa_cleanup_tx_fd(const struct dpaa_priv *priv,
1606                                           const struct qm_fd *fd)
1607 {
1608         const enum dma_data_direction dma_dir = DMA_TO_DEVICE;
1609         struct device *dev = priv->net_dev->dev.parent;
1610         dma_addr_t addr = qm_fd_addr(fd);
1611         const struct qm_sg_entry *sgt;
1612         struct sk_buff **skbh, *skb;
1613         int nr_frags, i;
1614
1615         skbh = (struct sk_buff **)phys_to_virt(addr);
1616         skb = *skbh;
1617
1618         if (unlikely(qm_fd_get_format(fd) == qm_fd_sg)) {
1619                 nr_frags = skb_shinfo(skb)->nr_frags;
1620                 dma_unmap_single(dev, addr, qm_fd_get_offset(fd) +
1621                                  sizeof(struct qm_sg_entry) * (1 + nr_frags),
1622                                  dma_dir);
1623
1624                 /* The sgt buffer has been allocated with netdev_alloc_frag(),
1625                  * it's from lowmem.
1626                  */
1627                 sgt = phys_to_virt(addr + qm_fd_get_offset(fd));
1628
1629                 /* sgt[0] is from lowmem, was dma_map_single()-ed */
1630                 dma_unmap_single(dev, qm_sg_addr(&sgt[0]),
1631                                  qm_sg_entry_get_len(&sgt[0]), dma_dir);
1632
1633                 /* remaining pages were mapped with skb_frag_dma_map() */
1634                 for (i = 1; i < nr_frags; i++) {
1635                         WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
1636
1637                         dma_unmap_page(dev, qm_sg_addr(&sgt[i]),
1638                                        qm_sg_entry_get_len(&sgt[i]), dma_dir);
1639                 }
1640
1641                 /* Free the page frag that we allocated on Tx */
1642                 skb_free_frag(phys_to_virt(addr));
1643         } else {
1644                 dma_unmap_single(dev, addr,
1645                                  skb_tail_pointer(skb) - (u8 *)skbh, dma_dir);
1646         }
1647
1648         return skb;
1649 }
1650
1651 static u8 rx_csum_offload(const struct dpaa_priv *priv, const struct qm_fd *fd)
1652 {
1653         /* The parser has run and performed L4 checksum validation.
1654          * We know there were no parser errors (and implicitly no
1655          * L4 csum error), otherwise we wouldn't be here.
1656          */
1657         if ((priv->net_dev->features & NETIF_F_RXCSUM) &&
1658             (be32_to_cpu(fd->status) & FM_FD_STAT_L4CV))
1659                 return CHECKSUM_UNNECESSARY;
1660
1661         /* We're here because either the parser didn't run or the L4 checksum
1662          * was not verified. This may include the case of a UDP frame with
1663          * checksum zero or an L4 proto other than TCP/UDP
1664          */
1665         return CHECKSUM_NONE;
1666 }
1667
1668 /* Build a linear skb around the received buffer.
1669  * We are guaranteed there is enough room at the end of the data buffer to
1670  * accommodate the shared info area of the skb.
1671  */
1672 static struct sk_buff *contig_fd_to_skb(const struct dpaa_priv *priv,
1673                                         const struct qm_fd *fd)
1674 {
1675         ssize_t fd_off = qm_fd_get_offset(fd);
1676         dma_addr_t addr = qm_fd_addr(fd);
1677         struct dpaa_bp *dpaa_bp;
1678         struct sk_buff *skb;
1679         void *vaddr;
1680
1681         vaddr = phys_to_virt(addr);
1682         WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES));
1683
1684         dpaa_bp = dpaa_bpid2pool(fd->bpid);
1685         if (!dpaa_bp)
1686                 goto free_buffer;
1687
1688         skb = build_skb(vaddr, dpaa_bp->size +
1689                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info)));
1690         if (unlikely(!skb)) {
1691                 WARN_ONCE(1, "Build skb failure on Rx\n");
1692                 goto free_buffer;
1693         }
1694         WARN_ON(fd_off != priv->rx_headroom);
1695         skb_reserve(skb, fd_off);
1696         skb_put(skb, qm_fd_get_length(fd));
1697
1698         skb->ip_summed = rx_csum_offload(priv, fd);
1699
1700         return skb;
1701
1702 free_buffer:
1703         skb_free_frag(vaddr);
1704         return NULL;
1705 }
1706
1707 /* Build an skb with the data of the first S/G entry in the linear portion and
1708  * the rest of the frame as skb fragments.
1709  *
1710  * The page fragment holding the S/G Table is recycled here.
1711  */
1712 static struct sk_buff *sg_fd_to_skb(const struct dpaa_priv *priv,
1713                                     const struct qm_fd *fd)
1714 {
1715         ssize_t fd_off = qm_fd_get_offset(fd);
1716         dma_addr_t addr = qm_fd_addr(fd);
1717         const struct qm_sg_entry *sgt;
1718         struct page *page, *head_page;
1719         struct dpaa_bp *dpaa_bp;
1720         void *vaddr, *sg_vaddr;
1721         int frag_off, frag_len;
1722         struct sk_buff *skb;
1723         dma_addr_t sg_addr;
1724         int page_offset;
1725         unsigned int sz;
1726         int *count_ptr;
1727         int i;
1728
1729         vaddr = phys_to_virt(addr);
1730         WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES));
1731
1732         /* Iterate through the SGT entries and add data buffers to the skb */
1733         sgt = vaddr + fd_off;
1734         skb = NULL;
1735         for (i = 0; i < DPAA_SGT_MAX_ENTRIES; i++) {
1736                 /* Extension bit is not supported */
1737                 WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
1738
1739                 sg_addr = qm_sg_addr(&sgt[i]);
1740                 sg_vaddr = phys_to_virt(sg_addr);
1741                 WARN_ON(!IS_ALIGNED((unsigned long)sg_vaddr,
1742                                     SMP_CACHE_BYTES));
1743
1744                 /* We may use multiple Rx pools */
1745                 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1746                 if (!dpaa_bp)
1747                         goto free_buffers;
1748
1749                 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
1750                 dma_unmap_single(dpaa_bp->dev, sg_addr, dpaa_bp->size,
1751                                  DMA_FROM_DEVICE);
1752                 if (!skb) {
1753                         sz = dpaa_bp->size +
1754                                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
1755                         skb = build_skb(sg_vaddr, sz);
1756                         if (WARN_ON(unlikely(!skb)))
1757                                 goto free_buffers;
1758
1759                         skb->ip_summed = rx_csum_offload(priv, fd);
1760
1761                         /* Make sure forwarded skbs will have enough space
1762                          * on Tx, if extra headers are added.
1763                          */
1764                         WARN_ON(fd_off != priv->rx_headroom);
1765                         skb_reserve(skb, fd_off);
1766                         skb_put(skb, qm_sg_entry_get_len(&sgt[i]));
1767                 } else {
1768                         /* Not the first S/G entry; all data from buffer will
1769                          * be added in an skb fragment; fragment index is offset
1770                          * by one since first S/G entry was incorporated in the
1771                          * linear part of the skb.
1772                          *
1773                          * Caution: 'page' may be a tail page.
1774                          */
1775                         page = virt_to_page(sg_vaddr);
1776                         head_page = virt_to_head_page(sg_vaddr);
1777
1778                         /* Compute offset in (possibly tail) page */
1779                         page_offset = ((unsigned long)sg_vaddr &
1780                                         (PAGE_SIZE - 1)) +
1781                                 (page_address(page) - page_address(head_page));
1782                         /* page_offset only refers to the beginning of sgt[i];
1783                          * but the buffer itself may have an internal offset.
1784                          */
1785                         frag_off = qm_sg_entry_get_off(&sgt[i]) + page_offset;
1786                         frag_len = qm_sg_entry_get_len(&sgt[i]);
1787                         /* skb_add_rx_frag() does no checking on the page; if
1788                          * we pass it a tail page, we'll end up with
1789                          * bad page accounting and eventually with segafults.
1790                          */
1791                         skb_add_rx_frag(skb, i - 1, head_page, frag_off,
1792                                         frag_len, dpaa_bp->size);
1793                 }
1794                 /* Update the pool count for the current {cpu x bpool} */
1795                 (*count_ptr)--;
1796
1797                 if (qm_sg_entry_is_final(&sgt[i]))
1798                         break;
1799         }
1800         WARN_ONCE(i == DPAA_SGT_MAX_ENTRIES, "No final bit on SGT\n");
1801
1802         /* free the SG table buffer */
1803         skb_free_frag(vaddr);
1804
1805         return skb;
1806
1807 free_buffers:
1808         /* compensate sw bpool counter changes */
1809         for (i--; i >= 0; i--) {
1810                 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1811                 if (dpaa_bp) {
1812                         count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
1813                         (*count_ptr)++;
1814                 }
1815         }
1816         /* free all the SG entries */
1817         for (i = 0; i < DPAA_SGT_MAX_ENTRIES ; i++) {
1818                 sg_addr = qm_sg_addr(&sgt[i]);
1819                 sg_vaddr = phys_to_virt(sg_addr);
1820                 skb_free_frag(sg_vaddr);
1821                 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1822                 if (dpaa_bp) {
1823                         count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
1824                         (*count_ptr)--;
1825                 }
1826
1827                 if (qm_sg_entry_is_final(&sgt[i]))
1828                         break;
1829         }
1830         /* free the SGT fragment */
1831         skb_free_frag(vaddr);
1832
1833         return NULL;
1834 }
1835
1836 static int skb_to_contig_fd(struct dpaa_priv *priv,
1837                             struct sk_buff *skb, struct qm_fd *fd,
1838                             int *offset)
1839 {
1840         struct net_device *net_dev = priv->net_dev;
1841         struct device *dev = net_dev->dev.parent;
1842         enum dma_data_direction dma_dir;
1843         unsigned char *buffer_start;
1844         struct sk_buff **skbh;
1845         dma_addr_t addr;
1846         int err;
1847
1848         /* We are guaranteed to have at least tx_headroom bytes
1849          * available, so just use that for offset.
1850          */
1851         fd->bpid = FSL_DPAA_BPID_INV;
1852         buffer_start = skb->data - priv->tx_headroom;
1853         dma_dir = DMA_TO_DEVICE;
1854
1855         skbh = (struct sk_buff **)buffer_start;
1856         *skbh = skb;
1857
1858         /* Enable L3/L4 hardware checksum computation.
1859          *
1860          * We must do this before dma_map_single(DMA_TO_DEVICE), because we may
1861          * need to write into the skb.
1862          */
1863         err = dpaa_enable_tx_csum(priv, skb, fd,
1864                                   ((char *)skbh) + DPAA_TX_PRIV_DATA_SIZE);
1865         if (unlikely(err < 0)) {
1866                 if (net_ratelimit())
1867                         netif_err(priv, tx_err, net_dev, "HW csum error: %d\n",
1868                                   err);
1869                 return err;
1870         }
1871
1872         /* Fill in the rest of the FD fields */
1873         qm_fd_set_contig(fd, priv->tx_headroom, skb->len);
1874         fd->cmd |= cpu_to_be32(FM_FD_CMD_FCO);
1875
1876         /* Map the entire buffer size that may be seen by FMan, but no more */
1877         addr = dma_map_single(dev, skbh,
1878                               skb_tail_pointer(skb) - buffer_start, dma_dir);
1879         if (unlikely(dma_mapping_error(dev, addr))) {
1880                 if (net_ratelimit())
1881                         netif_err(priv, tx_err, net_dev, "dma_map_single() failed\n");
1882                 return -EINVAL;
1883         }
1884         qm_fd_addr_set64(fd, addr);
1885
1886         return 0;
1887 }
1888
1889 static int skb_to_sg_fd(struct dpaa_priv *priv,
1890                         struct sk_buff *skb, struct qm_fd *fd)
1891 {
1892         const enum dma_data_direction dma_dir = DMA_TO_DEVICE;
1893         const int nr_frags = skb_shinfo(skb)->nr_frags;
1894         struct net_device *net_dev = priv->net_dev;
1895         struct device *dev = net_dev->dev.parent;
1896         struct qm_sg_entry *sgt;
1897         struct sk_buff **skbh;
1898         int i, j, err, sz;
1899         void *buffer_start;
1900         skb_frag_t *frag;
1901         dma_addr_t addr;
1902         size_t frag_len;
1903         void *sgt_buf;
1904
1905         /* get a page frag to store the SGTable */
1906         sz = SKB_DATA_ALIGN(priv->tx_headroom +
1907                 sizeof(struct qm_sg_entry) * (1 + nr_frags));
1908         sgt_buf = netdev_alloc_frag(sz);
1909         if (unlikely(!sgt_buf)) {
1910                 netdev_err(net_dev, "netdev_alloc_frag() failed for size %d\n",
1911                            sz);
1912                 return -ENOMEM;
1913         }
1914
1915         /* Enable L3/L4 hardware checksum computation.
1916          *
1917          * We must do this before dma_map_single(DMA_TO_DEVICE), because we may
1918          * need to write into the skb.
1919          */
1920         err = dpaa_enable_tx_csum(priv, skb, fd,
1921                                   sgt_buf + DPAA_TX_PRIV_DATA_SIZE);
1922         if (unlikely(err < 0)) {
1923                 if (net_ratelimit())
1924                         netif_err(priv, tx_err, net_dev, "HW csum error: %d\n",
1925                                   err);
1926                 goto csum_failed;
1927         }
1928
1929         /* SGT[0] is used by the linear part */
1930         sgt = (struct qm_sg_entry *)(sgt_buf + priv->tx_headroom);
1931         frag_len = skb_headlen(skb);
1932         qm_sg_entry_set_len(&sgt[0], frag_len);
1933         sgt[0].bpid = FSL_DPAA_BPID_INV;
1934         sgt[0].offset = 0;
1935         addr = dma_map_single(dev, skb->data,
1936                               skb_headlen(skb), dma_dir);
1937         if (unlikely(dma_mapping_error(dev, addr))) {
1938                 dev_err(dev, "DMA mapping failed");
1939                 err = -EINVAL;
1940                 goto sg0_map_failed;
1941         }
1942         qm_sg_entry_set64(&sgt[0], addr);
1943
1944         /* populate the rest of SGT entries */
1945         for (i = 0; i < nr_frags; i++) {
1946                 frag = &skb_shinfo(skb)->frags[i];
1947                 frag_len = frag->size;
1948                 WARN_ON(!skb_frag_page(frag));
1949                 addr = skb_frag_dma_map(dev, frag, 0,
1950                                         frag_len, dma_dir);
1951                 if (unlikely(dma_mapping_error(dev, addr))) {
1952                         dev_err(dev, "DMA mapping failed");
1953                         err = -EINVAL;
1954                         goto sg_map_failed;
1955                 }
1956
1957                 qm_sg_entry_set_len(&sgt[i + 1], frag_len);
1958                 sgt[i + 1].bpid = FSL_DPAA_BPID_INV;
1959                 sgt[i + 1].offset = 0;
1960
1961                 /* keep the offset in the address */
1962                 qm_sg_entry_set64(&sgt[i + 1], addr);
1963         }
1964
1965         /* Set the final bit in the last used entry of the SGT */
1966         qm_sg_entry_set_f(&sgt[nr_frags], frag_len);
1967
1968         qm_fd_set_sg(fd, priv->tx_headroom, skb->len);
1969
1970         /* DMA map the SGT page */
1971         buffer_start = (void *)sgt - priv->tx_headroom;
1972         skbh = (struct sk_buff **)buffer_start;
1973         *skbh = skb;
1974
1975         addr = dma_map_single(dev, buffer_start, priv->tx_headroom +
1976                               sizeof(struct qm_sg_entry) * (1 + nr_frags),
1977                               dma_dir);
1978         if (unlikely(dma_mapping_error(dev, addr))) {
1979                 dev_err(dev, "DMA mapping failed");
1980                 err = -EINVAL;
1981                 goto sgt_map_failed;
1982         }
1983
1984         fd->bpid = FSL_DPAA_BPID_INV;
1985         fd->cmd |= cpu_to_be32(FM_FD_CMD_FCO);
1986         qm_fd_addr_set64(fd, addr);
1987
1988         return 0;
1989
1990 sgt_map_failed:
1991 sg_map_failed:
1992         for (j = 0; j < i; j++)
1993                 dma_unmap_page(dev, qm_sg_addr(&sgt[j]),
1994                                qm_sg_entry_get_len(&sgt[j]), dma_dir);
1995 sg0_map_failed:
1996 csum_failed:
1997         skb_free_frag(sgt_buf);
1998
1999         return err;
2000 }
2001
2002 static inline int dpaa_xmit(struct dpaa_priv *priv,
2003                             struct rtnl_link_stats64 *percpu_stats,
2004                             int queue,
2005                             struct qm_fd *fd)
2006 {
2007         struct qman_fq *egress_fq;
2008         int err, i;
2009
2010         egress_fq = priv->egress_fqs[queue];
2011         if (fd->bpid == FSL_DPAA_BPID_INV)
2012                 fd->cmd |= cpu_to_be32(qman_fq_fqid(priv->conf_fqs[queue]));
2013
2014         /* Trace this Tx fd */
2015         trace_dpaa_tx_fd(priv->net_dev, egress_fq, fd);
2016
2017         for (i = 0; i < DPAA_ENQUEUE_RETRIES; i++) {
2018                 err = qman_enqueue(egress_fq, fd);
2019                 if (err != -EBUSY)
2020                         break;
2021         }
2022
2023         if (unlikely(err < 0)) {
2024                 percpu_stats->tx_fifo_errors++;
2025                 return err;
2026         }
2027
2028         percpu_stats->tx_packets++;
2029         percpu_stats->tx_bytes += qm_fd_get_length(fd);
2030
2031         return 0;
2032 }
2033
2034 static int dpaa_start_xmit(struct sk_buff *skb, struct net_device *net_dev)
2035 {
2036         const int queue_mapping = skb_get_queue_mapping(skb);
2037         bool nonlinear = skb_is_nonlinear(skb);
2038         struct rtnl_link_stats64 *percpu_stats;
2039         struct dpaa_percpu_priv *percpu_priv;
2040         struct dpaa_priv *priv;
2041         struct qm_fd fd;
2042         int offset = 0;
2043         int err = 0;
2044
2045         priv = netdev_priv(net_dev);
2046         percpu_priv = this_cpu_ptr(priv->percpu_priv);
2047         percpu_stats = &percpu_priv->stats;
2048
2049         qm_fd_clear_fd(&fd);
2050
2051         if (!nonlinear) {
2052                 /* We're going to store the skb backpointer at the beginning
2053                  * of the data buffer, so we need a privately owned skb
2054                  *
2055                  * We've made sure skb is not shared in dev->priv_flags,
2056                  * we need to verify the skb head is not cloned
2057                  */
2058                 if (skb_cow_head(skb, priv->tx_headroom))
2059                         goto enomem;
2060
2061                 WARN_ON(skb_is_nonlinear(skb));
2062         }
2063
2064         /* MAX_SKB_FRAGS is equal or larger than our dpaa_SGT_MAX_ENTRIES;
2065          * make sure we don't feed FMan with more fragments than it supports.
2066          */
2067         if (unlikely(nonlinear &&
2068                      (skb_shinfo(skb)->nr_frags >= DPAA_SGT_MAX_ENTRIES))) {
2069                 /* If the egress skb contains more fragments than we support
2070                  * we have no choice but to linearize it ourselves.
2071                  */
2072                 if (__skb_linearize(skb))
2073                         goto enomem;
2074
2075                 nonlinear = skb_is_nonlinear(skb);
2076         }
2077
2078         if (nonlinear) {
2079                 /* Just create a S/G fd based on the skb */
2080                 err = skb_to_sg_fd(priv, skb, &fd);
2081                 percpu_priv->tx_frag_skbuffs++;
2082         } else {
2083                 /* Create a contig FD from this skb */
2084                 err = skb_to_contig_fd(priv, skb, &fd, &offset);
2085         }
2086         if (unlikely(err < 0))
2087                 goto skb_to_fd_failed;
2088
2089         if (likely(dpaa_xmit(priv, percpu_stats, queue_mapping, &fd) == 0))
2090                 return NETDEV_TX_OK;
2091
2092         dpaa_cleanup_tx_fd(priv, &fd);
2093 skb_to_fd_failed:
2094 enomem:
2095         percpu_stats->tx_errors++;
2096         dev_kfree_skb(skb);
2097         return NETDEV_TX_OK;
2098 }
2099
2100 static void dpaa_rx_error(struct net_device *net_dev,
2101                           const struct dpaa_priv *priv,
2102                           struct dpaa_percpu_priv *percpu_priv,
2103                           const struct qm_fd *fd,
2104                           u32 fqid)
2105 {
2106         if (net_ratelimit())
2107                 netif_err(priv, hw, net_dev, "Err FD status = 0x%08x\n",
2108                           be32_to_cpu(fd->status) & FM_FD_STAT_RX_ERRORS);
2109
2110         percpu_priv->stats.rx_errors++;
2111
2112         if (be32_to_cpu(fd->status) & FM_FD_ERR_DMA)
2113                 percpu_priv->rx_errors.dme++;
2114         if (be32_to_cpu(fd->status) & FM_FD_ERR_PHYSICAL)
2115                 percpu_priv->rx_errors.fpe++;
2116         if (be32_to_cpu(fd->status) & FM_FD_ERR_SIZE)
2117                 percpu_priv->rx_errors.fse++;
2118         if (be32_to_cpu(fd->status) & FM_FD_ERR_PRS_HDR_ERR)
2119                 percpu_priv->rx_errors.phe++;
2120
2121         dpaa_fd_release(net_dev, fd);
2122 }
2123
2124 static void dpaa_tx_error(struct net_device *net_dev,
2125                           const struct dpaa_priv *priv,
2126                           struct dpaa_percpu_priv *percpu_priv,
2127                           const struct qm_fd *fd,
2128                           u32 fqid)
2129 {
2130         struct sk_buff *skb;
2131
2132         if (net_ratelimit())
2133                 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
2134                            be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS);
2135
2136         percpu_priv->stats.tx_errors++;
2137
2138         skb = dpaa_cleanup_tx_fd(priv, fd);
2139         dev_kfree_skb(skb);
2140 }
2141
2142 static int dpaa_eth_poll(struct napi_struct *napi, int budget)
2143 {
2144         struct dpaa_napi_portal *np =
2145                         container_of(napi, struct dpaa_napi_portal, napi);
2146
2147         int cleaned = qman_p_poll_dqrr(np->p, budget);
2148
2149         if (cleaned < budget) {
2150                 napi_complete_done(napi, cleaned);
2151                 qman_p_irqsource_add(np->p, QM_PIRQ_DQRI);
2152
2153         } else if (np->down) {
2154                 qman_p_irqsource_add(np->p, QM_PIRQ_DQRI);
2155         }
2156
2157         return cleaned;
2158 }
2159
2160 static void dpaa_tx_conf(struct net_device *net_dev,
2161                          const struct dpaa_priv *priv,
2162                          struct dpaa_percpu_priv *percpu_priv,
2163                          const struct qm_fd *fd,
2164                          u32 fqid)
2165 {
2166         struct sk_buff  *skb;
2167
2168         if (unlikely(be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS)) {
2169                 if (net_ratelimit())
2170                         netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
2171                                    be32_to_cpu(fd->status) &
2172                                    FM_FD_STAT_TX_ERRORS);
2173
2174                 percpu_priv->stats.tx_errors++;
2175         }
2176
2177         percpu_priv->tx_confirm++;
2178
2179         skb = dpaa_cleanup_tx_fd(priv, fd);
2180
2181         consume_skb(skb);
2182 }
2183
2184 static inline int dpaa_eth_napi_schedule(struct dpaa_percpu_priv *percpu_priv,
2185                                          struct qman_portal *portal)
2186 {
2187         if (unlikely(in_irq() || !in_serving_softirq())) {
2188                 /* Disable QMan IRQ and invoke NAPI */
2189                 qman_p_irqsource_remove(portal, QM_PIRQ_DQRI);
2190
2191                 percpu_priv->np.p = portal;
2192                 napi_schedule(&percpu_priv->np.napi);
2193                 percpu_priv->in_interrupt++;
2194                 return 1;
2195         }
2196         return 0;
2197 }
2198
2199 static enum qman_cb_dqrr_result rx_error_dqrr(struct qman_portal *portal,
2200                                               struct qman_fq *fq,
2201                                               const struct qm_dqrr_entry *dq)
2202 {
2203         struct dpaa_fq *dpaa_fq = container_of(fq, struct dpaa_fq, fq_base);
2204         struct dpaa_percpu_priv *percpu_priv;
2205         struct net_device *net_dev;
2206         struct dpaa_bp *dpaa_bp;
2207         struct dpaa_priv *priv;
2208
2209         net_dev = dpaa_fq->net_dev;
2210         priv = netdev_priv(net_dev);
2211         dpaa_bp = dpaa_bpid2pool(dq->fd.bpid);
2212         if (!dpaa_bp)
2213                 return qman_cb_dqrr_consume;
2214
2215         percpu_priv = this_cpu_ptr(priv->percpu_priv);
2216
2217         if (dpaa_eth_napi_schedule(percpu_priv, portal))
2218                 return qman_cb_dqrr_stop;
2219
2220         dpaa_eth_refill_bpools(priv);
2221         dpaa_rx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
2222
2223         return qman_cb_dqrr_consume;
2224 }
2225
2226 static enum qman_cb_dqrr_result rx_default_dqrr(struct qman_portal *portal,
2227                                                 struct qman_fq *fq,
2228                                                 const struct qm_dqrr_entry *dq)
2229 {
2230         struct rtnl_link_stats64 *percpu_stats;
2231         struct dpaa_percpu_priv *percpu_priv;
2232         const struct qm_fd *fd = &dq->fd;
2233         dma_addr_t addr = qm_fd_addr(fd);
2234         enum qm_fd_format fd_format;
2235         struct net_device *net_dev;
2236         u32 fd_status, hash_offset;
2237         struct dpaa_bp *dpaa_bp;
2238         struct dpaa_priv *priv;
2239         unsigned int skb_len;
2240         struct sk_buff *skb;
2241         int *count_ptr;
2242         void *vaddr;
2243
2244         fd_status = be32_to_cpu(fd->status);
2245         fd_format = qm_fd_get_format(fd);
2246         net_dev = ((struct dpaa_fq *)fq)->net_dev;
2247         priv = netdev_priv(net_dev);
2248         dpaa_bp = dpaa_bpid2pool(dq->fd.bpid);
2249         if (!dpaa_bp)
2250                 return qman_cb_dqrr_consume;
2251
2252         /* Trace the Rx fd */
2253         trace_dpaa_rx_fd(net_dev, fq, &dq->fd);
2254
2255         percpu_priv = this_cpu_ptr(priv->percpu_priv);
2256         percpu_stats = &percpu_priv->stats;
2257
2258         if (unlikely(dpaa_eth_napi_schedule(percpu_priv, portal)))
2259                 return qman_cb_dqrr_stop;
2260
2261         /* Make sure we didn't run out of buffers */
2262         if (unlikely(dpaa_eth_refill_bpools(priv))) {
2263                 /* Unable to refill the buffer pool due to insufficient
2264                  * system memory. Just release the frame back into the pool,
2265                  * otherwise we'll soon end up with an empty buffer pool.
2266                  */
2267                 dpaa_fd_release(net_dev, &dq->fd);
2268                 return qman_cb_dqrr_consume;
2269         }
2270
2271         if (unlikely(fd_status & FM_FD_STAT_RX_ERRORS) != 0) {
2272                 if (net_ratelimit())
2273                         netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
2274                                    fd_status & FM_FD_STAT_RX_ERRORS);
2275
2276                 percpu_stats->rx_errors++;
2277                 dpaa_fd_release(net_dev, fd);
2278                 return qman_cb_dqrr_consume;
2279         }
2280
2281         dpaa_bp = dpaa_bpid2pool(fd->bpid);
2282         if (!dpaa_bp)
2283                 return qman_cb_dqrr_consume;
2284
2285         dma_unmap_single(dpaa_bp->dev, addr, dpaa_bp->size, DMA_FROM_DEVICE);
2286
2287         /* prefetch the first 64 bytes of the frame or the SGT start */
2288         vaddr = phys_to_virt(addr);
2289         prefetch(vaddr + qm_fd_get_offset(fd));
2290
2291         /* The only FD types that we may receive are contig and S/G */
2292         WARN_ON((fd_format != qm_fd_contig) && (fd_format != qm_fd_sg));
2293
2294         /* Account for either the contig buffer or the SGT buffer (depending on
2295          * which case we were in) having been removed from the pool.
2296          */
2297         count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
2298         (*count_ptr)--;
2299
2300         if (likely(fd_format == qm_fd_contig))
2301                 skb = contig_fd_to_skb(priv, fd);
2302         else
2303                 skb = sg_fd_to_skb(priv, fd);
2304         if (!skb)
2305                 return qman_cb_dqrr_consume;
2306
2307         skb->protocol = eth_type_trans(skb, net_dev);
2308
2309         if (net_dev->features & NETIF_F_RXHASH && priv->keygen_in_use &&
2310             !fman_port_get_hash_result_offset(priv->mac_dev->port[RX],
2311                                               &hash_offset)) {
2312                 enum pkt_hash_types type;
2313
2314                 /* if L4 exists, it was used in the hash generation */
2315                 type = be32_to_cpu(fd->status) & FM_FD_STAT_L4CV ?
2316                         PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3;
2317                 skb_set_hash(skb, be32_to_cpu(*(u32 *)(vaddr + hash_offset)),
2318                              type);
2319         }
2320
2321         skb_len = skb->len;
2322
2323         if (unlikely(netif_receive_skb(skb) == NET_RX_DROP)) {
2324                 percpu_stats->rx_dropped++;
2325                 return qman_cb_dqrr_consume;
2326         }
2327
2328         percpu_stats->rx_packets++;
2329         percpu_stats->rx_bytes += skb_len;
2330
2331         return qman_cb_dqrr_consume;
2332 }
2333
2334 static enum qman_cb_dqrr_result conf_error_dqrr(struct qman_portal *portal,
2335                                                 struct qman_fq *fq,
2336                                                 const struct qm_dqrr_entry *dq)
2337 {
2338         struct dpaa_percpu_priv *percpu_priv;
2339         struct net_device *net_dev;
2340         struct dpaa_priv *priv;
2341
2342         net_dev = ((struct dpaa_fq *)fq)->net_dev;
2343         priv = netdev_priv(net_dev);
2344
2345         percpu_priv = this_cpu_ptr(priv->percpu_priv);
2346
2347         if (dpaa_eth_napi_schedule(percpu_priv, portal))
2348                 return qman_cb_dqrr_stop;
2349
2350         dpaa_tx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
2351
2352         return qman_cb_dqrr_consume;
2353 }
2354
2355 static enum qman_cb_dqrr_result conf_dflt_dqrr(struct qman_portal *portal,
2356                                                struct qman_fq *fq,
2357                                                const struct qm_dqrr_entry *dq)
2358 {
2359         struct dpaa_percpu_priv *percpu_priv;
2360         struct net_device *net_dev;
2361         struct dpaa_priv *priv;
2362
2363         net_dev = ((struct dpaa_fq *)fq)->net_dev;
2364         priv = netdev_priv(net_dev);
2365
2366         /* Trace the fd */
2367         trace_dpaa_tx_conf_fd(net_dev, fq, &dq->fd);
2368
2369         percpu_priv = this_cpu_ptr(priv->percpu_priv);
2370
2371         if (dpaa_eth_napi_schedule(percpu_priv, portal))
2372                 return qman_cb_dqrr_stop;
2373
2374         dpaa_tx_conf(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
2375
2376         return qman_cb_dqrr_consume;
2377 }
2378
2379 static void egress_ern(struct qman_portal *portal,
2380                        struct qman_fq *fq,
2381                        const union qm_mr_entry *msg)
2382 {
2383         const struct qm_fd *fd = &msg->ern.fd;
2384         struct dpaa_percpu_priv *percpu_priv;
2385         const struct dpaa_priv *priv;
2386         struct net_device *net_dev;
2387         struct sk_buff *skb;
2388
2389         net_dev = ((struct dpaa_fq *)fq)->net_dev;
2390         priv = netdev_priv(net_dev);
2391         percpu_priv = this_cpu_ptr(priv->percpu_priv);
2392
2393         percpu_priv->stats.tx_dropped++;
2394         percpu_priv->stats.tx_fifo_errors++;
2395         count_ern(percpu_priv, msg);
2396
2397         skb = dpaa_cleanup_tx_fd(priv, fd);
2398         dev_kfree_skb_any(skb);
2399 }
2400
2401 static const struct dpaa_fq_cbs dpaa_fq_cbs = {
2402         .rx_defq = { .cb = { .dqrr = rx_default_dqrr } },
2403         .tx_defq = { .cb = { .dqrr = conf_dflt_dqrr } },
2404         .rx_errq = { .cb = { .dqrr = rx_error_dqrr } },
2405         .tx_errq = { .cb = { .dqrr = conf_error_dqrr } },
2406         .egress_ern = { .cb = { .ern = egress_ern } }
2407 };
2408
2409 static void dpaa_eth_napi_enable(struct dpaa_priv *priv)
2410 {
2411         struct dpaa_percpu_priv *percpu_priv;
2412         int i;
2413
2414         for_each_possible_cpu(i) {
2415                 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
2416
2417                 percpu_priv->np.down = 0;
2418                 napi_enable(&percpu_priv->np.napi);
2419         }
2420 }
2421
2422 static void dpaa_eth_napi_disable(struct dpaa_priv *priv)
2423 {
2424         struct dpaa_percpu_priv *percpu_priv;
2425         int i;
2426
2427         for_each_possible_cpu(i) {
2428                 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
2429
2430                 percpu_priv->np.down = 1;
2431                 napi_disable(&percpu_priv->np.napi);
2432         }
2433 }
2434
2435 static void dpaa_adjust_link(struct net_device *net_dev)
2436 {
2437         struct mac_device *mac_dev;
2438         struct dpaa_priv *priv;
2439
2440         priv = netdev_priv(net_dev);
2441         mac_dev = priv->mac_dev;
2442         mac_dev->adjust_link(mac_dev);
2443 }
2444
2445 static int dpaa_phy_init(struct net_device *net_dev)
2446 {
2447         struct mac_device *mac_dev;
2448         struct phy_device *phy_dev;
2449         struct dpaa_priv *priv;
2450
2451         priv = netdev_priv(net_dev);
2452         mac_dev = priv->mac_dev;
2453
2454         phy_dev = of_phy_connect(net_dev, mac_dev->phy_node,
2455                                  &dpaa_adjust_link, 0,
2456                                  mac_dev->phy_if);
2457         if (!phy_dev) {
2458                 netif_err(priv, ifup, net_dev, "init_phy() failed\n");
2459                 return -ENODEV;
2460         }
2461
2462         /* Remove any features not supported by the controller */
2463         phy_dev->supported &= mac_dev->if_support;
2464         phy_dev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
2465         phy_dev->advertising = phy_dev->supported;
2466
2467         mac_dev->phy_dev = phy_dev;
2468         net_dev->phydev = phy_dev;
2469
2470         return 0;
2471 }
2472
2473 static int dpaa_open(struct net_device *net_dev)
2474 {
2475         struct mac_device *mac_dev;
2476         struct dpaa_priv *priv;
2477         int err, i;
2478
2479         priv = netdev_priv(net_dev);
2480         mac_dev = priv->mac_dev;
2481         dpaa_eth_napi_enable(priv);
2482
2483         err = dpaa_phy_init(net_dev);
2484         if (err)
2485                 goto phy_init_failed;
2486
2487         for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) {
2488                 err = fman_port_enable(mac_dev->port[i]);
2489                 if (err)
2490                         goto mac_start_failed;
2491         }
2492
2493         err = priv->mac_dev->start(mac_dev);
2494         if (err < 0) {
2495                 netif_err(priv, ifup, net_dev, "mac_dev->start() = %d\n", err);
2496                 goto mac_start_failed;
2497         }
2498
2499         netif_tx_start_all_queues(net_dev);
2500
2501         return 0;
2502
2503 mac_start_failed:
2504         for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++)
2505                 fman_port_disable(mac_dev->port[i]);
2506
2507 phy_init_failed:
2508         dpaa_eth_napi_disable(priv);
2509
2510         return err;
2511 }
2512
2513 static int dpaa_eth_stop(struct net_device *net_dev)
2514 {
2515         struct dpaa_priv *priv;
2516         int err;
2517
2518         err = dpaa_stop(net_dev);
2519
2520         priv = netdev_priv(net_dev);
2521         dpaa_eth_napi_disable(priv);
2522
2523         return err;
2524 }
2525
2526 static int dpaa_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd)
2527 {
2528         if (!net_dev->phydev)
2529                 return -EINVAL;
2530         return phy_mii_ioctl(net_dev->phydev, rq, cmd);
2531 }
2532
2533 static const struct net_device_ops dpaa_ops = {
2534         .ndo_open = dpaa_open,
2535         .ndo_start_xmit = dpaa_start_xmit,
2536         .ndo_stop = dpaa_eth_stop,
2537         .ndo_tx_timeout = dpaa_tx_timeout,
2538         .ndo_get_stats64 = dpaa_get_stats64,
2539         .ndo_set_mac_address = dpaa_set_mac_address,
2540         .ndo_validate_addr = eth_validate_addr,
2541         .ndo_set_rx_mode = dpaa_set_rx_mode,
2542         .ndo_do_ioctl = dpaa_ioctl,
2543         .ndo_setup_tc = dpaa_setup_tc,
2544 };
2545
2546 static int dpaa_napi_add(struct net_device *net_dev)
2547 {
2548         struct dpaa_priv *priv = netdev_priv(net_dev);
2549         struct dpaa_percpu_priv *percpu_priv;
2550         int cpu;
2551
2552         for_each_possible_cpu(cpu) {
2553                 percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu);
2554
2555                 netif_napi_add(net_dev, &percpu_priv->np.napi,
2556                                dpaa_eth_poll, NAPI_POLL_WEIGHT);
2557         }
2558
2559         return 0;
2560 }
2561
2562 static void dpaa_napi_del(struct net_device *net_dev)
2563 {
2564         struct dpaa_priv *priv = netdev_priv(net_dev);
2565         struct dpaa_percpu_priv *percpu_priv;
2566         int cpu;
2567
2568         for_each_possible_cpu(cpu) {
2569                 percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu);
2570
2571                 netif_napi_del(&percpu_priv->np.napi);
2572         }
2573 }
2574
2575 static inline void dpaa_bp_free_pf(const struct dpaa_bp *bp,
2576                                    struct bm_buffer *bmb)
2577 {
2578         dma_addr_t addr = bm_buf_addr(bmb);
2579
2580         dma_unmap_single(bp->dev, addr, bp->size, DMA_FROM_DEVICE);
2581
2582         skb_free_frag(phys_to_virt(addr));
2583 }
2584
2585 /* Alloc the dpaa_bp struct and configure default values */
2586 static struct dpaa_bp *dpaa_bp_alloc(struct device *dev)
2587 {
2588         struct dpaa_bp *dpaa_bp;
2589
2590         dpaa_bp = devm_kzalloc(dev, sizeof(*dpaa_bp), GFP_KERNEL);
2591         if (!dpaa_bp)
2592                 return ERR_PTR(-ENOMEM);
2593
2594         dpaa_bp->bpid = FSL_DPAA_BPID_INV;
2595         dpaa_bp->percpu_count = devm_alloc_percpu(dev, *dpaa_bp->percpu_count);
2596         if (!dpaa_bp->percpu_count)
2597                 return ERR_PTR(-ENOMEM);
2598
2599         dpaa_bp->config_count = FSL_DPAA_ETH_MAX_BUF_COUNT;
2600
2601         dpaa_bp->seed_cb = dpaa_bp_seed;
2602         dpaa_bp->free_buf_cb = dpaa_bp_free_pf;
2603
2604         return dpaa_bp;
2605 }
2606
2607 /* Place all ingress FQs (Rx Default, Rx Error) in a dedicated CGR.
2608  * We won't be sending congestion notifications to FMan; for now, we just use
2609  * this CGR to generate enqueue rejections to FMan in order to drop the frames
2610  * before they reach our ingress queues and eat up memory.
2611  */
2612 static int dpaa_ingress_cgr_init(struct dpaa_priv *priv)
2613 {
2614         struct qm_mcc_initcgr initcgr;
2615         u32 cs_th;
2616         int err;
2617
2618         err = qman_alloc_cgrid(&priv->ingress_cgr.cgrid);
2619         if (err < 0) {
2620                 if (netif_msg_drv(priv))
2621                         pr_err("Error %d allocating CGR ID\n", err);
2622                 goto out_error;
2623         }
2624
2625         /* Enable CS TD, but disable Congestion State Change Notifications. */
2626         memset(&initcgr, 0, sizeof(initcgr));
2627         initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CS_THRES);
2628         initcgr.cgr.cscn_en = QM_CGR_EN;
2629         cs_th = DPAA_INGRESS_CS_THRESHOLD;
2630         qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1);
2631
2632         initcgr.we_mask |= cpu_to_be16(QM_CGR_WE_CSTD_EN);
2633         initcgr.cgr.cstd_en = QM_CGR_EN;
2634
2635         /* This CGR will be associated with the SWP affined to the current CPU.
2636          * However, we'll place all our ingress FQs in it.
2637          */
2638         err = qman_create_cgr(&priv->ingress_cgr, QMAN_CGR_FLAG_USE_INIT,
2639                               &initcgr);
2640         if (err < 0) {
2641                 if (netif_msg_drv(priv))
2642                         pr_err("Error %d creating ingress CGR with ID %d\n",
2643                                err, priv->ingress_cgr.cgrid);
2644                 qman_release_cgrid(priv->ingress_cgr.cgrid);
2645                 goto out_error;
2646         }
2647         if (netif_msg_drv(priv))
2648                 pr_debug("Created ingress CGR %d for netdev with hwaddr %pM\n",
2649                          priv->ingress_cgr.cgrid, priv->mac_dev->addr);
2650
2651         priv->use_ingress_cgr = true;
2652
2653 out_error:
2654         return err;
2655 }
2656
2657 static const struct of_device_id dpaa_match[];
2658
2659 static inline u16 dpaa_get_headroom(struct dpaa_buffer_layout *bl)
2660 {
2661         u16 headroom;
2662
2663         /* The frame headroom must accommodate:
2664          * - the driver private data area
2665          * - parse results, hash results, timestamp if selected
2666          * If either hash results or time stamp are selected, both will
2667          * be copied to/from the frame headroom, as TS is located between PR and
2668          * HR in the IC and IC copy size has a granularity of 16bytes
2669          * (see description of FMBM_RICP and FMBM_TICP registers in DPAARM)
2670          *
2671          * Also make sure the headroom is a multiple of data_align bytes
2672          */
2673         headroom = (u16)(bl->priv_data_size + DPAA_PARSE_RESULTS_SIZE +
2674                 DPAA_TIME_STAMP_SIZE + DPAA_HASH_RESULTS_SIZE);
2675
2676         return DPAA_FD_DATA_ALIGNMENT ? ALIGN(headroom,
2677                                               DPAA_FD_DATA_ALIGNMENT) :
2678                                         headroom;
2679 }
2680
2681 static int dpaa_eth_probe(struct platform_device *pdev)
2682 {
2683         struct dpaa_bp *dpaa_bps[DPAA_BPS_NUM] = {NULL};
2684         struct net_device *net_dev = NULL;
2685         struct dpaa_fq *dpaa_fq, *tmp;
2686         struct dpaa_priv *priv = NULL;
2687         struct fm_port_fqs port_fqs;
2688         struct mac_device *mac_dev;
2689         int err = 0, i, channel;
2690         struct device *dev;
2691
2692         /* device used for DMA mapping */
2693         dev = pdev->dev.parent;
2694         err = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(40));
2695         if (err) {
2696                 dev_err(dev, "dma_coerce_mask_and_coherent() failed\n");
2697                 return err;
2698         }
2699
2700         /* Allocate this early, so we can store relevant information in
2701          * the private area
2702          */
2703         net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA_ETH_TXQ_NUM);
2704         if (!net_dev) {
2705                 dev_err(dev, "alloc_etherdev_mq() failed\n");
2706                 return -ENOMEM;
2707         }
2708
2709         /* Do this here, so we can be verbose early */
2710         SET_NETDEV_DEV(net_dev, dev);
2711         dev_set_drvdata(dev, net_dev);
2712
2713         priv = netdev_priv(net_dev);
2714         priv->net_dev = net_dev;
2715
2716         priv->msg_enable = netif_msg_init(debug, DPAA_MSG_DEFAULT);
2717
2718         mac_dev = dpaa_mac_dev_get(pdev);
2719         if (IS_ERR(mac_dev)) {
2720                 dev_err(dev, "dpaa_mac_dev_get() failed\n");
2721                 err = PTR_ERR(mac_dev);
2722                 goto free_netdev;
2723         }
2724
2725         /* If fsl_fm_max_frm is set to a higher value than the all-common 1500,
2726          * we choose conservatively and let the user explicitly set a higher
2727          * MTU via ifconfig. Otherwise, the user may end up with different MTUs
2728          * in the same LAN.
2729          * If on the other hand fsl_fm_max_frm has been chosen below 1500,
2730          * start with the maximum allowed.
2731          */
2732         net_dev->mtu = min(dpaa_get_max_mtu(), ETH_DATA_LEN);
2733
2734         netdev_dbg(net_dev, "Setting initial MTU on net device: %d\n",
2735                    net_dev->mtu);
2736
2737         priv->buf_layout[RX].priv_data_size = DPAA_RX_PRIV_DATA_SIZE; /* Rx */
2738         priv->buf_layout[TX].priv_data_size = DPAA_TX_PRIV_DATA_SIZE; /* Tx */
2739
2740         /* bp init */
2741         for (i = 0; i < DPAA_BPS_NUM; i++) {
2742                 dpaa_bps[i] = dpaa_bp_alloc(dev);
2743                 if (IS_ERR(dpaa_bps[i])) {
2744                         err = PTR_ERR(dpaa_bps[i]);
2745                         goto free_dpaa_bps;
2746                 }
2747                 /* the raw size of the buffers used for reception */
2748                 dpaa_bps[i]->raw_size = bpool_buffer_raw_size(i, DPAA_BPS_NUM);
2749                 /* avoid runtime computations by keeping the usable size here */
2750                 dpaa_bps[i]->size = dpaa_bp_size(dpaa_bps[i]->raw_size);
2751                 dpaa_bps[i]->dev = dev;
2752
2753                 err = dpaa_bp_alloc_pool(dpaa_bps[i]);
2754                 if (err < 0)
2755                         goto free_dpaa_bps;
2756                 priv->dpaa_bps[i] = dpaa_bps[i];
2757         }
2758
2759         INIT_LIST_HEAD(&priv->dpaa_fq_list);
2760
2761         memset(&port_fqs, 0, sizeof(port_fqs));
2762
2763         err = dpaa_alloc_all_fqs(dev, &priv->dpaa_fq_list, &port_fqs);
2764         if (err < 0) {
2765                 dev_err(dev, "dpaa_alloc_all_fqs() failed\n");
2766                 goto free_dpaa_bps;
2767         }
2768
2769         priv->mac_dev = mac_dev;
2770
2771         channel = dpaa_get_channel();
2772         if (channel < 0) {
2773                 dev_err(dev, "dpaa_get_channel() failed\n");
2774                 err = channel;
2775                 goto free_dpaa_bps;
2776         }
2777
2778         priv->channel = (u16)channel;
2779
2780         /* Walk the CPUs with affine portals
2781          * and add this pool channel to each's dequeue mask.
2782          */
2783         dpaa_eth_add_channel(priv->channel);
2784
2785         dpaa_fq_setup(priv, &dpaa_fq_cbs, priv->mac_dev->port[TX]);
2786
2787         /* Create a congestion group for this netdev, with
2788          * dynamically-allocated CGR ID.
2789          * Must be executed after probing the MAC, but before
2790          * assigning the egress FQs to the CGRs.
2791          */
2792         err = dpaa_eth_cgr_init(priv);
2793         if (err < 0) {
2794                 dev_err(dev, "Error initializing CGR\n");
2795                 goto free_dpaa_bps;
2796         }
2797
2798         err = dpaa_ingress_cgr_init(priv);
2799         if (err < 0) {
2800                 dev_err(dev, "Error initializing ingress CGR\n");
2801                 goto delete_egress_cgr;
2802         }
2803
2804         /* Add the FQs to the interface, and make them active */
2805         list_for_each_entry_safe(dpaa_fq, tmp, &priv->dpaa_fq_list, list) {
2806                 err = dpaa_fq_init(dpaa_fq, false);
2807                 if (err < 0)
2808                         goto free_dpaa_fqs;
2809         }
2810
2811         priv->tx_headroom = dpaa_get_headroom(&priv->buf_layout[TX]);
2812         priv->rx_headroom = dpaa_get_headroom(&priv->buf_layout[RX]);
2813
2814         /* All real interfaces need their ports initialized */
2815         err = dpaa_eth_init_ports(mac_dev, dpaa_bps, DPAA_BPS_NUM, &port_fqs,
2816                                   &priv->buf_layout[0], dev);
2817         if (err)
2818                 goto free_dpaa_fqs;
2819
2820         /* Rx traffic distribution based on keygen hashing defaults to on */
2821         priv->keygen_in_use = true;
2822
2823         priv->percpu_priv = devm_alloc_percpu(dev, *priv->percpu_priv);
2824         if (!priv->percpu_priv) {
2825                 dev_err(dev, "devm_alloc_percpu() failed\n");
2826                 err = -ENOMEM;
2827                 goto free_dpaa_fqs;
2828         }
2829
2830         priv->num_tc = 1;
2831         netif_set_real_num_tx_queues(net_dev, priv->num_tc * DPAA_TC_TXQ_NUM);
2832
2833         /* Initialize NAPI */
2834         err = dpaa_napi_add(net_dev);
2835         if (err < 0)
2836                 goto delete_dpaa_napi;
2837
2838         err = dpaa_netdev_init(net_dev, &dpaa_ops, tx_timeout);
2839         if (err < 0)
2840                 goto delete_dpaa_napi;
2841
2842         dpaa_eth_sysfs_init(&net_dev->dev);
2843
2844         netif_info(priv, probe, net_dev, "Probed interface %s\n",
2845                    net_dev->name);
2846
2847         return 0;
2848
2849 delete_dpaa_napi:
2850         dpaa_napi_del(net_dev);
2851 free_dpaa_fqs:
2852         dpaa_fq_free(dev, &priv->dpaa_fq_list);
2853         qman_delete_cgr_safe(&priv->ingress_cgr);
2854         qman_release_cgrid(priv->ingress_cgr.cgrid);
2855 delete_egress_cgr:
2856         qman_delete_cgr_safe(&priv->cgr_data.cgr);
2857         qman_release_cgrid(priv->cgr_data.cgr.cgrid);
2858 free_dpaa_bps:
2859         dpaa_bps_free(priv);
2860 free_netdev:
2861         dev_set_drvdata(dev, NULL);
2862         free_netdev(net_dev);
2863
2864         return err;
2865 }
2866
2867 static int dpaa_remove(struct platform_device *pdev)
2868 {
2869         struct net_device *net_dev;
2870         struct dpaa_priv *priv;
2871         struct device *dev;
2872         int err;
2873
2874         dev = pdev->dev.parent;
2875         net_dev = dev_get_drvdata(dev);
2876
2877         priv = netdev_priv(net_dev);
2878
2879         dpaa_eth_sysfs_remove(dev);
2880
2881         dev_set_drvdata(dev, NULL);
2882         unregister_netdev(net_dev);
2883
2884         err = dpaa_fq_free(dev, &priv->dpaa_fq_list);
2885
2886         qman_delete_cgr_safe(&priv->ingress_cgr);
2887         qman_release_cgrid(priv->ingress_cgr.cgrid);
2888         qman_delete_cgr_safe(&priv->cgr_data.cgr);
2889         qman_release_cgrid(priv->cgr_data.cgr.cgrid);
2890
2891         dpaa_napi_del(net_dev);
2892
2893         dpaa_bps_free(priv);
2894
2895         free_netdev(net_dev);
2896
2897         return err;
2898 }
2899
2900 static const struct platform_device_id dpaa_devtype[] = {
2901         {
2902                 .name = "dpaa-ethernet",
2903                 .driver_data = 0,
2904         }, {
2905         }
2906 };
2907 MODULE_DEVICE_TABLE(platform, dpaa_devtype);
2908
2909 static struct platform_driver dpaa_driver = {
2910         .driver = {
2911                 .name = KBUILD_MODNAME,
2912         },
2913         .id_table = dpaa_devtype,
2914         .probe = dpaa_eth_probe,
2915         .remove = dpaa_remove
2916 };
2917
2918 static int __init dpaa_load(void)
2919 {
2920         int err;
2921
2922         pr_debug("FSL DPAA Ethernet driver\n");
2923
2924         /* initialize dpaa_eth mirror values */
2925         dpaa_rx_extra_headroom = fman_get_rx_extra_headroom();
2926         dpaa_max_frm = fman_get_max_frm();
2927
2928         err = platform_driver_register(&dpaa_driver);
2929         if (err < 0)
2930                 pr_err("Error, platform_driver_register() = %d\n", err);
2931
2932         return err;
2933 }
2934 module_init(dpaa_load);
2935
2936 static void __exit dpaa_unload(void)
2937 {
2938         platform_driver_unregister(&dpaa_driver);
2939
2940         /* Only one channel is used and needs to be released after all
2941          * interfaces are removed
2942          */
2943         dpaa_release_channel();
2944 }
2945 module_exit(dpaa_unload);
2946
2947 MODULE_LICENSE("Dual BSD/GPL");
2948 MODULE_DESCRIPTION("FSL DPAA Ethernet driver");