2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
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13 * without modification, are permitted provided that the following
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20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
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23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/delay.h>
38 #include "t4_values.h"
40 #include "t4fw_version.h"
43 * t4_wait_op_done_val - wait until an operation is completed
44 * @adapter: the adapter performing the operation
45 * @reg: the register to check for completion
46 * @mask: a single-bit field within @reg that indicates completion
47 * @polarity: the value of the field when the operation is completed
48 * @attempts: number of check iterations
49 * @delay: delay in usecs between iterations
50 * @valp: where to store the value of the register at completion time
52 * Wait until an operation is completed by checking a bit in a register
53 * up to @attempts times. If @valp is not NULL the value of the register
54 * at the time it indicated completion is stored there. Returns 0 if the
55 * operation completes and -EAGAIN otherwise.
57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
58 int polarity, int attempts, int delay, u32 *valp)
61 u32 val = t4_read_reg(adapter, reg);
63 if (!!(val & mask) == polarity) {
75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
76 int polarity, int attempts, int delay)
78 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
83 * t4_set_reg_field - set a register field to a value
84 * @adapter: the adapter to program
85 * @addr: the register address
86 * @mask: specifies the portion of the register to modify
87 * @val: the new value for the register field
89 * Sets a register field specified by the supplied mask to the
92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
95 u32 v = t4_read_reg(adapter, addr) & ~mask;
97 t4_write_reg(adapter, addr, v | val);
98 (void) t4_read_reg(adapter, addr); /* flush */
102 * t4_read_indirect - read indirectly addressed registers
104 * @addr_reg: register holding the indirect address
105 * @data_reg: register holding the value of the indirect register
106 * @vals: where the read register values are stored
107 * @nregs: how many indirect registers to read
108 * @start_idx: index of first indirect register to read
110 * Reads registers that are accessed indirectly through an address/data
113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
114 unsigned int data_reg, u32 *vals,
115 unsigned int nregs, unsigned int start_idx)
118 t4_write_reg(adap, addr_reg, start_idx);
119 *vals++ = t4_read_reg(adap, data_reg);
125 * t4_write_indirect - write indirectly addressed registers
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
137 unsigned int data_reg, const u32 *vals,
138 unsigned int nregs, unsigned int start_idx)
141 t4_write_reg(adap, addr_reg, start_idx++);
142 t4_write_reg(adap, data_reg, *vals++);
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
148 * mechanism. This guarantees that we get the real value even if we're
149 * operating within a Virtual Machine and the Hypervisor is trapping our
150 * Configuration Space accesses.
152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
154 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
161 if (is_t4(adap->params.chip))
164 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
165 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
168 * Configuration Space read. (None of the other fields matter when
169 * ENABLE is 0 so a simple register write is easier than a
170 * read-modify-write via t4_set_reg_field().)
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
176 * t4_report_fw_error - report firmware error
179 * The adapter firmware can indicate error conditions to the host.
180 * If the firmware has indicated an error, print out the reason for
181 * the firmware error.
183 static void t4_report_fw_error(struct adapter *adap)
185 static const char *const reason[] = {
186 "Crash", /* PCIE_FW_EVAL_CRASH */
187 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
188 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
189 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
190 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
191 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
192 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
193 "Reserved", /* reserved */
197 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
198 if (pcie_fw & PCIE_FW_ERR_F) {
199 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
200 reason[PCIE_FW_EVAL_G(pcie_fw)]);
201 adap->flags &= ~FW_OK;
206 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
208 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
211 for ( ; nflit; nflit--, mbox_addr += 8)
212 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
216 * Handle a FW assertion reported in a mailbox.
218 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
220 struct fw_debug_cmd asrt;
222 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
223 dev_alert(adap->pdev_dev,
224 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
225 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
226 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
230 * t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
231 * @adapter: the adapter
232 * @cmd: the Firmware Mailbox Command or Reply
233 * @size: command length in bytes
234 * @access: the time (ms) needed to access the Firmware Mailbox
235 * @execute: the time (ms) the command spent being executed
237 static void t4_record_mbox(struct adapter *adapter,
238 const __be64 *cmd, unsigned int size,
239 int access, int execute)
241 struct mbox_cmd_log *log = adapter->mbox_log;
242 struct mbox_cmd *entry;
245 entry = mbox_cmd_log_entry(log, log->cursor++);
246 if (log->cursor == log->size)
249 for (i = 0; i < size / 8; i++)
250 entry->cmd[i] = be64_to_cpu(cmd[i]);
251 while (i < MBOX_LEN / 8)
253 entry->timestamp = jiffies;
254 entry->seqno = log->seqno++;
255 entry->access = access;
256 entry->execute = execute;
260 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
262 * @mbox: index of the mailbox to use
263 * @cmd: the command to write
264 * @size: command length in bytes
265 * @rpl: where to optionally store the reply
266 * @sleep_ok: if true we may sleep while awaiting command completion
267 * @timeout: time to wait for command to finish before timing out
269 * Sends the given command to FW through the selected mailbox and waits
270 * for the FW to execute the command. If @rpl is not %NULL it is used to
271 * store the FW's reply to the command. The command and its optional
272 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
273 * to respond. @sleep_ok determines whether we may sleep while awaiting
274 * the response. If sleeping is allowed we use progressive backoff
277 * The return value is 0 on success or a negative errno on failure. A
278 * failure can happen either because we are not able to execute the
279 * command or FW executes it but signals an error. In the latter case
280 * the return value is the error code indicated by FW (negated).
282 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
283 int size, void *rpl, bool sleep_ok, int timeout)
285 static const int delay[] = {
286 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
289 struct mbox_list entry;
294 int i, ms, delay_idx, ret;
295 const __be64 *p = cmd;
296 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
297 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
298 __be64 cmd_rpl[MBOX_LEN / 8];
301 if ((size & 15) || size > MBOX_LEN)
305 * If the device is off-line, as in EEH, commands will time out.
306 * Fail them early so we don't waste time waiting.
308 if (adap->pdev->error_state != pci_channel_io_normal)
311 /* If we have a negative timeout, that implies that we can't sleep. */
317 /* Queue ourselves onto the mailbox access list. When our entry is at
318 * the front of the list, we have rights to access the mailbox. So we
319 * wait [for a while] till we're at the front [or bail out with an
322 spin_lock_bh(&adap->mbox_lock);
323 list_add_tail(&entry.list, &adap->mlist.list);
324 spin_unlock_bh(&adap->mbox_lock);
329 for (i = 0; ; i += ms) {
330 /* If we've waited too long, return a busy indication. This
331 * really ought to be based on our initial position in the
332 * mailbox access list but this is a start. We very rearely
333 * contend on access to the mailbox ...
335 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
336 if (i > FW_CMD_MAX_TIMEOUT || (pcie_fw & PCIE_FW_ERR_F)) {
337 spin_lock_bh(&adap->mbox_lock);
338 list_del(&entry.list);
339 spin_unlock_bh(&adap->mbox_lock);
340 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -EBUSY;
341 t4_record_mbox(adap, cmd, size, access, ret);
345 /* If we're at the head, break out and start the mailbox
348 if (list_first_entry(&adap->mlist.list, struct mbox_list,
352 /* Delay for a bit before checking again ... */
354 ms = delay[delay_idx]; /* last element may repeat */
355 if (delay_idx < ARRAY_SIZE(delay) - 1)
363 /* Loop trying to get ownership of the mailbox. Return an error
364 * if we can't gain ownership.
366 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
367 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
368 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
369 if (v != MBOX_OWNER_DRV) {
370 spin_lock_bh(&adap->mbox_lock);
371 list_del(&entry.list);
372 spin_unlock_bh(&adap->mbox_lock);
373 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
374 t4_record_mbox(adap, cmd, size, access, ret);
378 /* Copy in the new mailbox command and send it on its way ... */
379 t4_record_mbox(adap, cmd, size, access, 0);
380 for (i = 0; i < size; i += 8)
381 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
383 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
384 t4_read_reg(adap, ctl_reg); /* flush write */
390 !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
394 ms = delay[delay_idx]; /* last element may repeat */
395 if (delay_idx < ARRAY_SIZE(delay) - 1)
401 v = t4_read_reg(adap, ctl_reg);
402 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
403 if (!(v & MBMSGVALID_F)) {
404 t4_write_reg(adap, ctl_reg, 0);
408 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
409 res = be64_to_cpu(cmd_rpl[0]);
411 if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
412 fw_asrt(adap, data_reg);
413 res = FW_CMD_RETVAL_V(EIO);
415 memcpy(rpl, cmd_rpl, size);
418 t4_write_reg(adap, ctl_reg, 0);
421 t4_record_mbox(adap, cmd_rpl,
422 MBOX_LEN, access, execute);
423 spin_lock_bh(&adap->mbox_lock);
424 list_del(&entry.list);
425 spin_unlock_bh(&adap->mbox_lock);
426 return -FW_CMD_RETVAL_G((int)res);
430 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
431 t4_record_mbox(adap, cmd, size, access, ret);
432 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
433 *(const u8 *)cmd, mbox);
434 t4_report_fw_error(adap);
435 spin_lock_bh(&adap->mbox_lock);
436 list_del(&entry.list);
437 spin_unlock_bh(&adap->mbox_lock);
442 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
443 void *rpl, bool sleep_ok)
445 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
449 static int t4_edc_err_read(struct adapter *adap, int idx)
451 u32 edc_ecc_err_addr_reg;
454 if (is_t4(adap->params.chip)) {
455 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
458 if (idx != 0 && idx != 1) {
459 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
463 edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
464 rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
467 "edc%d err addr 0x%x: 0x%x.\n",
468 idx, edc_ecc_err_addr_reg,
469 t4_read_reg(adap, edc_ecc_err_addr_reg));
471 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
473 (unsigned long long)t4_read_reg64(adap, rdata_reg),
474 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
475 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
476 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
477 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
478 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
479 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
480 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
481 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
487 * t4_memory_rw_init - Get memory window relative offset, base, and size.
489 * @win: PCI-E Memory Window to use
490 * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_HMA or MEM_MC
491 * @mem_off: memory relative offset with respect to @mtype.
492 * @mem_base: configured memory base address.
493 * @mem_aperture: configured memory window aperture.
495 * Get the configured memory window's relative offset, base, and size.
497 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
498 u32 *mem_base, u32 *mem_aperture)
500 u32 edc_size, mc_size, mem_reg;
502 /* Offset into the region of memory which is being accessed
505 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
506 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
509 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
510 if (mtype == MEM_HMA) {
511 *mem_off = 2 * (edc_size * 1024 * 1024);
512 } else if (mtype != MEM_MC1) {
513 *mem_off = (mtype * (edc_size * 1024 * 1024));
515 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
516 MA_EXT_MEMORY0_BAR_A));
517 *mem_off = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
520 /* Each PCI-E Memory Window is programmed with a window size -- or
521 * "aperture" -- which controls the granularity of its mapping onto
522 * adapter memory. We need to grab that aperture in order to know
523 * how to use the specified window. The window is also programmed
524 * with the base address of the Memory Window in BAR0's address
525 * space. For T4 this is an absolute PCI-E Bus Address. For T5
526 * the address is relative to BAR0.
528 mem_reg = t4_read_reg(adap,
529 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
531 /* a dead adapter will return 0xffffffff for PIO reads */
532 if (mem_reg == 0xffffffff)
535 *mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
536 *mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
537 if (is_t4(adap->params.chip))
538 *mem_base -= adap->t4_bar0;
544 * t4_memory_update_win - Move memory window to specified address.
546 * @win: PCI-E Memory Window to use
547 * @addr: location to move.
549 * Move memory window to specified address.
551 void t4_memory_update_win(struct adapter *adap, int win, u32 addr)
554 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
556 /* Read it back to ensure that changes propagate before we
557 * attempt to use the new value.
560 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
564 * t4_memory_rw_residual - Read/Write residual data.
566 * @off: relative offset within residual to start read/write.
567 * @addr: address within indicated memory type.
568 * @buf: host memory buffer
569 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
571 * Read/Write residual data less than 32-bits.
573 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
583 if (dir == T4_MEMORY_READ) {
584 last.word = le32_to_cpu((__force __le32)
585 t4_read_reg(adap, addr));
586 for (bp = (unsigned char *)buf, i = off; i < 4; i++)
587 bp[i] = last.byte[i];
590 for (i = off; i < 4; i++)
592 t4_write_reg(adap, addr,
593 (__force u32)cpu_to_le32(last.word));
598 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
600 * @win: PCI-E Memory Window to use
601 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
602 * @addr: address within indicated memory type
603 * @len: amount of memory to transfer
604 * @hbuf: host memory buffer
605 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
607 * Reads/writes an [almost] arbitrary memory region in the firmware: the
608 * firmware memory address and host buffer must be aligned on 32-bit
609 * boudaries; the length may be arbitrary. The memory is transferred as
610 * a raw byte sequence from/to the firmware's memory. If this memory
611 * contains data structures which contain multi-byte integers, it's the
612 * caller's responsibility to perform appropriate byte order conversions.
614 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
615 u32 len, void *hbuf, int dir)
617 u32 pos, offset, resid, memoffset;
618 u32 win_pf, mem_aperture, mem_base;
622 /* Argument sanity checks ...
624 if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
628 /* It's convenient to be able to handle lengths which aren't a
629 * multiple of 32-bits because we often end up transferring files to
630 * the firmware. So we'll handle that by normalizing the length here
631 * and then handling any residual transfer at the end.
636 ret = t4_memory_rw_init(adap, win, mtype, &memoffset, &mem_base,
641 /* Determine the PCIE_MEM_ACCESS_OFFSET */
642 addr = addr + memoffset;
644 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
646 /* Calculate our initial PCI-E Memory Window Position and Offset into
649 pos = addr & ~(mem_aperture - 1);
652 /* Set up initial PCI-E Memory Window to cover the start of our
655 t4_memory_update_win(adap, win, pos | win_pf);
657 /* Transfer data to/from the adapter as long as there's an integral
658 * number of 32-bit transfers to complete.
660 * A note on Endianness issues:
662 * The "register" reads and writes below from/to the PCI-E Memory
663 * Window invoke the standard adapter Big-Endian to PCI-E Link
664 * Little-Endian "swizzel." As a result, if we have the following
665 * data in adapter memory:
667 * Memory: ... | b0 | b1 | b2 | b3 | ...
668 * Address: i+0 i+1 i+2 i+3
670 * Then a read of the adapter memory via the PCI-E Memory Window
675 * [ b3 | b2 | b1 | b0 ]
677 * If this value is stored into local memory on a Little-Endian system
678 * it will show up correctly in local memory as:
680 * ( ..., b0, b1, b2, b3, ... )
682 * But on a Big-Endian system, the store will show up in memory
683 * incorrectly swizzled as:
685 * ( ..., b3, b2, b1, b0, ... )
687 * So we need to account for this in the reads and writes to the
688 * PCI-E Memory Window below by undoing the register read/write
692 if (dir == T4_MEMORY_READ)
693 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
696 t4_write_reg(adap, mem_base + offset,
697 (__force u32)cpu_to_le32(*buf++));
698 offset += sizeof(__be32);
699 len -= sizeof(__be32);
701 /* If we've reached the end of our current window aperture,
702 * move the PCI-E Memory Window on to the next. Note that
703 * doing this here after "len" may be 0 allows us to set up
704 * the PCI-E Memory Window for a possible final residual
707 if (offset == mem_aperture) {
710 t4_memory_update_win(adap, win, pos | win_pf);
714 /* If the original transfer had a length which wasn't a multiple of
715 * 32-bits, now's where we need to finish off the transfer of the
716 * residual amount. The PCI-E Memory Window has already been moved
717 * above (if necessary) to cover this final transfer.
720 t4_memory_rw_residual(adap, resid, mem_base + offset,
726 /* Return the specified PCI-E Configuration Space register from our Physical
727 * Function. We try first via a Firmware LDST Command since we prefer to let
728 * the firmware own all of these registers, but if that fails we go for it
729 * directly ourselves.
731 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
733 u32 val, ldst_addrspace;
735 /* If fw_attach != 0, construct and send the Firmware LDST Command to
736 * retrieve the specified PCI-E Configuration Space register.
738 struct fw_ldst_cmd ldst_cmd;
741 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
742 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
743 ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
747 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
748 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
749 ldst_cmd.u.pcie.ctrl_to_fn =
750 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
751 ldst_cmd.u.pcie.r = reg;
753 /* If the LDST Command succeeds, return the result, otherwise
754 * fall through to reading it directly ourselves ...
756 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
759 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
761 /* Read the desired Configuration Space register via the PCI-E
762 * Backdoor mechanism.
764 t4_hw_pci_read_cfg4(adap, reg, &val);
768 /* Get the window based on base passed to it.
769 * Window aperture is currently unhandled, but there is no use case for it
772 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
777 if (is_t4(adap->params.chip)) {
780 /* Truncation intentional: we only read the bottom 32-bits of
781 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
782 * mechanism to read BAR0 instead of using
783 * pci_resource_start() because we could be operating from
784 * within a Virtual Machine which is trapping our accesses to
785 * our Configuration Space and we need to set up the PCI-E
786 * Memory Window decoders with the actual addresses which will
787 * be coming across the PCI-E link.
789 bar0 = t4_read_pcie_cfg4(adap, pci_base);
791 adap->t4_bar0 = bar0;
793 ret = bar0 + memwin_base;
795 /* For T5, only relative offset inside the PCIe BAR is passed */
801 /* Get the default utility window (win0) used by everyone */
802 u32 t4_get_util_window(struct adapter *adap)
804 return t4_get_window(adap, PCI_BASE_ADDRESS_0,
805 PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
808 /* Set up memory window for accessing adapter memory ranges. (Read
809 * back MA register to ensure that changes propagate before we attempt
810 * to use the new values.)
812 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
815 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
816 memwin_base | BIR_V(0) |
817 WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
819 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
823 * t4_get_regs_len - return the size of the chips register set
824 * @adapter: the adapter
826 * Returns the size of the chip's BAR0 register space.
828 unsigned int t4_get_regs_len(struct adapter *adapter)
830 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
832 switch (chip_version) {
834 return T4_REGMAP_SIZE;
838 return T5_REGMAP_SIZE;
841 dev_err(adapter->pdev_dev,
842 "Unsupported chip version %d\n", chip_version);
847 * t4_get_regs - read chip registers into provided buffer
849 * @buf: register buffer
850 * @buf_size: size (in bytes) of register buffer
852 * If the provided register buffer isn't large enough for the chip's
853 * full register range, the register dump will be truncated to the
854 * register buffer's size.
856 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
858 static const unsigned int t4_reg_ranges[] = {
1317 static const unsigned int t5_reg_ranges[] = {
2084 static const unsigned int t6_reg_ranges[] = {
2645 u32 *buf_end = (u32 *)((char *)buf + buf_size);
2646 const unsigned int *reg_ranges;
2647 int reg_ranges_size, range;
2648 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2650 /* Select the right set of register ranges to dump depending on the
2651 * adapter chip type.
2653 switch (chip_version) {
2655 reg_ranges = t4_reg_ranges;
2656 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2660 reg_ranges = t5_reg_ranges;
2661 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2665 reg_ranges = t6_reg_ranges;
2666 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2670 dev_err(adap->pdev_dev,
2671 "Unsupported chip version %d\n", chip_version);
2675 /* Clear the register buffer and insert the appropriate register
2676 * values selected by the above register ranges.
2678 memset(buf, 0, buf_size);
2679 for (range = 0; range < reg_ranges_size; range += 2) {
2680 unsigned int reg = reg_ranges[range];
2681 unsigned int last_reg = reg_ranges[range + 1];
2682 u32 *bufp = (u32 *)((char *)buf + reg);
2684 /* Iterate across the register range filling in the register
2685 * buffer but don't write past the end of the register buffer.
2687 while (reg <= last_reg && bufp < buf_end) {
2688 *bufp++ = t4_read_reg(adap, reg);
2694 #define EEPROM_STAT_ADDR 0x7bfc
2695 #define VPD_BASE 0x400
2696 #define VPD_BASE_OLD 0
2697 #define VPD_LEN 1024
2698 #define CHELSIO_VPD_UNIQUE_ID 0x82
2701 * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2702 * @phys_addr: the physical EEPROM address
2703 * @fn: the PCI function number
2704 * @sz: size of function-specific area
2706 * Translate a physical EEPROM address to virtual. The first 1K is
2707 * accessed through virtual addresses starting at 31K, the rest is
2708 * accessed through virtual addresses starting at 0.
2710 * The mapping is as follows:
2711 * [0..1K) -> [31K..32K)
2712 * [1K..1K+A) -> [31K-A..31K)
2713 * [1K+A..ES) -> [0..ES-A-1K)
2715 * where A = @fn * @sz, and ES = EEPROM size.
2717 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2720 if (phys_addr < 1024)
2721 return phys_addr + (31 << 10);
2722 if (phys_addr < 1024 + fn)
2723 return 31744 - fn + phys_addr - 1024;
2724 if (phys_addr < EEPROMSIZE)
2725 return phys_addr - 1024 - fn;
2730 * t4_seeprom_wp - enable/disable EEPROM write protection
2731 * @adapter: the adapter
2732 * @enable: whether to enable or disable write protection
2734 * Enables or disables write protection on the serial EEPROM.
2736 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2738 unsigned int v = enable ? 0xc : 0;
2739 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2740 return ret < 0 ? ret : 0;
2744 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2745 * @adapter: adapter to read
2746 * @p: where to store the parameters
2748 * Reads card parameters stored in VPD EEPROM.
2750 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2752 int i, ret = 0, addr;
2755 unsigned int vpdr_len, kw_offset, id_len;
2757 vpd = vmalloc(VPD_LEN);
2761 /* Card information normally starts at VPD_BASE but early cards had
2764 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2768 /* The VPD shall have a unique identifier specified by the PCI SIG.
2769 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2770 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2771 * is expected to automatically put this entry at the
2772 * beginning of the VPD.
2774 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2776 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2780 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2781 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2786 id_len = pci_vpd_lrdt_size(vpd);
2787 if (id_len > ID_LEN)
2790 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2792 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2797 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2798 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2799 if (vpdr_len + kw_offset > VPD_LEN) {
2800 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2805 #define FIND_VPD_KW(var, name) do { \
2806 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2808 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2812 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2815 FIND_VPD_KW(i, "RV");
2816 for (csum = 0; i >= 0; i--)
2820 dev_err(adapter->pdev_dev,
2821 "corrupted VPD EEPROM, actual csum %u\n", csum);
2826 FIND_VPD_KW(ec, "EC");
2827 FIND_VPD_KW(sn, "SN");
2828 FIND_VPD_KW(pn, "PN");
2829 FIND_VPD_KW(na, "NA");
2832 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2834 memcpy(p->ec, vpd + ec, EC_LEN);
2836 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2837 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2839 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2840 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2842 memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2843 strim((char *)p->na);
2847 return ret < 0 ? ret : 0;
2851 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2852 * @adapter: adapter to read
2853 * @p: where to store the parameters
2855 * Reads card parameters stored in VPD EEPROM and retrieves the Core
2856 * Clock. This can only be called after a connection to the firmware
2859 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2861 u32 cclk_param, cclk_val;
2864 /* Grab the raw VPD parameters.
2866 ret = t4_get_raw_vpd_params(adapter, p);
2870 /* Ask firmware for the Core Clock since it knows how to translate the
2871 * Reference Clock ('V2') VPD field into a Core Clock value ...
2873 cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2874 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2875 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2876 1, &cclk_param, &cclk_val);
2885 /* serial flash and firmware constants */
2887 SF_ATTEMPTS = 10, /* max retries for SF operations */
2889 /* flash command opcodes */
2890 SF_PROG_PAGE = 2, /* program page */
2891 SF_WR_DISABLE = 4, /* disable writes */
2892 SF_RD_STATUS = 5, /* read status register */
2893 SF_WR_ENABLE = 6, /* enable writes */
2894 SF_RD_DATA_FAST = 0xb, /* read flash */
2895 SF_RD_ID = 0x9f, /* read ID */
2896 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2900 * sf1_read - read data from the serial flash
2901 * @adapter: the adapter
2902 * @byte_cnt: number of bytes to read
2903 * @cont: whether another operation will be chained
2904 * @lock: whether to lock SF for PL access only
2905 * @valp: where to store the read data
2907 * Reads up to 4 bytes of data from the serial flash. The location of
2908 * the read needs to be specified prior to calling this by issuing the
2909 * appropriate commands to the serial flash.
2911 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2912 int lock, u32 *valp)
2916 if (!byte_cnt || byte_cnt > 4)
2918 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2920 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2921 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2922 ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2924 *valp = t4_read_reg(adapter, SF_DATA_A);
2929 * sf1_write - write data to the serial flash
2930 * @adapter: the adapter
2931 * @byte_cnt: number of bytes to write
2932 * @cont: whether another operation will be chained
2933 * @lock: whether to lock SF for PL access only
2934 * @val: value to write
2936 * Writes up to 4 bytes of data to the serial flash. The location of
2937 * the write needs to be specified prior to calling this by issuing the
2938 * appropriate commands to the serial flash.
2940 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2943 if (!byte_cnt || byte_cnt > 4)
2945 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2947 t4_write_reg(adapter, SF_DATA_A, val);
2948 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2949 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2950 return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2954 * flash_wait_op - wait for a flash operation to complete
2955 * @adapter: the adapter
2956 * @attempts: max number of polls of the status register
2957 * @delay: delay between polls in ms
2959 * Wait for a flash operation to complete by polling the status register.
2961 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
2967 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
2968 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
2972 if (--attempts == 0)
2980 * t4_read_flash - read words from serial flash
2981 * @adapter: the adapter
2982 * @addr: the start address for the read
2983 * @nwords: how many 32-bit words to read
2984 * @data: where to store the read data
2985 * @byte_oriented: whether to store data as bytes or as words
2987 * Read the specified number of 32-bit words from the serial flash.
2988 * If @byte_oriented is set the read data is stored as a byte array
2989 * (i.e., big-endian), otherwise as 32-bit words in the platform's
2990 * natural endianness.
2992 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2993 unsigned int nwords, u32 *data, int byte_oriented)
2997 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
3000 addr = swab32(addr) | SF_RD_DATA_FAST;
3002 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
3003 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
3006 for ( ; nwords; nwords--, data++) {
3007 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
3009 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3013 *data = (__force __u32)(cpu_to_be32(*data));
3019 * t4_write_flash - write up to a page of data to the serial flash
3020 * @adapter: the adapter
3021 * @addr: the start address to write
3022 * @n: length of data to write in bytes
3023 * @data: the data to write
3025 * Writes up to a page of data (256 bytes) to the serial flash starting
3026 * at the given address. All the data must be written to the same page.
3028 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
3029 unsigned int n, const u8 *data)
3033 unsigned int i, c, left, val, offset = addr & 0xff;
3035 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
3038 val = swab32(addr) | SF_PROG_PAGE;
3040 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3041 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
3044 for (left = n; left; left -= c) {
3046 for (val = 0, i = 0; i < c; ++i)
3047 val = (val << 8) + *data++;
3049 ret = sf1_write(adapter, c, c != left, 1, val);
3053 ret = flash_wait_op(adapter, 8, 1);
3057 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3059 /* Read the page to verify the write succeeded */
3060 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
3064 if (memcmp(data - n, (u8 *)buf + offset, n)) {
3065 dev_err(adapter->pdev_dev,
3066 "failed to correctly write the flash page at %#x\n",
3073 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3078 * t4_get_fw_version - read the firmware version
3079 * @adapter: the adapter
3080 * @vers: where to place the version
3082 * Reads the FW version from flash.
3084 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3086 return t4_read_flash(adapter, FLASH_FW_START +
3087 offsetof(struct fw_hdr, fw_ver), 1,
3092 * t4_get_bs_version - read the firmware bootstrap version
3093 * @adapter: the adapter
3094 * @vers: where to place the version
3096 * Reads the FW Bootstrap version from flash.
3098 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3100 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3101 offsetof(struct fw_hdr, fw_ver), 1,
3106 * t4_get_tp_version - read the TP microcode version
3107 * @adapter: the adapter
3108 * @vers: where to place the version
3110 * Reads the TP microcode version from flash.
3112 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3114 return t4_read_flash(adapter, FLASH_FW_START +
3115 offsetof(struct fw_hdr, tp_microcode_ver),
3120 * t4_get_exprom_version - return the Expansion ROM version (if any)
3121 * @adapter: the adapter
3122 * @vers: where to place the version
3124 * Reads the Expansion ROM header from FLASH and returns the version
3125 * number (if present) through the @vers return value pointer. We return
3126 * this in the Firmware Version Format since it's convenient. Return
3127 * 0 on success, -ENOENT if no Expansion ROM is present.
3129 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3131 struct exprom_header {
3132 unsigned char hdr_arr[16]; /* must start with 0x55aa */
3133 unsigned char hdr_ver[4]; /* Expansion ROM version */
3135 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3139 ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3140 ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3145 hdr = (struct exprom_header *)exprom_header_buf;
3146 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3149 *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3150 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3151 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3152 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3157 * t4_get_vpd_version - return the VPD version
3158 * @adapter: the adapter
3159 * @vers: where to place the version
3161 * Reads the VPD via the Firmware interface (thus this can only be called
3162 * once we're ready to issue Firmware commands). The format of the
3163 * VPD version is adapter specific. Returns 0 on success, an error on
3166 * Note that early versions of the Firmware didn't include the ability
3167 * to retrieve the VPD version, so we zero-out the return-value parameter
3168 * in that case to avoid leaving it with garbage in it.
3170 * Also note that the Firmware will return its cached copy of the VPD
3171 * Revision ID, not the actual Revision ID as written in the Serial
3172 * EEPROM. This is only an issue if a new VPD has been written and the
3173 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best
3174 * to defer calling this routine till after a FW_RESET_CMD has been issued
3175 * if the Host Driver will be performing a full adapter initialization.
3177 int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3182 vpdrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3183 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_VPDREV));
3184 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3185 1, &vpdrev_param, vers);
3192 * t4_get_scfg_version - return the Serial Configuration version
3193 * @adapter: the adapter
3194 * @vers: where to place the version
3196 * Reads the Serial Configuration Version via the Firmware interface
3197 * (thus this can only be called once we're ready to issue Firmware
3198 * commands). The format of the Serial Configuration version is
3199 * adapter specific. Returns 0 on success, an error on failure.
3201 * Note that early versions of the Firmware didn't include the ability
3202 * to retrieve the Serial Configuration version, so we zero-out the
3203 * return-value parameter in that case to avoid leaving it with
3206 * Also note that the Firmware will return its cached copy of the Serial
3207 * Initialization Revision ID, not the actual Revision ID as written in
3208 * the Serial EEPROM. This is only an issue if a new VPD has been written
3209 * and the Firmware/Chip haven't yet gone through a RESET sequence. So
3210 * it's best to defer calling this routine till after a FW_RESET_CMD has
3211 * been issued if the Host Driver will be performing a full adapter
3214 int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3219 scfgrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3220 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_SCFGREV));
3221 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3222 1, &scfgrev_param, vers);
3229 * t4_get_version_info - extract various chip/firmware version information
3230 * @adapter: the adapter
3232 * Reads various chip/firmware version numbers and stores them into the
3233 * adapter Adapter Parameters structure. If any of the efforts fails
3234 * the first failure will be returned, but all of the version numbers
3237 int t4_get_version_info(struct adapter *adapter)
3241 #define FIRST_RET(__getvinfo) \
3243 int __ret = __getvinfo; \
3244 if (__ret && !ret) \
3248 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3249 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3250 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3251 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3252 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3253 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3260 * t4_dump_version_info - dump all of the adapter configuration IDs
3261 * @adapter: the adapter
3263 * Dumps all of the various bits of adapter configuration version/revision
3264 * IDs information. This is typically called at some point after
3265 * t4_get_version_info() has been called.
3267 void t4_dump_version_info(struct adapter *adapter)
3269 /* Device information */
3270 dev_info(adapter->pdev_dev, "Chelsio %s rev %d\n",
3271 adapter->params.vpd.id,
3272 CHELSIO_CHIP_RELEASE(adapter->params.chip));
3273 dev_info(adapter->pdev_dev, "S/N: %s, P/N: %s\n",
3274 adapter->params.vpd.sn, adapter->params.vpd.pn);
3276 /* Firmware Version */
3277 if (!adapter->params.fw_vers)
3278 dev_warn(adapter->pdev_dev, "No firmware loaded\n");
3280 dev_info(adapter->pdev_dev, "Firmware version: %u.%u.%u.%u\n",
3281 FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
3282 FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
3283 FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
3284 FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers));
3286 /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap
3287 * Firmware, so dev_info() is more appropriate here.)
3289 if (!adapter->params.bs_vers)
3290 dev_info(adapter->pdev_dev, "No bootstrap loaded\n");
3292 dev_info(adapter->pdev_dev, "Bootstrap version: %u.%u.%u.%u\n",
3293 FW_HDR_FW_VER_MAJOR_G(adapter->params.bs_vers),
3294 FW_HDR_FW_VER_MINOR_G(adapter->params.bs_vers),
3295 FW_HDR_FW_VER_MICRO_G(adapter->params.bs_vers),
3296 FW_HDR_FW_VER_BUILD_G(adapter->params.bs_vers));
3298 /* TP Microcode Version */
3299 if (!adapter->params.tp_vers)
3300 dev_warn(adapter->pdev_dev, "No TP Microcode loaded\n");
3302 dev_info(adapter->pdev_dev,
3303 "TP Microcode version: %u.%u.%u.%u\n",
3304 FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
3305 FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
3306 FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
3307 FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
3309 /* Expansion ROM version */
3310 if (!adapter->params.er_vers)
3311 dev_info(adapter->pdev_dev, "No Expansion ROM loaded\n");
3313 dev_info(adapter->pdev_dev,
3314 "Expansion ROM version: %u.%u.%u.%u\n",
3315 FW_HDR_FW_VER_MAJOR_G(adapter->params.er_vers),
3316 FW_HDR_FW_VER_MINOR_G(adapter->params.er_vers),
3317 FW_HDR_FW_VER_MICRO_G(adapter->params.er_vers),
3318 FW_HDR_FW_VER_BUILD_G(adapter->params.er_vers));
3320 /* Serial Configuration version */
3321 dev_info(adapter->pdev_dev, "Serial Configuration version: %#x\n",
3322 adapter->params.scfg_vers);
3325 dev_info(adapter->pdev_dev, "VPD version: %#x\n",
3326 adapter->params.vpd_vers);
3330 * t4_check_fw_version - check if the FW is supported with this driver
3331 * @adap: the adapter
3333 * Checks if an adapter's FW is compatible with the driver. Returns 0
3334 * if there's exact match, a negative error if the version could not be
3335 * read or there's a major version mismatch
3337 int t4_check_fw_version(struct adapter *adap)
3339 int i, ret, major, minor, micro;
3340 int exp_major, exp_minor, exp_micro;
3341 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3343 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3344 /* Try multiple times before returning error */
3345 for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3346 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3351 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3352 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3353 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3355 switch (chip_version) {
3357 exp_major = T4FW_MIN_VERSION_MAJOR;
3358 exp_minor = T4FW_MIN_VERSION_MINOR;
3359 exp_micro = T4FW_MIN_VERSION_MICRO;
3362 exp_major = T5FW_MIN_VERSION_MAJOR;
3363 exp_minor = T5FW_MIN_VERSION_MINOR;
3364 exp_micro = T5FW_MIN_VERSION_MICRO;
3367 exp_major = T6FW_MIN_VERSION_MAJOR;
3368 exp_minor = T6FW_MIN_VERSION_MINOR;
3369 exp_micro = T6FW_MIN_VERSION_MICRO;
3372 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3377 if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3378 (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3379 dev_err(adap->pdev_dev,
3380 "Card has firmware version %u.%u.%u, minimum "
3381 "supported firmware is %u.%u.%u.\n", major, minor,
3382 micro, exp_major, exp_minor, exp_micro);
3388 /* Is the given firmware API compatible with the one the driver was compiled
3391 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3394 /* short circuit if it's the exact same firmware version */
3395 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3398 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3399 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3400 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3407 /* The firmware in the filesystem is usable, but should it be installed?
3408 * This routine explains itself in detail if it indicates the filesystem
3409 * firmware should be installed.
3411 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3416 if (!card_fw_usable) {
3417 reason = "incompatible or unusable";
3422 reason = "older than the version supported with this driver";
3429 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3430 "installing firmware %u.%u.%u.%u on card.\n",
3431 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3432 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3433 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3434 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3439 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3440 const u8 *fw_data, unsigned int fw_size,
3441 struct fw_hdr *card_fw, enum dev_state state,
3444 int ret, card_fw_usable, fs_fw_usable;
3445 const struct fw_hdr *fs_fw;
3446 const struct fw_hdr *drv_fw;
3448 drv_fw = &fw_info->fw_hdr;
3450 /* Read the header of the firmware on the card */
3451 ret = -t4_read_flash(adap, FLASH_FW_START,
3452 sizeof(*card_fw) / sizeof(uint32_t),
3453 (uint32_t *)card_fw, 1);
3455 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3457 dev_err(adap->pdev_dev,
3458 "Unable to read card's firmware header: %d\n", ret);
3462 if (fw_data != NULL) {
3463 fs_fw = (const void *)fw_data;
3464 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3470 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3471 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3472 /* Common case: the firmware on the card is an exact match and
3473 * the filesystem one is an exact match too, or the filesystem
3474 * one is absent/incompatible.
3476 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3477 should_install_fs_fw(adap, card_fw_usable,
3478 be32_to_cpu(fs_fw->fw_ver),
3479 be32_to_cpu(card_fw->fw_ver))) {
3480 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
3483 dev_err(adap->pdev_dev,
3484 "failed to install firmware: %d\n", ret);
3488 /* Installed successfully, update the cached header too. */
3491 *reset = 0; /* already reset as part of load_fw */
3494 if (!card_fw_usable) {
3497 d = be32_to_cpu(drv_fw->fw_ver);
3498 c = be32_to_cpu(card_fw->fw_ver);
3499 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3501 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3503 "driver compiled with %d.%d.%d.%d, "
3504 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3506 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3507 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3508 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3509 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3510 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3511 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3516 /* We're using whatever's on the card and it's known to be good. */
3517 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3518 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3525 * t4_flash_erase_sectors - erase a range of flash sectors
3526 * @adapter: the adapter
3527 * @start: the first sector to erase
3528 * @end: the last sector to erase
3530 * Erases the sectors in the given inclusive range.
3532 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3536 if (end >= adapter->params.sf_nsec)
3539 while (start <= end) {
3540 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3541 (ret = sf1_write(adapter, 4, 0, 1,
3542 SF_ERASE_SECTOR | (start << 8))) != 0 ||
3543 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3544 dev_err(adapter->pdev_dev,
3545 "erase of flash sector %d failed, error %d\n",
3551 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3556 * t4_flash_cfg_addr - return the address of the flash configuration file
3557 * @adapter: the adapter
3559 * Return the address within the flash where the Firmware Configuration
3562 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3564 if (adapter->params.sf_size == 0x100000)
3565 return FLASH_FPGA_CFG_START;
3567 return FLASH_CFG_START;
3570 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
3571 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3572 * and emit an error message for mismatched firmware to save our caller the
3575 static bool t4_fw_matches_chip(const struct adapter *adap,
3576 const struct fw_hdr *hdr)
3578 /* The expression below will return FALSE for any unsupported adapter
3579 * which will keep us "honest" in the future ...
3581 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3582 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3583 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3586 dev_err(adap->pdev_dev,
3587 "FW image (%d) is not suitable for this adapter (%d)\n",
3588 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3593 * t4_load_fw - download firmware
3594 * @adap: the adapter
3595 * @fw_data: the firmware image to write
3598 * Write the supplied firmware image to the card's serial flash.
3600 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3605 u8 first_page[SF_PAGE_SIZE];
3606 const __be32 *p = (const __be32 *)fw_data;
3607 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3608 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3609 unsigned int fw_start_sec = FLASH_FW_START_SEC;
3610 unsigned int fw_size = FLASH_FW_MAX_SIZE;
3611 unsigned int fw_start = FLASH_FW_START;
3614 dev_err(adap->pdev_dev, "FW image has no data\n");
3618 dev_err(adap->pdev_dev,
3619 "FW image size not multiple of 512 bytes\n");
3622 if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3623 dev_err(adap->pdev_dev,
3624 "FW image size differs from size in FW header\n");
3627 if (size > fw_size) {
3628 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3632 if (!t4_fw_matches_chip(adap, hdr))
3635 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3636 csum += be32_to_cpu(p[i]);
3638 if (csum != 0xffffffff) {
3639 dev_err(adap->pdev_dev,
3640 "corrupted firmware image, checksum %#x\n", csum);
3644 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
3645 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3650 * We write the correct version at the end so the driver can see a bad
3651 * version if the FW write fails. Start by writing a copy of the
3652 * first page with a bad version.
3654 memcpy(first_page, fw_data, SF_PAGE_SIZE);
3655 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3656 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page);
3661 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3662 addr += SF_PAGE_SIZE;
3663 fw_data += SF_PAGE_SIZE;
3664 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3669 ret = t4_write_flash(adap,
3670 fw_start + offsetof(struct fw_hdr, fw_ver),
3671 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3674 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3677 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3682 * t4_phy_fw_ver - return current PHY firmware version
3683 * @adap: the adapter
3684 * @phy_fw_ver: return value buffer for PHY firmware version
3686 * Returns the current version of external PHY firmware on the
3689 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3694 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3695 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3696 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3697 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3698 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3707 * t4_load_phy_fw - download port PHY firmware
3708 * @adap: the adapter
3709 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3710 * @win_lock: the lock to use to guard the memory copy
3711 * @phy_fw_version: function to check PHY firmware versions
3712 * @phy_fw_data: the PHY firmware image to write
3713 * @phy_fw_size: image size
3715 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3716 * @phy_fw_version is supplied, then it will be used to determine if
3717 * it's necessary to perform the transfer by comparing the version
3718 * of any existing adapter PHY firmware with that of the passed in
3719 * PHY firmware image. If @win_lock is non-NULL then it will be used
3720 * around the call to t4_memory_rw() which transfers the PHY firmware
3723 * A negative error number will be returned if an error occurs. If
3724 * version number support is available and there's no need to upgrade
3725 * the firmware, 0 will be returned. If firmware is successfully
3726 * transferred to the adapter, 1 will be retured.
3728 * NOTE: some adapters only have local RAM to store the PHY firmware. As
3729 * a result, a RESET of the adapter would cause that RAM to lose its
3730 * contents. Thus, loading PHY firmware on such adapters must happen
3731 * after any FW_RESET_CMDs ...
3733 int t4_load_phy_fw(struct adapter *adap,
3734 int win, spinlock_t *win_lock,
3735 int (*phy_fw_version)(const u8 *, size_t),
3736 const u8 *phy_fw_data, size_t phy_fw_size)
3738 unsigned long mtype = 0, maddr = 0;
3740 int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3743 /* If we have version number support, then check to see if the adapter
3744 * already has up-to-date PHY firmware loaded.
3746 if (phy_fw_version) {
3747 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3748 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3752 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3753 CH_WARN(adap, "PHY Firmware already up-to-date, "
3754 "version %#x\n", cur_phy_fw_ver);
3759 /* Ask the firmware where it wants us to copy the PHY firmware image.
3760 * The size of the file requires a special version of the READ coommand
3761 * which will pass the file size via the values field in PARAMS_CMD and
3762 * retrieve the return value from firmware and place it in the same
3765 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3766 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3767 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3768 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3770 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3771 ¶m, &val, 1, true);
3775 maddr = (val & 0xff) << 16;
3777 /* Copy the supplied PHY Firmware image to the adapter memory location
3778 * allocated by the adapter firmware.
3781 spin_lock_bh(win_lock);
3782 ret = t4_memory_rw(adap, win, mtype, maddr,
3783 phy_fw_size, (__be32 *)phy_fw_data,
3786 spin_unlock_bh(win_lock);
3790 /* Tell the firmware that the PHY firmware image has been written to
3791 * RAM and it can now start copying it over to the PHYs. The chip
3792 * firmware will RESET the affected PHYs as part of this operation
3793 * leaving them running the new PHY firmware image.
3795 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3796 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3797 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3798 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3799 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3800 ¶m, &val, 30000);
3802 /* If we have version number support, then check to see that the new
3803 * firmware got loaded properly.
3805 if (phy_fw_version) {
3806 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3810 if (cur_phy_fw_ver != new_phy_fw_vers) {
3811 CH_WARN(adap, "PHY Firmware did not update: "
3812 "version on adapter %#x, "
3813 "version flashed %#x\n",
3814 cur_phy_fw_ver, new_phy_fw_vers);
3823 * t4_fwcache - firmware cache operation
3824 * @adap: the adapter
3825 * @op : the operation (flush or flush and invalidate)
3827 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3829 struct fw_params_cmd c;
3831 memset(&c, 0, sizeof(c));
3833 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3834 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3835 FW_PARAMS_CMD_PFN_V(adap->pf) |
3836 FW_PARAMS_CMD_VFN_V(0));
3837 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3839 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3840 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3841 c.param[0].val = (__force __be32)op;
3843 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3846 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3847 unsigned int *pif_req_wrptr,
3848 unsigned int *pif_rsp_wrptr)
3851 u32 cfg, val, req, rsp;
3853 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3854 if (cfg & LADBGEN_F)
3855 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3857 val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3858 req = POLADBGWRPTR_G(val);
3859 rsp = PILADBGWRPTR_G(val);
3861 *pif_req_wrptr = req;
3863 *pif_rsp_wrptr = rsp;
3865 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3866 for (j = 0; j < 6; j++) {
3867 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3868 PILADBGRDPTR_V(rsp));
3869 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3870 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3874 req = (req + 2) & POLADBGRDPTR_M;
3875 rsp = (rsp + 2) & PILADBGRDPTR_M;
3877 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3880 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3885 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3886 if (cfg & LADBGEN_F)
3887 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3889 for (i = 0; i < CIM_MALA_SIZE; i++) {
3890 for (j = 0; j < 5; j++) {
3892 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3893 PILADBGRDPTR_V(idx));
3894 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3895 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3898 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3901 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3905 for (i = 0; i < 8; i++) {
3906 u32 *p = la_buf + i;
3908 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3909 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3910 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3911 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3912 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3916 #define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
3920 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3921 * @caps16: a 16-bit Port Capabilities value
3923 * Returns the equivalent 32-bit Port Capabilities value.
3925 static fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
3927 fw_port_cap32_t caps32 = 0;
3929 #define CAP16_TO_CAP32(__cap) \
3931 if (caps16 & FW_PORT_CAP_##__cap) \
3932 caps32 |= FW_PORT_CAP32_##__cap; \
3935 CAP16_TO_CAP32(SPEED_100M);
3936 CAP16_TO_CAP32(SPEED_1G);
3937 CAP16_TO_CAP32(SPEED_25G);
3938 CAP16_TO_CAP32(SPEED_10G);
3939 CAP16_TO_CAP32(SPEED_40G);
3940 CAP16_TO_CAP32(SPEED_100G);
3941 CAP16_TO_CAP32(FC_RX);
3942 CAP16_TO_CAP32(FC_TX);
3943 CAP16_TO_CAP32(ANEG);
3944 CAP16_TO_CAP32(FORCE_PAUSE);
3945 CAP16_TO_CAP32(MDIAUTO);
3946 CAP16_TO_CAP32(MDISTRAIGHT);
3947 CAP16_TO_CAP32(FEC_RS);
3948 CAP16_TO_CAP32(FEC_BASER_RS);
3949 CAP16_TO_CAP32(802_3_PAUSE);
3950 CAP16_TO_CAP32(802_3_ASM_DIR);
3952 #undef CAP16_TO_CAP32
3958 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
3959 * @caps32: a 32-bit Port Capabilities value
3961 * Returns the equivalent 16-bit Port Capabilities value. Note that
3962 * not all 32-bit Port Capabilities can be represented in the 16-bit
3963 * Port Capabilities and some fields/values may not make it.
3965 static fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32)
3967 fw_port_cap16_t caps16 = 0;
3969 #define CAP32_TO_CAP16(__cap) \
3971 if (caps32 & FW_PORT_CAP32_##__cap) \
3972 caps16 |= FW_PORT_CAP_##__cap; \
3975 CAP32_TO_CAP16(SPEED_100M);
3976 CAP32_TO_CAP16(SPEED_1G);
3977 CAP32_TO_CAP16(SPEED_10G);
3978 CAP32_TO_CAP16(SPEED_25G);
3979 CAP32_TO_CAP16(SPEED_40G);
3980 CAP32_TO_CAP16(SPEED_100G);
3981 CAP32_TO_CAP16(FC_RX);
3982 CAP32_TO_CAP16(FC_TX);
3983 CAP32_TO_CAP16(802_3_PAUSE);
3984 CAP32_TO_CAP16(802_3_ASM_DIR);
3985 CAP32_TO_CAP16(ANEG);
3986 CAP32_TO_CAP16(FORCE_PAUSE);
3987 CAP32_TO_CAP16(MDIAUTO);
3988 CAP32_TO_CAP16(MDISTRAIGHT);
3989 CAP32_TO_CAP16(FEC_RS);
3990 CAP32_TO_CAP16(FEC_BASER_RS);
3992 #undef CAP32_TO_CAP16
3997 /* Translate Firmware Port Capabilities Pause specification to Common Code */
3998 static inline enum cc_pause fwcap_to_cc_pause(fw_port_cap32_t fw_pause)
4000 enum cc_pause cc_pause = 0;
4002 if (fw_pause & FW_PORT_CAP32_FC_RX)
4003 cc_pause |= PAUSE_RX;
4004 if (fw_pause & FW_PORT_CAP32_FC_TX)
4005 cc_pause |= PAUSE_TX;
4010 /* Translate Common Code Pause specification into Firmware Port Capabilities */
4011 static inline fw_port_cap32_t cc_to_fwcap_pause(enum cc_pause cc_pause)
4013 fw_port_cap32_t fw_pause = 0;
4015 if (cc_pause & PAUSE_RX)
4016 fw_pause |= FW_PORT_CAP32_FC_RX;
4017 if (cc_pause & PAUSE_TX)
4018 fw_pause |= FW_PORT_CAP32_FC_TX;
4019 if (!(cc_pause & PAUSE_AUTONEG))
4020 fw_pause |= FW_PORT_CAP32_FORCE_PAUSE;
4025 /* Translate Firmware Forward Error Correction specification to Common Code */
4026 static inline enum cc_fec fwcap_to_cc_fec(fw_port_cap32_t fw_fec)
4028 enum cc_fec cc_fec = 0;
4030 if (fw_fec & FW_PORT_CAP32_FEC_RS)
4032 if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
4033 cc_fec |= FEC_BASER_RS;
4038 /* Translate Common Code Forward Error Correction specification to Firmware */
4039 static inline fw_port_cap32_t cc_to_fwcap_fec(enum cc_fec cc_fec)
4041 fw_port_cap32_t fw_fec = 0;
4043 if (cc_fec & FEC_RS)
4044 fw_fec |= FW_PORT_CAP32_FEC_RS;
4045 if (cc_fec & FEC_BASER_RS)
4046 fw_fec |= FW_PORT_CAP32_FEC_BASER_RS;
4052 * t4_link_l1cfg - apply link configuration to MAC/PHY
4053 * @adapter: the adapter
4054 * @mbox: the Firmware Mailbox to use
4055 * @port: the Port ID
4056 * @lc: the Port's Link Configuration
4058 * Set up a port's MAC and PHY according to a desired link configuration.
4059 * - If the PHY can auto-negotiate first decide what to advertise, then
4060 * enable/disable auto-negotiation as desired, and reset.
4061 * - If the PHY does not auto-negotiate just reset it.
4062 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
4063 * otherwise do it later based on the outcome of auto-negotiation.
4065 int t4_link_l1cfg_core(struct adapter *adapter, unsigned int mbox,
4066 unsigned int port, struct link_config *lc,
4067 bool sleep_ok, int timeout)
4069 unsigned int fw_caps = adapter->params.fw_caps_support;
4070 fw_port_cap32_t fw_fc, cc_fec, fw_fec, rcap;
4071 struct fw_port_cmd cmd;
4072 unsigned int fw_mdi;
4075 fw_mdi = (FW_PORT_CAP32_MDI_V(FW_PORT_CAP32_MDI_AUTO) & lc->pcaps);
4076 /* Convert driver coding of Pause Frame Flow Control settings into the
4079 fw_fc = cc_to_fwcap_pause(lc->requested_fc);
4081 /* Convert Common Code Forward Error Control settings into the
4082 * Firmware's API. If the current Requested FEC has "Automatic"
4083 * (IEEE 802.3) specified, then we use whatever the Firmware
4084 * sent us as part of it's IEEE 802.3-based interpratation of
4085 * the Transceiver Module EPROM FEC parameters. Otherwise we
4086 * use whatever is in the current Requested FEC settings.
4088 if (lc->requested_fec & FEC_AUTO)
4089 cc_fec = fwcap_to_cc_fec(lc->def_acaps);
4091 cc_fec = lc->requested_fec;
4092 fw_fec = cc_to_fwcap_fec(cc_fec);
4094 /* Figure out what our Requested Port Capabilities are going to be.
4096 if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
4097 rcap = lc->acaps | fw_fc | fw_fec;
4098 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4100 } else if (lc->autoneg == AUTONEG_DISABLE) {
4101 rcap = lc->speed_caps | fw_fc | fw_fec | fw_mdi;
4102 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4105 rcap = lc->acaps | fw_fc | fw_fec | fw_mdi;
4108 /* Note that older Firmware doesn't have FW_PORT_CAP32_FORCE_PAUSE, so
4109 * we need to exclude this from this check in order to maintain
4112 if ((rcap & ~lc->pcaps) & ~FW_PORT_CAP32_FORCE_PAUSE) {
4113 dev_err(adapter->pdev_dev,
4114 "Requested Port Capabilities %#x exceed Physical Port Capabilities %#x\n",
4119 /* And send that on to the Firmware ...
4121 memset(&cmd, 0, sizeof(cmd));
4122 cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4123 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4124 FW_PORT_CMD_PORTID_V(port));
4125 cmd.action_to_len16 =
4126 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4127 ? FW_PORT_ACTION_L1_CFG
4128 : FW_PORT_ACTION_L1_CFG32) |
4130 if (fw_caps == FW_CAPS16)
4131 cmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
4133 cmd.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
4135 ret = t4_wr_mbox_meat_timeout(adapter, mbox, &cmd, sizeof(cmd), NULL,
4138 dev_err(adapter->pdev_dev,
4139 "Requested Port Capabilities %#x rejected, error %d\n",
4147 * t4_restart_aneg - restart autonegotiation
4148 * @adap: the adapter
4149 * @mbox: mbox to use for the FW command
4150 * @port: the port id
4152 * Restarts autonegotiation for the selected port.
4154 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
4156 struct fw_port_cmd c;
4158 memset(&c, 0, sizeof(c));
4159 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4160 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4161 FW_PORT_CMD_PORTID_V(port));
4163 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
4165 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP32_ANEG);
4166 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4169 typedef void (*int_handler_t)(struct adapter *adap);
4172 unsigned int mask; /* bits to check in interrupt status */
4173 const char *msg; /* message to print or NULL */
4174 short stat_idx; /* stat counter to increment or -1 */
4175 unsigned short fatal; /* whether the condition reported is fatal */
4176 int_handler_t int_handler; /* platform-specific int handler */
4180 * t4_handle_intr_status - table driven interrupt handler
4181 * @adapter: the adapter that generated the interrupt
4182 * @reg: the interrupt status register to process
4183 * @acts: table of interrupt actions
4185 * A table driven interrupt handler that applies a set of masks to an
4186 * interrupt status word and performs the corresponding actions if the
4187 * interrupts described by the mask have occurred. The actions include
4188 * optionally emitting a warning or alert message. The table is terminated
4189 * by an entry specifying mask 0. Returns the number of fatal interrupt
4192 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
4193 const struct intr_info *acts)
4196 unsigned int mask = 0;
4197 unsigned int status = t4_read_reg(adapter, reg);
4199 for ( ; acts->mask; ++acts) {
4200 if (!(status & acts->mask))
4204 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4205 status & acts->mask);
4206 } else if (acts->msg && printk_ratelimit())
4207 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4208 status & acts->mask);
4209 if (acts->int_handler)
4210 acts->int_handler(adapter);
4214 if (status) /* clear processed interrupts */
4215 t4_write_reg(adapter, reg, status);
4220 * Interrupt handler for the PCIE module.
4222 static void pcie_intr_handler(struct adapter *adapter)
4224 static const struct intr_info sysbus_intr_info[] = {
4225 { RNPP_F, "RXNP array parity error", -1, 1 },
4226 { RPCP_F, "RXPC array parity error", -1, 1 },
4227 { RCIP_F, "RXCIF array parity error", -1, 1 },
4228 { RCCP_F, "Rx completions control array parity error", -1, 1 },
4229 { RFTP_F, "RXFT array parity error", -1, 1 },
4232 static const struct intr_info pcie_port_intr_info[] = {
4233 { TPCP_F, "TXPC array parity error", -1, 1 },
4234 { TNPP_F, "TXNP array parity error", -1, 1 },
4235 { TFTP_F, "TXFT array parity error", -1, 1 },
4236 { TCAP_F, "TXCA array parity error", -1, 1 },
4237 { TCIP_F, "TXCIF array parity error", -1, 1 },
4238 { RCAP_F, "RXCA array parity error", -1, 1 },
4239 { OTDD_F, "outbound request TLP discarded", -1, 1 },
4240 { RDPE_F, "Rx data parity error", -1, 1 },
4241 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
4244 static const struct intr_info pcie_intr_info[] = {
4245 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
4246 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
4247 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
4248 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4249 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4250 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4251 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4252 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
4253 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
4254 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4255 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
4256 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4257 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4258 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
4259 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4260 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4261 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
4262 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4263 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4264 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4265 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4266 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
4267 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
4268 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4269 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
4270 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
4271 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
4272 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
4273 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
4274 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
4279 static struct intr_info t5_pcie_intr_info[] = {
4280 { MSTGRPPERR_F, "Master Response Read Queue parity error",
4282 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
4283 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
4284 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4285 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4286 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4287 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4288 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
4290 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
4292 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4293 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
4294 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4295 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4296 { DREQWRPERR_F, "PCI DMA channel write request parity error",
4298 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4299 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4300 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
4301 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4302 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4303 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4304 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4305 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
4306 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
4307 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4308 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
4310 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
4312 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
4313 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
4314 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
4315 { READRSPERR_F, "Outbound read error", -1, 0 },
4321 if (is_t4(adapter->params.chip))
4322 fat = t4_handle_intr_status(adapter,
4323 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
4325 t4_handle_intr_status(adapter,
4326 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
4327 pcie_port_intr_info) +
4328 t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4331 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4335 t4_fatal_err(adapter);
4339 * TP interrupt handler.
4341 static void tp_intr_handler(struct adapter *adapter)
4343 static const struct intr_info tp_intr_info[] = {
4344 { 0x3fffffff, "TP parity error", -1, 1 },
4345 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
4349 if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
4350 t4_fatal_err(adapter);
4354 * SGE interrupt handler.
4356 static void sge_intr_handler(struct adapter *adapter)
4361 static const struct intr_info sge_intr_info[] = {
4362 { ERR_CPL_EXCEED_IQE_SIZE_F,
4363 "SGE received CPL exceeding IQE size", -1, 1 },
4364 { ERR_INVALID_CIDX_INC_F,
4365 "SGE GTS CIDX increment too large", -1, 0 },
4366 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
4367 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
4368 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
4369 "SGE IQID > 1023 received CPL for FL", -1, 0 },
4370 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
4372 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
4374 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
4376 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
4378 { ERR_ING_CTXT_PRIO_F,
4379 "SGE too many priority ingress contexts", -1, 0 },
4380 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
4381 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
4385 static struct intr_info t4t5_sge_intr_info[] = {
4386 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
4387 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
4388 { ERR_EGR_CTXT_PRIO_F,
4389 "SGE too many priority egress contexts", -1, 0 },
4393 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
4394 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
4396 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
4397 (unsigned long long)v);
4398 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
4399 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
4402 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
4403 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4404 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
4405 t4t5_sge_intr_info);
4407 err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
4408 if (err & ERROR_QID_VALID_F) {
4409 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
4411 if (err & UNCAPTURED_ERROR_F)
4412 dev_err(adapter->pdev_dev,
4413 "SGE UNCAPTURED_ERROR set (clearing)\n");
4414 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
4415 UNCAPTURED_ERROR_F);
4419 t4_fatal_err(adapter);
4422 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4423 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4424 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4425 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4428 * CIM interrupt handler.
4430 static void cim_intr_handler(struct adapter *adapter)
4432 static const struct intr_info cim_intr_info[] = {
4433 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
4434 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4435 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4436 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
4437 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
4438 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
4439 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
4440 { TIMER0INT_F, "CIM TIMER0 interrupt", -1, 1 },
4443 static const struct intr_info cim_upintr_info[] = {
4444 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
4445 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
4446 { ILLWRINT_F, "CIM illegal write", -1, 1 },
4447 { ILLRDINT_F, "CIM illegal read", -1, 1 },
4448 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
4449 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
4450 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
4451 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
4452 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
4453 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
4454 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
4455 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
4456 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
4457 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
4458 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
4459 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
4460 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
4461 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
4462 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
4463 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
4464 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
4465 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
4466 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
4467 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
4468 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
4469 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
4470 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
4471 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4478 fw_err = t4_read_reg(adapter, PCIE_FW_A);
4479 if (fw_err & PCIE_FW_ERR_F)
4480 t4_report_fw_error(adapter);
4482 /* When the Firmware detects an internal error which normally
4483 * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
4484 * in order to make sure the Host sees the Firmware Crash. So
4485 * if we have a Timer0 interrupt and don't see a Firmware Crash,
4486 * ignore the Timer0 interrupt.
4489 val = t4_read_reg(adapter, CIM_HOST_INT_CAUSE_A);
4490 if (val & TIMER0INT_F)
4491 if (!(fw_err & PCIE_FW_ERR_F) ||
4492 (PCIE_FW_EVAL_G(fw_err) != PCIE_FW_EVAL_CRASH))
4493 t4_write_reg(adapter, CIM_HOST_INT_CAUSE_A,
4496 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4498 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4501 t4_fatal_err(adapter);
4505 * ULP RX interrupt handler.
4507 static void ulprx_intr_handler(struct adapter *adapter)
4509 static const struct intr_info ulprx_intr_info[] = {
4510 { 0x1800000, "ULPRX context error", -1, 1 },
4511 { 0x7fffff, "ULPRX parity error", -1, 1 },
4515 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4516 t4_fatal_err(adapter);
4520 * ULP TX interrupt handler.
4522 static void ulptx_intr_handler(struct adapter *adapter)
4524 static const struct intr_info ulptx_intr_info[] = {
4525 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4527 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4529 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4531 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4533 { 0xfffffff, "ULPTX parity error", -1, 1 },
4537 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4538 t4_fatal_err(adapter);
4542 * PM TX interrupt handler.
4544 static void pmtx_intr_handler(struct adapter *adapter)
4546 static const struct intr_info pmtx_intr_info[] = {
4547 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4548 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4549 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4550 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4551 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4552 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4553 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4555 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4556 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4560 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4561 t4_fatal_err(adapter);
4565 * PM RX interrupt handler.
4567 static void pmrx_intr_handler(struct adapter *adapter)
4569 static const struct intr_info pmrx_intr_info[] = {
4570 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4571 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4572 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4573 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4575 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4576 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4580 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4581 t4_fatal_err(adapter);
4585 * CPL switch interrupt handler.
4587 static void cplsw_intr_handler(struct adapter *adapter)
4589 static const struct intr_info cplsw_intr_info[] = {
4590 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4591 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4592 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4593 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4594 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4595 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4599 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4600 t4_fatal_err(adapter);
4604 * LE interrupt handler.
4606 static void le_intr_handler(struct adapter *adap)
4608 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4609 static const struct intr_info le_intr_info[] = {
4610 { LIPMISS_F, "LE LIP miss", -1, 0 },
4611 { LIP0_F, "LE 0 LIP error", -1, 0 },
4612 { PARITYERR_F, "LE parity error", -1, 1 },
4613 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4614 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4618 static struct intr_info t6_le_intr_info[] = {
4619 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4620 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4621 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4622 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4623 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4627 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4628 (chip <= CHELSIO_T5) ?
4629 le_intr_info : t6_le_intr_info))
4634 * MPS interrupt handler.
4636 static void mps_intr_handler(struct adapter *adapter)
4638 static const struct intr_info mps_rx_intr_info[] = {
4639 { 0xffffff, "MPS Rx parity error", -1, 1 },
4642 static const struct intr_info mps_tx_intr_info[] = {
4643 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4644 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4645 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4647 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4649 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4650 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4651 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4654 static const struct intr_info t6_mps_tx_intr_info[] = {
4655 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4656 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4657 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4659 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4661 /* MPS Tx Bubble is normal for T6 */
4662 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4663 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4666 static const struct intr_info mps_trc_intr_info[] = {
4667 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4668 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4670 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4673 static const struct intr_info mps_stat_sram_intr_info[] = {
4674 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4677 static const struct intr_info mps_stat_tx_intr_info[] = {
4678 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4681 static const struct intr_info mps_stat_rx_intr_info[] = {
4682 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4685 static const struct intr_info mps_cls_intr_info[] = {
4686 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4687 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4688 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4694 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4696 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4697 is_t6(adapter->params.chip)
4698 ? t6_mps_tx_intr_info
4699 : mps_tx_intr_info) +
4700 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4701 mps_trc_intr_info) +
4702 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4703 mps_stat_sram_intr_info) +
4704 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4705 mps_stat_tx_intr_info) +
4706 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4707 mps_stat_rx_intr_info) +
4708 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4711 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4712 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */
4714 t4_fatal_err(adapter);
4717 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4721 * EDC/MC interrupt handler.
4723 static void mem_intr_handler(struct adapter *adapter, int idx)
4725 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4727 unsigned int addr, cnt_addr, v;
4729 if (idx <= MEM_EDC1) {
4730 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4731 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4732 } else if (idx == MEM_MC) {
4733 if (is_t4(adapter->params.chip)) {
4734 addr = MC_INT_CAUSE_A;
4735 cnt_addr = MC_ECC_STATUS_A;
4737 addr = MC_P_INT_CAUSE_A;
4738 cnt_addr = MC_P_ECC_STATUS_A;
4741 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4742 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4745 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4746 if (v & PERR_INT_CAUSE_F)
4747 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4749 if (v & ECC_CE_INT_CAUSE_F) {
4750 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4752 t4_edc_err_read(adapter, idx);
4754 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4755 if (printk_ratelimit())
4756 dev_warn(adapter->pdev_dev,
4757 "%u %s correctable ECC data error%s\n",
4758 cnt, name[idx], cnt > 1 ? "s" : "");
4760 if (v & ECC_UE_INT_CAUSE_F)
4761 dev_alert(adapter->pdev_dev,
4762 "%s uncorrectable ECC data error\n", name[idx]);
4764 t4_write_reg(adapter, addr, v);
4765 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4766 t4_fatal_err(adapter);
4770 * MA interrupt handler.
4772 static void ma_intr_handler(struct adapter *adap)
4774 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4776 if (status & MEM_PERR_INT_CAUSE_F) {
4777 dev_alert(adap->pdev_dev,
4778 "MA parity error, parity status %#x\n",
4779 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4780 if (is_t5(adap->params.chip))
4781 dev_alert(adap->pdev_dev,
4782 "MA parity error, parity status %#x\n",
4784 MA_PARITY_ERROR_STATUS2_A));
4786 if (status & MEM_WRAP_INT_CAUSE_F) {
4787 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4788 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4789 "client %u to address %#x\n",
4790 MEM_WRAP_CLIENT_NUM_G(v),
4791 MEM_WRAP_ADDRESS_G(v) << 4);
4793 t4_write_reg(adap, MA_INT_CAUSE_A, status);
4798 * SMB interrupt handler.
4800 static void smb_intr_handler(struct adapter *adap)
4802 static const struct intr_info smb_intr_info[] = {
4803 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4804 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4805 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4809 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4814 * NC-SI interrupt handler.
4816 static void ncsi_intr_handler(struct adapter *adap)
4818 static const struct intr_info ncsi_intr_info[] = {
4819 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4820 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4821 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4822 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4826 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4831 * XGMAC interrupt handler.
4833 static void xgmac_intr_handler(struct adapter *adap, int port)
4835 u32 v, int_cause_reg;
4837 if (is_t4(adap->params.chip))
4838 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4840 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4842 v = t4_read_reg(adap, int_cause_reg);
4844 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4848 if (v & TXFIFO_PRTY_ERR_F)
4849 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4851 if (v & RXFIFO_PRTY_ERR_F)
4852 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4854 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4859 * PL interrupt handler.
4861 static void pl_intr_handler(struct adapter *adap)
4863 static const struct intr_info pl_intr_info[] = {
4864 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4865 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4869 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4873 #define PF_INTR_MASK (PFSW_F)
4874 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4875 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4876 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
4879 * t4_slow_intr_handler - control path interrupt handler
4880 * @adapter: the adapter
4882 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
4883 * The designation 'slow' is because it involves register reads, while
4884 * data interrupts typically don't involve any MMIOs.
4886 int t4_slow_intr_handler(struct adapter *adapter)
4888 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
4890 if (!(cause & GLBL_INTR_MASK))
4893 cim_intr_handler(adapter);
4895 mps_intr_handler(adapter);
4897 ncsi_intr_handler(adapter);
4899 pl_intr_handler(adapter);
4901 smb_intr_handler(adapter);
4902 if (cause & XGMAC0_F)
4903 xgmac_intr_handler(adapter, 0);
4904 if (cause & XGMAC1_F)
4905 xgmac_intr_handler(adapter, 1);
4906 if (cause & XGMAC_KR0_F)
4907 xgmac_intr_handler(adapter, 2);
4908 if (cause & XGMAC_KR1_F)
4909 xgmac_intr_handler(adapter, 3);
4911 pcie_intr_handler(adapter);
4913 mem_intr_handler(adapter, MEM_MC);
4914 if (is_t5(adapter->params.chip) && (cause & MC1_F))
4915 mem_intr_handler(adapter, MEM_MC1);
4917 mem_intr_handler(adapter, MEM_EDC0);
4919 mem_intr_handler(adapter, MEM_EDC1);
4921 le_intr_handler(adapter);
4923 tp_intr_handler(adapter);
4925 ma_intr_handler(adapter);
4926 if (cause & PM_TX_F)
4927 pmtx_intr_handler(adapter);
4928 if (cause & PM_RX_F)
4929 pmrx_intr_handler(adapter);
4930 if (cause & ULP_RX_F)
4931 ulprx_intr_handler(adapter);
4932 if (cause & CPL_SWITCH_F)
4933 cplsw_intr_handler(adapter);
4935 sge_intr_handler(adapter);
4936 if (cause & ULP_TX_F)
4937 ulptx_intr_handler(adapter);
4939 /* Clear the interrupts just processed for which we are the master. */
4940 t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
4941 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
4946 * t4_intr_enable - enable interrupts
4947 * @adapter: the adapter whose interrupts should be enabled
4949 * Enable PF-specific interrupts for the calling function and the top-level
4950 * interrupt concentrator for global interrupts. Interrupts are already
4951 * enabled at each module, here we just enable the roots of the interrupt
4954 * Note: this function should be called only when the driver manages
4955 * non PF-specific interrupts from the various HW modules. Only one PCI
4956 * function at a time should be doing this.
4958 void t4_intr_enable(struct adapter *adapter)
4961 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4962 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4963 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4965 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4966 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
4967 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
4968 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
4969 ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
4970 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
4971 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
4972 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
4973 DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
4974 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
4975 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
4979 * t4_intr_disable - disable interrupts
4980 * @adapter: the adapter whose interrupts should be disabled
4982 * Disable interrupts. We only disable the top-level interrupt
4983 * concentrators. The caller must be a PCI function managing global
4986 void t4_intr_disable(struct adapter *adapter)
4990 if (pci_channel_offline(adapter->pdev))
4993 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4994 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4995 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4997 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
4998 t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
5001 unsigned int t4_chip_rss_size(struct adapter *adap)
5003 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
5004 return RSS_NENTRIES;
5006 return T6_RSS_NENTRIES;
5010 * t4_config_rss_range - configure a portion of the RSS mapping table
5011 * @adapter: the adapter
5012 * @mbox: mbox to use for the FW command
5013 * @viid: virtual interface whose RSS subtable is to be written
5014 * @start: start entry in the table to write
5015 * @n: how many table entries to write
5016 * @rspq: values for the response queue lookup table
5017 * @nrspq: number of values in @rspq
5019 * Programs the selected part of the VI's RSS mapping table with the
5020 * provided values. If @nrspq < @n the supplied values are used repeatedly
5021 * until the full table range is populated.
5023 * The caller must ensure the values in @rspq are in the range allowed for
5026 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
5027 int start, int n, const u16 *rspq, unsigned int nrspq)
5030 const u16 *rsp = rspq;
5031 const u16 *rsp_end = rspq + nrspq;
5032 struct fw_rss_ind_tbl_cmd cmd;
5034 memset(&cmd, 0, sizeof(cmd));
5035 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
5036 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5037 FW_RSS_IND_TBL_CMD_VIID_V(viid));
5038 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
5040 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
5042 int nq = min(n, 32);
5043 __be32 *qp = &cmd.iq0_to_iq2;
5045 cmd.niqid = cpu_to_be16(nq);
5046 cmd.startidx = cpu_to_be16(start);
5054 v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
5055 if (++rsp >= rsp_end)
5057 v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
5058 if (++rsp >= rsp_end)
5060 v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
5061 if (++rsp >= rsp_end)
5064 *qp++ = cpu_to_be32(v);
5068 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
5076 * t4_config_glbl_rss - configure the global RSS mode
5077 * @adapter: the adapter
5078 * @mbox: mbox to use for the FW command
5079 * @mode: global RSS mode
5080 * @flags: mode-specific flags
5082 * Sets the global RSS mode.
5084 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
5087 struct fw_rss_glb_config_cmd c;
5089 memset(&c, 0, sizeof(c));
5090 c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
5091 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
5092 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5093 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
5094 c.u.manual.mode_pkd =
5095 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5096 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
5097 c.u.basicvirtual.mode_pkd =
5098 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5099 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
5102 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5106 * t4_config_vi_rss - configure per VI RSS settings
5107 * @adapter: the adapter
5108 * @mbox: mbox to use for the FW command
5111 * @defq: id of the default RSS queue for the VI.
5113 * Configures VI-specific RSS properties.
5115 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
5116 unsigned int flags, unsigned int defq)
5118 struct fw_rss_vi_config_cmd c;
5120 memset(&c, 0, sizeof(c));
5121 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
5122 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5123 FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
5124 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5125 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
5126 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
5127 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5130 /* Read an RSS table row */
5131 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
5133 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
5134 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
5139 * t4_read_rss - read the contents of the RSS mapping table
5140 * @adapter: the adapter
5141 * @map: holds the contents of the RSS mapping table
5143 * Reads the contents of the RSS hash->queue mapping table.
5145 int t4_read_rss(struct adapter *adapter, u16 *map)
5147 int i, ret, nentries;
5150 nentries = t4_chip_rss_size(adapter);
5151 for (i = 0; i < nentries / 2; ++i) {
5152 ret = rd_rss_row(adapter, i, &val);
5155 *map++ = LKPTBLQUEUE0_G(val);
5156 *map++ = LKPTBLQUEUE1_G(val);
5161 static unsigned int t4_use_ldst(struct adapter *adap)
5163 return (adap->flags & FW_OK) && !adap->use_bd;
5167 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5168 * @adap: the adapter
5169 * @cmd: TP fw ldst address space type
5170 * @vals: where the indirect register values are stored/written
5171 * @nregs: how many indirect registers to read/write
5172 * @start_idx: index of first indirect register to read/write
5173 * @rw: Read (1) or Write (0)
5174 * @sleep_ok: if true we may sleep while awaiting command completion
5176 * Access TP indirect registers through LDST
5178 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals,
5179 unsigned int nregs, unsigned int start_index,
5180 unsigned int rw, bool sleep_ok)
5184 struct fw_ldst_cmd c;
5186 for (i = 0; i < nregs; i++) {
5187 memset(&c, 0, sizeof(c));
5188 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5190 (rw ? FW_CMD_READ_F :
5192 FW_LDST_CMD_ADDRSPACE_V(cmd));
5193 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5195 c.u.addrval.addr = cpu_to_be32(start_index + i);
5196 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
5197 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c,
5203 vals[i] = be32_to_cpu(c.u.addrval.val);
5209 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5210 * @adap: the adapter
5211 * @reg_addr: Address Register
5212 * @reg_data: Data register
5213 * @buff: where the indirect register values are stored/written
5214 * @nregs: how many indirect registers to read/write
5215 * @start_index: index of first indirect register to read/write
5216 * @rw: READ(1) or WRITE(0)
5217 * @sleep_ok: if true we may sleep while awaiting command completion
5219 * Read/Write TP indirect registers through LDST if possible.
5220 * Else, use backdoor access
5222 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data,
5223 u32 *buff, u32 nregs, u32 start_index, int rw,
5231 cmd = FW_LDST_ADDRSPC_TP_PIO;
5233 case TP_TM_PIO_ADDR_A:
5234 cmd = FW_LDST_ADDRSPC_TP_TM_PIO;
5236 case TP_MIB_INDEX_A:
5237 cmd = FW_LDST_ADDRSPC_TP_MIB;
5240 goto indirect_access;
5243 if (t4_use_ldst(adap))
5244 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw,
5251 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs,
5254 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs,
5260 * t4_tp_pio_read - Read TP PIO registers
5261 * @adap: the adapter
5262 * @buff: where the indirect register values are written
5263 * @nregs: how many indirect registers to read
5264 * @start_index: index of first indirect register to read
5265 * @sleep_ok: if true we may sleep while awaiting command completion
5267 * Read TP PIO Registers
5269 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5270 u32 start_index, bool sleep_ok)
5272 t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5273 start_index, 1, sleep_ok);
5277 * t4_tp_pio_write - Write TP PIO registers
5278 * @adap: the adapter
5279 * @buff: where the indirect register values are stored
5280 * @nregs: how many indirect registers to write
5281 * @start_index: index of first indirect register to write
5282 * @sleep_ok: if true we may sleep while awaiting command completion
5284 * Write TP PIO Registers
5286 static void t4_tp_pio_write(struct adapter *adap, u32 *buff, u32 nregs,
5287 u32 start_index, bool sleep_ok)
5289 t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5290 start_index, 0, sleep_ok);
5294 * t4_tp_tm_pio_read - Read TP TM PIO registers
5295 * @adap: the adapter
5296 * @buff: where the indirect register values are written
5297 * @nregs: how many indirect registers to read
5298 * @start_index: index of first indirect register to read
5299 * @sleep_ok: if true we may sleep while awaiting command completion
5301 * Read TP TM PIO Registers
5303 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5304 u32 start_index, bool sleep_ok)
5306 t4_tp_indirect_rw(adap, TP_TM_PIO_ADDR_A, TP_TM_PIO_DATA_A, buff,
5307 nregs, start_index, 1, sleep_ok);
5311 * t4_tp_mib_read - Read TP MIB registers
5312 * @adap: the adapter
5313 * @buff: where the indirect register values are written
5314 * @nregs: how many indirect registers to read
5315 * @start_index: index of first indirect register to read
5316 * @sleep_ok: if true we may sleep while awaiting command completion
5318 * Read TP MIB Registers
5320 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index,
5323 t4_tp_indirect_rw(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, buff, nregs,
5324 start_index, 1, sleep_ok);
5328 * t4_read_rss_key - read the global RSS key
5329 * @adap: the adapter
5330 * @key: 10-entry array holding the 320-bit RSS key
5331 * @sleep_ok: if true we may sleep while awaiting command completion
5333 * Reads the global 320-bit RSS key.
5335 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok)
5337 t4_tp_pio_read(adap, key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5341 * t4_write_rss_key - program one of the RSS keys
5342 * @adap: the adapter
5343 * @key: 10-entry array holding the 320-bit RSS key
5344 * @idx: which RSS key to write
5345 * @sleep_ok: if true we may sleep while awaiting command completion
5347 * Writes one of the RSS keys with the given 320-bit value. If @idx is
5348 * 0..15 the corresponding entry in the RSS key table is written,
5349 * otherwise the global RSS key is written.
5351 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
5354 u8 rss_key_addr_cnt = 16;
5355 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
5357 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5358 * allows access to key addresses 16-63 by using KeyWrAddrX
5359 * as index[5:4](upper 2) into key table
5361 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
5362 (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
5363 rss_key_addr_cnt = 32;
5365 t4_tp_pio_write(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5367 if (idx >= 0 && idx < rss_key_addr_cnt) {
5368 if (rss_key_addr_cnt > 16)
5369 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5370 KEYWRADDRX_V(idx >> 4) |
5371 T6_VFWRADDR_V(idx) | KEYWREN_F);
5373 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5374 KEYWRADDR_V(idx) | KEYWREN_F);
5379 * t4_read_rss_pf_config - read PF RSS Configuration Table
5380 * @adapter: the adapter
5381 * @index: the entry in the PF RSS table to read
5382 * @valp: where to store the returned value
5383 * @sleep_ok: if true we may sleep while awaiting command completion
5385 * Reads the PF RSS Configuration Table at the specified index and returns
5386 * the value found there.
5388 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
5389 u32 *valp, bool sleep_ok)
5391 t4_tp_pio_read(adapter, valp, 1, TP_RSS_PF0_CONFIG_A + index, sleep_ok);
5395 * t4_read_rss_vf_config - read VF RSS Configuration Table
5396 * @adapter: the adapter
5397 * @index: the entry in the VF RSS table to read
5398 * @vfl: where to store the returned VFL
5399 * @vfh: where to store the returned VFH
5400 * @sleep_ok: if true we may sleep while awaiting command completion
5402 * Reads the VF RSS Configuration Table at the specified index and returns
5403 * the (VFL, VFH) values found there.
5405 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
5406 u32 *vfl, u32 *vfh, bool sleep_ok)
5408 u32 vrt, mask, data;
5410 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
5411 mask = VFWRADDR_V(VFWRADDR_M);
5412 data = VFWRADDR_V(index);
5414 mask = T6_VFWRADDR_V(T6_VFWRADDR_M);
5415 data = T6_VFWRADDR_V(index);
5418 /* Request that the index'th VF Table values be read into VFL/VFH.
5420 vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
5421 vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
5422 vrt |= data | VFRDEN_F;
5423 t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
5425 /* Grab the VFL/VFH values ...
5427 t4_tp_pio_read(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, sleep_ok);
5428 t4_tp_pio_read(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, sleep_ok);
5432 * t4_read_rss_pf_map - read PF RSS Map
5433 * @adapter: the adapter
5434 * @sleep_ok: if true we may sleep while awaiting command completion
5436 * Reads the PF RSS Map register and returns its value.
5438 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok)
5442 t4_tp_pio_read(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, sleep_ok);
5447 * t4_read_rss_pf_mask - read PF RSS Mask
5448 * @adapter: the adapter
5449 * @sleep_ok: if true we may sleep while awaiting command completion
5451 * Reads the PF RSS Mask register and returns its value.
5453 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok)
5457 t4_tp_pio_read(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, sleep_ok);
5462 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
5463 * @adap: the adapter
5464 * @v4: holds the TCP/IP counter values
5465 * @v6: holds the TCP/IPv6 counter values
5466 * @sleep_ok: if true we may sleep while awaiting command completion
5468 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
5469 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
5471 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
5472 struct tp_tcp_stats *v6, bool sleep_ok)
5474 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
5476 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
5477 #define STAT(x) val[STAT_IDX(x)]
5478 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
5481 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5482 TP_MIB_TCP_OUT_RST_A, sleep_ok);
5483 v4->tcp_out_rsts = STAT(OUT_RST);
5484 v4->tcp_in_segs = STAT64(IN_SEG);
5485 v4->tcp_out_segs = STAT64(OUT_SEG);
5486 v4->tcp_retrans_segs = STAT64(RXT_SEG);
5489 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5490 TP_MIB_TCP_V6OUT_RST_A, sleep_ok);
5491 v6->tcp_out_rsts = STAT(OUT_RST);
5492 v6->tcp_in_segs = STAT64(IN_SEG);
5493 v6->tcp_out_segs = STAT64(OUT_SEG);
5494 v6->tcp_retrans_segs = STAT64(RXT_SEG);
5502 * t4_tp_get_err_stats - read TP's error MIB counters
5503 * @adap: the adapter
5504 * @st: holds the counter values
5505 * @sleep_ok: if true we may sleep while awaiting command completion
5507 * Returns the values of TP's error counters.
5509 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
5512 int nchan = adap->params.arch.nchan;
5514 t4_tp_mib_read(adap, st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A,
5516 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A,
5518 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A,
5520 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan,
5521 TP_MIB_TNL_CNG_DROP_0_A, sleep_ok);
5522 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan,
5523 TP_MIB_OFD_CHN_DROP_0_A, sleep_ok);
5524 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A,
5526 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan,
5527 TP_MIB_OFD_VLN_DROP_0_A, sleep_ok);
5528 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan,
5529 TP_MIB_TCP_V6IN_ERR_0_A, sleep_ok);
5530 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A,
5535 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
5536 * @adap: the adapter
5537 * @st: holds the counter values
5538 * @sleep_ok: if true we may sleep while awaiting command completion
5540 * Returns the values of TP's CPL counters.
5542 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
5545 int nchan = adap->params.arch.nchan;
5547 t4_tp_mib_read(adap, st->req, nchan, TP_MIB_CPL_IN_REQ_0_A, sleep_ok);
5549 t4_tp_mib_read(adap, st->rsp, nchan, TP_MIB_CPL_OUT_RSP_0_A, sleep_ok);
5553 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5554 * @adap: the adapter
5555 * @st: holds the counter values
5556 * @sleep_ok: if true we may sleep while awaiting command completion
5558 * Returns the values of TP's RDMA counters.
5560 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
5563 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, TP_MIB_RQE_DFR_PKT_A,
5568 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5569 * @adap: the adapter
5570 * @idx: the port index
5571 * @st: holds the counter values
5572 * @sleep_ok: if true we may sleep while awaiting command completion
5574 * Returns the values of TP's FCoE counters for the selected port.
5576 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5577 struct tp_fcoe_stats *st, bool sleep_ok)
5581 t4_tp_mib_read(adap, &st->frames_ddp, 1, TP_MIB_FCOE_DDP_0_A + idx,
5584 t4_tp_mib_read(adap, &st->frames_drop, 1,
5585 TP_MIB_FCOE_DROP_0_A + idx, sleep_ok);
5587 t4_tp_mib_read(adap, val, 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx,
5590 st->octets_ddp = ((u64)val[0] << 32) | val[1];
5594 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5595 * @adap: the adapter
5596 * @st: holds the counter values
5597 * @sleep_ok: if true we may sleep while awaiting command completion
5599 * Returns the values of TP's counters for non-TCP directly-placed packets.
5601 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
5606 t4_tp_mib_read(adap, val, 4, TP_MIB_USM_PKTS_A, sleep_ok);
5607 st->frames = val[0];
5609 st->octets = ((u64)val[2] << 32) | val[3];
5613 * t4_read_mtu_tbl - returns the values in the HW path MTU table
5614 * @adap: the adapter
5615 * @mtus: where to store the MTU values
5616 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
5618 * Reads the HW path MTU table.
5620 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5625 for (i = 0; i < NMTUS; ++i) {
5626 t4_write_reg(adap, TP_MTU_TABLE_A,
5627 MTUINDEX_V(0xff) | MTUVALUE_V(i));
5628 v = t4_read_reg(adap, TP_MTU_TABLE_A);
5629 mtus[i] = MTUVALUE_G(v);
5631 mtu_log[i] = MTUWIDTH_G(v);
5636 * t4_read_cong_tbl - reads the congestion control table
5637 * @adap: the adapter
5638 * @incr: where to store the alpha values
5640 * Reads the additive increments programmed into the HW congestion
5643 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5645 unsigned int mtu, w;
5647 for (mtu = 0; mtu < NMTUS; ++mtu)
5648 for (w = 0; w < NCCTRL_WIN; ++w) {
5649 t4_write_reg(adap, TP_CCTRL_TABLE_A,
5650 ROWINDEX_V(0xffff) | (mtu << 5) | w);
5651 incr[mtu][w] = (u16)t4_read_reg(adap,
5652 TP_CCTRL_TABLE_A) & 0x1fff;
5657 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5658 * @adap: the adapter
5659 * @addr: the indirect TP register address
5660 * @mask: specifies the field within the register to modify
5661 * @val: new value for the field
5663 * Sets a field of an indirect TP register to the given value.
5665 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5666 unsigned int mask, unsigned int val)
5668 t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5669 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5670 t4_write_reg(adap, TP_PIO_DATA_A, val);
5674 * init_cong_ctrl - initialize congestion control parameters
5675 * @a: the alpha values for congestion control
5676 * @b: the beta values for congestion control
5678 * Initialize the congestion control parameters.
5680 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5682 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5707 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5710 b[13] = b[14] = b[15] = b[16] = 3;
5711 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5712 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5717 /* The minimum additive increment value for the congestion control table */
5718 #define CC_MIN_INCR 2U
5721 * t4_load_mtus - write the MTU and congestion control HW tables
5722 * @adap: the adapter
5723 * @mtus: the values for the MTU table
5724 * @alpha: the values for the congestion control alpha parameter
5725 * @beta: the values for the congestion control beta parameter
5727 * Write the HW MTU table with the supplied MTUs and the high-speed
5728 * congestion control table with the supplied alpha, beta, and MTUs.
5729 * We write the two tables together because the additive increments
5730 * depend on the MTUs.
5732 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5733 const unsigned short *alpha, const unsigned short *beta)
5735 static const unsigned int avg_pkts[NCCTRL_WIN] = {
5736 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5737 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5738 28672, 40960, 57344, 81920, 114688, 163840, 229376
5743 for (i = 0; i < NMTUS; ++i) {
5744 unsigned int mtu = mtus[i];
5745 unsigned int log2 = fls(mtu);
5747 if (!(mtu & ((1 << log2) >> 2))) /* round */
5749 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5750 MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5752 for (w = 0; w < NCCTRL_WIN; ++w) {
5755 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5758 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5759 (w << 16) | (beta[w] << 13) | inc);
5764 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5765 * clocks. The formula is
5767 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5769 * which is equivalent to
5771 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5773 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5775 u64 v = bytes256 * adap->params.vpd.cclk;
5777 return v * 62 + v / 2;
5781 * t4_get_chan_txrate - get the current per channel Tx rates
5782 * @adap: the adapter
5783 * @nic_rate: rates for NIC traffic
5784 * @ofld_rate: rates for offloaded traffic
5786 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
5789 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5793 v = t4_read_reg(adap, TP_TX_TRATE_A);
5794 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5795 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5796 if (adap->params.arch.nchan == NCHAN) {
5797 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5798 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5801 v = t4_read_reg(adap, TP_TX_ORATE_A);
5802 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5803 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5804 if (adap->params.arch.nchan == NCHAN) {
5805 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5806 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5811 * t4_set_trace_filter - configure one of the tracing filters
5812 * @adap: the adapter
5813 * @tp: the desired trace filter parameters
5814 * @idx: which filter to configure
5815 * @enable: whether to enable or disable the filter
5817 * Configures one of the tracing filters available in HW. If @enable is
5818 * %0 @tp is not examined and may be %NULL. The user is responsible to
5819 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5821 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5822 int idx, int enable)
5824 int i, ofst = idx * 4;
5825 u32 data_reg, mask_reg, cfg;
5826 u32 multitrc = TRCMULTIFILTER_F;
5829 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5833 cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5834 if (cfg & TRCMULTIFILTER_F) {
5835 /* If multiple tracers are enabled, then maximum
5836 * capture size is 2.5KB (FIFO size of a single channel)
5837 * minus 2 flits for CPL_TRACE_PKT header.
5839 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5842 /* If multiple tracers are disabled, to avoid deadlocks
5843 * maximum packet capture size of 9600 bytes is recommended.
5844 * Also in this mode, only trace0 can be enabled and running.
5847 if (tp->snap_len > 9600 || idx)
5851 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5852 tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5853 tp->min_len > TFMINPKTSIZE_M)
5856 /* stop the tracer we'll be changing */
5857 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5859 idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5860 data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5861 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5863 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5864 t4_write_reg(adap, data_reg, tp->data[i]);
5865 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5867 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5868 TFCAPTUREMAX_V(tp->snap_len) |
5869 TFMINPKTSIZE_V(tp->min_len));
5870 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5871 TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5872 (is_t4(adap->params.chip) ?
5873 TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5874 T5_TFPORT_V(tp->port) | T5_TFEN_F |
5875 T5_TFINVERTMATCH_V(tp->invert)));
5881 * t4_get_trace_filter - query one of the tracing filters
5882 * @adap: the adapter
5883 * @tp: the current trace filter parameters
5884 * @idx: which trace filter to query
5885 * @enabled: non-zero if the filter is enabled
5887 * Returns the current settings of one of the HW tracing filters.
5889 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5893 int i, ofst = idx * 4;
5894 u32 data_reg, mask_reg;
5896 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
5897 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
5899 if (is_t4(adap->params.chip)) {
5900 *enabled = !!(ctla & TFEN_F);
5901 tp->port = TFPORT_G(ctla);
5902 tp->invert = !!(ctla & TFINVERTMATCH_F);
5904 *enabled = !!(ctla & T5_TFEN_F);
5905 tp->port = T5_TFPORT_G(ctla);
5906 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
5908 tp->snap_len = TFCAPTUREMAX_G(ctlb);
5909 tp->min_len = TFMINPKTSIZE_G(ctlb);
5910 tp->skip_ofst = TFOFFSET_G(ctla);
5911 tp->skip_len = TFLENGTH_G(ctla);
5913 ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
5914 data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
5915 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
5917 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5918 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5919 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5924 * t4_pmtx_get_stats - returns the HW stats from PMTX
5925 * @adap: the adapter
5926 * @cnt: where to store the count statistics
5927 * @cycles: where to store the cycle statistics
5929 * Returns performance statistics from PMTX.
5931 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5936 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5937 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
5938 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
5939 if (is_t4(adap->params.chip)) {
5940 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
5942 t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
5943 PM_TX_DBG_DATA_A, data, 2,
5944 PM_TX_DBG_STAT_MSB_A);
5945 cycles[i] = (((u64)data[0] << 32) | data[1]);
5951 * t4_pmrx_get_stats - returns the HW stats from PMRX
5952 * @adap: the adapter
5953 * @cnt: where to store the count statistics
5954 * @cycles: where to store the cycle statistics
5956 * Returns performance statistics from PMRX.
5958 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5963 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5964 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
5965 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
5966 if (is_t4(adap->params.chip)) {
5967 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
5969 t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
5970 PM_RX_DBG_DATA_A, data, 2,
5971 PM_RX_DBG_STAT_MSB_A);
5972 cycles[i] = (((u64)data[0] << 32) | data[1]);
5978 * compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
5979 * @adap: the adapter
5980 * @pidx: the port index
5982 * Computes and returns a bitmap indicating which MPS buffer groups are
5983 * associated with the given Port. Bit i is set if buffer group i is
5986 static inline unsigned int compute_mps_bg_map(struct adapter *adapter,
5989 unsigned int chip_version, nports;
5991 chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
5992 nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
5994 switch (chip_version) {
5999 case 2: return 3 << (2 * pidx);
6000 case 4: return 1 << pidx;
6006 case 2: return 1 << (2 * pidx);
6011 dev_err(adapter->pdev_dev, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
6012 chip_version, nports);
6018 * t4_get_mps_bg_map - return the buffer groups associated with a port
6019 * @adapter: the adapter
6020 * @pidx: the port index
6022 * Returns a bitmap indicating which MPS buffer groups are associated
6023 * with the given Port. Bit i is set if buffer group i is used by the
6026 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx)
6029 unsigned int nports;
6031 nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6032 if (pidx >= nports) {
6033 CH_WARN(adapter, "MPS Port Index %d >= Nports %d\n",
6038 /* If we've already retrieved/computed this, just return the result.
6040 mps_bg_map = adapter->params.mps_bg_map;
6041 if (mps_bg_map[pidx])
6042 return mps_bg_map[pidx];
6044 /* Newer Firmware can tell us what the MPS Buffer Group Map is.
6045 * If we're talking to such Firmware, let it tell us. If the new
6046 * API isn't supported, revert back to old hardcoded way. The value
6047 * obtained from Firmware is encoded in below format:
6049 * val = (( MPSBGMAP[Port 3] << 24 ) |
6050 * ( MPSBGMAP[Port 2] << 16 ) |
6051 * ( MPSBGMAP[Port 1] << 8 ) |
6052 * ( MPSBGMAP[Port 0] << 0 ))
6054 if (adapter->flags & FW_OK) {
6058 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6059 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_MPSBGMAP));
6060 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
6061 0, 1, ¶m, &val);
6065 /* Store the BG Map for all of the Ports in order to
6066 * avoid more calls to the Firmware in the future.
6068 for (p = 0; p < MAX_NPORTS; p++, val >>= 8)
6069 mps_bg_map[p] = val & 0xff;
6071 return mps_bg_map[pidx];
6075 /* Either we're not talking to the Firmware or we're dealing with
6076 * older Firmware which doesn't support the new API to get the MPS
6077 * Buffer Group Map. Fall back to computing it ourselves.
6079 mps_bg_map[pidx] = compute_mps_bg_map(adapter, pidx);
6080 return mps_bg_map[pidx];
6084 * t4_get_tp_ch_map - return TP ingress channels associated with a port
6085 * @adapter: the adapter
6086 * @pidx: the port index
6088 * Returns a bitmap indicating which TP Ingress Channels are associated
6089 * with a given Port. Bit i is set if TP Ingress Channel i is used by
6092 unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
6094 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
6095 unsigned int nports = 1 << NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
6097 if (pidx >= nports) {
6098 dev_warn(adap->pdev_dev, "TP Port Index %d >= Nports %d\n",
6103 switch (chip_version) {
6106 /* Note that this happens to be the same values as the MPS
6107 * Buffer Group Map for these Chips. But we replicate the code
6108 * here because they're really separate concepts.
6112 case 2: return 3 << (2 * pidx);
6113 case 4: return 1 << pidx;
6120 case 2: return 1 << pidx;
6125 dev_err(adap->pdev_dev, "Need TP Channel Map for Chip %0x, Nports %d\n",
6126 chip_version, nports);
6131 * t4_get_port_type_description - return Port Type string description
6132 * @port_type: firmware Port Type enumeration
6134 const char *t4_get_port_type_description(enum fw_port_type port_type)
6136 static const char *const port_type_description[] = {
6162 if (port_type < ARRAY_SIZE(port_type_description))
6163 return port_type_description[port_type];
6168 * t4_get_port_stats_offset - collect port stats relative to a previous
6170 * @adap: The adapter
6172 * @stats: Current stats to fill
6173 * @offset: Previous stats snapshot
6175 void t4_get_port_stats_offset(struct adapter *adap, int idx,
6176 struct port_stats *stats,
6177 struct port_stats *offset)
6182 t4_get_port_stats(adap, idx, stats);
6183 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
6184 i < (sizeof(struct port_stats) / sizeof(u64));
6190 * t4_get_port_stats - collect port statistics
6191 * @adap: the adapter
6192 * @idx: the port index
6193 * @p: the stats structure to fill
6195 * Collect statistics related to the given port from HW.
6197 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
6199 u32 bgmap = t4_get_mps_bg_map(adap, idx);
6200 u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
6202 #define GET_STAT(name) \
6203 t4_read_reg64(adap, \
6204 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
6205 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
6206 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6208 p->tx_octets = GET_STAT(TX_PORT_BYTES);
6209 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
6210 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
6211 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
6212 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
6213 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
6214 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
6215 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
6216 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
6217 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
6218 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
6219 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
6220 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
6221 p->tx_drop = GET_STAT(TX_PORT_DROP);
6222 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
6223 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
6224 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
6225 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
6226 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
6227 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
6228 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
6229 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
6230 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
6232 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6233 if (stat_ctl & COUNTPAUSESTATTX_F)
6234 p->tx_frames_64 -= p->tx_pause;
6235 if (stat_ctl & COUNTPAUSEMCTX_F)
6236 p->tx_mcast_frames -= p->tx_pause;
6238 p->rx_octets = GET_STAT(RX_PORT_BYTES);
6239 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
6240 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
6241 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
6242 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
6243 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
6244 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
6245 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
6246 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
6247 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
6248 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
6249 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
6250 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
6251 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
6252 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
6253 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
6254 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
6255 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
6256 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
6257 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
6258 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
6259 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
6260 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
6261 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
6262 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
6263 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
6264 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
6266 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6267 if (stat_ctl & COUNTPAUSESTATRX_F)
6268 p->rx_frames_64 -= p->rx_pause;
6269 if (stat_ctl & COUNTPAUSEMCRX_F)
6270 p->rx_mcast_frames -= p->rx_pause;
6273 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
6274 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
6275 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
6276 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
6277 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
6278 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
6279 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
6280 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
6287 * t4_get_lb_stats - collect loopback port statistics
6288 * @adap: the adapter
6289 * @idx: the loopback port index
6290 * @p: the stats structure to fill
6292 * Return HW statistics for the given loopback port.
6294 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
6296 u32 bgmap = t4_get_mps_bg_map(adap, idx);
6298 #define GET_STAT(name) \
6299 t4_read_reg64(adap, \
6300 (is_t4(adap->params.chip) ? \
6301 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
6302 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
6303 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6305 p->octets = GET_STAT(BYTES);
6306 p->frames = GET_STAT(FRAMES);
6307 p->bcast_frames = GET_STAT(BCAST);
6308 p->mcast_frames = GET_STAT(MCAST);
6309 p->ucast_frames = GET_STAT(UCAST);
6310 p->error_frames = GET_STAT(ERROR);
6312 p->frames_64 = GET_STAT(64B);
6313 p->frames_65_127 = GET_STAT(65B_127B);
6314 p->frames_128_255 = GET_STAT(128B_255B);
6315 p->frames_256_511 = GET_STAT(256B_511B);
6316 p->frames_512_1023 = GET_STAT(512B_1023B);
6317 p->frames_1024_1518 = GET_STAT(1024B_1518B);
6318 p->frames_1519_max = GET_STAT(1519B_MAX);
6319 p->drop = GET_STAT(DROP_FRAMES);
6321 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
6322 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
6323 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
6324 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
6325 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
6326 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
6327 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
6328 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
6334 /* t4_mk_filtdelwr - create a delete filter WR
6335 * @ftid: the filter ID
6336 * @wr: the filter work request to populate
6337 * @qid: ingress queue to receive the delete notification
6339 * Creates a filter work request to delete the supplied filter. If @qid is
6340 * negative the delete notification is suppressed.
6342 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
6344 memset(wr, 0, sizeof(*wr));
6345 wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
6346 wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
6347 wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
6348 FW_FILTER_WR_NOREPLY_V(qid < 0));
6349 wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
6351 wr->rx_chan_rx_rpl_iq =
6352 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
6355 #define INIT_CMD(var, cmd, rd_wr) do { \
6356 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
6357 FW_CMD_REQUEST_F | \
6358 FW_CMD_##rd_wr##_F); \
6359 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
6362 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
6366 struct fw_ldst_cmd c;
6368 memset(&c, 0, sizeof(c));
6369 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
6370 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6374 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6375 c.u.addrval.addr = cpu_to_be32(addr);
6376 c.u.addrval.val = cpu_to_be32(val);
6378 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6382 * t4_mdio_rd - read a PHY register through MDIO
6383 * @adap: the adapter
6384 * @mbox: mailbox to use for the FW command
6385 * @phy_addr: the PHY address
6386 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6387 * @reg: the register to read
6388 * @valp: where to store the value
6390 * Issues a FW command through the given mailbox to read a PHY register.
6392 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6393 unsigned int mmd, unsigned int reg, u16 *valp)
6397 struct fw_ldst_cmd c;
6399 memset(&c, 0, sizeof(c));
6400 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6401 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6402 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6404 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6405 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6406 FW_LDST_CMD_MMD_V(mmd));
6407 c.u.mdio.raddr = cpu_to_be16(reg);
6409 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6411 *valp = be16_to_cpu(c.u.mdio.rval);
6416 * t4_mdio_wr - write a PHY register through MDIO
6417 * @adap: the adapter
6418 * @mbox: mailbox to use for the FW command
6419 * @phy_addr: the PHY address
6420 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6421 * @reg: the register to write
6422 * @valp: value to write
6424 * Issues a FW command through the given mailbox to write a PHY register.
6426 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6427 unsigned int mmd, unsigned int reg, u16 val)
6430 struct fw_ldst_cmd c;
6432 memset(&c, 0, sizeof(c));
6433 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6434 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6435 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6437 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6438 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6439 FW_LDST_CMD_MMD_V(mmd));
6440 c.u.mdio.raddr = cpu_to_be16(reg);
6441 c.u.mdio.rval = cpu_to_be16(val);
6443 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6447 * t4_sge_decode_idma_state - decode the idma state
6448 * @adap: the adapter
6449 * @state: the state idma is stuck in
6451 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
6453 static const char * const t4_decode[] = {
6455 "IDMA_PUSH_MORE_CPL_FIFO",
6456 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6458 "IDMA_PHYSADDR_SEND_PCIEHDR",
6459 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6460 "IDMA_PHYSADDR_SEND_PAYLOAD",
6461 "IDMA_SEND_FIFO_TO_IMSG",
6462 "IDMA_FL_REQ_DATA_FL_PREP",
6463 "IDMA_FL_REQ_DATA_FL",
6465 "IDMA_FL_H_REQ_HEADER_FL",
6466 "IDMA_FL_H_SEND_PCIEHDR",
6467 "IDMA_FL_H_PUSH_CPL_FIFO",
6468 "IDMA_FL_H_SEND_CPL",
6469 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6470 "IDMA_FL_H_SEND_IP_HDR",
6471 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6472 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6473 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6474 "IDMA_FL_D_SEND_PCIEHDR",
6475 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6476 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6477 "IDMA_FL_SEND_PCIEHDR",
6478 "IDMA_FL_PUSH_CPL_FIFO",
6480 "IDMA_FL_SEND_PAYLOAD_FIRST",
6481 "IDMA_FL_SEND_PAYLOAD",
6482 "IDMA_FL_REQ_NEXT_DATA_FL",
6483 "IDMA_FL_SEND_NEXT_PCIEHDR",
6484 "IDMA_FL_SEND_PADDING",
6485 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6486 "IDMA_FL_SEND_FIFO_TO_IMSG",
6487 "IDMA_FL_REQ_DATAFL_DONE",
6488 "IDMA_FL_REQ_HEADERFL_DONE",
6490 static const char * const t5_decode[] = {
6493 "IDMA_PUSH_MORE_CPL_FIFO",
6494 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6495 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6496 "IDMA_PHYSADDR_SEND_PCIEHDR",
6497 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6498 "IDMA_PHYSADDR_SEND_PAYLOAD",
6499 "IDMA_SEND_FIFO_TO_IMSG",
6500 "IDMA_FL_REQ_DATA_FL",
6502 "IDMA_FL_DROP_SEND_INC",
6503 "IDMA_FL_H_REQ_HEADER_FL",
6504 "IDMA_FL_H_SEND_PCIEHDR",
6505 "IDMA_FL_H_PUSH_CPL_FIFO",
6506 "IDMA_FL_H_SEND_CPL",
6507 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6508 "IDMA_FL_H_SEND_IP_HDR",
6509 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6510 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6511 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6512 "IDMA_FL_D_SEND_PCIEHDR",
6513 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6514 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6515 "IDMA_FL_SEND_PCIEHDR",
6516 "IDMA_FL_PUSH_CPL_FIFO",
6518 "IDMA_FL_SEND_PAYLOAD_FIRST",
6519 "IDMA_FL_SEND_PAYLOAD",
6520 "IDMA_FL_REQ_NEXT_DATA_FL",
6521 "IDMA_FL_SEND_NEXT_PCIEHDR",
6522 "IDMA_FL_SEND_PADDING",
6523 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6525 static const char * const t6_decode[] = {
6527 "IDMA_PUSH_MORE_CPL_FIFO",
6528 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6529 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6530 "IDMA_PHYSADDR_SEND_PCIEHDR",
6531 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6532 "IDMA_PHYSADDR_SEND_PAYLOAD",
6533 "IDMA_FL_REQ_DATA_FL",
6535 "IDMA_FL_DROP_SEND_INC",
6536 "IDMA_FL_H_REQ_HEADER_FL",
6537 "IDMA_FL_H_SEND_PCIEHDR",
6538 "IDMA_FL_H_PUSH_CPL_FIFO",
6539 "IDMA_FL_H_SEND_CPL",
6540 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6541 "IDMA_FL_H_SEND_IP_HDR",
6542 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6543 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6544 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6545 "IDMA_FL_D_SEND_PCIEHDR",
6546 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6547 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6548 "IDMA_FL_SEND_PCIEHDR",
6549 "IDMA_FL_PUSH_CPL_FIFO",
6551 "IDMA_FL_SEND_PAYLOAD_FIRST",
6552 "IDMA_FL_SEND_PAYLOAD",
6553 "IDMA_FL_REQ_NEXT_DATA_FL",
6554 "IDMA_FL_SEND_NEXT_PCIEHDR",
6555 "IDMA_FL_SEND_PADDING",
6556 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6558 static const u32 sge_regs[] = {
6559 SGE_DEBUG_DATA_LOW_INDEX_2_A,
6560 SGE_DEBUG_DATA_LOW_INDEX_3_A,
6561 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
6563 const char **sge_idma_decode;
6564 int sge_idma_decode_nstates;
6566 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6568 /* Select the right set of decode strings to dump depending on the
6569 * adapter chip type.
6571 switch (chip_version) {
6573 sge_idma_decode = (const char **)t4_decode;
6574 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6578 sge_idma_decode = (const char **)t5_decode;
6579 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6583 sge_idma_decode = (const char **)t6_decode;
6584 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
6588 dev_err(adapter->pdev_dev,
6589 "Unsupported chip version %d\n", chip_version);
6593 if (is_t4(adapter->params.chip)) {
6594 sge_idma_decode = (const char **)t4_decode;
6595 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6597 sge_idma_decode = (const char **)t5_decode;
6598 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6601 if (state < sge_idma_decode_nstates)
6602 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
6604 CH_WARN(adapter, "idma state %d unknown\n", state);
6606 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
6607 CH_WARN(adapter, "SGE register %#x value %#x\n",
6608 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
6612 * t4_sge_ctxt_flush - flush the SGE context cache
6613 * @adap: the adapter
6614 * @mbox: mailbox to use for the FW command
6615 * @ctx_type: Egress or Ingress
6617 * Issues a FW command through the given mailbox to flush the
6618 * SGE context cache.
6620 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type)
6624 struct fw_ldst_cmd c;
6626 memset(&c, 0, sizeof(c));
6627 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(ctxt_type == CTXT_EGRESS ?
6628 FW_LDST_ADDRSPC_SGE_EGRC :
6629 FW_LDST_ADDRSPC_SGE_INGC);
6630 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6631 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6633 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6634 c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
6636 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6641 * t4_fw_hello - establish communication with FW
6642 * @adap: the adapter
6643 * @mbox: mailbox to use for the FW command
6644 * @evt_mbox: mailbox to receive async FW events
6645 * @master: specifies the caller's willingness to be the device master
6646 * @state: returns the current device state (if non-NULL)
6648 * Issues a command to establish communication with FW. Returns either
6649 * an error (negative integer) or the mailbox of the Master PF.
6651 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
6652 enum dev_master master, enum dev_state *state)
6655 struct fw_hello_cmd c;
6657 unsigned int master_mbox;
6658 int retries = FW_CMD_HELLO_RETRIES;
6661 memset(&c, 0, sizeof(c));
6662 INIT_CMD(c, HELLO, WRITE);
6663 c.err_to_clearinit = cpu_to_be32(
6664 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
6665 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
6666 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
6667 mbox : FW_HELLO_CMD_MBMASTER_M) |
6668 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
6669 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
6670 FW_HELLO_CMD_CLEARINIT_F);
6673 * Issue the HELLO command to the firmware. If it's not successful
6674 * but indicates that we got a "busy" or "timeout" condition, retry
6675 * the HELLO until we exhaust our retry limit. If we do exceed our
6676 * retry limit, check to see if the firmware left us any error
6677 * information and report that if so.
6679 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6681 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
6683 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
6684 t4_report_fw_error(adap);
6688 v = be32_to_cpu(c.err_to_clearinit);
6689 master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
6691 if (v & FW_HELLO_CMD_ERR_F)
6692 *state = DEV_STATE_ERR;
6693 else if (v & FW_HELLO_CMD_INIT_F)
6694 *state = DEV_STATE_INIT;
6696 *state = DEV_STATE_UNINIT;
6700 * If we're not the Master PF then we need to wait around for the
6701 * Master PF Driver to finish setting up the adapter.
6703 * Note that we also do this wait if we're a non-Master-capable PF and
6704 * there is no current Master PF; a Master PF may show up momentarily
6705 * and we wouldn't want to fail pointlessly. (This can happen when an
6706 * OS loads lots of different drivers rapidly at the same time). In
6707 * this case, the Master PF returned by the firmware will be
6708 * PCIE_FW_MASTER_M so the test below will work ...
6710 if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
6711 master_mbox != mbox) {
6712 int waiting = FW_CMD_HELLO_TIMEOUT;
6715 * Wait for the firmware to either indicate an error or
6716 * initialized state. If we see either of these we bail out
6717 * and report the issue to the caller. If we exhaust the
6718 * "hello timeout" and we haven't exhausted our retries, try
6719 * again. Otherwise bail with a timeout error.
6728 * If neither Error nor Initialialized are indicated
6729 * by the firmware keep waiting till we exaust our
6730 * timeout ... and then retry if we haven't exhausted
6733 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
6734 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
6745 * We either have an Error or Initialized condition
6746 * report errors preferentially.
6749 if (pcie_fw & PCIE_FW_ERR_F)
6750 *state = DEV_STATE_ERR;
6751 else if (pcie_fw & PCIE_FW_INIT_F)
6752 *state = DEV_STATE_INIT;
6756 * If we arrived before a Master PF was selected and
6757 * there's not a valid Master PF, grab its identity
6760 if (master_mbox == PCIE_FW_MASTER_M &&
6761 (pcie_fw & PCIE_FW_MASTER_VLD_F))
6762 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
6771 * t4_fw_bye - end communication with FW
6772 * @adap: the adapter
6773 * @mbox: mailbox to use for the FW command
6775 * Issues a command to terminate communication with FW.
6777 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6779 struct fw_bye_cmd c;
6781 memset(&c, 0, sizeof(c));
6782 INIT_CMD(c, BYE, WRITE);
6783 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6787 * t4_init_cmd - ask FW to initialize the device
6788 * @adap: the adapter
6789 * @mbox: mailbox to use for the FW command
6791 * Issues a command to FW to partially initialize the device. This
6792 * performs initialization that generally doesn't depend on user input.
6794 int t4_early_init(struct adapter *adap, unsigned int mbox)
6796 struct fw_initialize_cmd c;
6798 memset(&c, 0, sizeof(c));
6799 INIT_CMD(c, INITIALIZE, WRITE);
6800 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6804 * t4_fw_reset - issue a reset to FW
6805 * @adap: the adapter
6806 * @mbox: mailbox to use for the FW command
6807 * @reset: specifies the type of reset to perform
6809 * Issues a reset command of the specified type to FW.
6811 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
6813 struct fw_reset_cmd c;
6815 memset(&c, 0, sizeof(c));
6816 INIT_CMD(c, RESET, WRITE);
6817 c.val = cpu_to_be32(reset);
6818 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6822 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6823 * @adap: the adapter
6824 * @mbox: mailbox to use for the FW RESET command (if desired)
6825 * @force: force uP into RESET even if FW RESET command fails
6827 * Issues a RESET command to firmware (if desired) with a HALT indication
6828 * and then puts the microprocessor into RESET state. The RESET command
6829 * will only be issued if a legitimate mailbox is provided (mbox <=
6830 * PCIE_FW_MASTER_M).
6832 * This is generally used in order for the host to safely manipulate the
6833 * adapter without fear of conflicting with whatever the firmware might
6834 * be doing. The only way out of this state is to RESTART the firmware
6837 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6842 * If a legitimate mailbox is provided, issue a RESET command
6843 * with a HALT indication.
6845 if (mbox <= PCIE_FW_MASTER_M) {
6846 struct fw_reset_cmd c;
6848 memset(&c, 0, sizeof(c));
6849 INIT_CMD(c, RESET, WRITE);
6850 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
6851 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
6852 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6856 * Normally we won't complete the operation if the firmware RESET
6857 * command fails but if our caller insists we'll go ahead and put the
6858 * uP into RESET. This can be useful if the firmware is hung or even
6859 * missing ... We'll have to take the risk of putting the uP into
6860 * RESET without the cooperation of firmware in that case.
6862 * We also force the firmware's HALT flag to be on in case we bypassed
6863 * the firmware RESET command above or we're dealing with old firmware
6864 * which doesn't have the HALT capability. This will serve as a flag
6865 * for the incoming firmware to know that it's coming out of a HALT
6866 * rather than a RESET ... if it's new enough to understand that ...
6868 if (ret == 0 || force) {
6869 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
6870 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
6875 * And we always return the result of the firmware RESET command
6876 * even when we force the uP into RESET ...
6882 * t4_fw_restart - restart the firmware by taking the uP out of RESET
6883 * @adap: the adapter
6884 * @reset: if we want to do a RESET to restart things
6886 * Restart firmware previously halted by t4_fw_halt(). On successful
6887 * return the previous PF Master remains as the new PF Master and there
6888 * is no need to issue a new HELLO command, etc.
6890 * We do this in two ways:
6892 * 1. If we're dealing with newer firmware we'll simply want to take
6893 * the chip's microprocessor out of RESET. This will cause the
6894 * firmware to start up from its start vector. And then we'll loop
6895 * until the firmware indicates it's started again (PCIE_FW.HALT
6896 * reset to 0) or we timeout.
6898 * 2. If we're dealing with older firmware then we'll need to RESET
6899 * the chip since older firmware won't recognize the PCIE_FW.HALT
6900 * flag and automatically RESET itself on startup.
6902 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6906 * Since we're directing the RESET instead of the firmware
6907 * doing it automatically, we need to clear the PCIE_FW.HALT
6910 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
6913 * If we've been given a valid mailbox, first try to get the
6914 * firmware to do the RESET. If that works, great and we can
6915 * return success. Otherwise, if we haven't been given a
6916 * valid mailbox or the RESET command failed, fall back to
6917 * hitting the chip with a hammer.
6919 if (mbox <= PCIE_FW_MASTER_M) {
6920 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6922 if (t4_fw_reset(adap, mbox,
6923 PIORST_F | PIORSTMODE_F) == 0)
6927 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
6932 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6933 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6934 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
6945 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6946 * @adap: the adapter
6947 * @mbox: mailbox to use for the FW RESET command (if desired)
6948 * @fw_data: the firmware image to write
6950 * @force: force upgrade even if firmware doesn't cooperate
6952 * Perform all of the steps necessary for upgrading an adapter's
6953 * firmware image. Normally this requires the cooperation of the
6954 * existing firmware in order to halt all existing activities
6955 * but if an invalid mailbox token is passed in we skip that step
6956 * (though we'll still put the adapter microprocessor into RESET in
6959 * On successful return the new firmware will have been loaded and
6960 * the adapter will have been fully RESET losing all previous setup
6961 * state. On unsuccessful return the adapter may be completely hosed ...
6962 * positive errno indicates that the adapter is ~probably~ intact, a
6963 * negative errno indicates that things are looking bad ...
6965 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6966 const u8 *fw_data, unsigned int size, int force)
6968 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6971 if (!t4_fw_matches_chip(adap, fw_hdr))
6974 /* Disable FW_OK flag so that mbox commands with FW_OK flag set
6975 * wont be sent when we are flashing FW.
6977 adap->flags &= ~FW_OK;
6979 ret = t4_fw_halt(adap, mbox, force);
6980 if (ret < 0 && !force)
6983 ret = t4_load_fw(adap, fw_data, size);
6988 * If there was a Firmware Configuration File stored in FLASH,
6989 * there's a good chance that it won't be compatible with the new
6990 * Firmware. In order to prevent difficult to diagnose adapter
6991 * initialization issues, we clear out the Firmware Configuration File
6992 * portion of the FLASH . The user will need to re-FLASH a new
6993 * Firmware Configuration File which is compatible with the new
6994 * Firmware if that's desired.
6996 (void)t4_load_cfg(adap, NULL, 0);
6999 * Older versions of the firmware don't understand the new
7000 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
7001 * restart. So for newly loaded older firmware we'll have to do the
7002 * RESET for it so it starts up on a clean slate. We can tell if
7003 * the newly loaded firmware will handle this right by checking
7004 * its header flags to see if it advertises the capability.
7006 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
7007 ret = t4_fw_restart(adap, mbox, reset);
7009 /* Grab potentially new Firmware Device Log parameters so we can see
7010 * how healthy the new Firmware is. It's okay to contact the new
7011 * Firmware for these parameters even though, as far as it's
7012 * concerned, we've never said "HELLO" to it ...
7014 (void)t4_init_devlog_params(adap);
7016 adap->flags |= FW_OK;
7021 * t4_fl_pkt_align - return the fl packet alignment
7022 * @adap: the adapter
7024 * T4 has a single field to specify the packing and padding boundary.
7025 * T5 onwards has separate fields for this and hence the alignment for
7026 * next packet offset is maximum of these two.
7029 int t4_fl_pkt_align(struct adapter *adap)
7031 u32 sge_control, sge_control2;
7032 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
7034 sge_control = t4_read_reg(adap, SGE_CONTROL_A);
7036 /* T4 uses a single control field to specify both the PCIe Padding and
7037 * Packing Boundary. T5 introduced the ability to specify these
7038 * separately. The actual Ingress Packet Data alignment boundary
7039 * within Packed Buffer Mode is the maximum of these two
7040 * specifications. (Note that it makes no real practical sense to
7041 * have the Pading Boudary be larger than the Packing Boundary but you
7042 * could set the chip up that way and, in fact, legacy T4 code would
7043 * end doing this because it would initialize the Padding Boundary and
7044 * leave the Packing Boundary initialized to 0 (16 bytes).)
7045 * Padding Boundary values in T6 starts from 8B,
7046 * where as it is 32B for T4 and T5.
7048 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
7049 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
7051 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
7053 ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
7055 fl_align = ingpadboundary;
7056 if (!is_t4(adap->params.chip)) {
7057 /* T5 has a weird interpretation of one of the PCIe Packing
7058 * Boundary values. No idea why ...
7060 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
7061 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
7062 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
7063 ingpackboundary = 16;
7065 ingpackboundary = 1 << (ingpackboundary +
7066 INGPACKBOUNDARY_SHIFT_X);
7068 fl_align = max(ingpadboundary, ingpackboundary);
7074 * t4_fixup_host_params - fix up host-dependent parameters
7075 * @adap: the adapter
7076 * @page_size: the host's Base Page Size
7077 * @cache_line_size: the host's Cache Line Size
7079 * Various registers in T4 contain values which are dependent on the
7080 * host's Base Page and Cache Line Sizes. This function will fix all of
7081 * those registers with the appropriate values as passed in ...
7083 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
7084 unsigned int cache_line_size)
7086 unsigned int page_shift = fls(page_size) - 1;
7087 unsigned int sge_hps = page_shift - 10;
7088 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
7089 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
7090 unsigned int fl_align_log = fls(fl_align) - 1;
7092 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
7093 HOSTPAGESIZEPF0_V(sge_hps) |
7094 HOSTPAGESIZEPF1_V(sge_hps) |
7095 HOSTPAGESIZEPF2_V(sge_hps) |
7096 HOSTPAGESIZEPF3_V(sge_hps) |
7097 HOSTPAGESIZEPF4_V(sge_hps) |
7098 HOSTPAGESIZEPF5_V(sge_hps) |
7099 HOSTPAGESIZEPF6_V(sge_hps) |
7100 HOSTPAGESIZEPF7_V(sge_hps));
7102 if (is_t4(adap->params.chip)) {
7103 t4_set_reg_field(adap, SGE_CONTROL_A,
7104 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7105 EGRSTATUSPAGESIZE_F,
7106 INGPADBOUNDARY_V(fl_align_log -
7107 INGPADBOUNDARY_SHIFT_X) |
7108 EGRSTATUSPAGESIZE_V(stat_len != 64));
7110 unsigned int pack_align;
7111 unsigned int ingpad, ingpack;
7112 unsigned int pcie_cap;
7114 /* T5 introduced the separation of the Free List Padding and
7115 * Packing Boundaries. Thus, we can select a smaller Padding
7116 * Boundary to avoid uselessly chewing up PCIe Link and Memory
7117 * Bandwidth, and use a Packing Boundary which is large enough
7118 * to avoid false sharing between CPUs, etc.
7120 * For the PCI Link, the smaller the Padding Boundary the
7121 * better. For the Memory Controller, a smaller Padding
7122 * Boundary is better until we cross under the Memory Line
7123 * Size (the minimum unit of transfer to/from Memory). If we
7124 * have a Padding Boundary which is smaller than the Memory
7125 * Line Size, that'll involve a Read-Modify-Write cycle on the
7126 * Memory Controller which is never good.
7129 /* We want the Packing Boundary to be based on the Cache Line
7130 * Size in order to help avoid False Sharing performance
7131 * issues between CPUs, etc. We also want the Packing
7132 * Boundary to incorporate the PCI-E Maximum Payload Size. We
7133 * get best performance when the Packing Boundary is a
7134 * multiple of the Maximum Payload Size.
7136 pack_align = fl_align;
7137 pcie_cap = pci_find_capability(adap->pdev, PCI_CAP_ID_EXP);
7139 unsigned int mps, mps_log;
7142 /* The PCIe Device Control Maximum Payload Size field
7143 * [bits 7:5] encodes sizes as powers of 2 starting at
7146 pci_read_config_word(adap->pdev,
7147 pcie_cap + PCI_EXP_DEVCTL,
7149 mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
7151 if (mps > pack_align)
7155 /* N.B. T5/T6 have a crazy special interpretation of the "0"
7156 * value for the Packing Boundary. This corresponds to 16
7157 * bytes instead of the expected 32 bytes. So if we want 32
7158 * bytes, the best we can really do is 64 bytes ...
7160 if (pack_align <= 16) {
7161 ingpack = INGPACKBOUNDARY_16B_X;
7163 } else if (pack_align == 32) {
7164 ingpack = INGPACKBOUNDARY_64B_X;
7167 unsigned int pack_align_log = fls(pack_align) - 1;
7169 ingpack = pack_align_log - INGPACKBOUNDARY_SHIFT_X;
7170 fl_align = pack_align;
7173 /* Use the smallest Ingress Padding which isn't smaller than
7174 * the Memory Controller Read/Write Size. We'll take that as
7175 * being 8 bytes since we don't know of any system with a
7176 * wider Memory Controller Bus Width.
7178 if (is_t5(adap->params.chip))
7179 ingpad = INGPADBOUNDARY_32B_X;
7181 ingpad = T6_INGPADBOUNDARY_8B_X;
7183 t4_set_reg_field(adap, SGE_CONTROL_A,
7184 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7185 EGRSTATUSPAGESIZE_F,
7186 INGPADBOUNDARY_V(ingpad) |
7187 EGRSTATUSPAGESIZE_V(stat_len != 64));
7188 t4_set_reg_field(adap, SGE_CONTROL2_A,
7189 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
7190 INGPACKBOUNDARY_V(ingpack));
7193 * Adjust various SGE Free List Host Buffer Sizes.
7195 * This is something of a crock since we're using fixed indices into
7196 * the array which are also known by the sge.c code and the T4
7197 * Firmware Configuration File. We need to come up with a much better
7198 * approach to managing this array. For now, the first four entries
7203 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
7204 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
7206 * For the single-MTU buffers in unpacked mode we need to include
7207 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
7208 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
7209 * Padding boundary. All of these are accommodated in the Factory
7210 * Default Firmware Configuration File but we need to adjust it for
7211 * this host's cache line size.
7213 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
7214 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
7215 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
7217 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
7218 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
7221 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
7227 * t4_fw_initialize - ask FW to initialize the device
7228 * @adap: the adapter
7229 * @mbox: mailbox to use for the FW command
7231 * Issues a command to FW to partially initialize the device. This
7232 * performs initialization that generally doesn't depend on user input.
7234 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
7236 struct fw_initialize_cmd c;
7238 memset(&c, 0, sizeof(c));
7239 INIT_CMD(c, INITIALIZE, WRITE);
7240 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7244 * t4_query_params_rw - query FW or device parameters
7245 * @adap: the adapter
7246 * @mbox: mailbox to use for the FW command
7249 * @nparams: the number of parameters
7250 * @params: the parameter names
7251 * @val: the parameter values
7252 * @rw: Write and read flag
7253 * @sleep_ok: if true, we may sleep awaiting mbox cmd completion
7255 * Reads the value of FW or device parameters. Up to 7 parameters can be
7258 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
7259 unsigned int vf, unsigned int nparams, const u32 *params,
7260 u32 *val, int rw, bool sleep_ok)
7263 struct fw_params_cmd c;
7264 __be32 *p = &c.param[0].mnem;
7269 memset(&c, 0, sizeof(c));
7270 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7271 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7272 FW_PARAMS_CMD_PFN_V(pf) |
7273 FW_PARAMS_CMD_VFN_V(vf));
7274 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7276 for (i = 0; i < nparams; i++) {
7277 *p++ = cpu_to_be32(*params++);
7279 *p = cpu_to_be32(*(val + i));
7283 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7285 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
7286 *val++ = be32_to_cpu(*p);
7290 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7291 unsigned int vf, unsigned int nparams, const u32 *params,
7294 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7298 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
7299 unsigned int vf, unsigned int nparams, const u32 *params,
7302 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7307 * t4_set_params_timeout - sets FW or device parameters
7308 * @adap: the adapter
7309 * @mbox: mailbox to use for the FW command
7312 * @nparams: the number of parameters
7313 * @params: the parameter names
7314 * @val: the parameter values
7315 * @timeout: the timeout time
7317 * Sets the value of FW or device parameters. Up to 7 parameters can be
7318 * specified at once.
7320 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
7321 unsigned int pf, unsigned int vf,
7322 unsigned int nparams, const u32 *params,
7323 const u32 *val, int timeout)
7325 struct fw_params_cmd c;
7326 __be32 *p = &c.param[0].mnem;
7331 memset(&c, 0, sizeof(c));
7332 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7333 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7334 FW_PARAMS_CMD_PFN_V(pf) |
7335 FW_PARAMS_CMD_VFN_V(vf));
7336 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7339 *p++ = cpu_to_be32(*params++);
7340 *p++ = cpu_to_be32(*val++);
7343 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
7347 * t4_set_params - sets FW or device parameters
7348 * @adap: the adapter
7349 * @mbox: mailbox to use for the FW command
7352 * @nparams: the number of parameters
7353 * @params: the parameter names
7354 * @val: the parameter values
7356 * Sets the value of FW or device parameters. Up to 7 parameters can be
7357 * specified at once.
7359 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7360 unsigned int vf, unsigned int nparams, const u32 *params,
7363 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
7364 FW_CMD_MAX_TIMEOUT);
7368 * t4_cfg_pfvf - configure PF/VF resource limits
7369 * @adap: the adapter
7370 * @mbox: mailbox to use for the FW command
7371 * @pf: the PF being configured
7372 * @vf: the VF being configured
7373 * @txq: the max number of egress queues
7374 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
7375 * @rxqi: the max number of interrupt-capable ingress queues
7376 * @rxq: the max number of interruptless ingress queues
7377 * @tc: the PCI traffic class
7378 * @vi: the max number of virtual interfaces
7379 * @cmask: the channel access rights mask for the PF/VF
7380 * @pmask: the port access rights mask for the PF/VF
7381 * @nexact: the maximum number of exact MPS filters
7382 * @rcaps: read capabilities
7383 * @wxcaps: write/execute capabilities
7385 * Configures resource limits and capabilities for a physical or virtual
7388 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
7389 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
7390 unsigned int rxqi, unsigned int rxq, unsigned int tc,
7391 unsigned int vi, unsigned int cmask, unsigned int pmask,
7392 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
7394 struct fw_pfvf_cmd c;
7396 memset(&c, 0, sizeof(c));
7397 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
7398 FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
7399 FW_PFVF_CMD_VFN_V(vf));
7400 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7401 c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
7402 FW_PFVF_CMD_NIQ_V(rxq));
7403 c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
7404 FW_PFVF_CMD_PMASK_V(pmask) |
7405 FW_PFVF_CMD_NEQ_V(txq));
7406 c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
7407 FW_PFVF_CMD_NVI_V(vi) |
7408 FW_PFVF_CMD_NEXACTF_V(nexact));
7409 c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
7410 FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
7411 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
7412 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7416 * t4_alloc_vi - allocate a virtual interface
7417 * @adap: the adapter
7418 * @mbox: mailbox to use for the FW command
7419 * @port: physical port associated with the VI
7420 * @pf: the PF owning the VI
7421 * @vf: the VF owning the VI
7422 * @nmac: number of MAC addresses needed (1 to 5)
7423 * @mac: the MAC addresses of the VI
7424 * @rss_size: size of RSS table slice associated with this VI
7426 * Allocates a virtual interface for the given physical port. If @mac is
7427 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
7428 * @mac should be large enough to hold @nmac Ethernet addresses, they are
7429 * stored consecutively so the space needed is @nmac * 6 bytes.
7430 * Returns a negative error number or the non-negative VI id.
7432 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
7433 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
7434 unsigned int *rss_size)
7439 memset(&c, 0, sizeof(c));
7440 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
7441 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
7442 FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
7443 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
7444 c.portid_pkd = FW_VI_CMD_PORTID_V(port);
7447 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7452 memcpy(mac, c.mac, sizeof(c.mac));
7455 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
7457 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
7459 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
7461 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
7465 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
7466 return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
7470 * t4_free_vi - free a virtual interface
7471 * @adap: the adapter
7472 * @mbox: mailbox to use for the FW command
7473 * @pf: the PF owning the VI
7474 * @vf: the VF owning the VI
7475 * @viid: virtual interface identifiler
7477 * Free a previously allocated virtual interface.
7479 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
7480 unsigned int vf, unsigned int viid)
7484 memset(&c, 0, sizeof(c));
7485 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
7488 FW_VI_CMD_PFN_V(pf) |
7489 FW_VI_CMD_VFN_V(vf));
7490 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
7491 c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
7493 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7497 * t4_set_rxmode - set Rx properties of a virtual interface
7498 * @adap: the adapter
7499 * @mbox: mailbox to use for the FW command
7501 * @mtu: the new MTU or -1
7502 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7503 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7504 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7505 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7506 * @sleep_ok: if true we may sleep while awaiting command completion
7508 * Sets Rx properties of a virtual interface.
7510 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
7511 int mtu, int promisc, int all_multi, int bcast, int vlanex,
7514 struct fw_vi_rxmode_cmd c;
7516 /* convert to FW values */
7518 mtu = FW_RXMODE_MTU_NO_CHG;
7520 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
7522 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
7524 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
7526 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
7528 memset(&c, 0, sizeof(c));
7529 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
7530 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7531 FW_VI_RXMODE_CMD_VIID_V(viid));
7532 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7534 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
7535 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
7536 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
7537 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
7538 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
7539 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7543 * t4_free_encap_mac_filt - frees MPS entry at given index
7544 * @adap: the adapter
7546 * @idx: index of MPS entry to be freed
7547 * @sleep_ok: call is allowed to sleep
7549 * Frees the MPS entry at supplied index
7551 * Returns a negative error number or zero on success
7553 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
7554 int idx, bool sleep_ok)
7556 struct fw_vi_mac_exact *p;
7557 u8 addr[] = {0, 0, 0, 0, 0, 0};
7558 struct fw_vi_mac_cmd c;
7562 memset(&c, 0, sizeof(c));
7563 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7564 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7566 FW_VI_MAC_CMD_VIID_V(viid));
7567 exact = FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC);
7568 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7572 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7573 FW_VI_MAC_CMD_IDX_V(idx));
7574 memcpy(p->macaddr, addr, sizeof(p->macaddr));
7575 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7580 * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam
7581 * @adap: the adapter
7583 * @addr: the MAC address
7585 * @idx: index of the entry in mps tcam
7586 * @lookup_type: MAC address for inner (1) or outer (0) header
7587 * @port_id: the port index
7588 * @sleep_ok: call is allowed to sleep
7590 * Removes the mac entry at the specified index using raw mac interface.
7592 * Returns a negative error number on failure.
7594 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
7595 const u8 *addr, const u8 *mask, unsigned int idx,
7596 u8 lookup_type, u8 port_id, bool sleep_ok)
7598 struct fw_vi_mac_cmd c;
7599 struct fw_vi_mac_raw *p = &c.u.raw;
7602 memset(&c, 0, sizeof(c));
7603 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7604 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7606 FW_VI_MAC_CMD_VIID_V(viid));
7607 val = FW_CMD_LEN16_V(1) |
7608 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW);
7609 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7610 FW_CMD_LEN16_V(val));
7612 p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx) |
7613 FW_VI_MAC_ID_BASED_FREE);
7615 /* Lookup Type. Outer header: 0, Inner header: 1 */
7616 p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) |
7617 DATAPORTNUM_V(port_id));
7618 /* Lookup mask and port mask */
7619 p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) |
7620 DATAPORTNUM_V(DATAPORTNUM_M));
7622 /* Copy the address and the mask */
7623 memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN);
7624 memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN);
7626 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7630 * t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support
7631 * @adap: the adapter
7633 * @mac: the MAC address
7635 * @vni: the VNI id for the tunnel protocol
7636 * @vni_mask: mask for the VNI id
7637 * @dip_hit: to enable DIP match for the MPS entry
7638 * @lookup_type: MAC address for inner (1) or outer (0) header
7639 * @sleep_ok: call is allowed to sleep
7641 * Allocates an MPS entry with specified MAC address and VNI value.
7643 * Returns a negative error number or the allocated index for this mac.
7645 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
7646 const u8 *addr, const u8 *mask, unsigned int vni,
7647 unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
7650 struct fw_vi_mac_cmd c;
7651 struct fw_vi_mac_vni *p = c.u.exact_vni;
7655 memset(&c, 0, sizeof(c));
7656 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7657 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7658 FW_VI_MAC_CMD_VIID_V(viid));
7659 val = FW_CMD_LEN16_V(1) |
7660 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC_VNI);
7661 c.freemacs_to_len16 = cpu_to_be32(val);
7662 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7663 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_ADD_MAC));
7664 memcpy(p->macaddr, addr, sizeof(p->macaddr));
7665 memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask));
7667 p->lookup_type_to_vni =
7668 cpu_to_be32(FW_VI_MAC_CMD_VNI_V(vni) |
7669 FW_VI_MAC_CMD_DIP_HIT_V(dip_hit) |
7670 FW_VI_MAC_CMD_LOOKUP_TYPE_V(lookup_type));
7671 p->vni_mask_pkd = cpu_to_be32(FW_VI_MAC_CMD_VNI_MASK_V(vni_mask));
7672 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7674 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
7679 * t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam
7680 * @adap: the adapter
7682 * @mac: the MAC address
7684 * @idx: index at which to add this entry
7685 * @port_id: the port index
7686 * @lookup_type: MAC address for inner (1) or outer (0) header
7687 * @sleep_ok: call is allowed to sleep
7689 * Adds the mac entry at the specified index using raw mac interface.
7691 * Returns a negative error number or the allocated index for this mac.
7693 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
7694 const u8 *addr, const u8 *mask, unsigned int idx,
7695 u8 lookup_type, u8 port_id, bool sleep_ok)
7698 struct fw_vi_mac_cmd c;
7699 struct fw_vi_mac_raw *p = &c.u.raw;
7702 memset(&c, 0, sizeof(c));
7703 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7704 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7705 FW_VI_MAC_CMD_VIID_V(viid));
7706 val = FW_CMD_LEN16_V(1) |
7707 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW);
7708 c.freemacs_to_len16 = cpu_to_be32(val);
7710 /* Specify that this is an inner mac address */
7711 p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx));
7713 /* Lookup Type. Outer header: 0, Inner header: 1 */
7714 p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) |
7715 DATAPORTNUM_V(port_id));
7716 /* Lookup mask and port mask */
7717 p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) |
7718 DATAPORTNUM_V(DATAPORTNUM_M));
7720 /* Copy the address and the mask */
7721 memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN);
7722 memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN);
7724 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7726 ret = FW_VI_MAC_CMD_RAW_IDX_G(be32_to_cpu(p->raw_idx_pkd));
7735 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7736 * @adap: the adapter
7737 * @mbox: mailbox to use for the FW command
7739 * @free: if true any existing filters for this VI id are first removed
7740 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
7741 * @addr: the MAC address(es)
7742 * @idx: where to store the index of each allocated filter
7743 * @hash: pointer to hash address filter bitmap
7744 * @sleep_ok: call is allowed to sleep
7746 * Allocates an exact-match filter for each of the supplied addresses and
7747 * sets it to the corresponding address. If @idx is not %NULL it should
7748 * have at least @naddr entries, each of which will be set to the index of
7749 * the filter allocated for the corresponding MAC address. If a filter
7750 * could not be allocated for an address its index is set to 0xffff.
7751 * If @hash is not %NULL addresses that fail to allocate an exact filter
7752 * are hashed and update the hash filter bitmap pointed at by @hash.
7754 * Returns a negative error number or the number of filters allocated.
7756 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
7757 unsigned int viid, bool free, unsigned int naddr,
7758 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
7760 int offset, ret = 0;
7761 struct fw_vi_mac_cmd c;
7762 unsigned int nfilters = 0;
7763 unsigned int max_naddr = adap->params.arch.mps_tcam_size;
7764 unsigned int rem = naddr;
7766 if (naddr > max_naddr)
7769 for (offset = 0; offset < naddr ; /**/) {
7770 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
7771 rem : ARRAY_SIZE(c.u.exact));
7772 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7773 u.exact[fw_naddr]), 16);
7774 struct fw_vi_mac_exact *p;
7777 memset(&c, 0, sizeof(c));
7778 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7781 FW_CMD_EXEC_V(free) |
7782 FW_VI_MAC_CMD_VIID_V(viid));
7783 c.freemacs_to_len16 =
7784 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
7785 FW_CMD_LEN16_V(len16));
7787 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7789 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7790 FW_VI_MAC_CMD_IDX_V(
7791 FW_VI_MAC_ADD_MAC));
7792 memcpy(p->macaddr, addr[offset + i],
7793 sizeof(p->macaddr));
7796 /* It's okay if we run out of space in our MAC address arena.
7797 * Some of the addresses we submit may get stored so we need
7798 * to run through the reply to see what the results were ...
7800 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7801 if (ret && ret != -FW_ENOMEM)
7804 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7805 u16 index = FW_VI_MAC_CMD_IDX_G(
7806 be16_to_cpu(p->valid_to_idx));
7809 idx[offset + i] = (index >= max_naddr ?
7811 if (index < max_naddr)
7815 hash_mac_addr(addr[offset + i]));
7823 if (ret == 0 || ret == -FW_ENOMEM)
7829 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
7830 * @adap: the adapter
7831 * @mbox: mailbox to use for the FW command
7833 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
7834 * @addr: the MAC address(es)
7835 * @sleep_ok: call is allowed to sleep
7837 * Frees the exact-match filter for each of the supplied addresses
7839 * Returns a negative error number or the number of filters freed.
7841 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
7842 unsigned int viid, unsigned int naddr,
7843 const u8 **addr, bool sleep_ok)
7845 int offset, ret = 0;
7846 struct fw_vi_mac_cmd c;
7847 unsigned int nfilters = 0;
7848 unsigned int max_naddr = is_t4(adap->params.chip) ?
7849 NUM_MPS_CLS_SRAM_L_INSTANCES :
7850 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7851 unsigned int rem = naddr;
7853 if (naddr > max_naddr)
7856 for (offset = 0; offset < (int)naddr ; /**/) {
7857 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
7859 : ARRAY_SIZE(c.u.exact));
7860 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7861 u.exact[fw_naddr]), 16);
7862 struct fw_vi_mac_exact *p;
7865 memset(&c, 0, sizeof(c));
7866 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7870 FW_VI_MAC_CMD_VIID_V(viid));
7871 c.freemacs_to_len16 =
7872 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7873 FW_CMD_LEN16_V(len16));
7875 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
7876 p->valid_to_idx = cpu_to_be16(
7877 FW_VI_MAC_CMD_VALID_F |
7878 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
7879 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
7882 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7886 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7887 u16 index = FW_VI_MAC_CMD_IDX_G(
7888 be16_to_cpu(p->valid_to_idx));
7890 if (index < max_naddr)
7904 * t4_change_mac - modifies the exact-match filter for a MAC address
7905 * @adap: the adapter
7906 * @mbox: mailbox to use for the FW command
7908 * @idx: index of existing filter for old value of MAC address, or -1
7909 * @addr: the new MAC address value
7910 * @persist: whether a new MAC allocation should be persistent
7911 * @add_smt: if true also add the address to the HW SMT
7913 * Modifies an exact-match filter and sets it to the new MAC address.
7914 * Note that in general it is not possible to modify the value of a given
7915 * filter so the generic way to modify an address filter is to free the one
7916 * being used by the old address value and allocate a new filter for the
7917 * new address value. @idx can be -1 if the address is a new addition.
7919 * Returns a negative error number or the index of the filter with the new
7922 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
7923 int idx, const u8 *addr, bool persist, bool add_smt)
7926 struct fw_vi_mac_cmd c;
7927 struct fw_vi_mac_exact *p = c.u.exact;
7928 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
7930 if (idx < 0) /* new allocation */
7931 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
7932 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
7934 memset(&c, 0, sizeof(c));
7935 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7936 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7937 FW_VI_MAC_CMD_VIID_V(viid));
7938 c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
7939 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7940 FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
7941 FW_VI_MAC_CMD_IDX_V(idx));
7942 memcpy(p->macaddr, addr, sizeof(p->macaddr));
7944 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7946 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
7947 if (ret >= max_mac_addr)
7954 * t4_set_addr_hash - program the MAC inexact-match hash filter
7955 * @adap: the adapter
7956 * @mbox: mailbox to use for the FW command
7958 * @ucast: whether the hash filter should also match unicast addresses
7959 * @vec: the value to be written to the hash filter
7960 * @sleep_ok: call is allowed to sleep
7962 * Sets the 64-bit inexact-match hash filter for a virtual interface.
7964 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
7965 bool ucast, u64 vec, bool sleep_ok)
7967 struct fw_vi_mac_cmd c;
7969 memset(&c, 0, sizeof(c));
7970 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7971 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7972 FW_VI_ENABLE_CMD_VIID_V(viid));
7973 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
7974 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
7976 c.u.hash.hashvec = cpu_to_be64(vec);
7977 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7981 * t4_enable_vi_params - enable/disable a virtual interface
7982 * @adap: the adapter
7983 * @mbox: mailbox to use for the FW command
7985 * @rx_en: 1=enable Rx, 0=disable Rx
7986 * @tx_en: 1=enable Tx, 0=disable Tx
7987 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
7989 * Enables/disables a virtual interface. Note that setting DCB Enable
7990 * only makes sense when enabling a Virtual Interface ...
7992 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
7993 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
7995 struct fw_vi_enable_cmd c;
7997 memset(&c, 0, sizeof(c));
7998 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
7999 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8000 FW_VI_ENABLE_CMD_VIID_V(viid));
8001 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
8002 FW_VI_ENABLE_CMD_EEN_V(tx_en) |
8003 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
8005 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
8009 * t4_enable_vi - enable/disable a virtual interface
8010 * @adap: the adapter
8011 * @mbox: mailbox to use for the FW command
8013 * @rx_en: 1=enable Rx, 0=disable Rx
8014 * @tx_en: 1=enable Tx, 0=disable Tx
8016 * Enables/disables a virtual interface.
8018 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
8019 bool rx_en, bool tx_en)
8021 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
8025 * t4_enable_pi_params - enable/disable a Port's Virtual Interface
8026 * @adap: the adapter
8027 * @mbox: mailbox to use for the FW command
8028 * @pi: the Port Information structure
8029 * @rx_en: 1=enable Rx, 0=disable Rx
8030 * @tx_en: 1=enable Tx, 0=disable Tx
8031 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
8033 * Enables/disables a Port's Virtual Interface. Note that setting DCB
8034 * Enable only makes sense when enabling a Virtual Interface ...
8035 * If the Virtual Interface enable/disable operation is successful,
8036 * we notify the OS-specific code of a potential Link Status change
8037 * via the OS Contract API t4_os_link_changed().
8039 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
8040 struct port_info *pi,
8041 bool rx_en, bool tx_en, bool dcb_en)
8043 int ret = t4_enable_vi_params(adap, mbox, pi->viid,
8044 rx_en, tx_en, dcb_en);
8047 t4_os_link_changed(adap, pi->port_id,
8048 rx_en && tx_en && pi->link_cfg.link_ok);
8053 * t4_identify_port - identify a VI's port by blinking its LED
8054 * @adap: the adapter
8055 * @mbox: mailbox to use for the FW command
8057 * @nblinks: how many times to blink LED at 2.5 Hz
8059 * Identifies a VI's port by blinking its LED.
8061 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
8062 unsigned int nblinks)
8064 struct fw_vi_enable_cmd c;
8066 memset(&c, 0, sizeof(c));
8067 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
8068 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8069 FW_VI_ENABLE_CMD_VIID_V(viid));
8070 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
8071 c.blinkdur = cpu_to_be16(nblinks);
8072 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8076 * t4_iq_stop - stop an ingress queue and its FLs
8077 * @adap: the adapter
8078 * @mbox: mailbox to use for the FW command
8079 * @pf: the PF owning the queues
8080 * @vf: the VF owning the queues
8081 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
8082 * @iqid: ingress queue id
8083 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8084 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8086 * Stops an ingress queue and its associated FLs, if any. This causes
8087 * any current or future data/messages destined for these queues to be
8090 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
8091 unsigned int vf, unsigned int iqtype, unsigned int iqid,
8092 unsigned int fl0id, unsigned int fl1id)
8096 memset(&c, 0, sizeof(c));
8097 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
8098 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
8099 FW_IQ_CMD_VFN_V(vf));
8100 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
8101 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
8102 c.iqid = cpu_to_be16(iqid);
8103 c.fl0id = cpu_to_be16(fl0id);
8104 c.fl1id = cpu_to_be16(fl1id);
8105 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8109 * t4_iq_free - free an ingress queue and its FLs
8110 * @adap: the adapter
8111 * @mbox: mailbox to use for the FW command
8112 * @pf: the PF owning the queues
8113 * @vf: the VF owning the queues
8114 * @iqtype: the ingress queue type
8115 * @iqid: ingress queue id
8116 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8117 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8119 * Frees an ingress queue and its associated FLs, if any.
8121 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8122 unsigned int vf, unsigned int iqtype, unsigned int iqid,
8123 unsigned int fl0id, unsigned int fl1id)
8127 memset(&c, 0, sizeof(c));
8128 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
8129 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
8130 FW_IQ_CMD_VFN_V(vf));
8131 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
8132 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
8133 c.iqid = cpu_to_be16(iqid);
8134 c.fl0id = cpu_to_be16(fl0id);
8135 c.fl1id = cpu_to_be16(fl1id);
8136 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8140 * t4_eth_eq_free - free an Ethernet egress queue
8141 * @adap: the adapter
8142 * @mbox: mailbox to use for the FW command
8143 * @pf: the PF owning the queue
8144 * @vf: the VF owning the queue
8145 * @eqid: egress queue id
8147 * Frees an Ethernet egress queue.
8149 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8150 unsigned int vf, unsigned int eqid)
8152 struct fw_eq_eth_cmd c;
8154 memset(&c, 0, sizeof(c));
8155 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
8156 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8157 FW_EQ_ETH_CMD_PFN_V(pf) |
8158 FW_EQ_ETH_CMD_VFN_V(vf));
8159 c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
8160 c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
8161 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8165 * t4_ctrl_eq_free - free a control egress queue
8166 * @adap: the adapter
8167 * @mbox: mailbox to use for the FW command
8168 * @pf: the PF owning the queue
8169 * @vf: the VF owning the queue
8170 * @eqid: egress queue id
8172 * Frees a control egress queue.
8174 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8175 unsigned int vf, unsigned int eqid)
8177 struct fw_eq_ctrl_cmd c;
8179 memset(&c, 0, sizeof(c));
8180 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
8181 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8182 FW_EQ_CTRL_CMD_PFN_V(pf) |
8183 FW_EQ_CTRL_CMD_VFN_V(vf));
8184 c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
8185 c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
8186 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8190 * t4_ofld_eq_free - free an offload egress queue
8191 * @adap: the adapter
8192 * @mbox: mailbox to use for the FW command
8193 * @pf: the PF owning the queue
8194 * @vf: the VF owning the queue
8195 * @eqid: egress queue id
8197 * Frees a control egress queue.
8199 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8200 unsigned int vf, unsigned int eqid)
8202 struct fw_eq_ofld_cmd c;
8204 memset(&c, 0, sizeof(c));
8205 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
8206 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8207 FW_EQ_OFLD_CMD_PFN_V(pf) |
8208 FW_EQ_OFLD_CMD_VFN_V(vf));
8209 c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
8210 c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
8211 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8215 * t4_link_down_rc_str - return a string for a Link Down Reason Code
8216 * @adap: the adapter
8217 * @link_down_rc: Link Down Reason Code
8219 * Returns a string representation of the Link Down Reason Code.
8221 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
8223 static const char * const reason[] = {
8226 "Auto-negotiation Failure",
8228 "Insufficient Airflow",
8229 "Unable To Determine Reason",
8230 "No RX Signal Detected",
8234 if (link_down_rc >= ARRAY_SIZE(reason))
8235 return "Bad Reason Code";
8237 return reason[link_down_rc];
8241 * Return the highest speed set in the port capabilities, in Mb/s.
8243 static unsigned int fwcap_to_speed(fw_port_cap32_t caps)
8245 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
8247 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8251 TEST_SPEED_RETURN(400G, 400000);
8252 TEST_SPEED_RETURN(200G, 200000);
8253 TEST_SPEED_RETURN(100G, 100000);
8254 TEST_SPEED_RETURN(50G, 50000);
8255 TEST_SPEED_RETURN(40G, 40000);
8256 TEST_SPEED_RETURN(25G, 25000);
8257 TEST_SPEED_RETURN(10G, 10000);
8258 TEST_SPEED_RETURN(1G, 1000);
8259 TEST_SPEED_RETURN(100M, 100);
8261 #undef TEST_SPEED_RETURN
8267 * fwcap_to_fwspeed - return highest speed in Port Capabilities
8268 * @acaps: advertised Port Capabilities
8270 * Get the highest speed for the port from the advertised Port
8271 * Capabilities. It will be either the highest speed from the list of
8272 * speeds or whatever user has set using ethtool.
8274 static fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps)
8276 #define TEST_SPEED_RETURN(__caps_speed) \
8278 if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8279 return FW_PORT_CAP32_SPEED_##__caps_speed; \
8282 TEST_SPEED_RETURN(400G);
8283 TEST_SPEED_RETURN(200G);
8284 TEST_SPEED_RETURN(100G);
8285 TEST_SPEED_RETURN(50G);
8286 TEST_SPEED_RETURN(40G);
8287 TEST_SPEED_RETURN(25G);
8288 TEST_SPEED_RETURN(10G);
8289 TEST_SPEED_RETURN(1G);
8290 TEST_SPEED_RETURN(100M);
8292 #undef TEST_SPEED_RETURN
8298 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
8299 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
8301 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
8302 * 32-bit Port Capabilities value.
8304 static fw_port_cap32_t lstatus_to_fwcap(u32 lstatus)
8306 fw_port_cap32_t linkattr = 0;
8308 /* Unfortunately the format of the Link Status in the old
8309 * 16-bit Port Information message isn't the same as the
8310 * 16-bit Port Capabilities bitfield used everywhere else ...
8312 if (lstatus & FW_PORT_CMD_RXPAUSE_F)
8313 linkattr |= FW_PORT_CAP32_FC_RX;
8314 if (lstatus & FW_PORT_CMD_TXPAUSE_F)
8315 linkattr |= FW_PORT_CAP32_FC_TX;
8316 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
8317 linkattr |= FW_PORT_CAP32_SPEED_100M;
8318 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
8319 linkattr |= FW_PORT_CAP32_SPEED_1G;
8320 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
8321 linkattr |= FW_PORT_CAP32_SPEED_10G;
8322 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
8323 linkattr |= FW_PORT_CAP32_SPEED_25G;
8324 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
8325 linkattr |= FW_PORT_CAP32_SPEED_40G;
8326 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
8327 linkattr |= FW_PORT_CAP32_SPEED_100G;
8333 * t4_handle_get_port_info - process a FW reply message
8334 * @pi: the port info
8335 * @rpl: start of the FW message
8337 * Processes a GET_PORT_INFO FW reply message.
8339 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
8341 const struct fw_port_cmd *cmd = (const void *)rpl;
8342 int action = FW_PORT_CMD_ACTION_G(be32_to_cpu(cmd->action_to_len16));
8343 struct adapter *adapter = pi->adapter;
8344 struct link_config *lc = &pi->link_cfg;
8345 int link_ok, linkdnrc;
8346 enum fw_port_type port_type;
8347 enum fw_port_module_type mod_type;
8348 unsigned int speed, fc, fec;
8349 fw_port_cap32_t pcaps, acaps, lpacaps, linkattr;
8351 /* Extract the various fields from the Port Information message.
8354 case FW_PORT_ACTION_GET_PORT_INFO: {
8355 u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype);
8357 link_ok = (lstatus & FW_PORT_CMD_LSTATUS_F) != 0;
8358 linkdnrc = FW_PORT_CMD_LINKDNRC_G(lstatus);
8359 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
8360 mod_type = FW_PORT_CMD_MODTYPE_G(lstatus);
8361 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap));
8362 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap));
8363 lpacaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.lpacap));
8364 linkattr = lstatus_to_fwcap(lstatus);
8368 case FW_PORT_ACTION_GET_PORT_INFO32: {
8371 lstatus32 = be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32);
8372 link_ok = (lstatus32 & FW_PORT_CMD_LSTATUS32_F) != 0;
8373 linkdnrc = FW_PORT_CMD_LINKDNRC32_G(lstatus32);
8374 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
8375 mod_type = FW_PORT_CMD_MODTYPE32_G(lstatus32);
8376 pcaps = be32_to_cpu(cmd->u.info32.pcaps32);
8377 acaps = be32_to_cpu(cmd->u.info32.acaps32);
8378 lpacaps = be32_to_cpu(cmd->u.info32.lpacaps32);
8379 linkattr = be32_to_cpu(cmd->u.info32.linkattr32);
8384 dev_err(adapter->pdev_dev, "Handle Port Information: Bad Command/Action %#x\n",
8385 be32_to_cpu(cmd->action_to_len16));
8389 fec = fwcap_to_cc_fec(acaps);
8390 fc = fwcap_to_cc_pause(linkattr);
8391 speed = fwcap_to_speed(linkattr);
8393 lc->new_module = false;
8394 lc->redo_l1cfg = false;
8396 if (mod_type != pi->mod_type) {
8397 /* With the newer SFP28 and QSFP28 Transceiver Module Types,
8398 * various fundamental Port Capabilities which used to be
8399 * immutable can now change radically. We can now have
8400 * Speeds, Auto-Negotiation, Forward Error Correction, etc.
8401 * all change based on what Transceiver Module is inserted.
8402 * So we need to record the Physical "Port" Capabilities on
8403 * every Transceiver Module change.
8407 /* When a new Transceiver Module is inserted, the Firmware
8408 * will examine its i2c EPROM to determine its type and
8409 * general operating parameters including things like Forward
8410 * Error Control, etc. Various IEEE 802.3 standards dictate
8411 * how to interpret these i2c values to determine default
8412 * "sutomatic" settings. We record these for future use when
8413 * the user explicitly requests these standards-based values.
8415 lc->def_acaps = acaps;
8417 /* Some versions of the early T6 Firmware "cheated" when
8418 * handling different Transceiver Modules by changing the
8419 * underlaying Port Type reported to the Host Drivers. As
8420 * such we need to capture whatever Port Type the Firmware
8421 * sends us and record it in case it's different from what we
8422 * were told earlier. Unfortunately, since Firmware is
8423 * forever, we'll need to keep this code here forever, but in
8424 * later T6 Firmware it should just be an assignment of the
8425 * same value already recorded.
8427 pi->port_type = port_type;
8429 pi->mod_type = mod_type;
8431 lc->new_module = t4_is_inserted_mod_type(mod_type);
8432 t4_os_portmod_changed(adapter, pi->port_id);
8435 if (link_ok != lc->link_ok || speed != lc->speed ||
8436 fc != lc->fc || fec != lc->fec) { /* something changed */
8437 if (!link_ok && lc->link_ok) {
8438 lc->link_down_rc = linkdnrc;
8439 dev_warn(adapter->pdev_dev, "Port %d link down, reason: %s\n",
8440 pi->tx_chan, t4_link_down_rc_str(linkdnrc));
8442 lc->link_ok = link_ok;
8447 lc->lpacaps = lpacaps;
8448 lc->acaps = acaps & ADVERT_MASK;
8450 if (!(lc->acaps & FW_PORT_CAP32_ANEG)) {
8451 lc->autoneg = AUTONEG_DISABLE;
8452 } else if (lc->acaps & FW_PORT_CAP32_ANEG) {
8453 lc->autoneg = AUTONEG_ENABLE;
8455 /* When Autoneg is disabled, user needs to set
8457 * Similar to cxgb4_ethtool.c: set_link_ksettings
8460 lc->speed_caps = fwcap_to_fwspeed(acaps);
8461 lc->autoneg = AUTONEG_DISABLE;
8464 t4_os_link_changed(adapter, pi->port_id, link_ok);
8467 if (lc->new_module && lc->redo_l1cfg) {
8468 struct link_config old_lc;
8471 /* Save the current L1 Configuration and restore it if an
8472 * error occurs. We probably should fix the l1_cfg*()
8473 * routines not to change the link_config when an error
8477 ret = t4_link_l1cfg_ns(adapter, adapter->mbox, pi->lport, lc);
8480 dev_warn(adapter->pdev_dev,
8481 "Attempt to update new Transceiver Module settings failed\n");
8484 lc->new_module = false;
8485 lc->redo_l1cfg = false;
8489 * t4_update_port_info - retrieve and update port information if changed
8490 * @pi: the port_info
8492 * We issue a Get Port Information Command to the Firmware and, if
8493 * successful, we check to see if anything is different from what we
8494 * last recorded and update things accordingly.
8496 int t4_update_port_info(struct port_info *pi)
8498 unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8499 struct fw_port_cmd port_cmd;
8502 memset(&port_cmd, 0, sizeof(port_cmd));
8503 port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8504 FW_CMD_REQUEST_F | FW_CMD_READ_F |
8505 FW_PORT_CMD_PORTID_V(pi->tx_chan));
8506 port_cmd.action_to_len16 = cpu_to_be32(
8507 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
8508 ? FW_PORT_ACTION_GET_PORT_INFO
8509 : FW_PORT_ACTION_GET_PORT_INFO32) |
8510 FW_LEN16(port_cmd));
8511 ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8512 &port_cmd, sizeof(port_cmd), &port_cmd);
8516 t4_handle_get_port_info(pi, (__be64 *)&port_cmd);
8521 * t4_get_link_params - retrieve basic link parameters for given port
8523 * @link_okp: value return pointer for link up/down
8524 * @speedp: value return pointer for speed (Mb/s)
8525 * @mtup: value return pointer for mtu
8527 * Retrieves basic link parameters for a port: link up/down, speed (Mb/s),
8528 * and MTU for a specified port. A negative error is returned on
8529 * failure; 0 on success.
8531 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
8532 unsigned int *speedp, unsigned int *mtup)
8534 unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8535 struct fw_port_cmd port_cmd;
8536 unsigned int action, link_ok, speed, mtu;
8537 fw_port_cap32_t linkattr;
8540 memset(&port_cmd, 0, sizeof(port_cmd));
8541 port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8542 FW_CMD_REQUEST_F | FW_CMD_READ_F |
8543 FW_PORT_CMD_PORTID_V(pi->tx_chan));
8544 action = (fw_caps == FW_CAPS16
8545 ? FW_PORT_ACTION_GET_PORT_INFO
8546 : FW_PORT_ACTION_GET_PORT_INFO32);
8547 port_cmd.action_to_len16 = cpu_to_be32(
8548 FW_PORT_CMD_ACTION_V(action) |
8549 FW_LEN16(port_cmd));
8550 ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8551 &port_cmd, sizeof(port_cmd), &port_cmd);
8555 if (action == FW_PORT_ACTION_GET_PORT_INFO) {
8556 u32 lstatus = be32_to_cpu(port_cmd.u.info.lstatus_to_modtype);
8558 link_ok = !!(lstatus & FW_PORT_CMD_LSTATUS_F);
8559 linkattr = lstatus_to_fwcap(lstatus);
8560 mtu = be16_to_cpu(port_cmd.u.info.mtu);
8563 be32_to_cpu(port_cmd.u.info32.lstatus32_to_cbllen32);
8565 link_ok = !!(lstatus32 & FW_PORT_CMD_LSTATUS32_F);
8566 linkattr = be32_to_cpu(port_cmd.u.info32.linkattr32);
8567 mtu = FW_PORT_CMD_MTU32_G(
8568 be32_to_cpu(port_cmd.u.info32.auxlinfo32_mtu32));
8570 speed = fwcap_to_speed(linkattr);
8572 *link_okp = link_ok;
8573 *speedp = fwcap_to_speed(linkattr);
8580 * t4_handle_fw_rpl - process a FW reply message
8581 * @adap: the adapter
8582 * @rpl: start of the FW message
8584 * Processes a FW message, such as link state change messages.
8586 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
8588 u8 opcode = *(const u8 *)rpl;
8590 /* This might be a port command ... this simplifies the following
8591 * conditionals ... We can get away with pre-dereferencing
8592 * action_to_len16 because it's in the first 16 bytes and all messages
8593 * will be at least that long.
8595 const struct fw_port_cmd *p = (const void *)rpl;
8596 unsigned int action =
8597 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
8599 if (opcode == FW_PORT_CMD &&
8600 (action == FW_PORT_ACTION_GET_PORT_INFO ||
8601 action == FW_PORT_ACTION_GET_PORT_INFO32)) {
8603 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
8604 struct port_info *pi = NULL;
8606 for_each_port(adap, i) {
8607 pi = adap2pinfo(adap, i);
8608 if (pi->tx_chan == chan)
8612 t4_handle_get_port_info(pi, rpl);
8614 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n",
8621 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
8625 if (pci_is_pcie(adapter->pdev)) {
8626 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
8627 p->speed = val & PCI_EXP_LNKSTA_CLS;
8628 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
8633 * init_link_config - initialize a link's SW state
8634 * @lc: pointer to structure holding the link state
8635 * @pcaps: link Port Capabilities
8636 * @acaps: link current Advertised Port Capabilities
8638 * Initializes the SW state maintained for each link, including the link's
8639 * capabilities and default speed/flow-control/autonegotiation settings.
8641 static void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
8642 fw_port_cap32_t acaps)
8645 lc->def_acaps = acaps;
8649 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
8651 /* For Forward Error Control, we default to whatever the Firmware
8652 * tells us the Link is currently advertising.
8654 lc->requested_fec = FEC_AUTO;
8655 lc->fec = fwcap_to_cc_fec(lc->def_acaps);
8657 /* If the Port is capable of Auto-Negtotiation, initialize it as
8658 * "enabled" and copy over all of the Physical Port Capabilities
8659 * to the Advertised Port Capabilities. Otherwise mark it as
8660 * Auto-Negotiate disabled and select the highest supported speed
8661 * for the link. Note parallel structure in t4_link_l1cfg_core()
8662 * and t4_handle_get_port_info().
8664 if (lc->pcaps & FW_PORT_CAP32_ANEG) {
8665 lc->acaps = lc->pcaps & ADVERT_MASK;
8666 lc->autoneg = AUTONEG_ENABLE;
8667 lc->requested_fc |= PAUSE_AUTONEG;
8670 lc->autoneg = AUTONEG_DISABLE;
8671 lc->speed_caps = fwcap_to_fwspeed(acaps);
8675 #define CIM_PF_NOACCESS 0xeeeeeeee
8677 int t4_wait_dev_ready(void __iomem *regs)
8681 whoami = readl(regs + PL_WHOAMI_A);
8682 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
8686 whoami = readl(regs + PL_WHOAMI_A);
8687 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
8691 u32 vendor_and_model_id;
8695 static int t4_get_flash_params(struct adapter *adap)
8697 /* Table for non-Numonix supported flash parts. Numonix parts are left
8698 * to the preexisting code. All flash parts have 64KB sectors.
8700 static struct flash_desc supported_flash[] = {
8701 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
8704 unsigned int part, manufacturer;
8705 unsigned int density, size = 0;
8709 /* Issue a Read ID Command to the Flash part. We decode supported
8710 * Flash parts and their sizes from this. There's a newer Query
8711 * Command which can retrieve detailed geometry information but many
8712 * Flash parts don't support it.
8715 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
8717 ret = sf1_read(adap, 3, 0, 1, &flashid);
8718 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
8722 /* Check to see if it's one of our non-standard supported Flash parts.
8724 for (part = 0; part < ARRAY_SIZE(supported_flash); part++)
8725 if (supported_flash[part].vendor_and_model_id == flashid) {
8726 adap->params.sf_size = supported_flash[part].size_mb;
8727 adap->params.sf_nsec =
8728 adap->params.sf_size / SF_SEC_SIZE;
8732 /* Decode Flash part size. The code below looks repetative with
8733 * common encodings, but that's not guaranteed in the JEDEC
8734 * specification for the Read JADEC ID command. The only thing that
8735 * we're guaranteed by the JADEC specification is where the
8736 * Manufacturer ID is in the returned result. After that each
8737 * Manufacturer ~could~ encode things completely differently.
8738 * Note, all Flash parts must have 64KB sectors.
8740 manufacturer = flashid & 0xff;
8741 switch (manufacturer) {
8742 case 0x20: { /* Micron/Numonix */
8743 /* This Density -> Size decoding table is taken from Micron
8746 density = (flashid >> 16) & 0xff;
8748 case 0x14: /* 1MB */
8751 case 0x15: /* 2MB */
8754 case 0x16: /* 4MB */
8757 case 0x17: /* 8MB */
8760 case 0x18: /* 16MB */
8763 case 0x19: /* 32MB */
8766 case 0x20: /* 64MB */
8769 case 0x21: /* 128MB */
8772 case 0x22: /* 256MB */
8778 case 0x9d: { /* ISSI -- Integrated Silicon Solution, Inc. */
8779 /* This Density -> Size decoding table is taken from ISSI
8782 density = (flashid >> 16) & 0xff;
8784 case 0x16: /* 32 MB */
8787 case 0x17: /* 64MB */
8793 case 0xc2: { /* Macronix */
8794 /* This Density -> Size decoding table is taken from Macronix
8797 density = (flashid >> 16) & 0xff;
8799 case 0x17: /* 8MB */
8802 case 0x18: /* 16MB */
8808 case 0xef: { /* Winbond */
8809 /* This Density -> Size decoding table is taken from Winbond
8812 density = (flashid >> 16) & 0xff;
8814 case 0x17: /* 8MB */
8817 case 0x18: /* 16MB */
8825 /* If we didn't recognize the FLASH part, that's no real issue: the
8826 * Hardware/Software contract says that Hardware will _*ALWAYS*_
8827 * use a FLASH part which is at least 4MB in size and has 64KB
8828 * sectors. The unrecognized FLASH part is likely to be much larger
8829 * than 4MB, but that's all we really need.
8832 dev_warn(adap->pdev_dev, "Unknown Flash Part, ID = %#x, assuming 4MB\n",
8837 /* Store decoded Flash size and fall through into vetting code. */
8838 adap->params.sf_size = size;
8839 adap->params.sf_nsec = size / SF_SEC_SIZE;
8842 if (adap->params.sf_size < FLASH_MIN_SIZE)
8843 dev_warn(adap->pdev_dev, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
8844 flashid, adap->params.sf_size, FLASH_MIN_SIZE);
8849 * t4_prep_adapter - prepare SW and HW for operation
8850 * @adapter: the adapter
8851 * @reset: if true perform a HW reset
8853 * Initialize adapter SW state for the various HW modules, set initial
8854 * values for some adapter tunables, take PHYs out of reset, and
8855 * initialize the MDIO interface.
8857 int t4_prep_adapter(struct adapter *adapter)
8863 get_pci_mode(adapter, &adapter->params.pci);
8864 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
8866 ret = t4_get_flash_params(adapter);
8868 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
8872 /* Retrieve adapter's device ID
8874 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
8875 ver = device_id >> 12;
8876 adapter->params.chip = 0;
8879 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
8880 adapter->params.arch.sge_fl_db = DBPRIO_F;
8881 adapter->params.arch.mps_tcam_size =
8882 NUM_MPS_CLS_SRAM_L_INSTANCES;
8883 adapter->params.arch.mps_rplc_size = 128;
8884 adapter->params.arch.nchan = NCHAN;
8885 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
8886 adapter->params.arch.vfcount = 128;
8887 /* Congestion map is for 4 channels so that
8888 * MPS can have 4 priority per port.
8890 adapter->params.arch.cng_ch_bits_log = 2;
8893 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
8894 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
8895 adapter->params.arch.mps_tcam_size =
8896 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8897 adapter->params.arch.mps_rplc_size = 128;
8898 adapter->params.arch.nchan = NCHAN;
8899 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
8900 adapter->params.arch.vfcount = 128;
8901 adapter->params.arch.cng_ch_bits_log = 2;
8904 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
8905 adapter->params.arch.sge_fl_db = 0;
8906 adapter->params.arch.mps_tcam_size =
8907 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8908 adapter->params.arch.mps_rplc_size = 256;
8909 adapter->params.arch.nchan = 2;
8910 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
8911 adapter->params.arch.vfcount = 256;
8912 /* Congestion map will be for 2 channels so that
8913 * MPS can have 8 priority per port.
8915 adapter->params.arch.cng_ch_bits_log = 3;
8918 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
8923 adapter->params.cim_la_size = CIMLA_SIZE;
8924 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
8927 * Default port for debugging in case we can't reach FW.
8929 adapter->params.nports = 1;
8930 adapter->params.portvec = 1;
8931 adapter->params.vpd.cclk = 50000;
8933 /* Set PCIe completion timeout to 4 seconds. */
8934 pcie_capability_clear_and_set_word(adapter->pdev, PCI_EXP_DEVCTL2,
8935 PCI_EXP_DEVCTL2_COMP_TIMEOUT, 0xd);
8940 * t4_shutdown_adapter - shut down adapter, host & wire
8941 * @adapter: the adapter
8943 * Perform an emergency shutdown of the adapter and stop it from
8944 * continuing any further communication on the ports or DMA to the
8945 * host. This is typically used when the adapter and/or firmware
8946 * have crashed and we want to prevent any further accidental
8947 * communication with the rest of the world. This will also force
8948 * the port Link Status to go down -- if register writes work --
8949 * which should help our peers figure out that we're down.
8951 int t4_shutdown_adapter(struct adapter *adapter)
8955 t4_intr_disable(adapter);
8956 t4_write_reg(adapter, DBG_GPIO_EN_A, 0);
8957 for_each_port(adapter, port) {
8958 u32 a_port_cfg = is_t4(adapter->params.chip) ?
8959 PORT_REG(port, XGMAC_PORT_CFG_A) :
8960 T5_PORT_REG(port, MAC_PORT_CFG_A);
8962 t4_write_reg(adapter, a_port_cfg,
8963 t4_read_reg(adapter, a_port_cfg)
8964 & ~SIGNAL_DET_V(1));
8966 t4_set_reg_field(adapter, SGE_CONTROL_A, GLOBALENABLE_F, 0);
8972 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
8973 * @adapter: the adapter
8974 * @qid: the Queue ID
8975 * @qtype: the Ingress or Egress type for @qid
8976 * @user: true if this request is for a user mode queue
8977 * @pbar2_qoffset: BAR2 Queue Offset
8978 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
8980 * Returns the BAR2 SGE Queue Registers information associated with the
8981 * indicated Absolute Queue ID. These are passed back in return value
8982 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
8983 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
8985 * This may return an error which indicates that BAR2 SGE Queue
8986 * registers aren't available. If an error is not returned, then the
8987 * following values are returned:
8989 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
8990 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
8992 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
8993 * require the "Inferred Queue ID" ability may be used. E.g. the
8994 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
8995 * then these "Inferred Queue ID" register may not be used.
8997 int t4_bar2_sge_qregs(struct adapter *adapter,
8999 enum t4_bar2_qtype qtype,
9002 unsigned int *pbar2_qid)
9004 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
9005 u64 bar2_page_offset, bar2_qoffset;
9006 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
9008 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
9009 if (!user && is_t4(adapter->params.chip))
9012 /* Get our SGE Page Size parameters.
9014 page_shift = adapter->params.sge.hps + 10;
9015 page_size = 1 << page_shift;
9017 /* Get the right Queues per Page parameters for our Queue.
9019 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
9020 ? adapter->params.sge.eq_qpp
9021 : adapter->params.sge.iq_qpp);
9022 qpp_mask = (1 << qpp_shift) - 1;
9024 /* Calculate the basics of the BAR2 SGE Queue register area:
9025 * o The BAR2 page the Queue registers will be in.
9026 * o The BAR2 Queue ID.
9027 * o The BAR2 Queue ID Offset into the BAR2 page.
9029 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
9030 bar2_qid = qid & qpp_mask;
9031 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
9033 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
9034 * hardware will infer the Absolute Queue ID simply from the writes to
9035 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
9036 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
9037 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
9038 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
9039 * from the BAR2 Page and BAR2 Queue ID.
9041 * One important censequence of this is that some BAR2 SGE registers
9042 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
9043 * there. But other registers synthesize the SGE Queue ID purely
9044 * from the writes to the registers -- the Write Combined Doorbell
9045 * Buffer is a good example. These BAR2 SGE Registers are only
9046 * available for those BAR2 SGE Register areas where the SGE Absolute
9047 * Queue ID can be inferred from simple writes.
9049 bar2_qoffset = bar2_page_offset;
9050 bar2_qinferred = (bar2_qid_offset < page_size);
9051 if (bar2_qinferred) {
9052 bar2_qoffset += bar2_qid_offset;
9056 *pbar2_qoffset = bar2_qoffset;
9057 *pbar2_qid = bar2_qid;
9062 * t4_init_devlog_params - initialize adapter->params.devlog
9063 * @adap: the adapter
9065 * Initialize various fields of the adapter's Firmware Device Log
9066 * Parameters structure.
9068 int t4_init_devlog_params(struct adapter *adap)
9070 struct devlog_params *dparams = &adap->params.devlog;
9072 unsigned int devlog_meminfo;
9073 struct fw_devlog_cmd devlog_cmd;
9076 /* If we're dealing with newer firmware, the Device Log Paramerters
9077 * are stored in a designated register which allows us to access the
9078 * Device Log even if we can't talk to the firmware.
9081 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
9083 unsigned int nentries, nentries128;
9085 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
9086 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
9088 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
9089 nentries = (nentries128 + 1) * 128;
9090 dparams->size = nentries * sizeof(struct fw_devlog_e);
9095 /* Otherwise, ask the firmware for it's Device Log Parameters.
9097 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
9098 devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
9099 FW_CMD_REQUEST_F | FW_CMD_READ_F);
9100 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9101 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
9107 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
9108 dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
9109 dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
9110 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
9116 * t4_init_sge_params - initialize adap->params.sge
9117 * @adapter: the adapter
9119 * Initialize various fields of the adapter's SGE Parameters structure.
9121 int t4_init_sge_params(struct adapter *adapter)
9123 struct sge_params *sge_params = &adapter->params.sge;
9125 unsigned int s_hps, s_qpp;
9127 /* Extract the SGE Page Size for our PF.
9129 hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
9130 s_hps = (HOSTPAGESIZEPF0_S +
9131 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
9132 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
9134 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
9136 s_qpp = (QUEUESPERPAGEPF0_S +
9137 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
9138 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
9139 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
9140 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
9141 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
9147 * t4_init_tp_params - initialize adap->params.tp
9148 * @adap: the adapter
9149 * @sleep_ok: if true we may sleep while awaiting command completion
9151 * Initialize various fields of the adapter's TP Parameters structure.
9153 int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
9158 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
9159 adap->params.tp.tre = TIMERRESOLUTION_G(v);
9160 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
9162 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
9163 for (chan = 0; chan < NCHAN; chan++)
9164 adap->params.tp.tx_modq[chan] = chan;
9166 /* Cache the adapter's Compressed Filter Mode and global Incress
9169 t4_tp_pio_read(adap, &adap->params.tp.vlan_pri_map, 1,
9170 TP_VLAN_PRI_MAP_A, sleep_ok);
9171 t4_tp_pio_read(adap, &adap->params.tp.ingress_config, 1,
9172 TP_INGRESS_CONFIG_A, sleep_ok);
9174 /* For T6, cache the adapter's compressed error vector
9175 * and passing outer header info for encapsulated packets.
9177 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
9178 v = t4_read_reg(adap, TP_OUT_CONFIG_A);
9179 adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0;
9182 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
9183 * shift positions of several elements of the Compressed Filter Tuple
9184 * for this adapter which we need frequently ...
9186 adap->params.tp.fcoe_shift = t4_filter_field_shift(adap, FCOE_F);
9187 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
9188 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
9189 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
9190 adap->params.tp.tos_shift = t4_filter_field_shift(adap, TOS_F);
9191 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
9193 adap->params.tp.ethertype_shift = t4_filter_field_shift(adap,
9195 adap->params.tp.macmatch_shift = t4_filter_field_shift(adap,
9197 adap->params.tp.matchtype_shift = t4_filter_field_shift(adap,
9199 adap->params.tp.frag_shift = t4_filter_field_shift(adap,
9202 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
9203 * represents the presence of an Outer VLAN instead of a VNIC ID.
9205 if ((adap->params.tp.ingress_config & VNIC_F) == 0)
9206 adap->params.tp.vnic_shift = -1;
9208 v = t4_read_reg(adap, LE_3_DB_HASH_MASK_GEN_IPV4_T6_A);
9209 adap->params.tp.hash_filter_mask = v;
9210 v = t4_read_reg(adap, LE_4_DB_HASH_MASK_GEN_IPV4_T6_A);
9211 adap->params.tp.hash_filter_mask |= ((u64)v << 32);
9216 * t4_filter_field_shift - calculate filter field shift
9217 * @adap: the adapter
9218 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
9220 * Return the shift position of a filter field within the Compressed
9221 * Filter Tuple. The filter field is specified via its selection bit
9222 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
9224 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
9226 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
9230 if ((filter_mode & filter_sel) == 0)
9233 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
9234 switch (filter_mode & sel) {
9236 field_shift += FT_FCOE_W;
9239 field_shift += FT_PORT_W;
9242 field_shift += FT_VNIC_ID_W;
9245 field_shift += FT_VLAN_W;
9248 field_shift += FT_TOS_W;
9251 field_shift += FT_PROTOCOL_W;
9254 field_shift += FT_ETHERTYPE_W;
9257 field_shift += FT_MACMATCH_W;
9260 field_shift += FT_MPSHITTYPE_W;
9262 case FRAGMENTATION_F:
9263 field_shift += FT_FRAGMENTATION_W;
9270 int t4_init_rss_mode(struct adapter *adap, int mbox)
9273 struct fw_rss_vi_config_cmd rvc;
9275 memset(&rvc, 0, sizeof(rvc));
9277 for_each_port(adap, i) {
9278 struct port_info *p = adap2pinfo(adap, i);
9281 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
9282 FW_CMD_REQUEST_F | FW_CMD_READ_F |
9283 FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
9284 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
9285 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
9288 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
9294 * t4_init_portinfo - allocate a virtual interface and initialize port_info
9295 * @pi: the port_info
9296 * @mbox: mailbox to use for the FW command
9297 * @port: physical port associated with the VI
9298 * @pf: the PF owning the VI
9299 * @vf: the VF owning the VI
9300 * @mac: the MAC address of the VI
9302 * Allocates a virtual interface for the given physical port. If @mac is
9303 * not %NULL it contains the MAC address of the VI as assigned by FW.
9304 * @mac should be large enough to hold an Ethernet address.
9305 * Returns < 0 on error.
9307 int t4_init_portinfo(struct port_info *pi, int mbox,
9308 int port, int pf, int vf, u8 mac[])
9310 struct adapter *adapter = pi->adapter;
9311 unsigned int fw_caps = adapter->params.fw_caps_support;
9312 struct fw_port_cmd cmd;
9313 unsigned int rss_size;
9314 enum fw_port_type port_type;
9316 fw_port_cap32_t pcaps, acaps;
9319 /* If we haven't yet determined whether we're talking to Firmware
9320 * which knows the new 32-bit Port Capabilities, it's time to find
9321 * out now. This will also tell new Firmware to send us Port Status
9322 * Updates using the new 32-bit Port Capabilities version of the
9323 * Port Information message.
9325 if (fw_caps == FW_CAPS_UNKNOWN) {
9328 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
9329 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_PORT_CAPS32));
9331 ret = t4_set_params(adapter, mbox, pf, vf, 1, ¶m, &val);
9332 fw_caps = (ret == 0 ? FW_CAPS32 : FW_CAPS16);
9333 adapter->params.fw_caps_support = fw_caps;
9336 memset(&cmd, 0, sizeof(cmd));
9337 cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
9338 FW_CMD_REQUEST_F | FW_CMD_READ_F |
9339 FW_PORT_CMD_PORTID_V(port));
9340 cmd.action_to_len16 = cpu_to_be32(
9341 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
9342 ? FW_PORT_ACTION_GET_PORT_INFO
9343 : FW_PORT_ACTION_GET_PORT_INFO32) |
9345 ret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd);
9349 /* Extract the various fields from the Port Information message.
9351 if (fw_caps == FW_CAPS16) {
9352 u32 lstatus = be32_to_cpu(cmd.u.info.lstatus_to_modtype);
9354 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
9355 mdio_addr = ((lstatus & FW_PORT_CMD_MDIOCAP_F)
9356 ? FW_PORT_CMD_MDIOADDR_G(lstatus)
9358 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.pcap));
9359 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.acap));
9361 u32 lstatus32 = be32_to_cpu(cmd.u.info32.lstatus32_to_cbllen32);
9363 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
9364 mdio_addr = ((lstatus32 & FW_PORT_CMD_MDIOCAP32_F)
9365 ? FW_PORT_CMD_MDIOADDR32_G(lstatus32)
9367 pcaps = be32_to_cpu(cmd.u.info32.pcaps32);
9368 acaps = be32_to_cpu(cmd.u.info32.acaps32);
9371 ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size);
9378 pi->rss_size = rss_size;
9380 pi->port_type = port_type;
9381 pi->mdio_addr = mdio_addr;
9382 pi->mod_type = FW_PORT_MOD_TYPE_NA;
9384 init_link_config(&pi->link_cfg, pcaps, acaps);
9388 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
9393 for_each_port(adap, i) {
9394 struct port_info *pi = adap2pinfo(adap, i);
9396 while ((adap->params.portvec & (1 << j)) == 0)
9399 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
9403 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
9410 * t4_read_cimq_cfg - read CIM queue configuration
9411 * @adap: the adapter
9412 * @base: holds the queue base addresses in bytes
9413 * @size: holds the queue sizes in bytes
9414 * @thres: holds the queue full thresholds in bytes
9416 * Returns the current configuration of the CIM queues, starting with
9417 * the IBQs, then the OBQs.
9419 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
9422 int cim_num_obq = is_t4(adap->params.chip) ?
9423 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9425 for (i = 0; i < CIM_NUM_IBQ; i++) {
9426 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
9428 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9429 /* value is in 256-byte units */
9430 *base++ = CIMQBASE_G(v) * 256;
9431 *size++ = CIMQSIZE_G(v) * 256;
9432 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
9434 for (i = 0; i < cim_num_obq; i++) {
9435 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9437 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9438 /* value is in 256-byte units */
9439 *base++ = CIMQBASE_G(v) * 256;
9440 *size++ = CIMQSIZE_G(v) * 256;
9445 * t4_read_cim_ibq - read the contents of a CIM inbound queue
9446 * @adap: the adapter
9447 * @qid: the queue index
9448 * @data: where to store the queue contents
9449 * @n: capacity of @data in 32-bit words
9451 * Reads the contents of the selected CIM queue starting at address 0 up
9452 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9453 * error and the number of 32-bit words actually read on success.
9455 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9457 int i, err, attempts;
9459 const unsigned int nwords = CIM_IBQ_SIZE * 4;
9461 if (qid > 5 || (n & 3))
9464 addr = qid * nwords;
9468 /* It might take 3-10ms before the IBQ debug read access is allowed.
9469 * Wait for 1 Sec with a delay of 1 usec.
9473 for (i = 0; i < n; i++, addr++) {
9474 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
9476 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
9480 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
9482 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
9487 * t4_read_cim_obq - read the contents of a CIM outbound queue
9488 * @adap: the adapter
9489 * @qid: the queue index
9490 * @data: where to store the queue contents
9491 * @n: capacity of @data in 32-bit words
9493 * Reads the contents of the selected CIM queue starting at address 0 up
9494 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9495 * error and the number of 32-bit words actually read on success.
9497 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9500 unsigned int addr, v, nwords;
9501 int cim_num_obq = is_t4(adap->params.chip) ?
9502 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9504 if ((qid > (cim_num_obq - 1)) || (n & 3))
9507 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9508 QUENUMSELECT_V(qid));
9509 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9511 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
9512 nwords = CIMQSIZE_G(v) * 64; /* same */
9516 for (i = 0; i < n; i++, addr++) {
9517 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
9519 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
9523 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
9525 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
9530 * t4_cim_read - read a block from CIM internal address space
9531 * @adap: the adapter
9532 * @addr: the start address within the CIM address space
9533 * @n: number of words to read
9534 * @valp: where to store the result
9536 * Reads a block of 4-byte words from the CIM intenal address space.
9538 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
9543 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9546 for ( ; !ret && n--; addr += 4) {
9547 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
9548 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9551 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
9557 * t4_cim_write - write a block into CIM internal address space
9558 * @adap: the adapter
9559 * @addr: the start address within the CIM address space
9560 * @n: number of words to write
9561 * @valp: set of values to write
9563 * Writes a block of 4-byte words into the CIM intenal address space.
9565 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
9566 const unsigned int *valp)
9570 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9573 for ( ; !ret && n--; addr += 4) {
9574 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
9575 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
9576 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9582 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
9585 return t4_cim_write(adap, addr, 1, &val);
9589 * t4_cim_read_la - read CIM LA capture buffer
9590 * @adap: the adapter
9591 * @la_buf: where to store the LA data
9592 * @wrptr: the HW write pointer within the capture buffer
9594 * Reads the contents of the CIM LA buffer with the most recent entry at
9595 * the end of the returned data and with the entry at @wrptr first.
9596 * We try to leave the LA in the running state we find it in.
9598 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
9601 unsigned int cfg, val, idx;
9603 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
9607 if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
9608 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
9613 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9617 idx = UPDBGLAWRPTR_G(val);
9621 for (i = 0; i < adap->params.cim_la_size; i++) {
9622 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9623 UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
9626 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9629 if (val & UPDBGLARDEN_F) {
9633 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
9637 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
9638 * identify the 32-bit portion of the full 312-bit data
9640 if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
9641 idx = (idx & 0xff0) + 0x10;
9644 /* address can't exceed 0xfff */
9645 idx &= UPDBGLARDPTR_M;
9648 if (cfg & UPDBGLAEN_F) {
9649 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9650 cfg & ~UPDBGLARDEN_F);
9658 * t4_tp_read_la - read TP LA capture buffer
9659 * @adap: the adapter
9660 * @la_buf: where to store the LA data
9661 * @wrptr: the HW write pointer within the capture buffer
9663 * Reads the contents of the TP LA buffer with the most recent entry at
9664 * the end of the returned data and with the entry at @wrptr first.
9665 * We leave the LA in the running state we find it in.
9667 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
9669 bool last_incomplete;
9670 unsigned int i, cfg, val, idx;
9672 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
9673 if (cfg & DBGLAENABLE_F) /* freeze LA */
9674 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
9675 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
9677 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
9678 idx = DBGLAWPTR_G(val);
9679 last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
9680 if (last_incomplete)
9681 idx = (idx + 1) & DBGLARPTR_M;
9686 val &= ~DBGLARPTR_V(DBGLARPTR_M);
9687 val |= adap->params.tp.la_mask;
9689 for (i = 0; i < TPLA_SIZE; i++) {
9690 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
9691 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
9692 idx = (idx + 1) & DBGLARPTR_M;
9695 /* Wipe out last entry if it isn't valid */
9696 if (last_incomplete)
9697 la_buf[TPLA_SIZE - 1] = ~0ULL;
9699 if (cfg & DBGLAENABLE_F) /* restore running state */
9700 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
9701 cfg | adap->params.tp.la_mask);
9704 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
9705 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
9706 * state for more than the Warning Threshold then we'll issue a warning about
9707 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
9708 * appears to be hung every Warning Repeat second till the situation clears.
9709 * If the situation clears, we'll note that as well.
9711 #define SGE_IDMA_WARN_THRESH 1
9712 #define SGE_IDMA_WARN_REPEAT 300
9715 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
9716 * @adapter: the adapter
9717 * @idma: the adapter IDMA Monitor state
9719 * Initialize the state of an SGE Ingress DMA Monitor.
9721 void t4_idma_monitor_init(struct adapter *adapter,
9722 struct sge_idma_monitor_state *idma)
9724 /* Initialize the state variables for detecting an SGE Ingress DMA
9725 * hang. The SGE has internal counters which count up on each clock
9726 * tick whenever the SGE finds its Ingress DMA State Engines in the
9727 * same state they were on the previous clock tick. The clock used is
9728 * the Core Clock so we have a limit on the maximum "time" they can
9729 * record; typically a very small number of seconds. For instance,
9730 * with a 600MHz Core Clock, we can only count up to a bit more than
9731 * 7s. So we'll synthesize a larger counter in order to not run the
9732 * risk of having the "timers" overflow and give us the flexibility to
9733 * maintain a Hung SGE State Machine of our own which operates across
9734 * a longer time frame.
9736 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
9737 idma->idma_stalled[0] = 0;
9738 idma->idma_stalled[1] = 0;
9742 * t4_idma_monitor - monitor SGE Ingress DMA state
9743 * @adapter: the adapter
9744 * @idma: the adapter IDMA Monitor state
9745 * @hz: number of ticks/second
9746 * @ticks: number of ticks since the last IDMA Monitor call
9748 void t4_idma_monitor(struct adapter *adapter,
9749 struct sge_idma_monitor_state *idma,
9752 int i, idma_same_state_cnt[2];
9754 /* Read the SGE Debug Ingress DMA Same State Count registers. These
9755 * are counters inside the SGE which count up on each clock when the
9756 * SGE finds its Ingress DMA State Engines in the same states they
9757 * were in the previous clock. The counters will peg out at
9758 * 0xffffffff without wrapping around so once they pass the 1s
9759 * threshold they'll stay above that till the IDMA state changes.
9761 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
9762 idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
9763 idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9765 for (i = 0; i < 2; i++) {
9766 u32 debug0, debug11;
9768 /* If the Ingress DMA Same State Counter ("timer") is less
9769 * than 1s, then we can reset our synthesized Stall Timer and
9770 * continue. If we have previously emitted warnings about a
9771 * potential stalled Ingress Queue, issue a note indicating
9772 * that the Ingress Queue has resumed forward progress.
9774 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
9775 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
9776 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
9777 "resumed after %d seconds\n",
9778 i, idma->idma_qid[i],
9779 idma->idma_stalled[i] / hz);
9780 idma->idma_stalled[i] = 0;
9784 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
9785 * domain. The first time we get here it'll be because we
9786 * passed the 1s Threshold; each additional time it'll be
9787 * because the RX Timer Callback is being fired on its regular
9790 * If the stall is below our Potential Hung Ingress Queue
9791 * Warning Threshold, continue.
9793 if (idma->idma_stalled[i] == 0) {
9794 idma->idma_stalled[i] = hz;
9795 idma->idma_warn[i] = 0;
9797 idma->idma_stalled[i] += ticks;
9798 idma->idma_warn[i] -= ticks;
9801 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
9804 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
9806 if (idma->idma_warn[i] > 0)
9808 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
9810 /* Read and save the SGE IDMA State and Queue ID information.
9811 * We do this every time in case it changes across time ...
9812 * can't be too careful ...
9814 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
9815 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9816 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
9818 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
9819 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9820 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
9822 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
9823 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
9824 i, idma->idma_qid[i], idma->idma_state[i],
9825 idma->idma_stalled[i] / hz,
9827 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
9832 * t4_load_cfg - download config file
9833 * @adap: the adapter
9834 * @cfg_data: the cfg text file to write
9835 * @size: text file size
9837 * Write the supplied config text file to the card's serial flash.
9839 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
9841 int ret, i, n, cfg_addr;
9843 unsigned int flash_cfg_start_sec;
9844 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
9846 cfg_addr = t4_flash_cfg_addr(adap);
9851 flash_cfg_start_sec = addr / SF_SEC_SIZE;
9853 if (size > FLASH_CFG_MAX_SIZE) {
9854 dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n",
9855 FLASH_CFG_MAX_SIZE);
9859 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */
9861 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
9862 flash_cfg_start_sec + i - 1);
9863 /* If size == 0 then we're simply erasing the FLASH sectors associated
9864 * with the on-adapter Firmware Configuration File.
9866 if (ret || size == 0)
9869 /* this will write to the flash up to SF_PAGE_SIZE at a time */
9870 for (i = 0; i < size; i += SF_PAGE_SIZE) {
9871 if ((size - i) < SF_PAGE_SIZE)
9875 ret = t4_write_flash(adap, addr, n, cfg_data);
9879 addr += SF_PAGE_SIZE;
9880 cfg_data += SF_PAGE_SIZE;
9885 dev_err(adap->pdev_dev, "config file %s failed %d\n",
9886 (size == 0 ? "clear" : "download"), ret);
9891 * t4_set_vf_mac - Set MAC address for the specified VF
9892 * @adapter: The adapter
9893 * @vf: one of the VFs instantiated by the specified PF
9894 * @naddr: the number of MAC addresses
9895 * @addr: the MAC address(es) to be set to the specified VF
9897 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
9898 unsigned int naddr, u8 *addr)
9900 struct fw_acl_mac_cmd cmd;
9902 memset(&cmd, 0, sizeof(cmd));
9903 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
9906 FW_ACL_MAC_CMD_PFN_V(adapter->pf) |
9907 FW_ACL_MAC_CMD_VFN_V(vf));
9909 /* Note: Do not enable the ACL */
9910 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
9913 switch (adapter->pf) {
9915 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
9918 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
9921 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
9924 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
9928 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
9932 * t4_read_pace_tbl - read the pace table
9933 * @adap: the adapter
9934 * @pace_vals: holds the returned values
9936 * Returns the values of TP's pace table in microseconds.
9938 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
9942 for (i = 0; i < NTX_SCHED; i++) {
9943 t4_write_reg(adap, TP_PACE_TABLE_A, 0xffff0000 + i);
9944 v = t4_read_reg(adap, TP_PACE_TABLE_A);
9945 pace_vals[i] = dack_ticks_to_usec(adap, v);
9950 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
9951 * @adap: the adapter
9952 * @sched: the scheduler index
9953 * @kbps: the byte rate in Kbps
9954 * @ipg: the interpacket delay in tenths of nanoseconds
9955 * @sleep_ok: if true we may sleep while awaiting command completion
9957 * Return the current configuration of a HW Tx scheduler.
9959 void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
9960 unsigned int *kbps, unsigned int *ipg, bool sleep_ok)
9962 unsigned int v, addr, bpt, cpt;
9965 addr = TP_TX_MOD_Q1_Q0_RATE_LIMIT_A - sched / 2;
9966 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
9969 bpt = (v >> 8) & 0xff;
9972 *kbps = 0; /* scheduler disabled */
9974 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
9975 *kbps = (v * bpt) / 125;
9979 addr = TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A - sched / 2;
9980 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
9984 *ipg = (10000 * v) / core_ticks_per_usec(adap);
9988 /* t4_sge_ctxt_rd - read an SGE context through FW
9989 * @adap: the adapter
9990 * @mbox: mailbox to use for the FW command
9991 * @cid: the context id
9992 * @ctype: the context type
9993 * @data: where to store the context data
9995 * Issues a FW command through the given mailbox to read an SGE context.
9997 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
9998 enum ctxt_type ctype, u32 *data)
10000 struct fw_ldst_cmd c;
10003 if (ctype == CTXT_FLM)
10004 ret = FW_LDST_ADDRSPC_SGE_FLMC;
10006 ret = FW_LDST_ADDRSPC_SGE_CONMC;
10008 memset(&c, 0, sizeof(c));
10009 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
10010 FW_CMD_REQUEST_F | FW_CMD_READ_F |
10011 FW_LDST_CMD_ADDRSPACE_V(ret));
10012 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
10013 c.u.idctxt.physid = cpu_to_be32(cid);
10015 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
10017 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
10018 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
10019 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
10020 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
10021 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
10022 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
10028 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
10029 * @adap: the adapter
10030 * @cid: the context id
10031 * @ctype: the context type
10032 * @data: where to store the context data
10034 * Reads an SGE context directly, bypassing FW. This is only for
10035 * debugging when FW is unavailable.
10037 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
10038 enum ctxt_type ctype, u32 *data)
10042 t4_write_reg(adap, SGE_CTXT_CMD_A, CTXTQID_V(cid) | CTXTTYPE_V(ctype));
10043 ret = t4_wait_op_done(adap, SGE_CTXT_CMD_A, BUSY_F, 0, 3, 1);
10045 for (i = SGE_CTXT_DATA0_A; i <= SGE_CTXT_DATA5_A; i += 4)
10046 *data++ = t4_read_reg(adap, i);
10050 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
10051 int rateunit, int ratemode, int channel, int class,
10052 int minrate, int maxrate, int weight, int pktsize)
10054 struct fw_sched_cmd cmd;
10056 memset(&cmd, 0, sizeof(cmd));
10057 cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD) |
10060 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10062 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
10063 cmd.u.params.type = type;
10064 cmd.u.params.level = level;
10065 cmd.u.params.mode = mode;
10066 cmd.u.params.ch = channel;
10067 cmd.u.params.cl = class;
10068 cmd.u.params.unit = rateunit;
10069 cmd.u.params.rate = ratemode;
10070 cmd.u.params.min = cpu_to_be32(minrate);
10071 cmd.u.params.max = cpu_to_be32(maxrate);
10072 cmd.u.params.weight = cpu_to_be16(weight);
10073 cmd.u.params.pktsize = cpu_to_be16(pktsize);
10075 return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),
10080 * t4_i2c_rd - read I2C data from adapter
10081 * @adap: the adapter
10082 * @port: Port number if per-port device; <0 if not
10083 * @devid: per-port device ID or absolute device ID
10084 * @offset: byte offset into device I2C space
10085 * @len: byte length of I2C space data
10086 * @buf: buffer in which to return I2C data
10088 * Reads the I2C data from the indicated device and location.
10090 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
10091 unsigned int devid, unsigned int offset,
10092 unsigned int len, u8 *buf)
10094 struct fw_ldst_cmd ldst_cmd, ldst_rpl;
10095 unsigned int i2c_max = sizeof(ldst_cmd.u.i2c.data);
10098 if (len > I2C_PAGE_SIZE)
10101 /* Dont allow reads that spans multiple pages */
10102 if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE)
10105 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
10106 ldst_cmd.op_to_addrspace =
10107 cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
10110 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_I2C));
10111 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
10112 ldst_cmd.u.i2c.pid = (port < 0 ? 0xff : port);
10113 ldst_cmd.u.i2c.did = devid;
10116 unsigned int i2c_len = (len < i2c_max) ? len : i2c_max;
10118 ldst_cmd.u.i2c.boffset = offset;
10119 ldst_cmd.u.i2c.blen = i2c_len;
10121 ret = t4_wr_mbox(adap, mbox, &ldst_cmd, sizeof(ldst_cmd),
10126 memcpy(buf, ldst_rpl.u.i2c.data, i2c_len);
10136 * t4_set_vlan_acl - Set a VLAN id for the specified VF
10137 * @adapter: the adapter
10138 * @mbox: mailbox to use for the FW command
10139 * @vf: one of the VFs instantiated by the specified PF
10140 * @vlan: The vlanid to be set
10142 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
10145 struct fw_acl_vlan_cmd vlan_cmd;
10146 unsigned int enable;
10148 enable = (vlan ? FW_ACL_VLAN_CMD_EN_F : 0);
10149 memset(&vlan_cmd, 0, sizeof(vlan_cmd));
10150 vlan_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_VLAN_CMD) |
10154 FW_ACL_VLAN_CMD_PFN_V(adap->pf) |
10155 FW_ACL_VLAN_CMD_VFN_V(vf));
10156 vlan_cmd.en_to_len16 = cpu_to_be32(enable | FW_LEN16(vlan_cmd));
10157 /* Drop all packets that donot match vlan id */
10158 vlan_cmd.dropnovlan_fm = FW_ACL_VLAN_CMD_FM_F;
10160 vlan_cmd.nvlan = 1;
10161 vlan_cmd.vlanid[0] = cpu_to_be16(vlan);
10164 return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL);
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