2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37 #include <linux/bitmap.h>
38 #include <linux/crc32.h>
39 #include <linux/ctype.h>
40 #include <linux/debugfs.h>
41 #include <linux/err.h>
42 #include <linux/etherdevice.h>
43 #include <linux/firmware.h>
45 #include <linux/if_vlan.h>
46 #include <linux/init.h>
47 #include <linux/log2.h>
48 #include <linux/mdio.h>
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/mutex.h>
52 #include <linux/netdevice.h>
53 #include <linux/pci.h>
54 #include <linux/aer.h>
55 #include <linux/rtnetlink.h>
56 #include <linux/sched.h>
57 #include <linux/seq_file.h>
58 #include <linux/sockios.h>
59 #include <linux/vmalloc.h>
60 #include <linux/workqueue.h>
61 #include <net/neighbour.h>
62 #include <net/netevent.h>
63 #include <net/addrconf.h>
64 #include <net/bonding.h>
65 #include <net/addrconf.h>
66 #include <asm/uaccess.h>
70 #include "t4_values.h"
73 #include "t4fw_version.h"
74 #include "cxgb4_dcb.h"
75 #include "cxgb4_debugfs.h"
79 char cxgb4_driver_name[] = KBUILD_MODNAME;
84 #define DRV_VERSION "2.0.0-ko"
85 const char cxgb4_driver_version[] = DRV_VERSION;
86 #define DRV_DESC "Chelsio T4/T5 Network Driver"
88 /* Host shadow copy of ingress filter entry. This is in host native format
89 * and doesn't match the ordering or bit order, etc. of the hardware of the
90 * firmware command. The use of bit-field structure elements is purely to
91 * remind ourselves of the field size limitations and save memory in the case
92 * where the filter table is large.
95 /* Administrative fields for filter.
97 u32 valid:1; /* filter allocated and valid */
98 u32 locked:1; /* filter is administratively locked */
100 u32 pending:1; /* filter action is pending firmware reply */
101 u32 smtidx:8; /* Source MAC Table index for smac */
102 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
104 /* The filter itself. Most of this is a straight copy of information
105 * provided by the extended ioctl(). Some fields are translated to
106 * internal forms -- for instance the Ingress Queue ID passed in from
107 * the ioctl() is translated into the Absolute Ingress Queue ID.
109 struct ch_filter_specification fs;
112 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
113 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
114 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
116 /* Macros needed to support the PCI Device ID Table ...
118 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
119 static const struct pci_device_id cxgb4_pci_tbl[] = {
120 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
122 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
125 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0
127 #define CH_PCI_ID_TABLE_ENTRY(devid) \
128 {PCI_VDEVICE(CHELSIO, (devid)), 4}
130 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
134 #include "t4_pci_id_tbl.h"
136 #define FW4_FNAME "cxgb4/t4fw.bin"
137 #define FW5_FNAME "cxgb4/t5fw.bin"
138 #define FW4_CFNAME "cxgb4/t4-config.txt"
139 #define FW5_CFNAME "cxgb4/t5-config.txt"
140 #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
141 #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
142 #define PHY_AQ1202_DEVICEID 0x4409
143 #define PHY_BCM84834_DEVICEID 0x4486
145 MODULE_DESCRIPTION(DRV_DESC);
146 MODULE_AUTHOR("Chelsio Communications");
147 MODULE_LICENSE("Dual BSD/GPL");
148 MODULE_VERSION(DRV_VERSION);
149 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
150 MODULE_FIRMWARE(FW4_FNAME);
151 MODULE_FIRMWARE(FW5_FNAME);
154 * Normally we're willing to become the firmware's Master PF but will be happy
155 * if another PF has already become the Master and initialized the adapter.
156 * Setting "force_init" will cause this driver to forcibly establish itself as
157 * the Master PF and initialize the adapter.
159 static uint force_init;
161 module_param(force_init, uint, 0644);
162 MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter");
165 * Normally if the firmware we connect to has Configuration File support, we
166 * use that and only fall back to the old Driver-based initialization if the
167 * Configuration File fails for some reason. If force_old_init is set, then
168 * we'll always use the old Driver-based initialization sequence.
170 static uint force_old_init;
172 module_param(force_old_init, uint, 0644);
173 MODULE_PARM_DESC(force_old_init, "Force old initialization sequence, deprecated"
176 static int dflt_msg_enable = DFLT_MSG_ENABLE;
178 module_param(dflt_msg_enable, int, 0644);
179 MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
182 * The driver uses the best interrupt scheme available on a platform in the
183 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
184 * of these schemes the driver may consider as follows:
186 * msi = 2: choose from among all three options
187 * msi = 1: only consider MSI and INTx interrupts
188 * msi = 0: force INTx interrupts
192 module_param(msi, int, 0644);
193 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
196 * Queue interrupt hold-off timer values. Queues default to the first of these
199 static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 };
201 module_param_array(intr_holdoff, uint, NULL, 0644);
202 MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers "
203 "0..4 in microseconds, deprecated parameter");
205 static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 };
207 module_param_array(intr_cnt, uint, NULL, 0644);
208 MODULE_PARM_DESC(intr_cnt,
209 "thresholds 1..3 for queue interrupt packet counters, "
210 "deprecated parameter");
213 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
214 * offset by 2 bytes in order to have the IP headers line up on 4-byte
215 * boundaries. This is a requirement for many architectures which will throw
216 * a machine check fault if an attempt is made to access one of the 4-byte IP
217 * header fields on a non-4-byte boundary. And it's a major performance issue
218 * even on some architectures which allow it like some implementations of the
219 * x86 ISA. However, some architectures don't mind this and for some very
220 * edge-case performance sensitive applications (like forwarding large volumes
221 * of small packets), setting this DMA offset to 0 will decrease the number of
222 * PCI-E Bus transfers enough to measurably affect performance.
224 static int rx_dma_offset = 2;
228 #ifdef CONFIG_PCI_IOV
229 module_param(vf_acls, bool, 0644);
230 MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement, "
231 "deprecated parameter");
233 /* Configure the number of PCI-E Virtual Function which are to be instantiated
234 * on SR-IOV Capable Physical Functions.
236 static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV];
238 module_param_array(num_vf, uint, NULL, 0644);
239 MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
242 /* TX Queue select used to determine what algorithm to use for selecting TX
243 * queue. Select between the kernel provided function (select_queue=0) or user
244 * cxgb_select_queue function (select_queue=1)
246 * Default: select_queue=0
248 static int select_queue;
249 module_param(select_queue, int, 0644);
250 MODULE_PARM_DESC(select_queue,
251 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
253 static unsigned int tp_vlan_pri_map = HW_TPL_FR_MT_PR_IV_P_FC;
255 module_param(tp_vlan_pri_map, uint, 0644);
256 MODULE_PARM_DESC(tp_vlan_pri_map, "global compressed filter configuration, "
257 "deprecated parameter");
259 static struct dentry *cxgb4_debugfs_root;
261 static LIST_HEAD(adapter_list);
262 static DEFINE_MUTEX(uld_mutex);
263 /* Adapter list to be accessed from atomic context */
264 static LIST_HEAD(adap_rcu_list);
265 static DEFINE_SPINLOCK(adap_rcu_lock);
266 static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
267 static const char *uld_str[] = { "RDMA", "iSCSI" };
269 static void link_report(struct net_device *dev)
271 if (!netif_carrier_ok(dev))
272 netdev_info(dev, "link down\n");
274 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
276 const char *s = "10Mbps";
277 const struct port_info *p = netdev_priv(dev);
279 switch (p->link_cfg.speed) {
294 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
299 #ifdef CONFIG_CHELSIO_T4_DCB
300 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
301 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
303 struct port_info *pi = netdev_priv(dev);
304 struct adapter *adap = pi->adapter;
305 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
308 /* We use a simple mapping of Port TX Queue Index to DCB
309 * Priority when we're enabling DCB.
311 for (i = 0; i < pi->nqsets; i++, txq++) {
315 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
317 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
318 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
319 value = enable ? i : 0xffffffff;
321 /* Since we can be called while atomic (from "interrupt
322 * level") we need to issue the Set Parameters Commannd
323 * without sleeping (timeout < 0).
325 err = t4_set_params_timeout(adap, adap->mbox, adap->fn, 0, 1,
327 -FW_CMD_MAX_TIMEOUT);
330 dev_err(adap->pdev_dev,
331 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
332 enable ? "set" : "unset", pi->port_id, i, -err);
334 txq->dcb_prio = value;
337 #endif /* CONFIG_CHELSIO_T4_DCB */
339 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
341 struct net_device *dev = adapter->port[port_id];
343 /* Skip changes from disabled ports. */
344 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
346 netif_carrier_on(dev);
348 #ifdef CONFIG_CHELSIO_T4_DCB
349 cxgb4_dcb_state_init(dev);
350 dcb_tx_queue_prio_enable(dev, false);
351 #endif /* CONFIG_CHELSIO_T4_DCB */
352 netif_carrier_off(dev);
359 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
361 static const char *mod_str[] = {
362 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
365 const struct net_device *dev = adap->port[port_id];
366 const struct port_info *pi = netdev_priv(dev);
368 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
369 netdev_info(dev, "port module unplugged\n");
370 else if (pi->mod_type < ARRAY_SIZE(mod_str))
371 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
375 * Configure the exact and hash address filters to handle a port's multicast
376 * and secondary unicast MAC addresses.
378 static int set_addr_filters(const struct net_device *dev, bool sleep)
386 const struct netdev_hw_addr *ha;
387 int uc_cnt = netdev_uc_count(dev);
388 int mc_cnt = netdev_mc_count(dev);
389 const struct port_info *pi = netdev_priv(dev);
390 unsigned int mb = pi->adapter->fn;
392 /* first do the secondary unicast addresses */
393 netdev_for_each_uc_addr(ha, dev) {
394 addr[naddr++] = ha->addr;
395 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
396 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
397 naddr, addr, filt_idx, &uhash, sleep);
406 /* next set up the multicast addresses */
407 netdev_for_each_mc_addr(ha, dev) {
408 addr[naddr++] = ha->addr;
409 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
410 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
411 naddr, addr, filt_idx, &mhash, sleep);
420 return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0,
421 uhash | mhash, sleep);
424 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
425 module_param(dbfifo_int_thresh, int, 0644);
426 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
429 * usecs to sleep while draining the dbfifo
431 static int dbfifo_drain_delay = 1000;
432 module_param(dbfifo_drain_delay, int, 0644);
433 MODULE_PARM_DESC(dbfifo_drain_delay,
434 "usecs to sleep while draining the dbfifo");
437 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
438 * If @mtu is -1 it is left unchanged.
440 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
443 struct port_info *pi = netdev_priv(dev);
445 ret = set_addr_filters(dev, sleep_ok);
447 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, mtu,
448 (dev->flags & IFF_PROMISC) ? 1 : 0,
449 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
455 * link_start - enable a port
456 * @dev: the port to enable
458 * Performs the MAC and PHY actions needed to enable a port.
460 static int link_start(struct net_device *dev)
463 struct port_info *pi = netdev_priv(dev);
464 unsigned int mb = pi->adapter->fn;
467 * We do not set address filters and promiscuity here, the stack does
468 * that step explicitly.
470 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
471 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
473 ret = t4_change_mac(pi->adapter, mb, pi->viid,
474 pi->xact_addr_filt, dev->dev_addr, true,
477 pi->xact_addr_filt = ret;
482 ret = t4_link_start(pi->adapter, mb, pi->tx_chan,
486 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
487 true, CXGB4_DCB_ENABLED);
494 int cxgb4_dcb_enabled(const struct net_device *dev)
496 #ifdef CONFIG_CHELSIO_T4_DCB
497 struct port_info *pi = netdev_priv(dev);
499 if (!pi->dcb.enabled)
502 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
503 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
508 EXPORT_SYMBOL(cxgb4_dcb_enabled);
510 #ifdef CONFIG_CHELSIO_T4_DCB
511 /* Handle a Data Center Bridging update message from the firmware. */
512 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
514 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
515 struct net_device *dev = adap->port[port];
516 int old_dcb_enabled = cxgb4_dcb_enabled(dev);
519 cxgb4_dcb_handle_fw_update(adap, pcmd);
520 new_dcb_enabled = cxgb4_dcb_enabled(dev);
522 /* If the DCB has become enabled or disabled on the port then we're
523 * going to need to set up/tear down DCB Priority parameters for the
524 * TX Queues associated with the port.
526 if (new_dcb_enabled != old_dcb_enabled)
527 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
529 #endif /* CONFIG_CHELSIO_T4_DCB */
531 /* Clear a filter and release any of its resources that we own. This also
532 * clears the filter's "pending" status.
534 static void clear_filter(struct adapter *adap, struct filter_entry *f)
536 /* If the new or old filter have loopback rewriteing rules then we'll
537 * need to free any existing Layer Two Table (L2T) entries of the old
538 * filter rule. The firmware will handle freeing up any Source MAC
539 * Table (SMT) entries used for rewriting Source MAC Addresses in
543 cxgb4_l2t_release(f->l2t);
545 /* The zeroing of the filter rule below clears the filter valid,
546 * pending, locked flags, l2t pointer, etc. so it's all we need for
549 memset(f, 0, sizeof(*f));
552 /* Handle a filter write/deletion reply.
554 static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
556 unsigned int idx = GET_TID(rpl);
557 unsigned int nidx = idx - adap->tids.ftid_base;
559 struct filter_entry *f;
561 if (idx >= adap->tids.ftid_base && nidx <
562 (adap->tids.nftids + adap->tids.nsftids)) {
564 ret = TCB_COOKIE_G(rpl->cookie);
565 f = &adap->tids.ftid_tab[idx];
567 if (ret == FW_FILTER_WR_FLT_DELETED) {
568 /* Clear the filter when we get confirmation from the
569 * hardware that the filter has been deleted.
571 clear_filter(adap, f);
572 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) {
573 dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n",
575 clear_filter(adap, f);
576 } else if (ret == FW_FILTER_WR_FLT_ADDED) {
577 f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff;
578 f->pending = 0; /* asynchronous setup completed */
581 /* Something went wrong. Issue a warning about the
582 * problem and clear everything out.
584 dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n",
586 clear_filter(adap, f);
591 /* Response queue handler for the FW event queue.
593 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
594 const struct pkt_gl *gl)
596 u8 opcode = ((const struct rss_header *)rsp)->opcode;
598 rsp++; /* skip RSS header */
600 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
602 if (unlikely(opcode == CPL_FW4_MSG &&
603 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
605 opcode = ((const struct rss_header *)rsp)->opcode;
607 if (opcode != CPL_SGE_EGR_UPDATE) {
608 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
614 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
615 const struct cpl_sge_egr_update *p = (void *)rsp;
616 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
619 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
621 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
622 struct sge_eth_txq *eq;
624 eq = container_of(txq, struct sge_eth_txq, q);
625 netif_tx_wake_queue(eq->txq);
627 struct sge_ofld_txq *oq;
629 oq = container_of(txq, struct sge_ofld_txq, q);
630 tasklet_schedule(&oq->qresume_tsk);
632 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
633 const struct cpl_fw6_msg *p = (void *)rsp;
635 #ifdef CONFIG_CHELSIO_T4_DCB
636 const struct fw_port_cmd *pcmd = (const void *)p->data;
637 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
638 unsigned int action =
639 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
641 if (cmd == FW_PORT_CMD &&
642 action == FW_PORT_ACTION_GET_PORT_INFO) {
643 int port = FW_PORT_CMD_PORTID_G(
644 be32_to_cpu(pcmd->op_to_portid));
645 struct net_device *dev = q->adap->port[port];
646 int state_input = ((pcmd->u.info.dcbxdis_pkd &
647 FW_PORT_CMD_DCBXDIS_F)
648 ? CXGB4_DCB_INPUT_FW_DISABLED
649 : CXGB4_DCB_INPUT_FW_ENABLED);
651 cxgb4_dcb_state_fsm(dev, state_input);
654 if (cmd == FW_PORT_CMD &&
655 action == FW_PORT_ACTION_L2_DCB_CFG)
656 dcb_rpl(q->adap, pcmd);
660 t4_handle_fw_rpl(q->adap, p->data);
661 } else if (opcode == CPL_L2T_WRITE_RPL) {
662 const struct cpl_l2t_write_rpl *p = (void *)rsp;
664 do_l2t_write_rpl(q->adap, p);
665 } else if (opcode == CPL_SET_TCB_RPL) {
666 const struct cpl_set_tcb_rpl *p = (void *)rsp;
668 filter_rpl(q->adap, p);
670 dev_err(q->adap->pdev_dev,
671 "unexpected CPL %#x on FW event queue\n", opcode);
677 * uldrx_handler - response queue handler for ULD queues
678 * @q: the response queue that received the packet
679 * @rsp: the response queue descriptor holding the offload message
680 * @gl: the gather list of packet fragments
682 * Deliver an ingress offload packet to a ULD. All processing is done by
683 * the ULD, we just maintain statistics.
685 static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
686 const struct pkt_gl *gl)
688 struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
690 /* FW can send CPLs encapsulated in a CPL_FW4_MSG.
692 if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
693 ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
696 if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) {
702 else if (gl == CXGB4_MSG_AN)
709 static void disable_msi(struct adapter *adapter)
711 if (adapter->flags & USING_MSIX) {
712 pci_disable_msix(adapter->pdev);
713 adapter->flags &= ~USING_MSIX;
714 } else if (adapter->flags & USING_MSI) {
715 pci_disable_msi(adapter->pdev);
716 adapter->flags &= ~USING_MSI;
721 * Interrupt handler for non-data events used with MSI-X.
723 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
725 struct adapter *adap = cookie;
726 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
730 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
732 if (adap->flags & MASTER_PF)
733 t4_slow_intr_handler(adap);
738 * Name the MSI-X interrupts.
740 static void name_msix_vecs(struct adapter *adap)
742 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
744 /* non-data interrupts */
745 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
748 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
749 adap->port[0]->name);
751 /* Ethernet queues */
752 for_each_port(adap, j) {
753 struct net_device *d = adap->port[j];
754 const struct port_info *pi = netdev_priv(d);
756 for (i = 0; i < pi->nqsets; i++, msi_idx++)
757 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
762 for_each_ofldrxq(&adap->sge, i)
763 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d",
764 adap->port[0]->name, i);
766 for_each_rdmarxq(&adap->sge, i)
767 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
768 adap->port[0]->name, i);
770 for_each_rdmaciq(&adap->sge, i)
771 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d",
772 adap->port[0]->name, i);
775 static int request_msix_queue_irqs(struct adapter *adap)
777 struct sge *s = &adap->sge;
778 int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0;
781 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
782 adap->msix_info[1].desc, &s->fw_evtq);
786 for_each_ethrxq(s, ethqidx) {
787 err = request_irq(adap->msix_info[msi_index].vec,
789 adap->msix_info[msi_index].desc,
790 &s->ethrxq[ethqidx].rspq);
795 for_each_ofldrxq(s, ofldqidx) {
796 err = request_irq(adap->msix_info[msi_index].vec,
798 adap->msix_info[msi_index].desc,
799 &s->ofldrxq[ofldqidx].rspq);
804 for_each_rdmarxq(s, rdmaqidx) {
805 err = request_irq(adap->msix_info[msi_index].vec,
807 adap->msix_info[msi_index].desc,
808 &s->rdmarxq[rdmaqidx].rspq);
813 for_each_rdmaciq(s, rdmaciqqidx) {
814 err = request_irq(adap->msix_info[msi_index].vec,
816 adap->msix_info[msi_index].desc,
817 &s->rdmaciq[rdmaciqqidx].rspq);
825 while (--rdmaciqqidx >= 0)
826 free_irq(adap->msix_info[--msi_index].vec,
827 &s->rdmaciq[rdmaciqqidx].rspq);
828 while (--rdmaqidx >= 0)
829 free_irq(adap->msix_info[--msi_index].vec,
830 &s->rdmarxq[rdmaqidx].rspq);
831 while (--ofldqidx >= 0)
832 free_irq(adap->msix_info[--msi_index].vec,
833 &s->ofldrxq[ofldqidx].rspq);
834 while (--ethqidx >= 0)
835 free_irq(adap->msix_info[--msi_index].vec,
836 &s->ethrxq[ethqidx].rspq);
837 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
841 static void free_msix_queue_irqs(struct adapter *adap)
843 int i, msi_index = 2;
844 struct sge *s = &adap->sge;
846 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
847 for_each_ethrxq(s, i)
848 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
849 for_each_ofldrxq(s, i)
850 free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq);
851 for_each_rdmarxq(s, i)
852 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
853 for_each_rdmaciq(s, i)
854 free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq);
858 * cxgb4_write_rss - write the RSS table for a given port
860 * @queues: array of queue indices for RSS
862 * Sets up the portion of the HW RSS table for the port's VI to distribute
863 * packets to the Rx queues in @queues.
864 * Should never be called before setting up sge eth rx queues
866 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
870 struct adapter *adapter = pi->adapter;
871 const struct sge_eth_rxq *rxq;
873 rxq = &adapter->sge.ethrxq[pi->first_qset];
874 rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
878 /* map the queue indices to queue ids */
879 for (i = 0; i < pi->rss_size; i++, queues++)
880 rss[i] = rxq[*queues].rspq.abs_id;
882 err = t4_config_rss_range(adapter, adapter->fn, pi->viid, 0,
883 pi->rss_size, rss, pi->rss_size);
884 /* If Tunnel All Lookup isn't specified in the global RSS
885 * Configuration, then we need to specify a default Ingress
886 * Queue for any ingress packets which aren't hashed. We'll
887 * use our first ingress queue ...
890 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
891 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
892 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
893 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
894 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
895 FW_RSS_VI_CONFIG_CMD_UDPEN_F,
902 * setup_rss - configure RSS
905 * Sets up RSS for each port.
907 static int setup_rss(struct adapter *adap)
911 for_each_port(adap, i) {
912 const struct port_info *pi = adap2pinfo(adap, i);
914 /* Fill default values with equal distribution */
915 for (j = 0; j < pi->rss_size; j++)
916 pi->rss[j] = j % pi->nqsets;
918 err = cxgb4_write_rss(pi, pi->rss);
926 * Return the channel of the ingress queue with the given qid.
928 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
930 qid -= p->ingr_start;
931 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
935 * Wait until all NAPI handlers are descheduled.
937 static void quiesce_rx(struct adapter *adap)
941 for (i = 0; i < adap->sge.ingr_sz; i++) {
942 struct sge_rspq *q = adap->sge.ingr_map[i];
944 if (q && q->handler) {
945 napi_disable(&q->napi);
947 while (!cxgb_poll_lock_napi(q))
955 /* Disable interrupt and napi handler */
956 static void disable_interrupts(struct adapter *adap)
958 if (adap->flags & FULL_INIT_DONE) {
959 t4_intr_disable(adap);
960 if (adap->flags & USING_MSIX) {
961 free_msix_queue_irqs(adap);
962 free_irq(adap->msix_info[0].vec, adap);
964 free_irq(adap->pdev->irq, adap);
971 * Enable NAPI scheduling and interrupt generation for all Rx queues.
973 static void enable_rx(struct adapter *adap)
977 for (i = 0; i < adap->sge.ingr_sz; i++) {
978 struct sge_rspq *q = adap->sge.ingr_map[i];
983 cxgb_busy_poll_init_lock(q);
984 napi_enable(&q->napi);
986 /* 0-increment GTS to start the timer and enable interrupts */
987 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
988 SEINTARM_V(q->intr_params) |
989 INGRESSQID_V(q->cntxt_id));
993 static int alloc_ofld_rxqs(struct adapter *adap, struct sge_ofld_rxq *q,
994 unsigned int nq, unsigned int per_chan, int msi_idx,
999 for (i = 0; i < nq; i++, q++) {
1002 err = t4_sge_alloc_rxq(adap, &q->rspq, false,
1003 adap->port[i / per_chan],
1004 msi_idx, q->fl.size ? &q->fl : NULL,
1008 memset(&q->stats, 0, sizeof(q->stats));
1010 ids[i] = q->rspq.abs_id;
1016 * setup_sge_queues - configure SGE Tx/Rx/response queues
1017 * @adap: the adapter
1019 * Determines how many sets of SGE queues to use and initializes them.
1020 * We support multiple queue sets per port if we have MSI-X, otherwise
1021 * just one queue set per port.
1023 static int setup_sge_queues(struct adapter *adap)
1025 int err, msi_idx, i, j;
1026 struct sge *s = &adap->sge;
1028 bitmap_zero(s->starving_fl, s->egr_sz);
1029 bitmap_zero(s->txq_maperr, s->egr_sz);
1031 if (adap->flags & USING_MSIX)
1032 msi_idx = 1; /* vector 0 is for non-queue interrupts */
1034 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
1038 msi_idx = -((int)s->intrq.abs_id + 1);
1041 /* NOTE: If you add/delete any Ingress/Egress Queue allocations in here,
1042 * don't forget to update the following which need to be
1043 * synchronized to and changes here.
1045 * 1. The calculations of MAX_INGQ in cxgb4.h.
1047 * 2. Update enable_msix/name_msix_vecs/request_msix_queue_irqs
1048 * to accommodate any new/deleted Ingress Queues
1049 * which need MSI-X Vectors.
1051 * 3. Update sge_qinfo_show() to include information on the
1052 * new/deleted queues.
1054 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
1055 msi_idx, NULL, fwevtq_handler, -1);
1057 freeout: t4_free_sge_resources(adap);
1061 for_each_port(adap, i) {
1062 struct net_device *dev = adap->port[i];
1063 struct port_info *pi = netdev_priv(dev);
1064 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1065 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1067 for (j = 0; j < pi->nqsets; j++, q++) {
1070 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1073 t4_get_mps_bg_map(adap,
1078 memset(&q->stats, 0, sizeof(q->stats));
1080 for (j = 0; j < pi->nqsets; j++, t++) {
1081 err = t4_sge_alloc_eth_txq(adap, t, dev,
1082 netdev_get_tx_queue(dev, j),
1083 s->fw_evtq.cntxt_id);
1089 j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */
1090 for_each_ofldrxq(s, i) {
1091 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i],
1093 s->fw_evtq.cntxt_id);
1098 #define ALLOC_OFLD_RXQS(firstq, nq, per_chan, ids) do { \
1099 err = alloc_ofld_rxqs(adap, firstq, nq, per_chan, msi_idx, ids); \
1106 ALLOC_OFLD_RXQS(s->ofldrxq, s->ofldqsets, j, s->ofld_rxq);
1107 ALLOC_OFLD_RXQS(s->rdmarxq, s->rdmaqs, 1, s->rdma_rxq);
1108 j = s->rdmaciqs / adap->params.nports; /* rdmaq queues per channel */
1109 ALLOC_OFLD_RXQS(s->rdmaciq, s->rdmaciqs, j, s->rdma_ciq);
1111 #undef ALLOC_OFLD_RXQS
1113 for_each_port(adap, i) {
1115 * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
1116 * have RDMA queues, and that's the right value.
1118 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1119 s->fw_evtq.cntxt_id,
1120 s->rdmarxq[i].rspq.cntxt_id);
1125 t4_write_reg(adap, is_t4(adap->params.chip) ?
1126 MPS_TRC_RSS_CONTROL_A :
1127 MPS_T5_TRC_RSS_CONTROL_A,
1128 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
1129 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
1134 * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1135 * The allocated memory is cleared.
1137 void *t4_alloc_mem(size_t size)
1139 void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
1147 * Free memory allocated through alloc_mem().
1149 void t4_free_mem(void *addr)
1151 if (is_vmalloc_addr(addr))
1157 /* Send a Work Request to write the filter at a specified index. We construct
1158 * a Firmware Filter Work Request to have the work done and put the indicated
1159 * filter into "pending" mode which will prevent any further actions against
1160 * it till we get a reply from the firmware on the completion status of the
1163 static int set_filter_wr(struct adapter *adapter, int fidx)
1165 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1166 struct sk_buff *skb;
1167 struct fw_filter_wr *fwr;
1170 skb = alloc_skb(sizeof(*fwr), GFP_KERNEL);
1174 /* If the new filter requires loopback Destination MAC and/or VLAN
1175 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1178 if (f->fs.newdmac || f->fs.newvlan) {
1179 /* allocate L2T entry for new filter */
1180 f->l2t = t4_l2t_alloc_switching(adapter->l2t);
1181 if (f->l2t == NULL) {
1185 if (t4_l2t_set_switching(adapter, f->l2t, f->fs.vlan,
1186 f->fs.eport, f->fs.dmac)) {
1187 cxgb4_l2t_release(f->l2t);
1194 ftid = adapter->tids.ftid_base + fidx;
1196 fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr));
1197 memset(fwr, 0, sizeof(*fwr));
1199 /* It would be nice to put most of the following in t4_hw.c but most
1200 * of the work is translating the cxgbtool ch_filter_specification
1201 * into the Work Request and the definition of that structure is
1202 * currently in cxgbtool.h which isn't appropriate to pull into the
1203 * common code. We may eventually try to come up with a more neutral
1204 * filter specification structure but for now it's easiest to simply
1205 * put this fairly direct code in line ...
1207 fwr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR));
1208 fwr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*fwr)/16));
1210 htonl(FW_FILTER_WR_TID_V(ftid) |
1211 FW_FILTER_WR_RQTYPE_V(f->fs.type) |
1212 FW_FILTER_WR_NOREPLY_V(0) |
1213 FW_FILTER_WR_IQ_V(f->fs.iq));
1214 fwr->del_filter_to_l2tix =
1215 htonl(FW_FILTER_WR_RPTTID_V(f->fs.rpttid) |
1216 FW_FILTER_WR_DROP_V(f->fs.action == FILTER_DROP) |
1217 FW_FILTER_WR_DIRSTEER_V(f->fs.dirsteer) |
1218 FW_FILTER_WR_MASKHASH_V(f->fs.maskhash) |
1219 FW_FILTER_WR_DIRSTEERHASH_V(f->fs.dirsteerhash) |
1220 FW_FILTER_WR_LPBK_V(f->fs.action == FILTER_SWITCH) |
1221 FW_FILTER_WR_DMAC_V(f->fs.newdmac) |
1222 FW_FILTER_WR_SMAC_V(f->fs.newsmac) |
1223 FW_FILTER_WR_INSVLAN_V(f->fs.newvlan == VLAN_INSERT ||
1224 f->fs.newvlan == VLAN_REWRITE) |
1225 FW_FILTER_WR_RMVLAN_V(f->fs.newvlan == VLAN_REMOVE ||
1226 f->fs.newvlan == VLAN_REWRITE) |
1227 FW_FILTER_WR_HITCNTS_V(f->fs.hitcnts) |
1228 FW_FILTER_WR_TXCHAN_V(f->fs.eport) |
1229 FW_FILTER_WR_PRIO_V(f->fs.prio) |
1230 FW_FILTER_WR_L2TIX_V(f->l2t ? f->l2t->idx : 0));
1231 fwr->ethtype = htons(f->fs.val.ethtype);
1232 fwr->ethtypem = htons(f->fs.mask.ethtype);
1233 fwr->frag_to_ovlan_vldm =
1234 (FW_FILTER_WR_FRAG_V(f->fs.val.frag) |
1235 FW_FILTER_WR_FRAGM_V(f->fs.mask.frag) |
1236 FW_FILTER_WR_IVLAN_VLD_V(f->fs.val.ivlan_vld) |
1237 FW_FILTER_WR_OVLAN_VLD_V(f->fs.val.ovlan_vld) |
1238 FW_FILTER_WR_IVLAN_VLDM_V(f->fs.mask.ivlan_vld) |
1239 FW_FILTER_WR_OVLAN_VLDM_V(f->fs.mask.ovlan_vld));
1241 fwr->rx_chan_rx_rpl_iq =
1242 htons(FW_FILTER_WR_RX_CHAN_V(0) |
1243 FW_FILTER_WR_RX_RPL_IQ_V(adapter->sge.fw_evtq.abs_id));
1244 fwr->maci_to_matchtypem =
1245 htonl(FW_FILTER_WR_MACI_V(f->fs.val.macidx) |
1246 FW_FILTER_WR_MACIM_V(f->fs.mask.macidx) |
1247 FW_FILTER_WR_FCOE_V(f->fs.val.fcoe) |
1248 FW_FILTER_WR_FCOEM_V(f->fs.mask.fcoe) |
1249 FW_FILTER_WR_PORT_V(f->fs.val.iport) |
1250 FW_FILTER_WR_PORTM_V(f->fs.mask.iport) |
1251 FW_FILTER_WR_MATCHTYPE_V(f->fs.val.matchtype) |
1252 FW_FILTER_WR_MATCHTYPEM_V(f->fs.mask.matchtype));
1253 fwr->ptcl = f->fs.val.proto;
1254 fwr->ptclm = f->fs.mask.proto;
1255 fwr->ttyp = f->fs.val.tos;
1256 fwr->ttypm = f->fs.mask.tos;
1257 fwr->ivlan = htons(f->fs.val.ivlan);
1258 fwr->ivlanm = htons(f->fs.mask.ivlan);
1259 fwr->ovlan = htons(f->fs.val.ovlan);
1260 fwr->ovlanm = htons(f->fs.mask.ovlan);
1261 memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
1262 memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
1263 memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
1264 memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
1265 fwr->lp = htons(f->fs.val.lport);
1266 fwr->lpm = htons(f->fs.mask.lport);
1267 fwr->fp = htons(f->fs.val.fport);
1268 fwr->fpm = htons(f->fs.mask.fport);
1270 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma));
1272 /* Mark the filter as "pending" and ship off the Filter Work Request.
1273 * When we get the Work Request Reply we'll clear the pending status.
1276 set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3);
1277 t4_ofld_send(adapter, skb);
1281 /* Delete the filter at a specified index.
1283 static int del_filter_wr(struct adapter *adapter, int fidx)
1285 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1286 struct sk_buff *skb;
1287 struct fw_filter_wr *fwr;
1288 unsigned int len, ftid;
1291 ftid = adapter->tids.ftid_base + fidx;
1293 skb = alloc_skb(len, GFP_KERNEL);
1297 fwr = (struct fw_filter_wr *)__skb_put(skb, len);
1298 t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id);
1300 /* Mark the filter as "pending" and ship off the Filter Work Request.
1301 * When we get the Work Request Reply we'll clear the pending status.
1304 t4_mgmt_tx(adapter, skb);
1308 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1309 void *accel_priv, select_queue_fallback_t fallback)
1313 #ifdef CONFIG_CHELSIO_T4_DCB
1314 /* If a Data Center Bridging has been successfully negotiated on this
1315 * link then we'll use the skb's priority to map it to a TX Queue.
1316 * The skb's priority is determined via the VLAN Tag Priority Code
1319 if (cxgb4_dcb_enabled(dev)) {
1323 err = vlan_get_tag(skb, &vlan_tci);
1324 if (unlikely(err)) {
1325 if (net_ratelimit())
1327 "TX Packet without VLAN Tag on DCB Link\n");
1330 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1331 #ifdef CONFIG_CHELSIO_T4_FCOE
1332 if (skb->protocol == htons(ETH_P_FCOE))
1333 txq = skb->priority & 0x7;
1334 #endif /* CONFIG_CHELSIO_T4_FCOE */
1338 #endif /* CONFIG_CHELSIO_T4_DCB */
1341 txq = (skb_rx_queue_recorded(skb)
1342 ? skb_get_rx_queue(skb)
1343 : smp_processor_id());
1345 while (unlikely(txq >= dev->real_num_tx_queues))
1346 txq -= dev->real_num_tx_queues;
1351 return fallback(dev, skb) % dev->real_num_tx_queues;
1354 static inline int is_offload(const struct adapter *adap)
1356 return adap->params.offload;
1359 static int closest_timer(const struct sge *s, int time)
1361 int i, delta, match = 0, min_delta = INT_MAX;
1363 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1364 delta = time - s->timer_val[i];
1367 if (delta < min_delta) {
1375 static int closest_thres(const struct sge *s, int thres)
1377 int i, delta, match = 0, min_delta = INT_MAX;
1379 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1380 delta = thres - s->counter_val[i];
1383 if (delta < min_delta) {
1392 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
1394 * @us: the hold-off time in us, or 0 to disable timer
1395 * @cnt: the hold-off packet count, or 0 to disable counter
1397 * Sets an Rx queue's interrupt hold-off time and packet count. At least
1398 * one of the two needs to be enabled for the queue to generate interrupts.
1400 int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
1401 unsigned int us, unsigned int cnt)
1403 struct adapter *adap = q->adap;
1405 if ((us | cnt) == 0)
1412 new_idx = closest_thres(&adap->sge, cnt);
1413 if (q->desc && q->pktcnt_idx != new_idx) {
1414 /* the queue has already been created, update it */
1415 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1416 FW_PARAMS_PARAM_X_V(
1417 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1418 FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
1419 err = t4_set_params(adap, adap->fn, adap->fn, 0, 1, &v,
1424 q->pktcnt_idx = new_idx;
1427 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1428 q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
1432 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
1434 const struct port_info *pi = netdev_priv(dev);
1435 netdev_features_t changed = dev->features ^ features;
1438 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
1441 err = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, -1,
1443 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
1445 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
1449 static int setup_debugfs(struct adapter *adap)
1451 if (IS_ERR_OR_NULL(adap->debugfs_root))
1454 #ifdef CONFIG_DEBUG_FS
1455 t4_setup_debugfs(adap);
1461 * upper-layer driver support
1465 * Allocate an active-open TID and set it to the supplied value.
1467 int cxgb4_alloc_atid(struct tid_info *t, void *data)
1471 spin_lock_bh(&t->atid_lock);
1473 union aopen_entry *p = t->afree;
1475 atid = (p - t->atid_tab) + t->atid_base;
1480 spin_unlock_bh(&t->atid_lock);
1483 EXPORT_SYMBOL(cxgb4_alloc_atid);
1486 * Release an active-open TID.
1488 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1490 union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
1492 spin_lock_bh(&t->atid_lock);
1496 spin_unlock_bh(&t->atid_lock);
1498 EXPORT_SYMBOL(cxgb4_free_atid);
1501 * Allocate a server TID and set it to the supplied value.
1503 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1507 spin_lock_bh(&t->stid_lock);
1508 if (family == PF_INET) {
1509 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1510 if (stid < t->nstids)
1511 __set_bit(stid, t->stid_bmap);
1515 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2);
1520 t->stid_tab[stid].data = data;
1521 stid += t->stid_base;
1522 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1523 * This is equivalent to 4 TIDs. With CLIP enabled it
1526 if (family == PF_INET)
1529 t->stids_in_use += 4;
1531 spin_unlock_bh(&t->stid_lock);
1534 EXPORT_SYMBOL(cxgb4_alloc_stid);
1536 /* Allocate a server filter TID and set it to the supplied value.
1538 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1542 spin_lock_bh(&t->stid_lock);
1543 if (family == PF_INET) {
1544 stid = find_next_zero_bit(t->stid_bmap,
1545 t->nstids + t->nsftids, t->nstids);
1546 if (stid < (t->nstids + t->nsftids))
1547 __set_bit(stid, t->stid_bmap);
1554 t->stid_tab[stid].data = data;
1556 stid += t->sftid_base;
1559 spin_unlock_bh(&t->stid_lock);
1562 EXPORT_SYMBOL(cxgb4_alloc_sftid);
1564 /* Release a server TID.
1566 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1568 /* Is it a server filter TID? */
1569 if (t->nsftids && (stid >= t->sftid_base)) {
1570 stid -= t->sftid_base;
1573 stid -= t->stid_base;
1576 spin_lock_bh(&t->stid_lock);
1577 if (family == PF_INET)
1578 __clear_bit(stid, t->stid_bmap);
1580 bitmap_release_region(t->stid_bmap, stid, 2);
1581 t->stid_tab[stid].data = NULL;
1582 if (family == PF_INET)
1585 t->stids_in_use -= 4;
1586 spin_unlock_bh(&t->stid_lock);
1588 EXPORT_SYMBOL(cxgb4_free_stid);
1591 * Populate a TID_RELEASE WR. Caller must properly size the skb.
1593 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1596 struct cpl_tid_release *req;
1598 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
1599 req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
1600 INIT_TP_WR(req, tid);
1601 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1605 * Queue a TID release request and if necessary schedule a work queue to
1608 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1611 void **p = &t->tid_tab[tid];
1612 struct adapter *adap = container_of(t, struct adapter, tids);
1614 spin_lock_bh(&adap->tid_release_lock);
1615 *p = adap->tid_release_head;
1616 /* Low 2 bits encode the Tx channel number */
1617 adap->tid_release_head = (void **)((uintptr_t)p | chan);
1618 if (!adap->tid_release_task_busy) {
1619 adap->tid_release_task_busy = true;
1620 queue_work(adap->workq, &adap->tid_release_task);
1622 spin_unlock_bh(&adap->tid_release_lock);
1626 * Process the list of pending TID release requests.
1628 static void process_tid_release_list(struct work_struct *work)
1630 struct sk_buff *skb;
1631 struct adapter *adap;
1633 adap = container_of(work, struct adapter, tid_release_task);
1635 spin_lock_bh(&adap->tid_release_lock);
1636 while (adap->tid_release_head) {
1637 void **p = adap->tid_release_head;
1638 unsigned int chan = (uintptr_t)p & 3;
1639 p = (void *)p - chan;
1641 adap->tid_release_head = *p;
1643 spin_unlock_bh(&adap->tid_release_lock);
1645 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1647 schedule_timeout_uninterruptible(1);
1649 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1650 t4_ofld_send(adap, skb);
1651 spin_lock_bh(&adap->tid_release_lock);
1653 adap->tid_release_task_busy = false;
1654 spin_unlock_bh(&adap->tid_release_lock);
1658 * Release a TID and inform HW. If we are unable to allocate the release
1659 * message we defer to a work queue.
1661 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
1664 struct sk_buff *skb;
1665 struct adapter *adap = container_of(t, struct adapter, tids);
1667 old = t->tid_tab[tid];
1668 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1670 t->tid_tab[tid] = NULL;
1671 mk_tid_release(skb, chan, tid);
1672 t4_ofld_send(adap, skb);
1674 cxgb4_queue_tid_release(t, chan, tid);
1676 atomic_dec(&t->tids_in_use);
1678 EXPORT_SYMBOL(cxgb4_remove_tid);
1681 * Allocate and initialize the TID tables. Returns 0 on success.
1683 static int tid_init(struct tid_info *t)
1686 unsigned int stid_bmap_size;
1687 unsigned int natids = t->natids;
1688 struct adapter *adap = container_of(t, struct adapter, tids);
1690 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
1691 size = t->ntids * sizeof(*t->tid_tab) +
1692 natids * sizeof(*t->atid_tab) +
1693 t->nstids * sizeof(*t->stid_tab) +
1694 t->nsftids * sizeof(*t->stid_tab) +
1695 stid_bmap_size * sizeof(long) +
1696 t->nftids * sizeof(*t->ftid_tab) +
1697 t->nsftids * sizeof(*t->ftid_tab);
1699 t->tid_tab = t4_alloc_mem(size);
1703 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1704 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
1705 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
1706 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
1707 spin_lock_init(&t->stid_lock);
1708 spin_lock_init(&t->atid_lock);
1710 t->stids_in_use = 0;
1712 t->atids_in_use = 0;
1713 atomic_set(&t->tids_in_use, 0);
1715 /* Setup the free list for atid_tab and clear the stid bitmap. */
1718 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1719 t->afree = t->atid_tab;
1721 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1722 /* Reserve stid 0 for T4/T5 adapters */
1723 if (!t->stid_base &&
1724 (is_t4(adap->params.chip) || is_t5(adap->params.chip)))
1725 __set_bit(0, t->stid_bmap);
1731 * cxgb4_create_server - create an IP server
1733 * @stid: the server TID
1734 * @sip: local IP address to bind server to
1735 * @sport: the server's TCP port
1736 * @queue: queue to direct messages from this server to
1738 * Create an IP server for the given port and address.
1739 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1741 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
1742 __be32 sip, __be16 sport, __be16 vlan,
1746 struct sk_buff *skb;
1747 struct adapter *adap;
1748 struct cpl_pass_open_req *req;
1751 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1755 adap = netdev2adap(dev);
1756 req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
1758 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1759 req->local_port = sport;
1760 req->peer_port = htons(0);
1761 req->local_ip = sip;
1762 req->peer_ip = htonl(0);
1763 chan = rxq_to_chan(&adap->sge, queue);
1764 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1765 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1766 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1767 ret = t4_mgmt_tx(adap, skb);
1768 return net_xmit_eval(ret);
1770 EXPORT_SYMBOL(cxgb4_create_server);
1772 /* cxgb4_create_server6 - create an IPv6 server
1774 * @stid: the server TID
1775 * @sip: local IPv6 address to bind server to
1776 * @sport: the server's TCP port
1777 * @queue: queue to direct messages from this server to
1779 * Create an IPv6 server for the given port and address.
1780 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1782 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1783 const struct in6_addr *sip, __be16 sport,
1787 struct sk_buff *skb;
1788 struct adapter *adap;
1789 struct cpl_pass_open_req6 *req;
1792 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1796 adap = netdev2adap(dev);
1797 req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
1799 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1800 req->local_port = sport;
1801 req->peer_port = htons(0);
1802 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1803 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1804 req->peer_ip_hi = cpu_to_be64(0);
1805 req->peer_ip_lo = cpu_to_be64(0);
1806 chan = rxq_to_chan(&adap->sge, queue);
1807 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1808 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1809 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1810 ret = t4_mgmt_tx(adap, skb);
1811 return net_xmit_eval(ret);
1813 EXPORT_SYMBOL(cxgb4_create_server6);
1815 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1816 unsigned int queue, bool ipv6)
1818 struct sk_buff *skb;
1819 struct adapter *adap;
1820 struct cpl_close_listsvr_req *req;
1823 adap = netdev2adap(dev);
1825 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1829 req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req));
1831 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
1832 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1833 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
1834 ret = t4_mgmt_tx(adap, skb);
1835 return net_xmit_eval(ret);
1837 EXPORT_SYMBOL(cxgb4_remove_server);
1840 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1841 * @mtus: the HW MTU table
1842 * @mtu: the target MTU
1843 * @idx: index of selected entry in the MTU table
1845 * Returns the index and the value in the HW MTU table that is closest to
1846 * but does not exceed @mtu, unless @mtu is smaller than any value in the
1847 * table, in which case that smallest available value is selected.
1849 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1854 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1860 EXPORT_SYMBOL(cxgb4_best_mtu);
1863 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1864 * @mtus: the HW MTU table
1865 * @header_size: Header Size
1866 * @data_size_max: maximum Data Segment Size
1867 * @data_size_align: desired Data Segment Size Alignment (2^N)
1868 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1870 * Similar to cxgb4_best_mtu() but instead of searching the Hardware
1871 * MTU Table based solely on a Maximum MTU parameter, we break that
1872 * parameter up into a Header Size and Maximum Data Segment Size, and
1873 * provide a desired Data Segment Size Alignment. If we find an MTU in
1874 * the Hardware MTU Table which will result in a Data Segment Size with
1875 * the requested alignment _and_ that MTU isn't "too far" from the
1876 * closest MTU, then we'll return that rather than the closest MTU.
1878 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1879 unsigned short header_size,
1880 unsigned short data_size_max,
1881 unsigned short data_size_align,
1882 unsigned int *mtu_idxp)
1884 unsigned short max_mtu = header_size + data_size_max;
1885 unsigned short data_size_align_mask = data_size_align - 1;
1886 int mtu_idx, aligned_mtu_idx;
1888 /* Scan the MTU Table till we find an MTU which is larger than our
1889 * Maximum MTU or we reach the end of the table. Along the way,
1890 * record the last MTU found, if any, which will result in a Data
1891 * Segment Length matching the requested alignment.
1893 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1894 unsigned short data_size = mtus[mtu_idx] - header_size;
1896 /* If this MTU minus the Header Size would result in a
1897 * Data Segment Size of the desired alignment, remember it.
1899 if ((data_size & data_size_align_mask) == 0)
1900 aligned_mtu_idx = mtu_idx;
1902 /* If we're not at the end of the Hardware MTU Table and the
1903 * next element is larger than our Maximum MTU, drop out of
1906 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1910 /* If we fell out of the loop because we ran to the end of the table,
1911 * then we just have to use the last [largest] entry.
1913 if (mtu_idx == NMTUS)
1916 /* If we found an MTU which resulted in the requested Data Segment
1917 * Length alignment and that's "not far" from the largest MTU which is
1918 * less than or equal to the maximum MTU, then use that.
1920 if (aligned_mtu_idx >= 0 &&
1921 mtu_idx - aligned_mtu_idx <= 1)
1922 mtu_idx = aligned_mtu_idx;
1924 /* If the caller has passed in an MTU Index pointer, pass the
1925 * MTU Index back. Return the MTU value.
1928 *mtu_idxp = mtu_idx;
1929 return mtus[mtu_idx];
1931 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1934 * cxgb4_port_chan - get the HW channel of a port
1935 * @dev: the net device for the port
1937 * Return the HW Tx channel of the given port.
1939 unsigned int cxgb4_port_chan(const struct net_device *dev)
1941 return netdev2pinfo(dev)->tx_chan;
1943 EXPORT_SYMBOL(cxgb4_port_chan);
1945 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1947 struct adapter *adap = netdev2adap(dev);
1948 u32 v1, v2, lp_count, hp_count;
1950 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1951 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1952 if (is_t4(adap->params.chip)) {
1953 lp_count = LP_COUNT_G(v1);
1954 hp_count = HP_COUNT_G(v1);
1956 lp_count = LP_COUNT_T5_G(v1);
1957 hp_count = HP_COUNT_T5_G(v2);
1959 return lpfifo ? lp_count : hp_count;
1961 EXPORT_SYMBOL(cxgb4_dbfifo_count);
1964 * cxgb4_port_viid - get the VI id of a port
1965 * @dev: the net device for the port
1967 * Return the VI id of the given port.
1969 unsigned int cxgb4_port_viid(const struct net_device *dev)
1971 return netdev2pinfo(dev)->viid;
1973 EXPORT_SYMBOL(cxgb4_port_viid);
1976 * cxgb4_port_idx - get the index of a port
1977 * @dev: the net device for the port
1979 * Return the index of the given port.
1981 unsigned int cxgb4_port_idx(const struct net_device *dev)
1983 return netdev2pinfo(dev)->port_id;
1985 EXPORT_SYMBOL(cxgb4_port_idx);
1987 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
1988 struct tp_tcp_stats *v6)
1990 struct adapter *adap = pci_get_drvdata(pdev);
1992 spin_lock(&adap->stats_lock);
1993 t4_tp_get_tcp_stats(adap, v4, v6);
1994 spin_unlock(&adap->stats_lock);
1996 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
1998 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
1999 const unsigned int *pgsz_order)
2001 struct adapter *adap = netdev2adap(dev);
2003 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
2004 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
2005 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
2006 HPZ3_V(pgsz_order[3]));
2008 EXPORT_SYMBOL(cxgb4_iscsi_init);
2010 int cxgb4_flush_eq_cache(struct net_device *dev)
2012 struct adapter *adap = netdev2adap(dev);
2015 ret = t4_fwaddrspace_write(adap, adap->mbox,
2016 0xe1000000 + SGE_CTXT_CMD_A, 0x20000000);
2019 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
2021 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
2023 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
2027 spin_lock(&adap->win0_lock);
2028 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
2029 sizeof(indices), (__be32 *)&indices,
2031 spin_unlock(&adap->win0_lock);
2033 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
2034 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
2039 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
2042 struct adapter *adap = netdev2adap(dev);
2043 u16 hw_pidx, hw_cidx;
2046 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
2050 if (pidx != hw_pidx) {
2054 if (pidx >= hw_pidx)
2055 delta = pidx - hw_pidx;
2057 delta = size - hw_pidx + pidx;
2059 if (is_t4(adap->params.chip))
2060 val = PIDX_V(delta);
2062 val = PIDX_T5_V(delta);
2064 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2070 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
2072 void cxgb4_disable_db_coalescing(struct net_device *dev)
2074 struct adapter *adap;
2076 adap = netdev2adap(dev);
2077 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, NOCOALESCE_F,
2080 EXPORT_SYMBOL(cxgb4_disable_db_coalescing);
2082 void cxgb4_enable_db_coalescing(struct net_device *dev)
2084 struct adapter *adap;
2086 adap = netdev2adap(dev);
2087 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, NOCOALESCE_F, 0);
2089 EXPORT_SYMBOL(cxgb4_enable_db_coalescing);
2091 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
2093 struct adapter *adap;
2094 u32 offset, memtype, memaddr;
2095 u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
2096 u32 edc0_end, edc1_end, mc0_end, mc1_end;
2099 adap = netdev2adap(dev);
2101 offset = ((stag >> 8) * 32) + adap->vres.stag.start;
2103 /* Figure out where the offset lands in the Memory Type/Address scheme.
2104 * This code assumes that the memory is laid out starting at offset 0
2105 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
2106 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have
2107 * MC0, and some have both MC0 and MC1.
2109 size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
2110 edc0_size = EDRAM0_SIZE_G(size) << 20;
2111 size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
2112 edc1_size = EDRAM1_SIZE_G(size) << 20;
2113 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
2114 mc0_size = EXT_MEM0_SIZE_G(size) << 20;
2116 edc0_end = edc0_size;
2117 edc1_end = edc0_end + edc1_size;
2118 mc0_end = edc1_end + mc0_size;
2120 if (offset < edc0_end) {
2123 } else if (offset < edc1_end) {
2125 memaddr = offset - edc0_end;
2127 if (offset < mc0_end) {
2129 memaddr = offset - edc1_end;
2130 } else if (is_t4(adap->params.chip)) {
2131 /* T4 only has a single memory channel */
2134 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
2135 mc1_size = EXT_MEM1_SIZE_G(size) << 20;
2136 mc1_end = mc0_end + mc1_size;
2137 if (offset < mc1_end) {
2139 memaddr = offset - mc0_end;
2141 /* offset beyond the end of any memory */
2147 spin_lock(&adap->win0_lock);
2148 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
2149 spin_unlock(&adap->win0_lock);
2153 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
2157 EXPORT_SYMBOL(cxgb4_read_tpte);
2159 u64 cxgb4_read_sge_timestamp(struct net_device *dev)
2162 struct adapter *adap;
2164 adap = netdev2adap(dev);
2165 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
2166 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
2168 return ((u64)hi << 32) | (u64)lo;
2170 EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
2172 int cxgb4_bar2_sge_qregs(struct net_device *dev,
2174 enum cxgb4_bar2_qtype qtype,
2176 unsigned int *pbar2_qid)
2178 return cxgb4_t4_bar2_sge_qregs(netdev2adap(dev),
2180 (qtype == CXGB4_BAR2_QTYPE_EGRESS
2181 ? T4_BAR2_QTYPE_EGRESS
2182 : T4_BAR2_QTYPE_INGRESS),
2186 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
2188 static struct pci_driver cxgb4_driver;
2190 static void check_neigh_update(struct neighbour *neigh)
2192 const struct device *parent;
2193 const struct net_device *netdev = neigh->dev;
2195 if (netdev->priv_flags & IFF_802_1Q_VLAN)
2196 netdev = vlan_dev_real_dev(netdev);
2197 parent = netdev->dev.parent;
2198 if (parent && parent->driver == &cxgb4_driver.driver)
2199 t4_l2t_update(dev_get_drvdata(parent), neigh);
2202 static int netevent_cb(struct notifier_block *nb, unsigned long event,
2206 case NETEVENT_NEIGH_UPDATE:
2207 check_neigh_update(data);
2209 case NETEVENT_REDIRECT:
2216 static bool netevent_registered;
2217 static struct notifier_block cxgb4_netevent_nb = {
2218 .notifier_call = netevent_cb
2221 static void drain_db_fifo(struct adapter *adap, int usecs)
2223 u32 v1, v2, lp_count, hp_count;
2226 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
2227 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
2228 if (is_t4(adap->params.chip)) {
2229 lp_count = LP_COUNT_G(v1);
2230 hp_count = HP_COUNT_G(v1);
2232 lp_count = LP_COUNT_T5_G(v1);
2233 hp_count = HP_COUNT_T5_G(v2);
2236 if (lp_count == 0 && hp_count == 0)
2238 set_current_state(TASK_UNINTERRUPTIBLE);
2239 schedule_timeout(usecs_to_jiffies(usecs));
2243 static void disable_txq_db(struct sge_txq *q)
2245 unsigned long flags;
2247 spin_lock_irqsave(&q->db_lock, flags);
2249 spin_unlock_irqrestore(&q->db_lock, flags);
2252 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
2254 spin_lock_irq(&q->db_lock);
2255 if (q->db_pidx_inc) {
2256 /* Make sure that all writes to the TX descriptors
2257 * are committed before we tell HW about them.
2260 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2261 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
2265 spin_unlock_irq(&q->db_lock);
2268 static void disable_dbs(struct adapter *adap)
2272 for_each_ethrxq(&adap->sge, i)
2273 disable_txq_db(&adap->sge.ethtxq[i].q);
2274 for_each_ofldrxq(&adap->sge, i)
2275 disable_txq_db(&adap->sge.ofldtxq[i].q);
2276 for_each_port(adap, i)
2277 disable_txq_db(&adap->sge.ctrlq[i].q);
2280 static void enable_dbs(struct adapter *adap)
2284 for_each_ethrxq(&adap->sge, i)
2285 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
2286 for_each_ofldrxq(&adap->sge, i)
2287 enable_txq_db(adap, &adap->sge.ofldtxq[i].q);
2288 for_each_port(adap, i)
2289 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
2292 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
2294 if (adap->uld_handle[CXGB4_ULD_RDMA])
2295 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA],
2299 static void process_db_full(struct work_struct *work)
2301 struct adapter *adap;
2303 adap = container_of(work, struct adapter, db_full_task);
2305 drain_db_fifo(adap, dbfifo_drain_delay);
2307 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2308 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2309 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
2310 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
2313 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
2315 u16 hw_pidx, hw_cidx;
2318 spin_lock_irq(&q->db_lock);
2319 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
2322 if (q->db_pidx != hw_pidx) {
2326 if (q->db_pidx >= hw_pidx)
2327 delta = q->db_pidx - hw_pidx;
2329 delta = q->size - hw_pidx + q->db_pidx;
2331 if (is_t4(adap->params.chip))
2332 val = PIDX_V(delta);
2334 val = PIDX_T5_V(delta);
2336 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2337 QID_V(q->cntxt_id) | val);
2342 spin_unlock_irq(&q->db_lock);
2344 CH_WARN(adap, "DB drop recovery failed.\n");
2346 static void recover_all_queues(struct adapter *adap)
2350 for_each_ethrxq(&adap->sge, i)
2351 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
2352 for_each_ofldrxq(&adap->sge, i)
2353 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
2354 for_each_port(adap, i)
2355 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2358 static void process_db_drop(struct work_struct *work)
2360 struct adapter *adap;
2362 adap = container_of(work, struct adapter, db_drop_task);
2364 if (is_t4(adap->params.chip)) {
2365 drain_db_fifo(adap, dbfifo_drain_delay);
2366 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
2367 drain_db_fifo(adap, dbfifo_drain_delay);
2368 recover_all_queues(adap);
2369 drain_db_fifo(adap, dbfifo_drain_delay);
2371 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2373 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2374 u16 qid = (dropped_db >> 15) & 0x1ffff;
2375 u16 pidx_inc = dropped_db & 0x1fff;
2377 unsigned int bar2_qid;
2380 ret = cxgb4_t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
2381 &bar2_qoffset, &bar2_qid);
2383 dev_err(adap->pdev_dev, "doorbell drop recovery: "
2384 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2386 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
2387 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2389 /* Re-enable BAR2 WC */
2390 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2393 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
2396 void t4_db_full(struct adapter *adap)
2398 if (is_t4(adap->params.chip)) {
2400 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2401 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2402 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
2403 queue_work(adap->workq, &adap->db_full_task);
2407 void t4_db_dropped(struct adapter *adap)
2409 if (is_t4(adap->params.chip)) {
2411 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2413 queue_work(adap->workq, &adap->db_drop_task);
2416 static void uld_attach(struct adapter *adap, unsigned int uld)
2419 struct cxgb4_lld_info lli;
2422 lli.pdev = adap->pdev;
2424 lli.l2t = adap->l2t;
2425 lli.tids = &adap->tids;
2426 lli.ports = adap->port;
2427 lli.vr = &adap->vres;
2428 lli.mtus = adap->params.mtus;
2429 if (uld == CXGB4_ULD_RDMA) {
2430 lli.rxq_ids = adap->sge.rdma_rxq;
2431 lli.ciq_ids = adap->sge.rdma_ciq;
2432 lli.nrxq = adap->sge.rdmaqs;
2433 lli.nciq = adap->sge.rdmaciqs;
2434 } else if (uld == CXGB4_ULD_ISCSI) {
2435 lli.rxq_ids = adap->sge.ofld_rxq;
2436 lli.nrxq = adap->sge.ofldqsets;
2438 lli.ntxq = adap->sge.ofldqsets;
2439 lli.nchan = adap->params.nports;
2440 lli.nports = adap->params.nports;
2441 lli.wr_cred = adap->params.ofldq_wr_cred;
2442 lli.adapter_type = adap->params.chip;
2443 lli.iscsi_iolen = MAXRXDATA_G(t4_read_reg(adap, TP_PARA_REG2_A));
2444 lli.cclk_ps = 1000000000 / adap->params.vpd.cclk;
2445 lli.udb_density = 1 << adap->params.sge.eq_qpp;
2446 lli.ucq_density = 1 << adap->params.sge.iq_qpp;
2447 lli.filt_mode = adap->params.tp.vlan_pri_map;
2448 /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
2449 for (i = 0; i < NCHAN; i++)
2451 lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS_A);
2452 lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL_A);
2453 lli.fw_vers = adap->params.fw_vers;
2454 lli.dbfifo_int_thresh = dbfifo_int_thresh;
2455 lli.sge_ingpadboundary = adap->sge.fl_align;
2456 lli.sge_egrstatuspagesize = adap->sge.stat_len;
2457 lli.sge_pktshift = adap->sge.pktshift;
2458 lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
2459 lli.max_ordird_qp = adap->params.max_ordird_qp;
2460 lli.max_ird_adapter = adap->params.max_ird_adapter;
2461 lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
2462 lli.nodeid = dev_to_node(adap->pdev_dev);
2464 handle = ulds[uld].add(&lli);
2465 if (IS_ERR(handle)) {
2466 dev_warn(adap->pdev_dev,
2467 "could not attach to the %s driver, error %ld\n",
2468 uld_str[uld], PTR_ERR(handle));
2472 adap->uld_handle[uld] = handle;
2474 if (!netevent_registered) {
2475 register_netevent_notifier(&cxgb4_netevent_nb);
2476 netevent_registered = true;
2479 if (adap->flags & FULL_INIT_DONE)
2480 ulds[uld].state_change(handle, CXGB4_STATE_UP);
2483 static void attach_ulds(struct adapter *adap)
2487 spin_lock(&adap_rcu_lock);
2488 list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list);
2489 spin_unlock(&adap_rcu_lock);
2491 mutex_lock(&uld_mutex);
2492 list_add_tail(&adap->list_node, &adapter_list);
2493 for (i = 0; i < CXGB4_ULD_MAX; i++)
2495 uld_attach(adap, i);
2496 mutex_unlock(&uld_mutex);
2499 static void detach_ulds(struct adapter *adap)
2503 mutex_lock(&uld_mutex);
2504 list_del(&adap->list_node);
2505 for (i = 0; i < CXGB4_ULD_MAX; i++)
2506 if (adap->uld_handle[i]) {
2507 ulds[i].state_change(adap->uld_handle[i],
2508 CXGB4_STATE_DETACH);
2509 adap->uld_handle[i] = NULL;
2511 if (netevent_registered && list_empty(&adapter_list)) {
2512 unregister_netevent_notifier(&cxgb4_netevent_nb);
2513 netevent_registered = false;
2515 mutex_unlock(&uld_mutex);
2517 spin_lock(&adap_rcu_lock);
2518 list_del_rcu(&adap->rcu_node);
2519 spin_unlock(&adap_rcu_lock);
2522 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2526 mutex_lock(&uld_mutex);
2527 for (i = 0; i < CXGB4_ULD_MAX; i++)
2528 if (adap->uld_handle[i])
2529 ulds[i].state_change(adap->uld_handle[i], new_state);
2530 mutex_unlock(&uld_mutex);
2534 * cxgb4_register_uld - register an upper-layer driver
2535 * @type: the ULD type
2536 * @p: the ULD methods
2538 * Registers an upper-layer driver with this driver and notifies the ULD
2539 * about any presently available devices that support its type. Returns
2540 * %-EBUSY if a ULD of the same type is already registered.
2542 int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
2545 struct adapter *adap;
2547 if (type >= CXGB4_ULD_MAX)
2549 mutex_lock(&uld_mutex);
2550 if (ulds[type].add) {
2555 list_for_each_entry(adap, &adapter_list, list_node)
2556 uld_attach(adap, type);
2557 out: mutex_unlock(&uld_mutex);
2560 EXPORT_SYMBOL(cxgb4_register_uld);
2563 * cxgb4_unregister_uld - unregister an upper-layer driver
2564 * @type: the ULD type
2566 * Unregisters an existing upper-layer driver.
2568 int cxgb4_unregister_uld(enum cxgb4_uld type)
2570 struct adapter *adap;
2572 if (type >= CXGB4_ULD_MAX)
2574 mutex_lock(&uld_mutex);
2575 list_for_each_entry(adap, &adapter_list, list_node)
2576 adap->uld_handle[type] = NULL;
2577 ulds[type].add = NULL;
2578 mutex_unlock(&uld_mutex);
2581 EXPORT_SYMBOL(cxgb4_unregister_uld);
2583 #if IS_ENABLED(CONFIG_IPV6)
2584 static int cxgb4_inet6addr_handler(struct notifier_block *this,
2585 unsigned long event, void *data)
2587 struct inet6_ifaddr *ifa = data;
2588 struct net_device *event_dev = ifa->idev->dev;
2589 const struct device *parent = NULL;
2590 #if IS_ENABLED(CONFIG_BONDING)
2591 struct adapter *adap;
2593 if (event_dev->priv_flags & IFF_802_1Q_VLAN)
2594 event_dev = vlan_dev_real_dev(event_dev);
2595 #if IS_ENABLED(CONFIG_BONDING)
2596 if (event_dev->flags & IFF_MASTER) {
2597 list_for_each_entry(adap, &adapter_list, list_node) {
2600 cxgb4_clip_get(adap->port[0],
2601 (const u32 *)ifa, 1);
2604 cxgb4_clip_release(adap->port[0],
2605 (const u32 *)ifa, 1);
2616 parent = event_dev->dev.parent;
2618 if (parent && parent->driver == &cxgb4_driver.driver) {
2621 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
2624 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
2633 static bool inet6addr_registered;
2634 static struct notifier_block cxgb4_inet6addr_notifier = {
2635 .notifier_call = cxgb4_inet6addr_handler
2638 static void update_clip(const struct adapter *adap)
2641 struct net_device *dev;
2646 for (i = 0; i < MAX_NPORTS; i++) {
2647 dev = adap->port[i];
2651 ret = cxgb4_update_root_dev_clip(dev);
2658 #endif /* IS_ENABLED(CONFIG_IPV6) */
2661 * cxgb_up - enable the adapter
2662 * @adap: adapter being enabled
2664 * Called when the first port is enabled, this function performs the
2665 * actions necessary to make an adapter operational, such as completing
2666 * the initialization of HW modules, and enabling interrupts.
2668 * Must be called with the rtnl lock held.
2670 static int cxgb_up(struct adapter *adap)
2674 err = setup_sge_queues(adap);
2677 err = setup_rss(adap);
2681 if (adap->flags & USING_MSIX) {
2682 name_msix_vecs(adap);
2683 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2684 adap->msix_info[0].desc, adap);
2688 err = request_msix_queue_irqs(adap);
2690 free_irq(adap->msix_info[0].vec, adap);
2694 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2695 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
2696 adap->port[0]->name, adap);
2702 t4_intr_enable(adap);
2703 adap->flags |= FULL_INIT_DONE;
2704 notify_ulds(adap, CXGB4_STATE_UP);
2705 #if IS_ENABLED(CONFIG_IPV6)
2711 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
2713 t4_free_sge_resources(adap);
2717 static void cxgb_down(struct adapter *adapter)
2719 cancel_work_sync(&adapter->tid_release_task);
2720 cancel_work_sync(&adapter->db_full_task);
2721 cancel_work_sync(&adapter->db_drop_task);
2722 adapter->tid_release_task_busy = false;
2723 adapter->tid_release_head = NULL;
2725 t4_sge_stop(adapter);
2726 t4_free_sge_resources(adapter);
2727 adapter->flags &= ~FULL_INIT_DONE;
2731 * net_device operations
2733 static int cxgb_open(struct net_device *dev)
2736 struct port_info *pi = netdev_priv(dev);
2737 struct adapter *adapter = pi->adapter;
2739 netif_carrier_off(dev);
2741 if (!(adapter->flags & FULL_INIT_DONE)) {
2742 err = cxgb_up(adapter);
2747 err = link_start(dev);
2749 netif_tx_start_all_queues(dev);
2753 static int cxgb_close(struct net_device *dev)
2755 struct port_info *pi = netdev_priv(dev);
2756 struct adapter *adapter = pi->adapter;
2758 netif_tx_stop_all_queues(dev);
2759 netif_carrier_off(dev);
2760 return t4_enable_vi(adapter, adapter->fn, pi->viid, false, false);
2763 /* Return an error number if the indicated filter isn't writable ...
2765 static int writable_filter(struct filter_entry *f)
2775 /* Delete the filter at the specified index (if valid). The checks for all
2776 * the common problems with doing this like the filter being locked, currently
2777 * pending in another operation, etc.
2779 static int delete_filter(struct adapter *adapter, unsigned int fidx)
2781 struct filter_entry *f;
2784 if (fidx >= adapter->tids.nftids + adapter->tids.nsftids)
2787 f = &adapter->tids.ftid_tab[fidx];
2788 ret = writable_filter(f);
2792 return del_filter_wr(adapter, fidx);
2797 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
2798 __be32 sip, __be16 sport, __be16 vlan,
2799 unsigned int queue, unsigned char port, unsigned char mask)
2802 struct filter_entry *f;
2803 struct adapter *adap;
2807 adap = netdev2adap(dev);
2809 /* Adjust stid to correct filter index */
2810 stid -= adap->tids.sftid_base;
2811 stid += adap->tids.nftids;
2813 /* Check to make sure the filter requested is writable ...
2815 f = &adap->tids.ftid_tab[stid];
2816 ret = writable_filter(f);
2820 /* Clear out any old resources being used by the filter before
2821 * we start constructing the new filter.
2824 clear_filter(adap, f);
2826 /* Clear out filter specifications */
2827 memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2828 f->fs.val.lport = cpu_to_be16(sport);
2829 f->fs.mask.lport = ~0;
2831 if ((val[0] | val[1] | val[2] | val[3]) != 0) {
2832 for (i = 0; i < 4; i++) {
2833 f->fs.val.lip[i] = val[i];
2834 f->fs.mask.lip[i] = ~0;
2836 if (adap->params.tp.vlan_pri_map & PORT_F) {
2837 f->fs.val.iport = port;
2838 f->fs.mask.iport = mask;
2842 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
2843 f->fs.val.proto = IPPROTO_TCP;
2844 f->fs.mask.proto = ~0;
2849 /* Mark filter as locked */
2853 ret = set_filter_wr(adap, stid);
2855 clear_filter(adap, f);
2861 EXPORT_SYMBOL(cxgb4_create_server_filter);
2863 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2864 unsigned int queue, bool ipv6)
2867 struct filter_entry *f;
2868 struct adapter *adap;
2870 adap = netdev2adap(dev);
2872 /* Adjust stid to correct filter index */
2873 stid -= adap->tids.sftid_base;
2874 stid += adap->tids.nftids;
2876 f = &adap->tids.ftid_tab[stid];
2877 /* Unlock the filter */
2880 ret = delete_filter(adap, stid);
2886 EXPORT_SYMBOL(cxgb4_remove_server_filter);
2888 static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
2889 struct rtnl_link_stats64 *ns)
2891 struct port_stats stats;
2892 struct port_info *p = netdev_priv(dev);
2893 struct adapter *adapter = p->adapter;
2895 /* Block retrieving statistics during EEH error
2896 * recovery. Otherwise, the recovery might fail
2897 * and the PCI device will be removed permanently
2899 spin_lock(&adapter->stats_lock);
2900 if (!netif_device_present(dev)) {
2901 spin_unlock(&adapter->stats_lock);
2904 t4_get_port_stats(adapter, p->tx_chan, &stats);
2905 spin_unlock(&adapter->stats_lock);
2907 ns->tx_bytes = stats.tx_octets;
2908 ns->tx_packets = stats.tx_frames;
2909 ns->rx_bytes = stats.rx_octets;
2910 ns->rx_packets = stats.rx_frames;
2911 ns->multicast = stats.rx_mcast_frames;
2913 /* detailed rx_errors */
2914 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2916 ns->rx_over_errors = 0;
2917 ns->rx_crc_errors = stats.rx_fcs_err;
2918 ns->rx_frame_errors = stats.rx_symbol_err;
2919 ns->rx_fifo_errors = stats.rx_ovflow0 + stats.rx_ovflow1 +
2920 stats.rx_ovflow2 + stats.rx_ovflow3 +
2921 stats.rx_trunc0 + stats.rx_trunc1 +
2922 stats.rx_trunc2 + stats.rx_trunc3;
2923 ns->rx_missed_errors = 0;
2925 /* detailed tx_errors */
2926 ns->tx_aborted_errors = 0;
2927 ns->tx_carrier_errors = 0;
2928 ns->tx_fifo_errors = 0;
2929 ns->tx_heartbeat_errors = 0;
2930 ns->tx_window_errors = 0;
2932 ns->tx_errors = stats.tx_error_frames;
2933 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2934 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2938 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2941 int ret = 0, prtad, devad;
2942 struct port_info *pi = netdev_priv(dev);
2943 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2947 if (pi->mdio_addr < 0)
2949 data->phy_id = pi->mdio_addr;
2953 if (mdio_phy_id_is_c45(data->phy_id)) {
2954 prtad = mdio_phy_id_prtad(data->phy_id);
2955 devad = mdio_phy_id_devad(data->phy_id);
2956 } else if (data->phy_id < 32) {
2957 prtad = data->phy_id;
2959 data->reg_num &= 0x1f;
2963 mbox = pi->adapter->fn;
2964 if (cmd == SIOCGMIIREG)
2965 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
2966 data->reg_num, &data->val_out);
2968 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
2969 data->reg_num, data->val_in);
2977 static void cxgb_set_rxmode(struct net_device *dev)
2979 /* unfortunately we can't return errors to the stack */
2980 set_rxmode(dev, -1, false);
2983 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2986 struct port_info *pi = netdev_priv(dev);
2988 if (new_mtu < 81 || new_mtu > MAX_MTU) /* accommodate SACK */
2990 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, new_mtu, -1,
2997 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
3000 struct sockaddr *addr = p;
3001 struct port_info *pi = netdev_priv(dev);
3003 if (!is_valid_ether_addr(addr->sa_data))
3004 return -EADDRNOTAVAIL;
3006 ret = t4_change_mac(pi->adapter, pi->adapter->fn, pi->viid,
3007 pi->xact_addr_filt, addr->sa_data, true, true);
3011 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3012 pi->xact_addr_filt = ret;
3016 #ifdef CONFIG_NET_POLL_CONTROLLER
3017 static void cxgb_netpoll(struct net_device *dev)
3019 struct port_info *pi = netdev_priv(dev);
3020 struct adapter *adap = pi->adapter;
3022 if (adap->flags & USING_MSIX) {
3024 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
3026 for (i = pi->nqsets; i; i--, rx++)
3027 t4_sge_intr_msix(0, &rx->rspq);
3029 t4_intr_handler(adap)(0, adap);
3033 static const struct net_device_ops cxgb4_netdev_ops = {
3034 .ndo_open = cxgb_open,
3035 .ndo_stop = cxgb_close,
3036 .ndo_start_xmit = t4_eth_xmit,
3037 .ndo_select_queue = cxgb_select_queue,
3038 .ndo_get_stats64 = cxgb_get_stats,
3039 .ndo_set_rx_mode = cxgb_set_rxmode,
3040 .ndo_set_mac_address = cxgb_set_mac_addr,
3041 .ndo_set_features = cxgb_set_features,
3042 .ndo_validate_addr = eth_validate_addr,
3043 .ndo_do_ioctl = cxgb_ioctl,
3044 .ndo_change_mtu = cxgb_change_mtu,
3045 #ifdef CONFIG_NET_POLL_CONTROLLER
3046 .ndo_poll_controller = cxgb_netpoll,
3048 #ifdef CONFIG_CHELSIO_T4_FCOE
3049 .ndo_fcoe_enable = cxgb_fcoe_enable,
3050 .ndo_fcoe_disable = cxgb_fcoe_disable,
3051 #endif /* CONFIG_CHELSIO_T4_FCOE */
3052 #ifdef CONFIG_NET_RX_BUSY_POLL
3053 .ndo_busy_poll = cxgb_busy_poll,
3058 void t4_fatal_err(struct adapter *adap)
3060 t4_set_reg_field(adap, SGE_CONTROL_A, GLOBALENABLE_F, 0);
3061 t4_intr_disable(adap);
3062 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
3065 static void setup_memwin(struct adapter *adap)
3067 u32 nic_win_base = t4_get_util_window(adap);
3069 t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
3072 static void setup_memwin_rdma(struct adapter *adap)
3074 if (adap->vres.ocq.size) {
3078 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
3079 start &= PCI_BASE_ADDRESS_MEM_MASK;
3080 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
3081 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
3083 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
3084 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
3086 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
3087 adap->vres.ocq.start);
3089 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
3093 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3098 /* get device capabilities */
3099 memset(c, 0, sizeof(*c));
3100 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3101 FW_CMD_REQUEST_F | FW_CMD_READ_F);
3102 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
3103 ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), c);
3107 /* select capabilities we'll be using */
3108 if (c->niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
3110 c->niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
3112 c->niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
3113 } else if (vf_acls) {
3114 dev_err(adap->pdev_dev, "virtualization ACLs not supported");
3117 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3118 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3119 ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), NULL);
3123 ret = t4_config_glbl_rss(adap, adap->fn,
3124 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
3125 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
3126 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
3130 ret = t4_cfg_pfvf(adap, adap->fn, adap->fn, 0, adap->sge.egr_sz, 64,
3131 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
3138 /* tweak some settings */
3139 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
3140 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
3141 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
3142 v = t4_read_reg(adap, TP_PIO_DATA_A);
3143 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
3145 /* first 4 Tx modulation queues point to consecutive Tx channels */
3146 adap->params.tp.tx_modq_map = 0xE4;
3147 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
3148 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
3150 /* associate each Tx modulation queue with consecutive Tx channels */
3152 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3153 &v, 1, TP_TX_SCHED_HDR_A);
3154 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3155 &v, 1, TP_TX_SCHED_FIFO_A);
3156 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3157 &v, 1, TP_TX_SCHED_PCMD_A);
3159 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
3160 if (is_offload(adap)) {
3161 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
3162 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3163 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3164 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3165 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3166 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
3167 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3168 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3169 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3170 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3173 /* get basic stuff going */
3174 return t4_early_init(adap, adap->fn);
3178 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
3180 #define MAX_ATIDS 8192U
3183 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3185 * If the firmware we're dealing with has Configuration File support, then
3186 * we use that to perform all configuration
3190 * Tweak configuration based on module parameters, etc. Most of these have
3191 * defaults assigned to them by Firmware Configuration Files (if we're using
3192 * them) but need to be explicitly set if we're using hard-coded
3193 * initialization. But even in the case of using Firmware Configuration
3194 * Files, we'd like to expose the ability to change these via module
3195 * parameters so these are essentially common tweaks/settings for
3196 * Configuration Files and hard-coded initialization ...
3198 static int adap_init0_tweaks(struct adapter *adapter)
3201 * Fix up various Host-Dependent Parameters like Page Size, Cache
3202 * Line Size, etc. The firmware default is for a 4KB Page Size and
3203 * 64B Cache Line Size ...
3205 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
3208 * Process module parameters which affect early initialization.
3210 if (rx_dma_offset != 2 && rx_dma_offset != 0) {
3211 dev_err(&adapter->pdev->dev,
3212 "Ignoring illegal rx_dma_offset=%d, using 2\n",
3216 t4_set_reg_field(adapter, SGE_CONTROL_A,
3217 PKTSHIFT_V(PKTSHIFT_M),
3218 PKTSHIFT_V(rx_dma_offset));
3221 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
3222 * adds the pseudo header itself.
3224 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
3225 CSUM_HAS_PSEUDO_HDR_F, 0);
3230 /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips
3231 * unto themselves and they contain their own firmware to perform their
3234 static int phy_aq1202_version(const u8 *phy_fw_data,
3239 /* At offset 0x8 you're looking for the primary image's
3240 * starting offset which is 3 Bytes wide
3242 * At offset 0xa of the primary image, you look for the offset
3243 * of the DRAM segment which is 3 Bytes wide.
3245 * The FW version is at offset 0x27e of the DRAM and is 2 Bytes
3248 #define be16(__p) (((__p)[0] << 8) | (__p)[1])
3249 #define le16(__p) ((__p)[0] | ((__p)[1] << 8))
3250 #define le24(__p) (le16(__p) | ((__p)[2] << 16))
3252 offset = le24(phy_fw_data + 0x8) << 12;
3253 offset = le24(phy_fw_data + offset + 0xa);
3254 return be16(phy_fw_data + offset + 0x27e);
3261 static struct info_10gbt_phy_fw {
3262 unsigned int phy_fw_id; /* PCI Device ID */
3263 char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */
3264 int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size);
3265 int phy_flash; /* Has FLASH for PHY Firmware */
3266 } phy_info_array[] = {
3268 PHY_AQ1202_DEVICEID,
3269 PHY_AQ1202_FIRMWARE,
3274 PHY_BCM84834_DEVICEID,
3275 PHY_BCM84834_FIRMWARE,
3282 static struct info_10gbt_phy_fw *find_phy_info(int devid)
3286 for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) {
3287 if (phy_info_array[i].phy_fw_id == devid)
3288 return &phy_info_array[i];
3293 /* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to
3294 * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error
3295 * we return a negative error number. If we transfer new firmware we return 1
3296 * (from t4_load_phy_fw()). If we don't do anything we return 0.
3298 static int adap_init0_phy(struct adapter *adap)
3300 const struct firmware *phyf;
3302 struct info_10gbt_phy_fw *phy_info;
3304 /* Use the device ID to determine which PHY file to flash.
3306 phy_info = find_phy_info(adap->pdev->device);
3308 dev_warn(adap->pdev_dev,
3309 "No PHY Firmware file found for this PHY\n");
3313 /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then
3314 * use that. The adapter firmware provides us with a memory buffer
3315 * where we can load a PHY firmware file from the host if we want to
3316 * override the PHY firmware File in flash.
3318 ret = request_firmware_direct(&phyf, phy_info->phy_fw_file,
3321 /* For adapters without FLASH attached to PHY for their
3322 * firmware, it's obviously a fatal error if we can't get the
3323 * firmware to the adapter. For adapters with PHY firmware
3324 * FLASH storage, it's worth a warning if we can't find the
3325 * PHY Firmware but we'll neuter the error ...
3327 dev_err(adap->pdev_dev, "unable to find PHY Firmware image "
3328 "/lib/firmware/%s, error %d\n",
3329 phy_info->phy_fw_file, -ret);
3330 if (phy_info->phy_flash) {
3331 int cur_phy_fw_ver = 0;
3333 t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3334 dev_warn(adap->pdev_dev, "continuing with, on-adapter "
3335 "FLASH copy, version %#x\n", cur_phy_fw_ver);
3342 /* Load PHY Firmware onto adapter.
3344 ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock,
3345 phy_info->phy_fw_version,
3346 (u8 *)phyf->data, phyf->size);
3348 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n",
3351 int new_phy_fw_ver = 0;
3353 if (phy_info->phy_fw_version)
3354 new_phy_fw_ver = phy_info->phy_fw_version(phyf->data,
3356 dev_info(adap->pdev_dev, "Successfully transferred PHY "
3357 "Firmware /lib/firmware/%s, version %#x\n",
3358 phy_info->phy_fw_file, new_phy_fw_ver);
3361 release_firmware(phyf);
3367 * Attempt to initialize the adapter via a Firmware Configuration File.
3369 static int adap_init0_config(struct adapter *adapter, int reset)
3371 struct fw_caps_config_cmd caps_cmd;
3372 const struct firmware *cf;
3373 unsigned long mtype = 0, maddr = 0;
3374 u32 finiver, finicsum, cfcsum;
3376 int config_issued = 0;
3377 char *fw_config_file, fw_config_file_path[256];
3378 char *config_name = NULL;
3381 * Reset device if necessary.
3384 ret = t4_fw_reset(adapter, adapter->mbox,
3385 PIORSTMODE_F | PIORST_F);
3390 /* If this is a 10Gb/s-BT adapter make sure the chip-external
3391 * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs
3392 * to be performed after any global adapter RESET above since some
3393 * PHYs only have local RAM copies of the PHY firmware.
3395 if (is_10gbt_device(adapter->pdev->device)) {
3396 ret = adap_init0_phy(adapter);
3401 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
3402 * then use that. Otherwise, use the configuration file stored
3403 * in the adapter flash ...
3405 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
3407 fw_config_file = FW4_CFNAME;
3410 fw_config_file = FW5_CFNAME;
3413 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
3414 adapter->pdev->device);
3419 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
3421 config_name = "On FLASH";
3422 mtype = FW_MEMTYPE_CF_FLASH;
3423 maddr = t4_flash_cfg_addr(adapter);
3425 u32 params[7], val[7];
3427 sprintf(fw_config_file_path,
3428 "/lib/firmware/%s", fw_config_file);
3429 config_name = fw_config_file_path;
3431 if (cf->size >= FLASH_CFG_MAX_SIZE)
3434 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3435 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3436 ret = t4_query_params(adapter, adapter->mbox,
3437 adapter->fn, 0, 1, params, val);
3440 * For t4_memory_rw() below addresses and
3441 * sizes have to be in terms of multiples of 4
3442 * bytes. So, if the Configuration File isn't
3443 * a multiple of 4 bytes in length we'll have
3444 * to write that out separately since we can't
3445 * guarantee that the bytes following the
3446 * residual byte in the buffer returned by
3447 * request_firmware() are zeroed out ...
3449 size_t resid = cf->size & 0x3;
3450 size_t size = cf->size & ~0x3;
3451 __be32 *data = (__be32 *)cf->data;
3453 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
3454 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
3456 spin_lock(&adapter->win0_lock);
3457 ret = t4_memory_rw(adapter, 0, mtype, maddr,
3458 size, data, T4_MEMORY_WRITE);
3459 if (ret == 0 && resid != 0) {
3466 last.word = data[size >> 2];
3467 for (i = resid; i < 4; i++)
3469 ret = t4_memory_rw(adapter, 0, mtype,
3474 spin_unlock(&adapter->win0_lock);
3478 release_firmware(cf);
3484 * Issue a Capability Configuration command to the firmware to get it
3485 * to parse the Configuration File. We don't use t4_fw_config_file()
3486 * because we want the ability to modify various features after we've
3487 * processed the configuration file ...
3489 memset(&caps_cmd, 0, sizeof(caps_cmd));
3490 caps_cmd.op_to_write =
3491 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3494 caps_cmd.cfvalid_to_len16 =
3495 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
3496 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
3497 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
3498 FW_LEN16(caps_cmd));
3499 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3502 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
3503 * Configuration File in FLASH), our last gasp effort is to use the
3504 * Firmware Configuration File which is embedded in the firmware. A
3505 * very few early versions of the firmware didn't have one embedded
3506 * but we can ignore those.
3508 if (ret == -ENOENT) {
3509 memset(&caps_cmd, 0, sizeof(caps_cmd));
3510 caps_cmd.op_to_write =
3511 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3514 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3515 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
3516 sizeof(caps_cmd), &caps_cmd);
3517 config_name = "Firmware Default";
3524 finiver = ntohl(caps_cmd.finiver);
3525 finicsum = ntohl(caps_cmd.finicsum);
3526 cfcsum = ntohl(caps_cmd.cfcsum);
3527 if (finicsum != cfcsum)
3528 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
3529 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
3533 * And now tell the firmware to use the configuration we just loaded.
3535 caps_cmd.op_to_write =
3536 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3539 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3540 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3546 * Tweak configuration based on system architecture, module
3549 ret = adap_init0_tweaks(adapter);
3554 * And finally tell the firmware to initialize itself using the
3555 * parameters from the Configuration File.
3557 ret = t4_fw_initialize(adapter, adapter->mbox);
3561 /* Emit Firmware Configuration File information and return
3564 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
3565 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
3566 config_name, finiver, cfcsum);
3570 * Something bad happened. Return the error ... (If the "error"
3571 * is that there's no Configuration File on the adapter we don't
3572 * want to issue a warning since this is fairly common.)
3575 if (config_issued && ret != -ENOENT)
3576 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
3581 static struct fw_info fw_info_array[] = {
3584 .fs_name = FW4_CFNAME,
3585 .fw_mod_name = FW4_FNAME,
3587 .chip = FW_HDR_CHIP_T4,
3588 .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
3589 .intfver_nic = FW_INTFVER(T4, NIC),
3590 .intfver_vnic = FW_INTFVER(T4, VNIC),
3591 .intfver_ri = FW_INTFVER(T4, RI),
3592 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3593 .intfver_fcoe = FW_INTFVER(T4, FCOE),
3597 .fs_name = FW5_CFNAME,
3598 .fw_mod_name = FW5_FNAME,
3600 .chip = FW_HDR_CHIP_T5,
3601 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
3602 .intfver_nic = FW_INTFVER(T5, NIC),
3603 .intfver_vnic = FW_INTFVER(T5, VNIC),
3604 .intfver_ri = FW_INTFVER(T5, RI),
3605 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3606 .intfver_fcoe = FW_INTFVER(T5, FCOE),
3611 static struct fw_info *find_fw_info(int chip)
3615 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
3616 if (fw_info_array[i].chip == chip)
3617 return &fw_info_array[i];
3623 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3625 static int adap_init0(struct adapter *adap)
3629 enum dev_state state;
3630 u32 params[7], val[7];
3631 struct fw_caps_config_cmd caps_cmd;
3634 /* Grab Firmware Device Log parameters as early as possible so we have
3635 * access to it for debugging, etc.
3637 ret = t4_init_devlog_params(adap);
3641 /* Contact FW, advertising Master capability */
3642 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
3644 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
3648 if (ret == adap->mbox)
3649 adap->flags |= MASTER_PF;
3652 * If we're the Master PF Driver and the device is uninitialized,
3653 * then let's consider upgrading the firmware ... (We always want
3654 * to check the firmware version number in order to A. get it for
3655 * later reporting and B. to warn if the currently loaded firmware
3656 * is excessively mismatched relative to the driver.)
3658 t4_get_fw_version(adap, &adap->params.fw_vers);
3659 t4_get_tp_version(adap, &adap->params.tp_vers);
3660 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
3661 struct fw_info *fw_info;
3662 struct fw_hdr *card_fw;
3663 const struct firmware *fw;
3664 const u8 *fw_data = NULL;
3665 unsigned int fw_size = 0;
3667 /* This is the firmware whose headers the driver was compiled
3670 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
3671 if (fw_info == NULL) {
3672 dev_err(adap->pdev_dev,
3673 "unable to get firmware info for chip %d.\n",
3674 CHELSIO_CHIP_VERSION(adap->params.chip));
3678 /* allocate memory to read the header of the firmware on the
3681 card_fw = t4_alloc_mem(sizeof(*card_fw));
3683 /* Get FW from from /lib/firmware/ */
3684 ret = request_firmware(&fw, fw_info->fw_mod_name,
3687 dev_err(adap->pdev_dev,
3688 "unable to load firmware image %s, error %d\n",
3689 fw_info->fw_mod_name, ret);
3695 /* upgrade FW logic */
3696 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
3700 release_firmware(fw);
3701 t4_free_mem(card_fw);
3708 * Grab VPD parameters. This should be done after we establish a
3709 * connection to the firmware since some of the VPD parameters
3710 * (notably the Core Clock frequency) are retrieved via requests to
3711 * the firmware. On the other hand, we need these fairly early on
3712 * so we do this right after getting ahold of the firmware.
3714 ret = get_vpd_params(adap, &adap->params.vpd);
3719 * Find out what ports are available to us. Note that we need to do
3720 * this before calling adap_init0_no_config() since it needs nports
3724 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3725 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
3726 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1, &v, &port_vec);
3730 adap->params.nports = hweight32(port_vec);
3731 adap->params.portvec = port_vec;
3733 /* If the firmware is initialized already, emit a simply note to that
3734 * effect. Otherwise, it's time to try initializing the adapter.
3736 if (state == DEV_STATE_INIT) {
3737 dev_info(adap->pdev_dev, "Coming up as %s: "\
3738 "Adapter already initialized\n",
3739 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
3741 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
3742 "Initializing adapter\n");
3744 /* Find out whether we're dealing with a version of the
3745 * firmware which has configuration file support.
3747 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3748 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3749 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1,
3752 /* If the firmware doesn't support Configuration Files,
3756 dev_err(adap->pdev_dev, "firmware doesn't support "
3757 "Firmware Configuration Files\n");
3761 /* The firmware provides us with a memory buffer where we can
3762 * load a Configuration File from the host if we want to
3763 * override the Configuration File in flash.
3765 ret = adap_init0_config(adap, reset);
3766 if (ret == -ENOENT) {
3767 dev_err(adap->pdev_dev, "no Configuration File "
3768 "present on adapter.\n");
3772 dev_err(adap->pdev_dev, "could not initialize "
3773 "adapter, error %d\n", -ret);
3778 /* Give the SGE code a chance to pull in anything that it needs ...
3779 * Note that this must be called after we retrieve our VPD parameters
3780 * in order to know how to convert core ticks to seconds, etc.
3782 ret = t4_sge_init(adap);
3786 if (is_bypass_device(adap->pdev->device))
3787 adap->params.bypass = 1;
3790 * Grab some of our basic fundamental operating parameters.
3792 #define FW_PARAM_DEV(param) \
3793 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
3794 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
3796 #define FW_PARAM_PFVF(param) \
3797 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
3798 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \
3799 FW_PARAMS_PARAM_Y_V(0) | \
3800 FW_PARAMS_PARAM_Z_V(0)
3802 params[0] = FW_PARAM_PFVF(EQ_START);
3803 params[1] = FW_PARAM_PFVF(L2T_START);
3804 params[2] = FW_PARAM_PFVF(L2T_END);
3805 params[3] = FW_PARAM_PFVF(FILTER_START);
3806 params[4] = FW_PARAM_PFVF(FILTER_END);
3807 params[5] = FW_PARAM_PFVF(IQFLINT_START);
3808 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params, val);
3811 adap->sge.egr_start = val[0];
3812 adap->l2t_start = val[1];
3813 adap->l2t_end = val[2];
3814 adap->tids.ftid_base = val[3];
3815 adap->tids.nftids = val[4] - val[3] + 1;
3816 adap->sge.ingr_start = val[5];
3818 /* qids (ingress/egress) returned from firmware can be anywhere
3819 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
3820 * Hence driver needs to allocate memory for this range to
3821 * store the queue info. Get the highest IQFLINT/EQ index returned
3822 * in FW_EQ_*_CMD.alloc command.
3824 params[0] = FW_PARAM_PFVF(EQ_END);
3825 params[1] = FW_PARAM_PFVF(IQFLINT_END);
3826 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
3829 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
3830 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
3832 adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
3833 sizeof(*adap->sge.egr_map), GFP_KERNEL);
3834 if (!adap->sge.egr_map) {
3839 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
3840 sizeof(*adap->sge.ingr_map), GFP_KERNEL);
3841 if (!adap->sge.ingr_map) {
3846 /* Allocate the memory for the vaious egress queue bitmaps
3847 * ie starving_fl and txq_maperr.
3849 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3850 sizeof(long), GFP_KERNEL);
3851 if (!adap->sge.starving_fl) {
3856 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3857 sizeof(long), GFP_KERNEL);
3858 if (!adap->sge.txq_maperr) {
3863 params[0] = FW_PARAM_PFVF(CLIP_START);
3864 params[1] = FW_PARAM_PFVF(CLIP_END);
3865 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
3868 adap->clipt_start = val[0];
3869 adap->clipt_end = val[1];
3871 /* query params related to active filter region */
3872 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
3873 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
3874 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
3875 /* If Active filter size is set we enable establishing
3876 * offload connection through firmware work request
3878 if ((val[0] != val[1]) && (ret >= 0)) {
3879 adap->flags |= FW_OFLD_CONN;
3880 adap->tids.aftid_base = val[0];
3881 adap->tids.aftid_end = val[1];
3884 /* If we're running on newer firmware, let it know that we're
3885 * prepared to deal with encapsulated CPL messages. Older
3886 * firmware won't understand this and we'll just get
3887 * unencapsulated messages ...
3889 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
3891 (void) t4_set_params(adap, adap->mbox, adap->fn, 0, 1, params, val);
3894 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
3895 * capability. Earlier versions of the firmware didn't have the
3896 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
3897 * permission to use ULPTX MEMWRITE DSGL.
3899 if (is_t4(adap->params.chip)) {
3900 adap->params.ulptx_memwrite_dsgl = false;
3902 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
3903 ret = t4_query_params(adap, adap->mbox, adap->fn, 0,
3905 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
3909 * Get device capabilities so we can determine what resources we need
3912 memset(&caps_cmd, 0, sizeof(caps_cmd));
3913 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3914 FW_CMD_REQUEST_F | FW_CMD_READ_F);
3915 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3916 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
3921 if (caps_cmd.ofldcaps) {
3922 /* query offload-related parameters */
3923 params[0] = FW_PARAM_DEV(NTID);
3924 params[1] = FW_PARAM_PFVF(SERVER_START);
3925 params[2] = FW_PARAM_PFVF(SERVER_END);
3926 params[3] = FW_PARAM_PFVF(TDDP_START);
3927 params[4] = FW_PARAM_PFVF(TDDP_END);
3928 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3929 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
3933 adap->tids.ntids = val[0];
3934 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
3935 adap->tids.stid_base = val[1];
3936 adap->tids.nstids = val[2] - val[1] + 1;
3938 * Setup server filter region. Divide the available filter
3939 * region into two parts. Regular filters get 1/3rd and server
3940 * filters get 2/3rd part. This is only enabled if workarond
3942 * 1. For regular filters.
3943 * 2. Server filter: This are special filters which are used
3944 * to redirect SYN packets to offload queue.
3946 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
3947 adap->tids.sftid_base = adap->tids.ftid_base +
3948 DIV_ROUND_UP(adap->tids.nftids, 3);
3949 adap->tids.nsftids = adap->tids.nftids -
3950 DIV_ROUND_UP(adap->tids.nftids, 3);
3951 adap->tids.nftids = adap->tids.sftid_base -
3952 adap->tids.ftid_base;
3954 adap->vres.ddp.start = val[3];
3955 adap->vres.ddp.size = val[4] - val[3] + 1;
3956 adap->params.ofldq_wr_cred = val[5];
3958 adap->params.offload = 1;
3960 if (caps_cmd.rdmacaps) {
3961 params[0] = FW_PARAM_PFVF(STAG_START);
3962 params[1] = FW_PARAM_PFVF(STAG_END);
3963 params[2] = FW_PARAM_PFVF(RQ_START);
3964 params[3] = FW_PARAM_PFVF(RQ_END);
3965 params[4] = FW_PARAM_PFVF(PBL_START);
3966 params[5] = FW_PARAM_PFVF(PBL_END);
3967 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
3971 adap->vres.stag.start = val[0];
3972 adap->vres.stag.size = val[1] - val[0] + 1;
3973 adap->vres.rq.start = val[2];
3974 adap->vres.rq.size = val[3] - val[2] + 1;
3975 adap->vres.pbl.start = val[4];
3976 adap->vres.pbl.size = val[5] - val[4] + 1;
3978 params[0] = FW_PARAM_PFVF(SQRQ_START);
3979 params[1] = FW_PARAM_PFVF(SQRQ_END);
3980 params[2] = FW_PARAM_PFVF(CQ_START);
3981 params[3] = FW_PARAM_PFVF(CQ_END);
3982 params[4] = FW_PARAM_PFVF(OCQ_START);
3983 params[5] = FW_PARAM_PFVF(OCQ_END);
3984 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params,
3988 adap->vres.qp.start = val[0];
3989 adap->vres.qp.size = val[1] - val[0] + 1;
3990 adap->vres.cq.start = val[2];
3991 adap->vres.cq.size = val[3] - val[2] + 1;
3992 adap->vres.ocq.start = val[4];
3993 adap->vres.ocq.size = val[5] - val[4] + 1;
3995 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
3996 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
3997 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params,
4000 adap->params.max_ordird_qp = 8;
4001 adap->params.max_ird_adapter = 32 * adap->tids.ntids;
4004 adap->params.max_ordird_qp = val[0];
4005 adap->params.max_ird_adapter = val[1];
4007 dev_info(adap->pdev_dev,
4008 "max_ordird_qp %d max_ird_adapter %d\n",
4009 adap->params.max_ordird_qp,
4010 adap->params.max_ird_adapter);
4012 if (caps_cmd.iscsicaps) {
4013 params[0] = FW_PARAM_PFVF(ISCSI_START);
4014 params[1] = FW_PARAM_PFVF(ISCSI_END);
4015 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2,
4019 adap->vres.iscsi.start = val[0];
4020 adap->vres.iscsi.size = val[1] - val[0] + 1;
4022 #undef FW_PARAM_PFVF
4025 /* The MTU/MSS Table is initialized by now, so load their values. If
4026 * we're initializing the adapter, then we'll make any modifications
4027 * we want to the MTU/MSS Table and also initialize the congestion
4030 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
4031 if (state != DEV_STATE_INIT) {
4034 /* The default MTU Table contains values 1492 and 1500.
4035 * However, for TCP, it's better to have two values which are
4036 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
4037 * This allows us to have a TCP Data Payload which is a
4038 * multiple of 8 regardless of what combination of TCP Options
4039 * are in use (always a multiple of 4 bytes) which is
4040 * important for performance reasons. For instance, if no
4041 * options are in use, then we have a 20-byte IP header and a
4042 * 20-byte TCP header. In this case, a 1500-byte MSS would
4043 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
4044 * which is not a multiple of 8. So using an MSS of 1488 in
4045 * this case results in a TCP Data Payload of 1448 bytes which
4046 * is a multiple of 8. On the other hand, if 12-byte TCP Time
4047 * Stamps have been negotiated, then an MTU of 1500 bytes
4048 * results in a TCP Data Payload of 1448 bytes which, as
4049 * above, is a multiple of 8 bytes ...
4051 for (i = 0; i < NMTUS; i++)
4052 if (adap->params.mtus[i] == 1492) {
4053 adap->params.mtus[i] = 1488;
4057 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4058 adap->params.b_wnd);
4060 t4_init_sge_params(adap);
4061 t4_init_tp_params(adap);
4062 adap->flags |= FW_OK;
4066 * Something bad happened. If a command timed out or failed with EIO
4067 * FW does not operate within its spec or something catastrophic
4068 * happened to HW/FW, stop issuing commands.
4071 kfree(adap->sge.egr_map);
4072 kfree(adap->sge.ingr_map);
4073 kfree(adap->sge.starving_fl);
4074 kfree(adap->sge.txq_maperr);
4075 if (ret != -ETIMEDOUT && ret != -EIO)
4076 t4_fw_bye(adap, adap->mbox);
4082 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
4083 pci_channel_state_t state)
4086 struct adapter *adap = pci_get_drvdata(pdev);
4092 adap->flags &= ~FW_OK;
4093 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
4094 spin_lock(&adap->stats_lock);
4095 for_each_port(adap, i) {
4096 struct net_device *dev = adap->port[i];
4098 netif_device_detach(dev);
4099 netif_carrier_off(dev);
4101 spin_unlock(&adap->stats_lock);
4102 disable_interrupts(adap);
4103 if (adap->flags & FULL_INIT_DONE)
4106 if ((adap->flags & DEV_ENABLED)) {
4107 pci_disable_device(pdev);
4108 adap->flags &= ~DEV_ENABLED;
4110 out: return state == pci_channel_io_perm_failure ?
4111 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
4114 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
4117 struct fw_caps_config_cmd c;
4118 struct adapter *adap = pci_get_drvdata(pdev);
4121 pci_restore_state(pdev);
4122 pci_save_state(pdev);
4123 return PCI_ERS_RESULT_RECOVERED;
4126 if (!(adap->flags & DEV_ENABLED)) {
4127 if (pci_enable_device(pdev)) {
4128 dev_err(&pdev->dev, "Cannot reenable PCI "
4129 "device after reset\n");
4130 return PCI_ERS_RESULT_DISCONNECT;
4132 adap->flags |= DEV_ENABLED;
4135 pci_set_master(pdev);
4136 pci_restore_state(pdev);
4137 pci_save_state(pdev);
4138 pci_cleanup_aer_uncorrect_error_status(pdev);
4140 if (t4_wait_dev_ready(adap->regs) < 0)
4141 return PCI_ERS_RESULT_DISCONNECT;
4142 if (t4_fw_hello(adap, adap->fn, adap->fn, MASTER_MUST, NULL) < 0)
4143 return PCI_ERS_RESULT_DISCONNECT;
4144 adap->flags |= FW_OK;
4145 if (adap_init1(adap, &c))
4146 return PCI_ERS_RESULT_DISCONNECT;
4148 for_each_port(adap, i) {
4149 struct port_info *p = adap2pinfo(adap, i);
4151 ret = t4_alloc_vi(adap, adap->fn, p->tx_chan, adap->fn, 0, 1,
4154 return PCI_ERS_RESULT_DISCONNECT;
4156 p->xact_addr_filt = -1;
4159 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4160 adap->params.b_wnd);
4163 return PCI_ERS_RESULT_DISCONNECT;
4164 return PCI_ERS_RESULT_RECOVERED;
4167 static void eeh_resume(struct pci_dev *pdev)
4170 struct adapter *adap = pci_get_drvdata(pdev);
4176 for_each_port(adap, i) {
4177 struct net_device *dev = adap->port[i];
4179 if (netif_running(dev)) {
4181 cxgb_set_rxmode(dev);
4183 netif_device_attach(dev);
4188 static const struct pci_error_handlers cxgb4_eeh = {
4189 .error_detected = eeh_err_detected,
4190 .slot_reset = eeh_slot_reset,
4191 .resume = eeh_resume,
4194 static inline bool is_x_10g_port(const struct link_config *lc)
4196 return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||
4197 (lc->supported & FW_PORT_CAP_SPEED_40G) != 0;
4200 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
4201 unsigned int us, unsigned int cnt,
4202 unsigned int size, unsigned int iqe_size)
4205 cxgb4_set_rspq_intr_params(q, us, cnt);
4206 q->iqe_len = iqe_size;
4211 * Perform default configuration of DMA queues depending on the number and type
4212 * of ports we found and the number of available CPUs. Most settings can be
4213 * modified by the admin prior to actual use.
4215 static void cfg_queues(struct adapter *adap)
4217 struct sge *s = &adap->sge;
4218 int i, n10g = 0, qidx = 0;
4219 #ifndef CONFIG_CHELSIO_T4_DCB
4224 for_each_port(adap, i)
4225 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
4226 #ifdef CONFIG_CHELSIO_T4_DCB
4227 /* For Data Center Bridging support we need to be able to support up
4228 * to 8 Traffic Priorities; each of which will be assigned to its
4229 * own TX Queue in order to prevent Head-Of-Line Blocking.
4231 if (adap->params.nports * 8 > MAX_ETH_QSETS) {
4232 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
4233 MAX_ETH_QSETS, adap->params.nports * 8);
4237 for_each_port(adap, i) {
4238 struct port_info *pi = adap2pinfo(adap, i);
4240 pi->first_qset = qidx;
4244 #else /* !CONFIG_CHELSIO_T4_DCB */
4246 * We default to 1 queue per non-10G port and up to # of cores queues
4250 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
4251 if (q10g > netif_get_num_default_rss_queues())
4252 q10g = netif_get_num_default_rss_queues();
4254 for_each_port(adap, i) {
4255 struct port_info *pi = adap2pinfo(adap, i);
4257 pi->first_qset = qidx;
4258 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
4261 #endif /* !CONFIG_CHELSIO_T4_DCB */
4264 s->max_ethqsets = qidx; /* MSI-X may lower it later */
4266 if (is_offload(adap)) {
4268 * For offload we use 1 queue/channel if all ports are up to 1G,
4269 * otherwise we divide all available queues amongst the channels
4270 * capped by the number of available cores.
4273 i = min_t(int, ARRAY_SIZE(s->ofldrxq),
4275 s->ofldqsets = roundup(i, adap->params.nports);
4277 s->ofldqsets = adap->params.nports;
4278 /* For RDMA one Rx queue per channel suffices */
4279 s->rdmaqs = adap->params.nports;
4280 /* Try and allow at least 1 CIQ per cpu rounding down
4281 * to the number of ports, with a minimum of 1 per port.
4282 * A 2 port card in a 6 cpu system: 6 CIQs, 3 / port.
4283 * A 4 port card in a 6 cpu system: 4 CIQs, 1 / port.
4284 * A 4 port card in a 2 cpu system: 4 CIQs, 1 / port.
4286 s->rdmaciqs = min_t(int, MAX_RDMA_CIQS, num_online_cpus());
4287 s->rdmaciqs = (s->rdmaciqs / adap->params.nports) *
4288 adap->params.nports;
4289 s->rdmaciqs = max_t(int, s->rdmaciqs, adap->params.nports);
4292 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
4293 struct sge_eth_rxq *r = &s->ethrxq[i];
4295 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
4299 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
4300 s->ethtxq[i].q.size = 1024;
4302 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
4303 s->ctrlq[i].q.size = 512;
4305 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
4306 s->ofldtxq[i].q.size = 1024;
4308 for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) {
4309 struct sge_ofld_rxq *r = &s->ofldrxq[i];
4311 init_rspq(adap, &r->rspq, 5, 1, 1024, 64);
4312 r->rspq.uld = CXGB4_ULD_ISCSI;
4316 for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
4317 struct sge_ofld_rxq *r = &s->rdmarxq[i];
4319 init_rspq(adap, &r->rspq, 5, 1, 511, 64);
4320 r->rspq.uld = CXGB4_ULD_RDMA;
4324 ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids;
4325 if (ciq_size > SGE_MAX_IQ_SIZE) {
4326 CH_WARN(adap, "CIQ size too small for available IQs\n");
4327 ciq_size = SGE_MAX_IQ_SIZE;
4330 for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) {
4331 struct sge_ofld_rxq *r = &s->rdmaciq[i];
4333 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64);
4334 r->rspq.uld = CXGB4_ULD_RDMA;
4337 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
4338 init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64);
4342 * Reduce the number of Ethernet queues across all ports to at most n.
4343 * n provides at least one queue per port.
4345 static void reduce_ethqs(struct adapter *adap, int n)
4348 struct port_info *pi;
4350 while (n < adap->sge.ethqsets)
4351 for_each_port(adap, i) {
4352 pi = adap2pinfo(adap, i);
4353 if (pi->nqsets > 1) {
4355 adap->sge.ethqsets--;
4356 if (adap->sge.ethqsets <= n)
4362 for_each_port(adap, i) {
4363 pi = adap2pinfo(adap, i);
4369 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
4370 #define EXTRA_VECS 2
4372 static int enable_msix(struct adapter *adap)
4375 int i, want, need, allocated;
4376 struct sge *s = &adap->sge;
4377 unsigned int nchan = adap->params.nports;
4378 struct msix_entry *entries;
4380 entries = kmalloc(sizeof(*entries) * (MAX_INGQ + 1),
4385 for (i = 0; i < MAX_INGQ + 1; ++i)
4386 entries[i].entry = i;
4388 want = s->max_ethqsets + EXTRA_VECS;
4389 if (is_offload(adap)) {
4390 want += s->rdmaqs + s->rdmaciqs + s->ofldqsets;
4391 /* need nchan for each possible ULD */
4392 ofld_need = 3 * nchan;
4394 #ifdef CONFIG_CHELSIO_T4_DCB
4395 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
4398 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need;
4400 need = adap->params.nports + EXTRA_VECS + ofld_need;
4402 allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
4403 if (allocated < 0) {
4404 dev_info(adap->pdev_dev, "not enough MSI-X vectors left,"
4405 " not using MSI-X\n");
4410 /* Distribute available vectors to the various queue groups.
4411 * Every group gets its minimum requirement and NIC gets top
4412 * priority for leftovers.
4414 i = allocated - EXTRA_VECS - ofld_need;
4415 if (i < s->max_ethqsets) {
4416 s->max_ethqsets = i;
4417 if (i < s->ethqsets)
4418 reduce_ethqs(adap, i);
4420 if (is_offload(adap)) {
4421 if (allocated < want) {
4423 s->rdmaciqs = nchan;
4426 /* leftovers go to OFLD */
4427 i = allocated - EXTRA_VECS - s->max_ethqsets -
4428 s->rdmaqs - s->rdmaciqs;
4429 s->ofldqsets = (i / nchan) * nchan; /* round down */
4431 for (i = 0; i < allocated; ++i)
4432 adap->msix_info[i].vec = entries[i].vector;
4440 static int init_rss(struct adapter *adap)
4445 err = t4_init_rss_mode(adap, adap->mbox);
4449 for_each_port(adap, i) {
4450 struct port_info *pi = adap2pinfo(adap, i);
4452 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
4459 static void print_port_info(const struct net_device *dev)
4463 const char *spd = "";
4464 const struct port_info *pi = netdev_priv(dev);
4465 const struct adapter *adap = pi->adapter;
4467 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
4469 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
4471 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
4474 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
4475 bufp += sprintf(bufp, "100/");
4476 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
4477 bufp += sprintf(bufp, "1000/");
4478 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
4479 bufp += sprintf(bufp, "10G/");
4480 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
4481 bufp += sprintf(bufp, "40G/");
4484 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
4486 netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
4487 adap->params.vpd.id,
4488 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
4489 is_offload(adap) ? "R" : "", adap->params.pci.width, spd,
4490 (adap->flags & USING_MSIX) ? " MSI-X" :
4491 (adap->flags & USING_MSI) ? " MSI" : "");
4492 netdev_info(dev, "S/N: %s, P/N: %s\n",
4493 adap->params.vpd.sn, adap->params.vpd.pn);
4496 static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
4498 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
4502 * Free the following resources:
4503 * - memory used for tables
4506 * - resources FW is holding for us
4508 static void free_some_resources(struct adapter *adapter)
4512 t4_free_mem(adapter->l2t);
4513 t4_free_mem(adapter->tids.tid_tab);
4514 kfree(adapter->sge.egr_map);
4515 kfree(adapter->sge.ingr_map);
4516 kfree(adapter->sge.starving_fl);
4517 kfree(adapter->sge.txq_maperr);
4518 disable_msi(adapter);
4520 for_each_port(adapter, i)
4521 if (adapter->port[i]) {
4522 kfree(adap2pinfo(adapter, i)->rss);
4523 free_netdev(adapter->port[i]);
4525 if (adapter->flags & FW_OK)
4526 t4_fw_bye(adapter, adapter->fn);
4529 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
4530 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
4531 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
4532 #define SEGMENT_SIZE 128
4534 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
4536 int func, i, err, s_qpp, qpp, num_seg;
4537 struct port_info *pi;
4538 bool highdma = false;
4539 struct adapter *adapter = NULL;
4542 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
4544 err = pci_request_regions(pdev, KBUILD_MODNAME);
4546 /* Just info, some other driver may have claimed the device. */
4547 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
4551 err = pci_enable_device(pdev);
4553 dev_err(&pdev->dev, "cannot enable PCI device\n");
4554 goto out_release_regions;
4557 regs = pci_ioremap_bar(pdev, 0);
4559 dev_err(&pdev->dev, "cannot map device registers\n");
4561 goto out_disable_device;
4564 err = t4_wait_dev_ready(regs);
4566 goto out_unmap_bar0;
4568 /* We control everything through one PF */
4569 func = SOURCEPF_G(readl(regs + PL_WHOAMI_A));
4570 if (func != ent->driver_data) {
4572 pci_disable_device(pdev);
4573 pci_save_state(pdev); /* to restore SR-IOV later */
4577 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4579 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4581 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
4582 "coherent allocations\n");
4583 goto out_unmap_bar0;
4586 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4588 dev_err(&pdev->dev, "no usable DMA configuration\n");
4589 goto out_unmap_bar0;
4593 pci_enable_pcie_error_reporting(pdev);
4594 enable_pcie_relaxed_ordering(pdev);
4595 pci_set_master(pdev);
4596 pci_save_state(pdev);
4598 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
4601 goto out_unmap_bar0;
4604 adapter->workq = create_singlethread_workqueue("cxgb4");
4605 if (!adapter->workq) {
4607 goto out_free_adapter;
4610 /* PCI device has been enabled */
4611 adapter->flags |= DEV_ENABLED;
4613 adapter->regs = regs;
4614 adapter->pdev = pdev;
4615 adapter->pdev_dev = &pdev->dev;
4616 adapter->mbox = func;
4618 adapter->msg_enable = dflt_msg_enable;
4619 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
4621 spin_lock_init(&adapter->stats_lock);
4622 spin_lock_init(&adapter->tid_release_lock);
4623 spin_lock_init(&adapter->win0_lock);
4625 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
4626 INIT_WORK(&adapter->db_full_task, process_db_full);
4627 INIT_WORK(&adapter->db_drop_task, process_db_drop);
4629 err = t4_prep_adapter(adapter);
4631 goto out_free_adapter;
4634 if (!is_t4(adapter->params.chip)) {
4635 s_qpp = (QUEUESPERPAGEPF0_S +
4636 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
4638 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
4639 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
4640 num_seg = PAGE_SIZE / SEGMENT_SIZE;
4642 /* Each segment size is 128B. Write coalescing is enabled only
4643 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
4644 * queue is less no of segments that can be accommodated in
4647 if (qpp > num_seg) {
4649 "Incorrect number of egress queues per page\n");
4651 goto out_free_adapter;
4653 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
4654 pci_resource_len(pdev, 2));
4655 if (!adapter->bar2) {
4656 dev_err(&pdev->dev, "cannot map device bar2 region\n");
4658 goto out_free_adapter;
4662 setup_memwin(adapter);
4663 err = adap_init0(adapter);
4664 setup_memwin_rdma(adapter);
4668 for_each_port(adapter, i) {
4669 struct net_device *netdev;
4671 netdev = alloc_etherdev_mq(sizeof(struct port_info),
4678 SET_NETDEV_DEV(netdev, &pdev->dev);
4680 adapter->port[i] = netdev;
4681 pi = netdev_priv(netdev);
4682 pi->adapter = adapter;
4683 pi->xact_addr_filt = -1;
4685 netdev->irq = pdev->irq;
4687 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
4688 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4689 NETIF_F_RXCSUM | NETIF_F_RXHASH |
4690 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
4692 netdev->hw_features |= NETIF_F_HIGHDMA;
4693 netdev->features |= netdev->hw_features;
4694 netdev->vlan_features = netdev->features & VLAN_FEAT;
4696 netdev->priv_flags |= IFF_UNICAST_FLT;
4698 netdev->netdev_ops = &cxgb4_netdev_ops;
4699 #ifdef CONFIG_CHELSIO_T4_DCB
4700 netdev->dcbnl_ops = &cxgb4_dcb_ops;
4701 cxgb4_dcb_state_init(netdev);
4703 cxgb4_set_ethtool_ops(netdev);
4706 pci_set_drvdata(pdev, adapter);
4708 if (adapter->flags & FW_OK) {
4709 err = t4_port_init(adapter, func, func, 0);
4715 * Configure queues and allocate tables now, they can be needed as
4716 * soon as the first register_netdev completes.
4718 cfg_queues(adapter);
4720 adapter->l2t = t4_init_l2t();
4721 if (!adapter->l2t) {
4722 /* We tolerate a lack of L2T, giving up some functionality */
4723 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
4724 adapter->params.offload = 0;
4727 #if IS_ENABLED(CONFIG_IPV6)
4728 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
4729 adapter->clipt_end);
4730 if (!adapter->clipt) {
4731 /* We tolerate a lack of clip_table, giving up
4732 * some functionality
4734 dev_warn(&pdev->dev,
4735 "could not allocate Clip table, continuing\n");
4736 adapter->params.offload = 0;
4739 if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
4740 dev_warn(&pdev->dev, "could not allocate TID table, "
4742 adapter->params.offload = 0;
4745 /* See what interrupts we'll be using */
4746 if (msi > 1 && enable_msix(adapter) == 0)
4747 adapter->flags |= USING_MSIX;
4748 else if (msi > 0 && pci_enable_msi(pdev) == 0)
4749 adapter->flags |= USING_MSI;
4751 err = init_rss(adapter);
4756 * The card is now ready to go. If any errors occur during device
4757 * registration we do not fail the whole card but rather proceed only
4758 * with the ports we manage to register successfully. However we must
4759 * register at least one net device.
4761 for_each_port(adapter, i) {
4762 pi = adap2pinfo(adapter, i);
4763 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
4764 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
4766 err = register_netdev(adapter->port[i]);
4769 adapter->chan_map[pi->tx_chan] = i;
4770 print_port_info(adapter->port[i]);
4773 dev_err(&pdev->dev, "could not register any net devices\n");
4777 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
4781 if (cxgb4_debugfs_root) {
4782 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
4783 cxgb4_debugfs_root);
4784 setup_debugfs(adapter);
4787 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
4788 pdev->needs_freset = 1;
4790 if (is_offload(adapter))
4791 attach_ulds(adapter);
4794 #ifdef CONFIG_PCI_IOV
4795 if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
4796 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
4797 dev_info(&pdev->dev,
4798 "instantiated %u virtual functions\n",
4804 free_some_resources(adapter);
4806 if (!is_t4(adapter->params.chip))
4807 iounmap(adapter->bar2);
4810 destroy_workqueue(adapter->workq);
4816 pci_disable_pcie_error_reporting(pdev);
4817 pci_disable_device(pdev);
4818 out_release_regions:
4819 pci_release_regions(pdev);
4823 static void remove_one(struct pci_dev *pdev)
4825 struct adapter *adapter = pci_get_drvdata(pdev);
4827 #ifdef CONFIG_PCI_IOV
4828 pci_disable_sriov(pdev);
4835 /* Tear down per-adapter Work Queue first since it can contain
4836 * references to our adapter data structure.
4838 destroy_workqueue(adapter->workq);
4840 if (is_offload(adapter))
4841 detach_ulds(adapter);
4843 disable_interrupts(adapter);
4845 for_each_port(adapter, i)
4846 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
4847 unregister_netdev(adapter->port[i]);
4849 debugfs_remove_recursive(adapter->debugfs_root);
4851 /* If we allocated filters, free up state associated with any
4854 if (adapter->tids.ftid_tab) {
4855 struct filter_entry *f = &adapter->tids.ftid_tab[0];
4856 for (i = 0; i < (adapter->tids.nftids +
4857 adapter->tids.nsftids); i++, f++)
4859 clear_filter(adapter, f);
4862 if (adapter->flags & FULL_INIT_DONE)
4865 free_some_resources(adapter);
4866 #if IS_ENABLED(CONFIG_IPV6)
4867 t4_cleanup_clip_tbl(adapter);
4869 iounmap(adapter->regs);
4870 if (!is_t4(adapter->params.chip))
4871 iounmap(adapter->bar2);
4872 pci_disable_pcie_error_reporting(pdev);
4873 if ((adapter->flags & DEV_ENABLED)) {
4874 pci_disable_device(pdev);
4875 adapter->flags &= ~DEV_ENABLED;
4877 pci_release_regions(pdev);
4881 pci_release_regions(pdev);
4884 static struct pci_driver cxgb4_driver = {
4885 .name = KBUILD_MODNAME,
4886 .id_table = cxgb4_pci_tbl,
4888 .remove = remove_one,
4889 .shutdown = remove_one,
4890 .err_handler = &cxgb4_eeh,
4893 static int __init cxgb4_init_module(void)
4897 /* Debugfs support is optional, just warn if this fails */
4898 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
4899 if (!cxgb4_debugfs_root)
4900 pr_warn("could not create debugfs entry, continuing\n");
4902 ret = pci_register_driver(&cxgb4_driver);
4904 debugfs_remove(cxgb4_debugfs_root);
4906 #if IS_ENABLED(CONFIG_IPV6)
4907 if (!inet6addr_registered) {
4908 register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
4909 inet6addr_registered = true;
4916 static void __exit cxgb4_cleanup_module(void)
4918 #if IS_ENABLED(CONFIG_IPV6)
4919 if (inet6addr_registered) {
4920 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
4921 inet6addr_registered = false;
4924 pci_unregister_driver(&cxgb4_driver);
4925 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
4928 module_init(cxgb4_init_module);
4929 module_exit(cxgb4_cleanup_module);