drivers/net/ethernet/broadcom/bnxt/bnxt.h

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  * Copyright (c) 2016-2018 Broadcom Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #ifndef BNXT_H
  12 #define BNXT_H
  13
  14 #define DRV_MODULE_NAME         "bnxt_en"
  15
  16 /* DO NOT CHANGE DRV_VER_* defines
  17  * FIXME: Delete them
  18  */
  19 #define DRV_VER_MAJ     1
  20 #define DRV_VER_MIN     10
  21 #define DRV_VER_UPD     2
  22
  23 #include <linux/ethtool.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/rhashtable.h>
  26 #include <linux/crash_dump.h>
  27 #include <net/devlink.h>
  28 #include <net/dst_metadata.h>
  29 #include <net/xdp.h>
  30 #include <linux/dim.h>
  31 #ifdef CONFIG_TEE_BNXT_FW
  32 #include <linux/firmware/broadcom/tee_bnxt_fw.h>
  33 #endif
  34
  35 extern struct list_head bnxt_block_cb_list;
  36
  37 struct page_pool;
  38
  39 struct tx_bd {
  40         __le32 tx_bd_len_flags_type;
  41         #define TX_BD_TYPE                                      (0x3f << 0)
  42          #define TX_BD_TYPE_SHORT_TX_BD                          (0x00 << 0)
  43          #define TX_BD_TYPE_LONG_TX_BD                           (0x10 << 0)
  44         #define TX_BD_FLAGS_PACKET_END                          (1 << 6)
  45         #define TX_BD_FLAGS_NO_CMPL                             (1 << 7)
  46         #define TX_BD_FLAGS_BD_CNT                              (0x1f << 8)
  47          #define TX_BD_FLAGS_BD_CNT_SHIFT                        8
  48         #define TX_BD_FLAGS_LHINT                               (3 << 13)
  49          #define TX_BD_FLAGS_LHINT_SHIFT                         13
  50          #define TX_BD_FLAGS_LHINT_512_AND_SMALLER               (0 << 13)
  51          #define TX_BD_FLAGS_LHINT_512_TO_1023                   (1 << 13)
  52          #define TX_BD_FLAGS_LHINT_1024_TO_2047                  (2 << 13)
  53          #define TX_BD_FLAGS_LHINT_2048_AND_LARGER               (3 << 13)
  54         #define TX_BD_FLAGS_COAL_NOW                            (1 << 15)
  55         #define TX_BD_LEN                                       (0xffff << 16)
  56          #define TX_BD_LEN_SHIFT                                 16
  57
  58         u32 tx_bd_opaque;
  59         __le64 tx_bd_haddr;
  60 } __packed;
  61
  62 struct tx_bd_ext {
  63         __le32 tx_bd_hsize_lflags;
  64         #define TX_BD_FLAGS_TCP_UDP_CHKSUM                      (1 << 0)
  65         #define TX_BD_FLAGS_IP_CKSUM                            (1 << 1)
  66         #define TX_BD_FLAGS_NO_CRC                              (1 << 2)
  67         #define TX_BD_FLAGS_STAMP                               (1 << 3)
  68         #define TX_BD_FLAGS_T_IP_CHKSUM                         (1 << 4)
  69         #define TX_BD_FLAGS_LSO                                 (1 << 5)
  70         #define TX_BD_FLAGS_IPID_FMT                            (1 << 6)
  71         #define TX_BD_FLAGS_T_IPID                              (1 << 7)
  72         #define TX_BD_HSIZE                                     (0xff << 16)
  73          #define TX_BD_HSIZE_SHIFT                               16
  74
  75         __le32 tx_bd_mss;
  76         __le32 tx_bd_cfa_action;
  77         #define TX_BD_CFA_ACTION                                (0xffff << 16)
  78          #define TX_BD_CFA_ACTION_SHIFT                          16
  79
  80         __le32 tx_bd_cfa_meta;
  81         #define TX_BD_CFA_META_MASK                             0xfffffff
  82         #define TX_BD_CFA_META_VID_MASK                         0xfff
  83         #define TX_BD_CFA_META_PRI_MASK                         (0xf << 12)
  84          #define TX_BD_CFA_META_PRI_SHIFT                        12
  85         #define TX_BD_CFA_META_TPID_MASK                        (3 << 16)
  86          #define TX_BD_CFA_META_TPID_SHIFT                       16
  87         #define TX_BD_CFA_META_KEY                              (0xf << 28)
  88          #define TX_BD_CFA_META_KEY_SHIFT                        28
  89         #define TX_BD_CFA_META_KEY_VLAN                         (1 << 28)
  90 };
  91
  92 #define BNXT_TX_PTP_IS_SET(lflags) ((lflags) & cpu_to_le32(TX_BD_FLAGS_STAMP))
  93
  94 struct rx_bd {
  95         __le32 rx_bd_len_flags_type;
  96         #define RX_BD_TYPE                                      (0x3f << 0)
  97          #define RX_BD_TYPE_RX_PACKET_BD                         0x4
  98          #define RX_BD_TYPE_RX_BUFFER_BD                         0x5
  99          #define RX_BD_TYPE_RX_AGG_BD                            0x6
 100          #define RX_BD_TYPE_16B_BD_SIZE                          (0 << 4)
 101          #define RX_BD_TYPE_32B_BD_SIZE                          (1 << 4)
 102          #define RX_BD_TYPE_48B_BD_SIZE                          (2 << 4)
 103          #define RX_BD_TYPE_64B_BD_SIZE                          (3 << 4)
 104         #define RX_BD_FLAGS_SOP                                 (1 << 6)
 105         #define RX_BD_FLAGS_EOP                                 (1 << 7)
 106         #define RX_BD_FLAGS_BUFFERS                             (3 << 8)
 107          #define RX_BD_FLAGS_1_BUFFER_PACKET                     (0 << 8)
 108          #define RX_BD_FLAGS_2_BUFFER_PACKET                     (1 << 8)
 109          #define RX_BD_FLAGS_3_BUFFER_PACKET                     (2 << 8)
 110          #define RX_BD_FLAGS_4_BUFFER_PACKET                     (3 << 8)
 111         #define RX_BD_LEN                                       (0xffff << 16)
 112          #define RX_BD_LEN_SHIFT                                 16
 113
 114         u32 rx_bd_opaque;
 115         __le64 rx_bd_haddr;
 116 };
 117
 118 struct tx_cmp {
 119         __le32 tx_cmp_flags_type;
 120         #define CMP_TYPE                                        (0x3f << 0)
 121          #define CMP_TYPE_TX_L2_CMP                              0
 122          #define CMP_TYPE_RX_L2_CMP                              17
 123          #define CMP_TYPE_RX_AGG_CMP                             18
 124          #define CMP_TYPE_RX_L2_TPA_START_CMP                    19
 125          #define CMP_TYPE_RX_L2_TPA_END_CMP                      21
 126          #define CMP_TYPE_RX_TPA_AGG_CMP                         22
 127          #define CMP_TYPE_STATUS_CMP                             32
 128          #define CMP_TYPE_REMOTE_DRIVER_REQ                      34
 129          #define CMP_TYPE_REMOTE_DRIVER_RESP                     36
 130          #define CMP_TYPE_ERROR_STATUS                           48
 131          #define CMPL_BASE_TYPE_STAT_EJECT                       0x1aUL
 132          #define CMPL_BASE_TYPE_HWRM_DONE                        0x20UL
 133          #define CMPL_BASE_TYPE_HWRM_FWD_REQ                     0x22UL
 134          #define CMPL_BASE_TYPE_HWRM_FWD_RESP                    0x24UL
 135          #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT                 0x2eUL
 136
 137         #define TX_CMP_FLAGS_ERROR                              (1 << 6)
 138         #define TX_CMP_FLAGS_PUSH                               (1 << 7)
 139
 140         u32 tx_cmp_opaque;
 141         __le32 tx_cmp_errors_v;
 142         #define TX_CMP_V                                        (1 << 0)
 143         #define TX_CMP_ERRORS_BUFFER_ERROR                      (7 << 1)
 144          #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR             0
 145          #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT           2
 146          #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG         4
 147          #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS          5
 148          #define TX_CMP_ERRORS_ZERO_LENGTH_PKT                   (1 << 4)
 149          #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN                  (1 << 5)
 150          #define TX_CMP_ERRORS_DMA_ERROR                         (1 << 6)
 151          #define TX_CMP_ERRORS_HINT_TOO_SHORT                    (1 << 7)
 152
 153         __le32 tx_cmp_unsed_3;
 154 };
 155
 156 struct rx_cmp {
 157         __le32 rx_cmp_len_flags_type;
 158         #define RX_CMP_CMP_TYPE                                 (0x3f << 0)
 159         #define RX_CMP_FLAGS_ERROR                              (1 << 6)
 160         #define RX_CMP_FLAGS_PLACEMENT                          (7 << 7)
 161         #define RX_CMP_FLAGS_RSS_VALID                          (1 << 10)
 162         #define RX_CMP_FLAGS_UNUSED                             (1 << 11)
 163          #define RX_CMP_FLAGS_ITYPES_SHIFT                       12
 164          #define RX_CMP_FLAGS_ITYPES_MASK                        0xf000
 165          #define RX_CMP_FLAGS_ITYPE_UNKNOWN                      (0 << 12)
 166          #define RX_CMP_FLAGS_ITYPE_IP                           (1 << 12)
 167          #define RX_CMP_FLAGS_ITYPE_TCP                          (2 << 12)
 168          #define RX_CMP_FLAGS_ITYPE_UDP                          (3 << 12)
 169          #define RX_CMP_FLAGS_ITYPE_FCOE                         (4 << 12)
 170          #define RX_CMP_FLAGS_ITYPE_ROCE                         (5 << 12)
 171          #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS                    (8 << 12)
 172          #define RX_CMP_FLAGS_ITYPE_PTP_W_TS                     (9 << 12)
 173         #define RX_CMP_LEN                                      (0xffff << 16)
 174          #define RX_CMP_LEN_SHIFT                                16
 175
 176         u32 rx_cmp_opaque;
 177         __le32 rx_cmp_misc_v1;
 178         #define RX_CMP_V1                                       (1 << 0)
 179         #define RX_CMP_AGG_BUFS                                 (0x1f << 1)
 180          #define RX_CMP_AGG_BUFS_SHIFT                           1
 181         #define RX_CMP_RSS_HASH_TYPE                            (0x7f << 9)
 182          #define RX_CMP_RSS_HASH_TYPE_SHIFT                      9
 183         #define RX_CMP_PAYLOAD_OFFSET                           (0xff << 16)
 184          #define RX_CMP_PAYLOAD_OFFSET_SHIFT                     16
 185
 186         __le32 rx_cmp_rss_hash;
 187 };
 188
 189 #define RX_CMP_HASH_VALID(rxcmp)                                \
 190         ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
 191
 192 #define RSS_PROFILE_ID_MASK     0x1f
 193
 194 #define RX_CMP_HASH_TYPE(rxcmp)                                 \
 195         (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
 196           RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
 197
 198 struct rx_cmp_ext {
 199         __le32 rx_cmp_flags2;
 200         #define RX_CMP_FLAGS2_IP_CS_CALC                        0x1
 201         #define RX_CMP_FLAGS2_L4_CS_CALC                        (0x1 << 1)
 202         #define RX_CMP_FLAGS2_T_IP_CS_CALC                      (0x1 << 2)
 203         #define RX_CMP_FLAGS2_T_L4_CS_CALC                      (0x1 << 3)
 204         #define RX_CMP_FLAGS2_META_FORMAT_VLAN                  (0x1 << 4)
 205         __le32 rx_cmp_meta_data;
 206         #define RX_CMP_FLAGS2_METADATA_TCI_MASK                 0xffff
 207         #define RX_CMP_FLAGS2_METADATA_VID_MASK                 0xfff
 208         #define RX_CMP_FLAGS2_METADATA_TPID_MASK                0xffff0000
 209          #define RX_CMP_FLAGS2_METADATA_TPID_SFT                 16
 210         __le32 rx_cmp_cfa_code_errors_v2;
 211         #define RX_CMP_V                                        (1 << 0)
 212         #define RX_CMPL_ERRORS_MASK                             (0x7fff << 1)
 213          #define RX_CMPL_ERRORS_SFT                              1
 214         #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK                (0x7 << 1)
 215          #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER           (0x0 << 1)
 216          #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT         (0x1 << 1)
 217          #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP         (0x2 << 1)
 218          #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT          (0x3 << 1)
 219         #define RX_CMPL_ERRORS_IP_CS_ERROR                      (0x1 << 4)
 220         #define RX_CMPL_ERRORS_L4_CS_ERROR                      (0x1 << 5)
 221         #define RX_CMPL_ERRORS_T_IP_CS_ERROR                    (0x1 << 6)
 222         #define RX_CMPL_ERRORS_T_L4_CS_ERROR                    (0x1 << 7)
 223         #define RX_CMPL_ERRORS_CRC_ERROR                        (0x1 << 8)
 224         #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK                 (0x7 << 9)
 225          #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR             (0x0 << 9)
 226          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION     (0x1 << 9)
 227          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN     (0x2 << 9)
 228          #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR   (0x3 << 9)
 229          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR     (0x4 << 9)
 230          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR    (0x5 << 9)
 231          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL         (0x6 << 9)
 232         #define RX_CMPL_ERRORS_PKT_ERROR_MASK                   (0xf << 12)
 233          #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR               (0x0 << 12)
 234          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION         (0x1 << 12)
 235          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN         (0x2 << 12)
 236          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL             (0x3 << 12)
 237          #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR         (0x4 << 12)
 238          #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR        (0x5 << 12)
 239          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN         (0x6 << 12)
 240          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
 241          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN         (0x8 << 12)
 242
 243         #define RX_CMPL_CFA_CODE_MASK                           (0xffff << 16)
 244          #define RX_CMPL_CFA_CODE_SFT                            16
 245
 246         __le32 rx_cmp_timestamp;
 247 };
 248
 249 #define RX_CMP_L2_ERRORS                                                \
 250         cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
 251
 252 #define RX_CMP_L4_CS_BITS                                               \
 253         (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
 254
 255 #define RX_CMP_L4_CS_ERR_BITS                                           \
 256         (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
 257
 258 #define RX_CMP_L4_CS_OK(rxcmp1)                                         \
 259             (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) &&           \
 260              !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
 261
 262 #define RX_CMP_ENCAP(rxcmp1)                                            \
 263             ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) &                    \
 264              RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
 265
 266 #define RX_CMP_CFA_CODE(rxcmpl1)                                        \
 267         ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) &           \
 268           RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
 269
 270 struct rx_agg_cmp {
 271         __le32 rx_agg_cmp_len_flags_type;
 272         #define RX_AGG_CMP_TYPE                                 (0x3f << 0)
 273         #define RX_AGG_CMP_LEN                                  (0xffff << 16)
 274          #define RX_AGG_CMP_LEN_SHIFT                            16
 275         u32 rx_agg_cmp_opaque;
 276         __le32 rx_agg_cmp_v;
 277         #define RX_AGG_CMP_V                                    (1 << 0)
 278         #define RX_AGG_CMP_AGG_ID                               (0xffff << 16)
 279          #define RX_AGG_CMP_AGG_ID_SHIFT                         16
 280         __le32 rx_agg_cmp_unused;
 281 };
 282
 283 #define TPA_AGG_AGG_ID(rx_agg)                          \
 284         ((le32_to_cpu((rx_agg)->rx_agg_cmp_v) &         \
 285          RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT)
 286
 287 struct rx_tpa_start_cmp {
 288         __le32 rx_tpa_start_cmp_len_flags_type;
 289         #define RX_TPA_START_CMP_TYPE                           (0x3f << 0)
 290         #define RX_TPA_START_CMP_FLAGS                          (0x3ff << 6)
 291          #define RX_TPA_START_CMP_FLAGS_SHIFT                    6
 292         #define RX_TPA_START_CMP_FLAGS_ERROR                    (0x1 << 6)
 293         #define RX_TPA_START_CMP_FLAGS_PLACEMENT                (0x7 << 7)
 294          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT          7
 295          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO          (0x1 << 7)
 296          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS            (0x2 << 7)
 297          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO      (0x5 << 7)
 298          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS        (0x6 << 7)
 299         #define RX_TPA_START_CMP_FLAGS_RSS_VALID                (0x1 << 10)
 300         #define RX_TPA_START_CMP_FLAGS_TIMESTAMP                (0x1 << 11)
 301         #define RX_TPA_START_CMP_FLAGS_ITYPES                   (0xf << 12)
 302          #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT             12
 303          #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP                (0x2 << 12)
 304         #define RX_TPA_START_CMP_LEN                            (0xffff << 16)
 305          #define RX_TPA_START_CMP_LEN_SHIFT                      16
 306
 307         u32 rx_tpa_start_cmp_opaque;
 308         __le32 rx_tpa_start_cmp_misc_v1;
 309         #define RX_TPA_START_CMP_V1                             (0x1 << 0)
 310         #define RX_TPA_START_CMP_RSS_HASH_TYPE                  (0x7f << 9)
 311          #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT            9
 312         #define RX_TPA_START_CMP_AGG_ID                         (0x7f << 25)
 313          #define RX_TPA_START_CMP_AGG_ID_SHIFT                   25
 314         #define RX_TPA_START_CMP_AGG_ID_P5                      (0xffff << 16)
 315          #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5                16
 316
 317         __le32 rx_tpa_start_cmp_rss_hash;
 318 };
 319
 320 #define TPA_START_HASH_VALID(rx_tpa_start)                              \
 321         ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &              \
 322          cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
 323
 324 #define TPA_START_HASH_TYPE(rx_tpa_start)                               \
 325         (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &      \
 326            RX_TPA_START_CMP_RSS_HASH_TYPE) >>                           \
 327           RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
 328
 329 #define TPA_START_AGG_ID(rx_tpa_start)                                  \
 330         ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &       \
 331          RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
 332
 333 #define TPA_START_AGG_ID_P5(rx_tpa_start)                               \
 334         ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &       \
 335          RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5)
 336
 337 #define TPA_START_ERROR(rx_tpa_start)                                   \
 338         ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &              \
 339          cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))
 340
 341 struct rx_tpa_start_cmp_ext {
 342         __le32 rx_tpa_start_cmp_flags2;
 343         #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC              (0x1 << 0)
 344         #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC              (0x1 << 1)
 345         #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC            (0x1 << 2)
 346         #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC            (0x1 << 3)
 347         #define RX_TPA_START_CMP_FLAGS2_IP_TYPE                 (0x1 << 8)
 348         #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID         (0x1 << 9)
 349         #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT         (0x3 << 10)
 350          #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT   10
 351         #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL               (0xffff << 16)
 352          #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT         16
 353
 354         __le32 rx_tpa_start_cmp_metadata;
 355         __le32 rx_tpa_start_cmp_cfa_code_v2;
 356         #define RX_TPA_START_CMP_V2                             (0x1 << 0)
 357         #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK       (0x7 << 1)
 358          #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT      1
 359          #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER  (0x0 << 1)
 360          #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
 361          #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH      (0x5 << 1)
 362         #define RX_TPA_START_CMP_CFA_CODE                       (0xffff << 16)
 363          #define RX_TPA_START_CMPL_CFA_CODE_SHIFT                16
 364         __le32 rx_tpa_start_cmp_hdr_info;
 365 };
 366
 367 #define TPA_START_CFA_CODE(rx_tpa_start)                                \
 368         ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &   \
 369          RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
 370
 371 #define TPA_START_IS_IPV6(rx_tpa_start)                         \
 372         (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 &           \
 373             cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
 374
 375 #define TPA_START_ERROR_CODE(rx_tpa_start)                              \
 376         ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &   \
 377           RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >>                 \
 378          RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)
 379
 380 struct rx_tpa_end_cmp {
 381         __le32 rx_tpa_end_cmp_len_flags_type;
 382         #define RX_TPA_END_CMP_TYPE                             (0x3f << 0)
 383         #define RX_TPA_END_CMP_FLAGS                            (0x3ff << 6)
 384          #define RX_TPA_END_CMP_FLAGS_SHIFT                      6
 385         #define RX_TPA_END_CMP_FLAGS_PLACEMENT                  (0x7 << 7)
 386          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT            7
 387          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO            (0x1 << 7)
 388          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS              (0x2 << 7)
 389          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO        (0x5 << 7)
 390          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS          (0x6 << 7)
 391         #define RX_TPA_END_CMP_FLAGS_RSS_VALID                  (0x1 << 10)
 392         #define RX_TPA_END_CMP_FLAGS_ITYPES                     (0xf << 12)
 393          #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT               12
 394          #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP                  (0x2 << 12)
 395         #define RX_TPA_END_CMP_LEN                              (0xffff << 16)
 396          #define RX_TPA_END_CMP_LEN_SHIFT                        16
 397
 398         u32 rx_tpa_end_cmp_opaque;
 399         __le32 rx_tpa_end_cmp_misc_v1;
 400         #define RX_TPA_END_CMP_V1                               (0x1 << 0)
 401         #define RX_TPA_END_CMP_AGG_BUFS                         (0x3f << 1)
 402          #define RX_TPA_END_CMP_AGG_BUFS_SHIFT                   1
 403         #define RX_TPA_END_CMP_TPA_SEGS                         (0xff << 8)
 404          #define RX_TPA_END_CMP_TPA_SEGS_SHIFT                   8
 405         #define RX_TPA_END_CMP_PAYLOAD_OFFSET                   (0xff << 16)
 406          #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT             16
 407         #define RX_TPA_END_CMP_AGG_ID                           (0x7f << 25)
 408          #define RX_TPA_END_CMP_AGG_ID_SHIFT                     25
 409         #define RX_TPA_END_CMP_AGG_ID_P5                        (0xffff << 16)
 410          #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5                  16
 411
 412         __le32 rx_tpa_end_cmp_tsdelta;
 413         #define RX_TPA_END_GRO_TS                               (0x1 << 31)
 414 };
 415
 416 #define TPA_END_AGG_ID(rx_tpa_end)                                      \
 417         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 418          RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
 419
 420 #define TPA_END_AGG_ID_P5(rx_tpa_end)                                   \
 421         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 422          RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5)
 423
 424 #define TPA_END_PAYLOAD_OFF(rx_tpa_end)                                 \
 425         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 426          RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT)
 427
 428 #define TPA_END_AGG_BUFS(rx_tpa_end)                                    \
 429         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 430          RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT)
 431
 432 #define TPA_END_TPA_SEGS(rx_tpa_end)                                    \
 433         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 434          RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
 435
 436 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO                          \
 437         cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO &          \
 438                     RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
 439
 440 #define TPA_END_GRO(rx_tpa_end)                                         \
 441         ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type &                  \
 442          RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
 443
 444 #define TPA_END_GRO_TS(rx_tpa_end)                                      \
 445         (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta &                      \
 446             cpu_to_le32(RX_TPA_END_GRO_TS)))
 447
 448 struct rx_tpa_end_cmp_ext {
 449         __le32 rx_tpa_end_cmp_dup_acks;
 450         #define RX_TPA_END_CMP_TPA_DUP_ACKS                     (0xf << 0)
 451         #define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5                (0xff << 16)
 452          #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5          16
 453         #define RX_TPA_END_CMP_AGG_BUFS_P5                      (0xff << 24)
 454          #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5                24
 455
 456         __le32 rx_tpa_end_cmp_seg_len;
 457         #define RX_TPA_END_CMP_TPA_SEG_LEN                      (0xffff << 0)
 458
 459         __le32 rx_tpa_end_cmp_errors_v2;
 460         #define RX_TPA_END_CMP_V2                               (0x1 << 0)
 461         #define RX_TPA_END_CMP_ERRORS                           (0x3 << 1)
 462         #define RX_TPA_END_CMP_ERRORS_P5                        (0x7 << 1)
 463         #define RX_TPA_END_CMPL_ERRORS_SHIFT                     1
 464          #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER    (0x0 << 1)
 465          #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP  (0x2 << 1)
 466          #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT   (0x3 << 1)
 467          #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR    (0x4 << 1)
 468          #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH        (0x5 << 1)
 469
 470         u32 rx_tpa_end_cmp_start_opaque;
 471 };
 472
 473 #define TPA_END_ERRORS(rx_tpa_end_ext)                                  \
 474         ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 &                   \
 475          cpu_to_le32(RX_TPA_END_CMP_ERRORS))
 476
 477 #define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext)                          \
 478         ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) &      \
 479          RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >>                           \
 480         RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5)
 481
 482 #define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext)                             \
 483         ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) &      \
 484          RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5)
 485
 486 #define EVENT_DATA1_RESET_NOTIFY_FATAL(data1)                           \
 487         (((data1) &                                                     \
 488           ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
 489          ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL)
 490
 491 #define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1)                         \
 492         !!((data1) &                                                    \
 493            ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC)
 494
 495 #define EVENT_DATA1_RECOVERY_ENABLED(data1)                             \
 496         !!((data1) &                                                    \
 497            ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED)
 498
 499 struct nqe_cn {
 500         __le16  type;
 501         #define NQ_CN_TYPE_MASK           0x3fUL
 502         #define NQ_CN_TYPE_SFT            0
 503         #define NQ_CN_TYPE_CQ_NOTIFICATION  0x30UL
 504         #define NQ_CN_TYPE_LAST            NQ_CN_TYPE_CQ_NOTIFICATION
 505         __le16  reserved16;
 506         __le32  cq_handle_low;
 507         __le32  v;
 508         #define NQ_CN_V     0x1UL
 509         __le32  cq_handle_high;
 510 };
 511
 512 #define DB_IDX_MASK                                             0xffffff
 513 #define DB_IDX_VALID                                            (0x1 << 26)
 514 #define DB_IRQ_DIS                                              (0x1 << 27)
 515 #define DB_KEY_TX                                               (0x0 << 28)
 516 #define DB_KEY_RX                                               (0x1 << 28)
 517 #define DB_KEY_CP                                               (0x2 << 28)
 518 #define DB_KEY_ST                                               (0x3 << 28)
 519 #define DB_KEY_TX_PUSH                                          (0x4 << 28)
 520 #define DB_LONG_TX_PUSH                                         (0x2 << 24)
 521
 522 #define BNXT_MIN_ROCE_CP_RINGS  2
 523 #define BNXT_MIN_ROCE_STAT_CTXS 1
 524
 525 /* 64-bit doorbell */
 526 #define DBR_INDEX_MASK                                  0x0000000000ffffffULL
 527 #define DBR_XID_MASK                                    0x000fffff00000000ULL
 528 #define DBR_XID_SFT                                     32
 529 #define DBR_PATH_L2                                     (0x1ULL << 56)
 530 #define DBR_TYPE_SQ                                     (0x0ULL << 60)
 531 #define DBR_TYPE_RQ                                     (0x1ULL << 60)
 532 #define DBR_TYPE_SRQ                                    (0x2ULL << 60)
 533 #define DBR_TYPE_SRQ_ARM                                (0x3ULL << 60)
 534 #define DBR_TYPE_CQ                                     (0x4ULL << 60)
 535 #define DBR_TYPE_CQ_ARMSE                               (0x5ULL << 60)
 536 #define DBR_TYPE_CQ_ARMALL                              (0x6ULL << 60)
 537 #define DBR_TYPE_CQ_ARMENA                              (0x7ULL << 60)
 538 #define DBR_TYPE_SRQ_ARMENA                             (0x8ULL << 60)
 539 #define DBR_TYPE_CQ_CUTOFF_ACK                          (0x9ULL << 60)
 540 #define DBR_TYPE_NQ                                     (0xaULL << 60)
 541 #define DBR_TYPE_NQ_ARM                                 (0xbULL << 60)
 542 #define DBR_TYPE_NULL                                   (0xfULL << 60)
 543
 544 #define DB_PF_OFFSET_P5                                 0x10000
 545 #define DB_VF_OFFSET_P5                                 0x4000
 546
 547 #define INVALID_HW_RING_ID      ((u16)-1)
 548
 549 /* The hardware supports certain page sizes.  Use the supported page sizes
 550  * to allocate the rings.
 551  */
 552 #if (PAGE_SHIFT < 12)
 553 #define BNXT_PAGE_SHIFT 12
 554 #elif (PAGE_SHIFT <= 13)
 555 #define BNXT_PAGE_SHIFT PAGE_SHIFT
 556 #elif (PAGE_SHIFT < 16)
 557 #define BNXT_PAGE_SHIFT 13
 558 #else
 559 #define BNXT_PAGE_SHIFT 16
 560 #endif
 561
 562 #define BNXT_PAGE_SIZE  (1 << BNXT_PAGE_SHIFT)
 563
 564 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
 565 #if (PAGE_SHIFT > 15)
 566 #define BNXT_RX_PAGE_SHIFT 15
 567 #else
 568 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
 569 #endif
 570
 571 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
 572
 573 #define BNXT_MAX_MTU            9500
 574 #define BNXT_MAX_PAGE_MODE_MTU  \
 575         ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN -       \
 576          XDP_PACKET_HEADROOM)
 577
 578 #define BNXT_MIN_PKT_SIZE       52
 579
 580 #define BNXT_DEFAULT_RX_RING_SIZE       511
 581 #define BNXT_DEFAULT_TX_RING_SIZE       511
 582
 583 #define MAX_TPA         64
 584 #define MAX_TPA_P5      256
 585 #define MAX_TPA_P5_MASK (MAX_TPA_P5 - 1)
 586 #define MAX_TPA_SEGS_P5 0x3f
 587
 588 #if (BNXT_PAGE_SHIFT == 16)
 589 #define MAX_RX_PAGES    1
 590 #define MAX_RX_AGG_PAGES        4
 591 #define MAX_TX_PAGES    1
 592 #define MAX_CP_PAGES    8
 593 #else
 594 #define MAX_RX_PAGES    8
 595 #define MAX_RX_AGG_PAGES        32
 596 #define MAX_TX_PAGES    8
 597 #define MAX_CP_PAGES    64
 598 #endif
 599
 600 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
 601 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
 602 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
 603
 604 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
 605 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
 606
 607 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
 608
 609 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
 610 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
 611
 612 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
 613
 614 #define BNXT_MAX_RX_DESC_CNT            (RX_DESC_CNT * MAX_RX_PAGES - 1)
 615 #define BNXT_MAX_RX_JUM_DESC_CNT        (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
 616 #define BNXT_MAX_TX_DESC_CNT            (TX_DESC_CNT * MAX_TX_PAGES - 1)
 617
 618 #define RX_RING(x)      (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
 619 #define RX_IDX(x)       ((x) & (RX_DESC_CNT - 1))
 620
 621 #define TX_RING(x)      (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
 622 #define TX_IDX(x)       ((x) & (TX_DESC_CNT - 1))
 623
 624 #define CP_RING(x)      (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
 625 #define CP_IDX(x)       ((x) & (CP_DESC_CNT - 1))
 626
 627 #define TX_CMP_VALID(txcmp, raw_cons)                                   \
 628         (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) ==        \
 629          !((raw_cons) & bp->cp_bit))
 630
 631 #define RX_CMP_VALID(rxcmp1, raw_cons)                                  \
 632         (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
 633          !((raw_cons) & bp->cp_bit))
 634
 635 #define RX_AGG_CMP_VALID(agg, raw_cons)                         \
 636         (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
 637          !((raw_cons) & bp->cp_bit))
 638
 639 #define NQ_CMP_VALID(nqcmp, raw_cons)                           \
 640         (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
 641
 642 #define TX_CMP_TYPE(txcmp)                                      \
 643         (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
 644
 645 #define RX_CMP_TYPE(rxcmp)                                      \
 646         (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
 647
 648 #define NEXT_RX(idx)            (((idx) + 1) & bp->rx_ring_mask)
 649
 650 #define NEXT_RX_AGG(idx)        (((idx) + 1) & bp->rx_agg_ring_mask)
 651
 652 #define NEXT_TX(idx)            (((idx) + 1) & bp->tx_ring_mask)
 653
 654 #define ADV_RAW_CMP(idx, n)     ((idx) + (n))
 655 #define NEXT_RAW_CMP(idx)       ADV_RAW_CMP(idx, 1)
 656 #define RING_CMP(idx)           ((idx) & bp->cp_ring_mask)
 657 #define NEXT_CMP(idx)           RING_CMP(ADV_RAW_CMP(idx, 1))
 658
 659 #define BNXT_HWRM_MAX_REQ_LEN           (bp->hwrm_max_req_len)
 660 #define BNXT_HWRM_SHORT_REQ_LEN         sizeof(struct hwrm_short_input)
 661 #define DFLT_HWRM_CMD_TIMEOUT           500
 662 #define HWRM_CMD_MAX_TIMEOUT            40000
 663 #define SHORT_HWRM_CMD_TIMEOUT          20
 664 #define HWRM_CMD_TIMEOUT                (bp->hwrm_cmd_timeout)
 665 #define HWRM_RESET_TIMEOUT              ((HWRM_CMD_TIMEOUT) * 4)
 666 #define HWRM_COREDUMP_TIMEOUT           ((HWRM_CMD_TIMEOUT) * 12)
 667 #define BNXT_HWRM_REQ_MAX_SIZE          128
 668 #define BNXT_HWRM_REQS_PER_PAGE         (BNXT_PAGE_SIZE /       \
 669                                          BNXT_HWRM_REQ_MAX_SIZE)
 670 #define HWRM_SHORT_MIN_TIMEOUT          3
 671 #define HWRM_SHORT_MAX_TIMEOUT          10
 672 #define HWRM_SHORT_TIMEOUT_COUNTER      5
 673
 674 #define HWRM_MIN_TIMEOUT                25
 675 #define HWRM_MAX_TIMEOUT                40
 676
 677 #define HWRM_WAIT_MUST_ABORT(bp, req)                                   \
 678         (le16_to_cpu((req)->req_type) != HWRM_VER_GET &&                \
 679          !bnxt_is_fw_healthy(bp))
 680
 681 #define HWRM_TOTAL_TIMEOUT(n)   (((n) <= HWRM_SHORT_TIMEOUT_COUNTER) ?  \
 682         ((n) * HWRM_SHORT_MIN_TIMEOUT) :                                \
 683         (HWRM_SHORT_TIMEOUT_COUNTER * HWRM_SHORT_MIN_TIMEOUT +          \
 684          ((n) - HWRM_SHORT_TIMEOUT_COUNTER) * HWRM_MIN_TIMEOUT))
 685
 686 #define HWRM_VALID_BIT_DELAY_USEC       150
 687
 688 #define BNXT_HWRM_CHNL_CHIMP    0
 689 #define BNXT_HWRM_CHNL_KONG     1
 690
 691 #define BNXT_RX_EVENT           1
 692 #define BNXT_AGG_EVENT          2
 693 #define BNXT_TX_EVENT           4
 694 #define BNXT_REDIRECT_EVENT     8
 695
 696 struct bnxt_sw_tx_bd {
 697         union {
 698                 struct sk_buff          *skb;
 699                 struct xdp_frame        *xdpf;
 700         };
 701         DEFINE_DMA_UNMAP_ADDR(mapping);
 702         DEFINE_DMA_UNMAP_LEN(len);
 703         u8                      is_gso;
 704         u8                      is_push;
 705         u8                      action;
 706         union {
 707                 unsigned short          nr_frags;
 708                 u16                     rx_prod;
 709         };
 710 };
 711
 712 struct bnxt_sw_rx_bd {
 713         void                    *data;
 714         u8                      *data_ptr;
 715         dma_addr_t              mapping;
 716 };
 717
 718 struct bnxt_sw_rx_agg_bd {
 719         struct page             *page;
 720         unsigned int            offset;
 721         dma_addr_t              mapping;
 722 };
 723
 724 struct bnxt_mem_init {
 725         u8      init_val;
 726         u16     offset;
 727 #define BNXT_MEM_INVALID_OFFSET 0xffff
 728         u16     size;
 729 };
 730
 731 struct bnxt_ring_mem_info {
 732         int                     nr_pages;
 733         int                     page_size;
 734         u16                     flags;
 735 #define BNXT_RMEM_VALID_PTE_FLAG        1
 736 #define BNXT_RMEM_RING_PTE_FLAG         2
 737 #define BNXT_RMEM_USE_FULL_PAGE_FLAG    4
 738
 739         u16                     depth;
 740         struct bnxt_mem_init    *mem_init;
 741
 742         void                    **pg_arr;
 743         dma_addr_t              *dma_arr;
 744
 745         __le64                  *pg_tbl;
 746         dma_addr_t              pg_tbl_map;
 747
 748         int                     vmem_size;
 749         void                    **vmem;
 750 };
 751
 752 struct bnxt_ring_struct {
 753         struct bnxt_ring_mem_info       ring_mem;
 754
 755         u16                     fw_ring_id; /* Ring id filled by Chimp FW */
 756         union {
 757                 u16             grp_idx;
 758                 u16             map_idx; /* Used by cmpl rings */
 759         };
 760         u32                     handle;
 761         u8                      queue_id;
 762 };
 763
 764 struct tx_push_bd {
 765         __le32                  doorbell;
 766         __le32                  tx_bd_len_flags_type;
 767         u32                     tx_bd_opaque;
 768         struct tx_bd_ext        txbd2;
 769 };
 770
 771 struct tx_push_buffer {
 772         struct tx_push_bd       push_bd;
 773         u32                     data[25];
 774 };
 775
 776 struct bnxt_db_info {
 777         void __iomem            *doorbell;
 778         union {
 779                 u64             db_key64;
 780                 u32             db_key32;
 781         };
 782 };
 783
 784 struct bnxt_tx_ring_info {
 785         struct bnxt_napi        *bnapi;
 786         u16                     tx_prod;
 787         u16                     tx_cons;
 788         u16                     txq_index;
 789         u8                      kick_pending;
 790         struct bnxt_db_info     tx_db;
 791
 792         struct tx_bd            *tx_desc_ring[MAX_TX_PAGES];
 793         struct bnxt_sw_tx_bd    *tx_buf_ring;
 794
 795         dma_addr_t              tx_desc_mapping[MAX_TX_PAGES];
 796
 797         struct tx_push_buffer   *tx_push;
 798         dma_addr_t              tx_push_mapping;
 799         __le64                  data_mapping;
 800
 801 #define BNXT_DEV_STATE_CLOSING  0x1
 802         u32                     dev_state;
 803
 804         struct bnxt_ring_struct tx_ring_struct;
 805 };
 806
 807 #define BNXT_LEGACY_COAL_CMPL_PARAMS                                    \
 808         (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN |           \
 809          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX |           \
 810          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET |               \
 811          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE |                 \
 812          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR |         \
 813          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
 814          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR |         \
 815          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
 816          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
 817
 818 #define BNXT_COAL_CMPL_ENABLES                                          \
 819         (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
 820          RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
 821          RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
 822          RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
 823
 824 #define BNXT_COAL_CMPL_MIN_TMR_ENABLE                                   \
 825         RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
 826
 827 #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE                       \
 828         RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
 829
 830 struct bnxt_coal_cap {
 831         u32                     cmpl_params;
 832         u32                     nq_params;
 833         u16                     num_cmpl_dma_aggr_max;
 834         u16                     num_cmpl_dma_aggr_during_int_max;
 835         u16                     cmpl_aggr_dma_tmr_max;
 836         u16                     cmpl_aggr_dma_tmr_during_int_max;
 837         u16                     int_lat_tmr_min_max;
 838         u16                     int_lat_tmr_max_max;
 839         u16                     num_cmpl_aggr_int_max;
 840         u16                     timer_units;
 841 };
 842
 843 struct bnxt_coal {
 844         u16                     coal_ticks;
 845         u16                     coal_ticks_irq;
 846         u16                     coal_bufs;
 847         u16                     coal_bufs_irq;
 848                         /* RING_IDLE enabled when coal ticks < idle_thresh  */
 849         u16                     idle_thresh;
 850         u8                      bufs_per_record;
 851         u8                      budget;
 852 };
 853
 854 struct bnxt_tpa_info {
 855         void                    *data;
 856         u8                      *data_ptr;
 857         dma_addr_t              mapping;
 858         u16                     len;
 859         unsigned short          gso_type;
 860         u32                     flags2;
 861         u32                     metadata;
 862         enum pkt_hash_types     hash_type;
 863         u32                     rss_hash;
 864         u32                     hdr_info;
 865
 866 #define BNXT_TPA_L4_SIZE(hdr_info)      \
 867         (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
 868
 869 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \
 870         (((hdr_info) >> 18) & 0x1ff)
 871
 872 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \
 873         (((hdr_info) >> 9) & 0x1ff)
 874
 875 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
 876         ((hdr_info) & 0x1ff)
 877
 878         u16                     cfa_code; /* cfa_code in TPA start compl */
 879         u8                      agg_count;
 880         struct rx_agg_cmp       *agg_arr;
 881 };
 882
 883 #define BNXT_AGG_IDX_BMAP_SIZE  (MAX_TPA_P5 / BITS_PER_LONG)
 884
 885 struct bnxt_tpa_idx_map {
 886         u16             agg_id_tbl[1024];
 887         unsigned long   agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE];
 888 };
 889
 890 struct bnxt_rx_ring_info {
 891         struct bnxt_napi        *bnapi;
 892         u16                     rx_prod;
 893         u16                     rx_agg_prod;
 894         u16                     rx_sw_agg_prod;
 895         u16                     rx_next_cons;
 896         struct bnxt_db_info     rx_db;
 897         struct bnxt_db_info     rx_agg_db;
 898
 899         struct bpf_prog         *xdp_prog;
 900
 901         struct rx_bd            *rx_desc_ring[MAX_RX_PAGES];
 902         struct bnxt_sw_rx_bd    *rx_buf_ring;
 903
 904         struct rx_bd            *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
 905         struct bnxt_sw_rx_agg_bd        *rx_agg_ring;
 906
 907         unsigned long           *rx_agg_bmap;
 908         u16                     rx_agg_bmap_size;
 909
 910         struct page             *rx_page;
 911         unsigned int            rx_page_offset;
 912
 913         dma_addr_t              rx_desc_mapping[MAX_RX_PAGES];
 914         dma_addr_t              rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
 915
 916         struct bnxt_tpa_info    *rx_tpa;
 917         struct bnxt_tpa_idx_map *rx_tpa_idx_map;
 918
 919         struct bnxt_ring_struct rx_ring_struct;
 920         struct bnxt_ring_struct rx_agg_ring_struct;
 921         struct xdp_rxq_info     xdp_rxq;
 922         struct page_pool        *page_pool;
 923 };
 924
 925 struct bnxt_rx_sw_stats {
 926         u64                     rx_l4_csum_errors;
 927         u64                     rx_resets;
 928         u64                     rx_buf_errors;
 929 };
 930
 931 struct bnxt_cmn_sw_stats {
 932         u64                     missed_irqs;
 933 };
 934
 935 struct bnxt_sw_stats {
 936         struct bnxt_rx_sw_stats rx;
 937         struct bnxt_cmn_sw_stats cmn;
 938 };
 939
 940 struct bnxt_stats_mem {
 941         u64             *sw_stats;
 942         u64             *hw_masks;
 943         void            *hw_stats;
 944         dma_addr_t      hw_stats_map;
 945         int             len;
 946 };
 947
 948 struct bnxt_cp_ring_info {
 949         struct bnxt_napi        *bnapi;
 950         u32                     cp_raw_cons;
 951         struct bnxt_db_info     cp_db;
 952
 953         u8                      had_work_done:1;
 954         u8                      has_more_work:1;
 955
 956         u32                     last_cp_raw_cons;
 957
 958         struct bnxt_coal        rx_ring_coal;
 959         u64                     rx_packets;
 960         u64                     rx_bytes;
 961         u64                     event_ctr;
 962
 963         struct dim              dim;
 964
 965         union {
 966                 struct tx_cmp   *cp_desc_ring[MAX_CP_PAGES];
 967                 struct nqe_cn   *nq_desc_ring[MAX_CP_PAGES];
 968         };
 969
 970         dma_addr_t              cp_desc_mapping[MAX_CP_PAGES];
 971
 972         struct bnxt_stats_mem   stats;
 973         u32                     hw_stats_ctx_id;
 974
 975         struct bnxt_sw_stats    sw_stats;
 976
 977         struct bnxt_ring_struct cp_ring_struct;
 978
 979         struct bnxt_cp_ring_info *cp_ring_arr[2];
 980 #define BNXT_RX_HDL     0
 981 #define BNXT_TX_HDL     1
 982 };
 983
 984 struct bnxt_napi {
 985         struct napi_struct      napi;
 986         struct bnxt             *bp;
 987
 988         int                     index;
 989         struct bnxt_cp_ring_info        cp_ring;
 990         struct bnxt_rx_ring_info        *rx_ring;
 991         struct bnxt_tx_ring_info        *tx_ring;
 992
 993         void                    (*tx_int)(struct bnxt *, struct bnxt_napi *,
 994                                           int);
 995         int                     tx_pkts;
 996         u8                      events;
 997
 998         u32                     flags;
 999 #define BNXT_NAPI_FLAG_XDP      0x1
1000
1001         bool                    in_reset;
1002 };
1003
1004 struct bnxt_irq {
1005         irq_handler_t   handler;
1006         unsigned int    vector;
1007         u8              requested:1;
1008         u8              have_cpumask:1;
1009         char            name[IFNAMSIZ + 2];
1010         cpumask_var_t   cpu_mask;
1011 };
1012
1013 #define HWRM_RING_ALLOC_TX      0x1
1014 #define HWRM_RING_ALLOC_RX      0x2
1015 #define HWRM_RING_ALLOC_AGG     0x4
1016 #define HWRM_RING_ALLOC_CMPL    0x8
1017 #define HWRM_RING_ALLOC_NQ      0x10
1018
1019 #define INVALID_STATS_CTX_ID    -1
1020
1021 struct bnxt_ring_grp_info {
1022         u16     fw_stats_ctx;
1023         u16     fw_grp_id;
1024         u16     rx_fw_ring_id;
1025         u16     agg_fw_ring_id;
1026         u16     cp_fw_ring_id;
1027 };
1028
1029 struct bnxt_vnic_info {
1030         u16             fw_vnic_id; /* returned by Chimp during alloc */
1031 #define BNXT_MAX_CTX_PER_VNIC   8
1032         u16             fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
1033         u16             fw_l2_ctx_id;
1034 #define BNXT_MAX_UC_ADDRS       4
1035         __le64          fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
1036                                 /* index 0 always dev_addr */
1037         u16             uc_filter_count;
1038         u8              *uc_list;
1039
1040         u16             *fw_grp_ids;
1041         dma_addr_t      rss_table_dma_addr;
1042         __le16          *rss_table;
1043         dma_addr_t      rss_hash_key_dma_addr;
1044         u64             *rss_hash_key;
1045         int             rss_table_size;
1046 #define BNXT_RSS_TABLE_ENTRIES_P5       64
1047 #define BNXT_RSS_TABLE_SIZE_P5          (BNXT_RSS_TABLE_ENTRIES_P5 * 4)
1048 #define BNXT_RSS_TABLE_MAX_TBL_P5       8
1049 #define BNXT_MAX_RSS_TABLE_SIZE_P5                              \
1050         (BNXT_RSS_TABLE_SIZE_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1051 #define BNXT_MAX_RSS_TABLE_ENTRIES_P5                           \
1052         (BNXT_RSS_TABLE_ENTRIES_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1053
1054         u32             rx_mask;
1055
1056         u8              *mc_list;
1057         int             mc_list_size;
1058         int             mc_list_count;
1059         dma_addr_t      mc_list_mapping;
1060 #define BNXT_MAX_MC_ADDRS       16
1061
1062         u32             flags;
1063 #define BNXT_VNIC_RSS_FLAG      1
1064 #define BNXT_VNIC_RFS_FLAG      2
1065 #define BNXT_VNIC_MCAST_FLAG    4
1066 #define BNXT_VNIC_UCAST_FLAG    8
1067 #define BNXT_VNIC_RFS_NEW_RSS_FLAG      0x10
1068 };
1069
1070 struct bnxt_hw_resc {
1071         u16     min_rsscos_ctxs;
1072         u16     max_rsscos_ctxs;
1073         u16     min_cp_rings;
1074         u16     max_cp_rings;
1075         u16     resv_cp_rings;
1076         u16     min_tx_rings;
1077         u16     max_tx_rings;
1078         u16     resv_tx_rings;
1079         u16     max_tx_sch_inputs;
1080         u16     min_rx_rings;
1081         u16     max_rx_rings;
1082         u16     resv_rx_rings;
1083         u16     min_hw_ring_grps;
1084         u16     max_hw_ring_grps;
1085         u16     resv_hw_ring_grps;
1086         u16     min_l2_ctxs;
1087         u16     max_l2_ctxs;
1088         u16     min_vnics;
1089         u16     max_vnics;
1090         u16     resv_vnics;
1091         u16     min_stat_ctxs;
1092         u16     max_stat_ctxs;
1093         u16     resv_stat_ctxs;
1094         u16     max_nqs;
1095         u16     max_irqs;
1096         u16     resv_irqs;
1097 };
1098
1099 #if defined(CONFIG_BNXT_SRIOV)
1100 struct bnxt_vf_info {
1101         u16     fw_fid;
1102         u8      mac_addr[ETH_ALEN];     /* PF assigned MAC Address */
1103         u8      vf_mac_addr[ETH_ALEN];  /* VF assigned MAC address, only
1104                                          * stored by PF.
1105                                          */
1106         u16     vlan;
1107         u16     func_qcfg_flags;
1108         u32     flags;
1109 #define BNXT_VF_QOS             0x1
1110 #define BNXT_VF_SPOOFCHK        0x2
1111 #define BNXT_VF_LINK_FORCED     0x4
1112 #define BNXT_VF_LINK_UP         0x8
1113 #define BNXT_VF_TRUST           0x10
1114         u32     min_tx_rate;
1115         u32     max_tx_rate;
1116         void    *hwrm_cmd_req_addr;
1117         dma_addr_t      hwrm_cmd_req_dma_addr;
1118 };
1119 #endif
1120
1121 struct bnxt_pf_info {
1122 #define BNXT_FIRST_PF_FID       1
1123 #define BNXT_FIRST_VF_FID       128
1124         u16     fw_fid;
1125         u16     port_id;
1126         u8      mac_addr[ETH_ALEN];
1127         u32     first_vf_id;
1128         u16     active_vfs;
1129         u16     registered_vfs;
1130         u16     max_vfs;
1131         u32     max_encap_records;
1132         u32     max_decap_records;
1133         u32     max_tx_em_flows;
1134         u32     max_tx_wm_flows;
1135         u32     max_rx_em_flows;
1136         u32     max_rx_wm_flows;
1137         unsigned long   *vf_event_bmap;
1138         u16     hwrm_cmd_req_pages;
1139         u8      vf_resv_strategy;
1140 #define BNXT_VF_RESV_STRATEGY_MAXIMAL   0
1141 #define BNXT_VF_RESV_STRATEGY_MINIMAL   1
1142 #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC    2
1143         void                    *hwrm_cmd_req_addr[4];
1144         dma_addr_t              hwrm_cmd_req_dma_addr[4];
1145         struct bnxt_vf_info     *vf;
1146 };
1147
1148 struct bnxt_ntuple_filter {
1149         struct hlist_node       hash;
1150         u8                      dst_mac_addr[ETH_ALEN];
1151         u8                      src_mac_addr[ETH_ALEN];
1152         struct flow_keys        fkeys;
1153         __le64                  filter_id;
1154         u16                     sw_id;
1155         u8                      l2_fltr_idx;
1156         u16                     rxq;
1157         u32                     flow_id;
1158         unsigned long           state;
1159 #define BNXT_FLTR_VALID         0
1160 #define BNXT_FLTR_UPDATE        1
1161 };
1162
1163 struct bnxt_link_info {
1164         u8                      phy_type;
1165         u8                      media_type;
1166         u8                      transceiver;
1167         u8                      phy_addr;
1168         u8                      phy_link_status;
1169 #define BNXT_LINK_NO_LINK       PORT_PHY_QCFG_RESP_LINK_NO_LINK
1170 #define BNXT_LINK_SIGNAL        PORT_PHY_QCFG_RESP_LINK_SIGNAL
1171 #define BNXT_LINK_LINK          PORT_PHY_QCFG_RESP_LINK_LINK
1172         u8                      wire_speed;
1173         u8                      phy_state;
1174 #define BNXT_PHY_STATE_ENABLED          0
1175 #define BNXT_PHY_STATE_DISABLED         1
1176
1177         u8                      link_up;
1178         u8                      duplex;
1179 #define BNXT_LINK_DUPLEX_HALF   PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1180 #define BNXT_LINK_DUPLEX_FULL   PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1181         u8                      pause;
1182 #define BNXT_LINK_PAUSE_TX      PORT_PHY_QCFG_RESP_PAUSE_TX
1183 #define BNXT_LINK_PAUSE_RX      PORT_PHY_QCFG_RESP_PAUSE_RX
1184 #define BNXT_LINK_PAUSE_BOTH    (PORT_PHY_QCFG_RESP_PAUSE_RX | \
1185                                  PORT_PHY_QCFG_RESP_PAUSE_TX)
1186         u8                      lp_pause;
1187         u8                      auto_pause_setting;
1188         u8                      force_pause_setting;
1189         u8                      duplex_setting;
1190         u8                      auto_mode;
1191 #define BNXT_AUTO_MODE(mode)    ((mode) > BNXT_LINK_AUTO_NONE && \
1192                                  (mode) <= BNXT_LINK_AUTO_MSK)
1193 #define BNXT_LINK_AUTO_NONE     PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1194 #define BNXT_LINK_AUTO_ALLSPDS  PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1195 #define BNXT_LINK_AUTO_ONESPD   PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1196 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
1197 #define BNXT_LINK_AUTO_MSK      PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1198 #define PHY_VER_LEN             3
1199         u8                      phy_ver[PHY_VER_LEN];
1200         u16                     link_speed;
1201 #define BNXT_LINK_SPEED_100MB   PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1202 #define BNXT_LINK_SPEED_1GB     PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1203 #define BNXT_LINK_SPEED_2GB     PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1204 #define BNXT_LINK_SPEED_2_5GB   PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1205 #define BNXT_LINK_SPEED_10GB    PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1206 #define BNXT_LINK_SPEED_20GB    PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1207 #define BNXT_LINK_SPEED_25GB    PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1208 #define BNXT_LINK_SPEED_40GB    PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1209 #define BNXT_LINK_SPEED_50GB    PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
1210 #define BNXT_LINK_SPEED_100GB   PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1211         u16                     support_speeds;
1212         u16                     support_pam4_speeds;
1213         u16                     auto_link_speeds;       /* fw adv setting */
1214 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1215 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1216 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1217 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1218 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1219 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1220 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1221 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1222 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
1223 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1224         u16                     auto_pam4_link_speeds;
1225 #define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G
1226 #define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G
1227 #define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G
1228         u16                     support_auto_speeds;
1229         u16                     support_pam4_auto_speeds;
1230         u16                     lp_auto_link_speeds;
1231         u16                     lp_auto_pam4_link_speeds;
1232         u16                     force_link_speed;
1233         u16                     force_pam4_link_speed;
1234         u32                     preemphasis;
1235         u8                      module_status;
1236         u8                      active_fec_sig_mode;
1237         u16                     fec_cfg;
1238 #define BNXT_FEC_NONE           PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
1239 #define BNXT_FEC_AUTONEG_CAP    PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED
1240 #define BNXT_FEC_AUTONEG        PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
1241 #define BNXT_FEC_ENC_BASE_R_CAP \
1242         PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED
1243 #define BNXT_FEC_ENC_BASE_R     PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
1244 #define BNXT_FEC_ENC_RS_CAP     \
1245         PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED
1246 #define BNXT_FEC_ENC_LLRS_CAP   \
1247         (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED |   \
1248          PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED)
1249 #define BNXT_FEC_ENC_RS         \
1250         (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED |      \
1251          PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED |     \
1252          PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED)
1253 #define BNXT_FEC_ENC_LLRS       \
1254         (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED |     \
1255          PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED)
1256
1257         /* copy of requested setting from ethtool cmd */
1258         u8                      autoneg;
1259 #define BNXT_AUTONEG_SPEED              1
1260 #define BNXT_AUTONEG_FLOW_CTRL          2
1261         u8                      req_signal_mode;
1262 #define BNXT_SIG_MODE_NRZ       PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ
1263 #define BNXT_SIG_MODE_PAM4      PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4
1264         u8                      req_duplex;
1265         u8                      req_flow_ctrl;
1266         u16                     req_link_speed;
1267         u16                     advertising;    /* user adv setting */
1268         u16                     advertising_pam4;
1269         bool                    force_link_chng;
1270
1271         bool                    phy_retry;
1272         unsigned long           phy_retry_expires;
1273
1274         /* a copy of phy_qcfg output used to report link
1275          * info to VF
1276          */
1277         struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
1278 };
1279
1280 #define BNXT_FEC_RS544_ON                                       \
1281          (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE |         \
1282           PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE)
1283
1284 #define BNXT_FEC_RS544_OFF                                      \
1285          (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE |        \
1286           PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE)
1287
1288 #define BNXT_FEC_RS272_ON                                       \
1289          (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE |         \
1290           PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE)
1291
1292 #define BNXT_FEC_RS272_OFF                                      \
1293          (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE |        \
1294           PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE)
1295
1296 #define BNXT_PAM4_SUPPORTED(link_info)                          \
1297         ((link_info)->support_pam4_speeds)
1298
1299 #define BNXT_FEC_RS_ON(link_info)                               \
1300         (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE |           \
1301          PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |          \
1302          (BNXT_PAM4_SUPPORTED(link_info) ?                      \
1303           (BNXT_FEC_RS544_ON | BNXT_FEC_RS272_OFF) : 0))
1304
1305 #define BNXT_FEC_LLRS_ON                                        \
1306         (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE |           \
1307          PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |          \
1308          BNXT_FEC_RS272_ON | BNXT_FEC_RS544_OFF)
1309
1310 #define BNXT_FEC_RS_OFF(link_info)                              \
1311         (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE |          \
1312          (BNXT_PAM4_SUPPORTED(link_info) ?                      \
1313           (BNXT_FEC_RS544_OFF | BNXT_FEC_RS272_OFF) : 0))
1314
1315 #define BNXT_FEC_BASE_R_ON(link_info)                           \
1316         (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE |           \
1317          BNXT_FEC_RS_OFF(link_info))
1318
1319 #define BNXT_FEC_ALL_OFF(link_info)                             \
1320         (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |          \
1321          BNXT_FEC_RS_OFF(link_info))
1322
1323 #define BNXT_MAX_QUEUE  8
1324
1325 struct bnxt_queue_info {
1326         u8      queue_id;
1327         u8      queue_profile;
1328 };
1329
1330 #define BNXT_MAX_LED                    4
1331
1332 struct bnxt_led_info {
1333         u8      led_id;
1334         u8      led_type;
1335         u8      led_group_id;
1336         u8      unused;
1337         __le16  led_state_caps;
1338 #define BNXT_LED_ALT_BLINK_CAP(x)       ((x) &  \
1339         cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
1340
1341         __le16  led_color_caps;
1342 };
1343
1344 #define BNXT_MAX_TEST   8
1345
1346 struct bnxt_test_info {
1347         u8 offline_mask;
1348         u16 timeout;
1349         char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1350 };
1351
1352 #define CHIMP_REG_VIEW_ADDR                             \
1353         ((bp->flags & BNXT_FLAG_CHIP_P5) ? 0x80000000 : 0xb1000000)
1354
1355 #define BNXT_GRCPF_REG_CHIMP_COMM               0x0
1356 #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER       0x100
1357 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT          0x400
1358 #define BNXT_CAG_REG_LEGACY_INT_STATUS          0x4014
1359 #define BNXT_CAG_REG_BASE                       0x300000
1360
1361 #define BNXT_GRC_REG_STATUS_P5                  0x520
1362
1363 #define BNXT_GRCPF_REG_KONG_COMM                0xA00
1364 #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER        0xB00
1365
1366 #define BNXT_GRC_REG_CHIP_NUM                   0x48
1367 #define BNXT_GRC_REG_BASE                       0x260000
1368
1369 #define BNXT_TS_REG_TIMESYNC_TS0_LOWER          0x640180c
1370 #define BNXT_TS_REG_TIMESYNC_TS0_UPPER          0x6401810
1371
1372 #define BNXT_GRC_BASE_MASK                      0xfffff000
1373 #define BNXT_GRC_OFFSET_MASK                    0x00000ffc
1374
1375 struct bnxt_tc_flow_stats {
1376         u64             packets;
1377         u64             bytes;
1378 };
1379
1380 #ifdef CONFIG_BNXT_FLOWER_OFFLOAD
1381 struct bnxt_flower_indr_block_cb_priv {
1382         struct net_device *tunnel_netdev;
1383         struct bnxt *bp;
1384         struct list_head list;
1385 };
1386 #endif
1387
1388 struct bnxt_tc_info {
1389         bool                            enabled;
1390
1391         /* hash table to store TC offloaded flows */
1392         struct rhashtable               flow_table;
1393         struct rhashtable_params        flow_ht_params;
1394
1395         /* hash table to store L2 keys of TC flows */
1396         struct rhashtable               l2_table;
1397         struct rhashtable_params        l2_ht_params;
1398         /* hash table to store L2 keys for TC tunnel decap */
1399         struct rhashtable               decap_l2_table;
1400         struct rhashtable_params        decap_l2_ht_params;
1401         /* hash table to store tunnel decap entries */
1402         struct rhashtable               decap_table;
1403         struct rhashtable_params        decap_ht_params;
1404         /* hash table to store tunnel encap entries */
1405         struct rhashtable               encap_table;
1406         struct rhashtable_params        encap_ht_params;
1407
1408         /* lock to atomically add/del an l2 node when a flow is
1409          * added or deleted.
1410          */
1411         struct mutex                    lock;
1412
1413         /* Fields used for batching stats query */
1414         struct rhashtable_iter          iter;
1415 #define BNXT_FLOW_STATS_BATCH_MAX       10
1416         struct bnxt_tc_stats_batch {
1417                 void                      *flow_node;
1418                 struct bnxt_tc_flow_stats hw_stats;
1419         } stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
1420
1421         /* Stat counter mask (width) */
1422         u64                             bytes_mask;
1423         u64                             packets_mask;
1424 };
1425
1426 struct bnxt_vf_rep_stats {
1427         u64                     packets;
1428         u64                     bytes;
1429         u64                     dropped;
1430 };
1431
1432 struct bnxt_vf_rep {
1433         struct bnxt                     *bp;
1434         struct net_device               *dev;
1435         struct metadata_dst             *dst;
1436         u16                             vf_idx;
1437         u16                             tx_cfa_action;
1438         u16                             rx_cfa_code;
1439
1440         struct bnxt_vf_rep_stats        rx_stats;
1441         struct bnxt_vf_rep_stats        tx_stats;
1442 };
1443
1444 #define PTU_PTE_VALID             0x1UL
1445 #define PTU_PTE_LAST              0x2UL
1446 #define PTU_PTE_NEXT_TO_LAST      0x4UL
1447
1448 #define MAX_CTX_PAGES   (BNXT_PAGE_SIZE / 8)
1449 #define MAX_CTX_TOTAL_PAGES     (MAX_CTX_PAGES * MAX_CTX_PAGES)
1450
1451 struct bnxt_ctx_pg_info {
1452         u32             entries;
1453         u32             nr_pages;
1454         void            *ctx_pg_arr[MAX_CTX_PAGES];
1455         dma_addr_t      ctx_dma_arr[MAX_CTX_PAGES];
1456         struct bnxt_ring_mem_info ring_mem;
1457         struct bnxt_ctx_pg_info **ctx_pg_tbl;
1458 };
1459
1460 #define BNXT_MAX_TQM_SP_RINGS           1
1461 #define BNXT_MAX_TQM_FP_RINGS           8
1462 #define BNXT_MAX_TQM_RINGS              \
1463         (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS)
1464
1465 #define BNXT_BACKING_STORE_CFG_LEGACY_LEN       256
1466
1467 #define BNXT_SET_CTX_PAGE_ATTR(attr)                                    \
1468 do {                                                                    \
1469         if (BNXT_PAGE_SIZE == 0x2000)                                   \
1470                 attr = FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K;    \
1471         else if (BNXT_PAGE_SIZE == 0x10000)                             \
1472                 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K;   \
1473         else                                                            \
1474                 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K;    \
1475 } while (0)
1476
1477 struct bnxt_ctx_mem_info {
1478         u32     qp_max_entries;
1479         u16     qp_min_qp1_entries;
1480         u16     qp_max_l2_entries;
1481         u16     qp_entry_size;
1482         u16     srq_max_l2_entries;
1483         u32     srq_max_entries;
1484         u16     srq_entry_size;
1485         u16     cq_max_l2_entries;
1486         u32     cq_max_entries;
1487         u16     cq_entry_size;
1488         u16     vnic_max_vnic_entries;
1489         u16     vnic_max_ring_table_entries;
1490         u16     vnic_entry_size;
1491         u32     stat_max_entries;
1492         u16     stat_entry_size;
1493         u16     tqm_entry_size;
1494         u32     tqm_min_entries_per_ring;
1495         u32     tqm_max_entries_per_ring;
1496         u32     mrav_max_entries;
1497         u16     mrav_entry_size;
1498         u16     tim_entry_size;
1499         u32     tim_max_entries;
1500         u16     mrav_num_entries_units;
1501         u8      tqm_entries_multiple;
1502         u8      tqm_fp_rings_count;
1503
1504         u32     flags;
1505         #define BNXT_CTX_FLAG_INITED    0x01
1506
1507         struct bnxt_ctx_pg_info qp_mem;
1508         struct bnxt_ctx_pg_info srq_mem;
1509         struct bnxt_ctx_pg_info cq_mem;
1510         struct bnxt_ctx_pg_info vnic_mem;
1511         struct bnxt_ctx_pg_info stat_mem;
1512         struct bnxt_ctx_pg_info mrav_mem;
1513         struct bnxt_ctx_pg_info tim_mem;
1514         struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TQM_RINGS];
1515
1516 #define BNXT_CTX_MEM_INIT_QP    0
1517 #define BNXT_CTX_MEM_INIT_SRQ   1
1518 #define BNXT_CTX_MEM_INIT_CQ    2
1519 #define BNXT_CTX_MEM_INIT_VNIC  3
1520 #define BNXT_CTX_MEM_INIT_STAT  4
1521 #define BNXT_CTX_MEM_INIT_MRAV  5
1522 #define BNXT_CTX_MEM_INIT_MAX   6
1523         struct bnxt_mem_init    mem_init[BNXT_CTX_MEM_INIT_MAX];
1524 };
1525
1526 struct bnxt_fw_health {
1527         u32 flags;
1528         u32 polling_dsecs;
1529         u32 master_func_wait_dsecs;
1530         u32 normal_func_wait_dsecs;
1531         u32 post_reset_wait_dsecs;
1532         u32 post_reset_max_wait_dsecs;
1533         u32 regs[4];
1534         u32 mapped_regs[4];
1535 #define BNXT_FW_HEALTH_REG              0
1536 #define BNXT_FW_HEARTBEAT_REG           1
1537 #define BNXT_FW_RESET_CNT_REG           2
1538 #define BNXT_FW_RESET_INPROG_REG        3
1539         u32 fw_reset_inprog_reg_mask;
1540         u32 last_fw_heartbeat;
1541         u32 last_fw_reset_cnt;
1542         u8 enabled:1;
1543         u8 master:1;
1544         u8 fatal:1;
1545         u8 status_reliable:1;
1546         u8 tmr_multiplier;
1547         u8 tmr_counter;
1548         u8 fw_reset_seq_cnt;
1549         u32 fw_reset_seq_regs[16];
1550         u32 fw_reset_seq_vals[16];
1551         u32 fw_reset_seq_delay_msec[16];
1552         u32 echo_req_data1;
1553         u32 echo_req_data2;
1554         struct devlink_health_reporter  *fw_reporter;
1555         struct devlink_health_reporter *fw_reset_reporter;
1556         struct devlink_health_reporter *fw_fatal_reporter;
1557 };
1558
1559 struct bnxt_fw_reporter_ctx {
1560         unsigned long sp_event;
1561 };
1562
1563 #define BNXT_FW_HEALTH_REG_TYPE_MASK    3
1564 #define BNXT_FW_HEALTH_REG_TYPE_CFG     0
1565 #define BNXT_FW_HEALTH_REG_TYPE_GRC     1
1566 #define BNXT_FW_HEALTH_REG_TYPE_BAR0    2
1567 #define BNXT_FW_HEALTH_REG_TYPE_BAR1    3
1568
1569 #define BNXT_FW_HEALTH_REG_TYPE(reg)    ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)
1570 #define BNXT_FW_HEALTH_REG_OFF(reg)     ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)
1571
1572 #define BNXT_FW_HEALTH_WIN_BASE         0x3000
1573 #define BNXT_FW_HEALTH_WIN_MAP_OFF      8
1574
1575 #define BNXT_FW_HEALTH_WIN_OFF(reg)     (BNXT_FW_HEALTH_WIN_BASE +      \
1576                                          ((reg) & BNXT_GRC_OFFSET_MASK))
1577
1578 #define BNXT_FW_STATUS_HEALTH_MSK       0xffff
1579 #define BNXT_FW_STATUS_HEALTHY          0x8000
1580 #define BNXT_FW_STATUS_SHUTDOWN         0x100000
1581 #define BNXT_FW_STATUS_RECOVERING       0x400000
1582
1583 #define BNXT_FW_IS_HEALTHY(sts)         (((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\
1584                                          BNXT_FW_STATUS_HEALTHY)
1585
1586 #define BNXT_FW_IS_BOOTING(sts)         (((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \
1587                                          BNXT_FW_STATUS_HEALTHY)
1588
1589 #define BNXT_FW_IS_ERR(sts)             (((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \
1590                                          BNXT_FW_STATUS_HEALTHY)
1591
1592 #define BNXT_FW_IS_RECOVERING(sts)      (BNXT_FW_IS_ERR(sts) &&                \
1593                                          ((sts) & BNXT_FW_STATUS_RECOVERING))
1594
1595 #define BNXT_FW_RETRY                   5
1596 #define BNXT_FW_IF_RETRY                10
1597
1598 struct bnxt {
1599         void __iomem            *bar0;
1600         void __iomem            *bar1;
1601         void __iomem            *bar2;
1602
1603         u32                     reg_base;
1604         u16                     chip_num;
1605 #define CHIP_NUM_57301          0x16c8
1606 #define CHIP_NUM_57302          0x16c9
1607 #define CHIP_NUM_57304          0x16ca
1608 #define CHIP_NUM_58700          0x16cd
1609 #define CHIP_NUM_57402          0x16d0
1610 #define CHIP_NUM_57404          0x16d1
1611 #define CHIP_NUM_57406          0x16d2
1612 #define CHIP_NUM_57407          0x16d5
1613
1614 #define CHIP_NUM_57311          0x16ce
1615 #define CHIP_NUM_57312          0x16cf
1616 #define CHIP_NUM_57314          0x16df
1617 #define CHIP_NUM_57317          0x16e0
1618 #define CHIP_NUM_57412          0x16d6
1619 #define CHIP_NUM_57414          0x16d7
1620 #define CHIP_NUM_57416          0x16d8
1621 #define CHIP_NUM_57417          0x16d9
1622 #define CHIP_NUM_57412L         0x16da
1623 #define CHIP_NUM_57414L         0x16db
1624
1625 #define CHIP_NUM_5745X          0xd730
1626 #define CHIP_NUM_57452          0xc452
1627 #define CHIP_NUM_57454          0xc454
1628
1629 #define CHIP_NUM_57508          0x1750
1630 #define CHIP_NUM_57504          0x1751
1631 #define CHIP_NUM_57502          0x1752
1632
1633 #define CHIP_NUM_58802          0xd802
1634 #define CHIP_NUM_58804          0xd804
1635 #define CHIP_NUM_58808          0xd808
1636
1637         u8                      chip_rev;
1638
1639 #define CHIP_NUM_58818          0xd818
1640
1641 #define BNXT_CHIP_NUM_5730X(chip_num)           \
1642         ((chip_num) >= CHIP_NUM_57301 &&        \
1643          (chip_num) <= CHIP_NUM_57304)
1644
1645 #define BNXT_CHIP_NUM_5740X(chip_num)           \
1646         (((chip_num) >= CHIP_NUM_57402 &&       \
1647           (chip_num) <= CHIP_NUM_57406) ||      \
1648          (chip_num) == CHIP_NUM_57407)
1649
1650 #define BNXT_CHIP_NUM_5731X(chip_num)           \
1651         ((chip_num) == CHIP_NUM_57311 ||        \
1652          (chip_num) == CHIP_NUM_57312 ||        \
1653          (chip_num) == CHIP_NUM_57314 ||        \
1654          (chip_num) == CHIP_NUM_57317)
1655
1656 #define BNXT_CHIP_NUM_5741X(chip_num)           \
1657         ((chip_num) >= CHIP_NUM_57412 &&        \
1658          (chip_num) <= CHIP_NUM_57414L)
1659
1660 #define BNXT_CHIP_NUM_58700(chip_num)           \
1661          ((chip_num) == CHIP_NUM_58700)
1662
1663 #define BNXT_CHIP_NUM_5745X(chip_num)           \
1664         ((chip_num) == CHIP_NUM_5745X ||        \
1665          (chip_num) == CHIP_NUM_57452 ||        \
1666          (chip_num) == CHIP_NUM_57454)
1667
1668
1669 #define BNXT_CHIP_NUM_57X0X(chip_num)           \
1670         (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
1671
1672 #define BNXT_CHIP_NUM_57X1X(chip_num)           \
1673         (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
1674
1675 #define BNXT_CHIP_NUM_588XX(chip_num)           \
1676         ((chip_num) == CHIP_NUM_58802 ||        \
1677          (chip_num) == CHIP_NUM_58804 ||        \
1678          (chip_num) == CHIP_NUM_58808)
1679
1680 #define BNXT_VPD_FLD_LEN        32
1681         char                    board_partno[BNXT_VPD_FLD_LEN];
1682         char                    board_serialno[BNXT_VPD_FLD_LEN];
1683
1684         struct net_device       *dev;
1685         struct pci_dev          *pdev;
1686
1687         atomic_t                intr_sem;
1688
1689         u32                     flags;
1690         #define BNXT_FLAG_CHIP_P5       0x1
1691         #define BNXT_FLAG_VF            0x2
1692         #define BNXT_FLAG_LRO           0x4
1693 #ifdef CONFIG_INET
1694         #define BNXT_FLAG_GRO           0x8
1695 #else
1696         /* Cannot support hardware GRO if CONFIG_INET is not set */
1697         #define BNXT_FLAG_GRO           0x0
1698 #endif
1699         #define BNXT_FLAG_TPA           (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
1700         #define BNXT_FLAG_JUMBO         0x10
1701         #define BNXT_FLAG_STRIP_VLAN    0x20
1702         #define BNXT_FLAG_AGG_RINGS     (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
1703                                          BNXT_FLAG_LRO)
1704         #define BNXT_FLAG_USING_MSIX    0x40
1705         #define BNXT_FLAG_MSIX_CAP      0x80
1706         #define BNXT_FLAG_RFS           0x100
1707         #define BNXT_FLAG_SHARED_RINGS  0x200
1708         #define BNXT_FLAG_PORT_STATS    0x400
1709         #define BNXT_FLAG_UDP_RSS_CAP   0x800
1710         #define BNXT_FLAG_NEW_RSS_CAP   0x2000
1711         #define BNXT_FLAG_WOL_CAP       0x4000
1712         #define BNXT_FLAG_ROCEV1_CAP    0x8000
1713         #define BNXT_FLAG_ROCEV2_CAP    0x10000
1714         #define BNXT_FLAG_ROCE_CAP      (BNXT_FLAG_ROCEV1_CAP | \
1715                                          BNXT_FLAG_ROCEV2_CAP)
1716         #define BNXT_FLAG_NO_AGG_RINGS  0x20000
1717         #define BNXT_FLAG_RX_PAGE_MODE  0x40000
1718         #define BNXT_FLAG_CHIP_SR2      0x80000
1719         #define BNXT_FLAG_MULTI_HOST    0x100000
1720         #define BNXT_FLAG_DSN_VALID     0x200000
1721         #define BNXT_FLAG_DOUBLE_DB     0x400000
1722         #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
1723         #define BNXT_FLAG_DIM           0x2000000
1724         #define BNXT_FLAG_ROCE_MIRROR_CAP       0x4000000
1725         #define BNXT_FLAG_PORT_STATS_EXT        0x10000000
1726
1727         #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA |             \
1728                                             BNXT_FLAG_RFS |             \
1729                                             BNXT_FLAG_STRIP_VLAN)
1730
1731 #define BNXT_PF(bp)             (!((bp)->flags & BNXT_FLAG_VF))
1732 #define BNXT_VF(bp)             ((bp)->flags & BNXT_FLAG_VF)
1733 #define BNXT_NPAR(bp)           ((bp)->port_partition_type)
1734 #define BNXT_MH(bp)             ((bp)->flags & BNXT_FLAG_MULTI_HOST)
1735 #define BNXT_SINGLE_PF(bp)      (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
1736 #define BNXT_SH_PORT_CFG_OK(bp) (BNXT_PF(bp) &&                         \
1737                                  ((bp)->phy_flags & BNXT_PHY_FL_SHARED_PORT_CFG))
1738 #define BNXT_PHY_CFG_ABLE(bp)   ((BNXT_SINGLE_PF(bp) ||                 \
1739                                   BNXT_SH_PORT_CFG_OK(bp)) &&           \
1740                                  (bp)->link_info.phy_state == BNXT_PHY_STATE_ENABLED)
1741 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1742 #define BNXT_RX_PAGE_MODE(bp)   ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1743 #define BNXT_SUPPORTS_TPA(bp)   (!BNXT_CHIP_TYPE_NITRO_A0(bp) &&        \
1744                                  (!((bp)->flags & BNXT_FLAG_CHIP_P5) || \
1745                                   (bp)->max_tpa_v2) && !is_kdump_kernel())
1746
1747 #define BNXT_CHIP_SR2(bp)                       \
1748         ((bp)->chip_num == CHIP_NUM_58818)
1749
1750 #define BNXT_CHIP_P5_THOR(bp)                   \
1751         ((bp)->chip_num == CHIP_NUM_57508 ||    \
1752          (bp)->chip_num == CHIP_NUM_57504 ||    \
1753          (bp)->chip_num == CHIP_NUM_57502)
1754
1755 /* Chip class phase 5 */
1756 #define BNXT_CHIP_P5(bp)                        \
1757         (BNXT_CHIP_P5_THOR(bp) || BNXT_CHIP_SR2(bp))
1758
1759 /* Chip class phase 4.x */
1760 #define BNXT_CHIP_P4(bp)                        \
1761         (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
1762          BNXT_CHIP_NUM_5745X((bp)->chip_num) || \
1763          BNXT_CHIP_NUM_588XX((bp)->chip_num) || \
1764          (BNXT_CHIP_NUM_58700((bp)->chip_num) &&        \
1765           !BNXT_CHIP_TYPE_NITRO_A0(bp)))
1766
1767 #define BNXT_CHIP_P4_PLUS(bp)                   \
1768         (BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))
1769
1770         struct bnxt_en_dev      *edev;
1771
1772         struct bnxt_napi        **bnapi;
1773
1774         struct bnxt_rx_ring_info        *rx_ring;
1775         struct bnxt_tx_ring_info        *tx_ring;
1776         u16                     *tx_ring_map;
1777
1778         struct sk_buff *        (*gro_func)(struct bnxt_tpa_info *, int, int,
1779                                             struct sk_buff *);
1780
1781         struct sk_buff *        (*rx_skb_func)(struct bnxt *,
1782                                                struct bnxt_rx_ring_info *,
1783                                                u16, void *, u8 *, dma_addr_t,
1784                                                unsigned int);
1785
1786         u16                     max_tpa_v2;
1787         u16                     max_tpa;
1788         u32                     rx_buf_size;
1789         u32                     rx_buf_use_size;        /* useable size */
1790         u16                     rx_offset;
1791         u16                     rx_dma_offset;
1792         enum dma_data_direction rx_dir;
1793         u32                     rx_ring_size;
1794         u32                     rx_agg_ring_size;
1795         u32                     rx_copy_thresh;
1796         u32                     rx_ring_mask;
1797         u32                     rx_agg_ring_mask;
1798         int                     rx_nr_pages;
1799         int                     rx_agg_nr_pages;
1800         int                     rx_nr_rings;
1801         int                     rsscos_nr_ctxs;
1802
1803         u32                     tx_ring_size;
1804         u32                     tx_ring_mask;
1805         int                     tx_nr_pages;
1806         int                     tx_nr_rings;
1807         int                     tx_nr_rings_per_tc;
1808         int                     tx_nr_rings_xdp;
1809
1810         int                     tx_wake_thresh;
1811         int                     tx_push_thresh;
1812         int                     tx_push_size;
1813
1814         u32                     cp_ring_size;
1815         u32                     cp_ring_mask;
1816         u32                     cp_bit;
1817         int                     cp_nr_pages;
1818         int                     cp_nr_rings;
1819
1820         /* grp_info indexed by completion ring index */
1821         struct bnxt_ring_grp_info       *grp_info;
1822         struct bnxt_vnic_info   *vnic_info;
1823         int                     nr_vnics;
1824         u16                     *rss_indir_tbl;
1825         u16                     rss_indir_tbl_entries;
1826         u32                     rss_hash_cfg;
1827
1828         u16                     max_mtu;
1829         u8                      max_tc;
1830         u8                      max_lltc;       /* lossless TCs */
1831         struct bnxt_queue_info  q_info[BNXT_MAX_QUEUE];
1832         u8                      tc_to_qidx[BNXT_MAX_QUEUE];
1833         u8                      q_ids[BNXT_MAX_QUEUE];
1834         u8                      max_q;
1835
1836         unsigned int            current_interval;
1837 #define BNXT_TIMER_INTERVAL     HZ
1838
1839         struct timer_list       timer;
1840
1841         unsigned long           state;
1842 #define BNXT_STATE_OPEN         0
1843 #define BNXT_STATE_IN_SP_TASK   1
1844 #define BNXT_STATE_READ_STATS   2
1845 #define BNXT_STATE_FW_RESET_DET 3
1846 #define BNXT_STATE_IN_FW_RESET  4
1847 #define BNXT_STATE_ABORT_ERR    5
1848 #define BNXT_STATE_FW_FATAL_COND        6
1849 #define BNXT_STATE_DRV_REGISTERED       7
1850 #define BNXT_STATE_PCI_CHANNEL_IO_FROZEN        8
1851 #define BNXT_STATE_NAPI_DISABLED        9
1852
1853 #define BNXT_NO_FW_ACCESS(bp)                                   \
1854         (test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) ||    \
1855          pci_channel_offline((bp)->pdev))
1856
1857         struct bnxt_irq *irq_tbl;
1858         int                     total_irqs;
1859         u8                      mac_addr[ETH_ALEN];
1860
1861 #ifdef CONFIG_BNXT_DCB
1862         struct ieee_pfc         *ieee_pfc;
1863         struct ieee_ets         *ieee_ets;
1864         u8                      dcbx_cap;
1865         u8                      default_pri;
1866         u8                      max_dscp_value;
1867 #endif /* CONFIG_BNXT_DCB */
1868
1869         u32                     msg_enable;
1870
1871         u32                     fw_cap;
1872         #define BNXT_FW_CAP_SHORT_CMD                   0x00000001
1873         #define BNXT_FW_CAP_LLDP_AGENT                  0x00000002
1874         #define BNXT_FW_CAP_DCBX_AGENT                  0x00000004
1875         #define BNXT_FW_CAP_NEW_RM                      0x00000008
1876         #define BNXT_FW_CAP_IF_CHANGE                   0x00000010
1877         #define BNXT_FW_CAP_KONG_MB_CHNL                0x00000080
1878         #define BNXT_FW_CAP_OVS_64BIT_HANDLE            0x00000400
1879         #define BNXT_FW_CAP_TRUSTED_VF                  0x00000800
1880         #define BNXT_FW_CAP_ERROR_RECOVERY              0x00002000
1881         #define BNXT_FW_CAP_PKG_VER                     0x00004000
1882         #define BNXT_FW_CAP_CFA_ADV_FLOW                0x00008000
1883         #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2     0x00010000
1884         #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED        0x00020000
1885         #define BNXT_FW_CAP_EXT_STATS_SUPPORTED         0x00040000
1886         #define BNXT_FW_CAP_ERR_RECOVER_RELOAD          0x00100000
1887         #define BNXT_FW_CAP_HOT_RESET                   0x00200000
1888         #define BNXT_FW_CAP_VLAN_RX_STRIP               0x01000000
1889         #define BNXT_FW_CAP_VLAN_TX_INSERT              0x02000000
1890         #define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED      0x04000000
1891         #define BNXT_FW_CAP_RING_MONITOR                0x40000000
1892
1893 #define BNXT_NEW_RM(bp)         ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
1894         u32                     hwrm_spec_code;
1895         u16                     hwrm_cmd_seq;
1896         u16                     hwrm_cmd_kong_seq;
1897         u16                     hwrm_intr_seq_id;
1898         void                    *hwrm_short_cmd_req_addr;
1899         dma_addr_t              hwrm_short_cmd_req_dma_addr;
1900         void                    *hwrm_cmd_resp_addr;
1901         dma_addr_t              hwrm_cmd_resp_dma_addr;
1902         void                    *hwrm_cmd_kong_resp_addr;
1903         dma_addr_t              hwrm_cmd_kong_resp_dma_addr;
1904
1905         struct rtnl_link_stats64        net_stats_prev;
1906         struct bnxt_stats_mem   port_stats;
1907         struct bnxt_stats_mem   rx_port_stats_ext;
1908         struct bnxt_stats_mem   tx_port_stats_ext;
1909         u16                     fw_rx_stats_ext_size;
1910         u16                     fw_tx_stats_ext_size;
1911         u16                     hw_ring_stats_size;
1912         u8                      pri2cos_idx[8];
1913         u8                      pri2cos_valid;
1914
1915         u16                     hwrm_max_req_len;
1916         u16                     hwrm_max_ext_req_len;
1917         int                     hwrm_cmd_timeout;
1918         struct mutex            hwrm_cmd_lock;  /* serialize hwrm messages */
1919         struct hwrm_ver_get_output      ver_resp;
1920 #define FW_VER_STR_LEN          32
1921 #define BC_HWRM_STR_LEN         21
1922 #define PHY_VER_STR_LEN         (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
1923         char                    fw_ver_str[FW_VER_STR_LEN];
1924         char                    hwrm_ver_supp[FW_VER_STR_LEN];
1925         char                    nvm_cfg_ver[FW_VER_STR_LEN];
1926         u64                     fw_ver_code;
1927 #define BNXT_FW_VER_CODE(maj, min, bld, rsv)                    \
1928         ((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv))
1929 #define BNXT_FW_MAJ(bp)         ((bp)->fw_ver_code >> 48)
1930
1931         u16                     vxlan_fw_dst_port_id;
1932         u16                     nge_fw_dst_port_id;
1933         __be16                  vxlan_port;
1934         __be16                  nge_port;
1935         u8                      port_partition_type;
1936         u8                      port_count;
1937         u16                     br_mode;
1938
1939         struct bnxt_coal_cap    coal_cap;
1940         struct bnxt_coal        rx_coal;
1941         struct bnxt_coal        tx_coal;
1942
1943         u32                     stats_coal_ticks;
1944 #define BNXT_DEF_STATS_COAL_TICKS        1000000
1945 #define BNXT_MIN_STATS_COAL_TICKS         250000
1946 #define BNXT_MAX_STATS_COAL_TICKS        1000000
1947
1948         struct work_struct      sp_task;
1949         unsigned long           sp_event;
1950 #define BNXT_RX_MASK_SP_EVENT           0
1951 #define BNXT_RX_NTP_FLTR_SP_EVENT       1
1952 #define BNXT_LINK_CHNG_SP_EVENT         2
1953 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
1954 #define BNXT_RESET_TASK_SP_EVENT        6
1955 #define BNXT_RST_RING_SP_EVENT          7
1956 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT    8
1957 #define BNXT_PERIODIC_STATS_SP_EVENT    9
1958 #define BNXT_HWRM_PORT_MODULE_SP_EVENT  10
1959 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11
1960 #define BNXT_LINK_SPEED_CHNG_SP_EVENT   14
1961 #define BNXT_FLOW_STATS_SP_EVENT        15
1962 #define BNXT_UPDATE_PHY_SP_EVENT        16
1963 #define BNXT_RING_COAL_NOW_SP_EVENT     17
1964 #define BNXT_FW_RESET_NOTIFY_SP_EVENT   18
1965 #define BNXT_FW_EXCEPTION_SP_EVENT      19
1966 #define BNXT_LINK_CFG_CHANGE_SP_EVENT   21
1967 #define BNXT_FW_ECHO_REQUEST_SP_EVENT   23
1968
1969         struct delayed_work     fw_reset_task;
1970         int                     fw_reset_state;
1971 #define BNXT_FW_RESET_STATE_POLL_VF     1
1972 #define BNXT_FW_RESET_STATE_RESET_FW    2
1973 #define BNXT_FW_RESET_STATE_ENABLE_DEV  3
1974 #define BNXT_FW_RESET_STATE_POLL_FW     4
1975 #define BNXT_FW_RESET_STATE_OPENING     5
1976 #define BNXT_FW_RESET_STATE_POLL_FW_DOWN        6
1977
1978         u16                     fw_reset_min_dsecs;
1979 #define BNXT_DFLT_FW_RST_MIN_DSECS      20
1980         u16                     fw_reset_max_dsecs;
1981 #define BNXT_DFLT_FW_RST_MAX_DSECS      60
1982         unsigned long           fw_reset_timestamp;
1983
1984         struct bnxt_fw_health   *fw_health;
1985
1986         struct bnxt_hw_resc     hw_resc;
1987         struct bnxt_pf_info     pf;
1988         struct bnxt_ctx_mem_info        *ctx;
1989 #ifdef CONFIG_BNXT_SRIOV
1990         int                     nr_vfs;
1991         struct bnxt_vf_info     vf;
1992         wait_queue_head_t       sriov_cfg_wait;
1993         bool                    sriov_cfg;
1994 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
1995
1996         /* lock to protect VF-rep creation/cleanup via
1997          * multiple paths such as ->sriov_configure() and
1998          * devlink ->eswitch_mode_set()
1999          */
2000         struct mutex            sriov_lock;
2001 #endif
2002
2003 #if BITS_PER_LONG == 32
2004         /* ensure atomic 64-bit doorbell writes on 32-bit systems. */
2005         spinlock_t              db_lock;
2006 #endif
2007         int                     db_size;
2008
2009 #define BNXT_NTP_FLTR_MAX_FLTR  4096
2010 #define BNXT_NTP_FLTR_HASH_SIZE 512
2011 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
2012         struct hlist_head       ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
2013         spinlock_t              ntp_fltr_lock;  /* for hash table add, del */
2014
2015         unsigned long           *ntp_fltr_bmap;
2016         int                     ntp_fltr_count;
2017
2018         /* To protect link related settings during link changes and
2019          * ethtool settings changes.
2020          */
2021         struct mutex            link_lock;
2022         struct bnxt_link_info   link_info;
2023         struct ethtool_eee      eee;
2024         u32                     lpi_tmr_lo;
2025         u32                     lpi_tmr_hi;
2026
2027         /* copied from flags in hwrm_port_phy_qcaps_output */
2028         u8                      phy_flags;
2029 #define BNXT_PHY_FL_EEE_CAP             PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED
2030 #define BNXT_PHY_FL_EXT_LPBK            PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED
2031 #define BNXT_PHY_FL_AN_PHY_LPBK         PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED
2032 #define BNXT_PHY_FL_SHARED_PORT_CFG     PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED
2033 #define BNXT_PHY_FL_PORT_STATS_NO_RESET PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET
2034 #define BNXT_PHY_FL_NO_PHY_LPBK         PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED
2035 #define BNXT_PHY_FL_FW_MANAGED_LKDN     PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN
2036 #define BNXT_PHY_FL_NO_FCS              PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS
2037
2038         u8                      num_tests;
2039         struct bnxt_test_info   *test_info;
2040
2041         u8                      wol_filter_id;
2042         u8                      wol;
2043
2044         u8                      num_leds;
2045         struct bnxt_led_info    leds[BNXT_MAX_LED];
2046         u16                     dump_flag;
2047 #define BNXT_DUMP_LIVE          0
2048 #define BNXT_DUMP_CRASH         1
2049
2050         struct bpf_prog         *xdp_prog;
2051
2052         struct bnxt_ptp_cfg     *ptp_cfg;
2053
2054         /* devlink interface and vf-rep structs */
2055         struct devlink          *dl;
2056         struct devlink_port     dl_port;
2057         enum devlink_eswitch_mode eswitch_mode;
2058         struct bnxt_vf_rep      **vf_reps; /* array of vf-rep ptrs */
2059         u16                     *cfa_code_map; /* cfa_code -> vf_idx map */
2060         u8                      dsn[8];
2061         struct bnxt_tc_info     *tc_info;
2062         struct list_head        tc_indr_block_list;
2063         struct dentry           *debugfs_pdev;
2064         struct device           *hwmon_dev;
2065 };
2066
2067 #define BNXT_NUM_RX_RING_STATS                  8
2068 #define BNXT_NUM_TX_RING_STATS                  8
2069 #define BNXT_NUM_TPA_RING_STATS                 4
2070 #define BNXT_NUM_TPA_RING_STATS_P5              5
2071 #define BNXT_NUM_TPA_RING_STATS_P5_SR2          6
2072
2073 #define BNXT_RING_STATS_SIZE_P5                                 \
2074         ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +     \
2075           BNXT_NUM_TPA_RING_STATS_P5) * 8)
2076
2077 #define BNXT_RING_STATS_SIZE_P5_SR2                             \
2078         ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +     \
2079           BNXT_NUM_TPA_RING_STATS_P5_SR2) * 8)
2080
2081 #define BNXT_GET_RING_STATS64(sw, counter)              \
2082         (*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))
2083
2084 #define BNXT_GET_RX_PORT_STATS64(sw, counter)           \
2085         (*((sw) + offsetof(struct rx_port_stats, counter) / 8))
2086
2087 #define BNXT_GET_TX_PORT_STATS64(sw, counter)           \
2088         (*((sw) + offsetof(struct tx_port_stats, counter) / 8))
2089
2090 #define BNXT_PORT_STATS_SIZE                            \
2091         (sizeof(struct rx_port_stats) + sizeof(struct tx_port_stats) + 1024)
2092
2093 #define BNXT_TX_PORT_STATS_BYTE_OFFSET                  \
2094         (sizeof(struct rx_port_stats) + 512)
2095
2096 #define BNXT_RX_STATS_OFFSET(counter)                   \
2097         (offsetof(struct rx_port_stats, counter) / 8)
2098
2099 #define BNXT_TX_STATS_OFFSET(counter)                   \
2100         ((offsetof(struct tx_port_stats, counter) +     \
2101           BNXT_TX_PORT_STATS_BYTE_OFFSET) / 8)
2102
2103 #define BNXT_RX_STATS_EXT_OFFSET(counter)               \
2104         (offsetof(struct rx_port_stats_ext, counter) / 8)
2105
2106 #define BNXT_TX_STATS_EXT_OFFSET(counter)               \
2107         (offsetof(struct tx_port_stats_ext, counter) / 8)
2108
2109 #define BNXT_HW_FEATURE_VLAN_ALL_RX                             \
2110         (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)
2111 #define BNXT_HW_FEATURE_VLAN_ALL_TX                             \
2112         (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX)
2113
2114 #define I2C_DEV_ADDR_A0                         0xa0
2115 #define I2C_DEV_ADDR_A2                         0xa2
2116 #define SFF_DIAG_SUPPORT_OFFSET                 0x5c
2117 #define SFF_MODULE_ID_SFP                       0x3
2118 #define SFF_MODULE_ID_QSFP                      0xc
2119 #define SFF_MODULE_ID_QSFP_PLUS                 0xd
2120 #define SFF_MODULE_ID_QSFP28                    0x11
2121 #define BNXT_MAX_PHY_I2C_RESP_SIZE              64
2122
2123 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
2124 {
2125         /* Tell compiler to fetch tx indices from memory. */
2126         barrier();
2127
2128         return bp->tx_ring_size -
2129                 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
2130 }
2131
2132 #if BITS_PER_LONG == 32
2133 #define writeq(val64, db)                       \
2134 do {                                            \
2135         spin_lock(&bp->db_lock);                \
2136         writel((val64) & 0xffffffff, db);       \
2137         writel((val64) >> 32, (db) + 4);        \
2138         spin_unlock(&bp->db_lock);              \
2139 } while (0)
2140
2141 #define writeq_relaxed writeq
2142 #endif
2143
2144 /* For TX and RX ring doorbells with no ordering guarantee*/
2145 static inline void bnxt_db_write_relaxed(struct bnxt *bp,
2146                                          struct bnxt_db_info *db, u32 idx)
2147 {
2148         if (bp->flags & BNXT_FLAG_CHIP_P5) {
2149                 writeq_relaxed(db->db_key64 | idx, db->doorbell);
2150         } else {
2151                 u32 db_val = db->db_key32 | idx;
2152
2153                 writel_relaxed(db_val, db->doorbell);
2154                 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2155                         writel_relaxed(db_val, db->doorbell);
2156         }
2157 }
2158
2159 /* For TX and RX ring doorbells */
2160 static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
2161                                  u32 idx)
2162 {
2163         if (bp->flags & BNXT_FLAG_CHIP_P5) {
2164                 writeq(db->db_key64 | idx, db->doorbell);
2165         } else {
2166                 u32 db_val = db->db_key32 | idx;
2167
2168                 writel(db_val, db->doorbell);
2169                 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2170                         writel(db_val, db->doorbell);
2171         }
2172 }
2173
2174 static inline bool bnxt_cfa_hwrm_message(u16 req_type)
2175 {
2176         switch (req_type) {
2177         case HWRM_CFA_ENCAP_RECORD_ALLOC:
2178         case HWRM_CFA_ENCAP_RECORD_FREE:
2179         case HWRM_CFA_DECAP_FILTER_ALLOC:
2180         case HWRM_CFA_DECAP_FILTER_FREE:
2181         case HWRM_CFA_EM_FLOW_ALLOC:
2182         case HWRM_CFA_EM_FLOW_FREE:
2183         case HWRM_CFA_EM_FLOW_CFG:
2184         case HWRM_CFA_FLOW_ALLOC:
2185         case HWRM_CFA_FLOW_FREE:
2186         case HWRM_CFA_FLOW_INFO:
2187         case HWRM_CFA_FLOW_FLUSH:
2188         case HWRM_CFA_FLOW_STATS:
2189         case HWRM_CFA_METER_PROFILE_ALLOC:
2190         case HWRM_CFA_METER_PROFILE_FREE:
2191         case HWRM_CFA_METER_PROFILE_CFG:
2192         case HWRM_CFA_METER_INSTANCE_ALLOC:
2193         case HWRM_CFA_METER_INSTANCE_FREE:
2194                 return true;
2195         default:
2196                 return false;
2197         }
2198 }
2199
2200 static inline bool bnxt_kong_hwrm_message(struct bnxt *bp, struct input *req)
2201 {
2202         return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&
2203                 bnxt_cfa_hwrm_message(le16_to_cpu(req->req_type)));
2204 }
2205
2206 static inline bool bnxt_hwrm_kong_chnl(struct bnxt *bp, struct input *req)
2207 {
2208         return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&
2209                 req->resp_addr == cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr));
2210 }
2211
2212 static inline void *bnxt_get_hwrm_resp_addr(struct bnxt *bp, void *req)
2213 {
2214         if (bnxt_hwrm_kong_chnl(bp, (struct input *)req))
2215                 return bp->hwrm_cmd_kong_resp_addr;
2216         else
2217                 return bp->hwrm_cmd_resp_addr;
2218 }
2219
2220 static inline u16 bnxt_get_hwrm_seq_id(struct bnxt *bp, u16 dst)
2221 {
2222         u16 seq_id;
2223
2224         if (dst == BNXT_HWRM_CHNL_CHIMP)
2225                 seq_id = bp->hwrm_cmd_seq++;
2226         else
2227                 seq_id = bp->hwrm_cmd_kong_seq++;
2228         return seq_id;
2229 }
2230
2231 extern const u16 bnxt_lhint_arr[];
2232
2233 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
2234                        u16 prod, gfp_t gfp);
2235 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
2236 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx);
2237 void bnxt_set_tpa_flags(struct bnxt *bp);
2238 void bnxt_set_ring_params(struct bnxt *);
2239 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
2240 void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16);
2241 int _hwrm_send_message(struct bnxt *, void *, u32, int);
2242 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 len, int timeout);
2243 int hwrm_send_message(struct bnxt *, void *, u32, int);
2244 int hwrm_send_message_silent(struct bnxt *, void *, u32, int);
2245 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap,
2246                             int bmap_size, bool async_only);
2247 int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings);
2248 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
2249 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
2250 int bnxt_nq_rings_in_use(struct bnxt *bp);
2251 int bnxt_hwrm_set_coal(struct bnxt *);
2252 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
2253 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);
2254 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
2255 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);
2256 int bnxt_get_avail_msix(struct bnxt *bp, int num);
2257 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
2258 void bnxt_tx_disable(struct bnxt *bp);
2259 void bnxt_tx_enable(struct bnxt *bp);
2260 int bnxt_update_link(struct bnxt *bp, bool chng_link_state);
2261 int bnxt_hwrm_set_pause(struct bnxt *);
2262 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
2263 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
2264 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
2265 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);
2266 bool bnxt_is_fw_healthy(struct bnxt *bp);
2267 int bnxt_hwrm_fw_set_time(struct bnxt *);
2268 int bnxt_open_nic(struct bnxt *, bool, bool);
2269 int bnxt_half_open_nic(struct bnxt *bp);
2270 void bnxt_half_close_nic(struct bnxt *bp);
2271 int bnxt_close_nic(struct bnxt *, bool, bool);
2272 int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
2273                          u32 *reg_buf);
2274 void bnxt_fw_exception(struct bnxt *bp);
2275 void bnxt_fw_reset(struct bnxt *bp);
2276 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
2277                      int tx_xdp);
2278 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
2279 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
2280 int bnxt_restore_pf_fw_resources(struct bnxt *bp);
2281 int bnxt_get_port_parent_id(struct net_device *dev,
2282                             struct netdev_phys_item_id *ppid);
2283 void bnxt_dim_work(struct work_struct *work);
2284 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);
2285
2286 #endif