1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2018 Broadcom Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
14 #define DRV_MODULE_NAME "bnxt_en"
16 /* DO NOT CHANGE DRV_VER_* defines
20 #define DRV_VER_MIN 10
23 #include <linux/interrupt.h>
24 #include <linux/rhashtable.h>
25 #include <linux/crash_dump.h>
26 #include <net/devlink.h>
27 #include <net/dst_metadata.h>
29 #include <linux/dim.h>
30 #ifdef CONFIG_TEE_BNXT_FW
31 #include <linux/firmware/broadcom/tee_bnxt_fw.h>
34 extern struct list_head bnxt_block_cb_list;
39 __le32 tx_bd_len_flags_type;
40 #define TX_BD_TYPE (0x3f << 0)
41 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0)
42 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0)
43 #define TX_BD_FLAGS_PACKET_END (1 << 6)
44 #define TX_BD_FLAGS_NO_CMPL (1 << 7)
45 #define TX_BD_FLAGS_BD_CNT (0x1f << 8)
46 #define TX_BD_FLAGS_BD_CNT_SHIFT 8
47 #define TX_BD_FLAGS_LHINT (3 << 13)
48 #define TX_BD_FLAGS_LHINT_SHIFT 13
49 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13)
50 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13)
51 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13)
52 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13)
53 #define TX_BD_FLAGS_COAL_NOW (1 << 15)
54 #define TX_BD_LEN (0xffff << 16)
55 #define TX_BD_LEN_SHIFT 16
62 __le32 tx_bd_hsize_lflags;
63 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0)
64 #define TX_BD_FLAGS_IP_CKSUM (1 << 1)
65 #define TX_BD_FLAGS_NO_CRC (1 << 2)
66 #define TX_BD_FLAGS_STAMP (1 << 3)
67 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4)
68 #define TX_BD_FLAGS_LSO (1 << 5)
69 #define TX_BD_FLAGS_IPID_FMT (1 << 6)
70 #define TX_BD_FLAGS_T_IPID (1 << 7)
71 #define TX_BD_HSIZE (0xff << 16)
72 #define TX_BD_HSIZE_SHIFT 16
75 __le32 tx_bd_cfa_action;
76 #define TX_BD_CFA_ACTION (0xffff << 16)
77 #define TX_BD_CFA_ACTION_SHIFT 16
79 __le32 tx_bd_cfa_meta;
80 #define TX_BD_CFA_META_MASK 0xfffffff
81 #define TX_BD_CFA_META_VID_MASK 0xfff
82 #define TX_BD_CFA_META_PRI_MASK (0xf << 12)
83 #define TX_BD_CFA_META_PRI_SHIFT 12
84 #define TX_BD_CFA_META_TPID_MASK (3 << 16)
85 #define TX_BD_CFA_META_TPID_SHIFT 16
86 #define TX_BD_CFA_META_KEY (0xf << 28)
87 #define TX_BD_CFA_META_KEY_SHIFT 28
88 #define TX_BD_CFA_META_KEY_VLAN (1 << 28)
92 __le32 rx_bd_len_flags_type;
93 #define RX_BD_TYPE (0x3f << 0)
94 #define RX_BD_TYPE_RX_PACKET_BD 0x4
95 #define RX_BD_TYPE_RX_BUFFER_BD 0x5
96 #define RX_BD_TYPE_RX_AGG_BD 0x6
97 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4)
98 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4)
99 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4)
100 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4)
101 #define RX_BD_FLAGS_SOP (1 << 6)
102 #define RX_BD_FLAGS_EOP (1 << 7)
103 #define RX_BD_FLAGS_BUFFERS (3 << 8)
104 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8)
105 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8)
106 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8)
107 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8)
108 #define RX_BD_LEN (0xffff << 16)
109 #define RX_BD_LEN_SHIFT 16
116 __le32 tx_cmp_flags_type;
117 #define CMP_TYPE (0x3f << 0)
118 #define CMP_TYPE_TX_L2_CMP 0
119 #define CMP_TYPE_RX_L2_CMP 17
120 #define CMP_TYPE_RX_AGG_CMP 18
121 #define CMP_TYPE_RX_L2_TPA_START_CMP 19
122 #define CMP_TYPE_RX_L2_TPA_END_CMP 21
123 #define CMP_TYPE_RX_TPA_AGG_CMP 22
124 #define CMP_TYPE_STATUS_CMP 32
125 #define CMP_TYPE_REMOTE_DRIVER_REQ 34
126 #define CMP_TYPE_REMOTE_DRIVER_RESP 36
127 #define CMP_TYPE_ERROR_STATUS 48
128 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
129 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL
130 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL
131 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL
132 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
134 #define TX_CMP_FLAGS_ERROR (1 << 6)
135 #define TX_CMP_FLAGS_PUSH (1 << 7)
138 __le32 tx_cmp_errors_v;
139 #define TX_CMP_V (1 << 0)
140 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1)
141 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0
142 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2
143 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4
144 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5
145 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4)
146 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5)
147 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6)
148 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7)
150 __le32 tx_cmp_unsed_3;
154 __le32 rx_cmp_len_flags_type;
155 #define RX_CMP_CMP_TYPE (0x3f << 0)
156 #define RX_CMP_FLAGS_ERROR (1 << 6)
157 #define RX_CMP_FLAGS_PLACEMENT (7 << 7)
158 #define RX_CMP_FLAGS_RSS_VALID (1 << 10)
159 #define RX_CMP_FLAGS_UNUSED (1 << 11)
160 #define RX_CMP_FLAGS_ITYPES_SHIFT 12
161 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12)
162 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12)
163 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12)
164 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12)
165 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12)
166 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12)
167 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12)
168 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12)
169 #define RX_CMP_LEN (0xffff << 16)
170 #define RX_CMP_LEN_SHIFT 16
173 __le32 rx_cmp_misc_v1;
174 #define RX_CMP_V1 (1 << 0)
175 #define RX_CMP_AGG_BUFS (0x1f << 1)
176 #define RX_CMP_AGG_BUFS_SHIFT 1
177 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9)
178 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9
179 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16)
180 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16
182 __le32 rx_cmp_rss_hash;
185 #define RX_CMP_HASH_VALID(rxcmp) \
186 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
188 #define RSS_PROFILE_ID_MASK 0x1f
190 #define RX_CMP_HASH_TYPE(rxcmp) \
191 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
192 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
195 __le32 rx_cmp_flags2;
196 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1
197 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
198 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
199 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
200 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4)
201 __le32 rx_cmp_meta_data;
202 #define RX_CMP_FLAGS2_METADATA_TCI_MASK 0xffff
203 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff
204 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000
205 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16
206 __le32 rx_cmp_cfa_code_errors_v2;
207 #define RX_CMP_V (1 << 0)
208 #define RX_CMPL_ERRORS_MASK (0x7fff << 1)
209 #define RX_CMPL_ERRORS_SFT 1
210 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
211 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
212 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1)
213 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
214 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
215 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4)
216 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5)
217 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6)
218 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7)
219 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8)
220 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9)
221 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9)
222 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9)
223 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9)
224 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9)
225 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9)
226 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9)
227 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9)
228 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12)
229 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12)
230 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12)
231 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12)
232 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12)
233 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12)
234 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12)
235 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12)
236 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
237 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12)
239 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16)
240 #define RX_CMPL_CFA_CODE_SFT 16
242 __le32 rx_cmp_unused3;
245 #define RX_CMP_L2_ERRORS \
246 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
248 #define RX_CMP_L4_CS_BITS \
249 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
251 #define RX_CMP_L4_CS_ERR_BITS \
252 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
254 #define RX_CMP_L4_CS_OK(rxcmp1) \
255 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \
256 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
258 #define RX_CMP_ENCAP(rxcmp1) \
259 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \
260 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
262 #define RX_CMP_CFA_CODE(rxcmpl1) \
263 ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) & \
264 RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
267 __le32 rx_agg_cmp_len_flags_type;
268 #define RX_AGG_CMP_TYPE (0x3f << 0)
269 #define RX_AGG_CMP_LEN (0xffff << 16)
270 #define RX_AGG_CMP_LEN_SHIFT 16
271 u32 rx_agg_cmp_opaque;
273 #define RX_AGG_CMP_V (1 << 0)
274 #define RX_AGG_CMP_AGG_ID (0xffff << 16)
275 #define RX_AGG_CMP_AGG_ID_SHIFT 16
276 __le32 rx_agg_cmp_unused;
279 #define TPA_AGG_AGG_ID(rx_agg) \
280 ((le32_to_cpu((rx_agg)->rx_agg_cmp_v) & \
281 RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT)
283 struct rx_tpa_start_cmp {
284 __le32 rx_tpa_start_cmp_len_flags_type;
285 #define RX_TPA_START_CMP_TYPE (0x3f << 0)
286 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6)
287 #define RX_TPA_START_CMP_FLAGS_SHIFT 6
288 #define RX_TPA_START_CMP_FLAGS_ERROR (0x1 << 6)
289 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7)
290 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7
291 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
292 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
293 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
294 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
295 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10)
296 #define RX_TPA_START_CMP_FLAGS_TIMESTAMP (0x1 << 11)
297 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12)
298 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12
299 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
300 #define RX_TPA_START_CMP_LEN (0xffff << 16)
301 #define RX_TPA_START_CMP_LEN_SHIFT 16
303 u32 rx_tpa_start_cmp_opaque;
304 __le32 rx_tpa_start_cmp_misc_v1;
305 #define RX_TPA_START_CMP_V1 (0x1 << 0)
306 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9)
307 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9
308 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25)
309 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25
310 #define RX_TPA_START_CMP_AGG_ID_P5 (0xffff << 16)
311 #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5 16
313 __le32 rx_tpa_start_cmp_rss_hash;
316 #define TPA_START_HASH_VALID(rx_tpa_start) \
317 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
318 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
320 #define TPA_START_HASH_TYPE(rx_tpa_start) \
321 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
322 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \
323 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
325 #define TPA_START_AGG_ID(rx_tpa_start) \
326 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
327 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
329 #define TPA_START_AGG_ID_P5(rx_tpa_start) \
330 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
331 RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5)
333 #define TPA_START_ERROR(rx_tpa_start) \
334 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
335 cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))
337 struct rx_tpa_start_cmp_ext {
338 __le32 rx_tpa_start_cmp_flags2;
339 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0)
340 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
341 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
342 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
343 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8)
344 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID (0x1 << 9)
345 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT (0x3 << 10)
346 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT 10
347 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL (0xffff << 16)
348 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT 16
350 __le32 rx_tpa_start_cmp_metadata;
351 __le32 rx_tpa_start_cmp_cfa_code_v2;
352 #define RX_TPA_START_CMP_V2 (0x1 << 0)
353 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
354 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT 1
355 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
356 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
357 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
358 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16)
359 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16
360 __le32 rx_tpa_start_cmp_hdr_info;
363 #define TPA_START_CFA_CODE(rx_tpa_start) \
364 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
365 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
367 #define TPA_START_IS_IPV6(rx_tpa_start) \
368 (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 & \
369 cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
371 #define TPA_START_ERROR_CODE(rx_tpa_start) \
372 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
373 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >> \
374 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)
376 struct rx_tpa_end_cmp {
377 __le32 rx_tpa_end_cmp_len_flags_type;
378 #define RX_TPA_END_CMP_TYPE (0x3f << 0)
379 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6)
380 #define RX_TPA_END_CMP_FLAGS_SHIFT 6
381 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7)
382 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7
383 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
384 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
385 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
386 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
387 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10)
388 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12)
389 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12
390 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
391 #define RX_TPA_END_CMP_LEN (0xffff << 16)
392 #define RX_TPA_END_CMP_LEN_SHIFT 16
394 u32 rx_tpa_end_cmp_opaque;
395 __le32 rx_tpa_end_cmp_misc_v1;
396 #define RX_TPA_END_CMP_V1 (0x1 << 0)
397 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1)
398 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1
399 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8)
400 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8
401 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16)
402 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16
403 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25)
404 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25
405 #define RX_TPA_END_CMP_AGG_ID_P5 (0xffff << 16)
406 #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5 16
408 __le32 rx_tpa_end_cmp_tsdelta;
409 #define RX_TPA_END_GRO_TS (0x1 << 31)
412 #define TPA_END_AGG_ID(rx_tpa_end) \
413 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
414 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
416 #define TPA_END_AGG_ID_P5(rx_tpa_end) \
417 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
418 RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5)
420 #define TPA_END_PAYLOAD_OFF(rx_tpa_end) \
421 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
422 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT)
424 #define TPA_END_AGG_BUFS(rx_tpa_end) \
425 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
426 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT)
428 #define TPA_END_TPA_SEGS(rx_tpa_end) \
429 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
430 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
432 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \
433 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \
434 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
436 #define TPA_END_GRO(rx_tpa_end) \
437 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \
438 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
440 #define TPA_END_GRO_TS(rx_tpa_end) \
441 (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \
442 cpu_to_le32(RX_TPA_END_GRO_TS)))
444 struct rx_tpa_end_cmp_ext {
445 __le32 rx_tpa_end_cmp_dup_acks;
446 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0)
447 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5 (0xff << 16)
448 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5 16
449 #define RX_TPA_END_CMP_AGG_BUFS_P5 (0xff << 24)
450 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5 24
452 __le32 rx_tpa_end_cmp_seg_len;
453 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0)
455 __le32 rx_tpa_end_cmp_errors_v2;
456 #define RX_TPA_END_CMP_V2 (0x1 << 0)
457 #define RX_TPA_END_CMP_ERRORS (0x3 << 1)
458 #define RX_TPA_END_CMP_ERRORS_P5 (0x7 << 1)
459 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1
460 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
461 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
462 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
463 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR (0x4 << 1)
464 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)
466 u32 rx_tpa_end_cmp_start_opaque;
469 #define TPA_END_ERRORS(rx_tpa_end_ext) \
470 ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \
471 cpu_to_le32(RX_TPA_END_CMP_ERRORS))
473 #define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext) \
474 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
475 RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >> \
476 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5)
478 #define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext) \
479 ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) & \
480 RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5)
482 #define EVENT_DATA1_RESET_NOTIFY_FATAL(data1) \
484 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
485 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL)
487 #define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1) \
489 ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC)
491 #define EVENT_DATA1_RECOVERY_ENABLED(data1) \
493 ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED)
497 #define NQ_CN_TYPE_MASK 0x3fUL
498 #define NQ_CN_TYPE_SFT 0
499 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL
500 #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION
502 __le32 cq_handle_low;
504 #define NQ_CN_V 0x1UL
505 __le32 cq_handle_high;
508 #define DB_IDX_MASK 0xffffff
509 #define DB_IDX_VALID (0x1 << 26)
510 #define DB_IRQ_DIS (0x1 << 27)
511 #define DB_KEY_TX (0x0 << 28)
512 #define DB_KEY_RX (0x1 << 28)
513 #define DB_KEY_CP (0x2 << 28)
514 #define DB_KEY_ST (0x3 << 28)
515 #define DB_KEY_TX_PUSH (0x4 << 28)
516 #define DB_LONG_TX_PUSH (0x2 << 24)
518 #define BNXT_MIN_ROCE_CP_RINGS 2
519 #define BNXT_MIN_ROCE_STAT_CTXS 1
521 /* 64-bit doorbell */
522 #define DBR_INDEX_MASK 0x0000000000ffffffULL
523 #define DBR_XID_MASK 0x000fffff00000000ULL
524 #define DBR_XID_SFT 32
525 #define DBR_PATH_L2 (0x1ULL << 56)
526 #define DBR_TYPE_SQ (0x0ULL << 60)
527 #define DBR_TYPE_RQ (0x1ULL << 60)
528 #define DBR_TYPE_SRQ (0x2ULL << 60)
529 #define DBR_TYPE_SRQ_ARM (0x3ULL << 60)
530 #define DBR_TYPE_CQ (0x4ULL << 60)
531 #define DBR_TYPE_CQ_ARMSE (0x5ULL << 60)
532 #define DBR_TYPE_CQ_ARMALL (0x6ULL << 60)
533 #define DBR_TYPE_CQ_ARMENA (0x7ULL << 60)
534 #define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60)
535 #define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60)
536 #define DBR_TYPE_NQ (0xaULL << 60)
537 #define DBR_TYPE_NQ_ARM (0xbULL << 60)
538 #define DBR_TYPE_NULL (0xfULL << 60)
540 #define DB_PF_OFFSET_P5 0x10000
541 #define DB_VF_OFFSET_P5 0x4000
543 #define INVALID_HW_RING_ID ((u16)-1)
545 /* The hardware supports certain page sizes. Use the supported page sizes
546 * to allocate the rings.
548 #if (PAGE_SHIFT < 12)
549 #define BNXT_PAGE_SHIFT 12
550 #elif (PAGE_SHIFT <= 13)
551 #define BNXT_PAGE_SHIFT PAGE_SHIFT
552 #elif (PAGE_SHIFT < 16)
553 #define BNXT_PAGE_SHIFT 13
555 #define BNXT_PAGE_SHIFT 16
558 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT)
560 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
561 #if (PAGE_SHIFT > 15)
562 #define BNXT_RX_PAGE_SHIFT 15
564 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
567 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
569 #define BNXT_MAX_MTU 9500
570 #define BNXT_MAX_PAGE_MODE_MTU \
571 ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \
574 #define BNXT_MIN_PKT_SIZE 52
576 #define BNXT_DEFAULT_RX_RING_SIZE 511
577 #define BNXT_DEFAULT_TX_RING_SIZE 511
580 #define MAX_TPA_P5 256
581 #define MAX_TPA_P5_MASK (MAX_TPA_P5 - 1)
582 #define MAX_TPA_SEGS_P5 0x3f
584 #if (BNXT_PAGE_SHIFT == 16)
585 #define MAX_RX_PAGES 1
586 #define MAX_RX_AGG_PAGES 4
587 #define MAX_TX_PAGES 1
588 #define MAX_CP_PAGES 8
590 #define MAX_RX_PAGES 8
591 #define MAX_RX_AGG_PAGES 32
592 #define MAX_TX_PAGES 8
593 #define MAX_CP_PAGES 64
596 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
597 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
598 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
600 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
601 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
603 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
605 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
606 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
608 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
610 #define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1)
611 #define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
612 #define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1)
614 #define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
615 #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1))
617 #define TX_RING(x) (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
618 #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1))
620 #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
621 #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1))
623 #define TX_CMP_VALID(txcmp, raw_cons) \
624 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \
625 !((raw_cons) & bp->cp_bit))
627 #define RX_CMP_VALID(rxcmp1, raw_cons) \
628 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
629 !((raw_cons) & bp->cp_bit))
631 #define RX_AGG_CMP_VALID(agg, raw_cons) \
632 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
633 !((raw_cons) & bp->cp_bit))
635 #define NQ_CMP_VALID(nqcmp, raw_cons) \
636 (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
638 #define TX_CMP_TYPE(txcmp) \
639 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
641 #define RX_CMP_TYPE(rxcmp) \
642 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
644 #define NEXT_RX(idx) (((idx) + 1) & bp->rx_ring_mask)
646 #define NEXT_RX_AGG(idx) (((idx) + 1) & bp->rx_agg_ring_mask)
648 #define NEXT_TX(idx) (((idx) + 1) & bp->tx_ring_mask)
650 #define ADV_RAW_CMP(idx, n) ((idx) + (n))
651 #define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1)
652 #define RING_CMP(idx) ((idx) & bp->cp_ring_mask)
653 #define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1))
655 #define BNXT_HWRM_MAX_REQ_LEN (bp->hwrm_max_req_len)
656 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
657 #define DFLT_HWRM_CMD_TIMEOUT 500
658 #define SHORT_HWRM_CMD_TIMEOUT 20
659 #define HWRM_CMD_TIMEOUT (bp->hwrm_cmd_timeout)
660 #define HWRM_RESET_TIMEOUT ((HWRM_CMD_TIMEOUT) * 4)
661 #define HWRM_COREDUMP_TIMEOUT ((HWRM_CMD_TIMEOUT) * 12)
662 #define BNXT_HWRM_REQ_MAX_SIZE 128
663 #define BNXT_HWRM_REQS_PER_PAGE (BNXT_PAGE_SIZE / \
664 BNXT_HWRM_REQ_MAX_SIZE)
665 #define HWRM_SHORT_MIN_TIMEOUT 3
666 #define HWRM_SHORT_MAX_TIMEOUT 10
667 #define HWRM_SHORT_TIMEOUT_COUNTER 5
669 #define HWRM_MIN_TIMEOUT 25
670 #define HWRM_MAX_TIMEOUT 40
672 #define HWRM_TOTAL_TIMEOUT(n) (((n) <= HWRM_SHORT_TIMEOUT_COUNTER) ? \
673 ((n) * HWRM_SHORT_MIN_TIMEOUT) : \
674 (HWRM_SHORT_TIMEOUT_COUNTER * HWRM_SHORT_MIN_TIMEOUT + \
675 ((n) - HWRM_SHORT_TIMEOUT_COUNTER) * HWRM_MIN_TIMEOUT))
677 #define HWRM_VALID_BIT_DELAY_USEC 150
679 #define BNXT_HWRM_CHNL_CHIMP 0
680 #define BNXT_HWRM_CHNL_KONG 1
682 #define BNXT_RX_EVENT 1
683 #define BNXT_AGG_EVENT 2
684 #define BNXT_TX_EVENT 4
685 #define BNXT_REDIRECT_EVENT 8
687 struct bnxt_sw_tx_bd {
690 struct xdp_frame *xdpf;
692 DEFINE_DMA_UNMAP_ADDR(mapping);
693 DEFINE_DMA_UNMAP_LEN(len);
698 unsigned short nr_frags;
703 struct bnxt_sw_rx_bd {
709 struct bnxt_sw_rx_agg_bd {
715 struct bnxt_ring_mem_info {
719 #define BNXT_RMEM_VALID_PTE_FLAG 1
720 #define BNXT_RMEM_RING_PTE_FLAG 2
721 #define BNXT_RMEM_USE_FULL_PAGE_FLAG 4
730 dma_addr_t pg_tbl_map;
736 struct bnxt_ring_struct {
737 struct bnxt_ring_mem_info ring_mem;
739 u16 fw_ring_id; /* Ring id filled by Chimp FW */
742 u16 map_idx; /* Used by cmpl rings */
750 __le32 tx_bd_len_flags_type;
752 struct tx_bd_ext txbd2;
755 struct tx_push_buffer {
756 struct tx_push_bd push_bd;
760 struct bnxt_db_info {
761 void __iomem *doorbell;
768 struct bnxt_tx_ring_info {
769 struct bnxt_napi *bnapi;
773 struct bnxt_db_info tx_db;
775 struct tx_bd *tx_desc_ring[MAX_TX_PAGES];
776 struct bnxt_sw_tx_bd *tx_buf_ring;
778 dma_addr_t tx_desc_mapping[MAX_TX_PAGES];
780 struct tx_push_buffer *tx_push;
781 dma_addr_t tx_push_mapping;
784 #define BNXT_DEV_STATE_CLOSING 0x1
787 struct bnxt_ring_struct tx_ring_struct;
790 #define BNXT_LEGACY_COAL_CMPL_PARAMS \
791 (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN | \
792 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX | \
793 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET | \
794 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE | \
795 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR | \
796 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
797 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR | \
798 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
799 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
801 #define BNXT_COAL_CMPL_ENABLES \
802 (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
803 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
804 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
805 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
807 #define BNXT_COAL_CMPL_MIN_TMR_ENABLE \
808 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
810 #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE \
811 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
813 struct bnxt_coal_cap {
816 u16 num_cmpl_dma_aggr_max;
817 u16 num_cmpl_dma_aggr_during_int_max;
818 u16 cmpl_aggr_dma_tmr_max;
819 u16 cmpl_aggr_dma_tmr_during_int_max;
820 u16 int_lat_tmr_min_max;
821 u16 int_lat_tmr_max_max;
822 u16 num_cmpl_aggr_int_max;
831 /* RING_IDLE enabled when coal ticks < idle_thresh */
837 struct bnxt_tpa_info {
842 unsigned short gso_type;
845 enum pkt_hash_types hash_type;
849 #define BNXT_TPA_L4_SIZE(hdr_info) \
850 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
852 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \
853 (((hdr_info) >> 18) & 0x1ff)
855 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \
856 (((hdr_info) >> 9) & 0x1ff)
858 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
861 u16 cfa_code; /* cfa_code in TPA start compl */
863 struct rx_agg_cmp *agg_arr;
866 #define BNXT_AGG_IDX_BMAP_SIZE (MAX_TPA_P5 / BITS_PER_LONG)
868 struct bnxt_tpa_idx_map {
869 u16 agg_id_tbl[1024];
870 unsigned long agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE];
873 struct bnxt_rx_ring_info {
874 struct bnxt_napi *bnapi;
879 struct bnxt_db_info rx_db;
880 struct bnxt_db_info rx_agg_db;
882 struct bpf_prog *xdp_prog;
884 struct rx_bd *rx_desc_ring[MAX_RX_PAGES];
885 struct bnxt_sw_rx_bd *rx_buf_ring;
887 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
888 struct bnxt_sw_rx_agg_bd *rx_agg_ring;
890 unsigned long *rx_agg_bmap;
891 u16 rx_agg_bmap_size;
893 struct page *rx_page;
894 unsigned int rx_page_offset;
896 dma_addr_t rx_desc_mapping[MAX_RX_PAGES];
897 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
899 struct bnxt_tpa_info *rx_tpa;
900 struct bnxt_tpa_idx_map *rx_tpa_idx_map;
902 struct bnxt_ring_struct rx_ring_struct;
903 struct bnxt_ring_struct rx_agg_ring_struct;
904 struct xdp_rxq_info xdp_rxq;
905 struct page_pool *page_pool;
908 struct bnxt_rx_sw_stats {
909 u64 rx_l4_csum_errors;
913 struct bnxt_cmn_sw_stats {
917 struct bnxt_sw_stats {
918 struct bnxt_rx_sw_stats rx;
919 struct bnxt_cmn_sw_stats cmn;
922 struct bnxt_stats_mem {
926 dma_addr_t hw_stats_map;
930 struct bnxt_cp_ring_info {
931 struct bnxt_napi *bnapi;
933 struct bnxt_db_info cp_db;
938 u32 last_cp_raw_cons;
940 struct bnxt_coal rx_ring_coal;
948 struct tx_cmp *cp_desc_ring[MAX_CP_PAGES];
949 struct nqe_cn *nq_desc_ring[MAX_CP_PAGES];
952 dma_addr_t cp_desc_mapping[MAX_CP_PAGES];
954 struct bnxt_stats_mem stats;
957 struct bnxt_sw_stats sw_stats;
959 struct bnxt_ring_struct cp_ring_struct;
961 struct bnxt_cp_ring_info *cp_ring_arr[2];
962 #define BNXT_RX_HDL 0
963 #define BNXT_TX_HDL 1
967 struct napi_struct napi;
971 struct bnxt_cp_ring_info cp_ring;
972 struct bnxt_rx_ring_info *rx_ring;
973 struct bnxt_tx_ring_info *tx_ring;
975 void (*tx_int)(struct bnxt *, struct bnxt_napi *,
981 #define BNXT_NAPI_FLAG_XDP 0x1
987 irq_handler_t handler;
991 char name[IFNAMSIZ + 2];
992 cpumask_var_t cpu_mask;
995 #define HWRM_RING_ALLOC_TX 0x1
996 #define HWRM_RING_ALLOC_RX 0x2
997 #define HWRM_RING_ALLOC_AGG 0x4
998 #define HWRM_RING_ALLOC_CMPL 0x8
999 #define HWRM_RING_ALLOC_NQ 0x10
1001 #define INVALID_STATS_CTX_ID -1
1003 struct bnxt_ring_grp_info {
1011 struct bnxt_vnic_info {
1012 u16 fw_vnic_id; /* returned by Chimp during alloc */
1013 #define BNXT_MAX_CTX_PER_VNIC 8
1014 u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
1016 #define BNXT_MAX_UC_ADDRS 4
1017 __le64 fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
1018 /* index 0 always dev_addr */
1019 u16 uc_filter_count;
1023 dma_addr_t rss_table_dma_addr;
1025 dma_addr_t rss_hash_key_dma_addr;
1028 #define BNXT_RSS_TABLE_ENTRIES_P5 64
1029 #define BNXT_RSS_TABLE_SIZE_P5 (BNXT_RSS_TABLE_ENTRIES_P5 * 4)
1030 #define BNXT_RSS_TABLE_MAX_TBL_P5 8
1031 #define BNXT_MAX_RSS_TABLE_SIZE_P5 \
1032 (BNXT_RSS_TABLE_SIZE_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1033 #define BNXT_MAX_RSS_TABLE_ENTRIES_P5 \
1034 (BNXT_RSS_TABLE_ENTRIES_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1041 dma_addr_t mc_list_mapping;
1042 #define BNXT_MAX_MC_ADDRS 16
1045 #define BNXT_VNIC_RSS_FLAG 1
1046 #define BNXT_VNIC_RFS_FLAG 2
1047 #define BNXT_VNIC_MCAST_FLAG 4
1048 #define BNXT_VNIC_UCAST_FLAG 8
1049 #define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10
1052 struct bnxt_hw_resc {
1053 u16 min_rsscos_ctxs;
1054 u16 max_rsscos_ctxs;
1061 u16 max_tx_sch_inputs;
1065 u16 min_hw_ring_grps;
1066 u16 max_hw_ring_grps;
1067 u16 resv_hw_ring_grps;
1081 #if defined(CONFIG_BNXT_SRIOV)
1082 struct bnxt_vf_info {
1084 u8 mac_addr[ETH_ALEN]; /* PF assigned MAC Address */
1085 u8 vf_mac_addr[ETH_ALEN]; /* VF assigned MAC address, only
1089 u16 func_qcfg_flags;
1091 #define BNXT_VF_QOS 0x1
1092 #define BNXT_VF_SPOOFCHK 0x2
1093 #define BNXT_VF_LINK_FORCED 0x4
1094 #define BNXT_VF_LINK_UP 0x8
1095 #define BNXT_VF_TRUST 0x10
1098 void *hwrm_cmd_req_addr;
1099 dma_addr_t hwrm_cmd_req_dma_addr;
1103 struct bnxt_pf_info {
1104 #define BNXT_FIRST_PF_FID 1
1105 #define BNXT_FIRST_VF_FID 128
1108 u8 mac_addr[ETH_ALEN];
1113 u32 max_encap_records;
1114 u32 max_decap_records;
1115 u32 max_tx_em_flows;
1116 u32 max_tx_wm_flows;
1117 u32 max_rx_em_flows;
1118 u32 max_rx_wm_flows;
1119 unsigned long *vf_event_bmap;
1120 u16 hwrm_cmd_req_pages;
1121 u8 vf_resv_strategy;
1122 #define BNXT_VF_RESV_STRATEGY_MAXIMAL 0
1123 #define BNXT_VF_RESV_STRATEGY_MINIMAL 1
1124 #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC 2
1125 void *hwrm_cmd_req_addr[4];
1126 dma_addr_t hwrm_cmd_req_dma_addr[4];
1127 struct bnxt_vf_info *vf;
1130 struct bnxt_ntuple_filter {
1131 struct hlist_node hash;
1132 u8 dst_mac_addr[ETH_ALEN];
1133 u8 src_mac_addr[ETH_ALEN];
1134 struct flow_keys fkeys;
1140 unsigned long state;
1141 #define BNXT_FLTR_VALID 0
1142 #define BNXT_FLTR_UPDATE 1
1145 struct hwrm_port_phy_qcfg_output_compat {
1151 u8 link_signal_mode;
1155 __le16 support_speeds;
1156 __le16 force_link_speed;
1159 __le16 auto_link_speed;
1160 __le16 auto_link_speed_mask;
1172 u8 eee_config_phy_addr;
1174 __le16 link_partner_adv_speeds;
1175 u8 link_partner_adv_auto_mode;
1176 u8 link_partner_adv_pause;
1177 __le16 adv_eee_link_speed_mask;
1178 __le16 link_partner_adv_eee_link_speed_mask;
1179 __le32 xcvr_identifier_type_tx_lpi_timer;
1183 char phy_vendor_name[16];
1184 char phy_vendor_partnumber[16];
1189 struct bnxt_link_info {
1195 #define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK
1196 #define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL
1197 #define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK
1202 #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1203 #define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1205 #define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX
1206 #define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX
1207 #define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \
1208 PORT_PHY_QCFG_RESP_PAUSE_TX)
1210 u8 auto_pause_setting;
1211 u8 force_pause_setting;
1214 #define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \
1215 (mode) <= BNXT_LINK_AUTO_MSK)
1216 #define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1217 #define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1218 #define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1219 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
1220 #define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1221 #define PHY_VER_LEN 3
1222 u8 phy_ver[PHY_VER_LEN];
1224 #define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1225 #define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1226 #define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1227 #define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1228 #define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1229 #define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1230 #define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1231 #define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1232 #define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
1233 #define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1235 u16 auto_link_speeds; /* fw adv setting */
1236 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1237 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1238 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1239 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1240 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1241 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1242 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1243 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1244 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
1245 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1246 u16 support_auto_speeds;
1247 u16 lp_auto_link_speeds;
1248 u16 force_link_speed;
1252 #define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
1253 #define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
1254 #define BNXT_FEC_ENC_RS PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED
1256 /* copy of requested setting from ethtool cmd */
1258 #define BNXT_AUTONEG_SPEED 1
1259 #define BNXT_AUTONEG_FLOW_CTRL 2
1263 u16 advertising; /* user adv setting */
1264 bool force_link_chng;
1267 unsigned long phy_retry_expires;
1269 /* a copy of phy_qcfg output used to report link
1272 struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
1275 #define BNXT_MAX_QUEUE 8
1277 struct bnxt_queue_info {
1282 #define BNXT_MAX_LED 4
1284 struct bnxt_led_info {
1289 __le16 led_state_caps;
1290 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
1291 cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
1293 __le16 led_color_caps;
1296 #define BNXT_MAX_TEST 8
1298 struct bnxt_test_info {
1301 #define BNXT_TEST_FL_EXT_LPBK 0x1
1302 #define BNXT_TEST_FL_AN_PHY_LPBK 0x2
1304 char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1307 #define CHIMP_REG_VIEW_ADDR \
1308 ((bp->flags & BNXT_FLAG_CHIP_P5) ? 0x80000000 : 0xb1000000)
1310 #define BNXT_GRCPF_REG_CHIMP_COMM 0x0
1311 #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
1312 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
1313 #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014
1314 #define BNXT_CAG_REG_BASE 0x300000
1316 #define BNXT_GRCPF_REG_KONG_COMM 0xA00
1317 #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00
1319 #define BNXT_GRC_BASE_MASK 0xfffff000
1320 #define BNXT_GRC_OFFSET_MASK 0x00000ffc
1322 struct bnxt_tc_flow_stats {
1327 #ifdef CONFIG_BNXT_FLOWER_OFFLOAD
1328 struct bnxt_flower_indr_block_cb_priv {
1329 struct net_device *tunnel_netdev;
1331 struct list_head list;
1335 struct bnxt_tc_info {
1338 /* hash table to store TC offloaded flows */
1339 struct rhashtable flow_table;
1340 struct rhashtable_params flow_ht_params;
1342 /* hash table to store L2 keys of TC flows */
1343 struct rhashtable l2_table;
1344 struct rhashtable_params l2_ht_params;
1345 /* hash table to store L2 keys for TC tunnel decap */
1346 struct rhashtable decap_l2_table;
1347 struct rhashtable_params decap_l2_ht_params;
1348 /* hash table to store tunnel decap entries */
1349 struct rhashtable decap_table;
1350 struct rhashtable_params decap_ht_params;
1351 /* hash table to store tunnel encap entries */
1352 struct rhashtable encap_table;
1353 struct rhashtable_params encap_ht_params;
1355 /* lock to atomically add/del an l2 node when a flow is
1360 /* Fields used for batching stats query */
1361 struct rhashtable_iter iter;
1362 #define BNXT_FLOW_STATS_BATCH_MAX 10
1363 struct bnxt_tc_stats_batch {
1365 struct bnxt_tc_flow_stats hw_stats;
1366 } stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
1368 /* Stat counter mask (width) */
1373 struct bnxt_vf_rep_stats {
1379 struct bnxt_vf_rep {
1381 struct net_device *dev;
1382 struct metadata_dst *dst;
1387 struct bnxt_vf_rep_stats rx_stats;
1388 struct bnxt_vf_rep_stats tx_stats;
1391 #define PTU_PTE_VALID 0x1UL
1392 #define PTU_PTE_LAST 0x2UL
1393 #define PTU_PTE_NEXT_TO_LAST 0x4UL
1395 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
1396 #define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES)
1398 struct bnxt_ctx_pg_info {
1401 void *ctx_pg_arr[MAX_CTX_PAGES];
1402 dma_addr_t ctx_dma_arr[MAX_CTX_PAGES];
1403 struct bnxt_ring_mem_info ring_mem;
1404 struct bnxt_ctx_pg_info **ctx_pg_tbl;
1407 struct bnxt_ctx_mem_info {
1409 u16 qp_min_qp1_entries;
1410 u16 qp_max_l2_entries;
1412 u16 srq_max_l2_entries;
1413 u32 srq_max_entries;
1415 u16 cq_max_l2_entries;
1418 u16 vnic_max_vnic_entries;
1419 u16 vnic_max_ring_table_entries;
1420 u16 vnic_entry_size;
1421 u32 stat_max_entries;
1422 u16 stat_entry_size;
1424 u32 tqm_min_entries_per_ring;
1425 u32 tqm_max_entries_per_ring;
1426 u32 mrav_max_entries;
1427 u16 mrav_entry_size;
1429 u32 tim_max_entries;
1430 u16 mrav_num_entries_units;
1431 u8 tqm_entries_multiple;
1432 u8 ctx_kind_initializer;
1433 u8 tqm_fp_rings_count;
1436 #define BNXT_CTX_FLAG_INITED 0x01
1438 struct bnxt_ctx_pg_info qp_mem;
1439 struct bnxt_ctx_pg_info srq_mem;
1440 struct bnxt_ctx_pg_info cq_mem;
1441 struct bnxt_ctx_pg_info vnic_mem;
1442 struct bnxt_ctx_pg_info stat_mem;
1443 struct bnxt_ctx_pg_info mrav_mem;
1444 struct bnxt_ctx_pg_info tim_mem;
1445 struct bnxt_ctx_pg_info *tqm_mem[9];
1448 struct bnxt_fw_health {
1451 u32 master_func_wait_dsecs;
1452 u32 normal_func_wait_dsecs;
1453 u32 post_reset_wait_dsecs;
1454 u32 post_reset_max_wait_dsecs;
1457 #define BNXT_FW_HEALTH_REG 0
1458 #define BNXT_FW_HEARTBEAT_REG 1
1459 #define BNXT_FW_RESET_CNT_REG 2
1460 #define BNXT_FW_RESET_INPROG_REG 3
1461 u32 fw_reset_inprog_reg_mask;
1462 u32 last_fw_heartbeat;
1463 u32 last_fw_reset_cnt;
1469 u8 fw_reset_seq_cnt;
1470 u32 fw_reset_seq_regs[16];
1471 u32 fw_reset_seq_vals[16];
1472 u32 fw_reset_seq_delay_msec[16];
1473 struct devlink_health_reporter *fw_reporter;
1474 struct devlink_health_reporter *fw_reset_reporter;
1475 struct devlink_health_reporter *fw_fatal_reporter;
1478 struct bnxt_fw_reporter_ctx {
1479 unsigned long sp_event;
1482 #define BNXT_FW_HEALTH_REG_TYPE_MASK 3
1483 #define BNXT_FW_HEALTH_REG_TYPE_CFG 0
1484 #define BNXT_FW_HEALTH_REG_TYPE_GRC 1
1485 #define BNXT_FW_HEALTH_REG_TYPE_BAR0 2
1486 #define BNXT_FW_HEALTH_REG_TYPE_BAR1 3
1488 #define BNXT_FW_HEALTH_REG_TYPE(reg) ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)
1489 #define BNXT_FW_HEALTH_REG_OFF(reg) ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)
1491 #define BNXT_FW_HEALTH_WIN_BASE 0x3000
1492 #define BNXT_FW_HEALTH_WIN_MAP_OFF 8
1494 #define BNXT_FW_STATUS_HEALTHY 0x8000
1495 #define BNXT_FW_STATUS_SHUTDOWN 0x100000
1504 #define CHIP_NUM_57301 0x16c8
1505 #define CHIP_NUM_57302 0x16c9
1506 #define CHIP_NUM_57304 0x16ca
1507 #define CHIP_NUM_58700 0x16cd
1508 #define CHIP_NUM_57402 0x16d0
1509 #define CHIP_NUM_57404 0x16d1
1510 #define CHIP_NUM_57406 0x16d2
1511 #define CHIP_NUM_57407 0x16d5
1513 #define CHIP_NUM_57311 0x16ce
1514 #define CHIP_NUM_57312 0x16cf
1515 #define CHIP_NUM_57314 0x16df
1516 #define CHIP_NUM_57317 0x16e0
1517 #define CHIP_NUM_57412 0x16d6
1518 #define CHIP_NUM_57414 0x16d7
1519 #define CHIP_NUM_57416 0x16d8
1520 #define CHIP_NUM_57417 0x16d9
1521 #define CHIP_NUM_57412L 0x16da
1522 #define CHIP_NUM_57414L 0x16db
1524 #define CHIP_NUM_5745X 0xd730
1525 #define CHIP_NUM_57452 0xc452
1526 #define CHIP_NUM_57454 0xc454
1528 #define CHIP_NUM_57508 0x1750
1529 #define CHIP_NUM_57504 0x1751
1530 #define CHIP_NUM_57502 0x1752
1532 #define CHIP_NUM_58802 0xd802
1533 #define CHIP_NUM_58804 0xd804
1534 #define CHIP_NUM_58808 0xd808
1538 #define BNXT_CHIP_NUM_5730X(chip_num) \
1539 ((chip_num) >= CHIP_NUM_57301 && \
1540 (chip_num) <= CHIP_NUM_57304)
1542 #define BNXT_CHIP_NUM_5740X(chip_num) \
1543 (((chip_num) >= CHIP_NUM_57402 && \
1544 (chip_num) <= CHIP_NUM_57406) || \
1545 (chip_num) == CHIP_NUM_57407)
1547 #define BNXT_CHIP_NUM_5731X(chip_num) \
1548 ((chip_num) == CHIP_NUM_57311 || \
1549 (chip_num) == CHIP_NUM_57312 || \
1550 (chip_num) == CHIP_NUM_57314 || \
1551 (chip_num) == CHIP_NUM_57317)
1553 #define BNXT_CHIP_NUM_5741X(chip_num) \
1554 ((chip_num) >= CHIP_NUM_57412 && \
1555 (chip_num) <= CHIP_NUM_57414L)
1557 #define BNXT_CHIP_NUM_58700(chip_num) \
1558 ((chip_num) == CHIP_NUM_58700)
1560 #define BNXT_CHIP_NUM_5745X(chip_num) \
1561 ((chip_num) == CHIP_NUM_5745X || \
1562 (chip_num) == CHIP_NUM_57452 || \
1563 (chip_num) == CHIP_NUM_57454)
1566 #define BNXT_CHIP_NUM_57X0X(chip_num) \
1567 (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
1569 #define BNXT_CHIP_NUM_57X1X(chip_num) \
1570 (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
1572 #define BNXT_CHIP_NUM_588XX(chip_num) \
1573 ((chip_num) == CHIP_NUM_58802 || \
1574 (chip_num) == CHIP_NUM_58804 || \
1575 (chip_num) == CHIP_NUM_58808)
1577 #define BNXT_VPD_FLD_LEN 32
1578 char board_partno[BNXT_VPD_FLD_LEN];
1579 char board_serialno[BNXT_VPD_FLD_LEN];
1581 struct net_device *dev;
1582 struct pci_dev *pdev;
1587 #define BNXT_FLAG_CHIP_P5 0x1
1588 #define BNXT_FLAG_VF 0x2
1589 #define BNXT_FLAG_LRO 0x4
1591 #define BNXT_FLAG_GRO 0x8
1593 /* Cannot support hardware GRO if CONFIG_INET is not set */
1594 #define BNXT_FLAG_GRO 0x0
1596 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
1597 #define BNXT_FLAG_JUMBO 0x10
1598 #define BNXT_FLAG_STRIP_VLAN 0x20
1599 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
1601 #define BNXT_FLAG_USING_MSIX 0x40
1602 #define BNXT_FLAG_MSIX_CAP 0x80
1603 #define BNXT_FLAG_RFS 0x100
1604 #define BNXT_FLAG_SHARED_RINGS 0x200
1605 #define BNXT_FLAG_PORT_STATS 0x400
1606 #define BNXT_FLAG_UDP_RSS_CAP 0x800
1607 #define BNXT_FLAG_EEE_CAP 0x1000
1608 #define BNXT_FLAG_NEW_RSS_CAP 0x2000
1609 #define BNXT_FLAG_WOL_CAP 0x4000
1610 #define BNXT_FLAG_ROCEV1_CAP 0x8000
1611 #define BNXT_FLAG_ROCEV2_CAP 0x10000
1612 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \
1613 BNXT_FLAG_ROCEV2_CAP)
1614 #define BNXT_FLAG_NO_AGG_RINGS 0x20000
1615 #define BNXT_FLAG_RX_PAGE_MODE 0x40000
1616 #define BNXT_FLAG_MULTI_HOST 0x100000
1617 #define BNXT_FLAG_DSN_VALID 0x200000
1618 #define BNXT_FLAG_DOUBLE_DB 0x400000
1619 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
1620 #define BNXT_FLAG_DIM 0x2000000
1621 #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000
1622 #define BNXT_FLAG_PORT_STATS_EXT 0x10000000
1624 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \
1626 BNXT_FLAG_STRIP_VLAN)
1628 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
1629 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
1630 #define BNXT_NPAR(bp) ((bp)->port_partition_type)
1631 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
1632 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
1633 #define BNXT_PHY_CFG_ABLE(bp) (BNXT_SINGLE_PF(bp) || \
1634 ((bp)->fw_cap & BNXT_FW_CAP_SHARED_PORT_CFG))
1635 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1636 #define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1637 #define BNXT_SUPPORTS_TPA(bp) (!BNXT_CHIP_TYPE_NITRO_A0(bp) && \
1638 (!((bp)->flags & BNXT_FLAG_CHIP_P5) || \
1639 (bp)->max_tpa_v2) && !is_kdump_kernel())
1641 /* Chip class phase 5 */
1642 #define BNXT_CHIP_P5(bp) \
1643 ((bp)->chip_num == CHIP_NUM_57508 || \
1644 (bp)->chip_num == CHIP_NUM_57504 || \
1645 (bp)->chip_num == CHIP_NUM_57502)
1647 /* Chip class phase 4.x */
1648 #define BNXT_CHIP_P4(bp) \
1649 (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
1650 BNXT_CHIP_NUM_5745X((bp)->chip_num) || \
1651 BNXT_CHIP_NUM_588XX((bp)->chip_num) || \
1652 (BNXT_CHIP_NUM_58700((bp)->chip_num) && \
1653 !BNXT_CHIP_TYPE_NITRO_A0(bp)))
1655 #define BNXT_CHIP_P4_PLUS(bp) \
1656 (BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))
1658 struct bnxt_en_dev *edev;
1659 struct bnxt_en_dev * (*ulp_probe)(struct net_device *);
1661 struct bnxt_napi **bnapi;
1663 struct bnxt_rx_ring_info *rx_ring;
1664 struct bnxt_tx_ring_info *tx_ring;
1667 struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int,
1670 struct sk_buff * (*rx_skb_func)(struct bnxt *,
1671 struct bnxt_rx_ring_info *,
1672 u16, void *, u8 *, dma_addr_t,
1678 u32 rx_buf_use_size; /* useable size */
1681 enum dma_data_direction rx_dir;
1683 u32 rx_agg_ring_size;
1686 u32 rx_agg_ring_mask;
1688 int rx_agg_nr_pages;
1696 int tx_nr_rings_per_tc;
1697 int tx_nr_rings_xdp;
1709 /* grp_info indexed by completion ring index */
1710 struct bnxt_ring_grp_info *grp_info;
1711 struct bnxt_vnic_info *vnic_info;
1714 u16 rss_indir_tbl_entries;
1719 u8 max_lltc; /* lossless TCs */
1720 struct bnxt_queue_info q_info[BNXT_MAX_QUEUE];
1721 u8 tc_to_qidx[BNXT_MAX_QUEUE];
1722 u8 q_ids[BNXT_MAX_QUEUE];
1725 unsigned int current_interval;
1726 #define BNXT_TIMER_INTERVAL HZ
1728 struct timer_list timer;
1730 unsigned long state;
1731 #define BNXT_STATE_OPEN 0
1732 #define BNXT_STATE_IN_SP_TASK 1
1733 #define BNXT_STATE_READ_STATS 2
1734 #define BNXT_STATE_FW_RESET_DET 3
1735 #define BNXT_STATE_IN_FW_RESET 4
1736 #define BNXT_STATE_ABORT_ERR 5
1737 #define BNXT_STATE_FW_FATAL_COND 6
1738 #define BNXT_STATE_DRV_REGISTERED 7
1740 #define BNXT_NO_FW_ACCESS(bp) \
1741 (test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) || \
1742 pci_channel_offline((bp)->pdev))
1744 struct bnxt_irq *irq_tbl;
1746 u8 mac_addr[ETH_ALEN];
1748 #ifdef CONFIG_BNXT_DCB
1749 struct ieee_pfc *ieee_pfc;
1750 struct ieee_ets *ieee_ets;
1754 #endif /* CONFIG_BNXT_DCB */
1759 #define BNXT_FW_CAP_SHORT_CMD 0x00000001
1760 #define BNXT_FW_CAP_LLDP_AGENT 0x00000002
1761 #define BNXT_FW_CAP_DCBX_AGENT 0x00000004
1762 #define BNXT_FW_CAP_NEW_RM 0x00000008
1763 #define BNXT_FW_CAP_IF_CHANGE 0x00000010
1764 #define BNXT_FW_CAP_KONG_MB_CHNL 0x00000080
1765 #define BNXT_FW_CAP_OVS_64BIT_HANDLE 0x00000400
1766 #define BNXT_FW_CAP_TRUSTED_VF 0x00000800
1767 #define BNXT_FW_CAP_ERROR_RECOVERY 0x00002000
1768 #define BNXT_FW_CAP_PKG_VER 0x00004000
1769 #define BNXT_FW_CAP_CFA_ADV_FLOW 0x00008000
1770 #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 0x00010000
1771 #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED 0x00020000
1772 #define BNXT_FW_CAP_EXT_STATS_SUPPORTED 0x00040000
1773 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD 0x00100000
1774 #define BNXT_FW_CAP_HOT_RESET 0x00200000
1775 #define BNXT_FW_CAP_SHARED_PORT_CFG 0x00400000
1776 #define BNXT_FW_CAP_VLAN_RX_STRIP 0x01000000
1777 #define BNXT_FW_CAP_VLAN_TX_INSERT 0x02000000
1778 #define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED 0x04000000
1779 #define BNXT_FW_CAP_PORT_STATS_NO_RESET 0x10000000
1781 #define BNXT_NEW_RM(bp) ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
1784 u16 hwrm_cmd_kong_seq;
1785 u16 hwrm_intr_seq_id;
1786 void *hwrm_short_cmd_req_addr;
1787 dma_addr_t hwrm_short_cmd_req_dma_addr;
1788 void *hwrm_cmd_resp_addr;
1789 dma_addr_t hwrm_cmd_resp_dma_addr;
1790 void *hwrm_cmd_kong_resp_addr;
1791 dma_addr_t hwrm_cmd_kong_resp_dma_addr;
1793 struct rtnl_link_stats64 net_stats_prev;
1794 struct bnxt_stats_mem port_stats;
1795 struct bnxt_stats_mem rx_port_stats_ext;
1796 struct bnxt_stats_mem tx_port_stats_ext;
1797 u16 fw_rx_stats_ext_size;
1798 u16 fw_tx_stats_ext_size;
1799 u16 hw_ring_stats_size;
1803 u16 hwrm_max_req_len;
1804 u16 hwrm_max_ext_req_len;
1805 int hwrm_cmd_timeout;
1806 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */
1807 struct hwrm_ver_get_output ver_resp;
1808 #define FW_VER_STR_LEN 32
1809 #define BC_HWRM_STR_LEN 21
1810 #define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
1811 char fw_ver_str[FW_VER_STR_LEN];
1812 char hwrm_ver_supp[FW_VER_STR_LEN];
1814 #define BNXT_FW_VER_CODE(maj, min, bld, rsv) \
1815 ((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv))
1816 #define BNXT_FW_MAJ(bp) ((bp)->fw_ver_code >> 48)
1818 u16 vxlan_fw_dst_port_id;
1819 u16 nge_fw_dst_port_id;
1820 u8 port_partition_type;
1824 struct bnxt_coal_cap coal_cap;
1825 struct bnxt_coal rx_coal;
1826 struct bnxt_coal tx_coal;
1828 u32 stats_coal_ticks;
1829 #define BNXT_DEF_STATS_COAL_TICKS 1000000
1830 #define BNXT_MIN_STATS_COAL_TICKS 250000
1831 #define BNXT_MAX_STATS_COAL_TICKS 1000000
1833 struct work_struct sp_task;
1834 unsigned long sp_event;
1835 #define BNXT_RX_MASK_SP_EVENT 0
1836 #define BNXT_RX_NTP_FLTR_SP_EVENT 1
1837 #define BNXT_LINK_CHNG_SP_EVENT 2
1838 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
1839 #define BNXT_RESET_TASK_SP_EVENT 6
1840 #define BNXT_RST_RING_SP_EVENT 7
1841 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8
1842 #define BNXT_PERIODIC_STATS_SP_EVENT 9
1843 #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10
1844 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11
1845 #define BNXT_LINK_SPEED_CHNG_SP_EVENT 14
1846 #define BNXT_FLOW_STATS_SP_EVENT 15
1847 #define BNXT_UPDATE_PHY_SP_EVENT 16
1848 #define BNXT_RING_COAL_NOW_SP_EVENT 17
1849 #define BNXT_FW_RESET_NOTIFY_SP_EVENT 18
1850 #define BNXT_FW_EXCEPTION_SP_EVENT 19
1851 #define BNXT_LINK_CFG_CHANGE_SP_EVENT 21
1853 struct delayed_work fw_reset_task;
1855 #define BNXT_FW_RESET_STATE_POLL_VF 1
1856 #define BNXT_FW_RESET_STATE_RESET_FW 2
1857 #define BNXT_FW_RESET_STATE_ENABLE_DEV 3
1858 #define BNXT_FW_RESET_STATE_POLL_FW 4
1859 #define BNXT_FW_RESET_STATE_OPENING 5
1860 #define BNXT_FW_RESET_STATE_POLL_FW_DOWN 6
1862 u16 fw_reset_min_dsecs;
1863 #define BNXT_DFLT_FW_RST_MIN_DSECS 20
1864 u16 fw_reset_max_dsecs;
1865 #define BNXT_DFLT_FW_RST_MAX_DSECS 60
1866 unsigned long fw_reset_timestamp;
1868 struct bnxt_fw_health *fw_health;
1870 struct bnxt_hw_resc hw_resc;
1871 struct bnxt_pf_info pf;
1872 struct bnxt_ctx_mem_info *ctx;
1873 #ifdef CONFIG_BNXT_SRIOV
1875 struct bnxt_vf_info vf;
1876 wait_queue_head_t sriov_cfg_wait;
1878 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
1880 /* lock to protect VF-rep creation/cleanup via
1881 * multiple paths such as ->sriov_configure() and
1882 * devlink ->eswitch_mode_set()
1884 struct mutex sriov_lock;
1887 #if BITS_PER_LONG == 32
1888 /* ensure atomic 64-bit doorbell writes on 32-bit systems. */
1893 #define BNXT_NTP_FLTR_MAX_FLTR 4096
1894 #define BNXT_NTP_FLTR_HASH_SIZE 512
1895 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
1896 struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
1897 spinlock_t ntp_fltr_lock; /* for hash table add, del */
1899 unsigned long *ntp_fltr_bmap;
1902 /* To protect link related settings during link changes and
1903 * ethtool settings changes.
1905 struct mutex link_lock;
1906 struct bnxt_link_info link_info;
1907 struct ethtool_eee eee;
1912 struct bnxt_test_info *test_info;
1918 struct bnxt_led_info leds[BNXT_MAX_LED];
1920 #define BNXT_DUMP_LIVE 0
1921 #define BNXT_DUMP_CRASH 1
1923 struct bpf_prog *xdp_prog;
1925 /* devlink interface and vf-rep structs */
1927 struct devlink_port dl_port;
1928 enum devlink_eswitch_mode eswitch_mode;
1929 struct bnxt_vf_rep **vf_reps; /* array of vf-rep ptrs */
1930 u16 *cfa_code_map; /* cfa_code -> vf_idx map */
1932 struct bnxt_tc_info *tc_info;
1933 struct list_head tc_indr_block_list;
1934 struct dentry *debugfs_pdev;
1935 struct device *hwmon_dev;
1938 #define BNXT_GET_RING_STATS64(sw, counter) \
1939 (*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))
1941 #define BNXT_GET_RX_PORT_STATS64(sw, counter) \
1942 (*((sw) + offsetof(struct rx_port_stats, counter) / 8))
1944 #define BNXT_GET_TX_PORT_STATS64(sw, counter) \
1945 (*((sw) + offsetof(struct tx_port_stats, counter) / 8))
1947 #define BNXT_PORT_STATS_SIZE \
1948 (sizeof(struct rx_port_stats) + sizeof(struct tx_port_stats) + 1024)
1950 #define BNXT_TX_PORT_STATS_BYTE_OFFSET \
1951 (sizeof(struct rx_port_stats) + 512)
1953 #define BNXT_RX_STATS_OFFSET(counter) \
1954 (offsetof(struct rx_port_stats, counter) / 8)
1956 #define BNXT_TX_STATS_OFFSET(counter) \
1957 ((offsetof(struct tx_port_stats, counter) + \
1958 BNXT_TX_PORT_STATS_BYTE_OFFSET) / 8)
1960 #define BNXT_RX_STATS_EXT_OFFSET(counter) \
1961 (offsetof(struct rx_port_stats_ext, counter) / 8)
1963 #define BNXT_TX_STATS_EXT_OFFSET(counter) \
1964 (offsetof(struct tx_port_stats_ext, counter) / 8)
1966 #define BNXT_HW_FEATURE_VLAN_ALL_RX \
1967 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)
1968 #define BNXT_HW_FEATURE_VLAN_ALL_TX \
1969 (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX)
1971 #define I2C_DEV_ADDR_A0 0xa0
1972 #define I2C_DEV_ADDR_A2 0xa2
1973 #define SFF_DIAG_SUPPORT_OFFSET 0x5c
1974 #define SFF_MODULE_ID_SFP 0x3
1975 #define SFF_MODULE_ID_QSFP 0xc
1976 #define SFF_MODULE_ID_QSFP_PLUS 0xd
1977 #define SFF_MODULE_ID_QSFP28 0x11
1978 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64
1980 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
1982 /* Tell compiler to fetch tx indices from memory. */
1985 return bp->tx_ring_size -
1986 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
1989 #if BITS_PER_LONG == 32
1990 #define writeq(val64, db) \
1992 spin_lock(&bp->db_lock); \
1993 writel((val64) & 0xffffffff, db); \
1994 writel((val64) >> 32, (db) + 4); \
1995 spin_unlock(&bp->db_lock); \
1998 #define writeq_relaxed writeq
2001 /* For TX and RX ring doorbells with no ordering guarantee*/
2002 static inline void bnxt_db_write_relaxed(struct bnxt *bp,
2003 struct bnxt_db_info *db, u32 idx)
2005 if (bp->flags & BNXT_FLAG_CHIP_P5) {
2006 writeq_relaxed(db->db_key64 | idx, db->doorbell);
2008 u32 db_val = db->db_key32 | idx;
2010 writel_relaxed(db_val, db->doorbell);
2011 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2012 writel_relaxed(db_val, db->doorbell);
2016 /* For TX and RX ring doorbells */
2017 static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
2020 if (bp->flags & BNXT_FLAG_CHIP_P5) {
2021 writeq(db->db_key64 | idx, db->doorbell);
2023 u32 db_val = db->db_key32 | idx;
2025 writel(db_val, db->doorbell);
2026 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2027 writel(db_val, db->doorbell);
2031 static inline bool bnxt_cfa_hwrm_message(u16 req_type)
2034 case HWRM_CFA_ENCAP_RECORD_ALLOC:
2035 case HWRM_CFA_ENCAP_RECORD_FREE:
2036 case HWRM_CFA_DECAP_FILTER_ALLOC:
2037 case HWRM_CFA_DECAP_FILTER_FREE:
2038 case HWRM_CFA_EM_FLOW_ALLOC:
2039 case HWRM_CFA_EM_FLOW_FREE:
2040 case HWRM_CFA_EM_FLOW_CFG:
2041 case HWRM_CFA_FLOW_ALLOC:
2042 case HWRM_CFA_FLOW_FREE:
2043 case HWRM_CFA_FLOW_INFO:
2044 case HWRM_CFA_FLOW_FLUSH:
2045 case HWRM_CFA_FLOW_STATS:
2046 case HWRM_CFA_METER_PROFILE_ALLOC:
2047 case HWRM_CFA_METER_PROFILE_FREE:
2048 case HWRM_CFA_METER_PROFILE_CFG:
2049 case HWRM_CFA_METER_INSTANCE_ALLOC:
2050 case HWRM_CFA_METER_INSTANCE_FREE:
2057 static inline bool bnxt_kong_hwrm_message(struct bnxt *bp, struct input *req)
2059 return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&
2060 bnxt_cfa_hwrm_message(le16_to_cpu(req->req_type)));
2063 static inline bool bnxt_hwrm_kong_chnl(struct bnxt *bp, struct input *req)
2065 return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&
2066 req->resp_addr == cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr));
2069 static inline void *bnxt_get_hwrm_resp_addr(struct bnxt *bp, void *req)
2071 if (bnxt_hwrm_kong_chnl(bp, (struct input *)req))
2072 return bp->hwrm_cmd_kong_resp_addr;
2074 return bp->hwrm_cmd_resp_addr;
2077 static inline u16 bnxt_get_hwrm_seq_id(struct bnxt *bp, u16 dst)
2081 if (dst == BNXT_HWRM_CHNL_CHIMP)
2082 seq_id = bp->hwrm_cmd_seq++;
2084 seq_id = bp->hwrm_cmd_kong_seq++;
2088 extern const u16 bnxt_lhint_arr[];
2090 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
2091 u16 prod, gfp_t gfp);
2092 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
2093 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx);
2094 void bnxt_set_tpa_flags(struct bnxt *bp);
2095 void bnxt_set_ring_params(struct bnxt *);
2096 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
2097 void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16);
2098 int _hwrm_send_message(struct bnxt *, void *, u32, int);
2099 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 len, int timeout);
2100 int hwrm_send_message(struct bnxt *, void *, u32, int);
2101 int hwrm_send_message_silent(struct bnxt *, void *, u32, int);
2102 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap,
2103 int bmap_size, bool async_only);
2104 int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings);
2105 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
2106 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
2107 int bnxt_nq_rings_in_use(struct bnxt *bp);
2108 int bnxt_hwrm_set_coal(struct bnxt *);
2109 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
2110 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);
2111 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
2112 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);
2113 int bnxt_get_avail_msix(struct bnxt *bp, int num);
2114 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
2115 void bnxt_tx_disable(struct bnxt *bp);
2116 void bnxt_tx_enable(struct bnxt *bp);
2117 int bnxt_hwrm_set_pause(struct bnxt *);
2118 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
2119 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
2120 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
2121 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);
2122 int bnxt_hwrm_fw_set_time(struct bnxt *);
2123 int bnxt_open_nic(struct bnxt *, bool, bool);
2124 int bnxt_half_open_nic(struct bnxt *bp);
2125 void bnxt_half_close_nic(struct bnxt *bp);
2126 int bnxt_close_nic(struct bnxt *, bool, bool);
2127 int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
2129 void bnxt_fw_exception(struct bnxt *bp);
2130 void bnxt_fw_reset(struct bnxt *bp);
2131 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
2133 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
2134 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
2135 int bnxt_restore_pf_fw_resources(struct bnxt *bp);
2136 int bnxt_get_port_parent_id(struct net_device *dev,
2137 struct netdev_phys_item_id *ppid);
2138 void bnxt_dim_work(struct work_struct *work);
2139 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);