2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2016 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
117 #include <linux/module.h>
118 #include <linux/device.h>
119 #include <linux/kmod.h>
120 #include <linux/mdio.h>
121 #include <linux/phy.h>
122 #include <linux/ethtool.h>
125 #include "xgbe-common.h"
127 #define XGBE_PHY_PORT_SPEED_100 BIT(0)
128 #define XGBE_PHY_PORT_SPEED_1000 BIT(1)
129 #define XGBE_PHY_PORT_SPEED_2500 BIT(2)
130 #define XGBE_PHY_PORT_SPEED_10000 BIT(3)
132 #define XGBE_MUTEX_RELEASE 0x80000000
134 #define XGBE_SFP_DIRECT 7
136 /* I2C target addresses */
137 #define XGBE_SFP_SERIAL_ID_ADDRESS 0x50
138 #define XGBE_SFP_DIAG_INFO_ADDRESS 0x51
139 #define XGBE_SFP_PHY_ADDRESS 0x56
140 #define XGBE_GPIO_ADDRESS_PCA9555 0x20
142 /* SFP sideband signal indicators */
143 #define XGBE_GPIO_NO_TX_FAULT BIT(0)
144 #define XGBE_GPIO_NO_RATE_SELECT BIT(1)
145 #define XGBE_GPIO_NO_MOD_ABSENT BIT(2)
146 #define XGBE_GPIO_NO_RX_LOS BIT(3)
148 /* Rate-change complete wait/retry count */
149 #define XGBE_RATECHANGE_COUNT 500
151 /* CDR delay values for KR support (in usec) */
152 #define XGBE_CDR_DELAY_INIT 10000
153 #define XGBE_CDR_DELAY_INC 10000
154 #define XGBE_CDR_DELAY_MAX 100000
156 /* RRC frequency during link status check */
157 #define XGBE_RRC_FREQUENCY 10
159 enum xgbe_port_mode {
160 XGBE_PORT_MODE_RSVD = 0,
161 XGBE_PORT_MODE_BACKPLANE,
162 XGBE_PORT_MODE_BACKPLANE_2500,
163 XGBE_PORT_MODE_1000BASE_T,
164 XGBE_PORT_MODE_1000BASE_X,
165 XGBE_PORT_MODE_NBASE_T,
166 XGBE_PORT_MODE_10GBASE_T,
167 XGBE_PORT_MODE_10GBASE_R,
172 enum xgbe_conn_type {
173 XGBE_CONN_TYPE_NONE = 0,
176 XGBE_CONN_TYPE_RSVD1,
177 XGBE_CONN_TYPE_BACKPLANE,
181 /* SFP/SFP+ related definitions */
183 XGBE_SFP_COMM_DIRECT = 0,
184 XGBE_SFP_COMM_PCA9545,
187 enum xgbe_sfp_cable {
188 XGBE_SFP_CABLE_UNKNOWN = 0,
189 XGBE_SFP_CABLE_ACTIVE,
190 XGBE_SFP_CABLE_PASSIVE,
194 XGBE_SFP_BASE_UNKNOWN = 0,
195 XGBE_SFP_BASE_1000_T,
196 XGBE_SFP_BASE_1000_SX,
197 XGBE_SFP_BASE_1000_LX,
198 XGBE_SFP_BASE_1000_CX,
199 XGBE_SFP_BASE_10000_SR,
200 XGBE_SFP_BASE_10000_LR,
201 XGBE_SFP_BASE_10000_LRM,
202 XGBE_SFP_BASE_10000_ER,
203 XGBE_SFP_BASE_10000_CR,
206 enum xgbe_sfp_speed {
207 XGBE_SFP_SPEED_UNKNOWN = 0,
208 XGBE_SFP_SPEED_100_1000,
210 XGBE_SFP_SPEED_10000,
213 /* SFP Serial ID Base ID values relative to an offset of 0 */
214 #define XGBE_SFP_BASE_ID 0
215 #define XGBE_SFP_ID_SFP 0x03
217 #define XGBE_SFP_BASE_EXT_ID 1
218 #define XGBE_SFP_EXT_ID_SFP 0x04
220 #define XGBE_SFP_BASE_10GBE_CC 3
221 #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4)
222 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5)
223 #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6)
224 #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7)
226 #define XGBE_SFP_BASE_1GBE_CC 6
227 #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0)
228 #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1)
229 #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2)
230 #define XGBE_SFP_BASE_1GBE_CC_T BIT(3)
232 #define XGBE_SFP_BASE_CABLE 8
233 #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2)
234 #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3)
236 #define XGBE_SFP_BASE_BR 12
237 #define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a
238 #define XGBE_SFP_BASE_BR_1GBE_MAX 0x0d
239 #define XGBE_SFP_BASE_BR_10GBE_MIN 0x64
240 #define XGBE_SFP_BASE_BR_10GBE_MAX 0x68
242 #define XGBE_SFP_BASE_CU_CABLE_LEN 18
244 #define XGBE_SFP_BASE_VENDOR_NAME 20
245 #define XGBE_SFP_BASE_VENDOR_NAME_LEN 16
246 #define XGBE_SFP_BASE_VENDOR_PN 40
247 #define XGBE_SFP_BASE_VENDOR_PN_LEN 16
248 #define XGBE_SFP_BASE_VENDOR_REV 56
249 #define XGBE_SFP_BASE_VENDOR_REV_LEN 4
251 #define XGBE_SFP_BASE_CC 63
253 /* SFP Serial ID Extended ID values relative to an offset of 64 */
254 #define XGBE_SFP_BASE_VENDOR_SN 4
255 #define XGBE_SFP_BASE_VENDOR_SN_LEN 16
257 #define XGBE_SFP_EXTD_OPT1 1
258 #define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1)
259 #define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3)
261 #define XGBE_SFP_EXTD_DIAG 28
262 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2)
264 #define XGBE_SFP_EXTD_SFF_8472 30
266 #define XGBE_SFP_EXTD_CC 31
268 struct xgbe_sfp_eeprom {
274 #define XGBE_SFP_DIAGS_SUPPORTED(_x) \
275 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
276 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
278 #define XGBE_SFP_EEPROM_BASE_LEN 256
279 #define XGBE_SFP_EEPROM_DIAG_LEN 256
280 #define XGBE_SFP_EEPROM_MAX (XGBE_SFP_EEPROM_BASE_LEN + \
281 XGBE_SFP_EEPROM_DIAG_LEN)
283 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
284 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
286 struct xgbe_sfp_ascii {
288 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
289 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1];
290 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1];
291 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1];
295 /* MDIO PHY reset types */
296 enum xgbe_mdio_reset {
297 XGBE_MDIO_RESET_NONE = 0,
298 XGBE_MDIO_RESET_I2C_GPIO,
299 XGBE_MDIO_RESET_INT_GPIO,
303 /* Re-driver related definitions */
304 enum xgbe_phy_redrv_if {
305 XGBE_PHY_REDRV_IF_MDIO = 0,
306 XGBE_PHY_REDRV_IF_I2C,
307 XGBE_PHY_REDRV_IF_MAX,
310 enum xgbe_phy_redrv_model {
311 XGBE_PHY_REDRV_MODEL_4223 = 0,
312 XGBE_PHY_REDRV_MODEL_4227,
313 XGBE_PHY_REDRV_MODEL_MAX,
316 enum xgbe_phy_redrv_mode {
317 XGBE_PHY_REDRV_MODE_CX = 5,
318 XGBE_PHY_REDRV_MODE_SR = 9,
321 #define XGBE_PHY_REDRV_MODE_REG 0x12b0
323 /* PHY related configuration information */
324 struct xgbe_phy_data {
325 enum xgbe_port_mode port_mode;
327 unsigned int port_id;
329 unsigned int port_speeds;
331 enum xgbe_conn_type conn_type;
333 enum xgbe_mode cur_mode;
334 enum xgbe_mode start_mode;
336 unsigned int rrc_count;
338 unsigned int mdio_addr;
341 enum xgbe_sfp_comm sfp_comm;
342 unsigned int sfp_mux_address;
343 unsigned int sfp_mux_channel;
345 unsigned int sfp_gpio_address;
346 unsigned int sfp_gpio_mask;
347 unsigned int sfp_gpio_inputs;
348 unsigned int sfp_gpio_rx_los;
349 unsigned int sfp_gpio_tx_fault;
350 unsigned int sfp_gpio_mod_absent;
351 unsigned int sfp_gpio_rate_select;
353 unsigned int sfp_rx_los;
354 unsigned int sfp_tx_fault;
355 unsigned int sfp_mod_absent;
356 unsigned int sfp_changed;
357 unsigned int sfp_phy_avail;
358 unsigned int sfp_cable_len;
359 enum xgbe_sfp_base sfp_base;
360 enum xgbe_sfp_cable sfp_cable;
361 enum xgbe_sfp_speed sfp_speed;
362 struct xgbe_sfp_eeprom sfp_eeprom;
364 /* External PHY support */
365 enum xgbe_mdio_mode phydev_mode;
367 struct phy_device *phydev;
368 enum xgbe_mdio_reset mdio_reset;
369 unsigned int mdio_reset_addr;
370 unsigned int mdio_reset_gpio;
372 /* Re-driver support */
374 unsigned int redrv_if;
375 unsigned int redrv_addr;
376 unsigned int redrv_lane;
377 unsigned int redrv_model;
380 unsigned int phy_cdr_notrack;
381 unsigned int phy_cdr_delay;
384 /* I2C, MDIO and GPIO lines are muxed, so only one device at a time */
385 static DEFINE_MUTEX(xgbe_phy_comm_lock);
387 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata);
389 static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata,
390 struct xgbe_i2c_op *i2c_op)
392 return pdata->i2c_if.i2c_xfer(pdata, i2c_op);
395 static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg,
398 struct xgbe_phy_data *phy_data = pdata->phy_data;
399 struct xgbe_i2c_op i2c_op;
401 u8 redrv_data[5], csum;
402 unsigned int i, retry;
405 /* High byte of register contains read/write indicator */
406 redrv_data[0] = ((reg >> 8) & 0xff) << 1;
407 redrv_data[1] = reg & 0xff;
408 redrv_val = (__be16 *)&redrv_data[2];
409 *redrv_val = cpu_to_be16(val);
411 /* Calculate 1 byte checksum */
413 for (i = 0; i < 4; i++) {
414 csum += redrv_data[i];
415 if (redrv_data[i] > csum)
418 redrv_data[4] = ~csum;
422 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
423 i2c_op.target = phy_data->redrv_addr;
424 i2c_op.len = sizeof(redrv_data);
425 i2c_op.buf = redrv_data;
426 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
428 if ((ret == -EAGAIN) && retry--)
436 i2c_op.cmd = XGBE_I2C_CMD_READ;
437 i2c_op.target = phy_data->redrv_addr;
439 i2c_op.buf = redrv_data;
440 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
442 if ((ret == -EAGAIN) && retry--)
448 if (redrv_data[0] != 0xff) {
449 netif_dbg(pdata, drv, pdata->netdev,
450 "Redriver write checksum error\n");
457 static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target,
458 void *val, unsigned int val_len)
460 struct xgbe_i2c_op i2c_op;
465 /* Write the specfied register */
466 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
467 i2c_op.target = target;
468 i2c_op.len = val_len;
470 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
471 if ((ret == -EAGAIN) && retry--)
477 static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target,
478 void *reg, unsigned int reg_len,
479 void *val, unsigned int val_len)
481 struct xgbe_i2c_op i2c_op;
486 /* Set the specified register to read */
487 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
488 i2c_op.target = target;
489 i2c_op.len = reg_len;
491 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
493 if ((ret == -EAGAIN) && retry--)
501 /* Read the specfied register */
502 i2c_op.cmd = XGBE_I2C_CMD_READ;
503 i2c_op.target = target;
504 i2c_op.len = val_len;
506 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
507 if ((ret == -EAGAIN) && retry--)
513 static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata)
515 struct xgbe_phy_data *phy_data = pdata->phy_data;
516 struct xgbe_i2c_op i2c_op;
519 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
522 /* Select no mux channels */
524 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
525 i2c_op.target = phy_data->sfp_mux_address;
526 i2c_op.len = sizeof(mux_channel);
527 i2c_op.buf = &mux_channel;
529 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
532 static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata)
534 struct xgbe_phy_data *phy_data = pdata->phy_data;
535 struct xgbe_i2c_op i2c_op;
538 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
541 /* Select desired mux channel */
542 mux_channel = 1 << phy_data->sfp_mux_channel;
543 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
544 i2c_op.target = phy_data->sfp_mux_address;
545 i2c_op.len = sizeof(mux_channel);
546 i2c_op.buf = &mux_channel;
548 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
551 static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata)
553 mutex_unlock(&xgbe_phy_comm_lock);
556 static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata)
558 struct xgbe_phy_data *phy_data = pdata->phy_data;
559 unsigned long timeout;
560 unsigned int mutex_id;
562 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
563 * the driver needs to take the software mutex and then the hardware
564 * mutexes before being able to use the busses.
566 mutex_lock(&xgbe_phy_comm_lock);
568 /* Clear the mutexes */
569 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE);
570 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE);
572 /* Mutex formats are the same for I2C and MDIO/GPIO */
574 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
575 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
577 timeout = jiffies + (5 * HZ);
578 while (time_before(jiffies, timeout)) {
579 /* Must be all zeroes in order to obtain the mutex */
580 if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
581 XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
582 usleep_range(100, 200);
586 /* Obtain the mutex */
587 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
588 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
593 mutex_unlock(&xgbe_phy_comm_lock);
595 netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n");
600 static int xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr,
603 struct xgbe_phy_data *phy_data = pdata->phy_data;
605 if (reg & MII_ADDR_C45) {
606 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
609 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
613 return pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val);
616 static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val)
622 ret = xgbe_phy_sfp_get_mux(pdata);
626 mii_data[0] = reg & 0xff;
627 mii_val = (__be16 *)&mii_data[1];
628 *mii_val = cpu_to_be16(val);
630 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS,
631 mii_data, sizeof(mii_data));
633 xgbe_phy_sfp_put_mux(pdata);
638 static int xgbe_phy_mii_write(struct mii_bus *mii, int addr, int reg, u16 val)
640 struct xgbe_prv_data *pdata = mii->priv;
641 struct xgbe_phy_data *phy_data = pdata->phy_data;
644 ret = xgbe_phy_get_comm_ownership(pdata);
648 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
649 ret = xgbe_phy_i2c_mii_write(pdata, reg, val);
650 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
651 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val);
655 xgbe_phy_put_comm_ownership(pdata);
660 static int xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr,
663 struct xgbe_phy_data *phy_data = pdata->phy_data;
665 if (reg & MII_ADDR_C45) {
666 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
669 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
673 return pdata->hw_if.read_ext_mii_regs(pdata, addr, reg);
676 static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg)
682 ret = xgbe_phy_sfp_get_mux(pdata);
687 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS,
688 &mii_reg, sizeof(mii_reg),
689 &mii_val, sizeof(mii_val));
691 ret = be16_to_cpu(mii_val);
693 xgbe_phy_sfp_put_mux(pdata);
698 static int xgbe_phy_mii_read(struct mii_bus *mii, int addr, int reg)
700 struct xgbe_prv_data *pdata = mii->priv;
701 struct xgbe_phy_data *phy_data = pdata->phy_data;
704 ret = xgbe_phy_get_comm_ownership(pdata);
708 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
709 ret = xgbe_phy_i2c_mii_read(pdata, reg);
710 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
711 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg);
715 xgbe_phy_put_comm_ownership(pdata);
720 static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata)
722 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
723 struct xgbe_phy_data *phy_data = pdata->phy_data;
725 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed)
730 if (phy_data->sfp_mod_absent) {
731 pdata->phy.speed = SPEED_UNKNOWN;
732 pdata->phy.duplex = DUPLEX_UNKNOWN;
733 pdata->phy.autoneg = AUTONEG_ENABLE;
734 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
736 XGBE_SET_SUP(lks, Autoneg);
737 XGBE_SET_SUP(lks, Pause);
738 XGBE_SET_SUP(lks, Asym_Pause);
739 XGBE_SET_SUP(lks, TP);
740 XGBE_SET_SUP(lks, FIBRE);
742 XGBE_LM_COPY(lks, advertising, lks, supported);
747 switch (phy_data->sfp_base) {
748 case XGBE_SFP_BASE_1000_T:
749 case XGBE_SFP_BASE_1000_SX:
750 case XGBE_SFP_BASE_1000_LX:
751 case XGBE_SFP_BASE_1000_CX:
752 pdata->phy.speed = SPEED_UNKNOWN;
753 pdata->phy.duplex = DUPLEX_UNKNOWN;
754 pdata->phy.autoneg = AUTONEG_ENABLE;
755 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
756 XGBE_SET_SUP(lks, Autoneg);
757 XGBE_SET_SUP(lks, Pause);
758 XGBE_SET_SUP(lks, Asym_Pause);
759 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) {
760 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
761 XGBE_SET_SUP(lks, 100baseT_Full);
762 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
763 XGBE_SET_SUP(lks, 1000baseT_Full);
765 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
766 XGBE_SET_SUP(lks, 1000baseX_Full);
769 case XGBE_SFP_BASE_10000_SR:
770 case XGBE_SFP_BASE_10000_LR:
771 case XGBE_SFP_BASE_10000_LRM:
772 case XGBE_SFP_BASE_10000_ER:
773 case XGBE_SFP_BASE_10000_CR:
774 pdata->phy.speed = SPEED_10000;
775 pdata->phy.duplex = DUPLEX_FULL;
776 pdata->phy.autoneg = AUTONEG_DISABLE;
777 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
778 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
779 switch (phy_data->sfp_base) {
780 case XGBE_SFP_BASE_10000_SR:
781 XGBE_SET_SUP(lks, 10000baseSR_Full);
783 case XGBE_SFP_BASE_10000_LR:
784 XGBE_SET_SUP(lks, 10000baseLR_Full);
786 case XGBE_SFP_BASE_10000_LRM:
787 XGBE_SET_SUP(lks, 10000baseLRM_Full);
789 case XGBE_SFP_BASE_10000_ER:
790 XGBE_SET_SUP(lks, 10000baseER_Full);
792 case XGBE_SFP_BASE_10000_CR:
793 XGBE_SET_SUP(lks, 10000baseCR_Full);
801 pdata->phy.speed = SPEED_UNKNOWN;
802 pdata->phy.duplex = DUPLEX_UNKNOWN;
803 pdata->phy.autoneg = AUTONEG_DISABLE;
804 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
808 switch (phy_data->sfp_base) {
809 case XGBE_SFP_BASE_1000_T:
810 case XGBE_SFP_BASE_1000_CX:
811 case XGBE_SFP_BASE_10000_CR:
812 XGBE_SET_SUP(lks, TP);
815 XGBE_SET_SUP(lks, FIBRE);
819 XGBE_LM_COPY(lks, advertising, lks, supported);
822 static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom,
823 enum xgbe_sfp_speed sfp_speed)
825 u8 *sfp_base, min, max;
827 sfp_base = sfp_eeprom->base;
830 case XGBE_SFP_SPEED_1000:
831 min = XGBE_SFP_BASE_BR_1GBE_MIN;
832 max = XGBE_SFP_BASE_BR_1GBE_MAX;
834 case XGBE_SFP_SPEED_10000:
835 min = XGBE_SFP_BASE_BR_10GBE_MIN;
836 max = XGBE_SFP_BASE_BR_10GBE_MAX;
842 return ((sfp_base[XGBE_SFP_BASE_BR] >= min) &&
843 (sfp_base[XGBE_SFP_BASE_BR] <= max));
846 static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata)
848 struct xgbe_phy_data *phy_data = pdata->phy_data;
850 if (phy_data->phydev) {
851 phy_detach(phy_data->phydev);
852 phy_device_remove(phy_data->phydev);
853 phy_device_free(phy_data->phydev);
854 phy_data->phydev = NULL;
858 static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata)
860 struct xgbe_phy_data *phy_data = pdata->phy_data;
861 unsigned int phy_id = phy_data->phydev->phy_id;
863 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
866 if ((phy_id & 0xfffffff0) != 0x01ff0cc0)
869 /* Enable Base-T AN */
870 phy_write(phy_data->phydev, 0x16, 0x0001);
871 phy_write(phy_data->phydev, 0x00, 0x9140);
872 phy_write(phy_data->phydev, 0x16, 0x0000);
874 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */
875 phy_write(phy_data->phydev, 0x1b, 0x9084);
876 phy_write(phy_data->phydev, 0x09, 0x0e00);
877 phy_write(phy_data->phydev, 0x00, 0x8140);
878 phy_write(phy_data->phydev, 0x04, 0x0d01);
879 phy_write(phy_data->phydev, 0x00, 0x9140);
881 phy_data->phydev->supported = PHY_GBIT_FEATURES;
882 phy_data->phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
883 phy_data->phydev->advertising = phy_data->phydev->supported;
885 netif_dbg(pdata, drv, pdata->netdev,
886 "Finisar PHY quirk in place\n");
891 static bool xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata)
893 struct xgbe_phy_data *phy_data = pdata->phy_data;
894 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
895 unsigned int phy_id = phy_data->phydev->phy_id;
898 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
901 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
902 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN))
905 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
906 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN))
909 if ((phy_id & 0xfffffff0) != 0x03625d10)
912 /* Disable RGMII mode */
913 phy_write(phy_data->phydev, 0x18, 0x7007);
914 reg = phy_read(phy_data->phydev, 0x18);
915 phy_write(phy_data->phydev, 0x18, reg & ~0x0080);
917 /* Enable fiber register bank */
918 phy_write(phy_data->phydev, 0x1c, 0x7c00);
919 reg = phy_read(phy_data->phydev, 0x1c);
922 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0001);
924 /* Power down SerDes */
925 reg = phy_read(phy_data->phydev, 0x00);
926 phy_write(phy_data->phydev, 0x00, reg | 0x00800);
928 /* Configure SGMII-to-Copper mode */
929 phy_write(phy_data->phydev, 0x1c, 0x7c00);
930 reg = phy_read(phy_data->phydev, 0x1c);
933 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0004);
935 /* Power up SerDes */
936 reg = phy_read(phy_data->phydev, 0x00);
937 phy_write(phy_data->phydev, 0x00, reg & ~0x00800);
939 /* Enable copper register bank */
940 phy_write(phy_data->phydev, 0x1c, 0x7c00);
941 reg = phy_read(phy_data->phydev, 0x1c);
944 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg);
946 /* Power up SerDes */
947 reg = phy_read(phy_data->phydev, 0x00);
948 phy_write(phy_data->phydev, 0x00, reg & ~0x00800);
950 phy_data->phydev->supported = PHY_GBIT_FEATURES;
951 phy_data->phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
952 phy_data->phydev->advertising = phy_data->phydev->supported;
954 netif_dbg(pdata, drv, pdata->netdev,
955 "BelFuse PHY quirk in place\n");
960 static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata)
962 if (xgbe_phy_belfuse_phy_quirks(pdata))
965 if (xgbe_phy_finisar_phy_quirks(pdata))
969 static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
971 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
972 struct xgbe_phy_data *phy_data = pdata->phy_data;
973 struct phy_device *phydev;
977 /* If we already have a PHY, just return */
978 if (phy_data->phydev)
981 /* Check for the use of an external PHY */
982 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE)
985 /* For SFP, only use an external PHY if available */
986 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
987 !phy_data->sfp_phy_avail)
990 /* Set the proper MDIO mode for the PHY */
991 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
992 phy_data->phydev_mode);
994 netdev_err(pdata->netdev,
995 "mdio port/clause not compatible (%u/%u)\n",
996 phy_data->mdio_addr, phy_data->phydev_mode);
1000 /* Create and connect to the PHY device */
1001 phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr,
1002 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45));
1003 if (IS_ERR(phydev)) {
1004 netdev_err(pdata->netdev, "get_phy_device failed\n");
1007 netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n",
1010 /*TODO: If c45, add request_module based on one of the MMD ids? */
1012 ret = phy_device_register(phydev);
1014 netdev_err(pdata->netdev, "phy_device_register failed\n");
1015 phy_device_free(phydev);
1019 ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags,
1020 PHY_INTERFACE_MODE_SGMII);
1022 netdev_err(pdata->netdev, "phy_attach_direct failed\n");
1023 phy_device_remove(phydev);
1024 phy_device_free(phydev);
1027 phy_data->phydev = phydev;
1029 xgbe_phy_external_phy_quirks(pdata);
1031 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1032 lks->link_modes.advertising);
1033 phydev->advertising &= advertising;
1035 phy_start_aneg(phy_data->phydev);
1040 static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata)
1042 struct xgbe_phy_data *phy_data = pdata->phy_data;
1045 if (!phy_data->sfp_changed)
1048 phy_data->sfp_phy_avail = 0;
1050 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
1053 /* Check access to the PHY by reading CTRL1 */
1054 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR);
1058 /* Successfully accessed the PHY */
1059 phy_data->sfp_phy_avail = 1;
1062 static bool xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data)
1064 u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1066 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS))
1069 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS)
1072 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los))
1078 static bool xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data)
1080 u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1082 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT))
1085 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT)
1088 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault))
1094 static bool xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data)
1096 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT)
1099 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent))
1105 static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata)
1107 struct xgbe_phy_data *phy_data = pdata->phy_data;
1108 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
1111 sfp_base = sfp_eeprom->base;
1113 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP)
1116 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP)
1119 /* Update transceiver signals (eeprom extd/options) */
1120 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data);
1121 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data);
1123 /* Assume ACTIVE cable unless told it is PASSIVE */
1124 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) {
1125 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE;
1126 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN];
1128 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
1131 /* Determine the type of SFP */
1132 if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR)
1133 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR;
1134 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR)
1135 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR;
1136 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM)
1137 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM;
1138 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER)
1139 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER;
1140 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX)
1141 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
1142 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX)
1143 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX;
1144 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX)
1145 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX;
1146 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T)
1147 phy_data->sfp_base = XGBE_SFP_BASE_1000_T;
1148 else if ((phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE) &&
1149 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000))
1150 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR;
1152 switch (phy_data->sfp_base) {
1153 case XGBE_SFP_BASE_1000_T:
1154 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000;
1156 case XGBE_SFP_BASE_1000_SX:
1157 case XGBE_SFP_BASE_1000_LX:
1158 case XGBE_SFP_BASE_1000_CX:
1159 phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
1161 case XGBE_SFP_BASE_10000_SR:
1162 case XGBE_SFP_BASE_10000_LR:
1163 case XGBE_SFP_BASE_10000_LRM:
1164 case XGBE_SFP_BASE_10000_ER:
1165 case XGBE_SFP_BASE_10000_CR:
1166 phy_data->sfp_speed = XGBE_SFP_SPEED_10000;
1173 static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata,
1174 struct xgbe_sfp_eeprom *sfp_eeprom)
1176 struct xgbe_sfp_ascii sfp_ascii;
1177 char *sfp_data = (char *)&sfp_ascii;
1179 netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n");
1180 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
1181 XGBE_SFP_BASE_VENDOR_NAME_LEN);
1182 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0';
1183 netif_dbg(pdata, drv, pdata->netdev, " vendor: %s\n",
1186 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
1187 XGBE_SFP_BASE_VENDOR_PN_LEN);
1188 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0';
1189 netif_dbg(pdata, drv, pdata->netdev, " part number: %s\n",
1192 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV],
1193 XGBE_SFP_BASE_VENDOR_REV_LEN);
1194 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0';
1195 netif_dbg(pdata, drv, pdata->netdev, " revision level: %s\n",
1198 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN],
1199 XGBE_SFP_BASE_VENDOR_SN_LEN);
1200 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0';
1201 netif_dbg(pdata, drv, pdata->netdev, " serial number: %s\n",
1205 static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len)
1209 for (cc = 0; len; buf++, len--)
1212 return (cc == cc_in) ? true : false;
1215 static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata)
1217 struct xgbe_phy_data *phy_data = pdata->phy_data;
1218 struct xgbe_sfp_eeprom sfp_eeprom;
1222 ret = xgbe_phy_sfp_get_mux(pdata);
1224 dev_err_once(pdata->dev, "%s: I2C error setting SFP MUX\n",
1225 netdev_name(pdata->netdev));
1229 /* Read the SFP serial ID eeprom */
1231 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1232 &eeprom_addr, sizeof(eeprom_addr),
1233 &sfp_eeprom, sizeof(sfp_eeprom));
1235 dev_err_once(pdata->dev, "%s: I2C error reading SFP EEPROM\n",
1236 netdev_name(pdata->netdev));
1240 /* Validate the contents read */
1241 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC],
1243 sizeof(sfp_eeprom.base) - 1)) {
1248 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC],
1250 sizeof(sfp_eeprom.extd) - 1)) {
1255 /* Check for an added or changed SFP */
1256 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
1257 phy_data->sfp_changed = 1;
1259 if (netif_msg_drv(pdata))
1260 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom);
1262 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
1264 xgbe_phy_free_phy_device(pdata);
1266 phy_data->sfp_changed = 0;
1270 xgbe_phy_sfp_put_mux(pdata);
1275 static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata)
1277 struct xgbe_phy_data *phy_data = pdata->phy_data;
1278 u8 gpio_reg, gpio_ports[2];
1281 /* Read the input port registers */
1283 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
1284 &gpio_reg, sizeof(gpio_reg),
1285 gpio_ports, sizeof(gpio_ports));
1287 dev_err_once(pdata->dev, "%s: I2C error reading SFP GPIOs\n",
1288 netdev_name(pdata->netdev));
1292 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0];
1294 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data);
1297 static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata)
1299 struct xgbe_phy_data *phy_data = pdata->phy_data;
1301 xgbe_phy_free_phy_device(pdata);
1303 phy_data->sfp_mod_absent = 1;
1304 phy_data->sfp_phy_avail = 0;
1305 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
1308 static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data)
1310 phy_data->sfp_rx_los = 0;
1311 phy_data->sfp_tx_fault = 0;
1312 phy_data->sfp_mod_absent = 1;
1313 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN;
1314 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN;
1315 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN;
1318 static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata)
1320 struct xgbe_phy_data *phy_data = pdata->phy_data;
1323 /* Reset the SFP signals and info */
1324 xgbe_phy_sfp_reset(phy_data);
1326 ret = xgbe_phy_get_comm_ownership(pdata);
1330 /* Read the SFP signals and check for module presence */
1331 xgbe_phy_sfp_signals(pdata);
1332 if (phy_data->sfp_mod_absent) {
1333 xgbe_phy_sfp_mod_absent(pdata);
1337 ret = xgbe_phy_sfp_read_eeprom(pdata);
1339 /* Treat any error as if there isn't an SFP plugged in */
1340 xgbe_phy_sfp_reset(phy_data);
1341 xgbe_phy_sfp_mod_absent(pdata);
1345 xgbe_phy_sfp_parse_eeprom(pdata);
1347 xgbe_phy_sfp_external_phy(pdata);
1350 xgbe_phy_sfp_phy_settings(pdata);
1352 xgbe_phy_put_comm_ownership(pdata);
1355 static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata,
1356 struct ethtool_eeprom *eeprom, u8 *data)
1358 struct xgbe_phy_data *phy_data = pdata->phy_data;
1359 u8 eeprom_addr, eeprom_data[XGBE_SFP_EEPROM_MAX];
1360 struct xgbe_sfp_eeprom *sfp_eeprom;
1361 unsigned int i, j, rem;
1371 if ((eeprom->offset + eeprom->len) > XGBE_SFP_EEPROM_MAX) {
1376 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) {
1381 if (!netif_running(pdata->netdev)) {
1386 if (phy_data->sfp_mod_absent) {
1391 ret = xgbe_phy_get_comm_ownership(pdata);
1397 ret = xgbe_phy_sfp_get_mux(pdata);
1399 netdev_err(pdata->netdev, "I2C error setting SFP MUX\n");
1404 /* Read the SFP serial ID eeprom */
1406 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1407 &eeprom_addr, sizeof(eeprom_addr),
1408 eeprom_data, XGBE_SFP_EEPROM_BASE_LEN);
1410 netdev_err(pdata->netdev,
1411 "I2C error reading SFP EEPROM\n");
1416 sfp_eeprom = (struct xgbe_sfp_eeprom *)eeprom_data;
1418 if (XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) {
1419 /* Read the SFP diagnostic eeprom */
1421 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_DIAG_INFO_ADDRESS,
1422 &eeprom_addr, sizeof(eeprom_addr),
1423 eeprom_data + XGBE_SFP_EEPROM_BASE_LEN,
1424 XGBE_SFP_EEPROM_DIAG_LEN);
1426 netdev_err(pdata->netdev,
1427 "I2C error reading SFP DIAGS\n");
1433 for (i = 0, j = eeprom->offset; i < eeprom->len; i++, j++) {
1434 if ((j >= XGBE_SFP_EEPROM_BASE_LEN) &&
1435 !XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom))
1438 data[i] = eeprom_data[j];
1443 xgbe_phy_sfp_put_mux(pdata);
1446 xgbe_phy_put_comm_ownership(pdata);
1454 static int xgbe_phy_module_info(struct xgbe_prv_data *pdata,
1455 struct ethtool_modinfo *modinfo)
1457 struct xgbe_phy_data *phy_data = pdata->phy_data;
1459 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
1462 if (!netif_running(pdata->netdev))
1465 if (phy_data->sfp_mod_absent)
1468 if (XGBE_SFP_DIAGS_SUPPORTED(&phy_data->sfp_eeprom)) {
1469 modinfo->type = ETH_MODULE_SFF_8472;
1470 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1472 modinfo->type = ETH_MODULE_SFF_8079;
1473 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1479 static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata)
1481 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1482 struct xgbe_phy_data *phy_data = pdata->phy_data;
1483 u16 lcl_adv = 0, rmt_adv = 0;
1486 pdata->phy.tx_pause = 0;
1487 pdata->phy.rx_pause = 0;
1489 if (!phy_data->phydev)
1492 if (phy_data->phydev->advertising & ADVERTISED_Pause)
1493 lcl_adv |= ADVERTISE_PAUSE_CAP;
1494 if (phy_data->phydev->advertising & ADVERTISED_Asym_Pause)
1495 lcl_adv |= ADVERTISE_PAUSE_ASYM;
1497 if (phy_data->phydev->pause) {
1498 XGBE_SET_LP_ADV(lks, Pause);
1499 rmt_adv |= LPA_PAUSE_CAP;
1501 if (phy_data->phydev->asym_pause) {
1502 XGBE_SET_LP_ADV(lks, Asym_Pause);
1503 rmt_adv |= LPA_PAUSE_ASYM;
1506 fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1507 if (fc & FLOW_CTRL_TX)
1508 pdata->phy.tx_pause = 1;
1509 if (fc & FLOW_CTRL_RX)
1510 pdata->phy.rx_pause = 1;
1513 static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata)
1515 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1516 enum xgbe_mode mode;
1518 XGBE_SET_LP_ADV(lks, Autoneg);
1519 XGBE_SET_LP_ADV(lks, TP);
1521 /* Use external PHY to determine flow control */
1522 if (pdata->phy.pause_autoneg)
1523 xgbe_phy_phydev_flowctrl(pdata);
1525 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) {
1526 case XGBE_SGMII_AN_LINK_SPEED_100:
1527 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1528 XGBE_SET_LP_ADV(lks, 100baseT_Full);
1529 mode = XGBE_MODE_SGMII_100;
1531 /* Half-duplex not supported */
1532 XGBE_SET_LP_ADV(lks, 100baseT_Half);
1533 mode = XGBE_MODE_UNKNOWN;
1536 case XGBE_SGMII_AN_LINK_SPEED_1000:
1537 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1538 XGBE_SET_LP_ADV(lks, 1000baseT_Full);
1539 mode = XGBE_MODE_SGMII_1000;
1541 /* Half-duplex not supported */
1542 XGBE_SET_LP_ADV(lks, 1000baseT_Half);
1543 mode = XGBE_MODE_UNKNOWN;
1547 mode = XGBE_MODE_UNKNOWN;
1553 static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata)
1555 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1556 enum xgbe_mode mode;
1557 unsigned int ad_reg, lp_reg;
1559 XGBE_SET_LP_ADV(lks, Autoneg);
1560 XGBE_SET_LP_ADV(lks, FIBRE);
1562 /* Compare Advertisement and Link Partner register */
1563 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
1564 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY);
1566 XGBE_SET_LP_ADV(lks, Pause);
1568 XGBE_SET_LP_ADV(lks, Asym_Pause);
1570 if (pdata->phy.pause_autoneg) {
1571 /* Set flow control based on auto-negotiation result */
1572 pdata->phy.tx_pause = 0;
1573 pdata->phy.rx_pause = 0;
1575 if (ad_reg & lp_reg & 0x100) {
1576 pdata->phy.tx_pause = 1;
1577 pdata->phy.rx_pause = 1;
1578 } else if (ad_reg & lp_reg & 0x80) {
1580 pdata->phy.rx_pause = 1;
1581 else if (lp_reg & 0x100)
1582 pdata->phy.tx_pause = 1;
1587 XGBE_SET_LP_ADV(lks, 1000baseX_Full);
1589 /* Half duplex is not supported */
1591 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN;
1596 static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata)
1598 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1599 struct xgbe_phy_data *phy_data = pdata->phy_data;
1600 enum xgbe_mode mode;
1601 unsigned int ad_reg, lp_reg;
1603 XGBE_SET_LP_ADV(lks, Autoneg);
1604 XGBE_SET_LP_ADV(lks, Backplane);
1606 /* Use external PHY to determine flow control */
1607 if (pdata->phy.pause_autoneg)
1608 xgbe_phy_phydev_flowctrl(pdata);
1610 /* Compare Advertisement and Link Partner register 2 */
1611 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1612 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1614 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1616 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1619 if (ad_reg & 0x80) {
1620 switch (phy_data->port_mode) {
1621 case XGBE_PORT_MODE_BACKPLANE:
1622 mode = XGBE_MODE_KR;
1625 mode = XGBE_MODE_SFI;
1628 } else if (ad_reg & 0x20) {
1629 switch (phy_data->port_mode) {
1630 case XGBE_PORT_MODE_BACKPLANE:
1631 mode = XGBE_MODE_KX_1000;
1633 case XGBE_PORT_MODE_1000BASE_X:
1636 case XGBE_PORT_MODE_SFP:
1637 switch (phy_data->sfp_base) {
1638 case XGBE_SFP_BASE_1000_T:
1639 if (phy_data->phydev &&
1640 (phy_data->phydev->speed == SPEED_100))
1641 mode = XGBE_MODE_SGMII_100;
1643 mode = XGBE_MODE_SGMII_1000;
1645 case XGBE_SFP_BASE_1000_SX:
1646 case XGBE_SFP_BASE_1000_LX:
1647 case XGBE_SFP_BASE_1000_CX:
1654 if (phy_data->phydev &&
1655 (phy_data->phydev->speed == SPEED_100))
1656 mode = XGBE_MODE_SGMII_100;
1658 mode = XGBE_MODE_SGMII_1000;
1662 mode = XGBE_MODE_UNKNOWN;
1665 /* Compare Advertisement and Link Partner register 3 */
1666 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1667 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1668 if (lp_reg & 0xc000)
1669 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1674 static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata)
1676 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1677 enum xgbe_mode mode;
1678 unsigned int ad_reg, lp_reg;
1680 XGBE_SET_LP_ADV(lks, Autoneg);
1681 XGBE_SET_LP_ADV(lks, Backplane);
1683 /* Compare Advertisement and Link Partner register 1 */
1684 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1685 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
1687 XGBE_SET_LP_ADV(lks, Pause);
1689 XGBE_SET_LP_ADV(lks, Asym_Pause);
1691 if (pdata->phy.pause_autoneg) {
1692 /* Set flow control based on auto-negotiation result */
1693 pdata->phy.tx_pause = 0;
1694 pdata->phy.rx_pause = 0;
1696 if (ad_reg & lp_reg & 0x400) {
1697 pdata->phy.tx_pause = 1;
1698 pdata->phy.rx_pause = 1;
1699 } else if (ad_reg & lp_reg & 0x800) {
1701 pdata->phy.rx_pause = 1;
1702 else if (lp_reg & 0x400)
1703 pdata->phy.tx_pause = 1;
1707 /* Compare Advertisement and Link Partner register 2 */
1708 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1709 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1711 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1713 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1717 mode = XGBE_MODE_KR;
1718 else if (ad_reg & 0x20)
1719 mode = XGBE_MODE_KX_1000;
1721 mode = XGBE_MODE_UNKNOWN;
1723 /* Compare Advertisement and Link Partner register 3 */
1724 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1725 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1726 if (lp_reg & 0xc000)
1727 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1732 static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
1734 switch (pdata->an_mode) {
1735 case XGBE_AN_MODE_CL73:
1736 return xgbe_phy_an73_outcome(pdata);
1737 case XGBE_AN_MODE_CL73_REDRV:
1738 return xgbe_phy_an73_redrv_outcome(pdata);
1739 case XGBE_AN_MODE_CL37:
1740 return xgbe_phy_an37_outcome(pdata);
1741 case XGBE_AN_MODE_CL37_SGMII:
1742 return xgbe_phy_an37_sgmii_outcome(pdata);
1744 return XGBE_MODE_UNKNOWN;
1748 static void xgbe_phy_an_advertising(struct xgbe_prv_data *pdata,
1749 struct ethtool_link_ksettings *dlks)
1751 struct ethtool_link_ksettings *slks = &pdata->phy.lks;
1752 struct xgbe_phy_data *phy_data = pdata->phy_data;
1754 XGBE_LM_COPY(dlks, advertising, slks, advertising);
1756 /* Without a re-driver, just return current advertising */
1757 if (!phy_data->redrv)
1760 /* With the KR re-driver we need to advertise a single speed */
1761 XGBE_CLR_ADV(dlks, 1000baseKX_Full);
1762 XGBE_CLR_ADV(dlks, 10000baseKR_Full);
1764 /* Advertise FEC support is present */
1765 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
1766 XGBE_SET_ADV(dlks, 10000baseR_FEC);
1768 switch (phy_data->port_mode) {
1769 case XGBE_PORT_MODE_BACKPLANE:
1770 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1772 case XGBE_PORT_MODE_BACKPLANE_2500:
1773 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1775 case XGBE_PORT_MODE_1000BASE_T:
1776 case XGBE_PORT_MODE_1000BASE_X:
1777 case XGBE_PORT_MODE_NBASE_T:
1778 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1780 case XGBE_PORT_MODE_10GBASE_T:
1781 if (phy_data->phydev &&
1782 (phy_data->phydev->speed == SPEED_10000))
1783 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1785 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1787 case XGBE_PORT_MODE_10GBASE_R:
1788 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1790 case XGBE_PORT_MODE_SFP:
1791 switch (phy_data->sfp_base) {
1792 case XGBE_SFP_BASE_1000_T:
1793 case XGBE_SFP_BASE_1000_SX:
1794 case XGBE_SFP_BASE_1000_LX:
1795 case XGBE_SFP_BASE_1000_CX:
1796 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1799 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1804 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1809 static int xgbe_phy_an_config(struct xgbe_prv_data *pdata)
1811 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1812 struct xgbe_phy_data *phy_data = pdata->phy_data;
1816 ret = xgbe_phy_find_phy_device(pdata);
1820 if (!phy_data->phydev)
1823 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1824 lks->link_modes.advertising);
1826 phy_data->phydev->autoneg = pdata->phy.autoneg;
1827 phy_data->phydev->advertising = phy_data->phydev->supported &
1830 if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1831 phy_data->phydev->speed = pdata->phy.speed;
1832 phy_data->phydev->duplex = pdata->phy.duplex;
1835 ret = phy_start_aneg(phy_data->phydev);
1840 static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data)
1842 switch (phy_data->sfp_base) {
1843 case XGBE_SFP_BASE_1000_T:
1844 return XGBE_AN_MODE_CL37_SGMII;
1845 case XGBE_SFP_BASE_1000_SX:
1846 case XGBE_SFP_BASE_1000_LX:
1847 case XGBE_SFP_BASE_1000_CX:
1848 return XGBE_AN_MODE_CL37;
1850 return XGBE_AN_MODE_NONE;
1854 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
1856 struct xgbe_phy_data *phy_data = pdata->phy_data;
1858 /* A KR re-driver will always require CL73 AN */
1859 if (phy_data->redrv)
1860 return XGBE_AN_MODE_CL73_REDRV;
1862 switch (phy_data->port_mode) {
1863 case XGBE_PORT_MODE_BACKPLANE:
1864 return XGBE_AN_MODE_CL73;
1865 case XGBE_PORT_MODE_BACKPLANE_2500:
1866 return XGBE_AN_MODE_NONE;
1867 case XGBE_PORT_MODE_1000BASE_T:
1868 return XGBE_AN_MODE_CL37_SGMII;
1869 case XGBE_PORT_MODE_1000BASE_X:
1870 return XGBE_AN_MODE_CL37;
1871 case XGBE_PORT_MODE_NBASE_T:
1872 return XGBE_AN_MODE_CL37_SGMII;
1873 case XGBE_PORT_MODE_10GBASE_T:
1874 return XGBE_AN_MODE_CL73;
1875 case XGBE_PORT_MODE_10GBASE_R:
1876 return XGBE_AN_MODE_NONE;
1877 case XGBE_PORT_MODE_SFP:
1878 return xgbe_phy_an_sfp_mode(phy_data);
1880 return XGBE_AN_MODE_NONE;
1884 static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata,
1885 enum xgbe_phy_redrv_mode mode)
1887 struct xgbe_phy_data *phy_data = pdata->phy_data;
1888 u16 redrv_reg, redrv_val;
1890 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1891 redrv_val = (u16)mode;
1893 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
1894 redrv_reg, redrv_val);
1897 static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata,
1898 enum xgbe_phy_redrv_mode mode)
1900 struct xgbe_phy_data *phy_data = pdata->phy_data;
1901 unsigned int redrv_reg;
1904 /* Calculate the register to write */
1905 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1907 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode);
1912 static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata)
1914 struct xgbe_phy_data *phy_data = pdata->phy_data;
1915 enum xgbe_phy_redrv_mode mode;
1918 if (!phy_data->redrv)
1921 mode = XGBE_PHY_REDRV_MODE_CX;
1922 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1923 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) &&
1924 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR))
1925 mode = XGBE_PHY_REDRV_MODE_SR;
1927 ret = xgbe_phy_get_comm_ownership(pdata);
1931 if (phy_data->redrv_if)
1932 xgbe_phy_set_redrv_mode_i2c(pdata, mode);
1934 xgbe_phy_set_redrv_mode_mdio(pdata, mode);
1936 xgbe_phy_put_comm_ownership(pdata);
1939 static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata,
1940 unsigned int cmd, unsigned int sub_cmd)
1942 unsigned int s0 = 0;
1945 /* Log if a previous command did not complete */
1946 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
1947 netif_dbg(pdata, link, pdata->netdev,
1948 "firmware mailbox not ready for command\n");
1950 /* Construct the command */
1951 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
1952 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
1954 /* Issue the command */
1955 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1956 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
1957 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
1959 /* Wait for command to complete */
1960 wait = XGBE_RATECHANGE_COUNT;
1962 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
1965 usleep_range(1000, 2000);
1968 netif_dbg(pdata, link, pdata->netdev,
1969 "firmware mailbox command did not complete\n");
1972 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata)
1974 /* Receiver Reset Cycle */
1975 xgbe_phy_perform_ratechange(pdata, 5, 0);
1977 netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n");
1980 static void xgbe_phy_power_off(struct xgbe_prv_data *pdata)
1982 struct xgbe_phy_data *phy_data = pdata->phy_data;
1985 xgbe_phy_perform_ratechange(pdata, 0, 0);
1987 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
1989 netif_dbg(pdata, link, pdata->netdev, "phy powered off\n");
1992 static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata)
1994 struct xgbe_phy_data *phy_data = pdata->phy_data;
1996 xgbe_phy_set_redrv_mode(pdata);
1999 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) {
2000 xgbe_phy_perform_ratechange(pdata, 3, 0);
2002 if (phy_data->sfp_cable_len <= 1)
2003 xgbe_phy_perform_ratechange(pdata, 3, 1);
2004 else if (phy_data->sfp_cable_len <= 3)
2005 xgbe_phy_perform_ratechange(pdata, 3, 2);
2007 xgbe_phy_perform_ratechange(pdata, 3, 3);
2010 phy_data->cur_mode = XGBE_MODE_SFI;
2012 netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n");
2015 static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata)
2017 struct xgbe_phy_data *phy_data = pdata->phy_data;
2019 xgbe_phy_set_redrv_mode(pdata);
2022 xgbe_phy_perform_ratechange(pdata, 1, 3);
2024 phy_data->cur_mode = XGBE_MODE_X;
2026 netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n");
2029 static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata)
2031 struct xgbe_phy_data *phy_data = pdata->phy_data;
2033 xgbe_phy_set_redrv_mode(pdata);
2036 xgbe_phy_perform_ratechange(pdata, 1, 2);
2038 phy_data->cur_mode = XGBE_MODE_SGMII_1000;
2040 netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n");
2043 static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata)
2045 struct xgbe_phy_data *phy_data = pdata->phy_data;
2047 xgbe_phy_set_redrv_mode(pdata);
2050 xgbe_phy_perform_ratechange(pdata, 1, 1);
2052 phy_data->cur_mode = XGBE_MODE_SGMII_100;
2054 netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n");
2057 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
2059 struct xgbe_phy_data *phy_data = pdata->phy_data;
2061 xgbe_phy_set_redrv_mode(pdata);
2064 xgbe_phy_perform_ratechange(pdata, 4, 0);
2066 phy_data->cur_mode = XGBE_MODE_KR;
2068 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n");
2071 static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
2073 struct xgbe_phy_data *phy_data = pdata->phy_data;
2075 xgbe_phy_set_redrv_mode(pdata);
2078 xgbe_phy_perform_ratechange(pdata, 2, 0);
2080 phy_data->cur_mode = XGBE_MODE_KX_2500;
2082 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n");
2085 static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
2087 struct xgbe_phy_data *phy_data = pdata->phy_data;
2089 xgbe_phy_set_redrv_mode(pdata);
2092 xgbe_phy_perform_ratechange(pdata, 1, 3);
2094 phy_data->cur_mode = XGBE_MODE_KX_1000;
2096 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n");
2099 static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
2101 struct xgbe_phy_data *phy_data = pdata->phy_data;
2103 return phy_data->cur_mode;
2106 static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata)
2108 struct xgbe_phy_data *phy_data = pdata->phy_data;
2110 /* No switching if not 10GBase-T */
2111 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T)
2112 return xgbe_phy_cur_mode(pdata);
2114 switch (xgbe_phy_cur_mode(pdata)) {
2115 case XGBE_MODE_SGMII_100:
2116 case XGBE_MODE_SGMII_1000:
2117 return XGBE_MODE_KR;
2120 return XGBE_MODE_SGMII_1000;
2124 static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata)
2126 return XGBE_MODE_KX_2500;
2129 static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata)
2131 /* If we are in KR switch to KX, and vice-versa */
2132 switch (xgbe_phy_cur_mode(pdata)) {
2133 case XGBE_MODE_KX_1000:
2134 return XGBE_MODE_KR;
2137 return XGBE_MODE_KX_1000;
2141 static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
2143 struct xgbe_phy_data *phy_data = pdata->phy_data;
2145 switch (phy_data->port_mode) {
2146 case XGBE_PORT_MODE_BACKPLANE:
2147 return xgbe_phy_switch_bp_mode(pdata);
2148 case XGBE_PORT_MODE_BACKPLANE_2500:
2149 return xgbe_phy_switch_bp_2500_mode(pdata);
2150 case XGBE_PORT_MODE_1000BASE_T:
2151 case XGBE_PORT_MODE_NBASE_T:
2152 case XGBE_PORT_MODE_10GBASE_T:
2153 return xgbe_phy_switch_baset_mode(pdata);
2154 case XGBE_PORT_MODE_1000BASE_X:
2155 case XGBE_PORT_MODE_10GBASE_R:
2156 case XGBE_PORT_MODE_SFP:
2157 /* No switching, so just return current mode */
2158 return xgbe_phy_cur_mode(pdata);
2160 return XGBE_MODE_UNKNOWN;
2164 static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data,
2171 return XGBE_MODE_KR;
2173 return XGBE_MODE_UNKNOWN;
2177 static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data,
2182 return XGBE_MODE_SGMII_100;
2184 return XGBE_MODE_SGMII_1000;
2186 return XGBE_MODE_KX_2500;
2188 return XGBE_MODE_KR;
2190 return XGBE_MODE_UNKNOWN;
2194 static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data,
2199 return XGBE_MODE_SGMII_100;
2201 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2202 return XGBE_MODE_SGMII_1000;
2207 return XGBE_MODE_SFI;
2209 return XGBE_MODE_UNKNOWN;
2213 static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed)
2217 return XGBE_MODE_KX_2500;
2219 return XGBE_MODE_UNKNOWN;
2223 static enum xgbe_mode xgbe_phy_get_bp_mode(int speed)
2227 return XGBE_MODE_KX_1000;
2229 return XGBE_MODE_KR;
2231 return XGBE_MODE_UNKNOWN;
2235 static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata,
2238 struct xgbe_phy_data *phy_data = pdata->phy_data;
2240 switch (phy_data->port_mode) {
2241 case XGBE_PORT_MODE_BACKPLANE:
2242 return xgbe_phy_get_bp_mode(speed);
2243 case XGBE_PORT_MODE_BACKPLANE_2500:
2244 return xgbe_phy_get_bp_2500_mode(speed);
2245 case XGBE_PORT_MODE_1000BASE_T:
2246 case XGBE_PORT_MODE_NBASE_T:
2247 case XGBE_PORT_MODE_10GBASE_T:
2248 return xgbe_phy_get_baset_mode(phy_data, speed);
2249 case XGBE_PORT_MODE_1000BASE_X:
2250 case XGBE_PORT_MODE_10GBASE_R:
2251 return xgbe_phy_get_basex_mode(phy_data, speed);
2252 case XGBE_PORT_MODE_SFP:
2253 return xgbe_phy_get_sfp_mode(phy_data, speed);
2255 return XGBE_MODE_UNKNOWN;
2259 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2262 case XGBE_MODE_KX_1000:
2263 xgbe_phy_kx_1000_mode(pdata);
2265 case XGBE_MODE_KX_2500:
2266 xgbe_phy_kx_2500_mode(pdata);
2269 xgbe_phy_kr_mode(pdata);
2271 case XGBE_MODE_SGMII_100:
2272 xgbe_phy_sgmii_100_mode(pdata);
2274 case XGBE_MODE_SGMII_1000:
2275 xgbe_phy_sgmii_1000_mode(pdata);
2278 xgbe_phy_x_mode(pdata);
2281 xgbe_phy_sfi_mode(pdata);
2288 static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata,
2289 enum xgbe_mode mode, bool advert)
2291 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
2294 enum xgbe_mode cur_mode;
2296 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
2297 if (cur_mode == mode)
2304 static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata,
2305 enum xgbe_mode mode)
2307 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2311 return xgbe_phy_check_mode(pdata, mode,
2312 XGBE_ADV(lks, 1000baseX_Full));
2314 return xgbe_phy_check_mode(pdata, mode,
2315 XGBE_ADV(lks, 10000baseKR_Full));
2321 static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata,
2322 enum xgbe_mode mode)
2324 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2327 case XGBE_MODE_SGMII_100:
2328 return xgbe_phy_check_mode(pdata, mode,
2329 XGBE_ADV(lks, 100baseT_Full));
2330 case XGBE_MODE_SGMII_1000:
2331 return xgbe_phy_check_mode(pdata, mode,
2332 XGBE_ADV(lks, 1000baseT_Full));
2333 case XGBE_MODE_KX_2500:
2334 return xgbe_phy_check_mode(pdata, mode,
2335 XGBE_ADV(lks, 2500baseT_Full));
2337 return xgbe_phy_check_mode(pdata, mode,
2338 XGBE_ADV(lks, 10000baseT_Full));
2344 static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata,
2345 enum xgbe_mode mode)
2347 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2348 struct xgbe_phy_data *phy_data = pdata->phy_data;
2352 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2354 return xgbe_phy_check_mode(pdata, mode,
2355 XGBE_ADV(lks, 1000baseX_Full));
2356 case XGBE_MODE_SGMII_100:
2357 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2359 return xgbe_phy_check_mode(pdata, mode,
2360 XGBE_ADV(lks, 100baseT_Full));
2361 case XGBE_MODE_SGMII_1000:
2362 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2364 return xgbe_phy_check_mode(pdata, mode,
2365 XGBE_ADV(lks, 1000baseT_Full));
2367 if (phy_data->sfp_mod_absent)
2369 return xgbe_phy_check_mode(pdata, mode,
2370 XGBE_ADV(lks, 10000baseSR_Full) ||
2371 XGBE_ADV(lks, 10000baseLR_Full) ||
2372 XGBE_ADV(lks, 10000baseLRM_Full) ||
2373 XGBE_ADV(lks, 10000baseER_Full) ||
2374 XGBE_ADV(lks, 10000baseCR_Full));
2380 static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata,
2381 enum xgbe_mode mode)
2383 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2386 case XGBE_MODE_KX_2500:
2387 return xgbe_phy_check_mode(pdata, mode,
2388 XGBE_ADV(lks, 2500baseX_Full));
2394 static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata,
2395 enum xgbe_mode mode)
2397 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2400 case XGBE_MODE_KX_1000:
2401 return xgbe_phy_check_mode(pdata, mode,
2402 XGBE_ADV(lks, 1000baseKX_Full));
2404 return xgbe_phy_check_mode(pdata, mode,
2405 XGBE_ADV(lks, 10000baseKR_Full));
2411 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2413 struct xgbe_phy_data *phy_data = pdata->phy_data;
2415 switch (phy_data->port_mode) {
2416 case XGBE_PORT_MODE_BACKPLANE:
2417 return xgbe_phy_use_bp_mode(pdata, mode);
2418 case XGBE_PORT_MODE_BACKPLANE_2500:
2419 return xgbe_phy_use_bp_2500_mode(pdata, mode);
2420 case XGBE_PORT_MODE_1000BASE_T:
2421 case XGBE_PORT_MODE_NBASE_T:
2422 case XGBE_PORT_MODE_10GBASE_T:
2423 return xgbe_phy_use_baset_mode(pdata, mode);
2424 case XGBE_PORT_MODE_1000BASE_X:
2425 case XGBE_PORT_MODE_10GBASE_R:
2426 return xgbe_phy_use_basex_mode(pdata, mode);
2427 case XGBE_PORT_MODE_SFP:
2428 return xgbe_phy_use_sfp_mode(pdata, mode);
2434 static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data,
2439 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X);
2441 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R);
2447 static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data,
2455 return (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T);
2457 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T);
2463 static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data,
2468 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000);
2470 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) ||
2471 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000));
2473 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000);
2479 static bool xgbe_phy_valid_speed_bp_2500_mode(int speed)
2489 static bool xgbe_phy_valid_speed_bp_mode(int speed)
2500 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
2502 struct xgbe_phy_data *phy_data = pdata->phy_data;
2504 switch (phy_data->port_mode) {
2505 case XGBE_PORT_MODE_BACKPLANE:
2506 return xgbe_phy_valid_speed_bp_mode(speed);
2507 case XGBE_PORT_MODE_BACKPLANE_2500:
2508 return xgbe_phy_valid_speed_bp_2500_mode(speed);
2509 case XGBE_PORT_MODE_1000BASE_T:
2510 case XGBE_PORT_MODE_NBASE_T:
2511 case XGBE_PORT_MODE_10GBASE_T:
2512 return xgbe_phy_valid_speed_baset_mode(phy_data, speed);
2513 case XGBE_PORT_MODE_1000BASE_X:
2514 case XGBE_PORT_MODE_10GBASE_R:
2515 return xgbe_phy_valid_speed_basex_mode(phy_data, speed);
2516 case XGBE_PORT_MODE_SFP:
2517 return xgbe_phy_valid_speed_sfp_mode(phy_data, speed);
2523 static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
2525 struct xgbe_phy_data *phy_data = pdata->phy_data;
2531 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
2532 /* Check SFP signals */
2533 xgbe_phy_sfp_detect(pdata);
2535 if (phy_data->sfp_changed) {
2540 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los)
2544 if (phy_data->phydev) {
2545 /* Check external PHY */
2546 ret = phy_read_status(phy_data->phydev);
2550 if ((pdata->phy.autoneg == AUTONEG_ENABLE) &&
2551 !phy_aneg_done(phy_data->phydev))
2554 if (!phy_data->phydev->link)
2558 /* Link status is latched low, so read once to clear
2559 * and then read again to get current state
2561 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2562 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2563 if (reg & MDIO_STAT1_LSTATUS)
2566 /* No link, attempt a receiver reset cycle */
2567 if (phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) {
2568 phy_data->rrc_count = 0;
2569 xgbe_phy_rrc(pdata);
2575 static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata)
2577 struct xgbe_phy_data *phy_data = pdata->phy_data;
2579 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 +
2580 XP_GET_BITS(pdata->pp3, XP_PROP_3,
2583 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2586 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2588 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2590 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2592 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2595 if (netif_msg_probe(pdata)) {
2596 dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n",
2597 phy_data->sfp_gpio_address);
2598 dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n",
2599 phy_data->sfp_gpio_mask);
2600 dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n",
2601 phy_data->sfp_gpio_rx_los);
2602 dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n",
2603 phy_data->sfp_gpio_tx_fault);
2604 dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n",
2605 phy_data->sfp_gpio_mod_absent);
2606 dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n",
2607 phy_data->sfp_gpio_rate_select);
2611 static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata)
2613 struct xgbe_phy_data *phy_data = pdata->phy_data;
2614 unsigned int mux_addr_hi, mux_addr_lo;
2616 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI);
2617 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO);
2618 if (mux_addr_lo == XGBE_SFP_DIRECT)
2621 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545;
2622 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
2623 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4,
2626 if (netif_msg_probe(pdata)) {
2627 dev_dbg(pdata->dev, "SFP: mux_address=%#x\n",
2628 phy_data->sfp_mux_address);
2629 dev_dbg(pdata->dev, "SFP: mux_channel=%u\n",
2630 phy_data->sfp_mux_channel);
2634 static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata)
2636 xgbe_phy_sfp_comm_setup(pdata);
2637 xgbe_phy_sfp_gpio_setup(pdata);
2640 static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata)
2642 struct xgbe_phy_data *phy_data = pdata->phy_data;
2645 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio);
2649 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio);
2654 static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata)
2656 struct xgbe_phy_data *phy_data = pdata->phy_data;
2657 u8 gpio_reg, gpio_ports[2], gpio_data[3];
2660 /* Read the output port registers */
2662 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr,
2663 &gpio_reg, sizeof(gpio_reg),
2664 gpio_ports, sizeof(gpio_ports));
2668 /* Prepare to write the GPIO data */
2670 gpio_data[1] = gpio_ports[0];
2671 gpio_data[2] = gpio_ports[1];
2673 /* Set the GPIO pin */
2674 if (phy_data->mdio_reset_gpio < 8)
2675 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8));
2677 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8));
2679 /* Write the output port registers */
2680 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2681 gpio_data, sizeof(gpio_data));
2685 /* Clear the GPIO pin */
2686 if (phy_data->mdio_reset_gpio < 8)
2687 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2689 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2691 /* Write the output port registers */
2692 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2693 gpio_data, sizeof(gpio_data));
2698 static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata)
2700 struct xgbe_phy_data *phy_data = pdata->phy_data;
2703 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
2706 ret = xgbe_phy_get_comm_ownership(pdata);
2710 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO)
2711 ret = xgbe_phy_i2c_mdio_reset(pdata);
2712 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
2713 ret = xgbe_phy_int_mdio_reset(pdata);
2715 xgbe_phy_put_comm_ownership(pdata);
2720 static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data)
2722 if (!phy_data->redrv)
2725 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX)
2728 switch (phy_data->redrv_model) {
2729 case XGBE_PHY_REDRV_MODEL_4223:
2730 if (phy_data->redrv_lane > 3)
2733 case XGBE_PHY_REDRV_MODEL_4227:
2734 if (phy_data->redrv_lane > 1)
2744 static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata)
2746 struct xgbe_phy_data *phy_data = pdata->phy_data;
2748 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
2751 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET);
2752 switch (phy_data->mdio_reset) {
2753 case XGBE_MDIO_RESET_NONE:
2754 case XGBE_MDIO_RESET_I2C_GPIO:
2755 case XGBE_MDIO_RESET_INT_GPIO:
2758 dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n",
2759 phy_data->mdio_reset);
2763 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) {
2764 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 +
2765 XP_GET_BITS(pdata->pp3, XP_PROP_3,
2766 MDIO_RESET_I2C_ADDR);
2767 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2768 MDIO_RESET_I2C_GPIO);
2769 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) {
2770 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2771 MDIO_RESET_INT_GPIO);
2777 static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata)
2779 struct xgbe_phy_data *phy_data = pdata->phy_data;
2781 switch (phy_data->port_mode) {
2782 case XGBE_PORT_MODE_BACKPLANE:
2783 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2784 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2787 case XGBE_PORT_MODE_BACKPLANE_2500:
2788 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)
2791 case XGBE_PORT_MODE_1000BASE_T:
2792 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2793 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000))
2796 case XGBE_PORT_MODE_1000BASE_X:
2797 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
2800 case XGBE_PORT_MODE_NBASE_T:
2801 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2802 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2803 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500))
2806 case XGBE_PORT_MODE_10GBASE_T:
2807 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2808 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2809 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2812 case XGBE_PORT_MODE_10GBASE_R:
2813 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
2816 case XGBE_PORT_MODE_SFP:
2817 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2818 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2819 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2829 static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata)
2831 struct xgbe_phy_data *phy_data = pdata->phy_data;
2833 switch (phy_data->port_mode) {
2834 case XGBE_PORT_MODE_BACKPLANE:
2835 case XGBE_PORT_MODE_BACKPLANE_2500:
2836 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE)
2839 case XGBE_PORT_MODE_1000BASE_T:
2840 case XGBE_PORT_MODE_1000BASE_X:
2841 case XGBE_PORT_MODE_NBASE_T:
2842 case XGBE_PORT_MODE_10GBASE_T:
2843 case XGBE_PORT_MODE_10GBASE_R:
2844 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO)
2847 case XGBE_PORT_MODE_SFP:
2848 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
2858 static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata)
2860 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS))
2862 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE))
2868 static void xgbe_phy_cdr_track(struct xgbe_prv_data *pdata)
2870 struct xgbe_phy_data *phy_data = pdata->phy_data;
2872 if (!pdata->debugfs_an_cdr_workaround)
2875 if (!phy_data->phy_cdr_notrack)
2878 usleep_range(phy_data->phy_cdr_delay,
2879 phy_data->phy_cdr_delay + 500);
2881 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
2882 XGBE_PMA_CDR_TRACK_EN_MASK,
2883 XGBE_PMA_CDR_TRACK_EN_ON);
2885 phy_data->phy_cdr_notrack = 0;
2888 static void xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata)
2890 struct xgbe_phy_data *phy_data = pdata->phy_data;
2892 if (!pdata->debugfs_an_cdr_workaround)
2895 if (phy_data->phy_cdr_notrack)
2898 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
2899 XGBE_PMA_CDR_TRACK_EN_MASK,
2900 XGBE_PMA_CDR_TRACK_EN_OFF);
2902 xgbe_phy_rrc(pdata);
2904 phy_data->phy_cdr_notrack = 1;
2907 static void xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata)
2909 if (!pdata->debugfs_an_cdr_track_early)
2910 xgbe_phy_cdr_track(pdata);
2913 static void xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata)
2915 if (pdata->debugfs_an_cdr_track_early)
2916 xgbe_phy_cdr_track(pdata);
2919 static void xgbe_phy_an_post(struct xgbe_prv_data *pdata)
2921 struct xgbe_phy_data *phy_data = pdata->phy_data;
2923 switch (pdata->an_mode) {
2924 case XGBE_AN_MODE_CL73:
2925 case XGBE_AN_MODE_CL73_REDRV:
2926 if (phy_data->cur_mode != XGBE_MODE_KR)
2929 xgbe_phy_cdr_track(pdata);
2931 switch (pdata->an_result) {
2933 case XGBE_AN_COMPLETE:
2936 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX)
2937 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC;
2939 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
2948 static void xgbe_phy_an_pre(struct xgbe_prv_data *pdata)
2950 struct xgbe_phy_data *phy_data = pdata->phy_data;
2952 switch (pdata->an_mode) {
2953 case XGBE_AN_MODE_CL73:
2954 case XGBE_AN_MODE_CL73_REDRV:
2955 if (phy_data->cur_mode != XGBE_MODE_KR)
2958 xgbe_phy_cdr_notrack(pdata);
2965 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
2967 struct xgbe_phy_data *phy_data = pdata->phy_data;
2969 /* If we have an external PHY, free it */
2970 xgbe_phy_free_phy_device(pdata);
2972 /* Reset SFP data */
2973 xgbe_phy_sfp_reset(phy_data);
2974 xgbe_phy_sfp_mod_absent(pdata);
2976 /* Reset CDR support */
2977 xgbe_phy_cdr_track(pdata);
2979 /* Power off the PHY */
2980 xgbe_phy_power_off(pdata);
2982 /* Stop the I2C controller */
2983 pdata->i2c_if.i2c_stop(pdata);
2986 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
2988 struct xgbe_phy_data *phy_data = pdata->phy_data;
2991 /* Start the I2C controller */
2992 ret = pdata->i2c_if.i2c_start(pdata);
2996 /* Set the proper MDIO mode for the re-driver */
2997 if (phy_data->redrv && !phy_data->redrv_if) {
2998 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
2999 XGBE_MDIO_MODE_CL22);
3001 netdev_err(pdata->netdev,
3002 "redriver mdio port not compatible (%u)\n",
3003 phy_data->redrv_addr);
3008 /* Start in highest supported mode */
3009 xgbe_phy_set_mode(pdata, phy_data->start_mode);
3011 /* Reset CDR support */
3012 xgbe_phy_cdr_track(pdata);
3014 /* After starting the I2C controller, we can check for an SFP */
3015 switch (phy_data->port_mode) {
3016 case XGBE_PORT_MODE_SFP:
3017 xgbe_phy_sfp_detect(pdata);
3023 /* If we have an external PHY, start it */
3024 ret = xgbe_phy_find_phy_device(pdata);
3031 pdata->i2c_if.i2c_stop(pdata);
3036 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
3038 struct xgbe_phy_data *phy_data = pdata->phy_data;
3039 enum xgbe_mode cur_mode;
3042 /* Reset by power cycling the PHY */
3043 cur_mode = phy_data->cur_mode;
3044 xgbe_phy_power_off(pdata);
3045 xgbe_phy_set_mode(pdata, cur_mode);
3047 if (!phy_data->phydev)
3050 /* Reset the external PHY */
3051 ret = xgbe_phy_mdio_reset(pdata);
3055 return phy_init_hw(phy_data->phydev);
3058 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
3060 struct xgbe_phy_data *phy_data = pdata->phy_data;
3062 /* Unregister for driving external PHYs */
3063 mdiobus_unregister(phy_data->mii);
3066 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
3068 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
3069 struct xgbe_phy_data *phy_data;
3070 struct mii_bus *mii;
3073 /* Check if enabled */
3074 if (!xgbe_phy_port_enabled(pdata)) {
3075 dev_info(pdata->dev, "device is not enabled\n");
3079 /* Initialize the I2C controller */
3080 ret = pdata->i2c_if.i2c_init(pdata);
3084 phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL);
3087 pdata->phy_data = phy_data;
3089 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE);
3090 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID);
3091 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS);
3092 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE);
3093 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR);
3094 if (netif_msg_probe(pdata)) {
3095 dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode);
3096 dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id);
3097 dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds);
3098 dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type);
3099 dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr);
3102 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT);
3103 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF);
3104 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR);
3105 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE);
3106 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL);
3107 if (phy_data->redrv && netif_msg_probe(pdata)) {
3108 dev_dbg(pdata->dev, "redrv present\n");
3109 dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if);
3110 dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr);
3111 dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane);
3112 dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model);
3115 /* Validate the connection requested */
3116 if (xgbe_phy_conn_type_mismatch(pdata)) {
3117 dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n",
3118 phy_data->port_mode, phy_data->conn_type);
3122 /* Validate the mode requested */
3123 if (xgbe_phy_port_mode_mismatch(pdata)) {
3124 dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n",
3125 phy_data->port_mode, phy_data->port_speeds);
3129 /* Check for and validate MDIO reset support */
3130 ret = xgbe_phy_mdio_reset_setup(pdata);
3134 /* Validate the re-driver information */
3135 if (xgbe_phy_redrv_error(phy_data)) {
3136 dev_err(pdata->dev, "phy re-driver settings error\n");
3139 pdata->kr_redrv = phy_data->redrv;
3141 /* Indicate current mode is unknown */
3142 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
3144 /* Initialize supported features */
3147 switch (phy_data->port_mode) {
3148 /* Backplane support */
3149 case XGBE_PORT_MODE_BACKPLANE:
3150 XGBE_SET_SUP(lks, Autoneg);
3151 XGBE_SET_SUP(lks, Pause);
3152 XGBE_SET_SUP(lks, Asym_Pause);
3153 XGBE_SET_SUP(lks, Backplane);
3154 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3155 XGBE_SET_SUP(lks, 1000baseKX_Full);
3156 phy_data->start_mode = XGBE_MODE_KX_1000;
3158 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3159 XGBE_SET_SUP(lks, 10000baseKR_Full);
3160 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3161 XGBE_SET_SUP(lks, 10000baseR_FEC);
3162 phy_data->start_mode = XGBE_MODE_KR;
3165 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3167 case XGBE_PORT_MODE_BACKPLANE_2500:
3168 XGBE_SET_SUP(lks, Pause);
3169 XGBE_SET_SUP(lks, Asym_Pause);
3170 XGBE_SET_SUP(lks, Backplane);
3171 XGBE_SET_SUP(lks, 2500baseX_Full);
3172 phy_data->start_mode = XGBE_MODE_KX_2500;
3174 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3177 /* MDIO 1GBase-T support */
3178 case XGBE_PORT_MODE_1000BASE_T:
3179 XGBE_SET_SUP(lks, Autoneg);
3180 XGBE_SET_SUP(lks, Pause);
3181 XGBE_SET_SUP(lks, Asym_Pause);
3182 XGBE_SET_SUP(lks, TP);
3183 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3184 XGBE_SET_SUP(lks, 100baseT_Full);
3185 phy_data->start_mode = XGBE_MODE_SGMII_100;
3187 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3188 XGBE_SET_SUP(lks, 1000baseT_Full);
3189 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3192 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3195 /* MDIO Base-X support */
3196 case XGBE_PORT_MODE_1000BASE_X:
3197 XGBE_SET_SUP(lks, Autoneg);
3198 XGBE_SET_SUP(lks, Pause);
3199 XGBE_SET_SUP(lks, Asym_Pause);
3200 XGBE_SET_SUP(lks, FIBRE);
3201 XGBE_SET_SUP(lks, 1000baseX_Full);
3202 phy_data->start_mode = XGBE_MODE_X;
3204 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3207 /* MDIO NBase-T support */
3208 case XGBE_PORT_MODE_NBASE_T:
3209 XGBE_SET_SUP(lks, Autoneg);
3210 XGBE_SET_SUP(lks, Pause);
3211 XGBE_SET_SUP(lks, Asym_Pause);
3212 XGBE_SET_SUP(lks, TP);
3213 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3214 XGBE_SET_SUP(lks, 100baseT_Full);
3215 phy_data->start_mode = XGBE_MODE_SGMII_100;
3217 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3218 XGBE_SET_SUP(lks, 1000baseT_Full);
3219 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3221 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
3222 XGBE_SET_SUP(lks, 2500baseT_Full);
3223 phy_data->start_mode = XGBE_MODE_KX_2500;
3226 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3229 /* 10GBase-T support */
3230 case XGBE_PORT_MODE_10GBASE_T:
3231 XGBE_SET_SUP(lks, Autoneg);
3232 XGBE_SET_SUP(lks, Pause);
3233 XGBE_SET_SUP(lks, Asym_Pause);
3234 XGBE_SET_SUP(lks, TP);
3235 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3236 XGBE_SET_SUP(lks, 100baseT_Full);
3237 phy_data->start_mode = XGBE_MODE_SGMII_100;
3239 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3240 XGBE_SET_SUP(lks, 1000baseT_Full);
3241 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3243 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3244 XGBE_SET_SUP(lks, 10000baseT_Full);
3245 phy_data->start_mode = XGBE_MODE_KR;
3248 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3251 /* 10GBase-R support */
3252 case XGBE_PORT_MODE_10GBASE_R:
3253 XGBE_SET_SUP(lks, Autoneg);
3254 XGBE_SET_SUP(lks, Pause);
3255 XGBE_SET_SUP(lks, Asym_Pause);
3256 XGBE_SET_SUP(lks, FIBRE);
3257 XGBE_SET_SUP(lks, 10000baseSR_Full);
3258 XGBE_SET_SUP(lks, 10000baseLR_Full);
3259 XGBE_SET_SUP(lks, 10000baseLRM_Full);
3260 XGBE_SET_SUP(lks, 10000baseER_Full);
3261 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3262 XGBE_SET_SUP(lks, 10000baseR_FEC);
3263 phy_data->start_mode = XGBE_MODE_SFI;
3265 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3269 case XGBE_PORT_MODE_SFP:
3270 XGBE_SET_SUP(lks, Autoneg);
3271 XGBE_SET_SUP(lks, Pause);
3272 XGBE_SET_SUP(lks, Asym_Pause);
3273 XGBE_SET_SUP(lks, TP);
3274 XGBE_SET_SUP(lks, FIBRE);
3275 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
3276 phy_data->start_mode = XGBE_MODE_SGMII_100;
3277 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3278 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3279 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3280 phy_data->start_mode = XGBE_MODE_SFI;
3282 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3284 xgbe_phy_sfp_setup(pdata);
3290 if (netif_msg_probe(pdata))
3291 dev_dbg(pdata->dev, "phy supported=0x%*pb\n",
3292 __ETHTOOL_LINK_MODE_MASK_NBITS,
3293 lks->link_modes.supported);
3295 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) &&
3296 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) {
3297 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
3298 phy_data->phydev_mode);
3301 "mdio port/clause not compatible (%d/%u)\n",
3302 phy_data->mdio_addr, phy_data->phydev_mode);
3307 if (phy_data->redrv && !phy_data->redrv_if) {
3308 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3309 XGBE_MDIO_MODE_CL22);
3312 "redriver mdio port not compatible (%u)\n",
3313 phy_data->redrv_addr);
3318 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3320 /* Register for driving external PHYs */
3321 mii = devm_mdiobus_alloc(pdata->dev);
3323 dev_err(pdata->dev, "mdiobus_alloc failed\n");
3328 mii->name = "amd-xgbe-mii";
3329 mii->read = xgbe_phy_mii_read;
3330 mii->write = xgbe_phy_mii_write;
3331 mii->parent = pdata->dev;
3333 snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev));
3334 ret = mdiobus_register(mii);
3336 dev_err(pdata->dev, "mdiobus_register failed\n");
3339 phy_data->mii = mii;
3344 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if)
3346 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
3348 phy_impl->init = xgbe_phy_init;
3349 phy_impl->exit = xgbe_phy_exit;
3351 phy_impl->reset = xgbe_phy_reset;
3352 phy_impl->start = xgbe_phy_start;
3353 phy_impl->stop = xgbe_phy_stop;
3355 phy_impl->link_status = xgbe_phy_link_status;
3357 phy_impl->valid_speed = xgbe_phy_valid_speed;
3359 phy_impl->use_mode = xgbe_phy_use_mode;
3360 phy_impl->set_mode = xgbe_phy_set_mode;
3361 phy_impl->get_mode = xgbe_phy_get_mode;
3362 phy_impl->switch_mode = xgbe_phy_switch_mode;
3363 phy_impl->cur_mode = xgbe_phy_cur_mode;
3365 phy_impl->an_mode = xgbe_phy_an_mode;
3367 phy_impl->an_config = xgbe_phy_an_config;
3369 phy_impl->an_advertising = xgbe_phy_an_advertising;
3371 phy_impl->an_outcome = xgbe_phy_an_outcome;
3373 phy_impl->an_pre = xgbe_phy_an_pre;
3374 phy_impl->an_post = xgbe_phy_an_post;
3376 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre;
3377 phy_impl->kr_training_post = xgbe_phy_kr_training_post;
3379 phy_impl->module_info = xgbe_phy_module_info;
3380 phy_impl->module_eeprom = xgbe_phy_module_eeprom;