2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
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63 * modification, are permitted provided that the following conditions are met:
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68 * documentation and/or other materials provided with the distribution.
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70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
117 #include <linux/interrupt.h>
118 #include <linux/module.h>
119 #include <linux/kmod.h>
120 #include <linux/mdio.h>
121 #include <linux/phy.h>
122 #include <linux/of.h>
123 #include <linux/bitops.h>
124 #include <linux/jiffies.h>
127 #include "xgbe-common.h"
129 static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata,
130 struct ethtool_eeprom *eeprom, u8 *data)
132 if (!pdata->phy_if.phy_impl.module_eeprom)
135 return pdata->phy_if.phy_impl.module_eeprom(pdata, eeprom, data);
138 static int xgbe_phy_module_info(struct xgbe_prv_data *pdata,
139 struct ethtool_modinfo *modinfo)
141 if (!pdata->phy_if.phy_impl.module_info)
144 return pdata->phy_if.phy_impl.module_info(pdata, modinfo);
147 static void xgbe_an37_clear_interrupts(struct xgbe_prv_data *pdata)
151 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
152 reg &= ~XGBE_AN_CL37_INT_MASK;
153 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
156 static void xgbe_an37_disable_interrupts(struct xgbe_prv_data *pdata)
160 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
161 reg &= ~XGBE_AN_CL37_INT_MASK;
162 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
164 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
165 reg &= ~XGBE_PCS_CL37_BP;
166 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
169 static void xgbe_an37_enable_interrupts(struct xgbe_prv_data *pdata)
173 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
174 reg |= XGBE_PCS_CL37_BP;
175 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
177 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
178 reg |= XGBE_AN_CL37_INT_MASK;
179 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
182 static void xgbe_an73_clear_interrupts(struct xgbe_prv_data *pdata)
184 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
187 static void xgbe_an73_disable_interrupts(struct xgbe_prv_data *pdata)
189 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
192 static void xgbe_an73_enable_interrupts(struct xgbe_prv_data *pdata)
194 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, XGBE_AN_CL73_INT_MASK);
197 static void xgbe_an_enable_interrupts(struct xgbe_prv_data *pdata)
199 switch (pdata->an_mode) {
200 case XGBE_AN_MODE_CL73:
201 case XGBE_AN_MODE_CL73_REDRV:
202 xgbe_an73_enable_interrupts(pdata);
204 case XGBE_AN_MODE_CL37:
205 case XGBE_AN_MODE_CL37_SGMII:
206 xgbe_an37_enable_interrupts(pdata);
213 static void xgbe_an_clear_interrupts_all(struct xgbe_prv_data *pdata)
215 xgbe_an73_clear_interrupts(pdata);
216 xgbe_an37_clear_interrupts(pdata);
219 static void xgbe_kr_mode(struct xgbe_prv_data *pdata)
221 /* Set MAC to 10G speed */
222 pdata->hw_if.set_speed(pdata, SPEED_10000);
224 /* Call PHY implementation support to complete rate change */
225 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KR);
228 static void xgbe_kx_2500_mode(struct xgbe_prv_data *pdata)
230 /* Set MAC to 2.5G speed */
231 pdata->hw_if.set_speed(pdata, SPEED_2500);
233 /* Call PHY implementation support to complete rate change */
234 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_2500);
237 static void xgbe_kx_1000_mode(struct xgbe_prv_data *pdata)
239 /* Set MAC to 1G speed */
240 pdata->hw_if.set_speed(pdata, SPEED_1000);
242 /* Call PHY implementation support to complete rate change */
243 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_1000);
246 static void xgbe_sfi_mode(struct xgbe_prv_data *pdata)
248 /* If a KR re-driver is present, change to KR mode instead */
250 return xgbe_kr_mode(pdata);
252 /* Set MAC to 10G speed */
253 pdata->hw_if.set_speed(pdata, SPEED_10000);
255 /* Call PHY implementation support to complete rate change */
256 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SFI);
259 static void xgbe_x_mode(struct xgbe_prv_data *pdata)
261 /* Set MAC to 1G speed */
262 pdata->hw_if.set_speed(pdata, SPEED_1000);
264 /* Call PHY implementation support to complete rate change */
265 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_X);
268 static void xgbe_sgmii_1000_mode(struct xgbe_prv_data *pdata)
270 /* Set MAC to 1G speed */
271 pdata->hw_if.set_speed(pdata, SPEED_1000);
273 /* Call PHY implementation support to complete rate change */
274 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_1000);
277 static void xgbe_sgmii_100_mode(struct xgbe_prv_data *pdata)
279 /* Set MAC to 1G speed */
280 pdata->hw_if.set_speed(pdata, SPEED_1000);
282 /* Call PHY implementation support to complete rate change */
283 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_100);
286 static enum xgbe_mode xgbe_cur_mode(struct xgbe_prv_data *pdata)
288 return pdata->phy_if.phy_impl.cur_mode(pdata);
291 static bool xgbe_in_kr_mode(struct xgbe_prv_data *pdata)
293 return (xgbe_cur_mode(pdata) == XGBE_MODE_KR);
296 static void xgbe_change_mode(struct xgbe_prv_data *pdata,
300 case XGBE_MODE_KX_1000:
301 xgbe_kx_1000_mode(pdata);
303 case XGBE_MODE_KX_2500:
304 xgbe_kx_2500_mode(pdata);
309 case XGBE_MODE_SGMII_100:
310 xgbe_sgmii_100_mode(pdata);
312 case XGBE_MODE_SGMII_1000:
313 xgbe_sgmii_1000_mode(pdata);
319 xgbe_sfi_mode(pdata);
321 case XGBE_MODE_UNKNOWN:
324 netif_dbg(pdata, link, pdata->netdev,
325 "invalid operation mode requested (%u)\n", mode);
329 static void xgbe_switch_mode(struct xgbe_prv_data *pdata)
331 xgbe_change_mode(pdata, pdata->phy_if.phy_impl.switch_mode(pdata));
334 static void xgbe_set_mode(struct xgbe_prv_data *pdata,
337 if (mode == xgbe_cur_mode(pdata))
340 xgbe_change_mode(pdata, mode);
343 static bool xgbe_use_mode(struct xgbe_prv_data *pdata,
346 return pdata->phy_if.phy_impl.use_mode(pdata, mode);
349 static void xgbe_an37_set(struct xgbe_prv_data *pdata, bool enable,
354 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1);
355 reg &= ~MDIO_VEND2_CTRL1_AN_ENABLE;
358 reg |= MDIO_VEND2_CTRL1_AN_ENABLE;
361 reg |= MDIO_VEND2_CTRL1_AN_RESTART;
363 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg);
366 static void xgbe_an37_restart(struct xgbe_prv_data *pdata)
368 xgbe_an37_enable_interrupts(pdata);
369 xgbe_an37_set(pdata, true, true);
371 netif_dbg(pdata, link, pdata->netdev, "CL37 AN enabled/restarted\n");
374 static void xgbe_an37_disable(struct xgbe_prv_data *pdata)
376 xgbe_an37_set(pdata, false, false);
377 xgbe_an37_disable_interrupts(pdata);
379 netif_dbg(pdata, link, pdata->netdev, "CL37 AN disabled\n");
382 static void xgbe_an73_set(struct xgbe_prv_data *pdata, bool enable,
387 /* Disable KR training for now */
388 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
389 reg &= ~XGBE_KR_TRAINING_ENABLE;
390 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
392 /* Update AN settings */
393 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
394 reg &= ~MDIO_AN_CTRL1_ENABLE;
397 reg |= MDIO_AN_CTRL1_ENABLE;
400 reg |= MDIO_AN_CTRL1_RESTART;
402 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
405 static void xgbe_an73_restart(struct xgbe_prv_data *pdata)
407 xgbe_an73_enable_interrupts(pdata);
408 xgbe_an73_set(pdata, true, true);
410 netif_dbg(pdata, link, pdata->netdev, "CL73 AN enabled/restarted\n");
413 static void xgbe_an73_disable(struct xgbe_prv_data *pdata)
415 xgbe_an73_set(pdata, false, false);
416 xgbe_an73_disable_interrupts(pdata);
420 netif_dbg(pdata, link, pdata->netdev, "CL73 AN disabled\n");
423 static void xgbe_an_restart(struct xgbe_prv_data *pdata)
425 if (pdata->phy_if.phy_impl.an_pre)
426 pdata->phy_if.phy_impl.an_pre(pdata);
428 switch (pdata->an_mode) {
429 case XGBE_AN_MODE_CL73:
430 case XGBE_AN_MODE_CL73_REDRV:
431 xgbe_an73_restart(pdata);
433 case XGBE_AN_MODE_CL37:
434 case XGBE_AN_MODE_CL37_SGMII:
435 xgbe_an37_restart(pdata);
442 static void xgbe_an_disable(struct xgbe_prv_data *pdata)
444 if (pdata->phy_if.phy_impl.an_post)
445 pdata->phy_if.phy_impl.an_post(pdata);
447 switch (pdata->an_mode) {
448 case XGBE_AN_MODE_CL73:
449 case XGBE_AN_MODE_CL73_REDRV:
450 xgbe_an73_disable(pdata);
452 case XGBE_AN_MODE_CL37:
453 case XGBE_AN_MODE_CL37_SGMII:
454 xgbe_an37_disable(pdata);
461 static void xgbe_an_disable_all(struct xgbe_prv_data *pdata)
463 xgbe_an73_disable(pdata);
464 xgbe_an37_disable(pdata);
467 static enum xgbe_an xgbe_an73_tx_training(struct xgbe_prv_data *pdata,
470 unsigned int ad_reg, lp_reg, reg;
472 *state = XGBE_RX_COMPLETE;
474 /* If we're not in KR mode then we're done */
475 if (!xgbe_in_kr_mode(pdata))
476 return XGBE_AN_PAGE_RECEIVED;
478 /* Enable/Disable FEC */
479 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
480 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
482 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL);
483 reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE);
484 if ((ad_reg & 0xc000) && (lp_reg & 0xc000))
485 reg |= pdata->fec_ability;
487 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg);
489 /* Start KR training */
490 if (pdata->phy_if.phy_impl.kr_training_pre)
491 pdata->phy_if.phy_impl.kr_training_pre(pdata);
493 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
494 reg |= XGBE_KR_TRAINING_ENABLE;
495 reg |= XGBE_KR_TRAINING_START;
496 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
498 netif_dbg(pdata, link, pdata->netdev,
499 "KR training initiated\n");
501 if (pdata->phy_if.phy_impl.kr_training_post)
502 pdata->phy_if.phy_impl.kr_training_post(pdata);
504 return XGBE_AN_PAGE_RECEIVED;
507 static enum xgbe_an xgbe_an73_tx_xnp(struct xgbe_prv_data *pdata,
512 *state = XGBE_RX_XNP;
514 msg = XGBE_XNP_MCF_NULL_MESSAGE;
515 msg |= XGBE_XNP_MP_FORMATTED;
517 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0);
518 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0);
519 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg);
521 return XGBE_AN_PAGE_RECEIVED;
524 static enum xgbe_an xgbe_an73_rx_bpa(struct xgbe_prv_data *pdata,
527 unsigned int link_support;
528 unsigned int reg, ad_reg, lp_reg;
530 /* Read Base Ability register 2 first */
531 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
533 /* Check for a supported mode, otherwise restart in a different one */
534 link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20;
535 if (!(reg & link_support))
536 return XGBE_AN_INCOMPAT_LINK;
538 /* Check Extended Next Page support */
539 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
540 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
542 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
543 (lp_reg & XGBE_XNP_NP_EXCHANGE))
544 ? xgbe_an73_tx_xnp(pdata, state)
545 : xgbe_an73_tx_training(pdata, state);
548 static enum xgbe_an xgbe_an73_rx_xnp(struct xgbe_prv_data *pdata,
551 unsigned int ad_reg, lp_reg;
553 /* Check Extended Next Page support */
554 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP);
555 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX);
557 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
558 (lp_reg & XGBE_XNP_NP_EXCHANGE))
559 ? xgbe_an73_tx_xnp(pdata, state)
560 : xgbe_an73_tx_training(pdata, state);
563 static enum xgbe_an xgbe_an73_page_received(struct xgbe_prv_data *pdata)
566 unsigned long an_timeout;
569 if (!pdata->an_start) {
570 pdata->an_start = jiffies;
572 an_timeout = pdata->an_start +
573 msecs_to_jiffies(XGBE_AN_MS_TIMEOUT);
574 if (time_after(jiffies, an_timeout)) {
575 /* Auto-negotiation timed out, reset state */
576 pdata->kr_state = XGBE_RX_BPA;
577 pdata->kx_state = XGBE_RX_BPA;
579 pdata->an_start = jiffies;
581 netif_dbg(pdata, link, pdata->netdev,
582 "CL73 AN timed out, resetting state\n");
586 state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state
591 ret = xgbe_an73_rx_bpa(pdata, state);
595 ret = xgbe_an73_rx_xnp(pdata, state);
605 static enum xgbe_an xgbe_an73_incompat_link(struct xgbe_prv_data *pdata)
607 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
609 /* Be sure we aren't looping trying to negotiate */
610 if (xgbe_in_kr_mode(pdata)) {
611 pdata->kr_state = XGBE_RX_ERROR;
613 if (!XGBE_ADV(lks, 1000baseKX_Full) &&
614 !XGBE_ADV(lks, 2500baseX_Full))
615 return XGBE_AN_NO_LINK;
617 if (pdata->kx_state != XGBE_RX_BPA)
618 return XGBE_AN_NO_LINK;
620 pdata->kx_state = XGBE_RX_ERROR;
622 if (!XGBE_ADV(lks, 10000baseKR_Full))
623 return XGBE_AN_NO_LINK;
625 if (pdata->kr_state != XGBE_RX_BPA)
626 return XGBE_AN_NO_LINK;
629 xgbe_an_disable(pdata);
631 xgbe_switch_mode(pdata);
633 xgbe_an_restart(pdata);
635 return XGBE_AN_INCOMPAT_LINK;
638 static void xgbe_an37_isr(struct xgbe_prv_data *pdata)
642 /* Disable AN interrupts */
643 xgbe_an37_disable_interrupts(pdata);
645 /* Save the interrupt(s) that fired */
646 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
647 pdata->an_int = reg & XGBE_AN_CL37_INT_MASK;
648 pdata->an_status = reg & ~XGBE_AN_CL37_INT_MASK;
651 /* Clear the interrupt(s) that fired and process them */
652 reg &= ~XGBE_AN_CL37_INT_MASK;
653 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
655 queue_work(pdata->an_workqueue, &pdata->an_irq_work);
657 /* Enable AN interrupts */
658 xgbe_an37_enable_interrupts(pdata);
660 /* Reissue interrupt if status is not clear */
661 if (pdata->vdata->irq_reissue_support)
662 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
666 static void xgbe_an73_isr(struct xgbe_prv_data *pdata)
668 /* Disable AN interrupts */
669 xgbe_an73_disable_interrupts(pdata);
671 /* Save the interrupt(s) that fired */
672 pdata->an_int = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT);
675 /* Clear the interrupt(s) that fired and process them */
676 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, ~pdata->an_int);
678 queue_work(pdata->an_workqueue, &pdata->an_irq_work);
680 /* Enable AN interrupts */
681 xgbe_an73_enable_interrupts(pdata);
683 /* Reissue interrupt if status is not clear */
684 if (pdata->vdata->irq_reissue_support)
685 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
689 static void xgbe_an_isr_task(unsigned long data)
691 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
693 netif_dbg(pdata, intr, pdata->netdev, "AN interrupt received\n");
695 switch (pdata->an_mode) {
696 case XGBE_AN_MODE_CL73:
697 case XGBE_AN_MODE_CL73_REDRV:
698 xgbe_an73_isr(pdata);
700 case XGBE_AN_MODE_CL37:
701 case XGBE_AN_MODE_CL37_SGMII:
702 xgbe_an37_isr(pdata);
709 static irqreturn_t xgbe_an_isr(int irq, void *data)
711 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
713 if (pdata->isr_as_tasklet)
714 tasklet_schedule(&pdata->tasklet_an);
716 xgbe_an_isr_task((unsigned long)pdata);
721 static irqreturn_t xgbe_an_combined_isr(struct xgbe_prv_data *pdata)
723 xgbe_an_isr_task((unsigned long)pdata);
728 static void xgbe_an_irq_work(struct work_struct *work)
730 struct xgbe_prv_data *pdata = container_of(work,
731 struct xgbe_prv_data,
734 /* Avoid a race between enabling the IRQ and exiting the work by
735 * waiting for the work to finish and then queueing it
737 flush_work(&pdata->an_work);
738 queue_work(pdata->an_workqueue, &pdata->an_work);
741 static const char *xgbe_state_as_string(enum xgbe_an state)
746 case XGBE_AN_PAGE_RECEIVED:
747 return "Page-Received";
748 case XGBE_AN_INCOMPAT_LINK:
749 return "Incompatible-Link";
750 case XGBE_AN_COMPLETE:
752 case XGBE_AN_NO_LINK:
761 static void xgbe_an37_state_machine(struct xgbe_prv_data *pdata)
763 enum xgbe_an cur_state = pdata->an_state;
768 if (pdata->an_int & XGBE_AN_CL37_INT_CMPLT) {
769 pdata->an_state = XGBE_AN_COMPLETE;
770 pdata->an_int &= ~XGBE_AN_CL37_INT_CMPLT;
772 /* If SGMII is enabled, check the link status */
773 if ((pdata->an_mode == XGBE_AN_MODE_CL37_SGMII) &&
774 !(pdata->an_status & XGBE_SGMII_AN_LINK_STATUS))
775 pdata->an_state = XGBE_AN_NO_LINK;
778 netif_dbg(pdata, link, pdata->netdev, "CL37 AN %s\n",
779 xgbe_state_as_string(pdata->an_state));
781 cur_state = pdata->an_state;
783 switch (pdata->an_state) {
787 case XGBE_AN_COMPLETE:
788 netif_dbg(pdata, link, pdata->netdev,
789 "Auto negotiation successful\n");
792 case XGBE_AN_NO_LINK:
796 pdata->an_state = XGBE_AN_ERROR;
799 if (pdata->an_state == XGBE_AN_ERROR) {
800 netdev_err(pdata->netdev,
801 "error during auto-negotiation, state=%u\n",
805 xgbe_an37_clear_interrupts(pdata);
808 if (pdata->an_state >= XGBE_AN_COMPLETE) {
809 pdata->an_result = pdata->an_state;
810 pdata->an_state = XGBE_AN_READY;
812 if (pdata->phy_if.phy_impl.an_post)
813 pdata->phy_if.phy_impl.an_post(pdata);
815 netif_dbg(pdata, link, pdata->netdev, "CL37 AN result: %s\n",
816 xgbe_state_as_string(pdata->an_result));
819 xgbe_an37_enable_interrupts(pdata);
822 static void xgbe_an73_state_machine(struct xgbe_prv_data *pdata)
824 enum xgbe_an cur_state = pdata->an_state;
830 if (pdata->an_int & XGBE_AN_CL73_PG_RCV) {
831 pdata->an_state = XGBE_AN_PAGE_RECEIVED;
832 pdata->an_int &= ~XGBE_AN_CL73_PG_RCV;
833 } else if (pdata->an_int & XGBE_AN_CL73_INC_LINK) {
834 pdata->an_state = XGBE_AN_INCOMPAT_LINK;
835 pdata->an_int &= ~XGBE_AN_CL73_INC_LINK;
836 } else if (pdata->an_int & XGBE_AN_CL73_INT_CMPLT) {
837 pdata->an_state = XGBE_AN_COMPLETE;
838 pdata->an_int &= ~XGBE_AN_CL73_INT_CMPLT;
840 pdata->an_state = XGBE_AN_ERROR;
844 netif_dbg(pdata, link, pdata->netdev, "CL73 AN %s\n",
845 xgbe_state_as_string(pdata->an_state));
847 cur_state = pdata->an_state;
849 switch (pdata->an_state) {
851 pdata->an_supported = 0;
854 case XGBE_AN_PAGE_RECEIVED:
855 pdata->an_state = xgbe_an73_page_received(pdata);
856 pdata->an_supported++;
859 case XGBE_AN_INCOMPAT_LINK:
860 pdata->an_supported = 0;
861 pdata->parallel_detect = 0;
862 pdata->an_state = xgbe_an73_incompat_link(pdata);
865 case XGBE_AN_COMPLETE:
866 pdata->parallel_detect = pdata->an_supported ? 0 : 1;
867 netif_dbg(pdata, link, pdata->netdev, "%s successful\n",
868 pdata->an_supported ? "Auto negotiation"
869 : "Parallel detection");
872 case XGBE_AN_NO_LINK:
876 pdata->an_state = XGBE_AN_ERROR;
879 if (pdata->an_state == XGBE_AN_NO_LINK) {
881 xgbe_an73_clear_interrupts(pdata);
882 } else if (pdata->an_state == XGBE_AN_ERROR) {
883 netdev_err(pdata->netdev,
884 "error during auto-negotiation, state=%u\n",
888 xgbe_an73_clear_interrupts(pdata);
891 if (pdata->an_state >= XGBE_AN_COMPLETE) {
892 pdata->an_result = pdata->an_state;
893 pdata->an_state = XGBE_AN_READY;
894 pdata->kr_state = XGBE_RX_BPA;
895 pdata->kx_state = XGBE_RX_BPA;
898 if (pdata->phy_if.phy_impl.an_post)
899 pdata->phy_if.phy_impl.an_post(pdata);
901 netif_dbg(pdata, link, pdata->netdev, "CL73 AN result: %s\n",
902 xgbe_state_as_string(pdata->an_result));
905 if (cur_state != pdata->an_state)
911 xgbe_an73_enable_interrupts(pdata);
914 static void xgbe_an_state_machine(struct work_struct *work)
916 struct xgbe_prv_data *pdata = container_of(work,
917 struct xgbe_prv_data,
920 mutex_lock(&pdata->an_mutex);
922 switch (pdata->an_mode) {
923 case XGBE_AN_MODE_CL73:
924 case XGBE_AN_MODE_CL73_REDRV:
925 xgbe_an73_state_machine(pdata);
927 case XGBE_AN_MODE_CL37:
928 case XGBE_AN_MODE_CL37_SGMII:
929 xgbe_an37_state_machine(pdata);
935 /* Reissue interrupt if status is not clear */
936 if (pdata->vdata->irq_reissue_support)
937 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
939 mutex_unlock(&pdata->an_mutex);
942 static void xgbe_an37_init(struct xgbe_prv_data *pdata)
944 struct ethtool_link_ksettings lks;
947 pdata->phy_if.phy_impl.an_advertising(pdata, &lks);
949 /* Set up Advertisement register */
950 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
951 if (XGBE_ADV(&lks, Pause))
956 if (XGBE_ADV(&lks, Asym_Pause))
961 /* Full duplex, but not half */
962 reg |= XGBE_AN_CL37_FD_MASK;
963 reg &= ~XGBE_AN_CL37_HD_MASK;
965 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE, reg);
967 /* Set up the Control register */
968 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
969 reg &= ~XGBE_AN_CL37_TX_CONFIG_MASK;
970 reg &= ~XGBE_AN_CL37_PCS_MODE_MASK;
972 switch (pdata->an_mode) {
973 case XGBE_AN_MODE_CL37:
974 reg |= XGBE_AN_CL37_PCS_MODE_BASEX;
976 case XGBE_AN_MODE_CL37_SGMII:
977 reg |= XGBE_AN_CL37_PCS_MODE_SGMII;
983 reg |= XGBE_AN_CL37_MII_CTRL_8BIT;
985 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
987 netif_dbg(pdata, link, pdata->netdev, "CL37 AN (%s) initialized\n",
988 (pdata->an_mode == XGBE_AN_MODE_CL37) ? "BaseX" : "SGMII");
991 static void xgbe_an73_init(struct xgbe_prv_data *pdata)
993 struct ethtool_link_ksettings lks;
996 pdata->phy_if.phy_impl.an_advertising(pdata, &lks);
998 /* Set up Advertisement register 3 first */
999 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1000 if (XGBE_ADV(&lks, 10000baseR_FEC))
1005 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg);
1007 /* Set up Advertisement register 2 next */
1008 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1009 if (XGBE_ADV(&lks, 10000baseKR_Full))
1014 if (XGBE_ADV(&lks, 1000baseKX_Full) ||
1015 XGBE_ADV(&lks, 2500baseX_Full))
1020 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg);
1022 /* Set up Advertisement register 1 last */
1023 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1024 if (XGBE_ADV(&lks, Pause))
1029 if (XGBE_ADV(&lks, Asym_Pause))
1034 /* We don't intend to perform XNP */
1035 reg &= ~XGBE_XNP_NP_EXCHANGE;
1037 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);
1039 netif_dbg(pdata, link, pdata->netdev, "CL73 AN initialized\n");
1042 static void xgbe_an_init(struct xgbe_prv_data *pdata)
1044 /* Set up advertisement registers based on current settings */
1045 pdata->an_mode = pdata->phy_if.phy_impl.an_mode(pdata);
1046 switch (pdata->an_mode) {
1047 case XGBE_AN_MODE_CL73:
1048 case XGBE_AN_MODE_CL73_REDRV:
1049 xgbe_an73_init(pdata);
1051 case XGBE_AN_MODE_CL37:
1052 case XGBE_AN_MODE_CL37_SGMII:
1053 xgbe_an37_init(pdata);
1060 static const char *xgbe_phy_fc_string(struct xgbe_prv_data *pdata)
1062 if (pdata->tx_pause && pdata->rx_pause)
1064 else if (pdata->rx_pause)
1066 else if (pdata->tx_pause)
1072 static const char *xgbe_phy_speed_string(int speed)
1086 return "Unsupported";
1090 static void xgbe_phy_print_status(struct xgbe_prv_data *pdata)
1092 if (pdata->phy.link)
1093 netdev_info(pdata->netdev,
1094 "Link is Up - %s/%s - flow control %s\n",
1095 xgbe_phy_speed_string(pdata->phy.speed),
1096 pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half",
1097 xgbe_phy_fc_string(pdata));
1099 netdev_info(pdata->netdev, "Link is Down\n");
1102 static void xgbe_phy_adjust_link(struct xgbe_prv_data *pdata)
1106 if (pdata->phy.link) {
1107 /* Flow control support */
1108 pdata->pause_autoneg = pdata->phy.pause_autoneg;
1110 if (pdata->tx_pause != pdata->phy.tx_pause) {
1112 pdata->hw_if.config_tx_flow_control(pdata);
1113 pdata->tx_pause = pdata->phy.tx_pause;
1116 if (pdata->rx_pause != pdata->phy.rx_pause) {
1118 pdata->hw_if.config_rx_flow_control(pdata);
1119 pdata->rx_pause = pdata->phy.rx_pause;
1123 if (pdata->phy_speed != pdata->phy.speed) {
1125 pdata->phy_speed = pdata->phy.speed;
1128 if (pdata->phy_link != pdata->phy.link) {
1130 pdata->phy_link = pdata->phy.link;
1132 } else if (pdata->phy_link) {
1134 pdata->phy_link = 0;
1135 pdata->phy_speed = SPEED_UNKNOWN;
1138 if (new_state && netif_msg_link(pdata))
1139 xgbe_phy_print_status(pdata);
1142 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
1144 return pdata->phy_if.phy_impl.valid_speed(pdata, speed);
1147 static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata)
1149 enum xgbe_mode mode;
1151 netif_dbg(pdata, link, pdata->netdev, "fixed PHY configuration\n");
1153 /* Disable auto-negotiation */
1154 xgbe_an_disable(pdata);
1156 /* Set specified mode for specified speed */
1157 mode = pdata->phy_if.phy_impl.get_mode(pdata, pdata->phy.speed);
1159 case XGBE_MODE_KX_1000:
1160 case XGBE_MODE_KX_2500:
1162 case XGBE_MODE_SGMII_100:
1163 case XGBE_MODE_SGMII_1000:
1167 case XGBE_MODE_UNKNOWN:
1172 /* Validate duplex mode */
1173 if (pdata->phy.duplex != DUPLEX_FULL)
1176 xgbe_set_mode(pdata, mode);
1181 static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
1185 set_bit(XGBE_LINK_INIT, &pdata->dev_state);
1186 pdata->link_check = jiffies;
1188 ret = pdata->phy_if.phy_impl.an_config(pdata);
1192 if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1193 ret = xgbe_phy_config_fixed(pdata);
1194 if (ret || !pdata->kr_redrv)
1197 netif_dbg(pdata, link, pdata->netdev, "AN redriver support\n");
1199 netif_dbg(pdata, link, pdata->netdev, "AN PHY configuration\n");
1202 /* Disable auto-negotiation interrupt */
1203 disable_irq(pdata->an_irq);
1205 /* Start auto-negotiation in a supported mode */
1206 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) {
1207 xgbe_set_mode(pdata, XGBE_MODE_KR);
1208 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) {
1209 xgbe_set_mode(pdata, XGBE_MODE_KX_2500);
1210 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
1211 xgbe_set_mode(pdata, XGBE_MODE_KX_1000);
1212 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
1213 xgbe_set_mode(pdata, XGBE_MODE_SFI);
1214 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
1215 xgbe_set_mode(pdata, XGBE_MODE_X);
1216 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
1217 xgbe_set_mode(pdata, XGBE_MODE_SGMII_1000);
1218 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
1219 xgbe_set_mode(pdata, XGBE_MODE_SGMII_100);
1221 enable_irq(pdata->an_irq);
1225 /* Disable and stop any in progress auto-negotiation */
1226 xgbe_an_disable_all(pdata);
1228 /* Clear any auto-negotitation interrupts */
1229 xgbe_an_clear_interrupts_all(pdata);
1231 pdata->an_result = XGBE_AN_READY;
1232 pdata->an_state = XGBE_AN_READY;
1233 pdata->kr_state = XGBE_RX_BPA;
1234 pdata->kx_state = XGBE_RX_BPA;
1236 /* Re-enable auto-negotiation interrupt */
1237 enable_irq(pdata->an_irq);
1239 xgbe_an_init(pdata);
1240 xgbe_an_restart(pdata);
1245 static int xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
1249 mutex_lock(&pdata->an_mutex);
1251 ret = __xgbe_phy_config_aneg(pdata);
1253 set_bit(XGBE_LINK_ERR, &pdata->dev_state);
1255 clear_bit(XGBE_LINK_ERR, &pdata->dev_state);
1257 mutex_unlock(&pdata->an_mutex);
1262 static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata)
1264 return (pdata->an_result == XGBE_AN_COMPLETE);
1267 static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata)
1269 unsigned long link_timeout;
1271 link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * HZ);
1272 if (time_after(jiffies, link_timeout)) {
1273 netif_dbg(pdata, link, pdata->netdev, "AN link timeout\n");
1274 xgbe_phy_config_aneg(pdata);
1278 static enum xgbe_mode xgbe_phy_status_aneg(struct xgbe_prv_data *pdata)
1280 return pdata->phy_if.phy_impl.an_outcome(pdata);
1283 static void xgbe_phy_status_result(struct xgbe_prv_data *pdata)
1285 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1286 enum xgbe_mode mode;
1288 XGBE_ZERO_LP_ADV(lks);
1290 if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect)
1291 mode = xgbe_cur_mode(pdata);
1293 mode = xgbe_phy_status_aneg(pdata);
1296 case XGBE_MODE_SGMII_100:
1297 pdata->phy.speed = SPEED_100;
1300 case XGBE_MODE_KX_1000:
1301 case XGBE_MODE_SGMII_1000:
1302 pdata->phy.speed = SPEED_1000;
1304 case XGBE_MODE_KX_2500:
1305 pdata->phy.speed = SPEED_2500;
1309 pdata->phy.speed = SPEED_10000;
1311 case XGBE_MODE_UNKNOWN:
1313 pdata->phy.speed = SPEED_UNKNOWN;
1316 pdata->phy.duplex = DUPLEX_FULL;
1318 xgbe_set_mode(pdata, mode);
1321 static void xgbe_phy_status(struct xgbe_prv_data *pdata)
1323 unsigned int link_aneg;
1326 if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) {
1327 netif_carrier_off(pdata->netdev);
1329 pdata->phy.link = 0;
1333 link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE);
1335 pdata->phy.link = pdata->phy_if.phy_impl.link_status(pdata,
1338 xgbe_phy_config_aneg(pdata);
1342 if (pdata->phy.link) {
1343 if (link_aneg && !xgbe_phy_aneg_done(pdata)) {
1344 xgbe_check_link_timeout(pdata);
1348 xgbe_phy_status_result(pdata);
1350 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state))
1351 clear_bit(XGBE_LINK_INIT, &pdata->dev_state);
1353 netif_carrier_on(pdata->netdev);
1355 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
1356 xgbe_check_link_timeout(pdata);
1362 xgbe_phy_status_result(pdata);
1364 netif_carrier_off(pdata->netdev);
1368 xgbe_phy_adjust_link(pdata);
1371 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
1373 netif_dbg(pdata, link, pdata->netdev, "stopping PHY\n");
1375 if (!pdata->phy_started)
1378 /* Indicate the PHY is down */
1379 pdata->phy_started = 0;
1381 /* Disable auto-negotiation */
1382 xgbe_an_disable_all(pdata);
1384 if (pdata->dev_irq != pdata->an_irq)
1385 devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1387 pdata->phy_if.phy_impl.stop(pdata);
1389 pdata->phy.link = 0;
1390 netif_carrier_off(pdata->netdev);
1392 xgbe_phy_adjust_link(pdata);
1395 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
1397 struct net_device *netdev = pdata->netdev;
1400 netif_dbg(pdata, link, pdata->netdev, "starting PHY\n");
1402 ret = pdata->phy_if.phy_impl.start(pdata);
1406 /* If we have a separate AN irq, enable it */
1407 if (pdata->dev_irq != pdata->an_irq) {
1408 tasklet_init(&pdata->tasklet_an, xgbe_an_isr_task,
1409 (unsigned long)pdata);
1411 ret = devm_request_irq(pdata->dev, pdata->an_irq,
1412 xgbe_an_isr, 0, pdata->an_name,
1415 netdev_err(netdev, "phy irq request failed\n");
1420 /* Set initial mode - call the mode setting routines
1421 * directly to insure we are properly configured
1423 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) {
1424 xgbe_kr_mode(pdata);
1425 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) {
1426 xgbe_kx_2500_mode(pdata);
1427 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
1428 xgbe_kx_1000_mode(pdata);
1429 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
1430 xgbe_sfi_mode(pdata);
1431 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
1433 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
1434 xgbe_sgmii_1000_mode(pdata);
1435 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
1436 xgbe_sgmii_100_mode(pdata);
1442 /* Indicate the PHY is up and running */
1443 pdata->phy_started = 1;
1445 xgbe_an_init(pdata);
1446 xgbe_an_enable_interrupts(pdata);
1448 return xgbe_phy_config_aneg(pdata);
1451 if (pdata->dev_irq != pdata->an_irq)
1452 devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1455 pdata->phy_if.phy_impl.stop(pdata);
1460 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1464 ret = pdata->phy_if.phy_impl.reset(pdata);
1468 /* Disable auto-negotiation for now */
1469 xgbe_an_disable_all(pdata);
1471 /* Clear auto-negotiation interrupts */
1472 xgbe_an_clear_interrupts_all(pdata);
1477 static void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata)
1479 struct device *dev = pdata->dev;
1481 dev_dbg(dev, "\n************* PHY Reg dump **********************\n");
1483 dev_dbg(dev, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
1484 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
1485 dev_dbg(dev, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
1486 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1));
1487 dev_dbg(dev, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1,
1488 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1));
1489 dev_dbg(dev, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2,
1490 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2));
1491 dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1,
1492 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1));
1493 dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2,
1494 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2));
1496 dev_dbg(dev, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
1497 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
1498 dev_dbg(dev, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
1499 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1));
1500 dev_dbg(dev, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n",
1502 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE));
1503 dev_dbg(dev, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n",
1504 MDIO_AN_ADVERTISE + 1,
1505 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1));
1506 dev_dbg(dev, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n",
1507 MDIO_AN_ADVERTISE + 2,
1508 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2));
1509 dev_dbg(dev, "Auto-Neg Completion Reg (%#06x) = %#06x\n",
1511 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT));
1513 dev_dbg(dev, "\n*************************************************\n");
1516 static int xgbe_phy_best_advertised_speed(struct xgbe_prv_data *pdata)
1518 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1520 if (XGBE_ADV(lks, 10000baseKR_Full))
1522 else if (XGBE_ADV(lks, 10000baseT_Full))
1524 else if (XGBE_ADV(lks, 2500baseX_Full))
1526 else if (XGBE_ADV(lks, 2500baseT_Full))
1528 else if (XGBE_ADV(lks, 1000baseKX_Full))
1530 else if (XGBE_ADV(lks, 1000baseT_Full))
1532 else if (XGBE_ADV(lks, 100baseT_Full))
1535 return SPEED_UNKNOWN;
1538 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
1540 pdata->phy_if.phy_impl.exit(pdata);
1543 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
1545 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1548 mutex_init(&pdata->an_mutex);
1549 INIT_WORK(&pdata->an_irq_work, xgbe_an_irq_work);
1550 INIT_WORK(&pdata->an_work, xgbe_an_state_machine);
1551 pdata->mdio_mmd = MDIO_MMD_PCS;
1553 /* Check for FEC support */
1554 pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD,
1555 MDIO_PMA_10GBR_FECABLE);
1556 pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE |
1557 MDIO_PMA_10GBR_FECABLE_ERRABLE);
1559 /* Setup the phy (including supported features) */
1560 ret = pdata->phy_if.phy_impl.init(pdata);
1564 /* Copy supported link modes to advertising link modes */
1565 XGBE_LM_COPY(lks, advertising, lks, supported);
1567 pdata->phy.address = 0;
1569 if (XGBE_ADV(lks, Autoneg)) {
1570 pdata->phy.autoneg = AUTONEG_ENABLE;
1571 pdata->phy.speed = SPEED_UNKNOWN;
1572 pdata->phy.duplex = DUPLEX_UNKNOWN;
1574 pdata->phy.autoneg = AUTONEG_DISABLE;
1575 pdata->phy.speed = xgbe_phy_best_advertised_speed(pdata);
1576 pdata->phy.duplex = DUPLEX_FULL;
1579 pdata->phy.link = 0;
1581 pdata->phy.pause_autoneg = pdata->pause_autoneg;
1582 pdata->phy.tx_pause = pdata->tx_pause;
1583 pdata->phy.rx_pause = pdata->rx_pause;
1585 /* Fix up Flow Control advertising */
1586 XGBE_CLR_ADV(lks, Pause);
1587 XGBE_CLR_ADV(lks, Asym_Pause);
1589 if (pdata->rx_pause) {
1590 XGBE_SET_ADV(lks, Pause);
1591 XGBE_SET_ADV(lks, Asym_Pause);
1594 if (pdata->tx_pause) {
1595 /* Equivalent to XOR of Asym_Pause */
1596 if (XGBE_ADV(lks, Asym_Pause))
1597 XGBE_CLR_ADV(lks, Asym_Pause);
1599 XGBE_SET_ADV(lks, Asym_Pause);
1602 if (netif_msg_drv(pdata))
1603 xgbe_dump_phy_registers(pdata);
1608 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *phy_if)
1610 phy_if->phy_init = xgbe_phy_init;
1611 phy_if->phy_exit = xgbe_phy_exit;
1613 phy_if->phy_reset = xgbe_phy_reset;
1614 phy_if->phy_start = xgbe_phy_start;
1615 phy_if->phy_stop = xgbe_phy_stop;
1617 phy_if->phy_status = xgbe_phy_status;
1618 phy_if->phy_config_aneg = xgbe_phy_config_aneg;
1620 phy_if->phy_valid_speed = xgbe_phy_valid_speed;
1622 phy_if->an_isr = xgbe_an_combined_isr;
1624 phy_if->module_info = xgbe_phy_module_info;
1625 phy_if->module_eeprom = xgbe_phy_module_eeprom;