drivers/net/dsa/sja1105/sja1105.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
   3  * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
   4  */
   5 #ifndef _SJA1105_H
   6 #define _SJA1105_H
   7
   8 #include <linux/ptp_clock_kernel.h>
   9 #include <linux/timecounter.h>
  10 #include <linux/dsa/sja1105.h>
  11 #include <linux/dsa/8021q.h>
  12 #include <net/dsa.h>
  13 #include <linux/mutex.h>
  14 #include "sja1105_static_config.h"
  15
  16 #define SJA1105ET_FDB_BIN_SIZE          4
  17 /* The hardware value is in multiples of 10 ms.
  18  * The passed parameter is in multiples of 1 ms.
  19  */
  20 #define SJA1105_AGEING_TIME_MS(ms)      ((ms) / 10)
  21 #define SJA1105_NUM_L2_POLICERS         SJA1110_MAX_L2_POLICING_COUNT
  22
  23 typedef enum {
  24         SPI_READ = 0,
  25         SPI_WRITE = 1,
  26 } sja1105_spi_rw_mode_t;
  27
  28 #include "sja1105_tas.h"
  29 #include "sja1105_ptp.h"
  30
  31 enum sja1105_stats_area {
  32         MAC,
  33         HL1,
  34         HL2,
  35         ETHER,
  36         __MAX_SJA1105_STATS_AREA,
  37 };
  38
  39 /* Keeps the different addresses between E/T and P/Q/R/S */
  40 struct sja1105_regs {
  41         u64 device_id;
  42         u64 prod_id;
  43         u64 status;
  44         u64 port_control;
  45         u64 rgu;
  46         u64 vl_status;
  47         u64 config;
  48         u64 rmii_pll1;
  49         u64 ptppinst;
  50         u64 ptppindur;
  51         u64 ptp_control;
  52         u64 ptpclkval;
  53         u64 ptpclkrate;
  54         u64 ptpclkcorp;
  55         u64 ptpsyncts;
  56         u64 ptpschtm;
  57         u64 ptpegr_ts[SJA1105_MAX_NUM_PORTS];
  58         u64 pad_mii_tx[SJA1105_MAX_NUM_PORTS];
  59         u64 pad_mii_rx[SJA1105_MAX_NUM_PORTS];
  60         u64 pad_mii_id[SJA1105_MAX_NUM_PORTS];
  61         u64 cgu_idiv[SJA1105_MAX_NUM_PORTS];
  62         u64 mii_tx_clk[SJA1105_MAX_NUM_PORTS];
  63         u64 mii_rx_clk[SJA1105_MAX_NUM_PORTS];
  64         u64 mii_ext_tx_clk[SJA1105_MAX_NUM_PORTS];
  65         u64 mii_ext_rx_clk[SJA1105_MAX_NUM_PORTS];
  66         u64 rgmii_tx_clk[SJA1105_MAX_NUM_PORTS];
  67         u64 rmii_ref_clk[SJA1105_MAX_NUM_PORTS];
  68         u64 rmii_ext_tx_clk[SJA1105_MAX_NUM_PORTS];
  69         u64 stats[__MAX_SJA1105_STATS_AREA][SJA1105_MAX_NUM_PORTS];
  70         u64 mdio_100base_tx;
  71         u64 mdio_100base_t1;
  72 };
  73
  74 struct sja1105_mdio_private {
  75         struct sja1105_private *priv;
  76 };
  77
  78 enum {
  79         SJA1105_SPEED_AUTO,
  80         SJA1105_SPEED_10MBPS,
  81         SJA1105_SPEED_100MBPS,
  82         SJA1105_SPEED_1000MBPS,
  83         SJA1105_SPEED_2500MBPS,
  84         SJA1105_SPEED_MAX,
  85 };
  86
  87 enum sja1105_internal_phy_t {
  88         SJA1105_NO_PHY          = 0,
  89         SJA1105_PHY_BASE_TX,
  90         SJA1105_PHY_BASE_T1,
  91 };
  92
  93 struct sja1105_info {
  94         u64 device_id;
  95         /* Needed for distinction between P and R, and between Q and S
  96          * (since the parts with/without SGMII share the same
  97          * switch core and device_id)
  98          */
  99         u64 part_no;
 100         /* E/T and P/Q/R/S have partial timestamps of different sizes.
 101          * They must be reconstructed on both families anyway to get the full
 102          * 64-bit values back.
 103          */
 104         int ptp_ts_bits;
 105         /* Also SPI commands are of different sizes to retrieve
 106          * the egress timestamps.
 107          */
 108         int ptpegr_ts_bytes;
 109         int num_cbs_shapers;
 110         int max_frame_mem;
 111         int num_ports;
 112         bool multiple_cascade_ports;
 113         enum dsa_tag_protocol tag_proto;
 114         const struct sja1105_dynamic_table_ops *dyn_ops;
 115         const struct sja1105_table_ops *static_ops;
 116         const struct sja1105_regs *regs;
 117         /* Both E/T and P/Q/R/S have quirks when it comes to popping the S-Tag
 118          * from double-tagged frames. E/T will pop it only when it's equal to
 119          * TPID from the General Parameters Table, while P/Q/R/S will only
 120          * pop it when it's equal to TPID2.
 121          */
 122         u16 qinq_tpid;
 123         bool can_limit_mcast_flood;
 124         int (*reset_cmd)(struct dsa_switch *ds);
 125         int (*setup_rgmii_delay)(const void *ctx, int port);
 126         /* Prototypes from include/net/dsa.h */
 127         int (*fdb_add_cmd)(struct dsa_switch *ds, int port,
 128                            const unsigned char *addr, u16 vid);
 129         int (*fdb_del_cmd)(struct dsa_switch *ds, int port,
 130                            const unsigned char *addr, u16 vid);
 131         void (*ptp_cmd_packing)(u8 *buf, struct sja1105_ptp_cmd *cmd,
 132                                 enum packing_op op);
 133         bool (*rxtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb);
 134         void (*txtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb);
 135         int (*clocking_setup)(struct sja1105_private *priv);
 136         int (*pcs_mdio_read)(struct mii_bus *bus, int phy, int reg);
 137         int (*pcs_mdio_write)(struct mii_bus *bus, int phy, int reg, u16 val);
 138         const char *name;
 139         bool supports_mii[SJA1105_MAX_NUM_PORTS];
 140         bool supports_rmii[SJA1105_MAX_NUM_PORTS];
 141         bool supports_rgmii[SJA1105_MAX_NUM_PORTS];
 142         bool supports_sgmii[SJA1105_MAX_NUM_PORTS];
 143         bool supports_2500basex[SJA1105_MAX_NUM_PORTS];
 144         enum sja1105_internal_phy_t internal_phy[SJA1105_MAX_NUM_PORTS];
 145         const u64 port_speed[SJA1105_SPEED_MAX];
 146 };
 147
 148 enum sja1105_key_type {
 149         SJA1105_KEY_BCAST,
 150         SJA1105_KEY_TC,
 151         SJA1105_KEY_VLAN_UNAWARE_VL,
 152         SJA1105_KEY_VLAN_AWARE_VL,
 153 };
 154
 155 struct sja1105_key {
 156         enum sja1105_key_type type;
 157
 158         union {
 159                 /* SJA1105_KEY_TC */
 160                 struct {
 161                         int pcp;
 162                 } tc;
 163
 164                 /* SJA1105_KEY_VLAN_UNAWARE_VL */
 165                 /* SJA1105_KEY_VLAN_AWARE_VL */
 166                 struct {
 167                         u64 dmac;
 168                         u16 vid;
 169                         u16 pcp;
 170                 } vl;
 171         };
 172 };
 173
 174 enum sja1105_rule_type {
 175         SJA1105_RULE_BCAST_POLICER,
 176         SJA1105_RULE_TC_POLICER,
 177         SJA1105_RULE_VL,
 178 };
 179
 180 enum sja1105_vl_type {
 181         SJA1105_VL_NONCRITICAL,
 182         SJA1105_VL_RATE_CONSTRAINED,
 183         SJA1105_VL_TIME_TRIGGERED,
 184 };
 185
 186 struct sja1105_rule {
 187         struct list_head list;
 188         unsigned long cookie;
 189         unsigned long port_mask;
 190         struct sja1105_key key;
 191         enum sja1105_rule_type type;
 192
 193         /* Action */
 194         union {
 195                 /* SJA1105_RULE_BCAST_POLICER */
 196                 struct {
 197                         int sharindx;
 198                 } bcast_pol;
 199
 200                 /* SJA1105_RULE_TC_POLICER */
 201                 struct {
 202                         int sharindx;
 203                 } tc_pol;
 204
 205                 /* SJA1105_RULE_VL */
 206                 struct {
 207                         enum sja1105_vl_type type;
 208                         unsigned long destports;
 209                         int sharindx;
 210                         int maxlen;
 211                         int ipv;
 212                         u64 base_time;
 213                         u64 cycle_time;
 214                         int num_entries;
 215                         struct action_gate_entry *entries;
 216                         struct flow_stats stats;
 217                 } vl;
 218         };
 219 };
 220
 221 struct sja1105_flow_block {
 222         struct list_head rules;
 223         bool l2_policer_used[SJA1105_NUM_L2_POLICERS];
 224         int num_virtual_links;
 225 };
 226
 227 struct sja1105_bridge_vlan {
 228         struct list_head list;
 229         int port;
 230         u16 vid;
 231         bool pvid;
 232         bool untagged;
 233 };
 234
 235 enum sja1105_vlan_state {
 236         SJA1105_VLAN_UNAWARE,
 237         SJA1105_VLAN_BEST_EFFORT,
 238         SJA1105_VLAN_FILTERING_FULL,
 239 };
 240
 241 struct sja1105_private {
 242         struct sja1105_static_config static_config;
 243         bool rgmii_rx_delay[SJA1105_MAX_NUM_PORTS];
 244         bool rgmii_tx_delay[SJA1105_MAX_NUM_PORTS];
 245         phy_interface_t phy_mode[SJA1105_MAX_NUM_PORTS];
 246         bool fixed_link[SJA1105_MAX_NUM_PORTS];
 247         bool best_effort_vlan_filtering;
 248         unsigned long learn_ena;
 249         unsigned long ucast_egress_floods;
 250         unsigned long bcast_egress_floods;
 251         const struct sja1105_info *info;
 252         size_t max_xfer_len;
 253         struct gpio_desc *reset_gpio;
 254         struct spi_device *spidev;
 255         struct dsa_switch *ds;
 256         struct list_head dsa_8021q_vlans;
 257         struct list_head bridge_vlans;
 258         struct sja1105_flow_block flow_block;
 259         struct sja1105_port ports[SJA1105_MAX_NUM_PORTS];
 260         /* Serializes transmission of management frames so that
 261          * the switch doesn't confuse them with one another.
 262          */
 263         struct mutex mgmt_lock;
 264         struct dsa_8021q_context *dsa_8021q_ctx;
 265         enum sja1105_vlan_state vlan_state;
 266         struct devlink_region **regions;
 267         struct sja1105_cbs_entry *cbs;
 268         struct mii_bus *mdio_base_t1;
 269         struct mii_bus *mdio_base_tx;
 270         struct mii_bus *mdio_pcs;
 271         struct dw_xpcs *xpcs[SJA1105_MAX_NUM_PORTS];
 272         struct sja1105_tagger_data tagger_data;
 273         struct sja1105_ptp_data ptp_data;
 274         struct sja1105_tas_data tas_data;
 275 };
 276
 277 #include "sja1105_dynamic_config.h"
 278
 279 struct sja1105_spi_message {
 280         u64 access;
 281         u64 read_count;
 282         u64 address;
 283 };
 284
 285 /* From sja1105_main.c */
 286 enum sja1105_reset_reason {
 287         SJA1105_VLAN_FILTERING = 0,
 288         SJA1105_RX_HWTSTAMPING,
 289         SJA1105_AGEING_TIME,
 290         SJA1105_SCHEDULING,
 291         SJA1105_BEST_EFFORT_POLICING,
 292         SJA1105_VIRTUAL_LINKS,
 293 };
 294
 295 int sja1105_static_config_reload(struct sja1105_private *priv,
 296                                  enum sja1105_reset_reason reason);
 297 int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,
 298                            struct netlink_ext_ack *extack);
 299 void sja1105_frame_memory_partitioning(struct sja1105_private *priv);
 300
 301 /* From sja1105_mdio.c */
 302 int sja1105_mdiobus_register(struct dsa_switch *ds);
 303 void sja1105_mdiobus_unregister(struct dsa_switch *ds);
 304 int sja1105_pcs_mdio_read(struct mii_bus *bus, int phy, int reg);
 305 int sja1105_pcs_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val);
 306
 307 /* From sja1105_devlink.c */
 308 int sja1105_devlink_setup(struct dsa_switch *ds);
 309 void sja1105_devlink_teardown(struct dsa_switch *ds);
 310 int sja1105_devlink_param_get(struct dsa_switch *ds, u32 id,
 311                               struct devlink_param_gset_ctx *ctx);
 312 int sja1105_devlink_param_set(struct dsa_switch *ds, u32 id,
 313                               struct devlink_param_gset_ctx *ctx);
 314 int sja1105_devlink_info_get(struct dsa_switch *ds,
 315                              struct devlink_info_req *req,
 316                              struct netlink_ext_ack *extack);
 317
 318 /* From sja1105_spi.c */
 319 int sja1105_xfer_buf(const struct sja1105_private *priv,
 320                      sja1105_spi_rw_mode_t rw, u64 reg_addr,
 321                      u8 *buf, size_t len);
 322 int sja1105_xfer_u32(const struct sja1105_private *priv,
 323                      sja1105_spi_rw_mode_t rw, u64 reg_addr, u32 *value,
 324                      struct ptp_system_timestamp *ptp_sts);
 325 int sja1105_xfer_u64(const struct sja1105_private *priv,
 326                      sja1105_spi_rw_mode_t rw, u64 reg_addr, u64 *value,
 327                      struct ptp_system_timestamp *ptp_sts);
 328 int static_config_buf_prepare_for_upload(struct sja1105_private *priv,
 329                                          void *config_buf, int buf_len);
 330 int sja1105_static_config_upload(struct sja1105_private *priv);
 331 int sja1105_inhibit_tx(const struct sja1105_private *priv,
 332                        unsigned long port_bitmap, bool tx_inhibited);
 333
 334 extern const struct sja1105_info sja1105e_info;
 335 extern const struct sja1105_info sja1105t_info;
 336 extern const struct sja1105_info sja1105p_info;
 337 extern const struct sja1105_info sja1105q_info;
 338 extern const struct sja1105_info sja1105r_info;
 339 extern const struct sja1105_info sja1105s_info;
 340 extern const struct sja1105_info sja1110a_info;
 341 extern const struct sja1105_info sja1110b_info;
 342 extern const struct sja1105_info sja1110c_info;
 343 extern const struct sja1105_info sja1110d_info;
 344
 345 /* From sja1105_clocking.c */
 346
 347 typedef enum {
 348         XMII_MAC = 0,
 349         XMII_PHY = 1,
 350 } sja1105_mii_role_t;
 351
 352 typedef enum {
 353         XMII_MODE_MII           = 0,
 354         XMII_MODE_RMII          = 1,
 355         XMII_MODE_RGMII         = 2,
 356         XMII_MODE_SGMII         = 3,
 357 } sja1105_phy_interface_t;
 358
 359 int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port);
 360 int sja1110_setup_rgmii_delay(const void *ctx, int port);
 361 int sja1105_clocking_setup_port(struct sja1105_private *priv, int port);
 362 int sja1105_clocking_setup(struct sja1105_private *priv);
 363 int sja1110_clocking_setup(struct sja1105_private *priv);
 364
 365 /* From sja1105_ethtool.c */
 366 void sja1105_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data);
 367 void sja1105_get_strings(struct dsa_switch *ds, int port,
 368                          u32 stringset, u8 *data);
 369 int sja1105_get_sset_count(struct dsa_switch *ds, int port, int sset);
 370
 371 /* From sja1105_dynamic_config.c */
 372 int sja1105_dynamic_config_read(struct sja1105_private *priv,
 373                                 enum sja1105_blk_idx blk_idx,
 374                                 int index, void *entry);
 375 int sja1105_dynamic_config_write(struct sja1105_private *priv,
 376                                  enum sja1105_blk_idx blk_idx,
 377                                  int index, void *entry, bool keep);
 378
 379 enum sja1105_iotag {
 380         SJA1105_C_TAG = 0, /* Inner VLAN header */
 381         SJA1105_S_TAG = 1, /* Outer VLAN header */
 382 };
 383
 384 enum sja1110_vlan_type {
 385         SJA1110_VLAN_INVALID = 0,
 386         SJA1110_VLAN_C_TAG = 1, /* Single inner VLAN tag */
 387         SJA1110_VLAN_S_TAG = 2, /* Single outer VLAN tag */
 388         SJA1110_VLAN_D_TAG = 3, /* Double tagged, use outer tag for lookup */
 389 };
 390
 391 enum sja1110_shaper_type {
 392         SJA1110_LEAKY_BUCKET_SHAPER = 0,
 393         SJA1110_CBS_SHAPER = 1,
 394 };
 395
 396 u8 sja1105et_fdb_hash(struct sja1105_private *priv, const u8 *addr, u16 vid);
 397 int sja1105et_fdb_add(struct dsa_switch *ds, int port,
 398                       const unsigned char *addr, u16 vid);
 399 int sja1105et_fdb_del(struct dsa_switch *ds, int port,
 400                       const unsigned char *addr, u16 vid);
 401 int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port,
 402                         const unsigned char *addr, u16 vid);
 403 int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port,
 404                         const unsigned char *addr, u16 vid);
 405
 406 /* From sja1105_flower.c */
 407 int sja1105_cls_flower_del(struct dsa_switch *ds, int port,
 408                            struct flow_cls_offload *cls, bool ingress);
 409 int sja1105_cls_flower_add(struct dsa_switch *ds, int port,
 410                            struct flow_cls_offload *cls, bool ingress);
 411 int sja1105_cls_flower_stats(struct dsa_switch *ds, int port,
 412                              struct flow_cls_offload *cls, bool ingress);
 413 void sja1105_flower_setup(struct dsa_switch *ds);
 414 void sja1105_flower_teardown(struct dsa_switch *ds);
 415 struct sja1105_rule *sja1105_rule_find(struct sja1105_private *priv,
 416                                        unsigned long cookie);
 417
 418 #endif