1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
9 #define MT7530_NUM_PORTS 7
10 #define MT7530_NUM_PHYS 5
11 #define MT7530_CPU_PORT 6
12 #define MT7530_NUM_FDB_RECORDS 2048
13 #define MT7530_ALL_MEMBERS 0xff
16 #define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN)
24 #define NUM_TRGMII_CTRL 5
26 #define TRGMII_BASE(x) (0x10000 + (x))
28 /* Registers to ethsys access */
29 #define ETHSYS_CLKCFG0 0x2c
30 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
32 #define SYSC_REG_RSTCTRL 0x34
33 #define RESET_MCM BIT(2)
35 /* Registers to mac forward control for unknown frames */
36 #define MT7530_MFC 0x10
37 #define BC_FFP(x) (((x) & 0xff) << 24)
38 #define BC_FFP_MASK BC_FFP(~0)
39 #define UNM_FFP(x) (((x) & 0xff) << 16)
40 #define UNM_FFP_MASK UNM_FFP(~0)
41 #define UNU_FFP(x) (((x) & 0xff) << 8)
42 #define UNU_FFP_MASK UNU_FFP(~0)
44 #define CPU_PORT(x) ((x) << 4)
45 #define CPU_MASK (0xf << 4)
46 #define MIRROR_EN BIT(3)
47 #define MIRROR_PORT(x) ((x) & 0x7)
48 #define MIRROR_MASK 0x7
50 /* Registers for CPU forward control */
51 #define MT7531_CFC 0x4
52 #define MT7531_MIRROR_EN BIT(19)
53 #define MT7531_MIRROR_MASK (MIRROR_MASK << 16)
54 #define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK)
55 #define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16)
56 #define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
58 #define MT753X_MIRROR_REG(id) (((id) == ID_MT7531) ? \
59 MT7531_CFC : MT7530_MFC)
60 #define MT753X_MIRROR_EN(id) (((id) == ID_MT7531) ? \
61 MT7531_MIRROR_EN : MIRROR_EN)
62 #define MT753X_MIRROR_MASK(id) (((id) == ID_MT7531) ? \
63 MT7531_MIRROR_MASK : MIRROR_MASK)
65 /* Registers for BPDU and PAE frame control*/
66 #define MT753X_BPC 0x24
67 #define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0)
69 enum mt753x_bpdu_port_fw {
70 MT753X_BPDU_FOLLOW_MFC,
71 MT753X_BPDU_CPU_EXCLUDE = 4,
72 MT753X_BPDU_CPU_INCLUDE = 5,
73 MT753X_BPDU_CPU_ONLY = 6,
77 /* Registers for address table access */
78 #define MT7530_ATA1 0x74
81 #define MT7530_ATA2 0x78
82 #define ATA2_IVL BIT(15)
84 /* Register for address table write data */
85 #define MT7530_ATWD 0x7c
87 /* Register for address table control */
88 #define MT7530_ATC 0x80
89 #define ATC_HASH (((x) & 0xfff) << 16)
90 #define ATC_BUSY BIT(15)
91 #define ATC_SRCH_END BIT(14)
92 #define ATC_SRCH_HIT BIT(13)
93 #define ATC_INVALID BIT(12)
94 #define ATC_MAT(x) (((x) & 0xf) << 8)
95 #define ATC_MAT_MACTAB ATC_MAT(0)
100 MT7530_FDB_FLUSH = 2,
101 MT7530_FDB_START = 4,
105 /* Registers for table search read address */
106 #define MT7530_TSRA1 0x84
107 #define MAC_BYTE_0 24
108 #define MAC_BYTE_1 16
111 #define MAC_BYTE_MASK 0xff
113 #define MT7530_TSRA2 0x88
114 #define MAC_BYTE_4 24
115 #define MAC_BYTE_5 16
117 #define CVID_MASK 0xfff
119 #define MT7530_ATRD 0x8C
121 #define AGE_TIMER_MASK 0xff
123 #define PORT_MAP_MASK 0xff
125 #define ENT_STATUS_MASK 0x3
127 /* Register for vlan table control */
128 #define MT7530_VTCR 0x90
129 #define VTCR_BUSY BIT(31)
130 #define VTCR_INVALID BIT(16)
131 #define VTCR_FUNC(x) (((x) & 0xf) << 12)
132 #define VTCR_VID ((x) & 0xfff)
134 enum mt7530_vlan_cmd {
135 /* Read/Write the specified VID entry from VAWD register based
138 MT7530_VTCR_RD_VID = 0,
139 MT7530_VTCR_WR_VID = 1,
142 /* Register for setup vlan and acl write data */
143 #define MT7530_VAWD1 0x94
144 #define PORT_STAG BIT(31)
145 /* Independent VLAN Learning */
146 #define IVL_MAC BIT(30)
147 /* Per VLAN Egress Tag Control */
148 #define VTAG_EN BIT(28)
149 /* VLAN Member Control */
150 #define PORT_MEM(x) (((x) & 0xff) << 16)
151 /* VLAN Entry Valid */
152 #define VLAN_VALID BIT(0)
153 #define PORT_MEM_SHFT 16
154 #define PORT_MEM_MASK 0xff
156 #define MT7530_VAWD2 0x98
157 /* Egress Tag Control */
158 #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1))
159 #define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3)
161 enum mt7530_vlan_egress_attr {
162 MT7530_VLAN_EGRESS_UNTAG = 0,
163 MT7530_VLAN_EGRESS_TAG = 2,
164 MT7530_VLAN_EGRESS_STACK = 3,
167 /* Register for address age control */
168 #define MT7530_AAC 0xa0
170 #define AGE_DIS BIT(20)
172 #define AGE_CNT_MASK GENMASK(19, 12)
173 #define AGE_CNT_MAX 0xff
174 #define AGE_CNT(x) (AGE_CNT_MASK & ((x) << 12))
176 #define AGE_UNIT_MASK GENMASK(11, 0)
177 #define AGE_UNIT_MAX 0xfff
178 #define AGE_UNIT(x) (AGE_UNIT_MASK & (x))
180 /* Register for port STP state control */
181 #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100))
182 #define FID_PST(x) ((x) & 0x3)
183 #define FID_PST_MASK FID_PST(0x3)
185 enum mt7530_stp_state {
186 MT7530_STP_DISABLED = 0,
187 MT7530_STP_BLOCKING = 1,
188 MT7530_STP_LISTENING = 1,
189 MT7530_STP_LEARNING = 2,
190 MT7530_STP_FORWARDING = 3
193 /* Register for port control */
194 #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100))
195 #define PORT_TX_MIR BIT(9)
196 #define PORT_RX_MIR BIT(8)
197 #define PORT_VLAN(x) ((x) & 0x3)
199 enum mt7530_port_mode {
200 /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
201 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0),
203 /* Fallback Mode: Forward received frames with ingress ports that do
204 * not belong to the VLAN member. Frames whose VID is not listed on
205 * the VLAN table are forwarded by the PCR_MATRIX members.
207 MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1),
209 /* Security Mode: Discard any frame due to ingress membership
210 * violation or VID missed on the VLAN table.
212 MT7530_PORT_SECURITY_MODE = PORT_VLAN(3),
215 #define PCR_MATRIX(x) (((x) & 0xff) << 16)
216 #define PORT_PRI(x) (((x) & 0x7) << 24)
217 #define EG_TAG(x) (((x) & 0x3) << 28)
218 #define PCR_MATRIX_MASK PCR_MATRIX(0xff)
219 #define PCR_MATRIX_CLR PCR_MATRIX(0)
220 #define PCR_PORT_VLAN_MASK PORT_VLAN(3)
222 /* Register for port security control */
223 #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100))
224 #define SA_DIS BIT(4)
226 /* Register for port vlan control */
227 #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100))
228 #define PORT_SPEC_TAG BIT(5)
229 #define PVC_EG_TAG(x) (((x) & 0x7) << 8)
230 #define PVC_EG_TAG_MASK PVC_EG_TAG(7)
231 #define VLAN_ATTR(x) (((x) & 0x3) << 6)
232 #define VLAN_ATTR_MASK VLAN_ATTR(3)
234 enum mt7530_vlan_port_eg_tag {
235 MT7530_VLAN_EG_DISABLED = 0,
236 MT7530_VLAN_EG_CONSISTENT = 1,
239 enum mt7530_vlan_port_attr {
240 MT7530_VLAN_USER = 0,
241 MT7530_VLAN_TRANSPARENT = 3,
244 #define STAG_VPID (((x) & 0xffff) << 16)
246 /* Register for port port-and-protocol based vlan 1 control */
247 #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100))
248 #define G0_PORT_VID(x) (((x) & 0xfff) << 0)
249 #define G0_PORT_VID_MASK G0_PORT_VID(0xfff)
250 #define G0_PORT_VID_DEF G0_PORT_VID(1)
252 /* Register for port MAC control register */
253 #define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
254 #define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
255 #define PMCR_EXT_PHY BIT(17)
256 #define PMCR_MAC_MODE BIT(16)
257 #define PMCR_FORCE_MODE BIT(15)
258 #define PMCR_TX_EN BIT(14)
259 #define PMCR_RX_EN BIT(13)
260 #define PMCR_BACKOFF_EN BIT(9)
261 #define PMCR_BACKPR_EN BIT(8)
262 #define PMCR_FORCE_EEE1G BIT(7)
263 #define PMCR_FORCE_EEE100 BIT(6)
264 #define PMCR_TX_FC_EN BIT(5)
265 #define PMCR_RX_FC_EN BIT(4)
266 #define PMCR_FORCE_SPEED_1000 BIT(3)
267 #define PMCR_FORCE_SPEED_100 BIT(2)
268 #define PMCR_FORCE_FDX BIT(1)
269 #define PMCR_FORCE_LNK BIT(0)
270 #define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \
271 PMCR_FORCE_SPEED_1000)
272 #define MT7531_FORCE_LNK BIT(31)
273 #define MT7531_FORCE_SPD BIT(30)
274 #define MT7531_FORCE_DPX BIT(29)
275 #define MT7531_FORCE_RX_FC BIT(28)
276 #define MT7531_FORCE_TX_FC BIT(27)
277 #define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \
280 MT7531_FORCE_RX_FC | \
282 #define PMCR_FORCE_MODE_ID(id) (((id) == ID_MT7531) ? \
283 MT7531_FORCE_MODE : \
285 #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
286 PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
287 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
288 PMCR_FORCE_FDX | PMCR_FORCE_LNK | \
289 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100)
290 #define PMCR_CPU_PORT_SETTING(id) (PMCR_FORCE_MODE_ID((id)) | \
291 PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \
292 PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \
293 PMCR_TX_EN | PMCR_RX_EN | \
294 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
295 PMCR_FORCE_SPEED_1000 | \
296 PMCR_FORCE_FDX | PMCR_FORCE_LNK)
298 #define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
299 #define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
300 #define WAKEUP_TIME_100(x) (((x) & 0xFF) << 16)
301 #define LPI_THRESH_MASK GENMASK(15, 4)
302 #define LPI_THRESH_SHT 4
303 #define SET_LPI_THRESH(x) (((x) << LPI_THRESH_SHT) & LPI_THRESH_MASK)
304 #define GET_LPI_THRESH(x) (((x) & LPI_THRESH_MASK) >> LPI_THRESH_SHT)
305 #define LPI_MODE_EN BIT(0)
307 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
308 #define PMSR_EEE1G BIT(7)
309 #define PMSR_EEE100M BIT(6)
310 #define PMSR_RX_FC BIT(5)
311 #define PMSR_TX_FC BIT(4)
312 #define PMSR_SPEED_1000 BIT(3)
313 #define PMSR_SPEED_100 BIT(2)
314 #define PMSR_SPEED_10 0x00
315 #define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000)
316 #define PMSR_DPX BIT(1)
317 #define PMSR_LINK BIT(0)
319 /* Register for port debug count */
320 #define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100)
321 #define MT7531_DIS_CLR BIT(31)
323 #define MT7530_GMACCR 0x30e0
324 #define MAX_RX_JUMBO(x) ((x) << 2)
325 #define MAX_RX_JUMBO_MASK GENMASK(5, 2)
326 #define MAX_RX_PKT_LEN_MASK GENMASK(1, 0)
327 #define MAX_RX_PKT_LEN_1522 0x0
328 #define MAX_RX_PKT_LEN_1536 0x1
329 #define MAX_RX_PKT_LEN_1552 0x2
330 #define MAX_RX_PKT_LEN_JUMBO 0x3
332 /* Register for MIB */
333 #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
334 #define MT7530_MIB_CCR 0x4fe0
335 #define CCR_MIB_ENABLE BIT(31)
336 #define CCR_RX_OCT_CNT_GOOD BIT(7)
337 #define CCR_RX_OCT_CNT_BAD BIT(6)
338 #define CCR_TX_OCT_CNT_GOOD BIT(5)
339 #define CCR_TX_OCT_CNT_BAD BIT(4)
340 #define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \
341 CCR_RX_OCT_CNT_BAD | \
342 CCR_TX_OCT_CNT_GOOD | \
344 #define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \
345 CCR_RX_OCT_CNT_GOOD | \
346 CCR_RX_OCT_CNT_BAD | \
347 CCR_TX_OCT_CNT_GOOD | \
350 /* MT7531 SGMII register group */
351 #define MT7531_SGMII_REG_BASE 0x5000
352 #define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \
353 ((p) - 5) * 0x1000 + (r))
355 /* Register forSGMII PCS_CONTROL_1 */
356 #define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(p, 0x00)
357 #define MT7531_SGMII_LINK_STATUS BIT(18)
358 #define MT7531_SGMII_AN_ENABLE BIT(12)
359 #define MT7531_SGMII_AN_RESTART BIT(9)
361 /* Register for SGMII PCS_SPPED_ABILITY */
362 #define MT7531_PCS_SPEED_ABILITY(p) MT7531_SGMII_REG(p, 0x08)
363 #define MT7531_SGMII_TX_CONFIG_MASK GENMASK(15, 0)
364 #define MT7531_SGMII_TX_CONFIG BIT(0)
366 /* Register for SGMII_MODE */
367 #define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(p, 0x20)
368 #define MT7531_SGMII_REMOTE_FAULT_DIS BIT(8)
369 #define MT7531_SGMII_IF_MODE_MASK GENMASK(5, 1)
370 #define MT7531_SGMII_FORCE_DUPLEX BIT(4)
371 #define MT7531_SGMII_FORCE_SPEED_MASK GENMASK(3, 2)
372 #define MT7531_SGMII_FORCE_SPEED_1000 BIT(3)
373 #define MT7531_SGMII_FORCE_SPEED_100 BIT(2)
374 #define MT7531_SGMII_FORCE_SPEED_10 0
375 #define MT7531_SGMII_SPEED_DUPLEX_AN BIT(1)
377 enum mt7531_sgmii_force_duplex {
378 MT7531_SGMII_FORCE_FULL_DUPLEX = 0,
379 MT7531_SGMII_FORCE_HALF_DUPLEX = 0x10,
382 /* Fields of QPHY_PWR_STATE_CTRL */
383 #define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(p, 0xe8)
384 #define MT7531_SGMII_PHYA_PWD BIT(4)
386 /* Values of SGMII SPEED */
387 #define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(p, 0x128)
388 #define MT7531_RG_TPHY_SPEED_MASK (BIT(2) | BIT(3))
389 #define MT7531_RG_TPHY_SPEED_1_25G 0x0
390 #define MT7531_RG_TPHY_SPEED_3_125G BIT(2)
392 /* Register for system reset */
393 #define MT7530_SYS_CTRL 0x7000
394 #define SYS_CTRL_PHY_RST BIT(2)
395 #define SYS_CTRL_SW_RST BIT(1)
396 #define SYS_CTRL_REG_RST BIT(0)
398 /* Register for system interrupt */
399 #define MT7530_SYS_INT_EN 0x7008
401 /* Register for system interrupt status */
402 #define MT7530_SYS_INT_STS 0x700c
404 /* Register for PHY Indirect Access Control */
405 #define MT7531_PHY_IAC 0x701C
406 #define MT7531_PHY_ACS_ST BIT(31)
407 #define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25)
408 #define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20)
409 #define MT7531_MDIO_CMD_MASK (0x3 << 18)
410 #define MT7531_MDIO_ST_MASK (0x3 << 16)
411 #define MT7531_MDIO_RW_DATA_MASK (0xffff)
412 #define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25)
413 #define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25)
414 #define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20)
415 #define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18)
416 #define MT7531_MDIO_ST(x) (((x) & 0x3) << 16)
418 enum mt7531_phy_iac_cmd {
419 MT7531_MDIO_ADDR = 0,
420 MT7531_MDIO_WRITE = 1,
421 MT7531_MDIO_READ = 2,
422 MT7531_MDIO_READ_CL45 = 3,
425 /* MDIO_ST: MDIO start field */
426 enum mt7531_mdio_st {
427 MT7531_MDIO_ST_CL45 = 0,
428 MT7531_MDIO_ST_CL22 = 1,
431 #define MT7531_MDIO_CL22_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
432 MT7531_MDIO_CMD(MT7531_MDIO_READ))
433 #define MT7531_MDIO_CL22_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
434 MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
435 #define MT7531_MDIO_CL45_ADDR (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
436 MT7531_MDIO_CMD(MT7531_MDIO_ADDR))
437 #define MT7531_MDIO_CL45_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
438 MT7531_MDIO_CMD(MT7531_MDIO_READ))
439 #define MT7531_MDIO_CL45_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
440 MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
442 /* Register for RGMII clock phase */
443 #define MT7531_CLKGEN_CTRL 0x7500
444 #define CLK_SKEW_OUT(x) (((x) & 0x3) << 8)
445 #define CLK_SKEW_OUT_MASK GENMASK(9, 8)
446 #define CLK_SKEW_IN(x) (((x) & 0x3) << 6)
447 #define CLK_SKEW_IN_MASK GENMASK(7, 6)
448 #define RXCLK_NO_DELAY BIT(5)
449 #define TXCLK_NO_REVERSE BIT(4)
450 #define GP_MODE(x) (((x) & 0x3) << 1)
451 #define GP_MODE_MASK GENMASK(2, 1)
452 #define GP_CLK_EN BIT(0)
454 enum mt7531_gp_mode {
455 MT7531_GP_MODE_RGMII = 0,
456 MT7531_GP_MODE_MII = 1,
457 MT7531_GP_MODE_REV_MII = 2
460 enum mt7531_clk_skew {
461 MT7531_CLK_SKEW_NO_CHG = 0,
462 MT7531_CLK_SKEW_DLY_100PPS = 1,
463 MT7531_CLK_SKEW_DLY_200PPS = 2,
464 MT7531_CLK_SKEW_REVERSE = 3,
467 /* Register for hw trap status */
468 #define MT7530_HWTRAP 0x7800
469 #define HWTRAP_XTAL_MASK (BIT(10) | BIT(9))
470 #define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9))
471 #define HWTRAP_XTAL_40MHZ (BIT(10))
472 #define HWTRAP_XTAL_20MHZ (BIT(9))
474 #define MT7531_HWTRAP 0x7800
475 #define HWTRAP_XTAL_FSEL_MASK BIT(7)
476 #define HWTRAP_XTAL_FSEL_25MHZ BIT(7)
477 #define HWTRAP_XTAL_FSEL_40MHZ 0
478 /* Unique fields of (M)HWSTRAP for MT7531 */
479 #define XTAL_FSEL_S 7
480 #define XTAL_FSEL_M BIT(7)
481 #define PHY_EN BIT(6)
482 #define CHG_STRAP BIT(8)
484 /* Register for hw trap modification */
485 #define MT7530_MHWTRAP 0x7804
486 #define MHWTRAP_PHY0_SEL BIT(20)
487 #define MHWTRAP_MANUAL BIT(16)
488 #define MHWTRAP_P5_MAC_SEL BIT(13)
489 #define MHWTRAP_P6_DIS BIT(8)
490 #define MHWTRAP_P5_RGMII_MODE BIT(7)
491 #define MHWTRAP_P5_DIS BIT(6)
492 #define MHWTRAP_PHY_ACCESS BIT(5)
494 /* Register for TOP signal control */
495 #define MT7530_TOP_SIG_CTRL 0x7808
496 #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16))
498 #define MT7531_TOP_SIG_SR 0x780c
499 #define PAD_DUAL_SGMII_EN BIT(1)
500 #define PAD_MCM_SMI_EN BIT(0)
502 #define MT7530_IO_DRV_CR 0x7810
503 #define P5_IO_CLK_DRV(x) ((x) & 0x3)
504 #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4)
506 #define MT7531_CHIP_REV 0x781C
508 #define MT7531_PLLGP_EN 0x7820
509 #define EN_COREPLL BIT(2)
510 #define SW_CLKSW BIT(1)
511 #define SW_PLLGP BIT(0)
513 #define MT7530_P6ECR 0x7830
514 #define P6_INTF_MODE_MASK 0x3
515 #define P6_INTF_MODE(x) ((x) & 0x3)
517 #define MT7531_PLLGP_CR0 0x78a8
518 #define RG_COREPLL_EN BIT(22)
519 #define RG_COREPLL_POSDIV_S 23
520 #define RG_COREPLL_POSDIV_M 0x3800000
521 #define RG_COREPLL_SDM_PCW_S 1
522 #define RG_COREPLL_SDM_PCW_M 0x3ffffe
523 #define RG_COREPLL_SDM_PCW_CHG BIT(0)
525 /* Registers for RGMII and SGMII PLL clock */
526 #define MT7531_ANA_PLLGP_CR2 0x78b0
527 #define MT7531_ANA_PLLGP_CR5 0x78bc
529 /* Registers for TRGMII on the both side */
530 #define MT7530_TRGMII_RCK_CTRL 0x7a00
531 #define RX_RST BIT(31)
532 #define RXC_DQSISEL BIT(30)
533 #define DQSI1_TAP_MASK (0x7f << 8)
534 #define DQSI0_TAP_MASK 0x7f
535 #define DQSI1_TAP(x) (((x) & 0x7f) << 8)
536 #define DQSI0_TAP(x) ((x) & 0x7f)
538 #define MT7530_TRGMII_RCK_RTT 0x7a04
539 #define DQS1_GATE BIT(31)
540 #define DQS0_GATE BIT(30)
542 #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8)
543 #define BSLIP_EN BIT(31)
544 #define EDGE_CHK BIT(30)
545 #define RD_TAP_MASK 0x7f
546 #define RD_TAP(x) ((x) & 0x7f)
548 #define MT7530_TRGMII_TXCTRL 0x7a40
549 #define TRAIN_TXEN BIT(31)
550 #define TXC_INV BIT(30)
551 #define TX_RST BIT(28)
553 #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i))
554 #define TD_DM_DRVP(x) ((x) & 0xf)
555 #define TD_DM_DRVN(x) (((x) & 0xf) << 4)
557 #define MT7530_TRGMII_TCK_CTRL 0x7a78
558 #define TCK_TAP(x) (((x) & 0xf) << 8)
560 #define MT7530_P5RGMIIRXCR 0x7b00
561 #define CSR_RGMII_EDGE_ALIGN BIT(8)
562 #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf)
564 #define MT7530_P5RGMIITXCR 0x7b04
565 #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f)
567 /* Registers for GPIO mode */
568 #define MT7531_GPIO_MODE0 0x7c0c
569 #define MT7531_GPIO0_MASK GENMASK(3, 0)
570 #define MT7531_GPIO0_INTERRUPT 1
572 #define MT7531_GPIO_MODE1 0x7c10
573 #define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12)
574 #define MT7531_EXT_P_MDC_11 (2 << 12)
575 #define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16)
576 #define MT7531_EXT_P_MDIO_12 (2 << 16)
578 /* Registers for LED GPIO control (MT7530 only)
579 * All registers follow this pattern:
587 /* LED enable, 0: Disable, 1: Enable (Default) */
588 #define MT7530_LED_EN 0x7d00
589 /* LED mode, 0: GPIO mode, 1: PHY mode (Default) */
590 #define MT7530_LED_IO_MODE 0x7d04
591 /* GPIO direction, 0: Input, 1: Output */
592 #define MT7530_LED_GPIO_DIR 0x7d10
593 /* GPIO output enable, 0: Disable, 1: Enable */
594 #define MT7530_LED_GPIO_OE 0x7d14
595 /* GPIO value, 0: Low, 1: High */
596 #define MT7530_LED_GPIO_DATA 0x7d18
598 #define MT7530_CREV 0x7ffc
599 #define CHIP_NAME_SHIFT 16
600 #define MT7530_ID 0x7530
602 #define MT7531_CREV 0x781C
603 #define CHIP_REV_M 0x0f
604 #define MT7531_ID 0x7531
606 /* Registers for core PLL access through mmd indirect */
607 #define CORE_PLL_GROUP2 0x401
608 #define RG_SYSPLL_EN_NORMAL BIT(15)
609 #define RG_SYSPLL_VODEN BIT(14)
610 #define RG_SYSPLL_LF BIT(13)
611 #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12)
612 #define RG_SYSPLL_LVROD_EN BIT(10)
613 #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8)
614 #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5)
615 #define RG_SYSPLL_FBKSEL BIT(4)
616 #define RT_SYSPLL_EN_AFE_OLT BIT(0)
618 #define CORE_PLL_GROUP4 0x403
619 #define RG_SYSPLL_DDSFBK_EN BIT(12)
620 #define RG_SYSPLL_BIAS_EN BIT(11)
621 #define RG_SYSPLL_BIAS_LPF_EN BIT(10)
622 #define MT7531_PHY_PLL_OFF BIT(5)
623 #define MT7531_PHY_PLL_BYPASS_MODE BIT(4)
625 #define MT753X_CTRL_PHY_ADDR 0
627 #define CORE_PLL_GROUP5 0x404
628 #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
630 #define CORE_PLL_GROUP6 0x405
631 #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff)
633 #define CORE_PLL_GROUP7 0x406
634 #define RG_LCDDS_PWDB BIT(15)
635 #define RG_LCDDS_ISO_EN BIT(13)
636 #define RG_LCCDS_C(x) (((x) & 0x7) << 4)
637 #define RG_LCDDS_PCW_NCPO_CHG BIT(3)
639 #define CORE_PLL_GROUP10 0x409
640 #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff)
642 #define CORE_PLL_GROUP11 0x40a
643 #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff)
645 #define CORE_GSWPLL_GRP1 0x40d
646 #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14)
647 #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12)
648 #define RG_GSWPLL_EN_PRE BIT(11)
649 #define RG_GSWPLL_FBKSEL BIT(10)
650 #define RG_GSWPLL_BP BIT(9)
651 #define RG_GSWPLL_BR BIT(8)
652 #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff)
654 #define CORE_GSWPLL_GRP2 0x40e
655 #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8)
656 #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff)
658 #define CORE_TRGMII_GSW_CLK_CG 0x410
659 #define REG_GSWCK_EN BIT(0)
660 #define REG_TRGMIICK_EN BIT(1)
662 #define MIB_DESC(_s, _o, _n) \
669 struct mt7530_mib_desc {
683 /* struct mt7530_port - This is the main data structure for holding the state
685 * @enable: The status used for show port is enabled or not.
686 * @pm: The matrix used to show all connections with the port.
687 * @pvid: The VLAN specified is to be considered a PVID at ingress. Any
688 * untagged frames will be assigned to the related VLAN.
689 * @vlan_filtering: The flags indicating whether the port that can recognize
690 * VLAN-tagged frames.
698 /* Port 5 interface select definitions */
699 enum p5_interface_select {
704 P5_INTF_SEL_GMAC5_SGMII,
707 static const char *p5_intf_modes(unsigned int p5_interface)
709 switch (p5_interface) {
712 case P5_INTF_SEL_PHY_P0:
714 case P5_INTF_SEL_PHY_P4:
716 case P5_INTF_SEL_GMAC5:
718 case P5_INTF_SEL_GMAC5_SGMII:
719 return "GMAC5_SGMII";
727 /* struct mt753x_info - This is the main data structure for holding the specific
728 * part for each supported device
729 * @sw_setup: Holding the handler to a device initialization
730 * @phy_read: Holding the way reading PHY port
731 * @phy_write: Holding the way writing PHY port
732 * @pad_setup: Holding the way setting up the bus pad for a certain
734 * @phy_mode_supported: Check if the PHY type is being supported on a certain
736 * @mac_port_validate: Holding the way to set addition validate type for a
738 * @mac_port_get_state: Holding the way getting the MAC/PCS state for a certain
740 * @mac_port_config: Holding the way setting up the PHY attribute to a
742 * @mac_pcs_an_restart Holding the way restarting PCS autonegotiation for a
744 * @mac_pcs_link_up: Holding the way setting up the PHY attribute to the pcs
745 * of the certain MAC port
750 int (*sw_setup)(struct dsa_switch *ds);
751 int (*phy_read)(struct mt7530_priv *priv, int port, int regnum);
752 int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val);
753 int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface);
754 int (*cpu_port_config)(struct dsa_switch *ds, int port);
755 bool (*phy_mode_supported)(struct dsa_switch *ds, int port,
756 const struct phylink_link_state *state);
757 void (*mac_port_validate)(struct dsa_switch *ds, int port,
758 unsigned long *supported);
759 int (*mac_port_get_state)(struct dsa_switch *ds, int port,
760 struct phylink_link_state *state);
761 int (*mac_port_config)(struct dsa_switch *ds, int port,
763 phy_interface_t interface);
764 void (*mac_pcs_an_restart)(struct dsa_switch *ds, int port);
765 void (*mac_pcs_link_up)(struct dsa_switch *ds, int port,
766 unsigned int mode, phy_interface_t interface,
767 int speed, int duplex);
770 /* struct mt7530_priv - This is the main data structure for holding the state
772 * @dev: The device pointer
773 * @ds: The pointer to the dsa core structure
774 * @bus: The bus used for the device and built-in PHY
775 * @rstc: The pointer to reset control used by MCM
776 * @core_pwr: The power supplied into the core
777 * @io_pwr: The power supplied into the I/O
778 * @reset: The descriptor for GPIO line tied to its reset pin
779 * @mcm: Flag for distinguishing if standalone IC or module
781 * @ports: Holding the state among ports
782 * @reg_mutex: The lock for protecting among process accessing
784 * @p6_interface Holding the current port 6 interface
785 * @p5_intf_sel: Holding the current port 5 interface select
787 * @irq: IRQ number of the switch
788 * @irq_domain: IRQ domain of the switch irq_chip
789 * @irq_enable: IRQ enable bits, synced to SYS_INT_EN
793 struct dsa_switch *ds;
795 struct reset_control *rstc;
796 struct regulator *core_pwr;
797 struct regulator *io_pwr;
798 struct gpio_desc *reset;
799 const struct mt753x_info *info;
802 phy_interface_t p6_interface;
803 phy_interface_t p5_interface;
804 unsigned int p5_intf_sel;
808 struct mt7530_port ports[MT7530_NUM_PORTS];
809 /* protect among processes for registers access*/
810 struct mutex reg_mutex;
812 struct irq_domain *irq_domain;
816 struct mt7530_hw_vlan_entry {
822 static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e,
823 int port, bool untagged)
826 e->untagged = untagged;
829 typedef void (*mt7530_vlan_op)(struct mt7530_priv *,
830 struct mt7530_hw_vlan_entry *);
832 struct mt7530_hw_stats {
838 struct mt7530_dummy_poll {
839 struct mt7530_priv *priv;
843 static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p,
844 struct mt7530_priv *priv, u32 reg)
850 #endif /* __MT7530_H */