drivers/net/dsa/b53/b53_common.c

   1 /*
   2  * B53 switch driver main logic
   3  *
   4  * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
   5  * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
   6  *
   7  * Permission to use, copy, modify, and/or distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  */
  19
  20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21
  22 #include <linux/delay.h>
  23 #include <linux/export.h>
  24 #include <linux/gpio.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_data/b53.h>
  28 #include <linux/phy.h>
  29 #include <linux/phylink.h>
  30 #include <linux/etherdevice.h>
  31 #include <linux/if_bridge.h>
  32 #include <net/dsa.h>
  33
  34 #include "b53_regs.h"
  35 #include "b53_priv.h"
  36
  37 struct b53_mib_desc {
  38         u8 size;
  39         u8 offset;
  40         const char *name;
  41 };
  42
  43 /* BCM5365 MIB counters */
  44 static const struct b53_mib_desc b53_mibs_65[] = {
  45         { 8, 0x00, "TxOctets" },
  46         { 4, 0x08, "TxDropPkts" },
  47         { 4, 0x10, "TxBroadcastPkts" },
  48         { 4, 0x14, "TxMulticastPkts" },
  49         { 4, 0x18, "TxUnicastPkts" },
  50         { 4, 0x1c, "TxCollisions" },
  51         { 4, 0x20, "TxSingleCollision" },
  52         { 4, 0x24, "TxMultipleCollision" },
  53         { 4, 0x28, "TxDeferredTransmit" },
  54         { 4, 0x2c, "TxLateCollision" },
  55         { 4, 0x30, "TxExcessiveCollision" },
  56         { 4, 0x38, "TxPausePkts" },
  57         { 8, 0x44, "RxOctets" },
  58         { 4, 0x4c, "RxUndersizePkts" },
  59         { 4, 0x50, "RxPausePkts" },
  60         { 4, 0x54, "Pkts64Octets" },
  61         { 4, 0x58, "Pkts65to127Octets" },
  62         { 4, 0x5c, "Pkts128to255Octets" },
  63         { 4, 0x60, "Pkts256to511Octets" },
  64         { 4, 0x64, "Pkts512to1023Octets" },
  65         { 4, 0x68, "Pkts1024to1522Octets" },
  66         { 4, 0x6c, "RxOversizePkts" },
  67         { 4, 0x70, "RxJabbers" },
  68         { 4, 0x74, "RxAlignmentErrors" },
  69         { 4, 0x78, "RxFCSErrors" },
  70         { 8, 0x7c, "RxGoodOctets" },
  71         { 4, 0x84, "RxDropPkts" },
  72         { 4, 0x88, "RxUnicastPkts" },
  73         { 4, 0x8c, "RxMulticastPkts" },
  74         { 4, 0x90, "RxBroadcastPkts" },
  75         { 4, 0x94, "RxSAChanges" },
  76         { 4, 0x98, "RxFragments" },
  77 };
  78
  79 #define B53_MIBS_65_SIZE        ARRAY_SIZE(b53_mibs_65)
  80
  81 /* BCM63xx MIB counters */
  82 static const struct b53_mib_desc b53_mibs_63xx[] = {
  83         { 8, 0x00, "TxOctets" },
  84         { 4, 0x08, "TxDropPkts" },
  85         { 4, 0x0c, "TxQoSPkts" },
  86         { 4, 0x10, "TxBroadcastPkts" },
  87         { 4, 0x14, "TxMulticastPkts" },
  88         { 4, 0x18, "TxUnicastPkts" },
  89         { 4, 0x1c, "TxCollisions" },
  90         { 4, 0x20, "TxSingleCollision" },
  91         { 4, 0x24, "TxMultipleCollision" },
  92         { 4, 0x28, "TxDeferredTransmit" },
  93         { 4, 0x2c, "TxLateCollision" },
  94         { 4, 0x30, "TxExcessiveCollision" },
  95         { 4, 0x38, "TxPausePkts" },
  96         { 8, 0x3c, "TxQoSOctets" },
  97         { 8, 0x44, "RxOctets" },
  98         { 4, 0x4c, "RxUndersizePkts" },
  99         { 4, 0x50, "RxPausePkts" },
 100         { 4, 0x54, "Pkts64Octets" },
 101         { 4, 0x58, "Pkts65to127Octets" },
 102         { 4, 0x5c, "Pkts128to255Octets" },
 103         { 4, 0x60, "Pkts256to511Octets" },
 104         { 4, 0x64, "Pkts512to1023Octets" },
 105         { 4, 0x68, "Pkts1024to1522Octets" },
 106         { 4, 0x6c, "RxOversizePkts" },
 107         { 4, 0x70, "RxJabbers" },
 108         { 4, 0x74, "RxAlignmentErrors" },
 109         { 4, 0x78, "RxFCSErrors" },
 110         { 8, 0x7c, "RxGoodOctets" },
 111         { 4, 0x84, "RxDropPkts" },
 112         { 4, 0x88, "RxUnicastPkts" },
 113         { 4, 0x8c, "RxMulticastPkts" },
 114         { 4, 0x90, "RxBroadcastPkts" },
 115         { 4, 0x94, "RxSAChanges" },
 116         { 4, 0x98, "RxFragments" },
 117         { 4, 0xa0, "RxSymbolErrors" },
 118         { 4, 0xa4, "RxQoSPkts" },
 119         { 8, 0xa8, "RxQoSOctets" },
 120         { 4, 0xb0, "Pkts1523to2047Octets" },
 121         { 4, 0xb4, "Pkts2048to4095Octets" },
 122         { 4, 0xb8, "Pkts4096to8191Octets" },
 123         { 4, 0xbc, "Pkts8192to9728Octets" },
 124         { 4, 0xc0, "RxDiscarded" },
 125 };
 126
 127 #define B53_MIBS_63XX_SIZE      ARRAY_SIZE(b53_mibs_63xx)
 128
 129 /* MIB counters */
 130 static const struct b53_mib_desc b53_mibs[] = {
 131         { 8, 0x00, "TxOctets" },
 132         { 4, 0x08, "TxDropPkts" },
 133         { 4, 0x10, "TxBroadcastPkts" },
 134         { 4, 0x14, "TxMulticastPkts" },
 135         { 4, 0x18, "TxUnicastPkts" },
 136         { 4, 0x1c, "TxCollisions" },
 137         { 4, 0x20, "TxSingleCollision" },
 138         { 4, 0x24, "TxMultipleCollision" },
 139         { 4, 0x28, "TxDeferredTransmit" },
 140         { 4, 0x2c, "TxLateCollision" },
 141         { 4, 0x30, "TxExcessiveCollision" },
 142         { 4, 0x38, "TxPausePkts" },
 143         { 8, 0x50, "RxOctets" },
 144         { 4, 0x58, "RxUndersizePkts" },
 145         { 4, 0x5c, "RxPausePkts" },
 146         { 4, 0x60, "Pkts64Octets" },
 147         { 4, 0x64, "Pkts65to127Octets" },
 148         { 4, 0x68, "Pkts128to255Octets" },
 149         { 4, 0x6c, "Pkts256to511Octets" },
 150         { 4, 0x70, "Pkts512to1023Octets" },
 151         { 4, 0x74, "Pkts1024to1522Octets" },
 152         { 4, 0x78, "RxOversizePkts" },
 153         { 4, 0x7c, "RxJabbers" },
 154         { 4, 0x80, "RxAlignmentErrors" },
 155         { 4, 0x84, "RxFCSErrors" },
 156         { 8, 0x88, "RxGoodOctets" },
 157         { 4, 0x90, "RxDropPkts" },
 158         { 4, 0x94, "RxUnicastPkts" },
 159         { 4, 0x98, "RxMulticastPkts" },
 160         { 4, 0x9c, "RxBroadcastPkts" },
 161         { 4, 0xa0, "RxSAChanges" },
 162         { 4, 0xa4, "RxFragments" },
 163         { 4, 0xa8, "RxJumboPkts" },
 164         { 4, 0xac, "RxSymbolErrors" },
 165         { 4, 0xc0, "RxDiscarded" },
 166 };
 167
 168 #define B53_MIBS_SIZE   ARRAY_SIZE(b53_mibs)
 169
 170 static const struct b53_mib_desc b53_mibs_58xx[] = {
 171         { 8, 0x00, "TxOctets" },
 172         { 4, 0x08, "TxDropPkts" },
 173         { 4, 0x0c, "TxQPKTQ0" },
 174         { 4, 0x10, "TxBroadcastPkts" },
 175         { 4, 0x14, "TxMulticastPkts" },
 176         { 4, 0x18, "TxUnicastPKts" },
 177         { 4, 0x1c, "TxCollisions" },
 178         { 4, 0x20, "TxSingleCollision" },
 179         { 4, 0x24, "TxMultipleCollision" },
 180         { 4, 0x28, "TxDeferredCollision" },
 181         { 4, 0x2c, "TxLateCollision" },
 182         { 4, 0x30, "TxExcessiveCollision" },
 183         { 4, 0x34, "TxFrameInDisc" },
 184         { 4, 0x38, "TxPausePkts" },
 185         { 4, 0x3c, "TxQPKTQ1" },
 186         { 4, 0x40, "TxQPKTQ2" },
 187         { 4, 0x44, "TxQPKTQ3" },
 188         { 4, 0x48, "TxQPKTQ4" },
 189         { 4, 0x4c, "TxQPKTQ5" },
 190         { 8, 0x50, "RxOctets" },
 191         { 4, 0x58, "RxUndersizePkts" },
 192         { 4, 0x5c, "RxPausePkts" },
 193         { 4, 0x60, "RxPkts64Octets" },
 194         { 4, 0x64, "RxPkts65to127Octets" },
 195         { 4, 0x68, "RxPkts128to255Octets" },
 196         { 4, 0x6c, "RxPkts256to511Octets" },
 197         { 4, 0x70, "RxPkts512to1023Octets" },
 198         { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
 199         { 4, 0x78, "RxOversizePkts" },
 200         { 4, 0x7c, "RxJabbers" },
 201         { 4, 0x80, "RxAlignmentErrors" },
 202         { 4, 0x84, "RxFCSErrors" },
 203         { 8, 0x88, "RxGoodOctets" },
 204         { 4, 0x90, "RxDropPkts" },
 205         { 4, 0x94, "RxUnicastPkts" },
 206         { 4, 0x98, "RxMulticastPkts" },
 207         { 4, 0x9c, "RxBroadcastPkts" },
 208         { 4, 0xa0, "RxSAChanges" },
 209         { 4, 0xa4, "RxFragments" },
 210         { 4, 0xa8, "RxJumboPkt" },
 211         { 4, 0xac, "RxSymblErr" },
 212         { 4, 0xb0, "InRangeErrCount" },
 213         { 4, 0xb4, "OutRangeErrCount" },
 214         { 4, 0xb8, "EEELpiEvent" },
 215         { 4, 0xbc, "EEELpiDuration" },
 216         { 4, 0xc0, "RxDiscard" },
 217         { 4, 0xc8, "TxQPKTQ6" },
 218         { 4, 0xcc, "TxQPKTQ7" },
 219         { 4, 0xd0, "TxPkts64Octets" },
 220         { 4, 0xd4, "TxPkts65to127Octets" },
 221         { 4, 0xd8, "TxPkts128to255Octets" },
 222         { 4, 0xdc, "TxPkts256to511Ocets" },
 223         { 4, 0xe0, "TxPkts512to1023Ocets" },
 224         { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
 225 };
 226
 227 #define B53_MIBS_58XX_SIZE      ARRAY_SIZE(b53_mibs_58xx)
 228
 229 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
 230 {
 231         unsigned int i;
 232
 233         b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
 234
 235         for (i = 0; i < 10; i++) {
 236                 u8 vta;
 237
 238                 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
 239                 if (!(vta & VTA_START_CMD))
 240                         return 0;
 241
 242                 usleep_range(100, 200);
 243         }
 244
 245         return -EIO;
 246 }
 247
 248 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
 249                                struct b53_vlan *vlan)
 250 {
 251         if (is5325(dev)) {
 252                 u32 entry = 0;
 253
 254                 if (vlan->members) {
 255                         entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
 256                                  VA_UNTAG_S_25) | vlan->members;
 257                         if (dev->core_rev >= 3)
 258                                 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
 259                         else
 260                                 entry |= VA_VALID_25;
 261                 }
 262
 263                 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
 264                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
 265                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 266         } else if (is5365(dev)) {
 267                 u16 entry = 0;
 268
 269                 if (vlan->members)
 270                         entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
 271                                  VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
 272
 273                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
 274                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
 275                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 276         } else {
 277                 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
 278                 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
 279                             (vlan->untag << VTE_UNTAG_S) | vlan->members);
 280
 281                 b53_do_vlan_op(dev, VTA_CMD_WRITE);
 282         }
 283
 284         dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
 285                 vid, vlan->members, vlan->untag);
 286 }
 287
 288 static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
 289                                struct b53_vlan *vlan)
 290 {
 291         if (is5325(dev)) {
 292                 u32 entry = 0;
 293
 294                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
 295                             VTA_RW_STATE_RD | VTA_RW_OP_EN);
 296                 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
 297
 298                 if (dev->core_rev >= 3)
 299                         vlan->valid = !!(entry & VA_VALID_25_R4);
 300                 else
 301                         vlan->valid = !!(entry & VA_VALID_25);
 302                 vlan->members = entry & VA_MEMBER_MASK;
 303                 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
 304
 305         } else if (is5365(dev)) {
 306                 u16 entry = 0;
 307
 308                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
 309                             VTA_RW_STATE_WR | VTA_RW_OP_EN);
 310                 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
 311
 312                 vlan->valid = !!(entry & VA_VALID_65);
 313                 vlan->members = entry & VA_MEMBER_MASK;
 314                 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
 315         } else {
 316                 u32 entry = 0;
 317
 318                 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
 319                 b53_do_vlan_op(dev, VTA_CMD_READ);
 320                 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
 321                 vlan->members = entry & VTE_MEMBERS;
 322                 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
 323                 vlan->valid = true;
 324         }
 325 }
 326
 327 static void b53_set_forwarding(struct b53_device *dev, int enable)
 328 {
 329         u8 mgmt;
 330
 331         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 332
 333         if (enable)
 334                 mgmt |= SM_SW_FWD_EN;
 335         else
 336                 mgmt &= ~SM_SW_FWD_EN;
 337
 338         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 339
 340         /* Include IMP port in dumb forwarding mode
 341          */
 342         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
 343         mgmt |= B53_MII_DUMB_FWDG_EN;
 344         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
 345 }
 346
 347 static void b53_enable_vlan(struct b53_device *dev, bool enable,
 348                             bool enable_filtering)
 349 {
 350         u8 mgmt, vc0, vc1, vc4 = 0, vc5;
 351
 352         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 353         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
 354         b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
 355
 356         if (is5325(dev) || is5365(dev)) {
 357                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
 358                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
 359         } else if (is63xx(dev)) {
 360                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
 361                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
 362         } else {
 363                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
 364                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
 365         }
 366
 367         mgmt &= ~SM_SW_FWD_MODE;
 368
 369         if (enable) {
 370                 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
 371                 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
 372                 vc4 &= ~VC4_ING_VID_CHECK_MASK;
 373                 if (enable_filtering) {
 374                         vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
 375                         vc5 |= VC5_DROP_VTABLE_MISS;
 376                 } else {
 377                         vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
 378                         vc5 &= ~VC5_DROP_VTABLE_MISS;
 379                 }
 380
 381                 if (is5325(dev))
 382                         vc0 &= ~VC0_RESERVED_1;
 383
 384                 if (is5325(dev) || is5365(dev))
 385                         vc1 |= VC1_RX_MCST_TAG_EN;
 386
 387         } else {
 388                 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
 389                 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
 390                 vc4 &= ~VC4_ING_VID_CHECK_MASK;
 391                 vc5 &= ~VC5_DROP_VTABLE_MISS;
 392
 393                 if (is5325(dev) || is5365(dev))
 394                         vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
 395                 else
 396                         vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
 397
 398                 if (is5325(dev) || is5365(dev))
 399                         vc1 &= ~VC1_RX_MCST_TAG_EN;
 400         }
 401
 402         if (!is5325(dev) && !is5365(dev))
 403                 vc5 &= ~VC5_VID_FFF_EN;
 404
 405         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
 406         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
 407
 408         if (is5325(dev) || is5365(dev)) {
 409                 /* enable the high 8 bit vid check on 5325 */
 410                 if (is5325(dev) && enable)
 411                         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
 412                                    VC3_HIGH_8BIT_EN);
 413                 else
 414                         b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
 415
 416                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
 417                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
 418         } else if (is63xx(dev)) {
 419                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
 420                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
 421                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
 422         } else {
 423                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
 424                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
 425                 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
 426         }
 427
 428         b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 429
 430         dev->vlan_enabled = enable;
 431         dev->vlan_filtering_enabled = enable_filtering;
 432 }
 433
 434 static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
 435 {
 436         u32 port_mask = 0;
 437         u16 max_size = JMS_MIN_SIZE;
 438
 439         if (is5325(dev) || is5365(dev))
 440                 return -EINVAL;
 441
 442         if (enable) {
 443                 port_mask = dev->enabled_ports;
 444                 max_size = JMS_MAX_SIZE;
 445                 if (allow_10_100)
 446                         port_mask |= JPM_10_100_JUMBO_EN;
 447         }
 448
 449         b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
 450         return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
 451 }
 452
 453 static int b53_flush_arl(struct b53_device *dev, u8 mask)
 454 {
 455         unsigned int i;
 456
 457         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
 458                    FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
 459
 460         for (i = 0; i < 10; i++) {
 461                 u8 fast_age_ctrl;
 462
 463                 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
 464                           &fast_age_ctrl);
 465
 466                 if (!(fast_age_ctrl & FAST_AGE_DONE))
 467                         goto out;
 468
 469                 msleep(1);
 470         }
 471
 472         return -ETIMEDOUT;
 473 out:
 474         /* Only age dynamic entries (default behavior) */
 475         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
 476         return 0;
 477 }
 478
 479 static int b53_fast_age_port(struct b53_device *dev, int port)
 480 {
 481         b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
 482
 483         return b53_flush_arl(dev, FAST_AGE_PORT);
 484 }
 485
 486 static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
 487 {
 488         b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
 489
 490         return b53_flush_arl(dev, FAST_AGE_VLAN);
 491 }
 492
 493 void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
 494 {
 495         struct b53_device *dev = ds->priv;
 496         unsigned int i;
 497         u16 pvlan;
 498
 499         /* Enable the IMP port to be in the same VLAN as the other ports
 500          * on a per-port basis such that we only have Port i and IMP in
 501          * the same VLAN.
 502          */
 503         b53_for_each_port(dev, i) {
 504                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
 505                 pvlan |= BIT(cpu_port);
 506                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
 507         }
 508 }
 509 EXPORT_SYMBOL(b53_imp_vlan_setup);
 510
 511 int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
 512 {
 513         struct b53_device *dev = ds->priv;
 514         unsigned int cpu_port = ds->ports[port].cpu_dp->index;
 515         int ret = 0;
 516         u16 pvlan;
 517
 518         if (dev->ops->irq_enable)
 519                 ret = dev->ops->irq_enable(dev, port);
 520         if (ret)
 521                 return ret;
 522
 523         /* Clear the Rx and Tx disable bits and set to no spanning tree */
 524         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
 525
 526         /* Set this port, and only this one to be in the default VLAN,
 527          * if member of a bridge, restore its membership prior to
 528          * bringing down this port.
 529          */
 530         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
 531         pvlan &= ~0x1ff;
 532         pvlan |= BIT(port);
 533         pvlan |= dev->ports[port].vlan_ctl_mask;
 534         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
 535
 536         b53_imp_vlan_setup(ds, cpu_port);
 537
 538         /* If EEE was enabled, restore it */
 539         if (dev->ports[port].eee.eee_enabled)
 540                 b53_eee_enable_set(ds, port, true);
 541
 542         return 0;
 543 }
 544 EXPORT_SYMBOL(b53_enable_port);
 545
 546 void b53_disable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
 547 {
 548         struct b53_device *dev = ds->priv;
 549         u8 reg;
 550
 551         /* Disable Tx/Rx for the port */
 552         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
 553         reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
 554         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
 555
 556         if (dev->ops->irq_disable)
 557                 dev->ops->irq_disable(dev, port);
 558 }
 559 EXPORT_SYMBOL(b53_disable_port);
 560
 561 void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
 562 {
 563         bool tag_en = !(ds->ops->get_tag_protocol(ds, port) ==
 564                          DSA_TAG_PROTO_NONE);
 565         struct b53_device *dev = ds->priv;
 566         u8 hdr_ctl, val;
 567         u16 reg;
 568
 569         /* Resolve which bit controls the Broadcom tag */
 570         switch (port) {
 571         case 8:
 572                 val = BRCM_HDR_P8_EN;
 573                 break;
 574         case 7:
 575                 val = BRCM_HDR_P7_EN;
 576                 break;
 577         case 5:
 578                 val = BRCM_HDR_P5_EN;
 579                 break;
 580         default:
 581                 val = 0;
 582                 break;
 583         }
 584
 585         /* Enable Broadcom tags for IMP port */
 586         b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
 587         if (tag_en)
 588                 hdr_ctl |= val;
 589         else
 590                 hdr_ctl &= ~val;
 591         b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
 592
 593         /* Registers below are only accessible on newer devices */
 594         if (!is58xx(dev))
 595                 return;
 596
 597         /* Enable reception Broadcom tag for CPU TX (switch RX) to
 598          * allow us to tag outgoing frames
 599          */
 600         b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, &reg);
 601         if (tag_en)
 602                 reg &= ~BIT(port);
 603         else
 604                 reg |= BIT(port);
 605         b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
 606
 607         /* Enable transmission of Broadcom tags from the switch (CPU RX) to
 608          * allow delivering frames to the per-port net_devices
 609          */
 610         b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, &reg);
 611         if (tag_en)
 612                 reg &= ~BIT(port);
 613         else
 614                 reg |= BIT(port);
 615         b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
 616 }
 617 EXPORT_SYMBOL(b53_brcm_hdr_setup);
 618
 619 static void b53_enable_cpu_port(struct b53_device *dev, int port)
 620 {
 621         u8 port_ctrl;
 622
 623         /* BCM5325 CPU port is at 8 */
 624         if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
 625                 port = B53_CPU_PORT;
 626
 627         port_ctrl = PORT_CTRL_RX_BCST_EN |
 628                     PORT_CTRL_RX_MCST_EN |
 629                     PORT_CTRL_RX_UCST_EN;
 630         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
 631
 632         b53_brcm_hdr_setup(dev->ds, port);
 633 }
 634
 635 static void b53_enable_mib(struct b53_device *dev)
 636 {
 637         u8 gc;
 638
 639         b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
 640         gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
 641         b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
 642 }
 643
 644 static u16 b53_default_pvid(struct b53_device *dev)
 645 {
 646         if (is5325(dev) || is5365(dev))
 647                 return 1;
 648         else
 649                 return 0;
 650 }
 651
 652 int b53_configure_vlan(struct dsa_switch *ds)
 653 {
 654         struct b53_device *dev = ds->priv;
 655         struct b53_vlan vl = { 0 };
 656         int i, def_vid;
 657
 658         def_vid = b53_default_pvid(dev);
 659
 660         /* clear all vlan entries */
 661         if (is5325(dev) || is5365(dev)) {
 662                 for (i = def_vid; i < dev->num_vlans; i++)
 663                         b53_set_vlan_entry(dev, i, &vl);
 664         } else {
 665                 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
 666         }
 667
 668         b53_enable_vlan(dev, false, dev->vlan_filtering_enabled);
 669
 670         b53_for_each_port(dev, i)
 671                 b53_write16(dev, B53_VLAN_PAGE,
 672                             B53_VLAN_PORT_DEF_TAG(i), def_vid);
 673
 674         if (!is5325(dev) && !is5365(dev))
 675                 b53_set_jumbo(dev, dev->enable_jumbo, false);
 676
 677         return 0;
 678 }
 679 EXPORT_SYMBOL(b53_configure_vlan);
 680
 681 static void b53_switch_reset_gpio(struct b53_device *dev)
 682 {
 683         int gpio = dev->reset_gpio;
 684
 685         if (gpio < 0)
 686                 return;
 687
 688         /* Reset sequence: RESET low(50ms)->high(20ms)
 689          */
 690         gpio_set_value(gpio, 0);
 691         mdelay(50);
 692
 693         gpio_set_value(gpio, 1);
 694         mdelay(20);
 695
 696         dev->current_page = 0xff;
 697 }
 698
 699 static int b53_switch_reset(struct b53_device *dev)
 700 {
 701         unsigned int timeout = 1000;
 702         u8 mgmt, reg;
 703
 704         b53_switch_reset_gpio(dev);
 705
 706         if (is539x(dev)) {
 707                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
 708                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
 709         }
 710
 711         /* This is specific to 58xx devices here, do not use is58xx() which
 712          * covers the larger Starfigther 2 family, including 7445/7278 which
 713          * still use this driver as a library and need to perform the reset
 714          * earlier.
 715          */
 716         if (dev->chip_id == BCM58XX_DEVICE_ID ||
 717             dev->chip_id == BCM583XX_DEVICE_ID) {
 718                 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
 719                 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
 720                 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
 721
 722                 do {
 723                         b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
 724                         if (!(reg & SW_RST))
 725                                 break;
 726
 727                         usleep_range(1000, 2000);
 728                 } while (timeout-- > 0);
 729
 730                 if (timeout == 0)
 731                         return -ETIMEDOUT;
 732         }
 733
 734         b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 735
 736         if (!(mgmt & SM_SW_FWD_EN)) {
 737                 mgmt &= ~SM_SW_FWD_MODE;
 738                 mgmt |= SM_SW_FWD_EN;
 739
 740                 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 741                 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 742
 743                 if (!(mgmt & SM_SW_FWD_EN)) {
 744                         dev_err(dev->dev, "Failed to enable switch!\n");
 745                         return -EINVAL;
 746                 }
 747         }
 748
 749         b53_enable_mib(dev);
 750
 751         return b53_flush_arl(dev, FAST_AGE_STATIC);
 752 }
 753
 754 static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
 755 {
 756         struct b53_device *priv = ds->priv;
 757         u16 value = 0;
 758         int ret;
 759
 760         if (priv->ops->phy_read16)
 761                 ret = priv->ops->phy_read16(priv, addr, reg, &value);
 762         else
 763                 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
 764                                  reg * 2, &value);
 765
 766         return ret ? ret : value;
 767 }
 768
 769 static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
 770 {
 771         struct b53_device *priv = ds->priv;
 772
 773         if (priv->ops->phy_write16)
 774                 return priv->ops->phy_write16(priv, addr, reg, val);
 775
 776         return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
 777 }
 778
 779 static int b53_reset_switch(struct b53_device *priv)
 780 {
 781         /* reset vlans */
 782         priv->enable_jumbo = false;
 783
 784         memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
 785         memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
 786
 787         priv->serdes_lane = B53_INVALID_LANE;
 788
 789         return b53_switch_reset(priv);
 790 }
 791
 792 static int b53_apply_config(struct b53_device *priv)
 793 {
 794         /* disable switching */
 795         b53_set_forwarding(priv, 0);
 796
 797         b53_configure_vlan(priv->ds);
 798
 799         /* enable switching */
 800         b53_set_forwarding(priv, 1);
 801
 802         return 0;
 803 }
 804
 805 static void b53_reset_mib(struct b53_device *priv)
 806 {
 807         u8 gc;
 808
 809         b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
 810
 811         b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
 812         msleep(1);
 813         b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
 814         msleep(1);
 815 }
 816
 817 static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
 818 {
 819         if (is5365(dev))
 820                 return b53_mibs_65;
 821         else if (is63xx(dev))
 822                 return b53_mibs_63xx;
 823         else if (is58xx(dev))
 824                 return b53_mibs_58xx;
 825         else
 826                 return b53_mibs;
 827 }
 828
 829 static unsigned int b53_get_mib_size(struct b53_device *dev)
 830 {
 831         if (is5365(dev))
 832                 return B53_MIBS_65_SIZE;
 833         else if (is63xx(dev))
 834                 return B53_MIBS_63XX_SIZE;
 835         else if (is58xx(dev))
 836                 return B53_MIBS_58XX_SIZE;
 837         else
 838                 return B53_MIBS_SIZE;
 839 }
 840
 841 static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port)
 842 {
 843         /* These ports typically do not have built-in PHYs */
 844         switch (port) {
 845         case B53_CPU_PORT_25:
 846         case 7:
 847         case B53_CPU_PORT:
 848                 return NULL;
 849         }
 850
 851         return mdiobus_get_phy(ds->slave_mii_bus, port);
 852 }
 853
 854 void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset,
 855                      uint8_t *data)
 856 {
 857         struct b53_device *dev = ds->priv;
 858         const struct b53_mib_desc *mibs = b53_get_mib(dev);
 859         unsigned int mib_size = b53_get_mib_size(dev);
 860         struct phy_device *phydev;
 861         unsigned int i;
 862
 863         if (stringset == ETH_SS_STATS) {
 864                 for (i = 0; i < mib_size; i++)
 865                         strlcpy(data + i * ETH_GSTRING_LEN,
 866                                 mibs[i].name, ETH_GSTRING_LEN);
 867         } else if (stringset == ETH_SS_PHY_STATS) {
 868                 phydev = b53_get_phy_device(ds, port);
 869                 if (!phydev)
 870                         return;
 871
 872                 phy_ethtool_get_strings(phydev, data);
 873         }
 874 }
 875 EXPORT_SYMBOL(b53_get_strings);
 876
 877 void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
 878 {
 879         struct b53_device *dev = ds->priv;
 880         const struct b53_mib_desc *mibs = b53_get_mib(dev);
 881         unsigned int mib_size = b53_get_mib_size(dev);
 882         const struct b53_mib_desc *s;
 883         unsigned int i;
 884         u64 val = 0;
 885
 886         if (is5365(dev) && port == 5)
 887                 port = 8;
 888
 889         mutex_lock(&dev->stats_mutex);
 890
 891         for (i = 0; i < mib_size; i++) {
 892                 s = &mibs[i];
 893
 894                 if (s->size == 8) {
 895                         b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
 896                 } else {
 897                         u32 val32;
 898
 899                         b53_read32(dev, B53_MIB_PAGE(port), s->offset,
 900                                    &val32);
 901                         val = val32;
 902                 }
 903                 data[i] = (u64)val;
 904         }
 905
 906         mutex_unlock(&dev->stats_mutex);
 907 }
 908 EXPORT_SYMBOL(b53_get_ethtool_stats);
 909
 910 void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data)
 911 {
 912         struct phy_device *phydev;
 913
 914         phydev = b53_get_phy_device(ds, port);
 915         if (!phydev)
 916                 return;
 917
 918         phy_ethtool_get_stats(phydev, NULL, data);
 919 }
 920 EXPORT_SYMBOL(b53_get_ethtool_phy_stats);
 921
 922 int b53_get_sset_count(struct dsa_switch *ds, int port, int sset)
 923 {
 924         struct b53_device *dev = ds->priv;
 925         struct phy_device *phydev;
 926
 927         if (sset == ETH_SS_STATS) {
 928                 return b53_get_mib_size(dev);
 929         } else if (sset == ETH_SS_PHY_STATS) {
 930                 phydev = b53_get_phy_device(ds, port);
 931                 if (!phydev)
 932                         return 0;
 933
 934                 return phy_ethtool_get_sset_count(phydev);
 935         }
 936
 937         return 0;
 938 }
 939 EXPORT_SYMBOL(b53_get_sset_count);
 940
 941 static int b53_setup(struct dsa_switch *ds)
 942 {
 943         struct b53_device *dev = ds->priv;
 944         unsigned int port;
 945         int ret;
 946
 947         ret = b53_reset_switch(dev);
 948         if (ret) {
 949                 dev_err(ds->dev, "failed to reset switch\n");
 950                 return ret;
 951         }
 952
 953         b53_reset_mib(dev);
 954
 955         ret = b53_apply_config(dev);
 956         if (ret)
 957                 dev_err(ds->dev, "failed to apply configuration\n");
 958
 959         /* Configure IMP/CPU port, disable unused ports. Enabled
 960          * ports will be configured with .port_enable
 961          */
 962         for (port = 0; port < dev->num_ports; port++) {
 963                 if (dsa_is_cpu_port(ds, port))
 964                         b53_enable_cpu_port(dev, port);
 965                 else if (dsa_is_unused_port(ds, port))
 966                         b53_disable_port(ds, port, NULL);
 967         }
 968
 969         return ret;
 970 }
 971
 972 static void b53_force_link(struct b53_device *dev, int port, int link)
 973 {
 974         u8 reg, val, off;
 975
 976         /* Override the port settings */
 977         if (port == dev->cpu_port) {
 978                 off = B53_PORT_OVERRIDE_CTRL;
 979                 val = PORT_OVERRIDE_EN;
 980         } else {
 981                 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
 982                 val = GMII_PO_EN;
 983         }
 984
 985         b53_read8(dev, B53_CTRL_PAGE, off, &reg);
 986         reg |= val;
 987         if (link)
 988                 reg |= PORT_OVERRIDE_LINK;
 989         else
 990                 reg &= ~PORT_OVERRIDE_LINK;
 991         b53_write8(dev, B53_CTRL_PAGE, off, reg);
 992 }
 993
 994 static void b53_force_port_config(struct b53_device *dev, int port,
 995                                   int speed, int duplex, int pause)
 996 {
 997         u8 reg, val, off;
 998
 999         /* Override the port settings */
1000         if (port == dev->cpu_port) {
1001                 off = B53_PORT_OVERRIDE_CTRL;
1002                 val = PORT_OVERRIDE_EN;
1003         } else {
1004                 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1005                 val = GMII_PO_EN;
1006         }
1007
1008         b53_read8(dev, B53_CTRL_PAGE, off, &reg);
1009         reg |= val;
1010         if (duplex == DUPLEX_FULL)
1011                 reg |= PORT_OVERRIDE_FULL_DUPLEX;
1012         else
1013                 reg &= ~PORT_OVERRIDE_FULL_DUPLEX;
1014
1015         switch (speed) {
1016         case 2000:
1017                 reg |= PORT_OVERRIDE_SPEED_2000M;
1018                 /* fallthrough */
1019         case SPEED_1000:
1020                 reg |= PORT_OVERRIDE_SPEED_1000M;
1021                 break;
1022         case SPEED_100:
1023                 reg |= PORT_OVERRIDE_SPEED_100M;
1024                 break;
1025         case SPEED_10:
1026                 reg |= PORT_OVERRIDE_SPEED_10M;
1027                 break;
1028         default:
1029                 dev_err(dev->dev, "unknown speed: %d\n", speed);
1030                 return;
1031         }
1032
1033         if (pause & MLO_PAUSE_RX)
1034                 reg |= PORT_OVERRIDE_RX_FLOW;
1035         if (pause & MLO_PAUSE_TX)
1036                 reg |= PORT_OVERRIDE_TX_FLOW;
1037
1038         b53_write8(dev, B53_CTRL_PAGE, off, reg);
1039 }
1040
1041 static void b53_adjust_link(struct dsa_switch *ds, int port,
1042                             struct phy_device *phydev)
1043 {
1044         struct b53_device *dev = ds->priv;
1045         struct ethtool_eee *p = &dev->ports[port].eee;
1046         u8 rgmii_ctrl = 0, reg = 0, off;
1047         int pause = 0;
1048
1049         if (!phy_is_pseudo_fixed_link(phydev))
1050                 return;
1051
1052         /* Enable flow control on BCM5301x's CPU port */
1053         if (is5301x(dev) && port == dev->cpu_port)
1054                 pause = MLO_PAUSE_TXRX_MASK;
1055
1056         if (phydev->pause) {
1057                 if (phydev->asym_pause)
1058                         pause |= MLO_PAUSE_TX;
1059                 pause |= MLO_PAUSE_RX;
1060         }
1061
1062         b53_force_port_config(dev, port, phydev->speed, phydev->duplex, pause);
1063         b53_force_link(dev, port, phydev->link);
1064
1065         if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
1066                 if (port == 8)
1067                         off = B53_RGMII_CTRL_IMP;
1068                 else
1069                         off = B53_RGMII_CTRL_P(port);
1070
1071                 /* Configure the port RGMII clock delay by DLL disabled and
1072                  * tx_clk aligned timing (restoring to reset defaults)
1073                  */
1074                 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1075                 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
1076                                 RGMII_CTRL_TIMING_SEL);
1077
1078                 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
1079                  * sure that we enable the port TX clock internal delay to
1080                  * account for this internal delay that is inserted, otherwise
1081                  * the switch won't be able to receive correctly.
1082                  *
1083                  * PHY_INTERFACE_MODE_RGMII means that we are not introducing
1084                  * any delay neither on transmission nor reception, so the
1085                  * BCM53125 must also be configured accordingly to account for
1086                  * the lack of delay and introduce
1087                  *
1088                  * The BCM53125 switch has its RX clock and TX clock control
1089                  * swapped, hence the reason why we modify the TX clock path in
1090                  * the "RGMII" case
1091                  */
1092                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1093                         rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1094                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1095                         rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
1096                 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
1097                 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1098
1099                 dev_info(ds->dev, "Configured port %d for %s\n", port,
1100                          phy_modes(phydev->interface));
1101         }
1102
1103         /* configure MII port if necessary */
1104         if (is5325(dev)) {
1105                 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1106                           &reg);
1107
1108                 /* reverse mii needs to be enabled */
1109                 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1110                         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1111                                    reg | PORT_OVERRIDE_RV_MII_25);
1112                         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1113                                   &reg);
1114
1115                         if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1116                                 dev_err(ds->dev,
1117                                         "Failed to enable reverse MII mode\n");
1118                                 return;
1119                         }
1120                 }
1121         } else if (is5301x(dev)) {
1122                 if (port != dev->cpu_port) {
1123                         b53_force_port_config(dev, dev->cpu_port, 2000,
1124                                               DUPLEX_FULL, MLO_PAUSE_TXRX_MASK);
1125                         b53_force_link(dev, dev->cpu_port, 1);
1126                 }
1127         }
1128
1129         /* Re-negotiate EEE if it was enabled already */
1130         p->eee_enabled = b53_eee_init(ds, port, phydev);
1131 }
1132
1133 void b53_port_event(struct dsa_switch *ds, int port)
1134 {
1135         struct b53_device *dev = ds->priv;
1136         bool link;
1137         u16 sts;
1138
1139         b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts);
1140         link = !!(sts & BIT(port));
1141         dsa_port_phylink_mac_change(ds, port, link);
1142 }
1143 EXPORT_SYMBOL(b53_port_event);
1144
1145 void b53_phylink_validate(struct dsa_switch *ds, int port,
1146                           unsigned long *supported,
1147                           struct phylink_link_state *state)
1148 {
1149         struct b53_device *dev = ds->priv;
1150         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1151
1152         if (dev->ops->serdes_phylink_validate)
1153                 dev->ops->serdes_phylink_validate(dev, port, mask, state);
1154
1155         /* Allow all the expected bits */
1156         phylink_set(mask, Autoneg);
1157         phylink_set_port_modes(mask);
1158         phylink_set(mask, Pause);
1159         phylink_set(mask, Asym_Pause);
1160
1161         /* With the exclusion of 5325/5365, MII, Reverse MII and 802.3z, we
1162          * support Gigabit, including Half duplex.
1163          */
1164         if (state->interface != PHY_INTERFACE_MODE_MII &&
1165             state->interface != PHY_INTERFACE_MODE_REVMII &&
1166             !phy_interface_mode_is_8023z(state->interface) &&
1167             !(is5325(dev) || is5365(dev))) {
1168                 phylink_set(mask, 1000baseT_Full);
1169                 phylink_set(mask, 1000baseT_Half);
1170         }
1171
1172         if (!phy_interface_mode_is_8023z(state->interface)) {
1173                 phylink_set(mask, 10baseT_Half);
1174                 phylink_set(mask, 10baseT_Full);
1175                 phylink_set(mask, 100baseT_Half);
1176                 phylink_set(mask, 100baseT_Full);
1177         }
1178
1179         bitmap_and(supported, supported, mask,
1180                    __ETHTOOL_LINK_MODE_MASK_NBITS);
1181         bitmap_and(state->advertising, state->advertising, mask,
1182                    __ETHTOOL_LINK_MODE_MASK_NBITS);
1183
1184         phylink_helper_basex_speed(state);
1185 }
1186 EXPORT_SYMBOL(b53_phylink_validate);
1187
1188 int b53_phylink_mac_link_state(struct dsa_switch *ds, int port,
1189                                struct phylink_link_state *state)
1190 {
1191         struct b53_device *dev = ds->priv;
1192         int ret = -EOPNOTSUPP;
1193
1194         if ((phy_interface_mode_is_8023z(state->interface) ||
1195              state->interface == PHY_INTERFACE_MODE_SGMII) &&
1196              dev->ops->serdes_link_state)
1197                 ret = dev->ops->serdes_link_state(dev, port, state);
1198
1199         return ret;
1200 }
1201 EXPORT_SYMBOL(b53_phylink_mac_link_state);
1202
1203 void b53_phylink_mac_config(struct dsa_switch *ds, int port,
1204                             unsigned int mode,
1205                             const struct phylink_link_state *state)
1206 {
1207         struct b53_device *dev = ds->priv;
1208
1209         if (mode == MLO_AN_PHY)
1210                 return;
1211
1212         if (mode == MLO_AN_FIXED) {
1213                 b53_force_port_config(dev, port, state->speed,
1214                                       state->duplex, state->pause);
1215                 return;
1216         }
1217
1218         if ((phy_interface_mode_is_8023z(state->interface) ||
1219              state->interface == PHY_INTERFACE_MODE_SGMII) &&
1220              dev->ops->serdes_config)
1221                 dev->ops->serdes_config(dev, port, mode, state);
1222 }
1223 EXPORT_SYMBOL(b53_phylink_mac_config);
1224
1225 void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port)
1226 {
1227         struct b53_device *dev = ds->priv;
1228
1229         if (dev->ops->serdes_an_restart)
1230                 dev->ops->serdes_an_restart(dev, port);
1231 }
1232 EXPORT_SYMBOL(b53_phylink_mac_an_restart);
1233
1234 void b53_phylink_mac_link_down(struct dsa_switch *ds, int port,
1235                                unsigned int mode,
1236                                phy_interface_t interface)
1237 {
1238         struct b53_device *dev = ds->priv;
1239
1240         if (mode == MLO_AN_PHY)
1241                 return;
1242
1243         if (mode == MLO_AN_FIXED) {
1244                 b53_force_link(dev, port, false);
1245                 return;
1246         }
1247
1248         if (phy_interface_mode_is_8023z(interface) &&
1249             dev->ops->serdes_link_set)
1250                 dev->ops->serdes_link_set(dev, port, mode, interface, false);
1251 }
1252 EXPORT_SYMBOL(b53_phylink_mac_link_down);
1253
1254 void b53_phylink_mac_link_up(struct dsa_switch *ds, int port,
1255                              unsigned int mode,
1256                              phy_interface_t interface,
1257                              struct phy_device *phydev)
1258 {
1259         struct b53_device *dev = ds->priv;
1260
1261         if (mode == MLO_AN_PHY)
1262                 return;
1263
1264         if (mode == MLO_AN_FIXED) {
1265                 b53_force_link(dev, port, true);
1266                 return;
1267         }
1268
1269         if (phy_interface_mode_is_8023z(interface) &&
1270             dev->ops->serdes_link_set)
1271                 dev->ops->serdes_link_set(dev, port, mode, interface, true);
1272 }
1273 EXPORT_SYMBOL(b53_phylink_mac_link_up);
1274
1275 int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering)
1276 {
1277         struct b53_device *dev = ds->priv;
1278         struct net_device *bridge_dev;
1279         unsigned int i;
1280         u16 pvid, new_pvid;
1281
1282         /* Handle the case were multiple bridges span the same switch device
1283          * and one of them has a different setting than what is being requested
1284          * which would be breaking filtering semantics for any of the other
1285          * bridge devices.
1286          */
1287         b53_for_each_port(dev, i) {
1288                 bridge_dev = dsa_to_port(ds, i)->bridge_dev;
1289                 if (bridge_dev &&
1290                     bridge_dev != dsa_to_port(ds, port)->bridge_dev &&
1291                     br_vlan_enabled(bridge_dev) != vlan_filtering) {
1292                         netdev_err(bridge_dev,
1293                                    "VLAN filtering is global to the switch!\n");
1294                         return -EINVAL;
1295                 }
1296         }
1297
1298         b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1299         new_pvid = pvid;
1300         if (dev->vlan_filtering_enabled && !vlan_filtering) {
1301                 /* Filtering is currently enabled, use the default PVID since
1302                  * the bridge does not expect tagging anymore
1303                  */
1304                 dev->ports[port].pvid = pvid;
1305                 new_pvid = b53_default_pvid(dev);
1306         } else if (!dev->vlan_filtering_enabled && vlan_filtering) {
1307                 /* Filtering is currently disabled, restore the previous PVID */
1308                 new_pvid = dev->ports[port].pvid;
1309         }
1310
1311         if (pvid != new_pvid)
1312                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1313                             new_pvid);
1314
1315         b53_enable_vlan(dev, dev->vlan_enabled, vlan_filtering);
1316
1317         return 0;
1318 }
1319 EXPORT_SYMBOL(b53_vlan_filtering);
1320
1321 int b53_vlan_prepare(struct dsa_switch *ds, int port,
1322                      const struct switchdev_obj_port_vlan *vlan)
1323 {
1324         struct b53_device *dev = ds->priv;
1325
1326         if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
1327                 return -EOPNOTSUPP;
1328
1329         if (vlan->vid_end > dev->num_vlans)
1330                 return -ERANGE;
1331
1332         b53_enable_vlan(dev, true, dev->vlan_filtering_enabled);
1333
1334         return 0;
1335 }
1336 EXPORT_SYMBOL(b53_vlan_prepare);
1337
1338 void b53_vlan_add(struct dsa_switch *ds, int port,
1339                   const struct switchdev_obj_port_vlan *vlan)
1340 {
1341         struct b53_device *dev = ds->priv;
1342         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1343         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1344         struct b53_vlan *vl;
1345         u16 vid;
1346
1347         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1348                 vl = &dev->vlans[vid];
1349
1350                 b53_get_vlan_entry(dev, vid, vl);
1351
1352                 vl->members |= BIT(port);
1353                 if (untagged && !dsa_is_cpu_port(ds, port))
1354                         vl->untag |= BIT(port);
1355                 else
1356                         vl->untag &= ~BIT(port);
1357
1358                 b53_set_vlan_entry(dev, vid, vl);
1359                 b53_fast_age_vlan(dev, vid);
1360         }
1361
1362         if (pvid && !dsa_is_cpu_port(ds, port)) {
1363                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1364                             vlan->vid_end);
1365                 b53_fast_age_vlan(dev, vid);
1366         }
1367 }
1368 EXPORT_SYMBOL(b53_vlan_add);
1369
1370 int b53_vlan_del(struct dsa_switch *ds, int port,
1371                  const struct switchdev_obj_port_vlan *vlan)
1372 {
1373         struct b53_device *dev = ds->priv;
1374         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1375         struct b53_vlan *vl;
1376         u16 vid;
1377         u16 pvid;
1378
1379         b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1380
1381         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1382                 vl = &dev->vlans[vid];
1383
1384                 b53_get_vlan_entry(dev, vid, vl);
1385
1386                 vl->members &= ~BIT(port);
1387
1388                 if (pvid == vid)
1389                         pvid = b53_default_pvid(dev);
1390
1391                 if (untagged && !dsa_is_cpu_port(ds, port))
1392                         vl->untag &= ~(BIT(port));
1393
1394                 b53_set_vlan_entry(dev, vid, vl);
1395                 b53_fast_age_vlan(dev, vid);
1396         }
1397
1398         b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1399         b53_fast_age_vlan(dev, pvid);
1400
1401         return 0;
1402 }
1403 EXPORT_SYMBOL(b53_vlan_del);
1404
1405 /* Address Resolution Logic routines */
1406 static int b53_arl_op_wait(struct b53_device *dev)
1407 {
1408         unsigned int timeout = 10;
1409         u8 reg;
1410
1411         do {
1412                 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1413                 if (!(reg & ARLTBL_START_DONE))
1414                         return 0;
1415
1416                 usleep_range(1000, 2000);
1417         } while (timeout--);
1418
1419         dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1420
1421         return -ETIMEDOUT;
1422 }
1423
1424 static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1425 {
1426         u8 reg;
1427
1428         if (op > ARLTBL_RW)
1429                 return -EINVAL;
1430
1431         b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1432         reg |= ARLTBL_START_DONE;
1433         if (op)
1434                 reg |= ARLTBL_RW;
1435         else
1436                 reg &= ~ARLTBL_RW;
1437         b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1438
1439         return b53_arl_op_wait(dev);
1440 }
1441
1442 static int b53_arl_read(struct b53_device *dev, u64 mac,
1443                         u16 vid, struct b53_arl_entry *ent, u8 *idx,
1444                         bool is_valid)
1445 {
1446         unsigned int i;
1447         int ret;
1448
1449         ret = b53_arl_op_wait(dev);
1450         if (ret)
1451                 return ret;
1452
1453         /* Read the bins */
1454         for (i = 0; i < dev->num_arl_entries; i++) {
1455                 u64 mac_vid;
1456                 u32 fwd_entry;
1457
1458                 b53_read64(dev, B53_ARLIO_PAGE,
1459                            B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1460                 b53_read32(dev, B53_ARLIO_PAGE,
1461                            B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1462                 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1463
1464                 if (!(fwd_entry & ARLTBL_VALID))
1465                         continue;
1466                 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1467                         continue;
1468                 *idx = i;
1469         }
1470
1471         return -ENOENT;
1472 }
1473
1474 static int b53_arl_op(struct b53_device *dev, int op, int port,
1475                       const unsigned char *addr, u16 vid, bool is_valid)
1476 {
1477         struct b53_arl_entry ent;
1478         u32 fwd_entry;
1479         u64 mac, mac_vid = 0;
1480         u8 idx = 0;
1481         int ret;
1482
1483         /* Convert the array into a 64-bit MAC */
1484         mac = ether_addr_to_u64(addr);
1485
1486         /* Perform a read for the given MAC and VID */
1487         b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1488         b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1489
1490         /* Issue a read operation for this MAC */
1491         ret = b53_arl_rw_op(dev, 1);
1492         if (ret)
1493                 return ret;
1494
1495         ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1496         /* If this is a read, just finish now */
1497         if (op)
1498                 return ret;
1499
1500         /* We could not find a matching MAC, so reset to a new entry */
1501         if (ret) {
1502                 fwd_entry = 0;
1503                 idx = 1;
1504         }
1505
1506         memset(&ent, 0, sizeof(ent));
1507         ent.port = port;
1508         ent.is_valid = is_valid;
1509         ent.vid = vid;
1510         ent.is_static = true;
1511         memcpy(ent.mac, addr, ETH_ALEN);
1512         b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1513
1514         b53_write64(dev, B53_ARLIO_PAGE,
1515                     B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1516         b53_write32(dev, B53_ARLIO_PAGE,
1517                     B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1518
1519         return b53_arl_rw_op(dev, 0);
1520 }
1521
1522 int b53_fdb_add(struct dsa_switch *ds, int port,
1523                 const unsigned char *addr, u16 vid)
1524 {
1525         struct b53_device *priv = ds->priv;
1526
1527         /* 5325 and 5365 require some more massaging, but could
1528          * be supported eventually
1529          */
1530         if (is5325(priv) || is5365(priv))
1531                 return -EOPNOTSUPP;
1532
1533         return b53_arl_op(priv, 0, port, addr, vid, true);
1534 }
1535 EXPORT_SYMBOL(b53_fdb_add);
1536
1537 int b53_fdb_del(struct dsa_switch *ds, int port,
1538                 const unsigned char *addr, u16 vid)
1539 {
1540         struct b53_device *priv = ds->priv;
1541
1542         return b53_arl_op(priv, 0, port, addr, vid, false);
1543 }
1544 EXPORT_SYMBOL(b53_fdb_del);
1545
1546 static int b53_arl_search_wait(struct b53_device *dev)
1547 {
1548         unsigned int timeout = 1000;
1549         u8 reg;
1550
1551         do {
1552                 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
1553                 if (!(reg & ARL_SRCH_STDN))
1554                         return 0;
1555
1556                 if (reg & ARL_SRCH_VLID)
1557                         return 0;
1558
1559                 usleep_range(1000, 2000);
1560         } while (timeout--);
1561
1562         return -ETIMEDOUT;
1563 }
1564
1565 static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1566                               struct b53_arl_entry *ent)
1567 {
1568         u64 mac_vid;
1569         u32 fwd_entry;
1570
1571         b53_read64(dev, B53_ARLIO_PAGE,
1572                    B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1573         b53_read32(dev, B53_ARLIO_PAGE,
1574                    B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1575         b53_arl_to_entry(ent, mac_vid, fwd_entry);
1576 }
1577
1578 static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
1579                         dsa_fdb_dump_cb_t *cb, void *data)
1580 {
1581         if (!ent->is_valid)
1582                 return 0;
1583
1584         if (port != ent->port)
1585                 return 0;
1586
1587         return cb(ent->mac, ent->vid, ent->is_static, data);
1588 }
1589
1590 int b53_fdb_dump(struct dsa_switch *ds, int port,
1591                  dsa_fdb_dump_cb_t *cb, void *data)
1592 {
1593         struct b53_device *priv = ds->priv;
1594         struct b53_arl_entry results[2];
1595         unsigned int count = 0;
1596         int ret;
1597         u8 reg;
1598
1599         /* Start search operation */
1600         reg = ARL_SRCH_STDN;
1601         b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1602
1603         do {
1604                 ret = b53_arl_search_wait(priv);
1605                 if (ret)
1606                         return ret;
1607
1608                 b53_arl_search_rd(priv, 0, &results[0]);
1609                 ret = b53_fdb_copy(port, &results[0], cb, data);
1610                 if (ret)
1611                         return ret;
1612
1613                 if (priv->num_arl_entries > 2) {
1614                         b53_arl_search_rd(priv, 1, &results[1]);
1615                         ret = b53_fdb_copy(port, &results[1], cb, data);
1616                         if (ret)
1617                                 return ret;
1618
1619                         if (!results[0].is_valid && !results[1].is_valid)
1620                                 break;
1621                 }
1622
1623         } while (count++ < 1024);
1624
1625         return 0;
1626 }
1627 EXPORT_SYMBOL(b53_fdb_dump);
1628
1629 int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
1630 {
1631         struct b53_device *dev = ds->priv;
1632         s8 cpu_port = ds->ports[port].cpu_dp->index;
1633         u16 pvlan, reg;
1634         unsigned int i;
1635
1636         /* Make this port leave the all VLANs join since we will have proper
1637          * VLAN entries from now on
1638          */
1639         if (is58xx(dev)) {
1640                 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1641                 reg &= ~BIT(port);
1642                 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1643                         reg &= ~BIT(cpu_port);
1644                 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1645         }
1646
1647         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1648
1649         b53_for_each_port(dev, i) {
1650                 if (dsa_to_port(ds, i)->bridge_dev != br)
1651                         continue;
1652
1653                 /* Add this local port to the remote port VLAN control
1654                  * membership and update the remote port bitmask
1655                  */
1656                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1657                 reg |= BIT(port);
1658                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1659                 dev->ports[i].vlan_ctl_mask = reg;
1660
1661                 pvlan |= BIT(i);
1662         }
1663
1664         /* Configure the local port VLAN control membership to include
1665          * remote ports and update the local port bitmask
1666          */
1667         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1668         dev->ports[port].vlan_ctl_mask = pvlan;
1669
1670         return 0;
1671 }
1672 EXPORT_SYMBOL(b53_br_join);
1673
1674 void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
1675 {
1676         struct b53_device *dev = ds->priv;
1677         struct b53_vlan *vl = &dev->vlans[0];
1678         s8 cpu_port = ds->ports[port].cpu_dp->index;
1679         unsigned int i;
1680         u16 pvlan, reg, pvid;
1681
1682         b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1683
1684         b53_for_each_port(dev, i) {
1685                 /* Don't touch the remaining ports */
1686                 if (dsa_to_port(ds, i)->bridge_dev != br)
1687                         continue;
1688
1689                 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1690                 reg &= ~BIT(port);
1691                 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1692                 dev->ports[port].vlan_ctl_mask = reg;
1693
1694                 /* Prevent self removal to preserve isolation */
1695                 if (port != i)
1696                         pvlan &= ~BIT(i);
1697         }
1698
1699         b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1700         dev->ports[port].vlan_ctl_mask = pvlan;
1701
1702         pvid = b53_default_pvid(dev);
1703
1704         /* Make this port join all VLANs without VLAN entries */
1705         if (is58xx(dev)) {
1706                 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1707                 reg |= BIT(port);
1708                 if (!(reg & BIT(cpu_port)))
1709                         reg |= BIT(cpu_port);
1710                 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1711         } else {
1712                 b53_get_vlan_entry(dev, pvid, vl);
1713                 vl->members |= BIT(port) | BIT(cpu_port);
1714                 vl->untag |= BIT(port) | BIT(cpu_port);
1715                 b53_set_vlan_entry(dev, pvid, vl);
1716         }
1717 }
1718 EXPORT_SYMBOL(b53_br_leave);
1719
1720 void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1721 {
1722         struct b53_device *dev = ds->priv;
1723         u8 hw_state;
1724         u8 reg;
1725
1726         switch (state) {
1727         case BR_STATE_DISABLED:
1728                 hw_state = PORT_CTRL_DIS_STATE;
1729                 break;
1730         case BR_STATE_LISTENING:
1731                 hw_state = PORT_CTRL_LISTEN_STATE;
1732                 break;
1733         case BR_STATE_LEARNING:
1734                 hw_state = PORT_CTRL_LEARN_STATE;
1735                 break;
1736         case BR_STATE_FORWARDING:
1737                 hw_state = PORT_CTRL_FWD_STATE;
1738                 break;
1739         case BR_STATE_BLOCKING:
1740                 hw_state = PORT_CTRL_BLOCK_STATE;
1741                 break;
1742         default:
1743                 dev_err(ds->dev, "invalid STP state: %d\n", state);
1744                 return;
1745         }
1746
1747         b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1748         reg &= ~PORT_CTRL_STP_STATE_MASK;
1749         reg |= hw_state;
1750         b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1751 }
1752 EXPORT_SYMBOL(b53_br_set_stp_state);
1753
1754 void b53_br_fast_age(struct dsa_switch *ds, int port)
1755 {
1756         struct b53_device *dev = ds->priv;
1757
1758         if (b53_fast_age_port(dev, port))
1759                 dev_err(ds->dev, "fast ageing failed\n");
1760 }
1761 EXPORT_SYMBOL(b53_br_fast_age);
1762
1763 static bool b53_possible_cpu_port(struct dsa_switch *ds, int port)
1764 {
1765         /* Broadcom switches will accept enabling Broadcom tags on the
1766          * following ports: 5, 7 and 8, any other port is not supported
1767          */
1768         switch (port) {
1769         case B53_CPU_PORT_25:
1770         case 7:
1771         case B53_CPU_PORT:
1772                 return true;
1773         }
1774
1775         return false;
1776 }
1777
1778 static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port)
1779 {
1780         bool ret = b53_possible_cpu_port(ds, port);
1781
1782         if (!ret)
1783                 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n",
1784                          port);
1785         return ret;
1786 }
1787
1788 enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port)
1789 {
1790         struct b53_device *dev = ds->priv;
1791
1792         /* Older models (5325, 5365) support a different tag format that we do
1793          * not support in net/dsa/tag_brcm.c yet. 539x and 531x5 require managed
1794          * mode to be turned on which means we need to specifically manage ARL
1795          * misses on multicast addresses (TBD).
1796          */
1797         if (is5325(dev) || is5365(dev) || is539x(dev) || is531x5(dev) ||
1798             !b53_can_enable_brcm_tags(ds, port))
1799                 return DSA_TAG_PROTO_NONE;
1800
1801         /* Broadcom BCM58xx chips have a flow accelerator on Port 8
1802          * which requires us to use the prepended Broadcom tag type
1803          */
1804         if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT)
1805                 return DSA_TAG_PROTO_BRCM_PREPEND;
1806
1807         return DSA_TAG_PROTO_BRCM;
1808 }
1809 EXPORT_SYMBOL(b53_get_tag_protocol);
1810
1811 int b53_mirror_add(struct dsa_switch *ds, int port,
1812                    struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
1813 {
1814         struct b53_device *dev = ds->priv;
1815         u16 reg, loc;
1816
1817         if (ingress)
1818                 loc = B53_IG_MIR_CTL;
1819         else
1820                 loc = B53_EG_MIR_CTL;
1821
1822         b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1823         reg &= ~MIRROR_MASK;
1824         reg |= BIT(port);
1825         b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1826
1827         b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1828         reg &= ~CAP_PORT_MASK;
1829         reg |= mirror->to_local_port;
1830         reg |= MIRROR_EN;
1831         b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1832
1833         return 0;
1834 }
1835 EXPORT_SYMBOL(b53_mirror_add);
1836
1837 void b53_mirror_del(struct dsa_switch *ds, int port,
1838                     struct dsa_mall_mirror_tc_entry *mirror)
1839 {
1840         struct b53_device *dev = ds->priv;
1841         bool loc_disable = false, other_loc_disable = false;
1842         u16 reg, loc;
1843
1844         if (mirror->ingress)
1845                 loc = B53_IG_MIR_CTL;
1846         else
1847                 loc = B53_EG_MIR_CTL;
1848
1849         /* Update the desired ingress/egress register */
1850         b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1851         reg &= ~BIT(port);
1852         if (!(reg & MIRROR_MASK))
1853                 loc_disable = true;
1854         b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1855
1856         /* Now look at the other one to know if we can disable mirroring
1857          * entirely
1858          */
1859         if (mirror->ingress)
1860                 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, &reg);
1861         else
1862                 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, &reg);
1863         if (!(reg & MIRROR_MASK))
1864                 other_loc_disable = true;
1865
1866         b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1867         /* Both no longer have ports, let's disable mirroring */
1868         if (loc_disable && other_loc_disable) {
1869                 reg &= ~MIRROR_EN;
1870                 reg &= ~mirror->to_local_port;
1871         }
1872         b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1873 }
1874 EXPORT_SYMBOL(b53_mirror_del);
1875
1876 void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
1877 {
1878         struct b53_device *dev = ds->priv;
1879         u16 reg;
1880
1881         b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, &reg);
1882         if (enable)
1883                 reg |= BIT(port);
1884         else
1885                 reg &= ~BIT(port);
1886         b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
1887 }
1888 EXPORT_SYMBOL(b53_eee_enable_set);
1889
1890
1891 /* Returns 0 if EEE was not enabled, or 1 otherwise
1892  */
1893 int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
1894 {
1895         int ret;
1896
1897         ret = phy_init_eee(phy, 0);
1898         if (ret)
1899                 return 0;
1900
1901         b53_eee_enable_set(ds, port, true);
1902
1903         return 1;
1904 }
1905 EXPORT_SYMBOL(b53_eee_init);
1906
1907 int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1908 {
1909         struct b53_device *dev = ds->priv;
1910         struct ethtool_eee *p = &dev->ports[port].eee;
1911         u16 reg;
1912
1913         if (is5325(dev) || is5365(dev))
1914                 return -EOPNOTSUPP;
1915
1916         b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, &reg);
1917         e->eee_enabled = p->eee_enabled;
1918         e->eee_active = !!(reg & BIT(port));
1919
1920         return 0;
1921 }
1922 EXPORT_SYMBOL(b53_get_mac_eee);
1923
1924 int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1925 {
1926         struct b53_device *dev = ds->priv;
1927         struct ethtool_eee *p = &dev->ports[port].eee;
1928
1929         if (is5325(dev) || is5365(dev))
1930                 return -EOPNOTSUPP;
1931
1932         p->eee_enabled = e->eee_enabled;
1933         b53_eee_enable_set(ds, port, e->eee_enabled);
1934
1935         return 0;
1936 }
1937 EXPORT_SYMBOL(b53_set_mac_eee);
1938
1939 static const struct dsa_switch_ops b53_switch_ops = {
1940         .get_tag_protocol       = b53_get_tag_protocol,
1941         .setup                  = b53_setup,
1942         .get_strings            = b53_get_strings,
1943         .get_ethtool_stats      = b53_get_ethtool_stats,
1944         .get_sset_count         = b53_get_sset_count,
1945         .get_ethtool_phy_stats  = b53_get_ethtool_phy_stats,
1946         .phy_read               = b53_phy_read16,
1947         .phy_write              = b53_phy_write16,
1948         .adjust_link            = b53_adjust_link,
1949         .phylink_validate       = b53_phylink_validate,
1950         .phylink_mac_link_state = b53_phylink_mac_link_state,
1951         .phylink_mac_config     = b53_phylink_mac_config,
1952         .phylink_mac_an_restart = b53_phylink_mac_an_restart,
1953         .phylink_mac_link_down  = b53_phylink_mac_link_down,
1954         .phylink_mac_link_up    = b53_phylink_mac_link_up,
1955         .port_enable            = b53_enable_port,
1956         .port_disable           = b53_disable_port,
1957         .get_mac_eee            = b53_get_mac_eee,
1958         .set_mac_eee            = b53_set_mac_eee,
1959         .port_bridge_join       = b53_br_join,
1960         .port_bridge_leave      = b53_br_leave,
1961         .port_stp_state_set     = b53_br_set_stp_state,
1962         .port_fast_age          = b53_br_fast_age,
1963         .port_vlan_filtering    = b53_vlan_filtering,
1964         .port_vlan_prepare      = b53_vlan_prepare,
1965         .port_vlan_add          = b53_vlan_add,
1966         .port_vlan_del          = b53_vlan_del,
1967         .port_fdb_dump          = b53_fdb_dump,
1968         .port_fdb_add           = b53_fdb_add,
1969         .port_fdb_del           = b53_fdb_del,
1970         .port_mirror_add        = b53_mirror_add,
1971         .port_mirror_del        = b53_mirror_del,
1972 };
1973
1974 struct b53_chip_data {
1975         u32 chip_id;
1976         const char *dev_name;
1977         u16 vlans;
1978         u16 enabled_ports;
1979         u8 cpu_port;
1980         u8 vta_regs[3];
1981         u8 arl_entries;
1982         u8 duplex_reg;
1983         u8 jumbo_pm_reg;
1984         u8 jumbo_size_reg;
1985 };
1986
1987 #define B53_VTA_REGS    \
1988         { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1989 #define B53_VTA_REGS_9798 \
1990         { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1991 #define B53_VTA_REGS_63XX \
1992         { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1993
1994 static const struct b53_chip_data b53_switch_chips[] = {
1995         {
1996                 .chip_id = BCM5325_DEVICE_ID,
1997                 .dev_name = "BCM5325",
1998                 .vlans = 16,
1999                 .enabled_ports = 0x1f,
2000                 .arl_entries = 2,
2001                 .cpu_port = B53_CPU_PORT_25,
2002                 .duplex_reg = B53_DUPLEX_STAT_FE,
2003         },
2004         {
2005                 .chip_id = BCM5365_DEVICE_ID,
2006                 .dev_name = "BCM5365",
2007                 .vlans = 256,
2008                 .enabled_ports = 0x1f,
2009                 .arl_entries = 2,
2010                 .cpu_port = B53_CPU_PORT_25,
2011                 .duplex_reg = B53_DUPLEX_STAT_FE,
2012         },
2013         {
2014                 .chip_id = BCM5389_DEVICE_ID,
2015                 .dev_name = "BCM5389",
2016                 .vlans = 4096,
2017                 .enabled_ports = 0x1f,
2018                 .arl_entries = 4,
2019                 .cpu_port = B53_CPU_PORT,
2020                 .vta_regs = B53_VTA_REGS,
2021                 .duplex_reg = B53_DUPLEX_STAT_GE,
2022                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2023                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2024         },
2025         {
2026                 .chip_id = BCM5395_DEVICE_ID,
2027                 .dev_name = "BCM5395",
2028                 .vlans = 4096,
2029                 .enabled_ports = 0x1f,
2030                 .arl_entries = 4,
2031                 .cpu_port = B53_CPU_PORT,
2032                 .vta_regs = B53_VTA_REGS,
2033                 .duplex_reg = B53_DUPLEX_STAT_GE,
2034                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2035                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2036         },
2037         {
2038                 .chip_id = BCM5397_DEVICE_ID,
2039                 .dev_name = "BCM5397",
2040                 .vlans = 4096,
2041                 .enabled_ports = 0x1f,
2042                 .arl_entries = 4,
2043                 .cpu_port = B53_CPU_PORT,
2044                 .vta_regs = B53_VTA_REGS_9798,
2045                 .duplex_reg = B53_DUPLEX_STAT_GE,
2046                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2047                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2048         },
2049         {
2050                 .chip_id = BCM5398_DEVICE_ID,
2051                 .dev_name = "BCM5398",
2052                 .vlans = 4096,
2053                 .enabled_ports = 0x7f,
2054                 .arl_entries = 4,
2055                 .cpu_port = B53_CPU_PORT,
2056                 .vta_regs = B53_VTA_REGS_9798,
2057                 .duplex_reg = B53_DUPLEX_STAT_GE,
2058                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2059                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2060         },
2061         {
2062                 .chip_id = BCM53115_DEVICE_ID,
2063                 .dev_name = "BCM53115",
2064                 .vlans = 4096,
2065                 .enabled_ports = 0x1f,
2066                 .arl_entries = 4,
2067                 .vta_regs = B53_VTA_REGS,
2068                 .cpu_port = B53_CPU_PORT,
2069                 .duplex_reg = B53_DUPLEX_STAT_GE,
2070                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2071                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2072         },
2073         {
2074                 .chip_id = BCM53125_DEVICE_ID,
2075                 .dev_name = "BCM53125",
2076                 .vlans = 4096,
2077                 .enabled_ports = 0xff,
2078                 .arl_entries = 4,
2079                 .cpu_port = B53_CPU_PORT,
2080                 .vta_regs = B53_VTA_REGS,
2081                 .duplex_reg = B53_DUPLEX_STAT_GE,
2082                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2083                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2084         },
2085         {
2086                 .chip_id = BCM53128_DEVICE_ID,
2087                 .dev_name = "BCM53128",
2088                 .vlans = 4096,
2089                 .enabled_ports = 0x1ff,
2090                 .arl_entries = 4,
2091                 .cpu_port = B53_CPU_PORT,
2092                 .vta_regs = B53_VTA_REGS,
2093                 .duplex_reg = B53_DUPLEX_STAT_GE,
2094                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2095                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2096         },
2097         {
2098                 .chip_id = BCM63XX_DEVICE_ID,
2099                 .dev_name = "BCM63xx",
2100                 .vlans = 4096,
2101                 .enabled_ports = 0, /* pdata must provide them */
2102                 .arl_entries = 4,
2103                 .cpu_port = B53_CPU_PORT,
2104                 .vta_regs = B53_VTA_REGS_63XX,
2105                 .duplex_reg = B53_DUPLEX_STAT_63XX,
2106                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
2107                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
2108         },
2109         {
2110                 .chip_id = BCM53010_DEVICE_ID,
2111                 .dev_name = "BCM53010",
2112                 .vlans = 4096,
2113                 .enabled_ports = 0x1f,
2114                 .arl_entries = 4,
2115                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2116                 .vta_regs = B53_VTA_REGS,
2117                 .duplex_reg = B53_DUPLEX_STAT_GE,
2118                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2119                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2120         },
2121         {
2122                 .chip_id = BCM53011_DEVICE_ID,
2123                 .dev_name = "BCM53011",
2124                 .vlans = 4096,
2125                 .enabled_ports = 0x1bf,
2126                 .arl_entries = 4,
2127                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2128                 .vta_regs = B53_VTA_REGS,
2129                 .duplex_reg = B53_DUPLEX_STAT_GE,
2130                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2131                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2132         },
2133         {
2134                 .chip_id = BCM53012_DEVICE_ID,
2135                 .dev_name = "BCM53012",
2136                 .vlans = 4096,
2137                 .enabled_ports = 0x1bf,
2138                 .arl_entries = 4,
2139                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2140                 .vta_regs = B53_VTA_REGS,
2141                 .duplex_reg = B53_DUPLEX_STAT_GE,
2142                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2143                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2144         },
2145         {
2146                 .chip_id = BCM53018_DEVICE_ID,
2147                 .dev_name = "BCM53018",
2148                 .vlans = 4096,
2149                 .enabled_ports = 0x1f,
2150                 .arl_entries = 4,
2151                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2152                 .vta_regs = B53_VTA_REGS,
2153                 .duplex_reg = B53_DUPLEX_STAT_GE,
2154                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2155                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2156         },
2157         {
2158                 .chip_id = BCM53019_DEVICE_ID,
2159                 .dev_name = "BCM53019",
2160                 .vlans = 4096,
2161                 .enabled_ports = 0x1f,
2162                 .arl_entries = 4,
2163                 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2164                 .vta_regs = B53_VTA_REGS,
2165                 .duplex_reg = B53_DUPLEX_STAT_GE,
2166                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2167                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2168         },
2169         {
2170                 .chip_id = BCM58XX_DEVICE_ID,
2171                 .dev_name = "BCM585xx/586xx/88312",
2172                 .vlans  = 4096,
2173                 .enabled_ports = 0x1ff,
2174                 .arl_entries = 4,
2175                 .cpu_port = B53_CPU_PORT,
2176                 .vta_regs = B53_VTA_REGS,
2177                 .duplex_reg = B53_DUPLEX_STAT_GE,
2178                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2179                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2180         },
2181         {
2182                 .chip_id = BCM583XX_DEVICE_ID,
2183                 .dev_name = "BCM583xx/11360",
2184                 .vlans = 4096,
2185                 .enabled_ports = 0x103,
2186                 .arl_entries = 4,
2187                 .cpu_port = B53_CPU_PORT,
2188                 .vta_regs = B53_VTA_REGS,
2189                 .duplex_reg = B53_DUPLEX_STAT_GE,
2190                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2191                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2192         },
2193         {
2194                 .chip_id = BCM7445_DEVICE_ID,
2195                 .dev_name = "BCM7445",
2196                 .vlans  = 4096,
2197                 .enabled_ports = 0x1ff,
2198                 .arl_entries = 4,
2199                 .cpu_port = B53_CPU_PORT,
2200                 .vta_regs = B53_VTA_REGS,
2201                 .duplex_reg = B53_DUPLEX_STAT_GE,
2202                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2203                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2204         },
2205         {
2206                 .chip_id = BCM7278_DEVICE_ID,
2207                 .dev_name = "BCM7278",
2208                 .vlans = 4096,
2209                 .enabled_ports = 0x1ff,
2210                 .arl_entries= 4,
2211                 .cpu_port = B53_CPU_PORT,
2212                 .vta_regs = B53_VTA_REGS,
2213                 .duplex_reg = B53_DUPLEX_STAT_GE,
2214                 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2215                 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2216         },
2217 };
2218
2219 static int b53_switch_init(struct b53_device *dev)
2220 {
2221         unsigned int i;
2222         int ret;
2223
2224         for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
2225                 const struct b53_chip_data *chip = &b53_switch_chips[i];
2226
2227                 if (chip->chip_id == dev->chip_id) {
2228                         if (!dev->enabled_ports)
2229                                 dev->enabled_ports = chip->enabled_ports;
2230                         dev->name = chip->dev_name;
2231                         dev->duplex_reg = chip->duplex_reg;
2232                         dev->vta_regs[0] = chip->vta_regs[0];
2233                         dev->vta_regs[1] = chip->vta_regs[1];
2234                         dev->vta_regs[2] = chip->vta_regs[2];
2235                         dev->jumbo_pm_reg = chip->jumbo_pm_reg;
2236                         dev->cpu_port = chip->cpu_port;
2237                         dev->num_vlans = chip->vlans;
2238                         dev->num_arl_entries = chip->arl_entries;
2239                         break;
2240                 }
2241         }
2242
2243         /* check which BCM5325x version we have */
2244         if (is5325(dev)) {
2245                 u8 vc4;
2246
2247                 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
2248
2249                 /* check reserved bits */
2250                 switch (vc4 & 3) {
2251                 case 1:
2252                         /* BCM5325E */
2253                         break;
2254                 case 3:
2255                         /* BCM5325F - do not use port 4 */
2256                         dev->enabled_ports &= ~BIT(4);
2257                         break;
2258                 default:
2259 /* On the BCM47XX SoCs this is the supported internal switch.*/
2260 #ifndef CONFIG_BCM47XX
2261                         /* BCM5325M */
2262                         return -EINVAL;
2263 #else
2264                         break;
2265 #endif
2266                 }
2267         } else if (dev->chip_id == BCM53115_DEVICE_ID) {
2268                 u64 strap_value;
2269
2270                 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
2271                 /* use second IMP port if GMII is enabled */
2272                 if (strap_value & SV_GMII_CTRL_115)
2273                         dev->cpu_port = 5;
2274         }
2275
2276         /* cpu port is always last */
2277         dev->num_ports = dev->cpu_port + 1;
2278         dev->enabled_ports |= BIT(dev->cpu_port);
2279
2280         /* Include non standard CPU port built-in PHYs to be probed */
2281         if (is539x(dev) || is531x5(dev)) {
2282                 for (i = 0; i < dev->num_ports; i++) {
2283                         if (!(dev->ds->phys_mii_mask & BIT(i)) &&
2284                             !b53_possible_cpu_port(dev->ds, i))
2285                                 dev->ds->phys_mii_mask |= BIT(i);
2286                 }
2287         }
2288
2289         dev->ports = devm_kcalloc(dev->dev,
2290                                   dev->num_ports, sizeof(struct b53_port),
2291                                   GFP_KERNEL);
2292         if (!dev->ports)
2293                 return -ENOMEM;
2294
2295         dev->vlans = devm_kcalloc(dev->dev,
2296                                   dev->num_vlans, sizeof(struct b53_vlan),
2297                                   GFP_KERNEL);
2298         if (!dev->vlans)
2299                 return -ENOMEM;
2300
2301         dev->reset_gpio = b53_switch_get_reset_gpio(dev);
2302         if (dev->reset_gpio >= 0) {
2303                 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
2304                                             GPIOF_OUT_INIT_HIGH, "robo_reset");
2305                 if (ret)
2306                         return ret;
2307         }
2308
2309         return 0;
2310 }
2311
2312 struct b53_device *b53_switch_alloc(struct device *base,
2313                                     const struct b53_io_ops *ops,
2314                                     void *priv)
2315 {
2316         struct dsa_switch *ds;
2317         struct b53_device *dev;
2318
2319         ds = dsa_switch_alloc(base, DSA_MAX_PORTS);
2320         if (!ds)
2321                 return NULL;
2322
2323         dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
2324         if (!dev)
2325                 return NULL;
2326
2327         ds->priv = dev;
2328         dev->dev = base;
2329
2330         dev->ds = ds;
2331         dev->priv = priv;
2332         dev->ops = ops;
2333         ds->ops = &b53_switch_ops;
2334         mutex_init(&dev->reg_mutex);
2335         mutex_init(&dev->stats_mutex);
2336
2337         return dev;
2338 }
2339 EXPORT_SYMBOL(b53_switch_alloc);
2340
2341 int b53_switch_detect(struct b53_device *dev)
2342 {
2343         u32 id32;
2344         u16 tmp;
2345         u8 id8;
2346         int ret;
2347
2348         ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2349         if (ret)
2350                 return ret;
2351
2352         switch (id8) {
2353         case 0:
2354                 /* BCM5325 and BCM5365 do not have this register so reads
2355                  * return 0. But the read operation did succeed, so assume this
2356                  * is one of them.
2357                  *
2358                  * Next check if we can write to the 5325's VTA register; for
2359                  * 5365 it is read only.
2360                  */
2361                 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2362                 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2363
2364                 if (tmp == 0xf)
2365                         dev->chip_id = BCM5325_DEVICE_ID;
2366                 else
2367                         dev->chip_id = BCM5365_DEVICE_ID;
2368                 break;
2369         case BCM5389_DEVICE_ID:
2370         case BCM5395_DEVICE_ID:
2371         case BCM5397_DEVICE_ID:
2372         case BCM5398_DEVICE_ID:
2373                 dev->chip_id = id8;
2374                 break;
2375         default:
2376                 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2377                 if (ret)
2378                         return ret;
2379
2380                 switch (id32) {
2381                 case BCM53115_DEVICE_ID:
2382                 case BCM53125_DEVICE_ID:
2383                 case BCM53128_DEVICE_ID:
2384                 case BCM53010_DEVICE_ID:
2385                 case BCM53011_DEVICE_ID:
2386                 case BCM53012_DEVICE_ID:
2387                 case BCM53018_DEVICE_ID:
2388                 case BCM53019_DEVICE_ID:
2389                         dev->chip_id = id32;
2390                         break;
2391                 default:
2392                         pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
2393                                id8, id32);
2394                         return -ENODEV;
2395                 }
2396         }
2397
2398         if (dev->chip_id == BCM5325_DEVICE_ID)
2399                 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2400                                  &dev->core_rev);
2401         else
2402                 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2403                                  &dev->core_rev);
2404 }
2405 EXPORT_SYMBOL(b53_switch_detect);
2406
2407 int b53_switch_register(struct b53_device *dev)
2408 {
2409         int ret;
2410
2411         if (dev->pdata) {
2412                 dev->chip_id = dev->pdata->chip_id;
2413                 dev->enabled_ports = dev->pdata->enabled_ports;
2414         }
2415
2416         if (!dev->chip_id && b53_switch_detect(dev))
2417                 return -EINVAL;
2418
2419         ret = b53_switch_init(dev);
2420         if (ret)
2421                 return ret;
2422
2423         pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
2424
2425         return dsa_register_switch(dev->ds);
2426 }
2427 EXPORT_SYMBOL(b53_switch_register);
2428
2429 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2430 MODULE_DESCRIPTION("B53 switch library");
2431 MODULE_LICENSE("Dual BSD/GPL");