drivers/net/can/flexcan.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // flexcan.c - FLEXCAN CAN controller driver
   4 //
   5 // Copyright (c) 2005-2006 Varma Electronics Oy
   6 // Copyright (c) 2009 Sascha Hauer, Pengutronix
   7 // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
   8 // Copyright (c) 2014 David Jander, Protonic Holland
   9 //
  10 // Based on code originally by Andrey Volkov <avolkov@varma-el.com>
  11
  12 #include <linux/can.h>
  13 #include <linux/can/dev.h>
  14 #include <linux/can/error.h>
  15 #include <linux/can/led.h>
  16 #include <linux/can/rx-offload.h>
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/io.h>
  21 #include <linux/mfd/syscon.h>
  22 #include <linux/module.h>
  23 #include <linux/netdevice.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/regmap.h>
  29 #include <linux/regulator/consumer.h>
  30
  31 #define DRV_NAME                        "flexcan"
  32
  33 /* 8 for RX fifo and 2 error handling */
  34 #define FLEXCAN_NAPI_WEIGHT             (8 + 2)
  35
  36 /* FLEXCAN module configuration register (CANMCR) bits */
  37 #define FLEXCAN_MCR_MDIS                BIT(31)
  38 #define FLEXCAN_MCR_FRZ                 BIT(30)
  39 #define FLEXCAN_MCR_FEN                 BIT(29)
  40 #define FLEXCAN_MCR_HALT                BIT(28)
  41 #define FLEXCAN_MCR_NOT_RDY             BIT(27)
  42 #define FLEXCAN_MCR_WAK_MSK             BIT(26)
  43 #define FLEXCAN_MCR_SOFTRST             BIT(25)
  44 #define FLEXCAN_MCR_FRZ_ACK             BIT(24)
  45 #define FLEXCAN_MCR_SUPV                BIT(23)
  46 #define FLEXCAN_MCR_SLF_WAK             BIT(22)
  47 #define FLEXCAN_MCR_WRN_EN              BIT(21)
  48 #define FLEXCAN_MCR_LPM_ACK             BIT(20)
  49 #define FLEXCAN_MCR_WAK_SRC             BIT(19)
  50 #define FLEXCAN_MCR_DOZE                BIT(18)
  51 #define FLEXCAN_MCR_SRX_DIS             BIT(17)
  52 #define FLEXCAN_MCR_IRMQ                BIT(16)
  53 #define FLEXCAN_MCR_LPRIO_EN            BIT(13)
  54 #define FLEXCAN_MCR_AEN                 BIT(12)
  55 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
  56 #define FLEXCAN_MCR_MAXMB(x)            ((x) & 0x7f)
  57 #define FLEXCAN_MCR_IDAM_A              (0x0 << 8)
  58 #define FLEXCAN_MCR_IDAM_B              (0x1 << 8)
  59 #define FLEXCAN_MCR_IDAM_C              (0x2 << 8)
  60 #define FLEXCAN_MCR_IDAM_D              (0x3 << 8)
  61
  62 /* FLEXCAN control register (CANCTRL) bits */
  63 #define FLEXCAN_CTRL_PRESDIV(x)         (((x) & 0xff) << 24)
  64 #define FLEXCAN_CTRL_RJW(x)             (((x) & 0x03) << 22)
  65 #define FLEXCAN_CTRL_PSEG1(x)           (((x) & 0x07) << 19)
  66 #define FLEXCAN_CTRL_PSEG2(x)           (((x) & 0x07) << 16)
  67 #define FLEXCAN_CTRL_BOFF_MSK           BIT(15)
  68 #define FLEXCAN_CTRL_ERR_MSK            BIT(14)
  69 #define FLEXCAN_CTRL_CLK_SRC            BIT(13)
  70 #define FLEXCAN_CTRL_LPB                BIT(12)
  71 #define FLEXCAN_CTRL_TWRN_MSK           BIT(11)
  72 #define FLEXCAN_CTRL_RWRN_MSK           BIT(10)
  73 #define FLEXCAN_CTRL_SMP                BIT(7)
  74 #define FLEXCAN_CTRL_BOFF_REC           BIT(6)
  75 #define FLEXCAN_CTRL_TSYN               BIT(5)
  76 #define FLEXCAN_CTRL_LBUF               BIT(4)
  77 #define FLEXCAN_CTRL_LOM                BIT(3)
  78 #define FLEXCAN_CTRL_PROPSEG(x)         ((x) & 0x07)
  79 #define FLEXCAN_CTRL_ERR_BUS            (FLEXCAN_CTRL_ERR_MSK)
  80 #define FLEXCAN_CTRL_ERR_STATE \
  81         (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
  82          FLEXCAN_CTRL_BOFF_MSK)
  83 #define FLEXCAN_CTRL_ERR_ALL \
  84         (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
  85
  86 /* FLEXCAN control register 2 (CTRL2) bits */
  87 #define FLEXCAN_CTRL2_ECRWRE            BIT(29)
  88 #define FLEXCAN_CTRL2_WRMFRZ            BIT(28)
  89 #define FLEXCAN_CTRL2_RFFN(x)           (((x) & 0x0f) << 24)
  90 #define FLEXCAN_CTRL2_TASD(x)           (((x) & 0x1f) << 19)
  91 #define FLEXCAN_CTRL2_MRP               BIT(18)
  92 #define FLEXCAN_CTRL2_RRS               BIT(17)
  93 #define FLEXCAN_CTRL2_EACEN             BIT(16)
  94
  95 /* FLEXCAN memory error control register (MECR) bits */
  96 #define FLEXCAN_MECR_ECRWRDIS           BIT(31)
  97 #define FLEXCAN_MECR_HANCEI_MSK         BIT(19)
  98 #define FLEXCAN_MECR_FANCEI_MSK         BIT(18)
  99 #define FLEXCAN_MECR_CEI_MSK            BIT(16)
 100 #define FLEXCAN_MECR_HAERRIE            BIT(15)
 101 #define FLEXCAN_MECR_FAERRIE            BIT(14)
 102 #define FLEXCAN_MECR_EXTERRIE           BIT(13)
 103 #define FLEXCAN_MECR_RERRDIS            BIT(9)
 104 #define FLEXCAN_MECR_ECCDIS             BIT(8)
 105 #define FLEXCAN_MECR_NCEFAFRZ           BIT(7)
 106
 107 /* FLEXCAN error and status register (ESR) bits */
 108 #define FLEXCAN_ESR_TWRN_INT            BIT(17)
 109 #define FLEXCAN_ESR_RWRN_INT            BIT(16)
 110 #define FLEXCAN_ESR_BIT1_ERR            BIT(15)
 111 #define FLEXCAN_ESR_BIT0_ERR            BIT(14)
 112 #define FLEXCAN_ESR_ACK_ERR             BIT(13)
 113 #define FLEXCAN_ESR_CRC_ERR             BIT(12)
 114 #define FLEXCAN_ESR_FRM_ERR             BIT(11)
 115 #define FLEXCAN_ESR_STF_ERR             BIT(10)
 116 #define FLEXCAN_ESR_TX_WRN              BIT(9)
 117 #define FLEXCAN_ESR_RX_WRN              BIT(8)
 118 #define FLEXCAN_ESR_IDLE                BIT(7)
 119 #define FLEXCAN_ESR_TXRX                BIT(6)
 120 #define FLEXCAN_EST_FLT_CONF_SHIFT      (4)
 121 #define FLEXCAN_ESR_FLT_CONF_MASK       (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
 122 #define FLEXCAN_ESR_FLT_CONF_ACTIVE     (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
 123 #define FLEXCAN_ESR_FLT_CONF_PASSIVE    (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
 124 #define FLEXCAN_ESR_BOFF_INT            BIT(2)
 125 #define FLEXCAN_ESR_ERR_INT             BIT(1)
 126 #define FLEXCAN_ESR_WAK_INT             BIT(0)
 127 #define FLEXCAN_ESR_ERR_BUS \
 128         (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
 129          FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
 130          FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
 131 #define FLEXCAN_ESR_ERR_STATE \
 132         (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
 133 #define FLEXCAN_ESR_ERR_ALL \
 134         (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
 135 #define FLEXCAN_ESR_ALL_INT \
 136         (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
 137          FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT | \
 138          FLEXCAN_ESR_WAK_INT)
 139
 140 /* FLEXCAN interrupt flag register (IFLAG) bits */
 141 /* Errata ERR005829 step7: Reserve first valid MB */
 142 #define FLEXCAN_TX_MB_RESERVED_OFF_FIFO         8
 143 #define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP    0
 144 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST       (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
 145 #define FLEXCAN_IFLAG_MB(x)             BIT_ULL(x)
 146 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW  BIT(7)
 147 #define FLEXCAN_IFLAG_RX_FIFO_WARN      BIT(6)
 148 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
 149
 150 /* FLEXCAN message buffers */
 151 #define FLEXCAN_MB_CODE_MASK            (0xf << 24)
 152 #define FLEXCAN_MB_CODE_RX_BUSY_BIT     (0x1 << 24)
 153 #define FLEXCAN_MB_CODE_RX_INACTIVE     (0x0 << 24)
 154 #define FLEXCAN_MB_CODE_RX_EMPTY        (0x4 << 24)
 155 #define FLEXCAN_MB_CODE_RX_FULL         (0x2 << 24)
 156 #define FLEXCAN_MB_CODE_RX_OVERRUN      (0x6 << 24)
 157 #define FLEXCAN_MB_CODE_RX_RANSWER      (0xa << 24)
 158
 159 #define FLEXCAN_MB_CODE_TX_INACTIVE     (0x8 << 24)
 160 #define FLEXCAN_MB_CODE_TX_ABORT        (0x9 << 24)
 161 #define FLEXCAN_MB_CODE_TX_DATA         (0xc << 24)
 162 #define FLEXCAN_MB_CODE_TX_TANSWER      (0xe << 24)
 163
 164 #define FLEXCAN_MB_CNT_SRR              BIT(22)
 165 #define FLEXCAN_MB_CNT_IDE              BIT(21)
 166 #define FLEXCAN_MB_CNT_RTR              BIT(20)
 167 #define FLEXCAN_MB_CNT_LENGTH(x)        (((x) & 0xf) << 16)
 168 #define FLEXCAN_MB_CNT_TIMESTAMP(x)     ((x) & 0xffff)
 169
 170 #define FLEXCAN_TIMEOUT_US              (250)
 171
 172 /* FLEXCAN hardware feature flags
 173  *
 174  * Below is some version info we got:
 175  *    SOC   Version   IP-Version  Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
 176  *                                Filter? connected?  Passive detection  ception in MB
 177  *   MX25  FlexCAN2  03.00.00.00     no        no        no       no        no
 178  *   MX28  FlexCAN2  03.00.04.00    yes       yes        no       no        no
 179  *   MX35  FlexCAN2  03.00.00.00     no        no        no       no        no
 180  *   MX53  FlexCAN2  03.00.00.00    yes        no        no       no        no
 181  *   MX6s  FlexCAN3  10.00.12.00    yes       yes        no       no       yes
 182  *   VF610 FlexCAN3  ?               no       yes        no      yes       yes?
 183  * LS1021A FlexCAN2  03.00.04.00     no       yes        no       no       yes
 184  *
 185  * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
 186  */
 187 #define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1) /* [TR]WRN_INT not connected */
 188 #define FLEXCAN_QUIRK_DISABLE_RXFG      BIT(2) /* Disable RX FIFO Global mask */
 189 #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS  BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
 190 #define FLEXCAN_QUIRK_DISABLE_MECR      BIT(4) /* Disable Memory error detection */
 191 #define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5) /* Use timestamp based offloading */
 192 #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6) /* No interrupt for error passive */
 193 #define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN        BIT(7) /* default to BE register access */
 194 #define FLEXCAN_QUIRK_SETUP_STOP_MODE           BIT(8) /* Setup stop mode to support wakeup */
 195
 196 /* Structure of the message buffer */
 197 struct flexcan_mb {
 198         u32 can_ctrl;
 199         u32 can_id;
 200         u32 data[];
 201 };
 202
 203 /* Structure of the hardware registers */
 204 struct flexcan_regs {
 205         u32 mcr;                /* 0x00 */
 206         u32 ctrl;               /* 0x04 - Not affected by Soft Reset */
 207         u32 timer;              /* 0x08 */
 208         u32 tcr;                /* 0x0c */
 209         u32 rxgmask;            /* 0x10 - Not affected by Soft Reset */
 210         u32 rx14mask;           /* 0x14 - Not affected by Soft Reset */
 211         u32 rx15mask;           /* 0x18 - Not affected by Soft Reset */
 212         u32 ecr;                /* 0x1c */
 213         u32 esr;                /* 0x20 */
 214         u32 imask2;             /* 0x24 */
 215         u32 imask1;             /* 0x28 */
 216         u32 iflag2;             /* 0x2c */
 217         u32 iflag1;             /* 0x30 */
 218         union {                 /* 0x34 */
 219                 u32 gfwr_mx28;  /* MX28, MX53 */
 220                 u32 ctrl2;      /* MX6, VF610 - Not affected by Soft Reset */
 221         };
 222         u32 esr2;               /* 0x38 */
 223         u32 imeur;              /* 0x3c */
 224         u32 lrfr;               /* 0x40 */
 225         u32 crcr;               /* 0x44 */
 226         u32 rxfgmask;           /* 0x48 */
 227         u32 rxfir;              /* 0x4c - Not affected by Soft Reset */
 228         u32 cbt;                /* 0x50 - Not affected by Soft Reset */
 229         u32 _reserved2;         /* 0x54 */
 230         u32 dbg1;               /* 0x58 */
 231         u32 dbg2;               /* 0x5c */
 232         u32 _reserved3[8];      /* 0x60 */
 233         u8 mb[2][512];          /* 0x80 - Not affected by Soft Reset */
 234         /* FIFO-mode:
 235          *                      MB
 236          * 0x080...0x08f        0       RX message buffer
 237          * 0x090...0x0df        1-5     reserved
 238          * 0x0e0...0x0ff        6-7     8 entry ID table
 239          *                              (mx25, mx28, mx35, mx53)
 240          * 0x0e0...0x2df        6-7..37 8..128 entry ID table
 241          *                              size conf'ed via ctrl2::RFFN
 242          *                              (mx6, vf610)
 243          */
 244         u32 _reserved4[256];    /* 0x480 */
 245         u32 rximr[64];          /* 0x880 - Not affected by Soft Reset */
 246         u32 _reserved5[24];     /* 0x980 */
 247         u32 gfwr_mx6;           /* 0x9e0 - MX6 */
 248         u32 _reserved6[63];     /* 0x9e4 */
 249         u32 mecr;               /* 0xae0 */
 250         u32 erriar;             /* 0xae4 */
 251         u32 erridpr;            /* 0xae8 */
 252         u32 errippr;            /* 0xaec */
 253         u32 rerrar;             /* 0xaf0 */
 254         u32 rerrdr;             /* 0xaf4 */
 255         u32 rerrsynr;           /* 0xaf8 */
 256         u32 errsr;              /* 0xafc */
 257         u32 _reserved7[64];     /* 0xb00 */
 258         u32 fdctrl;             /* 0xc00 - Not affected by Soft Reset */
 259         u32 fdcbt;              /* 0xc04 - Not affected by Soft Reset */
 260         u32 fdcrc;              /* 0xc08 */
 261 };
 262
 263 static_assert(sizeof(struct flexcan_regs) == 0x4 + 0xc08);
 264
 265 struct flexcan_devtype_data {
 266         u32 quirks;             /* quirks needed for different IP cores */
 267 };
 268
 269 struct flexcan_stop_mode {
 270         struct regmap *gpr;
 271         u8 req_gpr;
 272         u8 req_bit;
 273         u8 ack_gpr;
 274         u8 ack_bit;
 275 };
 276
 277 struct flexcan_priv {
 278         struct can_priv can;
 279         struct can_rx_offload offload;
 280         struct device *dev;
 281
 282         struct flexcan_regs __iomem *regs;
 283         struct flexcan_mb __iomem *tx_mb;
 284         struct flexcan_mb __iomem *tx_mb_reserved;
 285         u8 tx_mb_idx;
 286         u8 mb_count;
 287         u8 mb_size;
 288         u8 clk_src;     /* clock source of CAN Protocol Engine */
 289
 290         u64 rx_mask;
 291         u64 tx_mask;
 292         u32 reg_ctrl_default;
 293
 294         struct clk *clk_ipg;
 295         struct clk *clk_per;
 296         const struct flexcan_devtype_data *devtype_data;
 297         struct regulator *reg_xceiver;
 298         struct flexcan_stop_mode stm;
 299
 300         /* Read and Write APIs */
 301         u32 (*read)(void __iomem *addr);
 302         void (*write)(u32 val, void __iomem *addr);
 303 };
 304
 305 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
 306         .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 307                 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 308                 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN,
 309 };
 310
 311 static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
 312         .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 313                 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 314 };
 315
 316 static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
 317         .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 318 };
 319
 320 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
 321         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 322                 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 323                 FLEXCAN_QUIRK_SETUP_STOP_MODE,
 324 };
 325
 326 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
 327         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 328                 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
 329                 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 330 };
 331
 332 static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
 333         .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 334                 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 335                 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
 336 };
 337
 338 static const struct can_bittiming_const flexcan_bittiming_const = {
 339         .name = DRV_NAME,
 340         .tseg1_min = 4,
 341         .tseg1_max = 16,
 342         .tseg2_min = 2,
 343         .tseg2_max = 8,
 344         .sjw_max = 4,
 345         .brp_min = 1,
 346         .brp_max = 256,
 347         .brp_inc = 1,
 348 };
 349
 350 /* FlexCAN module is essentially modelled as a little-endian IP in most
 351  * SoCs, i.e the registers as well as the message buffer areas are
 352  * implemented in a little-endian fashion.
 353  *
 354  * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
 355  * module in a big-endian fashion (i.e the registers as well as the
 356  * message buffer areas are implemented in a big-endian way).
 357  *
 358  * In addition, the FlexCAN module can be found on SoCs having ARM or
 359  * PPC cores. So, we need to abstract off the register read/write
 360  * functions, ensuring that these cater to all the combinations of module
 361  * endianness and underlying CPU endianness.
 362  */
 363 static inline u32 flexcan_read_be(void __iomem *addr)
 364 {
 365         return ioread32be(addr);
 366 }
 367
 368 static inline void flexcan_write_be(u32 val, void __iomem *addr)
 369 {
 370         iowrite32be(val, addr);
 371 }
 372
 373 static inline u32 flexcan_read_le(void __iomem *addr)
 374 {
 375         return ioread32(addr);
 376 }
 377
 378 static inline void flexcan_write_le(u32 val, void __iomem *addr)
 379 {
 380         iowrite32(val, addr);
 381 }
 382
 383 static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
 384                                                  u8 mb_index)
 385 {
 386         u8 bank_size;
 387         bool bank;
 388
 389         if (WARN_ON(mb_index >= priv->mb_count))
 390                 return NULL;
 391
 392         bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;
 393
 394         bank = mb_index >= bank_size;
 395         if (bank)
 396                 mb_index -= bank_size;
 397
 398         return (struct flexcan_mb __iomem *)
 399                 (&priv->regs->mb[bank][priv->mb_size * mb_index]);
 400 }
 401
 402 static int flexcan_low_power_enter_ack(struct flexcan_priv *priv)
 403 {
 404         struct flexcan_regs __iomem *regs = priv->regs;
 405         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 406
 407         while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 408                 udelay(10);
 409
 410         if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 411                 return -ETIMEDOUT;
 412
 413         return 0;
 414 }
 415
 416 static int flexcan_low_power_exit_ack(struct flexcan_priv *priv)
 417 {
 418         struct flexcan_regs __iomem *regs = priv->regs;
 419         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 420
 421         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 422                 udelay(10);
 423
 424         if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
 425                 return -ETIMEDOUT;
 426
 427         return 0;
 428 }
 429
 430 static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
 431 {
 432         struct flexcan_regs __iomem *regs = priv->regs;
 433         u32 reg_mcr;
 434
 435         reg_mcr = priv->read(&regs->mcr);
 436
 437         if (enable)
 438                 reg_mcr |= FLEXCAN_MCR_WAK_MSK;
 439         else
 440                 reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;
 441
 442         priv->write(reg_mcr, &regs->mcr);
 443 }
 444
 445 static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv)
 446 {
 447         struct flexcan_regs __iomem *regs = priv->regs;
 448         u32 reg_mcr;
 449
 450         reg_mcr = priv->read(&regs->mcr);
 451         reg_mcr |= FLEXCAN_MCR_SLF_WAK;
 452         priv->write(reg_mcr, &regs->mcr);
 453
 454         /* enable stop request */
 455         regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
 456                            1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
 457
 458         return flexcan_low_power_enter_ack(priv);
 459 }
 460
 461 static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
 462 {
 463         struct flexcan_regs __iomem *regs = priv->regs;
 464         u32 reg_mcr;
 465
 466         /* remove stop request */
 467         regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
 468                            1 << priv->stm.req_bit, 0);
 469
 470         reg_mcr = priv->read(&regs->mcr);
 471         reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
 472         priv->write(reg_mcr, &regs->mcr);
 473
 474         return flexcan_low_power_exit_ack(priv);
 475 }
 476
 477 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
 478 {
 479         struct flexcan_regs __iomem *regs = priv->regs;
 480         u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
 481
 482         priv->write(reg_ctrl, &regs->ctrl);
 483 }
 484
 485 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
 486 {
 487         struct flexcan_regs __iomem *regs = priv->regs;
 488         u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
 489
 490         priv->write(reg_ctrl, &regs->ctrl);
 491 }
 492
 493 static int flexcan_clks_enable(const struct flexcan_priv *priv)
 494 {
 495         int err;
 496
 497         err = clk_prepare_enable(priv->clk_ipg);
 498         if (err)
 499                 return err;
 500
 501         err = clk_prepare_enable(priv->clk_per);
 502         if (err)
 503                 clk_disable_unprepare(priv->clk_ipg);
 504
 505         return err;
 506 }
 507
 508 static void flexcan_clks_disable(const struct flexcan_priv *priv)
 509 {
 510         clk_disable_unprepare(priv->clk_per);
 511         clk_disable_unprepare(priv->clk_ipg);
 512 }
 513
 514 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
 515 {
 516         if (!priv->reg_xceiver)
 517                 return 0;
 518
 519         return regulator_enable(priv->reg_xceiver);
 520 }
 521
 522 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
 523 {
 524         if (!priv->reg_xceiver)
 525                 return 0;
 526
 527         return regulator_disable(priv->reg_xceiver);
 528 }
 529
 530 static int flexcan_chip_enable(struct flexcan_priv *priv)
 531 {
 532         struct flexcan_regs __iomem *regs = priv->regs;
 533         u32 reg;
 534
 535         reg = priv->read(&regs->mcr);
 536         reg &= ~FLEXCAN_MCR_MDIS;
 537         priv->write(reg, &regs->mcr);
 538
 539         return flexcan_low_power_exit_ack(priv);
 540 }
 541
 542 static int flexcan_chip_disable(struct flexcan_priv *priv)
 543 {
 544         struct flexcan_regs __iomem *regs = priv->regs;
 545         u32 reg;
 546
 547         reg = priv->read(&regs->mcr);
 548         reg |= FLEXCAN_MCR_MDIS;
 549         priv->write(reg, &regs->mcr);
 550
 551         return flexcan_low_power_enter_ack(priv);
 552 }
 553
 554 static int flexcan_chip_freeze(struct flexcan_priv *priv)
 555 {
 556         struct flexcan_regs __iomem *regs = priv->regs;
 557         unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
 558         u32 reg;
 559
 560         reg = priv->read(&regs->mcr);
 561         reg |= FLEXCAN_MCR_HALT;
 562         priv->write(reg, &regs->mcr);
 563
 564         while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 565                 udelay(100);
 566
 567         if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 568                 return -ETIMEDOUT;
 569
 570         return 0;
 571 }
 572
 573 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
 574 {
 575         struct flexcan_regs __iomem *regs = priv->regs;
 576         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 577         u32 reg;
 578
 579         reg = priv->read(&regs->mcr);
 580         reg &= ~FLEXCAN_MCR_HALT;
 581         priv->write(reg, &regs->mcr);
 582
 583         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 584                 udelay(10);
 585
 586         if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
 587                 return -ETIMEDOUT;
 588
 589         return 0;
 590 }
 591
 592 static int flexcan_chip_softreset(struct flexcan_priv *priv)
 593 {
 594         struct flexcan_regs __iomem *regs = priv->regs;
 595         unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 596
 597         priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
 598         while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
 599                 udelay(10);
 600
 601         if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
 602                 return -ETIMEDOUT;
 603
 604         return 0;
 605 }
 606
 607 static int __flexcan_get_berr_counter(const struct net_device *dev,
 608                                       struct can_berr_counter *bec)
 609 {
 610         const struct flexcan_priv *priv = netdev_priv(dev);
 611         struct flexcan_regs __iomem *regs = priv->regs;
 612         u32 reg = priv->read(&regs->ecr);
 613
 614         bec->txerr = (reg >> 0) & 0xff;
 615         bec->rxerr = (reg >> 8) & 0xff;
 616
 617         return 0;
 618 }
 619
 620 static int flexcan_get_berr_counter(const struct net_device *dev,
 621                                     struct can_berr_counter *bec)
 622 {
 623         const struct flexcan_priv *priv = netdev_priv(dev);
 624         int err;
 625
 626         err = pm_runtime_get_sync(priv->dev);
 627         if (err < 0)
 628                 return err;
 629
 630         err = __flexcan_get_berr_counter(dev, bec);
 631
 632         pm_runtime_put(priv->dev);
 633
 634         return err;
 635 }
 636
 637 static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
 638 {
 639         const struct flexcan_priv *priv = netdev_priv(dev);
 640         struct can_frame *cf = (struct can_frame *)skb->data;
 641         u32 can_id;
 642         u32 data;
 643         u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
 644         int i;
 645
 646         if (can_dropped_invalid_skb(dev, skb))
 647                 return NETDEV_TX_OK;
 648
 649         netif_stop_queue(dev);
 650
 651         if (cf->can_id & CAN_EFF_FLAG) {
 652                 can_id = cf->can_id & CAN_EFF_MASK;
 653                 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
 654         } else {
 655                 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
 656         }
 657
 658         if (cf->can_id & CAN_RTR_FLAG)
 659                 ctrl |= FLEXCAN_MB_CNT_RTR;
 660
 661         for (i = 0; i < cf->can_dlc; i += sizeof(u32)) {
 662                 data = be32_to_cpup((__be32 *)&cf->data[i]);
 663                 priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
 664         }
 665
 666         can_put_echo_skb(skb, dev, 0);
 667
 668         priv->write(can_id, &priv->tx_mb->can_id);
 669         priv->write(ctrl, &priv->tx_mb->can_ctrl);
 670
 671         /* Errata ERR005829 step8:
 672          * Write twice INACTIVE(0x8) code to first MB.
 673          */
 674         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 675                     &priv->tx_mb_reserved->can_ctrl);
 676         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 677                     &priv->tx_mb_reserved->can_ctrl);
 678
 679         return NETDEV_TX_OK;
 680 }
 681
 682 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
 683 {
 684         struct flexcan_priv *priv = netdev_priv(dev);
 685         struct flexcan_regs __iomem *regs = priv->regs;
 686         struct sk_buff *skb;
 687         struct can_frame *cf;
 688         bool rx_errors = false, tx_errors = false;
 689         u32 timestamp;
 690         int err;
 691
 692         timestamp = priv->read(&regs->timer) << 16;
 693
 694         skb = alloc_can_err_skb(dev, &cf);
 695         if (unlikely(!skb))
 696                 return;
 697
 698         cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
 699
 700         if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
 701                 netdev_dbg(dev, "BIT1_ERR irq\n");
 702                 cf->data[2] |= CAN_ERR_PROT_BIT1;
 703                 tx_errors = true;
 704         }
 705         if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
 706                 netdev_dbg(dev, "BIT0_ERR irq\n");
 707                 cf->data[2] |= CAN_ERR_PROT_BIT0;
 708                 tx_errors = true;
 709         }
 710         if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
 711                 netdev_dbg(dev, "ACK_ERR irq\n");
 712                 cf->can_id |= CAN_ERR_ACK;
 713                 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
 714                 tx_errors = true;
 715         }
 716         if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
 717                 netdev_dbg(dev, "CRC_ERR irq\n");
 718                 cf->data[2] |= CAN_ERR_PROT_BIT;
 719                 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
 720                 rx_errors = true;
 721         }
 722         if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
 723                 netdev_dbg(dev, "FRM_ERR irq\n");
 724                 cf->data[2] |= CAN_ERR_PROT_FORM;
 725                 rx_errors = true;
 726         }
 727         if (reg_esr & FLEXCAN_ESR_STF_ERR) {
 728                 netdev_dbg(dev, "STF_ERR irq\n");
 729                 cf->data[2] |= CAN_ERR_PROT_STUFF;
 730                 rx_errors = true;
 731         }
 732
 733         priv->can.can_stats.bus_error++;
 734         if (rx_errors)
 735                 dev->stats.rx_errors++;
 736         if (tx_errors)
 737                 dev->stats.tx_errors++;
 738
 739         err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
 740         if (err)
 741                 dev->stats.rx_fifo_errors++;
 742 }
 743
 744 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
 745 {
 746         struct flexcan_priv *priv = netdev_priv(dev);
 747         struct flexcan_regs __iomem *regs = priv->regs;
 748         struct sk_buff *skb;
 749         struct can_frame *cf;
 750         enum can_state new_state, rx_state, tx_state;
 751         int flt;
 752         struct can_berr_counter bec;
 753         u32 timestamp;
 754         int err;
 755
 756         flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
 757         if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
 758                 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
 759                         CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 760                 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
 761                         CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 762                 new_state = max(tx_state, rx_state);
 763         } else {
 764                 __flexcan_get_berr_counter(dev, &bec);
 765                 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
 766                         CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
 767                 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
 768                 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
 769         }
 770
 771         /* state hasn't changed */
 772         if (likely(new_state == priv->can.state))
 773                 return;
 774
 775         timestamp = priv->read(&regs->timer) << 16;
 776
 777         skb = alloc_can_err_skb(dev, &cf);
 778         if (unlikely(!skb))
 779                 return;
 780
 781         can_change_state(dev, cf, tx_state, rx_state);
 782
 783         if (unlikely(new_state == CAN_STATE_BUS_OFF))
 784                 can_bus_off(dev);
 785
 786         err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
 787         if (err)
 788                 dev->stats.rx_fifo_errors++;
 789 }
 790
 791 static inline u64 flexcan_read64_mask(struct flexcan_priv *priv, void __iomem *addr, u64 mask)
 792 {
 793         u64 reg = 0;
 794
 795         if (upper_32_bits(mask))
 796                 reg = (u64)priv->read(addr - 4) << 32;
 797         if (lower_32_bits(mask))
 798                 reg |= priv->read(addr);
 799
 800         return reg & mask;
 801 }
 802
 803 static inline void flexcan_write64(struct flexcan_priv *priv, u64 val, void __iomem *addr)
 804 {
 805         if (upper_32_bits(val))
 806                 priv->write(upper_32_bits(val), addr - 4);
 807         if (lower_32_bits(val))
 808                 priv->write(lower_32_bits(val), addr);
 809 }
 810
 811 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
 812 {
 813         return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask);
 814 }
 815
 816 static inline u64 flexcan_read_reg_iflag_tx(struct flexcan_priv *priv)
 817 {
 818         return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask);
 819 }
 820
 821 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
 822 {
 823         return container_of(offload, struct flexcan_priv, offload);
 824 }
 825
 826 static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload,
 827                                             unsigned int n, u32 *timestamp,
 828                                             bool drop)
 829 {
 830         struct flexcan_priv *priv = rx_offload_to_priv(offload);
 831         struct flexcan_regs __iomem *regs = priv->regs;
 832         struct flexcan_mb __iomem *mb;
 833         struct sk_buff *skb;
 834         struct can_frame *cf;
 835         u32 reg_ctrl, reg_id, reg_iflag1;
 836         int i;
 837
 838         if (unlikely(drop)) {
 839                 skb = ERR_PTR(-ENOBUFS);
 840                 goto mark_as_read;
 841         }
 842
 843         mb = flexcan_get_mb(priv, n);
 844
 845         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 846                 u32 code;
 847
 848                 do {
 849                         reg_ctrl = priv->read(&mb->can_ctrl);
 850                 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
 851
 852                 /* is this MB empty? */
 853                 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
 854                 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
 855                     (code != FLEXCAN_MB_CODE_RX_OVERRUN))
 856                         return NULL;
 857
 858                 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
 859                         /* This MB was overrun, we lost data */
 860                         offload->dev->stats.rx_over_errors++;
 861                         offload->dev->stats.rx_errors++;
 862                 }
 863         } else {
 864                 reg_iflag1 = priv->read(&regs->iflag1);
 865                 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
 866                         return NULL;
 867
 868                 reg_ctrl = priv->read(&mb->can_ctrl);
 869         }
 870
 871         skb = alloc_can_skb(offload->dev, &cf);
 872         if (!skb) {
 873                 skb = ERR_PTR(-ENOMEM);
 874                 goto mark_as_read;
 875         }
 876
 877         /* increase timstamp to full 32 bit */
 878         *timestamp = reg_ctrl << 16;
 879
 880         reg_id = priv->read(&mb->can_id);
 881         if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
 882                 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
 883         else
 884                 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
 885
 886         if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
 887                 cf->can_id |= CAN_RTR_FLAG;
 888         cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
 889
 890         for (i = 0; i < cf->can_dlc; i += sizeof(u32)) {
 891                 __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
 892                 *(__be32 *)(cf->data + i) = data;
 893         }
 894
 895  mark_as_read:
 896         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
 897                 flexcan_write64(priv, FLEXCAN_IFLAG_MB(n), &regs->iflag1);
 898         else
 899                 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
 900
 901         /* Read the Free Running Timer. It is optional but recommended
 902          * to unlock Mailbox as soon as possible and make it available
 903          * for reception.
 904          */
 905         priv->read(&regs->timer);
 906
 907         return skb;
 908 }
 909
 910 static irqreturn_t flexcan_irq(int irq, void *dev_id)
 911 {
 912         struct net_device *dev = dev_id;
 913         struct net_device_stats *stats = &dev->stats;
 914         struct flexcan_priv *priv = netdev_priv(dev);
 915         struct flexcan_regs __iomem *regs = priv->regs;
 916         irqreturn_t handled = IRQ_NONE;
 917         u64 reg_iflag_tx;
 918         u32 reg_esr;
 919         enum can_state last_state = priv->can.state;
 920
 921         /* reception interrupt */
 922         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 923                 u64 reg_iflag_rx;
 924                 int ret;
 925
 926                 while ((reg_iflag_rx = flexcan_read_reg_iflag_rx(priv))) {
 927                         handled = IRQ_HANDLED;
 928                         ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
 929                                                                    reg_iflag_rx);
 930                         if (!ret)
 931                                 break;
 932                 }
 933         } else {
 934                 u32 reg_iflag1;
 935
 936                 reg_iflag1 = priv->read(&regs->iflag1);
 937                 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
 938                         handled = IRQ_HANDLED;
 939                         can_rx_offload_irq_offload_fifo(&priv->offload);
 940                 }
 941
 942                 /* FIFO overflow interrupt */
 943                 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
 944                         handled = IRQ_HANDLED;
 945                         priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
 946                                     &regs->iflag1);
 947                         dev->stats.rx_over_errors++;
 948                         dev->stats.rx_errors++;
 949                 }
 950         }
 951
 952         reg_iflag_tx = flexcan_read_reg_iflag_tx(priv);
 953
 954         /* transmission complete interrupt */
 955         if (reg_iflag_tx & priv->tx_mask) {
 956                 u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
 957
 958                 handled = IRQ_HANDLED;
 959                 stats->tx_bytes += can_rx_offload_get_echo_skb(&priv->offload,
 960                                                                0, reg_ctrl << 16);
 961                 stats->tx_packets++;
 962                 can_led_event(dev, CAN_LED_EVENT_TX);
 963
 964                 /* after sending a RTR frame MB is in RX mode */
 965                 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 966                             &priv->tx_mb->can_ctrl);
 967                 flexcan_write64(priv, priv->tx_mask, &regs->iflag1);
 968                 netif_wake_queue(dev);
 969         }
 970
 971         reg_esr = priv->read(&regs->esr);
 972
 973         /* ACK all bus error and state change IRQ sources */
 974         if (reg_esr & FLEXCAN_ESR_ALL_INT) {
 975                 handled = IRQ_HANDLED;
 976                 priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
 977         }
 978
 979         /* state change interrupt or broken error state quirk fix is enabled */
 980         if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
 981             (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 982                                            FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
 983                 flexcan_irq_state(dev, reg_esr);
 984
 985         /* bus error IRQ - handle if bus error reporting is activated */
 986         if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
 987             (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
 988                 flexcan_irq_bus_err(dev, reg_esr);
 989
 990         /* availability of error interrupt among state transitions in case
 991          * bus error reporting is de-activated and
 992          * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
 993          *  +--------------------------------------------------------------+
 994          *  | +----------------------------------------------+ [stopped /  |
 995          *  | |                                              |  sleeping] -+
 996          *  +-+-> active <-> warning <-> passive -> bus off -+
 997          *        ___________^^^^^^^^^^^^_______________________________
 998          *        disabled(1)  enabled             disabled
 999          *
1000          * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
1001          */
1002         if ((last_state != priv->can.state) &&
1003             (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
1004             !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
1005                 switch (priv->can.state) {
1006                 case CAN_STATE_ERROR_ACTIVE:
1007                         if (priv->devtype_data->quirks &
1008                             FLEXCAN_QUIRK_BROKEN_WERR_STATE)
1009                                 flexcan_error_irq_enable(priv);
1010                         else
1011                                 flexcan_error_irq_disable(priv);
1012                         break;
1013
1014                 case CAN_STATE_ERROR_WARNING:
1015                         flexcan_error_irq_enable(priv);
1016                         break;
1017
1018                 case CAN_STATE_ERROR_PASSIVE:
1019                 case CAN_STATE_BUS_OFF:
1020                         flexcan_error_irq_disable(priv);
1021                         break;
1022
1023                 default:
1024                         break;
1025                 }
1026         }
1027
1028         return handled;
1029 }
1030
1031 static void flexcan_set_bittiming(struct net_device *dev)
1032 {
1033         const struct flexcan_priv *priv = netdev_priv(dev);
1034         const struct can_bittiming *bt = &priv->can.bittiming;
1035         struct flexcan_regs __iomem *regs = priv->regs;
1036         u32 reg;
1037
1038         reg = priv->read(&regs->ctrl);
1039         reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
1040                  FLEXCAN_CTRL_RJW(0x3) |
1041                  FLEXCAN_CTRL_PSEG1(0x7) |
1042                  FLEXCAN_CTRL_PSEG2(0x7) |
1043                  FLEXCAN_CTRL_PROPSEG(0x7) |
1044                  FLEXCAN_CTRL_LPB |
1045                  FLEXCAN_CTRL_SMP |
1046                  FLEXCAN_CTRL_LOM);
1047
1048         reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
1049                 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
1050                 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
1051                 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
1052                 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
1053
1054         if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1055                 reg |= FLEXCAN_CTRL_LPB;
1056         if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1057                 reg |= FLEXCAN_CTRL_LOM;
1058         if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
1059                 reg |= FLEXCAN_CTRL_SMP;
1060
1061         netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1062         priv->write(reg, &regs->ctrl);
1063
1064         /* print chip status */
1065         netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
1066                    priv->read(&regs->mcr), priv->read(&regs->ctrl));
1067 }
1068
1069 /* flexcan_chip_start
1070  *
1071  * this functions is entered with clocks enabled
1072  *
1073  */
1074 static int flexcan_chip_start(struct net_device *dev)
1075 {
1076         struct flexcan_priv *priv = netdev_priv(dev);
1077         struct flexcan_regs __iomem *regs = priv->regs;
1078         u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
1079         u64 reg_imask;
1080         int err, i;
1081         struct flexcan_mb __iomem *mb;
1082
1083         /* enable module */
1084         err = flexcan_chip_enable(priv);
1085         if (err)
1086                 return err;
1087
1088         /* soft reset */
1089         err = flexcan_chip_softreset(priv);
1090         if (err)
1091                 goto out_chip_disable;
1092
1093         flexcan_set_bittiming(dev);
1094
1095         /* MCR
1096          *
1097          * enable freeze
1098          * halt now
1099          * only supervisor access
1100          * enable warning int
1101          * enable individual RX masking
1102          * choose format C
1103          * set max mailbox number
1104          */
1105         reg_mcr = priv->read(&regs->mcr);
1106         reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
1107         reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
1108                 FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ | FLEXCAN_MCR_IDAM_C |
1109                 FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
1110
1111         /* MCR
1112          *
1113          * FIFO:
1114          * - disable for timestamp mode
1115          * - enable for FIFO mode
1116          */
1117         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1118                 reg_mcr &= ~FLEXCAN_MCR_FEN;
1119         else
1120                 reg_mcr |= FLEXCAN_MCR_FEN;
1121
1122         /* MCR
1123          *
1124          * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be
1125          *       asserted because this will impede the self reception
1126          *       of a transmitted message. This is not documented in
1127          *       earlier versions of flexcan block guide.
1128          *
1129          * Self Reception:
1130          * - enable Self Reception for loopback mode
1131          *   (by clearing "Self Reception Disable" bit)
1132          * - disable for normal operation
1133          */
1134         if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1135                 reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
1136         else
1137                 reg_mcr |= FLEXCAN_MCR_SRX_DIS;
1138
1139         netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
1140         priv->write(reg_mcr, &regs->mcr);
1141
1142         /* CTRL
1143          *
1144          * disable timer sync feature
1145          *
1146          * disable auto busoff recovery
1147          * transmit lowest buffer first
1148          *
1149          * enable tx and rx warning interrupt
1150          * enable bus off interrupt
1151          * (== FLEXCAN_CTRL_ERR_STATE)
1152          */
1153         reg_ctrl = priv->read(&regs->ctrl);
1154         reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
1155         reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
1156                 FLEXCAN_CTRL_ERR_STATE;
1157
1158         /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
1159          * on most Flexcan cores, too. Otherwise we don't get
1160          * any error warning or passive interrupts.
1161          */
1162         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
1163             priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
1164                 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
1165         else
1166                 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
1167
1168         /* save for later use */
1169         priv->reg_ctrl_default = reg_ctrl;
1170         /* leave interrupts disabled for now */
1171         reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1172         netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1173         priv->write(reg_ctrl, &regs->ctrl);
1174
1175         if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1176                 reg_ctrl2 = priv->read(&regs->ctrl2);
1177                 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1178                 priv->write(reg_ctrl2, &regs->ctrl2);
1179         }
1180
1181         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1182                 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1183                         mb = flexcan_get_mb(priv, i);
1184                         priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1185                                     &mb->can_ctrl);
1186                 }
1187         } else {
1188                 /* clear and invalidate unused mailboxes first */
1189                 for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i < priv->mb_count; i++) {
1190                         mb = flexcan_get_mb(priv, i);
1191                         priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1192                                     &mb->can_ctrl);
1193                 }
1194         }
1195
1196         /* Errata ERR005829: mark first TX mailbox as INACTIVE */
1197         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1198                     &priv->tx_mb_reserved->can_ctrl);
1199
1200         /* mark TX mailbox as INACTIVE */
1201         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1202                     &priv->tx_mb->can_ctrl);
1203
1204         /* acceptance mask/acceptance code (accept everything) */
1205         priv->write(0x0, &regs->rxgmask);
1206         priv->write(0x0, &regs->rx14mask);
1207         priv->write(0x0, &regs->rx15mask);
1208
1209         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1210                 priv->write(0x0, &regs->rxfgmask);
1211
1212         /* clear acceptance filters */
1213         for (i = 0; i < priv->mb_count; i++)
1214                 priv->write(0, &regs->rximr[i]);
1215
1216         /* On Vybrid, disable memory error detection interrupts
1217          * and freeze mode.
1218          * This also works around errata e5295 which generates
1219          * false positive memory errors and put the device in
1220          * freeze mode.
1221          */
1222         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1223                 /* Follow the protocol as described in "Detection
1224                  * and Correction of Memory Errors" to write to
1225                  * MECR register
1226                  */
1227                 reg_ctrl2 = priv->read(&regs->ctrl2);
1228                 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1229                 priv->write(reg_ctrl2, &regs->ctrl2);
1230
1231                 reg_mecr = priv->read(&regs->mecr);
1232                 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1233                 priv->write(reg_mecr, &regs->mecr);
1234                 reg_mecr |= FLEXCAN_MECR_ECCDIS;
1235                 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1236                               FLEXCAN_MECR_FANCEI_MSK);
1237                 priv->write(reg_mecr, &regs->mecr);
1238         }
1239
1240         err = flexcan_transceiver_enable(priv);
1241         if (err)
1242                 goto out_chip_disable;
1243
1244         /* synchronize with the can bus */
1245         err = flexcan_chip_unfreeze(priv);
1246         if (err)
1247                 goto out_transceiver_disable;
1248
1249         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1250
1251         /* enable interrupts atomically */
1252         disable_irq(dev->irq);
1253         priv->write(priv->reg_ctrl_default, &regs->ctrl);
1254         reg_imask = priv->rx_mask | priv->tx_mask;
1255         priv->write(upper_32_bits(reg_imask), &regs->imask2);
1256         priv->write(lower_32_bits(reg_imask), &regs->imask1);
1257         enable_irq(dev->irq);
1258
1259         /* print chip status */
1260         netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1261                    priv->read(&regs->mcr), priv->read(&regs->ctrl));
1262
1263         return 0;
1264
1265  out_transceiver_disable:
1266         flexcan_transceiver_disable(priv);
1267  out_chip_disable:
1268         flexcan_chip_disable(priv);
1269         return err;
1270 }
1271
1272 /* flexcan_chip_stop
1273  *
1274  * this functions is entered with clocks enabled
1275  */
1276 static void flexcan_chip_stop(struct net_device *dev)
1277 {
1278         struct flexcan_priv *priv = netdev_priv(dev);
1279         struct flexcan_regs __iomem *regs = priv->regs;
1280
1281         /* freeze + disable module */
1282         flexcan_chip_freeze(priv);
1283         flexcan_chip_disable(priv);
1284
1285         /* Disable all interrupts */
1286         priv->write(0, &regs->imask2);
1287         priv->write(0, &regs->imask1);
1288         priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1289                     &regs->ctrl);
1290
1291         flexcan_transceiver_disable(priv);
1292         priv->can.state = CAN_STATE_STOPPED;
1293 }
1294
1295 static int flexcan_open(struct net_device *dev)
1296 {
1297         struct flexcan_priv *priv = netdev_priv(dev);
1298         int err;
1299
1300         err = pm_runtime_get_sync(priv->dev);
1301         if (err < 0)
1302                 return err;
1303
1304         err = open_candev(dev);
1305         if (err)
1306                 goto out_runtime_put;
1307
1308         err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1309         if (err)
1310                 goto out_close;
1311
1312         priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
1313         priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
1314                          (sizeof(priv->regs->mb[1]) / priv->mb_size);
1315
1316         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1317                 priv->tx_mb_reserved =
1318                         flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP);
1319         else
1320                 priv->tx_mb_reserved =
1321                         flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_FIFO);
1322         priv->tx_mb_idx = priv->mb_count - 1;
1323         priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
1324         priv->tx_mask = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1325
1326         priv->offload.mailbox_read = flexcan_mailbox_read;
1327
1328         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1329                 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1330                 priv->offload.mb_last = priv->mb_count - 2;
1331
1332                 priv->rx_mask = GENMASK_ULL(priv->offload.mb_last,
1333                                             priv->offload.mb_first);
1334                 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1335         } else {
1336                 priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1337                         FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1338                 err = can_rx_offload_add_fifo(dev, &priv->offload,
1339                                               FLEXCAN_NAPI_WEIGHT);
1340         }
1341         if (err)
1342                 goto out_free_irq;
1343
1344         /* start chip and queuing */
1345         err = flexcan_chip_start(dev);
1346         if (err)
1347                 goto out_offload_del;
1348
1349         can_led_event(dev, CAN_LED_EVENT_OPEN);
1350
1351         can_rx_offload_enable(&priv->offload);
1352         netif_start_queue(dev);
1353
1354         return 0;
1355
1356  out_offload_del:
1357         can_rx_offload_del(&priv->offload);
1358  out_free_irq:
1359         free_irq(dev->irq, dev);
1360  out_close:
1361         close_candev(dev);
1362  out_runtime_put:
1363         pm_runtime_put(priv->dev);
1364
1365         return err;
1366 }
1367
1368 static int flexcan_close(struct net_device *dev)
1369 {
1370         struct flexcan_priv *priv = netdev_priv(dev);
1371
1372         netif_stop_queue(dev);
1373         can_rx_offload_disable(&priv->offload);
1374         flexcan_chip_stop(dev);
1375
1376         can_rx_offload_del(&priv->offload);
1377         free_irq(dev->irq, dev);
1378
1379         close_candev(dev);
1380         pm_runtime_put(priv->dev);
1381
1382         can_led_event(dev, CAN_LED_EVENT_STOP);
1383
1384         return 0;
1385 }
1386
1387 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1388 {
1389         int err;
1390
1391         switch (mode) {
1392         case CAN_MODE_START:
1393                 err = flexcan_chip_start(dev);
1394                 if (err)
1395                         return err;
1396
1397                 netif_wake_queue(dev);
1398                 break;
1399
1400         default:
1401                 return -EOPNOTSUPP;
1402         }
1403
1404         return 0;
1405 }
1406
1407 static const struct net_device_ops flexcan_netdev_ops = {
1408         .ndo_open       = flexcan_open,
1409         .ndo_stop       = flexcan_close,
1410         .ndo_start_xmit = flexcan_start_xmit,
1411         .ndo_change_mtu = can_change_mtu,
1412 };
1413
1414 static int register_flexcandev(struct net_device *dev)
1415 {
1416         struct flexcan_priv *priv = netdev_priv(dev);
1417         struct flexcan_regs __iomem *regs = priv->regs;
1418         u32 reg, err;
1419
1420         err = flexcan_clks_enable(priv);
1421         if (err)
1422                 return err;
1423
1424         /* select "bus clock", chip must be disabled */
1425         err = flexcan_chip_disable(priv);
1426         if (err)
1427                 goto out_clks_disable;
1428
1429         reg = priv->read(&regs->ctrl);
1430         if (priv->clk_src)
1431                 reg |= FLEXCAN_CTRL_CLK_SRC;
1432         else
1433                 reg &= ~FLEXCAN_CTRL_CLK_SRC;
1434         priv->write(reg, &regs->ctrl);
1435
1436         err = flexcan_chip_enable(priv);
1437         if (err)
1438                 goto out_chip_disable;
1439
1440         /* set freeze, halt and activate FIFO, restrict register access */
1441         reg = priv->read(&regs->mcr);
1442         reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1443                 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1444         priv->write(reg, &regs->mcr);
1445
1446         /* Currently we only support newer versions of this core
1447          * featuring a RX hardware FIFO (although this driver doesn't
1448          * make use of it on some cores). Older cores, found on some
1449          * Coldfire derivates are not tested.
1450          */
1451         reg = priv->read(&regs->mcr);
1452         if (!(reg & FLEXCAN_MCR_FEN)) {
1453                 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1454                 err = -ENODEV;
1455                 goto out_chip_disable;
1456         }
1457
1458         err = register_candev(dev);
1459         if (err)
1460                 goto out_chip_disable;
1461
1462         /* Disable core and let pm_runtime_put() disable the clocks.
1463          * If CONFIG_PM is not enabled, the clocks will stay powered.
1464          */
1465         flexcan_chip_disable(priv);
1466         pm_runtime_put(priv->dev);
1467
1468         return 0;
1469
1470  out_chip_disable:
1471         flexcan_chip_disable(priv);
1472  out_clks_disable:
1473         flexcan_clks_disable(priv);
1474         return err;
1475 }
1476
1477 static void unregister_flexcandev(struct net_device *dev)
1478 {
1479         unregister_candev(dev);
1480 }
1481
1482 static int flexcan_setup_stop_mode(struct platform_device *pdev)
1483 {
1484         struct net_device *dev = platform_get_drvdata(pdev);
1485         struct device_node *np = pdev->dev.of_node;
1486         struct device_node *gpr_np;
1487         struct flexcan_priv *priv;
1488         phandle phandle;
1489         u32 out_val[5];
1490         int ret;
1491
1492         if (!np)
1493                 return -EINVAL;
1494
1495         /* stop mode property format is:
1496          * <&gpr req_gpr req_bit ack_gpr ack_bit>.
1497          */
1498         ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
1499                                          ARRAY_SIZE(out_val));
1500         if (ret) {
1501                 dev_dbg(&pdev->dev, "no stop-mode property\n");
1502                 return ret;
1503         }
1504         phandle = *out_val;
1505
1506         gpr_np = of_find_node_by_phandle(phandle);
1507         if (!gpr_np) {
1508                 dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
1509                 return -ENODEV;
1510         }
1511
1512         priv = netdev_priv(dev);
1513         priv->stm.gpr = syscon_node_to_regmap(gpr_np);
1514         if (IS_ERR(priv->stm.gpr)) {
1515                 dev_dbg(&pdev->dev, "could not find gpr regmap\n");
1516                 ret = PTR_ERR(priv->stm.gpr);
1517                 goto out_put_node;
1518         }
1519
1520         priv->stm.req_gpr = out_val[1];
1521         priv->stm.req_bit = out_val[2];
1522         priv->stm.ack_gpr = out_val[3];
1523         priv->stm.ack_bit = out_val[4];
1524
1525         dev_dbg(&pdev->dev,
1526                 "gpr %s req_gpr=0x02%x req_bit=%u ack_gpr=0x02%x ack_bit=%u\n",
1527                 gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit,
1528                 priv->stm.ack_gpr, priv->stm.ack_bit);
1529
1530         device_set_wakeup_capable(&pdev->dev, true);
1531
1532         if (of_property_read_bool(np, "wakeup-source"))
1533                 device_set_wakeup_enable(&pdev->dev, true);
1534
1535         return 0;
1536
1537 out_put_node:
1538         of_node_put(gpr_np);
1539         return ret;
1540 }
1541
1542 static const struct of_device_id flexcan_of_match[] = {
1543         { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1544         { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1545         { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
1546         { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
1547         { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
1548         { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1549         { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1550         { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
1551         { /* sentinel */ },
1552 };
1553 MODULE_DEVICE_TABLE(of, flexcan_of_match);
1554
1555 static const struct platform_device_id flexcan_id_table[] = {
1556         { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1557         { /* sentinel */ },
1558 };
1559 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1560
1561 static int flexcan_probe(struct platform_device *pdev)
1562 {
1563         const struct of_device_id *of_id;
1564         const struct flexcan_devtype_data *devtype_data;
1565         struct net_device *dev;
1566         struct flexcan_priv *priv;
1567         struct regulator *reg_xceiver;
1568         struct clk *clk_ipg = NULL, *clk_per = NULL;
1569         struct flexcan_regs __iomem *regs;
1570         int err, irq;
1571         u8 clk_src = 1;
1572         u32 clock_freq = 0;
1573
1574         reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1575         if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1576                 return -EPROBE_DEFER;
1577         else if (IS_ERR(reg_xceiver))
1578                 reg_xceiver = NULL;
1579
1580         if (pdev->dev.of_node) {
1581                 of_property_read_u32(pdev->dev.of_node,
1582                                      "clock-frequency", &clock_freq);
1583                 of_property_read_u8(pdev->dev.of_node,
1584                                     "fsl,clk-source", &clk_src);
1585         }
1586
1587         if (!clock_freq) {
1588                 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1589                 if (IS_ERR(clk_ipg)) {
1590                         dev_err(&pdev->dev, "no ipg clock defined\n");
1591                         return PTR_ERR(clk_ipg);
1592                 }
1593
1594                 clk_per = devm_clk_get(&pdev->dev, "per");
1595                 if (IS_ERR(clk_per)) {
1596                         dev_err(&pdev->dev, "no per clock defined\n");
1597                         return PTR_ERR(clk_per);
1598                 }
1599                 clock_freq = clk_get_rate(clk_per);
1600         }
1601
1602         irq = platform_get_irq(pdev, 0);
1603         if (irq <= 0)
1604                 return -ENODEV;
1605
1606         regs = devm_platform_ioremap_resource(pdev, 0);
1607         if (IS_ERR(regs))
1608                 return PTR_ERR(regs);
1609
1610         of_id = of_match_device(flexcan_of_match, &pdev->dev);
1611         if (of_id) {
1612                 devtype_data = of_id->data;
1613         } else if (platform_get_device_id(pdev)->driver_data) {
1614                 devtype_data = (struct flexcan_devtype_data *)
1615                         platform_get_device_id(pdev)->driver_data;
1616         } else {
1617                 return -ENODEV;
1618         }
1619
1620         dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1621         if (!dev)
1622                 return -ENOMEM;
1623
1624         platform_set_drvdata(pdev, dev);
1625         SET_NETDEV_DEV(dev, &pdev->dev);
1626
1627         dev->netdev_ops = &flexcan_netdev_ops;
1628         dev->irq = irq;
1629         dev->flags |= IFF_ECHO;
1630
1631         priv = netdev_priv(dev);
1632
1633         if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
1634             devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
1635                 priv->read = flexcan_read_be;
1636                 priv->write = flexcan_write_be;
1637         } else {
1638                 priv->read = flexcan_read_le;
1639                 priv->write = flexcan_write_le;
1640         }
1641
1642         priv->dev = &pdev->dev;
1643         priv->can.clock.freq = clock_freq;
1644         priv->can.bittiming_const = &flexcan_bittiming_const;
1645         priv->can.do_set_mode = flexcan_set_mode;
1646         priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1647         priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1648                 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1649                 CAN_CTRLMODE_BERR_REPORTING;
1650         priv->regs = regs;
1651         priv->clk_ipg = clk_ipg;
1652         priv->clk_per = clk_per;
1653         priv->clk_src = clk_src;
1654         priv->devtype_data = devtype_data;
1655         priv->reg_xceiver = reg_xceiver;
1656
1657         pm_runtime_get_noresume(&pdev->dev);
1658         pm_runtime_set_active(&pdev->dev);
1659         pm_runtime_enable(&pdev->dev);
1660
1661         err = register_flexcandev(dev);
1662         if (err) {
1663                 dev_err(&pdev->dev, "registering netdev failed\n");
1664                 goto failed_register;
1665         }
1666
1667         devm_can_led_init(dev);
1668
1669         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE) {
1670                 err = flexcan_setup_stop_mode(pdev);
1671                 if (err)
1672                         dev_dbg(&pdev->dev, "failed to setup stop-mode\n");
1673         }
1674
1675         return 0;
1676
1677  failed_register:
1678         free_candev(dev);
1679         return err;
1680 }
1681
1682 static int flexcan_remove(struct platform_device *pdev)
1683 {
1684         struct net_device *dev = platform_get_drvdata(pdev);
1685
1686         unregister_flexcandev(dev);
1687         pm_runtime_disable(&pdev->dev);
1688         free_candev(dev);
1689
1690         return 0;
1691 }
1692
1693 static int __maybe_unused flexcan_suspend(struct device *device)
1694 {
1695         struct net_device *dev = dev_get_drvdata(device);
1696         struct flexcan_priv *priv = netdev_priv(dev);
1697         int err = 0;
1698
1699         if (netif_running(dev)) {
1700                 /* if wakeup is enabled, enter stop mode
1701                  * else enter disabled mode.
1702                  */
1703                 if (device_may_wakeup(device)) {
1704                         enable_irq_wake(dev->irq);
1705                         err = flexcan_enter_stop_mode(priv);
1706                         if (err)
1707                                 return err;
1708                 } else {
1709                         err = flexcan_chip_disable(priv);
1710                         if (err)
1711                                 return err;
1712
1713                         err = pm_runtime_force_suspend(device);
1714                 }
1715                 netif_stop_queue(dev);
1716                 netif_device_detach(dev);
1717         }
1718         priv->can.state = CAN_STATE_SLEEPING;
1719
1720         return err;
1721 }
1722
1723 static int __maybe_unused flexcan_resume(struct device *device)
1724 {
1725         struct net_device *dev = dev_get_drvdata(device);
1726         struct flexcan_priv *priv = netdev_priv(dev);
1727         int err = 0;
1728
1729         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1730         if (netif_running(dev)) {
1731                 netif_device_attach(dev);
1732                 netif_start_queue(dev);
1733                 if (device_may_wakeup(device)) {
1734                         disable_irq_wake(dev->irq);
1735                         err = flexcan_exit_stop_mode(priv);
1736                         if (err)
1737                                 return err;
1738                 } else {
1739                         err = pm_runtime_force_resume(device);
1740                         if (err)
1741                                 return err;
1742
1743                         err = flexcan_chip_enable(priv);
1744                 }
1745         }
1746
1747         return err;
1748 }
1749
1750 static int __maybe_unused flexcan_runtime_suspend(struct device *device)
1751 {
1752         struct net_device *dev = dev_get_drvdata(device);
1753         struct flexcan_priv *priv = netdev_priv(dev);
1754
1755         flexcan_clks_disable(priv);
1756
1757         return 0;
1758 }
1759
1760 static int __maybe_unused flexcan_runtime_resume(struct device *device)
1761 {
1762         struct net_device *dev = dev_get_drvdata(device);
1763         struct flexcan_priv *priv = netdev_priv(dev);
1764
1765         return flexcan_clks_enable(priv);
1766 }
1767
1768 static int __maybe_unused flexcan_noirq_suspend(struct device *device)
1769 {
1770         struct net_device *dev = dev_get_drvdata(device);
1771         struct flexcan_priv *priv = netdev_priv(dev);
1772
1773         if (netif_running(dev) && device_may_wakeup(device))
1774                 flexcan_enable_wakeup_irq(priv, true);
1775
1776         return 0;
1777 }
1778
1779 static int __maybe_unused flexcan_noirq_resume(struct device *device)
1780 {
1781         struct net_device *dev = dev_get_drvdata(device);
1782         struct flexcan_priv *priv = netdev_priv(dev);
1783
1784         if (netif_running(dev) && device_may_wakeup(device))
1785                 flexcan_enable_wakeup_irq(priv, false);
1786
1787         return 0;
1788 }
1789
1790 static const struct dev_pm_ops flexcan_pm_ops = {
1791         SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
1792         SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL)
1793         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
1794 };
1795
1796 static struct platform_driver flexcan_driver = {
1797         .driver = {
1798                 .name = DRV_NAME,
1799                 .pm = &flexcan_pm_ops,
1800                 .of_match_table = flexcan_of_match,
1801         },
1802         .probe = flexcan_probe,
1803         .remove = flexcan_remove,
1804         .id_table = flexcan_id_table,
1805 };
1806
1807 module_platform_driver(flexcan_driver);
1808
1809 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1810               "Marc Kleine-Budde <kernel@pengutronix.de>");
1811 MODULE_LICENSE("GPL v2");
1812 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");