drivers/mtd/nand/raw/stm32_fmc2_nand.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics 2018
   4  * Author: Christophe Kerello <christophe.kerello@st.com>
   5  */
   6
   7 #include <linux/bitfield.h>
   8 #include <linux/clk.h>
   9 #include <linux/dmaengine.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/errno.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/mfd/syscon.h>
  15 #include <linux/module.h>
  16 #include <linux/mtd/rawnand.h>
  17 #include <linux/of_address.h>
  18 #include <linux/pinctrl/consumer.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/regmap.h>
  21 #include <linux/reset.h>
  22
  23 /* Bad block marker length */
  24 #define FMC2_BBM_LEN                    2
  25
  26 /* ECC step size */
  27 #define FMC2_ECC_STEP_SIZE              512
  28
  29 /* BCHDSRx registers length */
  30 #define FMC2_BCHDSRS_LEN                20
  31
  32 /* HECCR length */
  33 #define FMC2_HECCR_LEN                  4
  34
  35 /* Max requests done for a 8k nand page size */
  36 #define FMC2_MAX_SG                     16
  37
  38 /* Max chip enable */
  39 #define FMC2_MAX_CE                     2
  40
  41 /* Max ECC buffer length */
  42 #define FMC2_MAX_ECC_BUF_LEN            (FMC2_BCHDSRS_LEN * FMC2_MAX_SG)
  43
  44 #define FMC2_TIMEOUT_MS                 5000
  45
  46 /* Timings */
  47 #define FMC2_THIZ                       1
  48 #define FMC2_TIO                        8000
  49 #define FMC2_TSYNC                      3000
  50 #define FMC2_PCR_TIMING_MASK            0xf
  51 #define FMC2_PMEM_PATT_TIMING_MASK      0xff
  52
  53 /* FMC2 Controller Registers */
  54 #define FMC2_BCR1                       0x0
  55 #define FMC2_PCR                        0x80
  56 #define FMC2_SR                         0x84
  57 #define FMC2_PMEM                       0x88
  58 #define FMC2_PATT                       0x8c
  59 #define FMC2_HECCR                      0x94
  60 #define FMC2_ISR                        0x184
  61 #define FMC2_ICR                        0x188
  62 #define FMC2_CSQCR                      0x200
  63 #define FMC2_CSQCFGR1                   0x204
  64 #define FMC2_CSQCFGR2                   0x208
  65 #define FMC2_CSQCFGR3                   0x20c
  66 #define FMC2_CSQAR1                     0x210
  67 #define FMC2_CSQAR2                     0x214
  68 #define FMC2_CSQIER                     0x220
  69 #define FMC2_CSQISR                     0x224
  70 #define FMC2_CSQICR                     0x228
  71 #define FMC2_CSQEMSR                    0x230
  72 #define FMC2_BCHIER                     0x250
  73 #define FMC2_BCHISR                     0x254
  74 #define FMC2_BCHICR                     0x258
  75 #define FMC2_BCHPBR1                    0x260
  76 #define FMC2_BCHPBR2                    0x264
  77 #define FMC2_BCHPBR3                    0x268
  78 #define FMC2_BCHPBR4                    0x26c
  79 #define FMC2_BCHDSR0                    0x27c
  80 #define FMC2_BCHDSR1                    0x280
  81 #define FMC2_BCHDSR2                    0x284
  82 #define FMC2_BCHDSR3                    0x288
  83 #define FMC2_BCHDSR4                    0x28c
  84
  85 /* Register: FMC2_BCR1 */
  86 #define FMC2_BCR1_FMC2EN                BIT(31)
  87
  88 /* Register: FMC2_PCR */
  89 #define FMC2_PCR_PWAITEN                BIT(1)
  90 #define FMC2_PCR_PBKEN                  BIT(2)
  91 #define FMC2_PCR_PWID                   GENMASK(5, 4)
  92 #define FMC2_PCR_PWID_BUSWIDTH_8        0
  93 #define FMC2_PCR_PWID_BUSWIDTH_16       1
  94 #define FMC2_PCR_ECCEN                  BIT(6)
  95 #define FMC2_PCR_ECCALG                 BIT(8)
  96 #define FMC2_PCR_TCLR                   GENMASK(12, 9)
  97 #define FMC2_PCR_TCLR_DEFAULT           0xf
  98 #define FMC2_PCR_TAR                    GENMASK(16, 13)
  99 #define FMC2_PCR_TAR_DEFAULT            0xf
 100 #define FMC2_PCR_ECCSS                  GENMASK(19, 17)
 101 #define FMC2_PCR_ECCSS_512              1
 102 #define FMC2_PCR_ECCSS_2048             3
 103 #define FMC2_PCR_BCHECC                 BIT(24)
 104 #define FMC2_PCR_WEN                    BIT(25)
 105
 106 /* Register: FMC2_SR */
 107 #define FMC2_SR_NWRF                    BIT(6)
 108
 109 /* Register: FMC2_PMEM */
 110 #define FMC2_PMEM_MEMSET                GENMASK(7, 0)
 111 #define FMC2_PMEM_MEMWAIT               GENMASK(15, 8)
 112 #define FMC2_PMEM_MEMHOLD               GENMASK(23, 16)
 113 #define FMC2_PMEM_MEMHIZ                GENMASK(31, 24)
 114 #define FMC2_PMEM_DEFAULT               0x0a0a0a0a
 115
 116 /* Register: FMC2_PATT */
 117 #define FMC2_PATT_ATTSET                GENMASK(7, 0)
 118 #define FMC2_PATT_ATTWAIT               GENMASK(15, 8)
 119 #define FMC2_PATT_ATTHOLD               GENMASK(23, 16)
 120 #define FMC2_PATT_ATTHIZ                GENMASK(31, 24)
 121 #define FMC2_PATT_DEFAULT               0x0a0a0a0a
 122
 123 /* Register: FMC2_ISR */
 124 #define FMC2_ISR_IHLF                   BIT(1)
 125
 126 /* Register: FMC2_ICR */
 127 #define FMC2_ICR_CIHLF                  BIT(1)
 128
 129 /* Register: FMC2_CSQCR */
 130 #define FMC2_CSQCR_CSQSTART             BIT(0)
 131
 132 /* Register: FMC2_CSQCFGR1 */
 133 #define FMC2_CSQCFGR1_CMD2EN            BIT(1)
 134 #define FMC2_CSQCFGR1_DMADEN            BIT(2)
 135 #define FMC2_CSQCFGR1_ACYNBR            GENMASK(6, 4)
 136 #define FMC2_CSQCFGR1_CMD1              GENMASK(15, 8)
 137 #define FMC2_CSQCFGR1_CMD2              GENMASK(23, 16)
 138 #define FMC2_CSQCFGR1_CMD1T             BIT(24)
 139 #define FMC2_CSQCFGR1_CMD2T             BIT(25)
 140
 141 /* Register: FMC2_CSQCFGR2 */
 142 #define FMC2_CSQCFGR2_SQSDTEN           BIT(0)
 143 #define FMC2_CSQCFGR2_RCMD2EN           BIT(1)
 144 #define FMC2_CSQCFGR2_DMASEN            BIT(2)
 145 #define FMC2_CSQCFGR2_RCMD1             GENMASK(15, 8)
 146 #define FMC2_CSQCFGR2_RCMD2             GENMASK(23, 16)
 147 #define FMC2_CSQCFGR2_RCMD1T            BIT(24)
 148 #define FMC2_CSQCFGR2_RCMD2T            BIT(25)
 149
 150 /* Register: FMC2_CSQCFGR3 */
 151 #define FMC2_CSQCFGR3_SNBR              GENMASK(13, 8)
 152 #define FMC2_CSQCFGR3_AC1T              BIT(16)
 153 #define FMC2_CSQCFGR3_AC2T              BIT(17)
 154 #define FMC2_CSQCFGR3_AC3T              BIT(18)
 155 #define FMC2_CSQCFGR3_AC4T              BIT(19)
 156 #define FMC2_CSQCFGR3_AC5T              BIT(20)
 157 #define FMC2_CSQCFGR3_SDT               BIT(21)
 158 #define FMC2_CSQCFGR3_RAC1T             BIT(22)
 159 #define FMC2_CSQCFGR3_RAC2T             BIT(23)
 160
 161 /* Register: FMC2_CSQCAR1 */
 162 #define FMC2_CSQCAR1_ADDC1              GENMASK(7, 0)
 163 #define FMC2_CSQCAR1_ADDC2              GENMASK(15, 8)
 164 #define FMC2_CSQCAR1_ADDC3              GENMASK(23, 16)
 165 #define FMC2_CSQCAR1_ADDC4              GENMASK(31, 24)
 166
 167 /* Register: FMC2_CSQCAR2 */
 168 #define FMC2_CSQCAR2_ADDC5              GENMASK(7, 0)
 169 #define FMC2_CSQCAR2_NANDCEN            GENMASK(11, 10)
 170 #define FMC2_CSQCAR2_SAO                GENMASK(31, 16)
 171
 172 /* Register: FMC2_CSQIER */
 173 #define FMC2_CSQIER_TCIE                BIT(0)
 174
 175 /* Register: FMC2_CSQICR */
 176 #define FMC2_CSQICR_CLEAR_IRQ           GENMASK(4, 0)
 177
 178 /* Register: FMC2_CSQEMSR */
 179 #define FMC2_CSQEMSR_SEM                GENMASK(15, 0)
 180
 181 /* Register: FMC2_BCHIER */
 182 #define FMC2_BCHIER_DERIE               BIT(1)
 183 #define FMC2_BCHIER_EPBRIE              BIT(4)
 184
 185 /* Register: FMC2_BCHICR */
 186 #define FMC2_BCHICR_CLEAR_IRQ           GENMASK(4, 0)
 187
 188 /* Register: FMC2_BCHDSR0 */
 189 #define FMC2_BCHDSR0_DUE                BIT(0)
 190 #define FMC2_BCHDSR0_DEF                BIT(1)
 191 #define FMC2_BCHDSR0_DEN                GENMASK(7, 4)
 192
 193 /* Register: FMC2_BCHDSR1 */
 194 #define FMC2_BCHDSR1_EBP1               GENMASK(12, 0)
 195 #define FMC2_BCHDSR1_EBP2               GENMASK(28, 16)
 196
 197 /* Register: FMC2_BCHDSR2 */
 198 #define FMC2_BCHDSR2_EBP3               GENMASK(12, 0)
 199 #define FMC2_BCHDSR2_EBP4               GENMASK(28, 16)
 200
 201 /* Register: FMC2_BCHDSR3 */
 202 #define FMC2_BCHDSR3_EBP5               GENMASK(12, 0)
 203 #define FMC2_BCHDSR3_EBP6               GENMASK(28, 16)
 204
 205 /* Register: FMC2_BCHDSR4 */
 206 #define FMC2_BCHDSR4_EBP7               GENMASK(12, 0)
 207 #define FMC2_BCHDSR4_EBP8               GENMASK(28, 16)
 208
 209 enum stm32_fmc2_ecc {
 210         FMC2_ECC_HAM = 1,
 211         FMC2_ECC_BCH4 = 4,
 212         FMC2_ECC_BCH8 = 8
 213 };
 214
 215 enum stm32_fmc2_irq_state {
 216         FMC2_IRQ_UNKNOWN = 0,
 217         FMC2_IRQ_BCH,
 218         FMC2_IRQ_SEQ
 219 };
 220
 221 struct stm32_fmc2_timings {
 222         u8 tclr;
 223         u8 tar;
 224         u8 thiz;
 225         u8 twait;
 226         u8 thold_mem;
 227         u8 tset_mem;
 228         u8 thold_att;
 229         u8 tset_att;
 230 };
 231
 232 struct stm32_fmc2_nand {
 233         struct nand_chip chip;
 234         struct stm32_fmc2_timings timings;
 235         int ncs;
 236         int cs_used[FMC2_MAX_CE];
 237 };
 238
 239 static inline struct stm32_fmc2_nand *to_fmc2_nand(struct nand_chip *chip)
 240 {
 241         return container_of(chip, struct stm32_fmc2_nand, chip);
 242 }
 243
 244 struct stm32_fmc2_nfc {
 245         struct nand_controller base;
 246         struct stm32_fmc2_nand nand;
 247         struct device *dev;
 248         struct device *cdev;
 249         struct regmap *regmap;
 250         void __iomem *data_base[FMC2_MAX_CE];
 251         void __iomem *cmd_base[FMC2_MAX_CE];
 252         void __iomem *addr_base[FMC2_MAX_CE];
 253         phys_addr_t io_phys_addr;
 254         phys_addr_t data_phys_addr[FMC2_MAX_CE];
 255         struct clk *clk;
 256         u8 irq_state;
 257
 258         struct dma_chan *dma_tx_ch;
 259         struct dma_chan *dma_rx_ch;
 260         struct dma_chan *dma_ecc_ch;
 261         struct sg_table dma_data_sg;
 262         struct sg_table dma_ecc_sg;
 263         u8 *ecc_buf;
 264         int dma_ecc_len;
 265
 266         struct completion complete;
 267         struct completion dma_data_complete;
 268         struct completion dma_ecc_complete;
 269
 270         u8 cs_assigned;
 271         int cs_sel;
 272 };
 273
 274 static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_controller *base)
 275 {
 276         return container_of(base, struct stm32_fmc2_nfc, base);
 277 }
 278
 279 static void stm32_fmc2_nfc_timings_init(struct nand_chip *chip)
 280 {
 281         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 282         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 283         struct stm32_fmc2_timings *timings = &nand->timings;
 284         u32 pmem, patt;
 285
 286         /* Set tclr/tar timings */
 287         regmap_update_bits(nfc->regmap, FMC2_PCR,
 288                            FMC2_PCR_TCLR | FMC2_PCR_TAR,
 289                            FIELD_PREP(FMC2_PCR_TCLR, timings->tclr) |
 290                            FIELD_PREP(FMC2_PCR_TAR, timings->tar));
 291
 292         /* Set tset/twait/thold/thiz timings in common bank */
 293         pmem = FIELD_PREP(FMC2_PMEM_MEMSET, timings->tset_mem);
 294         pmem |= FIELD_PREP(FMC2_PMEM_MEMWAIT, timings->twait);
 295         pmem |= FIELD_PREP(FMC2_PMEM_MEMHOLD, timings->thold_mem);
 296         pmem |= FIELD_PREP(FMC2_PMEM_MEMHIZ, timings->thiz);
 297         regmap_write(nfc->regmap, FMC2_PMEM, pmem);
 298
 299         /* Set tset/twait/thold/thiz timings in attribut bank */
 300         patt = FIELD_PREP(FMC2_PATT_ATTSET, timings->tset_att);
 301         patt |= FIELD_PREP(FMC2_PATT_ATTWAIT, timings->twait);
 302         patt |= FIELD_PREP(FMC2_PATT_ATTHOLD, timings->thold_att);
 303         patt |= FIELD_PREP(FMC2_PATT_ATTHIZ, timings->thiz);
 304         regmap_write(nfc->regmap, FMC2_PATT, patt);
 305 }
 306
 307 static void stm32_fmc2_nfc_setup(struct nand_chip *chip)
 308 {
 309         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 310         u32 pcr = 0, pcr_mask;
 311
 312         /* Configure ECC algorithm (default configuration is Hamming) */
 313         pcr_mask = FMC2_PCR_ECCALG;
 314         pcr_mask |= FMC2_PCR_BCHECC;
 315         if (chip->ecc.strength == FMC2_ECC_BCH8) {
 316                 pcr |= FMC2_PCR_ECCALG;
 317                 pcr |= FMC2_PCR_BCHECC;
 318         } else if (chip->ecc.strength == FMC2_ECC_BCH4) {
 319                 pcr |= FMC2_PCR_ECCALG;
 320         }
 321
 322         /* Set buswidth */
 323         pcr_mask |= FMC2_PCR_PWID;
 324         if (chip->options & NAND_BUSWIDTH_16)
 325                 pcr |= FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16);
 326
 327         /* Set ECC sector size */
 328         pcr_mask |= FMC2_PCR_ECCSS;
 329         pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_512);
 330
 331         regmap_update_bits(nfc->regmap, FMC2_PCR, pcr_mask, pcr);
 332 }
 333
 334 static int stm32_fmc2_nfc_select_chip(struct nand_chip *chip, int chipnr)
 335 {
 336         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 337         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 338         struct dma_slave_config dma_cfg;
 339         int ret;
 340
 341         if (nand->cs_used[chipnr] == nfc->cs_sel)
 342                 return 0;
 343
 344         nfc->cs_sel = nand->cs_used[chipnr];
 345         stm32_fmc2_nfc_setup(chip);
 346         stm32_fmc2_nfc_timings_init(chip);
 347
 348         if (nfc->dma_tx_ch && nfc->dma_rx_ch) {
 349                 memset(&dma_cfg, 0, sizeof(dma_cfg));
 350                 dma_cfg.src_addr = nfc->data_phys_addr[nfc->cs_sel];
 351                 dma_cfg.dst_addr = nfc->data_phys_addr[nfc->cs_sel];
 352                 dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 353                 dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 354                 dma_cfg.src_maxburst = 32;
 355                 dma_cfg.dst_maxburst = 32;
 356
 357                 ret = dmaengine_slave_config(nfc->dma_tx_ch, &dma_cfg);
 358                 if (ret) {
 359                         dev_err(nfc->dev, "tx DMA engine slave config failed\n");
 360                         return ret;
 361                 }
 362
 363                 ret = dmaengine_slave_config(nfc->dma_rx_ch, &dma_cfg);
 364                 if (ret) {
 365                         dev_err(nfc->dev, "rx DMA engine slave config failed\n");
 366                         return ret;
 367                 }
 368         }
 369
 370         if (nfc->dma_ecc_ch) {
 371                 /*
 372                  * Hamming: we read HECCR register
 373                  * BCH4/BCH8: we read BCHDSRSx registers
 374                  */
 375                 memset(&dma_cfg, 0, sizeof(dma_cfg));
 376                 dma_cfg.src_addr = nfc->io_phys_addr;
 377                 dma_cfg.src_addr += chip->ecc.strength == FMC2_ECC_HAM ?
 378                                     FMC2_HECCR : FMC2_BCHDSR0;
 379                 dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 380
 381                 ret = dmaengine_slave_config(nfc->dma_ecc_ch, &dma_cfg);
 382                 if (ret) {
 383                         dev_err(nfc->dev, "ECC DMA engine slave config failed\n");
 384                         return ret;
 385                 }
 386
 387                 /* Calculate ECC length needed for one sector */
 388                 nfc->dma_ecc_len = chip->ecc.strength == FMC2_ECC_HAM ?
 389                                    FMC2_HECCR_LEN : FMC2_BCHDSRS_LEN;
 390         }
 391
 392         return 0;
 393 }
 394
 395 static void stm32_fmc2_nfc_set_buswidth_16(struct stm32_fmc2_nfc *nfc, bool set)
 396 {
 397         u32 pcr;
 398
 399         pcr = set ? FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16) :
 400                     FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_8);
 401
 402         regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_PWID, pcr);
 403 }
 404
 405 static void stm32_fmc2_nfc_set_ecc(struct stm32_fmc2_nfc *nfc, bool enable)
 406 {
 407         regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_ECCEN,
 408                            enable ? FMC2_PCR_ECCEN : 0);
 409 }
 410
 411 static void stm32_fmc2_nfc_enable_seq_irq(struct stm32_fmc2_nfc *nfc)
 412 {
 413         nfc->irq_state = FMC2_IRQ_SEQ;
 414
 415         regmap_update_bits(nfc->regmap, FMC2_CSQIER,
 416                            FMC2_CSQIER_TCIE, FMC2_CSQIER_TCIE);
 417 }
 418
 419 static void stm32_fmc2_nfc_disable_seq_irq(struct stm32_fmc2_nfc *nfc)
 420 {
 421         regmap_update_bits(nfc->regmap, FMC2_CSQIER, FMC2_CSQIER_TCIE, 0);
 422
 423         nfc->irq_state = FMC2_IRQ_UNKNOWN;
 424 }
 425
 426 static void stm32_fmc2_nfc_clear_seq_irq(struct stm32_fmc2_nfc *nfc)
 427 {
 428         regmap_write(nfc->regmap, FMC2_CSQICR, FMC2_CSQICR_CLEAR_IRQ);
 429 }
 430
 431 static void stm32_fmc2_nfc_enable_bch_irq(struct stm32_fmc2_nfc *nfc, int mode)
 432 {
 433         nfc->irq_state = FMC2_IRQ_BCH;
 434
 435         if (mode == NAND_ECC_WRITE)
 436                 regmap_update_bits(nfc->regmap, FMC2_BCHIER,
 437                                    FMC2_BCHIER_EPBRIE, FMC2_BCHIER_EPBRIE);
 438         else
 439                 regmap_update_bits(nfc->regmap, FMC2_BCHIER,
 440                                    FMC2_BCHIER_DERIE, FMC2_BCHIER_DERIE);
 441 }
 442
 443 static void stm32_fmc2_nfc_disable_bch_irq(struct stm32_fmc2_nfc *nfc)
 444 {
 445         regmap_update_bits(nfc->regmap, FMC2_BCHIER,
 446                            FMC2_BCHIER_DERIE | FMC2_BCHIER_EPBRIE, 0);
 447
 448         nfc->irq_state = FMC2_IRQ_UNKNOWN;
 449 }
 450
 451 static void stm32_fmc2_nfc_clear_bch_irq(struct stm32_fmc2_nfc *nfc)
 452 {
 453         regmap_write(nfc->regmap, FMC2_BCHICR, FMC2_BCHICR_CLEAR_IRQ);
 454 }
 455
 456 /*
 457  * Enable ECC logic and reset syndrome/parity bits previously calculated
 458  * Syndrome/parity bits is cleared by setting the ECCEN bit to 0
 459  */
 460 static void stm32_fmc2_nfc_hwctl(struct nand_chip *chip, int mode)
 461 {
 462         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 463
 464         stm32_fmc2_nfc_set_ecc(nfc, false);
 465
 466         if (chip->ecc.strength != FMC2_ECC_HAM) {
 467                 regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_WEN,
 468                                    mode == NAND_ECC_WRITE ? FMC2_PCR_WEN : 0);
 469
 470                 reinit_completion(&nfc->complete);
 471                 stm32_fmc2_nfc_clear_bch_irq(nfc);
 472                 stm32_fmc2_nfc_enable_bch_irq(nfc, mode);
 473         }
 474
 475         stm32_fmc2_nfc_set_ecc(nfc, true);
 476 }
 477
 478 /*
 479  * ECC Hamming calculation
 480  * ECC is 3 bytes for 512 bytes of data (supports error correction up to
 481  * max of 1-bit)
 482  */
 483 static void stm32_fmc2_nfc_ham_set_ecc(const u32 ecc_sta, u8 *ecc)
 484 {
 485         ecc[0] = ecc_sta;
 486         ecc[1] = ecc_sta >> 8;
 487         ecc[2] = ecc_sta >> 16;
 488 }
 489
 490 static int stm32_fmc2_nfc_ham_calculate(struct nand_chip *chip, const u8 *data,
 491                                         u8 *ecc)
 492 {
 493         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 494         u32 sr, heccr;
 495         int ret;
 496
 497         ret = regmap_read_poll_timeout(nfc->regmap, FMC2_SR, sr,
 498                                        sr & FMC2_SR_NWRF, 1,
 499                                        1000 * FMC2_TIMEOUT_MS);
 500         if (ret) {
 501                 dev_err(nfc->dev, "ham timeout\n");
 502                 return ret;
 503         }
 504
 505         regmap_read(nfc->regmap, FMC2_HECCR, &heccr);
 506         stm32_fmc2_nfc_ham_set_ecc(heccr, ecc);
 507         stm32_fmc2_nfc_set_ecc(nfc, false);
 508
 509         return 0;
 510 }
 511
 512 static int stm32_fmc2_nfc_ham_correct(struct nand_chip *chip, u8 *dat,
 513                                       u8 *read_ecc, u8 *calc_ecc)
 514 {
 515         u8 bit_position = 0, b0, b1, b2;
 516         u32 byte_addr = 0, b;
 517         u32 i, shifting = 1;
 518
 519         /* Indicate which bit and byte is faulty (if any) */
 520         b0 = read_ecc[0] ^ calc_ecc[0];
 521         b1 = read_ecc[1] ^ calc_ecc[1];
 522         b2 = read_ecc[2] ^ calc_ecc[2];
 523         b = b0 | (b1 << 8) | (b2 << 16);
 524
 525         /* No errors */
 526         if (likely(!b))
 527                 return 0;
 528
 529         /* Calculate bit position */
 530         for (i = 0; i < 3; i++) {
 531                 switch (b % 4) {
 532                 case 2:
 533                         bit_position += shifting;
 534                 case 1:
 535                         break;
 536                 default:
 537                         return -EBADMSG;
 538                 }
 539                 shifting <<= 1;
 540                 b >>= 2;
 541         }
 542
 543         /* Calculate byte position */
 544         shifting = 1;
 545         for (i = 0; i < 9; i++) {
 546                 switch (b % 4) {
 547                 case 2:
 548                         byte_addr += shifting;
 549                 case 1:
 550                         break;
 551                 default:
 552                         return -EBADMSG;
 553                 }
 554                 shifting <<= 1;
 555                 b >>= 2;
 556         }
 557
 558         /* Flip the bit */
 559         dat[byte_addr] ^= (1 << bit_position);
 560
 561         return 1;
 562 }
 563
 564 /*
 565  * ECC BCH calculation and correction
 566  * ECC is 7/13 bytes for 512 bytes of data (supports error correction up to
 567  * max of 4-bit/8-bit)
 568  */
 569 static int stm32_fmc2_nfc_bch_calculate(struct nand_chip *chip, const u8 *data,
 570                                         u8 *ecc)
 571 {
 572         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 573         u32 bchpbr;
 574
 575         /* Wait until the BCH code is ready */
 576         if (!wait_for_completion_timeout(&nfc->complete,
 577                                          msecs_to_jiffies(FMC2_TIMEOUT_MS))) {
 578                 dev_err(nfc->dev, "bch timeout\n");
 579                 stm32_fmc2_nfc_disable_bch_irq(nfc);
 580                 return -ETIMEDOUT;
 581         }
 582
 583         /* Read parity bits */
 584         regmap_read(nfc->regmap, FMC2_BCHPBR1, &bchpbr);
 585         ecc[0] = bchpbr;
 586         ecc[1] = bchpbr >> 8;
 587         ecc[2] = bchpbr >> 16;
 588         ecc[3] = bchpbr >> 24;
 589
 590         regmap_read(nfc->regmap, FMC2_BCHPBR2, &bchpbr);
 591         ecc[4] = bchpbr;
 592         ecc[5] = bchpbr >> 8;
 593         ecc[6] = bchpbr >> 16;
 594
 595         if (chip->ecc.strength == FMC2_ECC_BCH8) {
 596                 ecc[7] = bchpbr >> 24;
 597
 598                 regmap_read(nfc->regmap, FMC2_BCHPBR3, &bchpbr);
 599                 ecc[8] = bchpbr;
 600                 ecc[9] = bchpbr >> 8;
 601                 ecc[10] = bchpbr >> 16;
 602                 ecc[11] = bchpbr >> 24;
 603
 604                 regmap_read(nfc->regmap, FMC2_BCHPBR4, &bchpbr);
 605                 ecc[12] = bchpbr;
 606         }
 607
 608         stm32_fmc2_nfc_set_ecc(nfc, false);
 609
 610         return 0;
 611 }
 612
 613 static int stm32_fmc2_nfc_bch_decode(int eccsize, u8 *dat, u32 *ecc_sta)
 614 {
 615         u32 bchdsr0 = ecc_sta[0];
 616         u32 bchdsr1 = ecc_sta[1];
 617         u32 bchdsr2 = ecc_sta[2];
 618         u32 bchdsr3 = ecc_sta[3];
 619         u32 bchdsr4 = ecc_sta[4];
 620         u16 pos[8];
 621         int i, den;
 622         unsigned int nb_errs = 0;
 623
 624         /* No errors found */
 625         if (likely(!(bchdsr0 & FMC2_BCHDSR0_DEF)))
 626                 return 0;
 627
 628         /* Too many errors detected */
 629         if (unlikely(bchdsr0 & FMC2_BCHDSR0_DUE))
 630                 return -EBADMSG;
 631
 632         pos[0] = FIELD_GET(FMC2_BCHDSR1_EBP1, bchdsr1);
 633         pos[1] = FIELD_GET(FMC2_BCHDSR1_EBP2, bchdsr1);
 634         pos[2] = FIELD_GET(FMC2_BCHDSR2_EBP3, bchdsr2);
 635         pos[3] = FIELD_GET(FMC2_BCHDSR2_EBP4, bchdsr2);
 636         pos[4] = FIELD_GET(FMC2_BCHDSR3_EBP5, bchdsr3);
 637         pos[5] = FIELD_GET(FMC2_BCHDSR3_EBP6, bchdsr3);
 638         pos[6] = FIELD_GET(FMC2_BCHDSR4_EBP7, bchdsr4);
 639         pos[7] = FIELD_GET(FMC2_BCHDSR4_EBP8, bchdsr4);
 640
 641         den = FIELD_GET(FMC2_BCHDSR0_DEN, bchdsr0);
 642         for (i = 0; i < den; i++) {
 643                 if (pos[i] < eccsize * 8) {
 644                         change_bit(pos[i], (unsigned long *)dat);
 645                         nb_errs++;
 646                 }
 647         }
 648
 649         return nb_errs;
 650 }
 651
 652 static int stm32_fmc2_nfc_bch_correct(struct nand_chip *chip, u8 *dat,
 653                                       u8 *read_ecc, u8 *calc_ecc)
 654 {
 655         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 656         u32 ecc_sta[5];
 657
 658         /* Wait until the decoding error is ready */
 659         if (!wait_for_completion_timeout(&nfc->complete,
 660                                          msecs_to_jiffies(FMC2_TIMEOUT_MS))) {
 661                 dev_err(nfc->dev, "bch timeout\n");
 662                 stm32_fmc2_nfc_disable_bch_irq(nfc);
 663                 return -ETIMEDOUT;
 664         }
 665
 666         regmap_bulk_read(nfc->regmap, FMC2_BCHDSR0, ecc_sta, 5);
 667
 668         stm32_fmc2_nfc_set_ecc(nfc, false);
 669
 670         return stm32_fmc2_nfc_bch_decode(chip->ecc.size, dat, ecc_sta);
 671 }
 672
 673 static int stm32_fmc2_nfc_read_page(struct nand_chip *chip, u8 *buf,
 674                                     int oob_required, int page)
 675 {
 676         struct mtd_info *mtd = nand_to_mtd(chip);
 677         int ret, i, s, stat, eccsize = chip->ecc.size;
 678         int eccbytes = chip->ecc.bytes;
 679         int eccsteps = chip->ecc.steps;
 680         int eccstrength = chip->ecc.strength;
 681         u8 *p = buf;
 682         u8 *ecc_calc = chip->ecc.calc_buf;
 683         u8 *ecc_code = chip->ecc.code_buf;
 684         unsigned int max_bitflips = 0;
 685
 686         ret = nand_read_page_op(chip, page, 0, NULL, 0);
 687         if (ret)
 688                 return ret;
 689
 690         for (i = mtd->writesize + FMC2_BBM_LEN, s = 0; s < eccsteps;
 691              s++, i += eccbytes, p += eccsize) {
 692                 chip->ecc.hwctl(chip, NAND_ECC_READ);
 693
 694                 /* Read the nand page sector (512 bytes) */
 695                 ret = nand_change_read_column_op(chip, s * eccsize, p,
 696                                                  eccsize, false);
 697                 if (ret)
 698                         return ret;
 699
 700                 /* Read the corresponding ECC bytes */
 701                 ret = nand_change_read_column_op(chip, i, ecc_code,
 702                                                  eccbytes, false);
 703                 if (ret)
 704                         return ret;
 705
 706                 /* Correct the data */
 707                 stat = chip->ecc.correct(chip, p, ecc_code, ecc_calc);
 708                 if (stat == -EBADMSG)
 709                         /* Check for empty pages with bitflips */
 710                         stat = nand_check_erased_ecc_chunk(p, eccsize,
 711                                                            ecc_code, eccbytes,
 712                                                            NULL, 0,
 713                                                            eccstrength);
 714
 715                 if (stat < 0) {
 716                         mtd->ecc_stats.failed++;
 717                 } else {
 718                         mtd->ecc_stats.corrected += stat;
 719                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
 720                 }
 721         }
 722
 723         /* Read oob */
 724         if (oob_required) {
 725                 ret = nand_change_read_column_op(chip, mtd->writesize,
 726                                                  chip->oob_poi, mtd->oobsize,
 727                                                  false);
 728                 if (ret)
 729                         return ret;
 730         }
 731
 732         return max_bitflips;
 733 }
 734
 735 /* Sequencer read/write configuration */
 736 static void stm32_fmc2_nfc_rw_page_init(struct nand_chip *chip, int page,
 737                                         int raw, bool write_data)
 738 {
 739         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 740         struct mtd_info *mtd = nand_to_mtd(chip);
 741         u32 ecc_offset = mtd->writesize + FMC2_BBM_LEN;
 742         /*
 743          * cfg[0] => csqcfgr1, cfg[1] => csqcfgr2, cfg[2] => csqcfgr3
 744          * cfg[3] => csqar1, cfg[4] => csqar2
 745          */
 746         u32 cfg[5];
 747
 748         regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_WEN,
 749                            write_data ? FMC2_PCR_WEN : 0);
 750
 751         /*
 752          * - Set Program Page/Page Read command
 753          * - Enable DMA request data
 754          * - Set timings
 755          */
 756         cfg[0] = FMC2_CSQCFGR1_DMADEN | FMC2_CSQCFGR1_CMD1T;
 757         if (write_data)
 758                 cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_CMD1, NAND_CMD_SEQIN);
 759         else
 760                 cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_CMD1, NAND_CMD_READ0) |
 761                           FMC2_CSQCFGR1_CMD2EN |
 762                           FIELD_PREP(FMC2_CSQCFGR1_CMD2, NAND_CMD_READSTART) |
 763                           FMC2_CSQCFGR1_CMD2T;
 764
 765         /*
 766          * - Set Random Data Input/Random Data Read command
 767          * - Enable the sequencer to access the Spare data area
 768          * - Enable  DMA request status decoding for read
 769          * - Set timings
 770          */
 771         if (write_data)
 772                 cfg[1] = FIELD_PREP(FMC2_CSQCFGR2_RCMD1, NAND_CMD_RNDIN);
 773         else
 774                 cfg[1] = FIELD_PREP(FMC2_CSQCFGR2_RCMD1, NAND_CMD_RNDOUT) |
 775                          FMC2_CSQCFGR2_RCMD2EN |
 776                          FIELD_PREP(FMC2_CSQCFGR2_RCMD2, NAND_CMD_RNDOUTSTART) |
 777                          FMC2_CSQCFGR2_RCMD1T |
 778                          FMC2_CSQCFGR2_RCMD2T;
 779         if (!raw) {
 780                 cfg[1] |= write_data ? 0 : FMC2_CSQCFGR2_DMASEN;
 781                 cfg[1] |= FMC2_CSQCFGR2_SQSDTEN;
 782         }
 783
 784         /*
 785          * - Set the number of sectors to be written
 786          * - Set timings
 787          */
 788         cfg[2] = FIELD_PREP(FMC2_CSQCFGR3_SNBR, chip->ecc.steps - 1);
 789         if (write_data) {
 790                 cfg[2] |= FMC2_CSQCFGR3_RAC2T;
 791                 if (chip->options & NAND_ROW_ADDR_3)
 792                         cfg[2] |= FMC2_CSQCFGR3_AC5T;
 793                 else
 794                         cfg[2] |= FMC2_CSQCFGR3_AC4T;
 795         }
 796
 797         /*
 798          * Set the fourth first address cycles
 799          * Byte 1 and byte 2 => column, we start at 0x0
 800          * Byte 3 and byte 4 => page
 801          */
 802         cfg[3] = FIELD_PREP(FMC2_CSQCAR1_ADDC3, page);
 803         cfg[3] |= FIELD_PREP(FMC2_CSQCAR1_ADDC4, page >> 8);
 804
 805         /*
 806          * - Set chip enable number
 807          * - Set ECC byte offset in the spare area
 808          * - Calculate the number of address cycles to be issued
 809          * - Set byte 5 of address cycle if needed
 810          */
 811         cfg[4] = FIELD_PREP(FMC2_CSQCAR2_NANDCEN, nfc->cs_sel);
 812         if (chip->options & NAND_BUSWIDTH_16)
 813                 cfg[4] |= FIELD_PREP(FMC2_CSQCAR2_SAO, ecc_offset >> 1);
 814         else
 815                 cfg[4] |= FIELD_PREP(FMC2_CSQCAR2_SAO, ecc_offset);
 816         if (chip->options & NAND_ROW_ADDR_3) {
 817                 cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_ACYNBR, 5);
 818                 cfg[4] |= FIELD_PREP(FMC2_CSQCAR2_ADDC5, page >> 16);
 819         } else {
 820                 cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_ACYNBR, 4);
 821         }
 822
 823         regmap_bulk_write(nfc->regmap, FMC2_CSQCFGR1, cfg, 5);
 824 }
 825
 826 static void stm32_fmc2_nfc_dma_callback(void *arg)
 827 {
 828         complete((struct completion *)arg);
 829 }
 830
 831 /* Read/write data from/to a page */
 832 static int stm32_fmc2_nfc_xfer(struct nand_chip *chip, const u8 *buf,
 833                                int raw, bool write_data)
 834 {
 835         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
 836         struct dma_async_tx_descriptor *desc_data, *desc_ecc;
 837         struct scatterlist *sg;
 838         struct dma_chan *dma_ch = nfc->dma_rx_ch;
 839         enum dma_data_direction dma_data_dir = DMA_FROM_DEVICE;
 840         enum dma_transfer_direction dma_transfer_dir = DMA_DEV_TO_MEM;
 841         int eccsteps = chip->ecc.steps;
 842         int eccsize = chip->ecc.size;
 843         unsigned long timeout = msecs_to_jiffies(FMC2_TIMEOUT_MS);
 844         const u8 *p = buf;
 845         int s, ret;
 846
 847         /* Configure DMA data */
 848         if (write_data) {
 849                 dma_data_dir = DMA_TO_DEVICE;
 850                 dma_transfer_dir = DMA_MEM_TO_DEV;
 851                 dma_ch = nfc->dma_tx_ch;
 852         }
 853
 854         for_each_sg(nfc->dma_data_sg.sgl, sg, eccsteps, s) {
 855                 sg_set_buf(sg, p, eccsize);
 856                 p += eccsize;
 857         }
 858
 859         ret = dma_map_sg(nfc->dev, nfc->dma_data_sg.sgl,
 860                          eccsteps, dma_data_dir);
 861         if (ret < 0)
 862                 return ret;
 863
 864         desc_data = dmaengine_prep_slave_sg(dma_ch, nfc->dma_data_sg.sgl,
 865                                             eccsteps, dma_transfer_dir,
 866                                             DMA_PREP_INTERRUPT);
 867         if (!desc_data) {
 868                 ret = -ENOMEM;
 869                 goto err_unmap_data;
 870         }
 871
 872         reinit_completion(&nfc->dma_data_complete);
 873         reinit_completion(&nfc->complete);
 874         desc_data->callback = stm32_fmc2_nfc_dma_callback;
 875         desc_data->callback_param = &nfc->dma_data_complete;
 876         ret = dma_submit_error(dmaengine_submit(desc_data));
 877         if (ret)
 878                 goto err_unmap_data;
 879
 880         dma_async_issue_pending(dma_ch);
 881
 882         if (!write_data && !raw) {
 883                 /* Configure DMA ECC status */
 884                 p = nfc->ecc_buf;
 885                 for_each_sg(nfc->dma_ecc_sg.sgl, sg, eccsteps, s) {
 886                         sg_set_buf(sg, p, nfc->dma_ecc_len);
 887                         p += nfc->dma_ecc_len;
 888                 }
 889
 890                 ret = dma_map_sg(nfc->dev, nfc->dma_ecc_sg.sgl,
 891                                  eccsteps, dma_data_dir);
 892                 if (ret < 0)
 893                         goto err_unmap_data;
 894
 895                 desc_ecc = dmaengine_prep_slave_sg(nfc->dma_ecc_ch,
 896                                                    nfc->dma_ecc_sg.sgl,
 897                                                    eccsteps, dma_transfer_dir,
 898                                                    DMA_PREP_INTERRUPT);
 899                 if (!desc_ecc) {
 900                         ret = -ENOMEM;
 901                         goto err_unmap_ecc;
 902                 }
 903
 904                 reinit_completion(&nfc->dma_ecc_complete);
 905                 desc_ecc->callback = stm32_fmc2_nfc_dma_callback;
 906                 desc_ecc->callback_param = &nfc->dma_ecc_complete;
 907                 ret = dma_submit_error(dmaengine_submit(desc_ecc));
 908                 if (ret)
 909                         goto err_unmap_ecc;
 910
 911                 dma_async_issue_pending(nfc->dma_ecc_ch);
 912         }
 913
 914         stm32_fmc2_nfc_clear_seq_irq(nfc);
 915         stm32_fmc2_nfc_enable_seq_irq(nfc);
 916
 917         /* Start the transfer */
 918         regmap_update_bits(nfc->regmap, FMC2_CSQCR,
 919                            FMC2_CSQCR_CSQSTART, FMC2_CSQCR_CSQSTART);
 920
 921         /* Wait end of sequencer transfer */
 922         if (!wait_for_completion_timeout(&nfc->complete, timeout)) {
 923                 dev_err(nfc->dev, "seq timeout\n");
 924                 stm32_fmc2_nfc_disable_seq_irq(nfc);
 925                 dmaengine_terminate_all(dma_ch);
 926                 if (!write_data && !raw)
 927                         dmaengine_terminate_all(nfc->dma_ecc_ch);
 928                 ret = -ETIMEDOUT;
 929                 goto err_unmap_ecc;
 930         }
 931
 932         /* Wait DMA data transfer completion */
 933         if (!wait_for_completion_timeout(&nfc->dma_data_complete, timeout)) {
 934                 dev_err(nfc->dev, "data DMA timeout\n");
 935                 dmaengine_terminate_all(dma_ch);
 936                 ret = -ETIMEDOUT;
 937         }
 938
 939         /* Wait DMA ECC transfer completion */
 940         if (!write_data && !raw) {
 941                 if (!wait_for_completion_timeout(&nfc->dma_ecc_complete,
 942                                                  timeout)) {
 943                         dev_err(nfc->dev, "ECC DMA timeout\n");
 944                         dmaengine_terminate_all(nfc->dma_ecc_ch);
 945                         ret = -ETIMEDOUT;
 946                 }
 947         }
 948
 949 err_unmap_ecc:
 950         if (!write_data && !raw)
 951                 dma_unmap_sg(nfc->dev, nfc->dma_ecc_sg.sgl,
 952                              eccsteps, dma_data_dir);
 953
 954 err_unmap_data:
 955         dma_unmap_sg(nfc->dev, nfc->dma_data_sg.sgl, eccsteps, dma_data_dir);
 956
 957         return ret;
 958 }
 959
 960 static int stm32_fmc2_nfc_seq_write(struct nand_chip *chip, const u8 *buf,
 961                                     int oob_required, int page, int raw)
 962 {
 963         struct mtd_info *mtd = nand_to_mtd(chip);
 964         int ret;
 965
 966         /* Configure the sequencer */
 967         stm32_fmc2_nfc_rw_page_init(chip, page, raw, true);
 968
 969         /* Write the page */
 970         ret = stm32_fmc2_nfc_xfer(chip, buf, raw, true);
 971         if (ret)
 972                 return ret;
 973
 974         /* Write oob */
 975         if (oob_required) {
 976                 ret = nand_change_write_column_op(chip, mtd->writesize,
 977                                                   chip->oob_poi, mtd->oobsize,
 978                                                   false);
 979                 if (ret)
 980                         return ret;
 981         }
 982
 983         return nand_prog_page_end_op(chip);
 984 }
 985
 986 static int stm32_fmc2_nfc_seq_write_page(struct nand_chip *chip, const u8 *buf,
 987                                          int oob_required, int page)
 988 {
 989         int ret;
 990
 991         ret = stm32_fmc2_nfc_select_chip(chip, chip->cur_cs);
 992         if (ret)
 993                 return ret;
 994
 995         return stm32_fmc2_nfc_seq_write(chip, buf, oob_required, page, false);
 996 }
 997
 998 static int stm32_fmc2_nfc_seq_write_page_raw(struct nand_chip *chip,
 999                                              const u8 *buf, int oob_required,
1000                                              int page)
1001 {
1002         int ret;
1003
1004         ret = stm32_fmc2_nfc_select_chip(chip, chip->cur_cs);
1005         if (ret)
1006                 return ret;
1007
1008         return stm32_fmc2_nfc_seq_write(chip, buf, oob_required, page, true);
1009 }
1010
1011 /* Get a status indicating which sectors have errors */
1012 static u16 stm32_fmc2_nfc_get_mapping_status(struct stm32_fmc2_nfc *nfc)
1013 {
1014         u32 csqemsr;
1015
1016         regmap_read(nfc->regmap, FMC2_CSQEMSR, &csqemsr);
1017
1018         return FIELD_GET(FMC2_CSQEMSR_SEM, csqemsr);
1019 }
1020
1021 static int stm32_fmc2_nfc_seq_correct(struct nand_chip *chip, u8 *dat,
1022                                       u8 *read_ecc, u8 *calc_ecc)
1023 {
1024         struct mtd_info *mtd = nand_to_mtd(chip);
1025         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1026         int eccbytes = chip->ecc.bytes;
1027         int eccsteps = chip->ecc.steps;
1028         int eccstrength = chip->ecc.strength;
1029         int i, s, eccsize = chip->ecc.size;
1030         u32 *ecc_sta = (u32 *)nfc->ecc_buf;
1031         u16 sta_map = stm32_fmc2_nfc_get_mapping_status(nfc);
1032         unsigned int max_bitflips = 0;
1033
1034         for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, dat += eccsize) {
1035                 int stat = 0;
1036
1037                 if (eccstrength == FMC2_ECC_HAM) {
1038                         /* Ecc_sta = FMC2_HECCR */
1039                         if (sta_map & BIT(s)) {
1040                                 stm32_fmc2_nfc_ham_set_ecc(*ecc_sta,
1041                                                            &calc_ecc[i]);
1042                                 stat = stm32_fmc2_nfc_ham_correct(chip, dat,
1043                                                                   &read_ecc[i],
1044                                                                   &calc_ecc[i]);
1045                         }
1046                         ecc_sta++;
1047                 } else {
1048                         /*
1049                          * Ecc_sta[0] = FMC2_BCHDSR0
1050                          * Ecc_sta[1] = FMC2_BCHDSR1
1051                          * Ecc_sta[2] = FMC2_BCHDSR2
1052                          * Ecc_sta[3] = FMC2_BCHDSR3
1053                          * Ecc_sta[4] = FMC2_BCHDSR4
1054                          */
1055                         if (sta_map & BIT(s))
1056                                 stat = stm32_fmc2_nfc_bch_decode(eccsize, dat,
1057                                                                  ecc_sta);
1058                         ecc_sta += 5;
1059                 }
1060
1061                 if (stat == -EBADMSG)
1062                         /* Check for empty pages with bitflips */
1063                         stat = nand_check_erased_ecc_chunk(dat, eccsize,
1064                                                            &read_ecc[i],
1065                                                            eccbytes,
1066                                                            NULL, 0,
1067                                                            eccstrength);
1068
1069                 if (stat < 0) {
1070                         mtd->ecc_stats.failed++;
1071                 } else {
1072                         mtd->ecc_stats.corrected += stat;
1073                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1074                 }
1075         }
1076
1077         return max_bitflips;
1078 }
1079
1080 static int stm32_fmc2_nfc_seq_read_page(struct nand_chip *chip, u8 *buf,
1081                                         int oob_required, int page)
1082 {
1083         struct mtd_info *mtd = nand_to_mtd(chip);
1084         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1085         u8 *ecc_calc = chip->ecc.calc_buf;
1086         u8 *ecc_code = chip->ecc.code_buf;
1087         u16 sta_map;
1088         int ret;
1089
1090         ret = stm32_fmc2_nfc_select_chip(chip, chip->cur_cs);
1091         if (ret)
1092                 return ret;
1093
1094         /* Configure the sequencer */
1095         stm32_fmc2_nfc_rw_page_init(chip, page, 0, false);
1096
1097         /* Read the page */
1098         ret = stm32_fmc2_nfc_xfer(chip, buf, 0, false);
1099         if (ret)
1100                 return ret;
1101
1102         sta_map = stm32_fmc2_nfc_get_mapping_status(nfc);
1103
1104         /* Check if errors happen */
1105         if (likely(!sta_map)) {
1106                 if (oob_required)
1107                         return nand_change_read_column_op(chip, mtd->writesize,
1108                                                           chip->oob_poi,
1109                                                           mtd->oobsize, false);
1110
1111                 return 0;
1112         }
1113
1114         /* Read oob */
1115         ret = nand_change_read_column_op(chip, mtd->writesize,
1116                                          chip->oob_poi, mtd->oobsize, false);
1117         if (ret)
1118                 return ret;
1119
1120         ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
1121                                          chip->ecc.total);
1122         if (ret)
1123                 return ret;
1124
1125         /* Correct data */
1126         return chip->ecc.correct(chip, buf, ecc_code, ecc_calc);
1127 }
1128
1129 static int stm32_fmc2_nfc_seq_read_page_raw(struct nand_chip *chip, u8 *buf,
1130                                             int oob_required, int page)
1131 {
1132         struct mtd_info *mtd = nand_to_mtd(chip);
1133         int ret;
1134
1135         ret = stm32_fmc2_nfc_select_chip(chip, chip->cur_cs);
1136         if (ret)
1137                 return ret;
1138
1139         /* Configure the sequencer */
1140         stm32_fmc2_nfc_rw_page_init(chip, page, 1, false);
1141
1142         /* Read the page */
1143         ret = stm32_fmc2_nfc_xfer(chip, buf, 1, false);
1144         if (ret)
1145                 return ret;
1146
1147         /* Read oob */
1148         if (oob_required)
1149                 return nand_change_read_column_op(chip, mtd->writesize,
1150                                                   chip->oob_poi, mtd->oobsize,
1151                                                   false);
1152
1153         return 0;
1154 }
1155
1156 static irqreturn_t stm32_fmc2_nfc_irq(int irq, void *dev_id)
1157 {
1158         struct stm32_fmc2_nfc *nfc = (struct stm32_fmc2_nfc *)dev_id;
1159
1160         if (nfc->irq_state == FMC2_IRQ_SEQ)
1161                 /* Sequencer is used */
1162                 stm32_fmc2_nfc_disable_seq_irq(nfc);
1163         else if (nfc->irq_state == FMC2_IRQ_BCH)
1164                 /* BCH is used */
1165                 stm32_fmc2_nfc_disable_bch_irq(nfc);
1166
1167         complete(&nfc->complete);
1168
1169         return IRQ_HANDLED;
1170 }
1171
1172 static void stm32_fmc2_nfc_read_data(struct nand_chip *chip, void *buf,
1173                                      unsigned int len, bool force_8bit)
1174 {
1175         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1176         void __iomem *io_addr_r = nfc->data_base[nfc->cs_sel];
1177
1178         if (force_8bit && chip->options & NAND_BUSWIDTH_16)
1179                 /* Reconfigure bus width to 8-bit */
1180                 stm32_fmc2_nfc_set_buswidth_16(nfc, false);
1181
1182         if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32))) {
1183                 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u16)) && len) {
1184                         *(u8 *)buf = readb_relaxed(io_addr_r);
1185                         buf += sizeof(u8);
1186                         len -= sizeof(u8);
1187                 }
1188
1189                 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
1190                     len >= sizeof(u16)) {
1191                         *(u16 *)buf = readw_relaxed(io_addr_r);
1192                         buf += sizeof(u16);
1193                         len -= sizeof(u16);
1194                 }
1195         }
1196
1197         /* Buf is aligned */
1198         while (len >= sizeof(u32)) {
1199                 *(u32 *)buf = readl_relaxed(io_addr_r);
1200                 buf += sizeof(u32);
1201                 len -= sizeof(u32);
1202         }
1203
1204         /* Read remaining bytes */
1205         if (len >= sizeof(u16)) {
1206                 *(u16 *)buf = readw_relaxed(io_addr_r);
1207                 buf += sizeof(u16);
1208                 len -= sizeof(u16);
1209         }
1210
1211         if (len)
1212                 *(u8 *)buf = readb_relaxed(io_addr_r);
1213
1214         if (force_8bit && chip->options & NAND_BUSWIDTH_16)
1215                 /* Reconfigure bus width to 16-bit */
1216                 stm32_fmc2_nfc_set_buswidth_16(nfc, true);
1217 }
1218
1219 static void stm32_fmc2_nfc_write_data(struct nand_chip *chip, const void *buf,
1220                                       unsigned int len, bool force_8bit)
1221 {
1222         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1223         void __iomem *io_addr_w = nfc->data_base[nfc->cs_sel];
1224
1225         if (force_8bit && chip->options & NAND_BUSWIDTH_16)
1226                 /* Reconfigure bus width to 8-bit */
1227                 stm32_fmc2_nfc_set_buswidth_16(nfc, false);
1228
1229         if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32))) {
1230                 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u16)) && len) {
1231                         writeb_relaxed(*(u8 *)buf, io_addr_w);
1232                         buf += sizeof(u8);
1233                         len -= sizeof(u8);
1234                 }
1235
1236                 if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
1237                     len >= sizeof(u16)) {
1238                         writew_relaxed(*(u16 *)buf, io_addr_w);
1239                         buf += sizeof(u16);
1240                         len -= sizeof(u16);
1241                 }
1242         }
1243
1244         /* Buf is aligned */
1245         while (len >= sizeof(u32)) {
1246                 writel_relaxed(*(u32 *)buf, io_addr_w);
1247                 buf += sizeof(u32);
1248                 len -= sizeof(u32);
1249         }
1250
1251         /* Write remaining bytes */
1252         if (len >= sizeof(u16)) {
1253                 writew_relaxed(*(u16 *)buf, io_addr_w);
1254                 buf += sizeof(u16);
1255                 len -= sizeof(u16);
1256         }
1257
1258         if (len)
1259                 writeb_relaxed(*(u8 *)buf, io_addr_w);
1260
1261         if (force_8bit && chip->options & NAND_BUSWIDTH_16)
1262                 /* Reconfigure bus width to 16-bit */
1263                 stm32_fmc2_nfc_set_buswidth_16(nfc, true);
1264 }
1265
1266 static int stm32_fmc2_nfc_waitrdy(struct nand_chip *chip,
1267                                   unsigned long timeout_ms)
1268 {
1269         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1270         const struct nand_sdr_timings *timings;
1271         u32 isr, sr;
1272
1273         /* Check if there is no pending requests to the NAND flash */
1274         if (regmap_read_poll_timeout(nfc->regmap, FMC2_SR, sr,
1275                                      sr & FMC2_SR_NWRF, 1,
1276                                      1000 * FMC2_TIMEOUT_MS))
1277                 dev_warn(nfc->dev, "Waitrdy timeout\n");
1278
1279         /* Wait tWB before R/B# signal is low */
1280         timings = nand_get_sdr_timings(nand_get_interface_config(chip));
1281         ndelay(PSEC_TO_NSEC(timings->tWB_max));
1282
1283         /* R/B# signal is low, clear high level flag */
1284         regmap_write(nfc->regmap, FMC2_ICR, FMC2_ICR_CIHLF);
1285
1286         /* Wait R/B# signal is high */
1287         return regmap_read_poll_timeout(nfc->regmap, FMC2_ISR, isr,
1288                                         isr & FMC2_ISR_IHLF, 5,
1289                                         1000 * FMC2_TIMEOUT_MS);
1290 }
1291
1292 static int stm32_fmc2_nfc_exec_op(struct nand_chip *chip,
1293                                   const struct nand_operation *op,
1294                                   bool check_only)
1295 {
1296         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1297         const struct nand_op_instr *instr = NULL;
1298         unsigned int op_id, i, timeout;
1299         int ret;
1300
1301         if (check_only)
1302                 return 0;
1303
1304         ret = stm32_fmc2_nfc_select_chip(chip, op->cs);
1305         if (ret)
1306                 return ret;
1307
1308         for (op_id = 0; op_id < op->ninstrs; op_id++) {
1309                 instr = &op->instrs[op_id];
1310
1311                 switch (instr->type) {
1312                 case NAND_OP_CMD_INSTR:
1313                         writeb_relaxed(instr->ctx.cmd.opcode,
1314                                        nfc->cmd_base[nfc->cs_sel]);
1315                         break;
1316
1317                 case NAND_OP_ADDR_INSTR:
1318                         for (i = 0; i < instr->ctx.addr.naddrs; i++)
1319                                 writeb_relaxed(instr->ctx.addr.addrs[i],
1320                                                nfc->addr_base[nfc->cs_sel]);
1321                         break;
1322
1323                 case NAND_OP_DATA_IN_INSTR:
1324                         stm32_fmc2_nfc_read_data(chip, instr->ctx.data.buf.in,
1325                                                  instr->ctx.data.len,
1326                                                  instr->ctx.data.force_8bit);
1327                         break;
1328
1329                 case NAND_OP_DATA_OUT_INSTR:
1330                         stm32_fmc2_nfc_write_data(chip, instr->ctx.data.buf.out,
1331                                                   instr->ctx.data.len,
1332                                                   instr->ctx.data.force_8bit);
1333                         break;
1334
1335                 case NAND_OP_WAITRDY_INSTR:
1336                         timeout = instr->ctx.waitrdy.timeout_ms;
1337                         ret = stm32_fmc2_nfc_waitrdy(chip, timeout);
1338                         break;
1339                 }
1340         }
1341
1342         return ret;
1343 }
1344
1345 static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc *nfc)
1346 {
1347         u32 pcr;
1348
1349         regmap_read(nfc->regmap, FMC2_PCR, &pcr);
1350
1351         /* Set CS used to undefined */
1352         nfc->cs_sel = -1;
1353
1354         /* Enable wait feature and nand flash memory bank */
1355         pcr |= FMC2_PCR_PWAITEN;
1356         pcr |= FMC2_PCR_PBKEN;
1357
1358         /* Set buswidth to 8 bits mode for identification */
1359         pcr &= ~FMC2_PCR_PWID;
1360
1361         /* ECC logic is disabled */
1362         pcr &= ~FMC2_PCR_ECCEN;
1363
1364         /* Default mode */
1365         pcr &= ~FMC2_PCR_ECCALG;
1366         pcr &= ~FMC2_PCR_BCHECC;
1367         pcr &= ~FMC2_PCR_WEN;
1368
1369         /* Set default ECC sector size */
1370         pcr &= ~FMC2_PCR_ECCSS;
1371         pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_2048);
1372
1373         /* Set default tclr/tar timings */
1374         pcr &= ~FMC2_PCR_TCLR;
1375         pcr |= FIELD_PREP(FMC2_PCR_TCLR, FMC2_PCR_TCLR_DEFAULT);
1376         pcr &= ~FMC2_PCR_TAR;
1377         pcr |= FIELD_PREP(FMC2_PCR_TAR, FMC2_PCR_TAR_DEFAULT);
1378
1379         /* Enable FMC2 controller */
1380         if (nfc->dev == nfc->cdev)
1381                 regmap_update_bits(nfc->regmap, FMC2_BCR1,
1382                                    FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN);
1383
1384         regmap_write(nfc->regmap, FMC2_PCR, pcr);
1385         regmap_write(nfc->regmap, FMC2_PMEM, FMC2_PMEM_DEFAULT);
1386         regmap_write(nfc->regmap, FMC2_PATT, FMC2_PATT_DEFAULT);
1387 }
1388
1389 static void stm32_fmc2_nfc_calc_timings(struct nand_chip *chip,
1390                                         const struct nand_sdr_timings *sdrt)
1391 {
1392         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1393         struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
1394         struct stm32_fmc2_timings *tims = &nand->timings;
1395         unsigned long hclk = clk_get_rate(nfc->clk);
1396         unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000);
1397         unsigned long timing, tar, tclr, thiz, twait;
1398         unsigned long tset_mem, tset_att, thold_mem, thold_att;
1399
1400         tar = max_t(unsigned long, hclkp, sdrt->tAR_min);
1401         timing = DIV_ROUND_UP(tar, hclkp) - 1;
1402         tims->tar = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
1403
1404         tclr = max_t(unsigned long, hclkp, sdrt->tCLR_min);
1405         timing = DIV_ROUND_UP(tclr, hclkp) - 1;
1406         tims->tclr = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
1407
1408         tims->thiz = FMC2_THIZ;
1409         thiz = (tims->thiz + 1) * hclkp;
1410
1411         /*
1412          * tWAIT > tRP
1413          * tWAIT > tWP
1414          * tWAIT > tREA + tIO
1415          */
1416         twait = max_t(unsigned long, hclkp, sdrt->tRP_min);
1417         twait = max_t(unsigned long, twait, sdrt->tWP_min);
1418         twait = max_t(unsigned long, twait, sdrt->tREA_max + FMC2_TIO);
1419         timing = DIV_ROUND_UP(twait, hclkp);
1420         tims->twait = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
1421
1422         /*
1423          * tSETUP_MEM > tCS - tWAIT
1424          * tSETUP_MEM > tALS - tWAIT
1425          * tSETUP_MEM > tDS - (tWAIT - tHIZ)
1426          */
1427         tset_mem = hclkp;
1428         if (sdrt->tCS_min > twait && (tset_mem < sdrt->tCS_min - twait))
1429                 tset_mem = sdrt->tCS_min - twait;
1430         if (sdrt->tALS_min > twait && (tset_mem < sdrt->tALS_min - twait))
1431                 tset_mem = sdrt->tALS_min - twait;
1432         if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
1433             (tset_mem < sdrt->tDS_min - (twait - thiz)))
1434                 tset_mem = sdrt->tDS_min - (twait - thiz);
1435         timing = DIV_ROUND_UP(tset_mem, hclkp);
1436         tims->tset_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
1437
1438         /*
1439          * tHOLD_MEM > tCH
1440          * tHOLD_MEM > tREH - tSETUP_MEM
1441          * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT)
1442          */
1443         thold_mem = max_t(unsigned long, hclkp, sdrt->tCH_min);
1444         if (sdrt->tREH_min > tset_mem &&
1445             (thold_mem < sdrt->tREH_min - tset_mem))
1446                 thold_mem = sdrt->tREH_min - tset_mem;
1447         if ((sdrt->tRC_min > tset_mem + twait) &&
1448             (thold_mem < sdrt->tRC_min - (tset_mem + twait)))
1449                 thold_mem = sdrt->tRC_min - (tset_mem + twait);
1450         if ((sdrt->tWC_min > tset_mem + twait) &&
1451             (thold_mem < sdrt->tWC_min - (tset_mem + twait)))
1452                 thold_mem = sdrt->tWC_min - (tset_mem + twait);
1453         timing = DIV_ROUND_UP(thold_mem, hclkp);
1454         tims->thold_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
1455
1456         /*
1457          * tSETUP_ATT > tCS - tWAIT
1458          * tSETUP_ATT > tCLS - tWAIT
1459          * tSETUP_ATT > tALS - tWAIT
1460          * tSETUP_ATT > tRHW - tHOLD_MEM
1461          * tSETUP_ATT > tDS - (tWAIT - tHIZ)
1462          */
1463         tset_att = hclkp;
1464         if (sdrt->tCS_min > twait && (tset_att < sdrt->tCS_min - twait))
1465                 tset_att = sdrt->tCS_min - twait;
1466         if (sdrt->tCLS_min > twait && (tset_att < sdrt->tCLS_min - twait))
1467                 tset_att = sdrt->tCLS_min - twait;
1468         if (sdrt->tALS_min > twait && (tset_att < sdrt->tALS_min - twait))
1469                 tset_att = sdrt->tALS_min - twait;
1470         if (sdrt->tRHW_min > thold_mem &&
1471             (tset_att < sdrt->tRHW_min - thold_mem))
1472                 tset_att = sdrt->tRHW_min - thold_mem;
1473         if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
1474             (tset_att < sdrt->tDS_min - (twait - thiz)))
1475                 tset_att = sdrt->tDS_min - (twait - thiz);
1476         timing = DIV_ROUND_UP(tset_att, hclkp);
1477         tims->tset_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
1478
1479         /*
1480          * tHOLD_ATT > tALH
1481          * tHOLD_ATT > tCH
1482          * tHOLD_ATT > tCLH
1483          * tHOLD_ATT > tCOH
1484          * tHOLD_ATT > tDH
1485          * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM
1486          * tHOLD_ATT > tADL - tSETUP_MEM
1487          * tHOLD_ATT > tWH - tSETUP_MEM
1488          * tHOLD_ATT > tWHR - tSETUP_MEM
1489          * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT)
1490          * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT)
1491          */
1492         thold_att = max_t(unsigned long, hclkp, sdrt->tALH_min);
1493         thold_att = max_t(unsigned long, thold_att, sdrt->tCH_min);
1494         thold_att = max_t(unsigned long, thold_att, sdrt->tCLH_min);
1495         thold_att = max_t(unsigned long, thold_att, sdrt->tCOH_min);
1496         thold_att = max_t(unsigned long, thold_att, sdrt->tDH_min);
1497         if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) &&
1498             (thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem))
1499                 thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem;
1500         if (sdrt->tADL_min > tset_mem &&
1501             (thold_att < sdrt->tADL_min - tset_mem))
1502                 thold_att = sdrt->tADL_min - tset_mem;
1503         if (sdrt->tWH_min > tset_mem &&
1504             (thold_att < sdrt->tWH_min - tset_mem))
1505                 thold_att = sdrt->tWH_min - tset_mem;
1506         if (sdrt->tWHR_min > tset_mem &&
1507             (thold_att < sdrt->tWHR_min - tset_mem))
1508                 thold_att = sdrt->tWHR_min - tset_mem;
1509         if ((sdrt->tRC_min > tset_att + twait) &&
1510             (thold_att < sdrt->tRC_min - (tset_att + twait)))
1511                 thold_att = sdrt->tRC_min - (tset_att + twait);
1512         if ((sdrt->tWC_min > tset_att + twait) &&
1513             (thold_att < sdrt->tWC_min - (tset_att + twait)))
1514                 thold_att = sdrt->tWC_min - (tset_att + twait);
1515         timing = DIV_ROUND_UP(thold_att, hclkp);
1516         tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
1517 }
1518
1519 static int stm32_fmc2_nfc_setup_interface(struct nand_chip *chip, int chipnr,
1520                                           const struct nand_interface_config *conf)
1521 {
1522         const struct nand_sdr_timings *sdrt;
1523
1524         sdrt = nand_get_sdr_timings(conf);
1525         if (IS_ERR(sdrt))
1526                 return PTR_ERR(sdrt);
1527
1528         if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
1529                 return 0;
1530
1531         stm32_fmc2_nfc_calc_timings(chip, sdrt);
1532         stm32_fmc2_nfc_timings_init(chip);
1533
1534         return 0;
1535 }
1536
1537 static int stm32_fmc2_nfc_dma_setup(struct stm32_fmc2_nfc *nfc)
1538 {
1539         int ret = 0;
1540
1541         nfc->dma_tx_ch = dma_request_chan(nfc->dev, "tx");
1542         if (IS_ERR(nfc->dma_tx_ch)) {
1543                 ret = PTR_ERR(nfc->dma_tx_ch);
1544                 if (ret != -ENODEV && ret != -EPROBE_DEFER)
1545                         dev_err(nfc->dev,
1546                                 "failed to request tx DMA channel: %d\n", ret);
1547                 nfc->dma_tx_ch = NULL;
1548                 goto err_dma;
1549         }
1550
1551         nfc->dma_rx_ch = dma_request_chan(nfc->dev, "rx");
1552         if (IS_ERR(nfc->dma_rx_ch)) {
1553                 ret = PTR_ERR(nfc->dma_rx_ch);
1554                 if (ret != -ENODEV && ret != -EPROBE_DEFER)
1555                         dev_err(nfc->dev,
1556                                 "failed to request rx DMA channel: %d\n", ret);
1557                 nfc->dma_rx_ch = NULL;
1558                 goto err_dma;
1559         }
1560
1561         nfc->dma_ecc_ch = dma_request_chan(nfc->dev, "ecc");
1562         if (IS_ERR(nfc->dma_ecc_ch)) {
1563                 ret = PTR_ERR(nfc->dma_ecc_ch);
1564                 if (ret != -ENODEV && ret != -EPROBE_DEFER)
1565                         dev_err(nfc->dev,
1566                                 "failed to request ecc DMA channel: %d\n", ret);
1567                 nfc->dma_ecc_ch = NULL;
1568                 goto err_dma;
1569         }
1570
1571         ret = sg_alloc_table(&nfc->dma_ecc_sg, FMC2_MAX_SG, GFP_KERNEL);
1572         if (ret)
1573                 return ret;
1574
1575         /* Allocate a buffer to store ECC status registers */
1576         nfc->ecc_buf = devm_kzalloc(nfc->dev, FMC2_MAX_ECC_BUF_LEN, GFP_KERNEL);
1577         if (!nfc->ecc_buf)
1578                 return -ENOMEM;
1579
1580         ret = sg_alloc_table(&nfc->dma_data_sg, FMC2_MAX_SG, GFP_KERNEL);
1581         if (ret)
1582                 return ret;
1583
1584         init_completion(&nfc->dma_data_complete);
1585         init_completion(&nfc->dma_ecc_complete);
1586
1587         return 0;
1588
1589 err_dma:
1590         if (ret == -ENODEV) {
1591                 dev_warn(nfc->dev,
1592                          "DMAs not defined in the DT, polling mode is used\n");
1593                 ret = 0;
1594         }
1595
1596         return ret;
1597 }
1598
1599 static void stm32_fmc2_nfc_nand_callbacks_setup(struct nand_chip *chip)
1600 {
1601         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1602
1603         /*
1604          * Specific callbacks to read/write a page depending on
1605          * the mode (polling/sequencer) and the algo used (Hamming, BCH).
1606          */
1607         if (nfc->dma_tx_ch && nfc->dma_rx_ch && nfc->dma_ecc_ch) {
1608                 /* DMA => use sequencer mode callbacks */
1609                 chip->ecc.correct = stm32_fmc2_nfc_seq_correct;
1610                 chip->ecc.write_page = stm32_fmc2_nfc_seq_write_page;
1611                 chip->ecc.read_page = stm32_fmc2_nfc_seq_read_page;
1612                 chip->ecc.write_page_raw = stm32_fmc2_nfc_seq_write_page_raw;
1613                 chip->ecc.read_page_raw = stm32_fmc2_nfc_seq_read_page_raw;
1614         } else {
1615                 /* No DMA => use polling mode callbacks */
1616                 chip->ecc.hwctl = stm32_fmc2_nfc_hwctl;
1617                 if (chip->ecc.strength == FMC2_ECC_HAM) {
1618                         /* Hamming is used */
1619                         chip->ecc.calculate = stm32_fmc2_nfc_ham_calculate;
1620                         chip->ecc.correct = stm32_fmc2_nfc_ham_correct;
1621                         chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK;
1622                 } else {
1623                         /* BCH is used */
1624                         chip->ecc.calculate = stm32_fmc2_nfc_bch_calculate;
1625                         chip->ecc.correct = stm32_fmc2_nfc_bch_correct;
1626                         chip->ecc.read_page = stm32_fmc2_nfc_read_page;
1627                 }
1628         }
1629
1630         /* Specific configurations depending on the algo used */
1631         if (chip->ecc.strength == FMC2_ECC_HAM)
1632                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 4 : 3;
1633         else if (chip->ecc.strength == FMC2_ECC_BCH8)
1634                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 14 : 13;
1635         else
1636                 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7;
1637 }
1638
1639 static int stm32_fmc2_nfc_ooblayout_ecc(struct mtd_info *mtd, int section,
1640                                         struct mtd_oob_region *oobregion)
1641 {
1642         struct nand_chip *chip = mtd_to_nand(mtd);
1643         struct nand_ecc_ctrl *ecc = &chip->ecc;
1644
1645         if (section)
1646                 return -ERANGE;
1647
1648         oobregion->length = ecc->total;
1649         oobregion->offset = FMC2_BBM_LEN;
1650
1651         return 0;
1652 }
1653
1654 static int stm32_fmc2_nfc_ooblayout_free(struct mtd_info *mtd, int section,
1655                                          struct mtd_oob_region *oobregion)
1656 {
1657         struct nand_chip *chip = mtd_to_nand(mtd);
1658         struct nand_ecc_ctrl *ecc = &chip->ecc;
1659
1660         if (section)
1661                 return -ERANGE;
1662
1663         oobregion->length = mtd->oobsize - ecc->total - FMC2_BBM_LEN;
1664         oobregion->offset = ecc->total + FMC2_BBM_LEN;
1665
1666         return 0;
1667 }
1668
1669 static const struct mtd_ooblayout_ops stm32_fmc2_nfc_ooblayout_ops = {
1670         .ecc = stm32_fmc2_nfc_ooblayout_ecc,
1671         .free = stm32_fmc2_nfc_ooblayout_free,
1672 };
1673
1674 static int stm32_fmc2_nfc_calc_ecc_bytes(int step_size, int strength)
1675 {
1676         /* Hamming */
1677         if (strength == FMC2_ECC_HAM)
1678                 return 4;
1679
1680         /* BCH8 */
1681         if (strength == FMC2_ECC_BCH8)
1682                 return 14;
1683
1684         /* BCH4 */
1685         return 8;
1686 }
1687
1688 NAND_ECC_CAPS_SINGLE(stm32_fmc2_nfc_ecc_caps, stm32_fmc2_nfc_calc_ecc_bytes,
1689                      FMC2_ECC_STEP_SIZE,
1690                      FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8);
1691
1692 static int stm32_fmc2_nfc_attach_chip(struct nand_chip *chip)
1693 {
1694         struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
1695         struct mtd_info *mtd = nand_to_mtd(chip);
1696         int ret;
1697
1698         /*
1699          * Only NAND_ECC_ENGINE_TYPE_ON_HOST mode is actually supported
1700          * Hamming => ecc.strength = 1
1701          * BCH4 => ecc.strength = 4
1702          * BCH8 => ecc.strength = 8
1703          * ECC sector size = 512
1704          */
1705         if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) {
1706                 dev_err(nfc->dev,
1707                         "nand_ecc_engine_type is not well defined in the DT\n");
1708                 return -EINVAL;
1709         }
1710
1711         ret = nand_ecc_choose_conf(chip, &stm32_fmc2_nfc_ecc_caps,
1712                                    mtd->oobsize - FMC2_BBM_LEN);
1713         if (ret) {
1714                 dev_err(nfc->dev, "no valid ECC settings set\n");
1715                 return ret;
1716         }
1717
1718         if (mtd->writesize / chip->ecc.size > FMC2_MAX_SG) {
1719                 dev_err(nfc->dev, "nand page size is not supported\n");
1720                 return -EINVAL;
1721         }
1722
1723         if (chip->bbt_options & NAND_BBT_USE_FLASH)
1724                 chip->bbt_options |= NAND_BBT_NO_OOB;
1725
1726         stm32_fmc2_nfc_nand_callbacks_setup(chip);
1727
1728         mtd_set_ooblayout(mtd, &stm32_fmc2_nfc_ooblayout_ops);
1729
1730         if (chip->options & NAND_BUSWIDTH_16)
1731                 stm32_fmc2_nfc_set_buswidth_16(nfc, true);
1732
1733         return 0;
1734 }
1735
1736 static const struct nand_controller_ops stm32_fmc2_nfc_controller_ops = {
1737         .attach_chip = stm32_fmc2_nfc_attach_chip,
1738         .exec_op = stm32_fmc2_nfc_exec_op,
1739         .setup_interface = stm32_fmc2_nfc_setup_interface,
1740 };
1741
1742 static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc,
1743                                       struct device_node *dn)
1744 {
1745         struct stm32_fmc2_nand *nand = &nfc->nand;
1746         u32 cs;
1747         int ret, i;
1748
1749         if (!of_get_property(dn, "reg", &nand->ncs))
1750                 return -EINVAL;
1751
1752         nand->ncs /= sizeof(u32);
1753         if (!nand->ncs) {
1754                 dev_err(nfc->dev, "invalid reg property size\n");
1755                 return -EINVAL;
1756         }
1757
1758         for (i = 0; i < nand->ncs; i++) {
1759                 ret = of_property_read_u32_index(dn, "reg", i, &cs);
1760                 if (ret) {
1761                         dev_err(nfc->dev, "could not retrieve reg property: %d\n",
1762                                 ret);
1763                         return ret;
1764                 }
1765
1766                 if (cs >= FMC2_MAX_CE) {
1767                         dev_err(nfc->dev, "invalid reg value: %d\n", cs);
1768                         return -EINVAL;
1769                 }
1770
1771                 if (nfc->cs_assigned & BIT(cs)) {
1772                         dev_err(nfc->dev, "cs already assigned: %d\n", cs);
1773                         return -EINVAL;
1774                 }
1775
1776                 nfc->cs_assigned |= BIT(cs);
1777                 nand->cs_used[i] = cs;
1778         }
1779
1780         nand_set_flash_node(&nand->chip, dn);
1781
1782         return 0;
1783 }
1784
1785 static int stm32_fmc2_nfc_parse_dt(struct stm32_fmc2_nfc *nfc)
1786 {
1787         struct device_node *dn = nfc->dev->of_node;
1788         struct device_node *child;
1789         int nchips = of_get_child_count(dn);
1790         int ret = 0;
1791
1792         if (!nchips) {
1793                 dev_err(nfc->dev, "NAND chip not defined\n");
1794                 return -EINVAL;
1795         }
1796
1797         if (nchips > 1) {
1798                 dev_err(nfc->dev, "too many NAND chips defined\n");
1799                 return -EINVAL;
1800         }
1801
1802         for_each_child_of_node(dn, child) {
1803                 ret = stm32_fmc2_nfc_parse_child(nfc, child);
1804                 if (ret < 0) {
1805                         of_node_put(child);
1806                         return ret;
1807                 }
1808         }
1809
1810         return ret;
1811 }
1812
1813 static int stm32_fmc2_nfc_set_cdev(struct stm32_fmc2_nfc *nfc)
1814 {
1815         struct device *dev = nfc->dev;
1816         bool ebi_found = false;
1817
1818         if (dev->parent && of_device_is_compatible(dev->parent->of_node,
1819                                                    "st,stm32mp1-fmc2-ebi"))
1820                 ebi_found = true;
1821
1822         if (of_device_is_compatible(dev->of_node, "st,stm32mp1-fmc2-nfc")) {
1823                 if (ebi_found) {
1824                         nfc->cdev = dev->parent;
1825
1826                         return 0;
1827                 }
1828
1829                 return -EINVAL;
1830         }
1831
1832         if (ebi_found)
1833                 return -EINVAL;
1834
1835         nfc->cdev = dev;
1836
1837         return 0;
1838 }
1839
1840 static int stm32_fmc2_nfc_probe(struct platform_device *pdev)
1841 {
1842         struct device *dev = &pdev->dev;
1843         struct reset_control *rstc;
1844         struct stm32_fmc2_nfc *nfc;
1845         struct stm32_fmc2_nand *nand;
1846         struct resource *res;
1847         struct mtd_info *mtd;
1848         struct nand_chip *chip;
1849         struct resource cres;
1850         int chip_cs, mem_region, ret, irq;
1851         int start_region = 0;
1852
1853         nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1854         if (!nfc)
1855                 return -ENOMEM;
1856
1857         nfc->dev = dev;
1858         nand_controller_init(&nfc->base);
1859         nfc->base.ops = &stm32_fmc2_nfc_controller_ops;
1860
1861         ret = stm32_fmc2_nfc_set_cdev(nfc);
1862         if (ret)
1863                 return ret;
1864
1865         ret = stm32_fmc2_nfc_parse_dt(nfc);
1866         if (ret)
1867                 return ret;
1868
1869         ret = of_address_to_resource(nfc->cdev->of_node, 0, &cres);
1870         if (ret)
1871                 return ret;
1872
1873         nfc->io_phys_addr = cres.start;
1874
1875         nfc->regmap = device_node_to_regmap(nfc->cdev->of_node);
1876         if (IS_ERR(nfc->regmap))
1877                 return PTR_ERR(nfc->regmap);
1878
1879         if (nfc->dev == nfc->cdev)
1880                 start_region = 1;
1881
1882         for (chip_cs = 0, mem_region = start_region; chip_cs < FMC2_MAX_CE;
1883              chip_cs++, mem_region += 3) {
1884                 if (!(nfc->cs_assigned & BIT(chip_cs)))
1885                         continue;
1886
1887                 res = platform_get_resource(pdev, IORESOURCE_MEM, mem_region);
1888                 nfc->data_base[chip_cs] = devm_ioremap_resource(dev, res);
1889                 if (IS_ERR(nfc->data_base[chip_cs]))
1890                         return PTR_ERR(nfc->data_base[chip_cs]);
1891
1892                 nfc->data_phys_addr[chip_cs] = res->start;
1893
1894                 res = platform_get_resource(pdev, IORESOURCE_MEM,
1895                                             mem_region + 1);
1896                 nfc->cmd_base[chip_cs] = devm_ioremap_resource(dev, res);
1897                 if (IS_ERR(nfc->cmd_base[chip_cs]))
1898                         return PTR_ERR(nfc->cmd_base[chip_cs]);
1899
1900                 res = platform_get_resource(pdev, IORESOURCE_MEM,
1901                                             mem_region + 2);
1902                 nfc->addr_base[chip_cs] = devm_ioremap_resource(dev, res);
1903                 if (IS_ERR(nfc->addr_base[chip_cs]))
1904                         return PTR_ERR(nfc->addr_base[chip_cs]);
1905         }
1906
1907         irq = platform_get_irq(pdev, 0);
1908         if (irq < 0)
1909                 return irq;
1910
1911         ret = devm_request_irq(dev, irq, stm32_fmc2_nfc_irq, 0,
1912                                dev_name(dev), nfc);
1913         if (ret) {
1914                 dev_err(dev, "failed to request irq\n");
1915                 return ret;
1916         }
1917
1918         init_completion(&nfc->complete);
1919
1920         nfc->clk = devm_clk_get(nfc->cdev, NULL);
1921         if (IS_ERR(nfc->clk))
1922                 return PTR_ERR(nfc->clk);
1923
1924         ret = clk_prepare_enable(nfc->clk);
1925         if (ret) {
1926                 dev_err(dev, "can not enable the clock\n");
1927                 return ret;
1928         }
1929
1930         rstc = devm_reset_control_get(dev, NULL);
1931         if (IS_ERR(rstc)) {
1932                 ret = PTR_ERR(rstc);
1933                 if (ret == -EPROBE_DEFER)
1934                         goto err_clk_disable;
1935         } else {
1936                 reset_control_assert(rstc);
1937                 reset_control_deassert(rstc);
1938         }
1939
1940         ret = stm32_fmc2_nfc_dma_setup(nfc);
1941         if (ret)
1942                 goto err_release_dma;
1943
1944         stm32_fmc2_nfc_init(nfc);
1945
1946         nand = &nfc->nand;
1947         chip = &nand->chip;
1948         mtd = nand_to_mtd(chip);
1949         mtd->dev.parent = dev;
1950
1951         chip->controller = &nfc->base;
1952         chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
1953                          NAND_USES_DMA;
1954
1955         /* Default ECC settings */
1956         chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
1957         chip->ecc.size = FMC2_ECC_STEP_SIZE;
1958         chip->ecc.strength = FMC2_ECC_BCH8;
1959
1960         /* Scan to find existence of the device */
1961         ret = nand_scan(chip, nand->ncs);
1962         if (ret)
1963                 goto err_release_dma;
1964
1965         ret = mtd_device_register(mtd, NULL, 0);
1966         if (ret)
1967                 goto err_nand_cleanup;
1968
1969         platform_set_drvdata(pdev, nfc);
1970
1971         return 0;
1972
1973 err_nand_cleanup:
1974         nand_cleanup(chip);
1975
1976 err_release_dma:
1977         if (nfc->dma_ecc_ch)
1978                 dma_release_channel(nfc->dma_ecc_ch);
1979         if (nfc->dma_tx_ch)
1980                 dma_release_channel(nfc->dma_tx_ch);
1981         if (nfc->dma_rx_ch)
1982                 dma_release_channel(nfc->dma_rx_ch);
1983
1984         sg_free_table(&nfc->dma_data_sg);
1985         sg_free_table(&nfc->dma_ecc_sg);
1986
1987 err_clk_disable:
1988         clk_disable_unprepare(nfc->clk);
1989
1990         return ret;
1991 }
1992
1993 static int stm32_fmc2_nfc_remove(struct platform_device *pdev)
1994 {
1995         struct stm32_fmc2_nfc *nfc = platform_get_drvdata(pdev);
1996         struct stm32_fmc2_nand *nand = &nfc->nand;
1997         struct nand_chip *chip = &nand->chip;
1998         int ret;
1999
2000         ret = mtd_device_unregister(nand_to_mtd(chip));
2001         WARN_ON(ret);
2002         nand_cleanup(chip);
2003
2004         if (nfc->dma_ecc_ch)
2005                 dma_release_channel(nfc->dma_ecc_ch);
2006         if (nfc->dma_tx_ch)
2007                 dma_release_channel(nfc->dma_tx_ch);
2008         if (nfc->dma_rx_ch)
2009                 dma_release_channel(nfc->dma_rx_ch);
2010
2011         sg_free_table(&nfc->dma_data_sg);
2012         sg_free_table(&nfc->dma_ecc_sg);
2013
2014         clk_disable_unprepare(nfc->clk);
2015
2016         return 0;
2017 }
2018
2019 static int __maybe_unused stm32_fmc2_nfc_suspend(struct device *dev)
2020 {
2021         struct stm32_fmc2_nfc *nfc = dev_get_drvdata(dev);
2022
2023         clk_disable_unprepare(nfc->clk);
2024
2025         pinctrl_pm_select_sleep_state(dev);
2026
2027         return 0;
2028 }
2029
2030 static int __maybe_unused stm32_fmc2_nfc_resume(struct device *dev)
2031 {
2032         struct stm32_fmc2_nfc *nfc = dev_get_drvdata(dev);
2033         struct stm32_fmc2_nand *nand = &nfc->nand;
2034         int chip_cs, ret;
2035
2036         pinctrl_pm_select_default_state(dev);
2037
2038         ret = clk_prepare_enable(nfc->clk);
2039         if (ret) {
2040                 dev_err(dev, "can not enable the clock\n");
2041                 return ret;
2042         }
2043
2044         stm32_fmc2_nfc_init(nfc);
2045
2046         for (chip_cs = 0; chip_cs < FMC2_MAX_CE; chip_cs++) {
2047                 if (!(nfc->cs_assigned & BIT(chip_cs)))
2048                         continue;
2049
2050                 nand_reset(&nand->chip, chip_cs);
2051         }
2052
2053         return 0;
2054 }
2055
2056 static SIMPLE_DEV_PM_OPS(stm32_fmc2_nfc_pm_ops, stm32_fmc2_nfc_suspend,
2057                          stm32_fmc2_nfc_resume);
2058
2059 static const struct of_device_id stm32_fmc2_nfc_match[] = {
2060         {.compatible = "st,stm32mp15-fmc2"},
2061         {.compatible = "st,stm32mp1-fmc2-nfc"},
2062         {}
2063 };
2064 MODULE_DEVICE_TABLE(of, stm32_fmc2_nfc_match);
2065
2066 static struct platform_driver stm32_fmc2_nfc_driver = {
2067         .probe  = stm32_fmc2_nfc_probe,
2068         .remove = stm32_fmc2_nfc_remove,
2069         .driver = {
2070                 .name = "stm32_fmc2_nfc",
2071                 .of_match_table = stm32_fmc2_nfc_match,
2072                 .pm = &stm32_fmc2_nfc_pm_ops,
2073         },
2074 };
2075 module_platform_driver(stm32_fmc2_nfc_driver);
2076
2077 MODULE_ALIAS("platform:stm32_fmc2_nfc");
2078 MODULE_AUTHOR("Christophe Kerello <christophe.kerello@st.com>");
2079 MODULE_DESCRIPTION("STMicroelectronics STM32 FMC2 NFC driver");
2080 MODULE_LICENSE("GPL v2");